1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009-2012 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE_V0 4 110 #define LPFC_MAX_WQ_PAGE 8 111 #define LPFC_MAX_CQ_PAGE 4 112 #define LPFC_MAX_EQ_PAGE 8 113 114 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 115 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 116 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 117 118 /* Define SLI4 Alignment requirements. */ 119 #define LPFC_ALIGN_16_BYTE 16 120 #define LPFC_ALIGN_64_BYTE 64 121 122 /* Define SLI4 specific definitions. */ 123 #define LPFC_MQ_CQE_BYTE_OFFSET 256 124 #define LPFC_MBX_CMD_HDR_LENGTH 16 125 #define LPFC_MBX_ERROR_RANGE 0x4000 126 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 127 #define LPFC_BMBX_BIT1_ADDR_LO 0 128 #define LPFC_RPI_HDR_COUNT 64 129 #define LPFC_HDR_TEMPLATE_SIZE 4096 130 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 131 #define LPFC_FCF_RECORD_WD_CNT 132 132 #define LPFC_ENTIRE_FCF_DATABASE 0 133 #define LPFC_DFLT_FCF_INDEX 0 134 135 /* Virtual function numbers */ 136 #define LPFC_VF0 0 137 #define LPFC_VF1 1 138 #define LPFC_VF2 2 139 #define LPFC_VF3 3 140 #define LPFC_VF4 4 141 #define LPFC_VF5 5 142 #define LPFC_VF6 6 143 #define LPFC_VF7 7 144 #define LPFC_VF8 8 145 #define LPFC_VF9 9 146 #define LPFC_VF10 10 147 #define LPFC_VF11 11 148 #define LPFC_VF12 12 149 #define LPFC_VF13 13 150 #define LPFC_VF14 14 151 #define LPFC_VF15 15 152 #define LPFC_VF16 16 153 #define LPFC_VF17 17 154 #define LPFC_VF18 18 155 #define LPFC_VF19 19 156 #define LPFC_VF20 20 157 #define LPFC_VF21 21 158 #define LPFC_VF22 22 159 #define LPFC_VF23 23 160 #define LPFC_VF24 24 161 #define LPFC_VF25 25 162 #define LPFC_VF26 26 163 #define LPFC_VF27 27 164 #define LPFC_VF28 28 165 #define LPFC_VF29 29 166 #define LPFC_VF30 30 167 #define LPFC_VF31 31 168 169 /* PCI function numbers */ 170 #define LPFC_PCI_FUNC0 0 171 #define LPFC_PCI_FUNC1 1 172 #define LPFC_PCI_FUNC2 2 173 #define LPFC_PCI_FUNC3 3 174 #define LPFC_PCI_FUNC4 4 175 176 /* SLI4 interface type-2 PDEV_CTL register */ 177 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 178 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 179 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 180 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 181 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 182 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 183 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 184 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 185 186 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 187 188 /* Active interrupt test count */ 189 #define LPFC_ACT_INTR_CNT 4 190 191 /* Algrithmns for scheduling FCP commands to WQs */ 192 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 193 #define LPFC_FCP_SCHED_BY_CPU 1 194 195 /* Delay Multiplier constant */ 196 #define LPFC_DMULT_CONST 651042 197 198 /* Configuration of Interrupts / sec for entire HBA port */ 199 #define LPFC_MIN_IMAX 5000 200 #define LPFC_MAX_IMAX 5000000 201 #define LPFC_DEF_IMAX 50000 202 203 #define LPFC_MIN_CPU_MAP 0 204 #define LPFC_MAX_CPU_MAP 2 205 #define LPFC_HBA_CPU_MAP 1 206 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 207 208 /* PORT_CAPABILITIES constants. */ 209 #define LPFC_MAX_SUPPORTED_PAGES 8 210 211 struct ulp_bde64 { 212 union ULP_BDE_TUS { 213 uint32_t w; 214 struct { 215 #ifdef __BIG_ENDIAN_BITFIELD 216 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 217 VALUE !! */ 218 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 219 #else /* __LITTLE_ENDIAN_BITFIELD */ 220 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 222 VALUE !! */ 223 #endif 224 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 225 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 226 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 227 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 228 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 229 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 230 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 231 } f; 232 } tus; 233 uint32_t addrLow; 234 uint32_t addrHigh; 235 }; 236 237 struct lpfc_sli4_flags { 238 uint32_t word0; 239 #define lpfc_idx_rsrc_rdy_SHIFT 0 240 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 241 #define lpfc_idx_rsrc_rdy_WORD word0 242 #define LPFC_IDX_RSRC_RDY 1 243 #define lpfc_rpi_rsrc_rdy_SHIFT 1 244 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 245 #define lpfc_rpi_rsrc_rdy_WORD word0 246 #define LPFC_RPI_RSRC_RDY 1 247 #define lpfc_vpi_rsrc_rdy_SHIFT 2 248 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 249 #define lpfc_vpi_rsrc_rdy_WORD word0 250 #define LPFC_VPI_RSRC_RDY 1 251 #define lpfc_vfi_rsrc_rdy_SHIFT 3 252 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 253 #define lpfc_vfi_rsrc_rdy_WORD word0 254 #define LPFC_VFI_RSRC_RDY 1 255 }; 256 257 struct sli4_bls_rsp { 258 uint32_t word0_rsvd; /* Word0 must be reserved */ 259 uint32_t word1; 260 #define lpfc_abts_orig_SHIFT 0 261 #define lpfc_abts_orig_MASK 0x00000001 262 #define lpfc_abts_orig_WORD word1 263 #define LPFC_ABTS_UNSOL_RSP 1 264 #define LPFC_ABTS_UNSOL_INT 0 265 uint32_t word2; 266 #define lpfc_abts_rxid_SHIFT 0 267 #define lpfc_abts_rxid_MASK 0x0000FFFF 268 #define lpfc_abts_rxid_WORD word2 269 #define lpfc_abts_oxid_SHIFT 16 270 #define lpfc_abts_oxid_MASK 0x0000FFFF 271 #define lpfc_abts_oxid_WORD word2 272 uint32_t word3; 273 #define lpfc_vndr_code_SHIFT 0 274 #define lpfc_vndr_code_MASK 0x000000FF 275 #define lpfc_vndr_code_WORD word3 276 #define lpfc_rsn_expln_SHIFT 8 277 #define lpfc_rsn_expln_MASK 0x000000FF 278 #define lpfc_rsn_expln_WORD word3 279 #define lpfc_rsn_code_SHIFT 16 280 #define lpfc_rsn_code_MASK 0x000000FF 281 #define lpfc_rsn_code_WORD word3 282 283 uint32_t word4; 284 uint32_t word5_rsvd; /* Word5 must be reserved */ 285 }; 286 287 /* event queue entry structure */ 288 struct lpfc_eqe { 289 uint32_t word0; 290 #define lpfc_eqe_resource_id_SHIFT 16 291 #define lpfc_eqe_resource_id_MASK 0x000000FF 292 #define lpfc_eqe_resource_id_WORD word0 293 #define lpfc_eqe_minor_code_SHIFT 4 294 #define lpfc_eqe_minor_code_MASK 0x00000FFF 295 #define lpfc_eqe_minor_code_WORD word0 296 #define lpfc_eqe_major_code_SHIFT 1 297 #define lpfc_eqe_major_code_MASK 0x00000007 298 #define lpfc_eqe_major_code_WORD word0 299 #define lpfc_eqe_valid_SHIFT 0 300 #define lpfc_eqe_valid_MASK 0x00000001 301 #define lpfc_eqe_valid_WORD word0 302 }; 303 304 /* completion queue entry structure (common fields for all cqe types) */ 305 struct lpfc_cqe { 306 uint32_t reserved0; 307 uint32_t reserved1; 308 uint32_t reserved2; 309 uint32_t word3; 310 #define lpfc_cqe_valid_SHIFT 31 311 #define lpfc_cqe_valid_MASK 0x00000001 312 #define lpfc_cqe_valid_WORD word3 313 #define lpfc_cqe_code_SHIFT 16 314 #define lpfc_cqe_code_MASK 0x000000FF 315 #define lpfc_cqe_code_WORD word3 316 }; 317 318 /* Completion Queue Entry Status Codes */ 319 #define CQE_STATUS_SUCCESS 0x0 320 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 321 #define CQE_STATUS_REMOTE_STOP 0x2 322 #define CQE_STATUS_LOCAL_REJECT 0x3 323 #define CQE_STATUS_NPORT_RJT 0x4 324 #define CQE_STATUS_FABRIC_RJT 0x5 325 #define CQE_STATUS_NPORT_BSY 0x6 326 #define CQE_STATUS_FABRIC_BSY 0x7 327 #define CQE_STATUS_INTERMED_RSP 0x8 328 #define CQE_STATUS_LS_RJT 0x9 329 #define CQE_STATUS_CMD_REJECT 0xb 330 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 331 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 332 #define CQE_STATUS_DI_ERROR 0x16 333 334 /* Used when mapping CQE status to IOCB */ 335 #define LPFC_IOCB_STATUS_MASK 0xf 336 337 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 338 #define CQE_HW_STATUS_NO_ERR 0x0 339 #define CQE_HW_STATUS_UNDERRUN 0x1 340 #define CQE_HW_STATUS_OVERRUN 0x2 341 342 /* Completion Queue Entry Codes */ 343 #define CQE_CODE_COMPL_WQE 0x1 344 #define CQE_CODE_RELEASE_WQE 0x2 345 #define CQE_CODE_RECEIVE 0x4 346 #define CQE_CODE_XRI_ABORTED 0x5 347 #define CQE_CODE_RECEIVE_V1 0x9 348 349 /* 350 * Define mask value for xri_aborted and wcqe completed CQE extended status. 351 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 352 */ 353 #define WCQE_PARAM_MASK 0x1FF 354 355 /* completion queue entry for wqe completions */ 356 struct lpfc_wcqe_complete { 357 uint32_t word0; 358 #define lpfc_wcqe_c_request_tag_SHIFT 16 359 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 360 #define lpfc_wcqe_c_request_tag_WORD word0 361 #define lpfc_wcqe_c_status_SHIFT 8 362 #define lpfc_wcqe_c_status_MASK 0x000000FF 363 #define lpfc_wcqe_c_status_WORD word0 364 #define lpfc_wcqe_c_hw_status_SHIFT 0 365 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 366 #define lpfc_wcqe_c_hw_status_WORD word0 367 uint32_t total_data_placed; 368 uint32_t parameter; 369 #define lpfc_wcqe_c_bg_edir_SHIFT 5 370 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 371 #define lpfc_wcqe_c_bg_edir_WORD parameter 372 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 373 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 374 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 375 #define lpfc_wcqe_c_bg_re_SHIFT 2 376 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 377 #define lpfc_wcqe_c_bg_re_WORD parameter 378 #define lpfc_wcqe_c_bg_ae_SHIFT 1 379 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 380 #define lpfc_wcqe_c_bg_ae_WORD parameter 381 #define lpfc_wcqe_c_bg_ge_SHIFT 0 382 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 383 #define lpfc_wcqe_c_bg_ge_WORD parameter 384 uint32_t word3; 385 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 386 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 387 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 388 #define lpfc_wcqe_c_xb_SHIFT 28 389 #define lpfc_wcqe_c_xb_MASK 0x00000001 390 #define lpfc_wcqe_c_xb_WORD word3 391 #define lpfc_wcqe_c_pv_SHIFT 27 392 #define lpfc_wcqe_c_pv_MASK 0x00000001 393 #define lpfc_wcqe_c_pv_WORD word3 394 #define lpfc_wcqe_c_priority_SHIFT 24 395 #define lpfc_wcqe_c_priority_MASK 0x00000007 396 #define lpfc_wcqe_c_priority_WORD word3 397 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 398 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 399 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 400 }; 401 402 /* completion queue entry for wqe release */ 403 struct lpfc_wcqe_release { 404 uint32_t reserved0; 405 uint32_t reserved1; 406 uint32_t word2; 407 #define lpfc_wcqe_r_wq_id_SHIFT 16 408 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 409 #define lpfc_wcqe_r_wq_id_WORD word2 410 #define lpfc_wcqe_r_wqe_index_SHIFT 0 411 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 412 #define lpfc_wcqe_r_wqe_index_WORD word2 413 uint32_t word3; 414 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 415 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 416 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 417 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 418 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 419 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 420 }; 421 422 struct sli4_wcqe_xri_aborted { 423 uint32_t word0; 424 #define lpfc_wcqe_xa_status_SHIFT 8 425 #define lpfc_wcqe_xa_status_MASK 0x000000FF 426 #define lpfc_wcqe_xa_status_WORD word0 427 uint32_t parameter; 428 uint32_t word2; 429 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 430 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 431 #define lpfc_wcqe_xa_remote_xid_WORD word2 432 #define lpfc_wcqe_xa_xri_SHIFT 0 433 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 434 #define lpfc_wcqe_xa_xri_WORD word2 435 uint32_t word3; 436 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 437 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 438 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 439 #define lpfc_wcqe_xa_ia_SHIFT 30 440 #define lpfc_wcqe_xa_ia_MASK 0x00000001 441 #define lpfc_wcqe_xa_ia_WORD word3 442 #define CQE_XRI_ABORTED_IA_REMOTE 0 443 #define CQE_XRI_ABORTED_IA_LOCAL 1 444 #define lpfc_wcqe_xa_br_SHIFT 29 445 #define lpfc_wcqe_xa_br_MASK 0x00000001 446 #define lpfc_wcqe_xa_br_WORD word3 447 #define CQE_XRI_ABORTED_BR_BA_ACC 0 448 #define CQE_XRI_ABORTED_BR_BA_RJT 1 449 #define lpfc_wcqe_xa_eo_SHIFT 28 450 #define lpfc_wcqe_xa_eo_MASK 0x00000001 451 #define lpfc_wcqe_xa_eo_WORD word3 452 #define CQE_XRI_ABORTED_EO_REMOTE 0 453 #define CQE_XRI_ABORTED_EO_LOCAL 1 454 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 455 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 456 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 457 }; 458 459 /* completion queue entry structure for rqe completion */ 460 struct lpfc_rcqe { 461 uint32_t word0; 462 #define lpfc_rcqe_bindex_SHIFT 16 463 #define lpfc_rcqe_bindex_MASK 0x0000FFF 464 #define lpfc_rcqe_bindex_WORD word0 465 #define lpfc_rcqe_status_SHIFT 8 466 #define lpfc_rcqe_status_MASK 0x000000FF 467 #define lpfc_rcqe_status_WORD word0 468 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 469 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 470 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 471 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 472 uint32_t word1; 473 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 474 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 475 #define lpfc_rcqe_fcf_id_v1_WORD word1 476 uint32_t word2; 477 #define lpfc_rcqe_length_SHIFT 16 478 #define lpfc_rcqe_length_MASK 0x0000FFFF 479 #define lpfc_rcqe_length_WORD word2 480 #define lpfc_rcqe_rq_id_SHIFT 6 481 #define lpfc_rcqe_rq_id_MASK 0x000003FF 482 #define lpfc_rcqe_rq_id_WORD word2 483 #define lpfc_rcqe_fcf_id_SHIFT 0 484 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 485 #define lpfc_rcqe_fcf_id_WORD word2 486 #define lpfc_rcqe_rq_id_v1_SHIFT 0 487 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 488 #define lpfc_rcqe_rq_id_v1_WORD word2 489 uint32_t word3; 490 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 491 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 492 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 493 #define lpfc_rcqe_port_SHIFT 30 494 #define lpfc_rcqe_port_MASK 0x00000001 495 #define lpfc_rcqe_port_WORD word3 496 #define lpfc_rcqe_hdr_length_SHIFT 24 497 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 498 #define lpfc_rcqe_hdr_length_WORD word3 499 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 500 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 501 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 502 #define lpfc_rcqe_eof_SHIFT 8 503 #define lpfc_rcqe_eof_MASK 0x000000FF 504 #define lpfc_rcqe_eof_WORD word3 505 #define FCOE_EOFn 0x41 506 #define FCOE_EOFt 0x42 507 #define FCOE_EOFni 0x49 508 #define FCOE_EOFa 0x50 509 #define lpfc_rcqe_sof_SHIFT 0 510 #define lpfc_rcqe_sof_MASK 0x000000FF 511 #define lpfc_rcqe_sof_WORD word3 512 #define FCOE_SOFi2 0x2d 513 #define FCOE_SOFi3 0x2e 514 #define FCOE_SOFn2 0x35 515 #define FCOE_SOFn3 0x36 516 }; 517 518 struct lpfc_rqe { 519 uint32_t address_hi; 520 uint32_t address_lo; 521 }; 522 523 /* buffer descriptors */ 524 struct lpfc_bde4 { 525 uint32_t addr_hi; 526 uint32_t addr_lo; 527 uint32_t word2; 528 #define lpfc_bde4_last_SHIFT 31 529 #define lpfc_bde4_last_MASK 0x00000001 530 #define lpfc_bde4_last_WORD word2 531 #define lpfc_bde4_sge_offset_SHIFT 0 532 #define lpfc_bde4_sge_offset_MASK 0x000003FF 533 #define lpfc_bde4_sge_offset_WORD word2 534 uint32_t word3; 535 #define lpfc_bde4_length_SHIFT 0 536 #define lpfc_bde4_length_MASK 0x000000FF 537 #define lpfc_bde4_length_WORD word3 538 }; 539 540 struct lpfc_register { 541 uint32_t word0; 542 }; 543 544 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 545 #define LPFC_UERR_STATUS_HI 0x00A4 546 #define LPFC_UERR_STATUS_LO 0x00A0 547 #define LPFC_UE_MASK_HI 0x00AC 548 #define LPFC_UE_MASK_LO 0x00A8 549 550 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 551 #define LPFC_SLI_INTF 0x0058 552 553 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 554 #define lpfc_port_smphr_perr_SHIFT 31 555 #define lpfc_port_smphr_perr_MASK 0x1 556 #define lpfc_port_smphr_perr_WORD word0 557 #define lpfc_port_smphr_sfi_SHIFT 30 558 #define lpfc_port_smphr_sfi_MASK 0x1 559 #define lpfc_port_smphr_sfi_WORD word0 560 #define lpfc_port_smphr_nip_SHIFT 29 561 #define lpfc_port_smphr_nip_MASK 0x1 562 #define lpfc_port_smphr_nip_WORD word0 563 #define lpfc_port_smphr_ipc_SHIFT 28 564 #define lpfc_port_smphr_ipc_MASK 0x1 565 #define lpfc_port_smphr_ipc_WORD word0 566 #define lpfc_port_smphr_scr1_SHIFT 27 567 #define lpfc_port_smphr_scr1_MASK 0x1 568 #define lpfc_port_smphr_scr1_WORD word0 569 #define lpfc_port_smphr_scr2_SHIFT 26 570 #define lpfc_port_smphr_scr2_MASK 0x1 571 #define lpfc_port_smphr_scr2_WORD word0 572 #define lpfc_port_smphr_host_scratch_SHIFT 16 573 #define lpfc_port_smphr_host_scratch_MASK 0xFF 574 #define lpfc_port_smphr_host_scratch_WORD word0 575 #define lpfc_port_smphr_port_status_SHIFT 0 576 #define lpfc_port_smphr_port_status_MASK 0xFFFF 577 #define lpfc_port_smphr_port_status_WORD word0 578 579 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 580 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 581 #define LPFC_POST_STAGE_HOST_RDY 0x0002 582 #define LPFC_POST_STAGE_BE_RESET 0x0003 583 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 584 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 585 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 586 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 587 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 588 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 589 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 590 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 591 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 592 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 593 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 594 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 595 #define LPFC_POST_STAGE_ARMFW_START 0x0800 596 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 597 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 598 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 599 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 600 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 601 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 602 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 603 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 604 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 605 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 606 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 607 #define LPFC_POST_STAGE_RC_DONE 0x0B07 608 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 609 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 610 #define LPFC_POST_STAGE_PORT_READY 0xC000 611 #define LPFC_POST_STAGE_PORT_UE 0xF000 612 613 #define LPFC_CTL_PORT_STA_OFFSET 0x404 614 #define lpfc_sliport_status_err_SHIFT 31 615 #define lpfc_sliport_status_err_MASK 0x1 616 #define lpfc_sliport_status_err_WORD word0 617 #define lpfc_sliport_status_end_SHIFT 30 618 #define lpfc_sliport_status_end_MASK 0x1 619 #define lpfc_sliport_status_end_WORD word0 620 #define lpfc_sliport_status_oti_SHIFT 29 621 #define lpfc_sliport_status_oti_MASK 0x1 622 #define lpfc_sliport_status_oti_WORD word0 623 #define lpfc_sliport_status_rn_SHIFT 24 624 #define lpfc_sliport_status_rn_MASK 0x1 625 #define lpfc_sliport_status_rn_WORD word0 626 #define lpfc_sliport_status_rdy_SHIFT 23 627 #define lpfc_sliport_status_rdy_MASK 0x1 628 #define lpfc_sliport_status_rdy_WORD word0 629 #define MAX_IF_TYPE_2_RESETS 6 630 631 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 632 #define lpfc_sliport_ctrl_end_SHIFT 30 633 #define lpfc_sliport_ctrl_end_MASK 0x1 634 #define lpfc_sliport_ctrl_end_WORD word0 635 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 636 #define LPFC_SLIPORT_BIG_ENDIAN 1 637 #define lpfc_sliport_ctrl_ip_SHIFT 27 638 #define lpfc_sliport_ctrl_ip_MASK 0x1 639 #define lpfc_sliport_ctrl_ip_WORD word0 640 #define LPFC_SLIPORT_INIT_PORT 1 641 642 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 643 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 644 645 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 646 * reside in BAR 2. 647 */ 648 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 649 650 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 651 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 652 653 #define LPFC_HST_ISR0 0x0C18 654 #define LPFC_HST_ISR1 0x0C1C 655 #define LPFC_HST_ISR2 0x0C20 656 #define LPFC_HST_ISR3 0x0C24 657 #define LPFC_HST_ISR4 0x0C28 658 659 #define LPFC_HST_IMR0 0x0C48 660 #define LPFC_HST_IMR1 0x0C4C 661 #define LPFC_HST_IMR2 0x0C50 662 #define LPFC_HST_IMR3 0x0C54 663 #define LPFC_HST_IMR4 0x0C58 664 665 #define LPFC_HST_ISCR0 0x0C78 666 #define LPFC_HST_ISCR1 0x0C7C 667 #define LPFC_HST_ISCR2 0x0C80 668 #define LPFC_HST_ISCR3 0x0C84 669 #define LPFC_HST_ISCR4 0x0C88 670 671 #define LPFC_SLI4_INTR0 BIT0 672 #define LPFC_SLI4_INTR1 BIT1 673 #define LPFC_SLI4_INTR2 BIT2 674 #define LPFC_SLI4_INTR3 BIT3 675 #define LPFC_SLI4_INTR4 BIT4 676 #define LPFC_SLI4_INTR5 BIT5 677 #define LPFC_SLI4_INTR6 BIT6 678 #define LPFC_SLI4_INTR7 BIT7 679 #define LPFC_SLI4_INTR8 BIT8 680 #define LPFC_SLI4_INTR9 BIT9 681 #define LPFC_SLI4_INTR10 BIT10 682 #define LPFC_SLI4_INTR11 BIT11 683 #define LPFC_SLI4_INTR12 BIT12 684 #define LPFC_SLI4_INTR13 BIT13 685 #define LPFC_SLI4_INTR14 BIT14 686 #define LPFC_SLI4_INTR15 BIT15 687 #define LPFC_SLI4_INTR16 BIT16 688 #define LPFC_SLI4_INTR17 BIT17 689 #define LPFC_SLI4_INTR18 BIT18 690 #define LPFC_SLI4_INTR19 BIT19 691 #define LPFC_SLI4_INTR20 BIT20 692 #define LPFC_SLI4_INTR21 BIT21 693 #define LPFC_SLI4_INTR22 BIT22 694 #define LPFC_SLI4_INTR23 BIT23 695 #define LPFC_SLI4_INTR24 BIT24 696 #define LPFC_SLI4_INTR25 BIT25 697 #define LPFC_SLI4_INTR26 BIT26 698 #define LPFC_SLI4_INTR27 BIT27 699 #define LPFC_SLI4_INTR28 BIT28 700 #define LPFC_SLI4_INTR29 BIT29 701 #define LPFC_SLI4_INTR30 BIT30 702 #define LPFC_SLI4_INTR31 BIT31 703 704 /* 705 * The Doorbell registers defined here exist in different BAR 706 * register sets depending on the UCNA Port's reported if_type 707 * value. For UCNA ports running SLI4 and if_type 0, they reside in 708 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 709 * BAR0. The offsets are the same so the driver must account for 710 * any base address difference. 711 */ 712 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 713 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 714 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 715 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 716 #define lpfc_rq_db_list_fm_num_posted_WORD word0 717 #define lpfc_rq_db_list_fm_index_SHIFT 16 718 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 719 #define lpfc_rq_db_list_fm_index_WORD word0 720 #define lpfc_rq_db_list_fm_id_SHIFT 0 721 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 722 #define lpfc_rq_db_list_fm_id_WORD word0 723 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 724 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 725 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 726 #define lpfc_rq_db_ring_fm_id_SHIFT 0 727 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 728 #define lpfc_rq_db_ring_fm_id_WORD word0 729 730 #define LPFC_ULP0_WQ_DOORBELL 0x0040 731 #define LPFC_ULP1_WQ_DOORBELL 0x0060 732 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 733 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 734 #define lpfc_wq_db_list_fm_num_posted_WORD word0 735 #define lpfc_wq_db_list_fm_index_SHIFT 16 736 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 737 #define lpfc_wq_db_list_fm_index_WORD word0 738 #define lpfc_wq_db_list_fm_id_SHIFT 0 739 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 740 #define lpfc_wq_db_list_fm_id_WORD word0 741 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 742 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 743 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 744 #define lpfc_wq_db_ring_fm_id_SHIFT 0 745 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 746 #define lpfc_wq_db_ring_fm_id_WORD word0 747 748 #define LPFC_EQCQ_DOORBELL 0x0120 749 #define lpfc_eqcq_doorbell_se_SHIFT 31 750 #define lpfc_eqcq_doorbell_se_MASK 0x0001 751 #define lpfc_eqcq_doorbell_se_WORD word0 752 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 753 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 754 #define lpfc_eqcq_doorbell_arm_SHIFT 29 755 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 756 #define lpfc_eqcq_doorbell_arm_WORD word0 757 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 758 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 759 #define lpfc_eqcq_doorbell_num_released_WORD word0 760 #define lpfc_eqcq_doorbell_qt_SHIFT 10 761 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 762 #define lpfc_eqcq_doorbell_qt_WORD word0 763 #define LPFC_QUEUE_TYPE_COMPLETION 0 764 #define LPFC_QUEUE_TYPE_EVENT 1 765 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 766 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 767 #define lpfc_eqcq_doorbell_eqci_WORD word0 768 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 769 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 770 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 771 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 772 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 773 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 774 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 775 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 776 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 777 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 778 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 779 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 780 #define LPFC_CQID_HI_FIELD_SHIFT 10 781 #define LPFC_EQID_HI_FIELD_SHIFT 9 782 783 #define LPFC_BMBX 0x0160 784 #define lpfc_bmbx_addr_SHIFT 2 785 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 786 #define lpfc_bmbx_addr_WORD word0 787 #define lpfc_bmbx_hi_SHIFT 1 788 #define lpfc_bmbx_hi_MASK 0x0001 789 #define lpfc_bmbx_hi_WORD word0 790 #define lpfc_bmbx_rdy_SHIFT 0 791 #define lpfc_bmbx_rdy_MASK 0x0001 792 #define lpfc_bmbx_rdy_WORD word0 793 794 #define LPFC_MQ_DOORBELL 0x0140 795 #define lpfc_mq_doorbell_num_posted_SHIFT 16 796 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 797 #define lpfc_mq_doorbell_num_posted_WORD word0 798 #define lpfc_mq_doorbell_id_SHIFT 0 799 #define lpfc_mq_doorbell_id_MASK 0xFFFF 800 #define lpfc_mq_doorbell_id_WORD word0 801 802 struct lpfc_sli4_cfg_mhdr { 803 uint32_t word1; 804 #define lpfc_mbox_hdr_emb_SHIFT 0 805 #define lpfc_mbox_hdr_emb_MASK 0x00000001 806 #define lpfc_mbox_hdr_emb_WORD word1 807 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 808 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 809 #define lpfc_mbox_hdr_sge_cnt_WORD word1 810 uint32_t payload_length; 811 uint32_t tag_lo; 812 uint32_t tag_hi; 813 uint32_t reserved5; 814 }; 815 816 union lpfc_sli4_cfg_shdr { 817 struct { 818 uint32_t word6; 819 #define lpfc_mbox_hdr_opcode_SHIFT 0 820 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 821 #define lpfc_mbox_hdr_opcode_WORD word6 822 #define lpfc_mbox_hdr_subsystem_SHIFT 8 823 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 824 #define lpfc_mbox_hdr_subsystem_WORD word6 825 #define lpfc_mbox_hdr_port_number_SHIFT 16 826 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 827 #define lpfc_mbox_hdr_port_number_WORD word6 828 #define lpfc_mbox_hdr_domain_SHIFT 24 829 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 830 #define lpfc_mbox_hdr_domain_WORD word6 831 uint32_t timeout; 832 uint32_t request_length; 833 uint32_t word9; 834 #define lpfc_mbox_hdr_version_SHIFT 0 835 #define lpfc_mbox_hdr_version_MASK 0x000000FF 836 #define lpfc_mbox_hdr_version_WORD word9 837 #define lpfc_mbox_hdr_pf_num_SHIFT 16 838 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 839 #define lpfc_mbox_hdr_pf_num_WORD word9 840 #define lpfc_mbox_hdr_vh_num_SHIFT 24 841 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 842 #define lpfc_mbox_hdr_vh_num_WORD word9 843 #define LPFC_Q_CREATE_VERSION_2 2 844 #define LPFC_Q_CREATE_VERSION_1 1 845 #define LPFC_Q_CREATE_VERSION_0 0 846 #define LPFC_OPCODE_VERSION_0 0 847 #define LPFC_OPCODE_VERSION_1 1 848 } request; 849 struct { 850 uint32_t word6; 851 #define lpfc_mbox_hdr_opcode_SHIFT 0 852 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 853 #define lpfc_mbox_hdr_opcode_WORD word6 854 #define lpfc_mbox_hdr_subsystem_SHIFT 8 855 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 856 #define lpfc_mbox_hdr_subsystem_WORD word6 857 #define lpfc_mbox_hdr_domain_SHIFT 24 858 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 859 #define lpfc_mbox_hdr_domain_WORD word6 860 uint32_t word7; 861 #define lpfc_mbox_hdr_status_SHIFT 0 862 #define lpfc_mbox_hdr_status_MASK 0x000000FF 863 #define lpfc_mbox_hdr_status_WORD word7 864 #define lpfc_mbox_hdr_add_status_SHIFT 8 865 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 866 #define lpfc_mbox_hdr_add_status_WORD word7 867 uint32_t response_length; 868 uint32_t actual_response_length; 869 } response; 870 }; 871 872 /* Mailbox Header structures. 873 * struct mbox_header is defined for first generation SLI4_CFG mailbox 874 * calls deployed for BE-based ports. 875 * 876 * struct sli4_mbox_header is defined for second generation SLI4 877 * ports that don't deploy the SLI4_CFG mechanism. 878 */ 879 struct mbox_header { 880 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 881 union lpfc_sli4_cfg_shdr cfg_shdr; 882 }; 883 884 #define LPFC_EXTENT_LOCAL 0 885 #define LPFC_TIMEOUT_DEFAULT 0 886 #define LPFC_EXTENT_VERSION_DEFAULT 0 887 888 /* Subsystem Definitions */ 889 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 890 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 891 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 892 893 /* Device Specific Definitions */ 894 895 /* The HOST ENDIAN defines are in Big Endian format. */ 896 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 897 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 898 899 /* Common Opcodes */ 900 #define LPFC_MBOX_OPCODE_NA 0x00 901 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 902 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 903 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 904 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 905 #define LPFC_MBOX_OPCODE_NOP 0x21 906 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 907 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 908 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 909 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 910 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 911 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 912 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 913 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 914 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 915 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 916 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 917 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 918 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 919 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 920 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 921 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 922 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 923 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 924 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 925 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 926 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 927 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 928 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 929 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 930 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 931 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 932 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 933 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 934 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 935 936 /* FCoE Opcodes */ 937 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 938 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 939 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 940 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 941 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 942 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 943 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 944 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 945 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 946 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 947 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 948 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 949 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 950 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 951 952 /* Mailbox command structures */ 953 struct eq_context { 954 uint32_t word0; 955 #define lpfc_eq_context_size_SHIFT 31 956 #define lpfc_eq_context_size_MASK 0x00000001 957 #define lpfc_eq_context_size_WORD word0 958 #define LPFC_EQE_SIZE_4 0x0 959 #define LPFC_EQE_SIZE_16 0x1 960 #define lpfc_eq_context_valid_SHIFT 29 961 #define lpfc_eq_context_valid_MASK 0x00000001 962 #define lpfc_eq_context_valid_WORD word0 963 uint32_t word1; 964 #define lpfc_eq_context_count_SHIFT 26 965 #define lpfc_eq_context_count_MASK 0x00000003 966 #define lpfc_eq_context_count_WORD word1 967 #define LPFC_EQ_CNT_256 0x0 968 #define LPFC_EQ_CNT_512 0x1 969 #define LPFC_EQ_CNT_1024 0x2 970 #define LPFC_EQ_CNT_2048 0x3 971 #define LPFC_EQ_CNT_4096 0x4 972 uint32_t word2; 973 #define lpfc_eq_context_delay_multi_SHIFT 13 974 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 975 #define lpfc_eq_context_delay_multi_WORD word2 976 uint32_t reserved3; 977 }; 978 979 struct eq_delay_info { 980 uint32_t eq_id; 981 uint32_t phase; 982 uint32_t delay_multi; 983 }; 984 #define LPFC_MAX_EQ_DELAY 8 985 986 struct sgl_page_pairs { 987 uint32_t sgl_pg0_addr_lo; 988 uint32_t sgl_pg0_addr_hi; 989 uint32_t sgl_pg1_addr_lo; 990 uint32_t sgl_pg1_addr_hi; 991 }; 992 993 struct lpfc_mbx_post_sgl_pages { 994 struct mbox_header header; 995 uint32_t word0; 996 #define lpfc_post_sgl_pages_xri_SHIFT 0 997 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 998 #define lpfc_post_sgl_pages_xri_WORD word0 999 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1000 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1001 #define lpfc_post_sgl_pages_xricnt_WORD word0 1002 struct sgl_page_pairs sgl_pg_pairs[1]; 1003 }; 1004 1005 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1006 struct lpfc_mbx_post_uembed_sgl_page1 { 1007 union lpfc_sli4_cfg_shdr cfg_shdr; 1008 uint32_t word0; 1009 struct sgl_page_pairs sgl_pg_pairs; 1010 }; 1011 1012 struct lpfc_mbx_sge { 1013 uint32_t pa_lo; 1014 uint32_t pa_hi; 1015 uint32_t length; 1016 }; 1017 1018 struct lpfc_mbx_nembed_cmd { 1019 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1020 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1021 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1022 }; 1023 1024 struct lpfc_mbx_nembed_sge_virt { 1025 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1026 }; 1027 1028 struct lpfc_mbx_eq_create { 1029 struct mbox_header header; 1030 union { 1031 struct { 1032 uint32_t word0; 1033 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1034 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1035 #define lpfc_mbx_eq_create_num_pages_WORD word0 1036 struct eq_context context; 1037 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1038 } request; 1039 struct { 1040 uint32_t word0; 1041 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1042 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1043 #define lpfc_mbx_eq_create_q_id_WORD word0 1044 } response; 1045 } u; 1046 }; 1047 1048 struct lpfc_mbx_modify_eq_delay { 1049 struct mbox_header header; 1050 union { 1051 struct { 1052 uint32_t num_eq; 1053 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY]; 1054 } request; 1055 struct { 1056 uint32_t word0; 1057 } response; 1058 } u; 1059 }; 1060 1061 struct lpfc_mbx_eq_destroy { 1062 struct mbox_header header; 1063 union { 1064 struct { 1065 uint32_t word0; 1066 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1067 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1068 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1069 } request; 1070 struct { 1071 uint32_t word0; 1072 } response; 1073 } u; 1074 }; 1075 1076 struct lpfc_mbx_nop { 1077 struct mbox_header header; 1078 uint32_t context[2]; 1079 }; 1080 1081 struct cq_context { 1082 uint32_t word0; 1083 #define lpfc_cq_context_event_SHIFT 31 1084 #define lpfc_cq_context_event_MASK 0x00000001 1085 #define lpfc_cq_context_event_WORD word0 1086 #define lpfc_cq_context_valid_SHIFT 29 1087 #define lpfc_cq_context_valid_MASK 0x00000001 1088 #define lpfc_cq_context_valid_WORD word0 1089 #define lpfc_cq_context_count_SHIFT 27 1090 #define lpfc_cq_context_count_MASK 0x00000003 1091 #define lpfc_cq_context_count_WORD word0 1092 #define LPFC_CQ_CNT_256 0x0 1093 #define LPFC_CQ_CNT_512 0x1 1094 #define LPFC_CQ_CNT_1024 0x2 1095 uint32_t word1; 1096 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1097 #define lpfc_cq_eq_id_MASK 0x000000FF 1098 #define lpfc_cq_eq_id_WORD word1 1099 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1100 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1101 #define lpfc_cq_eq_id_2_WORD word1 1102 uint32_t reserved0; 1103 uint32_t reserved1; 1104 }; 1105 1106 struct lpfc_mbx_cq_create { 1107 struct mbox_header header; 1108 union { 1109 struct { 1110 uint32_t word0; 1111 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1112 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1113 #define lpfc_mbx_cq_create_page_size_WORD word0 1114 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1115 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1116 #define lpfc_mbx_cq_create_num_pages_WORD word0 1117 struct cq_context context; 1118 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1119 } request; 1120 struct { 1121 uint32_t word0; 1122 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1123 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1124 #define lpfc_mbx_cq_create_q_id_WORD word0 1125 } response; 1126 } u; 1127 }; 1128 1129 struct lpfc_mbx_cq_destroy { 1130 struct mbox_header header; 1131 union { 1132 struct { 1133 uint32_t word0; 1134 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1135 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1136 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1137 } request; 1138 struct { 1139 uint32_t word0; 1140 } response; 1141 } u; 1142 }; 1143 1144 struct wq_context { 1145 uint32_t reserved0; 1146 uint32_t reserved1; 1147 uint32_t reserved2; 1148 uint32_t reserved3; 1149 }; 1150 1151 struct lpfc_mbx_wq_create { 1152 struct mbox_header header; 1153 union { 1154 struct { /* Version 0 Request */ 1155 uint32_t word0; 1156 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1157 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1158 #define lpfc_mbx_wq_create_num_pages_WORD word0 1159 #define lpfc_mbx_wq_create_dua_SHIFT 8 1160 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1161 #define lpfc_mbx_wq_create_dua_WORD word0 1162 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1163 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1164 #define lpfc_mbx_wq_create_cq_id_WORD word0 1165 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1166 uint32_t word9; 1167 #define lpfc_mbx_wq_create_bua_SHIFT 0 1168 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1169 #define lpfc_mbx_wq_create_bua_WORD word9 1170 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1171 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1172 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1173 } request; 1174 struct { /* Version 1 Request */ 1175 uint32_t word0; /* Word 0 is the same as in v0 */ 1176 uint32_t word1; 1177 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1178 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1179 #define lpfc_mbx_wq_create_page_size_WORD word1 1180 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1181 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1182 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1183 #define LPFC_WQ_WQE_SIZE_64 0x5 1184 #define LPFC_WQ_WQE_SIZE_128 0x6 1185 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1186 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1187 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1188 uint32_t word2; 1189 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1190 } request_1; 1191 struct { 1192 uint32_t word0; 1193 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1194 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1195 #define lpfc_mbx_wq_create_q_id_WORD word0 1196 uint32_t doorbell_offset; 1197 uint32_t word2; 1198 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1199 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1200 #define lpfc_mbx_wq_create_bar_set_WORD word2 1201 #define WQ_PCI_BAR_0_AND_1 0x00 1202 #define WQ_PCI_BAR_2_AND_3 0x01 1203 #define WQ_PCI_BAR_4_AND_5 0x02 1204 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1205 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1206 #define lpfc_mbx_wq_create_db_format_WORD word2 1207 } response; 1208 } u; 1209 }; 1210 1211 struct lpfc_mbx_wq_destroy { 1212 struct mbox_header header; 1213 union { 1214 struct { 1215 uint32_t word0; 1216 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1217 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1218 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1219 } request; 1220 struct { 1221 uint32_t word0; 1222 } response; 1223 } u; 1224 }; 1225 1226 #define LPFC_HDR_BUF_SIZE 128 1227 #define LPFC_DATA_BUF_SIZE 2048 1228 struct rq_context { 1229 uint32_t word0; 1230 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1231 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1232 #define lpfc_rq_context_rqe_count_WORD word0 1233 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1234 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1235 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1236 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1237 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1238 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1239 #define lpfc_rq_context_rqe_count_1_WORD word0 1240 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1241 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1242 #define lpfc_rq_context_rqe_size_WORD word0 1243 #define LPFC_RQE_SIZE_8 2 1244 #define LPFC_RQE_SIZE_16 3 1245 #define LPFC_RQE_SIZE_32 4 1246 #define LPFC_RQE_SIZE_64 5 1247 #define LPFC_RQE_SIZE_128 6 1248 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1249 #define lpfc_rq_context_page_size_MASK 0x000000FF 1250 #define lpfc_rq_context_page_size_WORD word0 1251 uint32_t reserved1; 1252 uint32_t word2; 1253 #define lpfc_rq_context_cq_id_SHIFT 16 1254 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1255 #define lpfc_rq_context_cq_id_WORD word2 1256 #define lpfc_rq_context_buf_size_SHIFT 0 1257 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1258 #define lpfc_rq_context_buf_size_WORD word2 1259 uint32_t buffer_size; /* Version 1 Only */ 1260 }; 1261 1262 struct lpfc_mbx_rq_create { 1263 struct mbox_header header; 1264 union { 1265 struct { 1266 uint32_t word0; 1267 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1268 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1269 #define lpfc_mbx_rq_create_num_pages_WORD word0 1270 #define lpfc_mbx_rq_create_dua_SHIFT 16 1271 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1272 #define lpfc_mbx_rq_create_dua_WORD word0 1273 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1274 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1275 #define lpfc_mbx_rq_create_bqu_WORD word0 1276 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1277 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1278 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1279 struct rq_context context; 1280 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1281 } request; 1282 struct { 1283 uint32_t word0; 1284 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1285 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1286 #define lpfc_mbx_rq_create_q_id_WORD word0 1287 uint32_t doorbell_offset; 1288 uint32_t word2; 1289 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1290 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1291 #define lpfc_mbx_rq_create_bar_set_WORD word2 1292 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1293 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1294 #define lpfc_mbx_rq_create_db_format_WORD word2 1295 } response; 1296 } u; 1297 }; 1298 1299 struct lpfc_mbx_rq_destroy { 1300 struct mbox_header header; 1301 union { 1302 struct { 1303 uint32_t word0; 1304 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1305 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1306 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1307 } request; 1308 struct { 1309 uint32_t word0; 1310 } response; 1311 } u; 1312 }; 1313 1314 struct mq_context { 1315 uint32_t word0; 1316 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1317 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1318 #define lpfc_mq_context_cq_id_WORD word0 1319 #define lpfc_mq_context_ring_size_SHIFT 16 1320 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1321 #define lpfc_mq_context_ring_size_WORD word0 1322 #define LPFC_MQ_RING_SIZE_16 0x5 1323 #define LPFC_MQ_RING_SIZE_32 0x6 1324 #define LPFC_MQ_RING_SIZE_64 0x7 1325 #define LPFC_MQ_RING_SIZE_128 0x8 1326 uint32_t word1; 1327 #define lpfc_mq_context_valid_SHIFT 31 1328 #define lpfc_mq_context_valid_MASK 0x00000001 1329 #define lpfc_mq_context_valid_WORD word1 1330 uint32_t reserved2; 1331 uint32_t reserved3; 1332 }; 1333 1334 struct lpfc_mbx_mq_create { 1335 struct mbox_header header; 1336 union { 1337 struct { 1338 uint32_t word0; 1339 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1340 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1341 #define lpfc_mbx_mq_create_num_pages_WORD word0 1342 struct mq_context context; 1343 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1344 } request; 1345 struct { 1346 uint32_t word0; 1347 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1348 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1349 #define lpfc_mbx_mq_create_q_id_WORD word0 1350 } response; 1351 } u; 1352 }; 1353 1354 struct lpfc_mbx_mq_create_ext { 1355 struct mbox_header header; 1356 union { 1357 struct { 1358 uint32_t word0; 1359 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1360 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1361 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1362 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1363 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1364 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1365 uint32_t async_evt_bmap; 1366 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1367 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1368 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1369 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1370 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1371 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1372 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1373 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1374 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1375 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1376 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1377 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1378 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1379 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1380 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1381 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1382 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1383 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1384 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1385 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1386 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1387 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1388 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1389 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1390 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1391 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1392 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1393 struct mq_context context; 1394 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1395 } request; 1396 struct { 1397 uint32_t word0; 1398 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1399 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1400 #define lpfc_mbx_mq_create_q_id_WORD word0 1401 } response; 1402 } u; 1403 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1404 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1405 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1406 }; 1407 1408 struct lpfc_mbx_mq_destroy { 1409 struct mbox_header header; 1410 union { 1411 struct { 1412 uint32_t word0; 1413 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1414 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1415 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1416 } request; 1417 struct { 1418 uint32_t word0; 1419 } response; 1420 } u; 1421 }; 1422 1423 /* Start Gen 2 SLI4 Mailbox definitions: */ 1424 1425 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1426 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1427 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1428 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1429 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1430 1431 struct lpfc_mbx_get_rsrc_extent_info { 1432 struct mbox_header header; 1433 union { 1434 struct { 1435 uint32_t word4; 1436 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1437 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1438 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1439 } req; 1440 struct { 1441 uint32_t word4; 1442 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1443 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1444 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1445 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1446 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1447 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1448 } rsp; 1449 } u; 1450 }; 1451 1452 struct lpfc_mbx_query_fw_config { 1453 struct mbox_header header; 1454 struct { 1455 uint32_t config_number; 1456 #define LPFC_FC_FCOE 0x00000007 1457 uint32_t asic_revision; 1458 uint32_t physical_port; 1459 uint32_t function_mode; 1460 #define LPFC_FCOE_INI_MODE 0x00000040 1461 #define LPFC_FCOE_TGT_MODE 0x00000080 1462 #define LPFC_DUA_MODE 0x00000800 1463 uint32_t ulp0_mode; 1464 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1465 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1466 uint32_t ulp0_nap_words[12]; 1467 uint32_t ulp1_mode; 1468 uint32_t ulp1_nap_words[12]; 1469 uint32_t function_capabilities; 1470 uint32_t cqid_base; 1471 uint32_t cqid_tot; 1472 uint32_t eqid_base; 1473 uint32_t eqid_tot; 1474 uint32_t ulp0_nap2_words[2]; 1475 uint32_t ulp1_nap2_words[2]; 1476 } rsp; 1477 }; 1478 1479 struct lpfc_id_range { 1480 uint32_t word5; 1481 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1482 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1483 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1484 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1485 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1486 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1487 }; 1488 1489 struct lpfc_mbx_set_link_diag_state { 1490 struct mbox_header header; 1491 union { 1492 struct { 1493 uint32_t word0; 1494 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1495 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1496 #define lpfc_mbx_set_diag_state_diag_WORD word0 1497 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1498 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1499 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1500 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1501 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1502 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1503 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1504 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1505 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1506 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1507 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1508 } req; 1509 struct { 1510 uint32_t word0; 1511 } rsp; 1512 } u; 1513 }; 1514 1515 struct lpfc_mbx_set_link_diag_loopback { 1516 struct mbox_header header; 1517 union { 1518 struct { 1519 uint32_t word0; 1520 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1521 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1522 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1523 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1524 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1525 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1526 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1527 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1528 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1529 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1530 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1531 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1532 } req; 1533 struct { 1534 uint32_t word0; 1535 } rsp; 1536 } u; 1537 }; 1538 1539 struct lpfc_mbx_run_link_diag_test { 1540 struct mbox_header header; 1541 union { 1542 struct { 1543 uint32_t word0; 1544 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1545 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1546 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1547 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1548 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1549 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1550 uint32_t word1; 1551 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1552 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1553 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1554 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1555 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1556 #define lpfc_mbx_run_diag_test_loops_WORD word1 1557 uint32_t word2; 1558 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1559 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1560 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1561 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1562 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1563 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1564 } req; 1565 struct { 1566 uint32_t word0; 1567 } rsp; 1568 } u; 1569 }; 1570 1571 /* 1572 * struct lpfc_mbx_alloc_rsrc_extents: 1573 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1574 * 6 words of header + 4 words of shared subcommand header + 1575 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1576 * 1577 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1578 * for extents payload. 1579 * 1580 * 212/2 (bytes per extent) = 106 extents. 1581 * 106/2 (extents per word) = 53 words. 1582 * lpfc_id_range id is statically size to 53. 1583 * 1584 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1585 * extent ranges. For ALLOC, the type and cnt are required. 1586 * For GET_ALLOCATED, only the type is required. 1587 */ 1588 struct lpfc_mbx_alloc_rsrc_extents { 1589 struct mbox_header header; 1590 union { 1591 struct { 1592 uint32_t word4; 1593 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1594 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1595 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1596 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1597 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1598 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1599 } req; 1600 struct { 1601 uint32_t word4; 1602 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1603 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1604 #define lpfc_mbx_rsrc_cnt_WORD word4 1605 struct lpfc_id_range id[53]; 1606 } rsp; 1607 } u; 1608 }; 1609 1610 /* 1611 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1612 * structure shares the same SHIFT/MASK/WORD defines provided in the 1613 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1614 * the structures defined above. This non-embedded structure provides for the 1615 * maximum number of extents supported by the port. 1616 */ 1617 struct lpfc_mbx_nembed_rsrc_extent { 1618 union lpfc_sli4_cfg_shdr cfg_shdr; 1619 uint32_t word4; 1620 struct lpfc_id_range id; 1621 }; 1622 1623 struct lpfc_mbx_dealloc_rsrc_extents { 1624 struct mbox_header header; 1625 struct { 1626 uint32_t word4; 1627 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1628 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1629 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1630 } req; 1631 1632 }; 1633 1634 /* Start SLI4 FCoE specific mbox structures. */ 1635 1636 struct lpfc_mbx_post_hdr_tmpl { 1637 struct mbox_header header; 1638 uint32_t word10; 1639 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1640 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1641 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1642 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1643 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1644 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1645 uint32_t rpi_paddr_lo; 1646 uint32_t rpi_paddr_hi; 1647 }; 1648 1649 struct sli4_sge { /* SLI-4 */ 1650 uint32_t addr_hi; 1651 uint32_t addr_lo; 1652 1653 uint32_t word2; 1654 #define lpfc_sli4_sge_offset_SHIFT 0 1655 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1656 #define lpfc_sli4_sge_offset_WORD word2 1657 #define lpfc_sli4_sge_type_SHIFT 27 1658 #define lpfc_sli4_sge_type_MASK 0x0000000F 1659 #define lpfc_sli4_sge_type_WORD word2 1660 #define LPFC_SGE_TYPE_DATA 0x0 1661 #define LPFC_SGE_TYPE_DIF 0x4 1662 #define LPFC_SGE_TYPE_LSP 0x5 1663 #define LPFC_SGE_TYPE_PEDIF 0x6 1664 #define LPFC_SGE_TYPE_PESEED 0x7 1665 #define LPFC_SGE_TYPE_DISEED 0x8 1666 #define LPFC_SGE_TYPE_ENC 0x9 1667 #define LPFC_SGE_TYPE_ATM 0xA 1668 #define LPFC_SGE_TYPE_SKIP 0xC 1669 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1670 #define lpfc_sli4_sge_last_MASK 0x00000001 1671 #define lpfc_sli4_sge_last_WORD word2 1672 uint32_t sge_len; 1673 }; 1674 1675 struct sli4_sge_diseed { /* SLI-4 */ 1676 uint32_t ref_tag; 1677 uint32_t ref_tag_tran; 1678 1679 uint32_t word2; 1680 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1681 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1682 #define lpfc_sli4_sge_dif_apptran_WORD word2 1683 #define lpfc_sli4_sge_dif_af_SHIFT 24 1684 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1685 #define lpfc_sli4_sge_dif_af_WORD word2 1686 #define lpfc_sli4_sge_dif_na_SHIFT 25 1687 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1688 #define lpfc_sli4_sge_dif_na_WORD word2 1689 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1690 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1691 #define lpfc_sli4_sge_dif_hi_WORD word2 1692 #define lpfc_sli4_sge_dif_type_SHIFT 27 1693 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1694 #define lpfc_sli4_sge_dif_type_WORD word2 1695 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1696 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1697 #define lpfc_sli4_sge_dif_last_WORD word2 1698 uint32_t word3; 1699 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1700 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1701 #define lpfc_sli4_sge_dif_apptag_WORD word3 1702 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1703 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1704 #define lpfc_sli4_sge_dif_bs_WORD word3 1705 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1706 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1707 #define lpfc_sli4_sge_dif_ai_WORD word3 1708 #define lpfc_sli4_sge_dif_me_SHIFT 20 1709 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1710 #define lpfc_sli4_sge_dif_me_WORD word3 1711 #define lpfc_sli4_sge_dif_re_SHIFT 21 1712 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1713 #define lpfc_sli4_sge_dif_re_WORD word3 1714 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1715 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1716 #define lpfc_sli4_sge_dif_ce_WORD word3 1717 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1718 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1719 #define lpfc_sli4_sge_dif_nr_WORD word3 1720 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1721 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1722 #define lpfc_sli4_sge_dif_oprx_WORD word3 1723 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1724 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1725 #define lpfc_sli4_sge_dif_optx_WORD word3 1726 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1727 }; 1728 1729 struct fcf_record { 1730 uint32_t max_rcv_size; 1731 uint32_t fka_adv_period; 1732 uint32_t fip_priority; 1733 uint32_t word3; 1734 #define lpfc_fcf_record_mac_0_SHIFT 0 1735 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1736 #define lpfc_fcf_record_mac_0_WORD word3 1737 #define lpfc_fcf_record_mac_1_SHIFT 8 1738 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1739 #define lpfc_fcf_record_mac_1_WORD word3 1740 #define lpfc_fcf_record_mac_2_SHIFT 16 1741 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1742 #define lpfc_fcf_record_mac_2_WORD word3 1743 #define lpfc_fcf_record_mac_3_SHIFT 24 1744 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1745 #define lpfc_fcf_record_mac_3_WORD word3 1746 uint32_t word4; 1747 #define lpfc_fcf_record_mac_4_SHIFT 0 1748 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1749 #define lpfc_fcf_record_mac_4_WORD word4 1750 #define lpfc_fcf_record_mac_5_SHIFT 8 1751 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1752 #define lpfc_fcf_record_mac_5_WORD word4 1753 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1754 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1755 #define lpfc_fcf_record_fcf_avail_WORD word4 1756 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1757 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1758 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1759 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1760 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1761 uint32_t word5; 1762 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1763 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1764 #define lpfc_fcf_record_fab_name_0_WORD word5 1765 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1766 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1767 #define lpfc_fcf_record_fab_name_1_WORD word5 1768 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1769 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1770 #define lpfc_fcf_record_fab_name_2_WORD word5 1771 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1772 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1773 #define lpfc_fcf_record_fab_name_3_WORD word5 1774 uint32_t word6; 1775 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1776 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1777 #define lpfc_fcf_record_fab_name_4_WORD word6 1778 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1779 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1780 #define lpfc_fcf_record_fab_name_5_WORD word6 1781 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1782 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1783 #define lpfc_fcf_record_fab_name_6_WORD word6 1784 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1785 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1786 #define lpfc_fcf_record_fab_name_7_WORD word6 1787 uint32_t word7; 1788 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1789 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1790 #define lpfc_fcf_record_fc_map_0_WORD word7 1791 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1792 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1793 #define lpfc_fcf_record_fc_map_1_WORD word7 1794 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1795 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1796 #define lpfc_fcf_record_fc_map_2_WORD word7 1797 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1798 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 1799 #define lpfc_fcf_record_fcf_valid_WORD word7 1800 #define lpfc_fcf_record_fcf_fc_SHIFT 25 1801 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 1802 #define lpfc_fcf_record_fcf_fc_WORD word7 1803 #define lpfc_fcf_record_fcf_sol_SHIFT 31 1804 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 1805 #define lpfc_fcf_record_fcf_sol_WORD word7 1806 uint32_t word8; 1807 #define lpfc_fcf_record_fcf_index_SHIFT 0 1808 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1809 #define lpfc_fcf_record_fcf_index_WORD word8 1810 #define lpfc_fcf_record_fcf_state_SHIFT 16 1811 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1812 #define lpfc_fcf_record_fcf_state_WORD word8 1813 uint8_t vlan_bitmap[512]; 1814 uint32_t word137; 1815 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1816 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1817 #define lpfc_fcf_record_switch_name_0_WORD word137 1818 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1819 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1820 #define lpfc_fcf_record_switch_name_1_WORD word137 1821 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1822 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1823 #define lpfc_fcf_record_switch_name_2_WORD word137 1824 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1825 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1826 #define lpfc_fcf_record_switch_name_3_WORD word137 1827 uint32_t word138; 1828 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1829 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1830 #define lpfc_fcf_record_switch_name_4_WORD word138 1831 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1832 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1833 #define lpfc_fcf_record_switch_name_5_WORD word138 1834 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1835 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1836 #define lpfc_fcf_record_switch_name_6_WORD word138 1837 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1838 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1839 #define lpfc_fcf_record_switch_name_7_WORD word138 1840 }; 1841 1842 struct lpfc_mbx_read_fcf_tbl { 1843 union lpfc_sli4_cfg_shdr cfg_shdr; 1844 union { 1845 struct { 1846 uint32_t word10; 1847 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1848 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1849 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1850 } request; 1851 struct { 1852 uint32_t eventag; 1853 } response; 1854 } u; 1855 uint32_t word11; 1856 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1857 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1858 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1859 }; 1860 1861 struct lpfc_mbx_add_fcf_tbl_entry { 1862 union lpfc_sli4_cfg_shdr cfg_shdr; 1863 uint32_t word10; 1864 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1865 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1866 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1867 struct lpfc_mbx_sge fcf_sge; 1868 }; 1869 1870 struct lpfc_mbx_del_fcf_tbl_entry { 1871 struct mbox_header header; 1872 uint32_t word10; 1873 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1874 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1875 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1876 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1877 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1878 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1879 }; 1880 1881 struct lpfc_mbx_redisc_fcf_tbl { 1882 struct mbox_header header; 1883 uint32_t word10; 1884 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1885 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1886 #define lpfc_mbx_redisc_fcf_count_WORD word10 1887 uint32_t resvd; 1888 uint32_t word12; 1889 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1890 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1891 #define lpfc_mbx_redisc_fcf_index_WORD word12 1892 }; 1893 1894 /* Status field for embedded SLI_CONFIG mailbox command */ 1895 #define STATUS_SUCCESS 0x0 1896 #define STATUS_FAILED 0x1 1897 #define STATUS_ILLEGAL_REQUEST 0x2 1898 #define STATUS_ILLEGAL_FIELD 0x3 1899 #define STATUS_INSUFFICIENT_BUFFER 0x4 1900 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1901 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1902 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1903 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1904 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1905 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1906 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1907 #define STATUS_ASSERT_FAILED 0x1e 1908 #define STATUS_INVALID_SESSION 0x1f 1909 #define STATUS_INVALID_CONNECTION 0x20 1910 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1911 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1912 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1913 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1914 #define STATUS_FLASHROM_READ_FAILED 0x27 1915 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1916 #define STATUS_ERROR_ACITMAIN 0x2a 1917 #define STATUS_REBOOT_REQUIRED 0x2c 1918 #define STATUS_FCF_IN_USE 0x3a 1919 #define STATUS_FCF_TABLE_EMPTY 0x43 1920 1921 struct lpfc_mbx_sli4_config { 1922 struct mbox_header header; 1923 }; 1924 1925 struct lpfc_mbx_init_vfi { 1926 uint32_t word1; 1927 #define lpfc_init_vfi_vr_SHIFT 31 1928 #define lpfc_init_vfi_vr_MASK 0x00000001 1929 #define lpfc_init_vfi_vr_WORD word1 1930 #define lpfc_init_vfi_vt_SHIFT 30 1931 #define lpfc_init_vfi_vt_MASK 0x00000001 1932 #define lpfc_init_vfi_vt_WORD word1 1933 #define lpfc_init_vfi_vf_SHIFT 29 1934 #define lpfc_init_vfi_vf_MASK 0x00000001 1935 #define lpfc_init_vfi_vf_WORD word1 1936 #define lpfc_init_vfi_vp_SHIFT 28 1937 #define lpfc_init_vfi_vp_MASK 0x00000001 1938 #define lpfc_init_vfi_vp_WORD word1 1939 #define lpfc_init_vfi_vfi_SHIFT 0 1940 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1941 #define lpfc_init_vfi_vfi_WORD word1 1942 uint32_t word2; 1943 #define lpfc_init_vfi_vpi_SHIFT 16 1944 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1945 #define lpfc_init_vfi_vpi_WORD word2 1946 #define lpfc_init_vfi_fcfi_SHIFT 0 1947 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1948 #define lpfc_init_vfi_fcfi_WORD word2 1949 uint32_t word3; 1950 #define lpfc_init_vfi_pri_SHIFT 13 1951 #define lpfc_init_vfi_pri_MASK 0x00000007 1952 #define lpfc_init_vfi_pri_WORD word3 1953 #define lpfc_init_vfi_vf_id_SHIFT 1 1954 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1955 #define lpfc_init_vfi_vf_id_WORD word3 1956 uint32_t word4; 1957 #define lpfc_init_vfi_hop_count_SHIFT 24 1958 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1959 #define lpfc_init_vfi_hop_count_WORD word4 1960 }; 1961 #define MBX_VFI_IN_USE 0x9F02 1962 1963 1964 struct lpfc_mbx_reg_vfi { 1965 uint32_t word1; 1966 #define lpfc_reg_vfi_upd_SHIFT 29 1967 #define lpfc_reg_vfi_upd_MASK 0x00000001 1968 #define lpfc_reg_vfi_upd_WORD word1 1969 #define lpfc_reg_vfi_vp_SHIFT 28 1970 #define lpfc_reg_vfi_vp_MASK 0x00000001 1971 #define lpfc_reg_vfi_vp_WORD word1 1972 #define lpfc_reg_vfi_vfi_SHIFT 0 1973 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1974 #define lpfc_reg_vfi_vfi_WORD word1 1975 uint32_t word2; 1976 #define lpfc_reg_vfi_vpi_SHIFT 16 1977 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1978 #define lpfc_reg_vfi_vpi_WORD word2 1979 #define lpfc_reg_vfi_fcfi_SHIFT 0 1980 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1981 #define lpfc_reg_vfi_fcfi_WORD word2 1982 uint32_t wwn[2]; 1983 struct ulp_bde64 bde; 1984 uint32_t e_d_tov; 1985 uint32_t r_a_tov; 1986 uint32_t word10; 1987 #define lpfc_reg_vfi_nport_id_SHIFT 0 1988 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1989 #define lpfc_reg_vfi_nport_id_WORD word10 1990 }; 1991 1992 struct lpfc_mbx_init_vpi { 1993 uint32_t word1; 1994 #define lpfc_init_vpi_vfi_SHIFT 16 1995 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1996 #define lpfc_init_vpi_vfi_WORD word1 1997 #define lpfc_init_vpi_vpi_SHIFT 0 1998 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1999 #define lpfc_init_vpi_vpi_WORD word1 2000 }; 2001 2002 struct lpfc_mbx_read_vpi { 2003 uint32_t word1_rsvd; 2004 uint32_t word2; 2005 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2006 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2007 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2008 uint32_t word3_rsvd; 2009 uint32_t word4; 2010 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2011 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2012 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2013 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2014 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2015 #define lpfc_mbx_read_vpi_pb_WORD word4 2016 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2017 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2018 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2019 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2020 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2021 #define lpfc_mbx_read_vpi_ns_WORD word4 2022 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2023 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2024 #define lpfc_mbx_read_vpi_hl_WORD word4 2025 uint32_t word5_rsvd; 2026 uint32_t word6; 2027 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2028 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2029 #define lpfc_mbx_read_vpi_vpi_WORD word6 2030 uint32_t word7; 2031 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2032 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2033 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2034 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2035 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2036 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2037 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2038 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2039 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2040 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2041 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2042 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2043 uint32_t word8; 2044 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2045 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2046 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2047 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2048 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2049 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2050 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2051 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2052 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2053 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2054 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2055 #define lpfc_mbx_read_vpi_vv_WORD word8 2056 }; 2057 2058 struct lpfc_mbx_unreg_vfi { 2059 uint32_t word1_rsvd; 2060 uint32_t word2; 2061 #define lpfc_unreg_vfi_vfi_SHIFT 0 2062 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2063 #define lpfc_unreg_vfi_vfi_WORD word2 2064 }; 2065 2066 struct lpfc_mbx_resume_rpi { 2067 uint32_t word1; 2068 #define lpfc_resume_rpi_index_SHIFT 0 2069 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2070 #define lpfc_resume_rpi_index_WORD word1 2071 #define lpfc_resume_rpi_ii_SHIFT 30 2072 #define lpfc_resume_rpi_ii_MASK 0x00000003 2073 #define lpfc_resume_rpi_ii_WORD word1 2074 #define RESUME_INDEX_RPI 0 2075 #define RESUME_INDEX_VPI 1 2076 #define RESUME_INDEX_VFI 2 2077 #define RESUME_INDEX_FCFI 3 2078 uint32_t event_tag; 2079 }; 2080 2081 #define REG_FCF_INVALID_QID 0xFFFF 2082 struct lpfc_mbx_reg_fcfi { 2083 uint32_t word1; 2084 #define lpfc_reg_fcfi_info_index_SHIFT 0 2085 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2086 #define lpfc_reg_fcfi_info_index_WORD word1 2087 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2088 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2089 #define lpfc_reg_fcfi_fcfi_WORD word1 2090 uint32_t word2; 2091 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2092 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2093 #define lpfc_reg_fcfi_rq_id1_WORD word2 2094 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2095 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2096 #define lpfc_reg_fcfi_rq_id0_WORD word2 2097 uint32_t word3; 2098 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2099 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2100 #define lpfc_reg_fcfi_rq_id3_WORD word3 2101 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2102 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2103 #define lpfc_reg_fcfi_rq_id2_WORD word3 2104 uint32_t word4; 2105 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2106 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2107 #define lpfc_reg_fcfi_type_match0_WORD word4 2108 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2109 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2110 #define lpfc_reg_fcfi_type_mask0_WORD word4 2111 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2112 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2113 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2114 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2115 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2116 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2117 uint32_t word5; 2118 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2119 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2120 #define lpfc_reg_fcfi_type_match1_WORD word5 2121 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2122 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2123 #define lpfc_reg_fcfi_type_mask1_WORD word5 2124 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2125 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2126 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2127 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2128 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2129 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2130 uint32_t word6; 2131 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2132 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2133 #define lpfc_reg_fcfi_type_match2_WORD word6 2134 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2135 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2136 #define lpfc_reg_fcfi_type_mask2_WORD word6 2137 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2138 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2139 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2140 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2141 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2142 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2143 uint32_t word7; 2144 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2145 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2146 #define lpfc_reg_fcfi_type_match3_WORD word7 2147 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2148 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2149 #define lpfc_reg_fcfi_type_mask3_WORD word7 2150 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2151 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2152 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2153 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2154 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2155 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2156 uint32_t word8; 2157 #define lpfc_reg_fcfi_mam_SHIFT 13 2158 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2159 #define lpfc_reg_fcfi_mam_WORD word8 2160 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2161 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2162 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2163 #define lpfc_reg_fcfi_vv_SHIFT 12 2164 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2165 #define lpfc_reg_fcfi_vv_WORD word8 2166 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2167 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2168 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2169 }; 2170 2171 struct lpfc_mbx_unreg_fcfi { 2172 uint32_t word1_rsv; 2173 uint32_t word2; 2174 #define lpfc_unreg_fcfi_SHIFT 0 2175 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2176 #define lpfc_unreg_fcfi_WORD word2 2177 }; 2178 2179 struct lpfc_mbx_read_rev { 2180 uint32_t word1; 2181 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2182 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2183 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2184 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2185 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2186 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2187 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2188 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2189 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2190 #define LPFC_PREDCBX_CEE_MODE 0 2191 #define LPFC_DCBX_CEE_MODE 1 2192 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2193 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2194 #define lpfc_mbx_rd_rev_vpd_WORD word1 2195 uint32_t first_hw_rev; 2196 uint32_t second_hw_rev; 2197 uint32_t word4_rsvd; 2198 uint32_t third_hw_rev; 2199 uint32_t word6; 2200 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2201 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2202 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2203 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2204 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2205 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2206 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2207 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2208 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2209 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2210 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2211 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2212 uint32_t word7_rsvd; 2213 uint32_t fw_id_rev; 2214 uint8_t fw_name[16]; 2215 uint32_t ulp_fw_id_rev; 2216 uint8_t ulp_fw_name[16]; 2217 uint32_t word18_47_rsvd[30]; 2218 uint32_t word48; 2219 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2220 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2221 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2222 uint32_t vpd_paddr_low; 2223 uint32_t vpd_paddr_high; 2224 uint32_t avail_vpd_len; 2225 uint32_t rsvd_52_63[12]; 2226 }; 2227 2228 struct lpfc_mbx_read_config { 2229 uint32_t word1; 2230 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2231 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2232 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2233 uint32_t word2; 2234 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2235 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2236 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2237 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2238 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2239 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2240 #define LPFC_LNK_TYPE_GE 0 2241 #define LPFC_LNK_TYPE_FC 1 2242 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2243 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2244 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2245 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2246 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2247 #define lpfc_mbx_rd_conf_topology_WORD word2 2248 uint32_t rsvd_3; 2249 uint32_t word4; 2250 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2251 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2252 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2253 uint32_t rsvd_5; 2254 uint32_t word6; 2255 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2256 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2257 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2258 uint32_t rsvd_7; 2259 uint32_t rsvd_8; 2260 uint32_t word9; 2261 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2262 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2263 #define lpfc_mbx_rd_conf_lmt_WORD word9 2264 uint32_t rsvd_10; 2265 uint32_t rsvd_11; 2266 uint32_t word12; 2267 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2268 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2269 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2270 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2271 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2272 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2273 uint32_t word13; 2274 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2275 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2276 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2277 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2278 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2279 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2280 uint32_t word14; 2281 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2282 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2283 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2284 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2285 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2286 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2287 uint32_t word15; 2288 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2289 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2290 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2291 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2292 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2293 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2294 uint32_t word16; 2295 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2296 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2297 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2298 uint32_t word17; 2299 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2300 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2301 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2302 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2303 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2304 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2305 uint32_t word18; 2306 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2307 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2308 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2309 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2310 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2311 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2312 }; 2313 2314 struct lpfc_mbx_request_features { 2315 uint32_t word1; 2316 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2317 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2318 #define lpfc_mbx_rq_ftr_qry_WORD word1 2319 uint32_t word2; 2320 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2321 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2322 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2323 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2324 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2325 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2326 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2327 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2328 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2329 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2330 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2331 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2332 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2333 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2334 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2335 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2336 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2337 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2338 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2339 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2340 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2341 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2342 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2343 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2344 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2345 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2346 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2347 uint32_t word3; 2348 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2349 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2350 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2351 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2352 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2353 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2354 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2355 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2356 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2357 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2358 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2359 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2360 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2361 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2362 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2363 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2364 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2365 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2366 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2367 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2368 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2369 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2370 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2371 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2372 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2373 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2374 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2375 }; 2376 2377 struct lpfc_mbx_supp_pages { 2378 uint32_t word1; 2379 #define qs_SHIFT 0 2380 #define qs_MASK 0x00000001 2381 #define qs_WORD word1 2382 #define wr_SHIFT 1 2383 #define wr_MASK 0x00000001 2384 #define wr_WORD word1 2385 #define pf_SHIFT 8 2386 #define pf_MASK 0x000000ff 2387 #define pf_WORD word1 2388 #define cpn_SHIFT 16 2389 #define cpn_MASK 0x000000ff 2390 #define cpn_WORD word1 2391 uint32_t word2; 2392 #define list_offset_SHIFT 0 2393 #define list_offset_MASK 0x000000ff 2394 #define list_offset_WORD word2 2395 #define next_offset_SHIFT 8 2396 #define next_offset_MASK 0x000000ff 2397 #define next_offset_WORD word2 2398 #define elem_cnt_SHIFT 16 2399 #define elem_cnt_MASK 0x000000ff 2400 #define elem_cnt_WORD word2 2401 uint32_t word3; 2402 #define pn_0_SHIFT 24 2403 #define pn_0_MASK 0x000000ff 2404 #define pn_0_WORD word3 2405 #define pn_1_SHIFT 16 2406 #define pn_1_MASK 0x000000ff 2407 #define pn_1_WORD word3 2408 #define pn_2_SHIFT 8 2409 #define pn_2_MASK 0x000000ff 2410 #define pn_2_WORD word3 2411 #define pn_3_SHIFT 0 2412 #define pn_3_MASK 0x000000ff 2413 #define pn_3_WORD word3 2414 uint32_t word4; 2415 #define pn_4_SHIFT 24 2416 #define pn_4_MASK 0x000000ff 2417 #define pn_4_WORD word4 2418 #define pn_5_SHIFT 16 2419 #define pn_5_MASK 0x000000ff 2420 #define pn_5_WORD word4 2421 #define pn_6_SHIFT 8 2422 #define pn_6_MASK 0x000000ff 2423 #define pn_6_WORD word4 2424 #define pn_7_SHIFT 0 2425 #define pn_7_MASK 0x000000ff 2426 #define pn_7_WORD word4 2427 uint32_t rsvd[27]; 2428 #define LPFC_SUPP_PAGES 0 2429 #define LPFC_BLOCK_GUARD_PROFILES 1 2430 #define LPFC_SLI4_PARAMETERS 2 2431 }; 2432 2433 struct lpfc_mbx_pc_sli4_params { 2434 uint32_t word1; 2435 #define qs_SHIFT 0 2436 #define qs_MASK 0x00000001 2437 #define qs_WORD word1 2438 #define wr_SHIFT 1 2439 #define wr_MASK 0x00000001 2440 #define wr_WORD word1 2441 #define pf_SHIFT 8 2442 #define pf_MASK 0x000000ff 2443 #define pf_WORD word1 2444 #define cpn_SHIFT 16 2445 #define cpn_MASK 0x000000ff 2446 #define cpn_WORD word1 2447 uint32_t word2; 2448 #define if_type_SHIFT 0 2449 #define if_type_MASK 0x00000007 2450 #define if_type_WORD word2 2451 #define sli_rev_SHIFT 4 2452 #define sli_rev_MASK 0x0000000f 2453 #define sli_rev_WORD word2 2454 #define sli_family_SHIFT 8 2455 #define sli_family_MASK 0x000000ff 2456 #define sli_family_WORD word2 2457 #define featurelevel_1_SHIFT 16 2458 #define featurelevel_1_MASK 0x000000ff 2459 #define featurelevel_1_WORD word2 2460 #define featurelevel_2_SHIFT 24 2461 #define featurelevel_2_MASK 0x0000001f 2462 #define featurelevel_2_WORD word2 2463 uint32_t word3; 2464 #define fcoe_SHIFT 0 2465 #define fcoe_MASK 0x00000001 2466 #define fcoe_WORD word3 2467 #define fc_SHIFT 1 2468 #define fc_MASK 0x00000001 2469 #define fc_WORD word3 2470 #define nic_SHIFT 2 2471 #define nic_MASK 0x00000001 2472 #define nic_WORD word3 2473 #define iscsi_SHIFT 3 2474 #define iscsi_MASK 0x00000001 2475 #define iscsi_WORD word3 2476 #define rdma_SHIFT 4 2477 #define rdma_MASK 0x00000001 2478 #define rdma_WORD word3 2479 uint32_t sge_supp_len; 2480 #define SLI4_PAGE_SIZE 4096 2481 uint32_t word5; 2482 #define if_page_sz_SHIFT 0 2483 #define if_page_sz_MASK 0x0000ffff 2484 #define if_page_sz_WORD word5 2485 #define loopbk_scope_SHIFT 24 2486 #define loopbk_scope_MASK 0x0000000f 2487 #define loopbk_scope_WORD word5 2488 #define rq_db_window_SHIFT 28 2489 #define rq_db_window_MASK 0x0000000f 2490 #define rq_db_window_WORD word5 2491 uint32_t word6; 2492 #define eq_pages_SHIFT 0 2493 #define eq_pages_MASK 0x0000000f 2494 #define eq_pages_WORD word6 2495 #define eqe_size_SHIFT 8 2496 #define eqe_size_MASK 0x000000ff 2497 #define eqe_size_WORD word6 2498 uint32_t word7; 2499 #define cq_pages_SHIFT 0 2500 #define cq_pages_MASK 0x0000000f 2501 #define cq_pages_WORD word7 2502 #define cqe_size_SHIFT 8 2503 #define cqe_size_MASK 0x000000ff 2504 #define cqe_size_WORD word7 2505 uint32_t word8; 2506 #define mq_pages_SHIFT 0 2507 #define mq_pages_MASK 0x0000000f 2508 #define mq_pages_WORD word8 2509 #define mqe_size_SHIFT 8 2510 #define mqe_size_MASK 0x000000ff 2511 #define mqe_size_WORD word8 2512 #define mq_elem_cnt_SHIFT 16 2513 #define mq_elem_cnt_MASK 0x000000ff 2514 #define mq_elem_cnt_WORD word8 2515 uint32_t word9; 2516 #define wq_pages_SHIFT 0 2517 #define wq_pages_MASK 0x0000ffff 2518 #define wq_pages_WORD word9 2519 #define wqe_size_SHIFT 8 2520 #define wqe_size_MASK 0x000000ff 2521 #define wqe_size_WORD word9 2522 uint32_t word10; 2523 #define rq_pages_SHIFT 0 2524 #define rq_pages_MASK 0x0000ffff 2525 #define rq_pages_WORD word10 2526 #define rqe_size_SHIFT 8 2527 #define rqe_size_MASK 0x000000ff 2528 #define rqe_size_WORD word10 2529 uint32_t word11; 2530 #define hdr_pages_SHIFT 0 2531 #define hdr_pages_MASK 0x0000000f 2532 #define hdr_pages_WORD word11 2533 #define hdr_size_SHIFT 8 2534 #define hdr_size_MASK 0x0000000f 2535 #define hdr_size_WORD word11 2536 #define hdr_pp_align_SHIFT 16 2537 #define hdr_pp_align_MASK 0x0000ffff 2538 #define hdr_pp_align_WORD word11 2539 uint32_t word12; 2540 #define sgl_pages_SHIFT 0 2541 #define sgl_pages_MASK 0x0000000f 2542 #define sgl_pages_WORD word12 2543 #define sgl_pp_align_SHIFT 16 2544 #define sgl_pp_align_MASK 0x0000ffff 2545 #define sgl_pp_align_WORD word12 2546 uint32_t rsvd_13_63[51]; 2547 }; 2548 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2549 &(~((SLI4_PAGE_SIZE)-1))) 2550 2551 struct lpfc_sli4_parameters { 2552 uint32_t word0; 2553 #define cfg_prot_type_SHIFT 0 2554 #define cfg_prot_type_MASK 0x000000FF 2555 #define cfg_prot_type_WORD word0 2556 uint32_t word1; 2557 #define cfg_ft_SHIFT 0 2558 #define cfg_ft_MASK 0x00000001 2559 #define cfg_ft_WORD word1 2560 #define cfg_sli_rev_SHIFT 4 2561 #define cfg_sli_rev_MASK 0x0000000f 2562 #define cfg_sli_rev_WORD word1 2563 #define cfg_sli_family_SHIFT 8 2564 #define cfg_sli_family_MASK 0x0000000f 2565 #define cfg_sli_family_WORD word1 2566 #define cfg_if_type_SHIFT 12 2567 #define cfg_if_type_MASK 0x0000000f 2568 #define cfg_if_type_WORD word1 2569 #define cfg_sli_hint_1_SHIFT 16 2570 #define cfg_sli_hint_1_MASK 0x000000ff 2571 #define cfg_sli_hint_1_WORD word1 2572 #define cfg_sli_hint_2_SHIFT 24 2573 #define cfg_sli_hint_2_MASK 0x0000001f 2574 #define cfg_sli_hint_2_WORD word1 2575 uint32_t word2; 2576 uint32_t word3; 2577 uint32_t word4; 2578 #define cfg_cqv_SHIFT 14 2579 #define cfg_cqv_MASK 0x00000003 2580 #define cfg_cqv_WORD word4 2581 uint32_t word5; 2582 uint32_t word6; 2583 #define cfg_mqv_SHIFT 14 2584 #define cfg_mqv_MASK 0x00000003 2585 #define cfg_mqv_WORD word6 2586 uint32_t word7; 2587 uint32_t word8; 2588 #define cfg_wqv_SHIFT 14 2589 #define cfg_wqv_MASK 0x00000003 2590 #define cfg_wqv_WORD word8 2591 uint32_t word9; 2592 uint32_t word10; 2593 #define cfg_rqv_SHIFT 14 2594 #define cfg_rqv_MASK 0x00000003 2595 #define cfg_rqv_WORD word10 2596 uint32_t word11; 2597 #define cfg_rq_db_window_SHIFT 28 2598 #define cfg_rq_db_window_MASK 0x0000000f 2599 #define cfg_rq_db_window_WORD word11 2600 uint32_t word12; 2601 #define cfg_fcoe_SHIFT 0 2602 #define cfg_fcoe_MASK 0x00000001 2603 #define cfg_fcoe_WORD word12 2604 #define cfg_ext_SHIFT 1 2605 #define cfg_ext_MASK 0x00000001 2606 #define cfg_ext_WORD word12 2607 #define cfg_hdrr_SHIFT 2 2608 #define cfg_hdrr_MASK 0x00000001 2609 #define cfg_hdrr_WORD word12 2610 #define cfg_phwq_SHIFT 15 2611 #define cfg_phwq_MASK 0x00000001 2612 #define cfg_phwq_WORD word12 2613 #define cfg_loopbk_scope_SHIFT 28 2614 #define cfg_loopbk_scope_MASK 0x0000000f 2615 #define cfg_loopbk_scope_WORD word12 2616 uint32_t sge_supp_len; 2617 uint32_t word14; 2618 #define cfg_sgl_page_cnt_SHIFT 0 2619 #define cfg_sgl_page_cnt_MASK 0x0000000f 2620 #define cfg_sgl_page_cnt_WORD word14 2621 #define cfg_sgl_page_size_SHIFT 8 2622 #define cfg_sgl_page_size_MASK 0x000000ff 2623 #define cfg_sgl_page_size_WORD word14 2624 #define cfg_sgl_pp_align_SHIFT 16 2625 #define cfg_sgl_pp_align_MASK 0x000000ff 2626 #define cfg_sgl_pp_align_WORD word14 2627 uint32_t word15; 2628 uint32_t word16; 2629 uint32_t word17; 2630 uint32_t word18; 2631 uint32_t word19; 2632 }; 2633 2634 struct lpfc_mbx_get_sli4_parameters { 2635 struct mbox_header header; 2636 struct lpfc_sli4_parameters sli4_parameters; 2637 }; 2638 2639 struct lpfc_rscr_desc_generic { 2640 #define LPFC_RSRC_DESC_WSIZE 22 2641 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2642 }; 2643 2644 struct lpfc_rsrc_desc_pcie { 2645 uint32_t word0; 2646 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2647 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2648 #define lpfc_rsrc_desc_pcie_type_WORD word0 2649 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2650 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 2651 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 2652 #define lpfc_rsrc_desc_pcie_length_WORD word0 2653 uint32_t word1; 2654 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2655 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2656 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2657 uint32_t reserved; 2658 uint32_t word3; 2659 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2660 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2661 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2662 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2663 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2664 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2665 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2666 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2667 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2668 uint32_t word4; 2669 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2670 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2671 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2672 }; 2673 2674 struct lpfc_rsrc_desc_fcfcoe { 2675 uint32_t word0; 2676 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2677 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2678 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2679 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2680 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 2681 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 2682 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 2683 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 2684 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 2685 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 2686 uint32_t word1; 2687 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2688 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2689 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2690 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2691 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2692 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2693 uint32_t word2; 2694 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2695 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2696 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2697 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2698 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2699 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2700 uint32_t word3; 2701 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2702 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2703 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2704 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2705 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2706 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2707 uint32_t word4; 2708 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2709 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2710 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2711 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2712 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2713 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2714 uint32_t word5; 2715 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2716 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2717 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2718 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2719 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2720 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2721 uint32_t word6; 2722 uint32_t word7; 2723 uint32_t word8; 2724 uint32_t word9; 2725 uint32_t word10; 2726 uint32_t word11; 2727 uint32_t word12; 2728 uint32_t word13; 2729 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2730 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2731 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2732 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2733 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2734 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2735 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2736 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2737 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2738 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2739 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2740 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2741 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 2742 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 2743 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 2744 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 2745 uint32_t bw_min; 2746 uint32_t bw_max; 2747 uint32_t iops_min; 2748 uint32_t iops_max; 2749 uint32_t reserved[4]; 2750 }; 2751 2752 struct lpfc_func_cfg { 2753 #define LPFC_RSRC_DESC_MAX_NUM 2 2754 uint32_t rsrc_desc_count; 2755 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2756 }; 2757 2758 struct lpfc_mbx_get_func_cfg { 2759 struct mbox_header header; 2760 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2761 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2762 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2763 struct lpfc_func_cfg func_cfg; 2764 }; 2765 2766 struct lpfc_prof_cfg { 2767 #define LPFC_RSRC_DESC_MAX_NUM 2 2768 uint32_t rsrc_desc_count; 2769 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2770 }; 2771 2772 struct lpfc_mbx_get_prof_cfg { 2773 struct mbox_header header; 2774 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2775 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2776 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2777 union { 2778 struct { 2779 uint32_t word10; 2780 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 2781 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 2782 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 2783 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 2784 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 2785 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 2786 } request; 2787 struct { 2788 struct lpfc_prof_cfg prof_cfg; 2789 } response; 2790 } u; 2791 }; 2792 2793 struct lpfc_controller_attribute { 2794 uint32_t version_string[8]; 2795 uint32_t manufacturer_name[8]; 2796 uint32_t supported_modes; 2797 uint32_t word17; 2798 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 2799 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 2800 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 2801 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 2802 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 2803 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 2804 uint32_t mbx_da_struct_ver; 2805 uint32_t ep_fw_da_struct_ver; 2806 uint32_t ncsi_ver_str[3]; 2807 uint32_t dflt_ext_timeout; 2808 uint32_t model_number[8]; 2809 uint32_t description[16]; 2810 uint32_t serial_number[8]; 2811 uint32_t ip_ver_str[8]; 2812 uint32_t fw_ver_str[8]; 2813 uint32_t bios_ver_str[8]; 2814 uint32_t redboot_ver_str[8]; 2815 uint32_t driver_ver_str[8]; 2816 uint32_t flash_fw_ver_str[8]; 2817 uint32_t functionality; 2818 uint32_t word105; 2819 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 2820 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 2821 #define lpfc_cntl_attr_max_cbd_len_WORD word105 2822 #define lpfc_cntl_attr_asic_rev_SHIFT 16 2823 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 2824 #define lpfc_cntl_attr_asic_rev_WORD word105 2825 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 2826 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 2827 #define lpfc_cntl_attr_gen_guid0_WORD word105 2828 uint32_t gen_guid1_12[3]; 2829 uint32_t word109; 2830 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 2831 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 2832 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 2833 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 2834 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 2835 #define lpfc_cntl_attr_gen_guid15_WORD word109 2836 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 2837 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 2838 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 2839 uint32_t word110; 2840 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 2841 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 2842 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 2843 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 2844 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 2845 #define lpfc_cntl_attr_multi_func_dev_WORD word110 2846 uint32_t word111; 2847 #define lpfc_cntl_attr_cache_valid_SHIFT 0 2848 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 2849 #define lpfc_cntl_attr_cache_valid_WORD word111 2850 #define lpfc_cntl_attr_hba_status_SHIFT 8 2851 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 2852 #define lpfc_cntl_attr_hba_status_WORD word111 2853 #define lpfc_cntl_attr_max_domain_SHIFT 16 2854 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 2855 #define lpfc_cntl_attr_max_domain_WORD word111 2856 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 2857 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 2858 #define lpfc_cntl_attr_lnk_numb_WORD word111 2859 #define lpfc_cntl_attr_lnk_type_SHIFT 30 2860 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 2861 #define lpfc_cntl_attr_lnk_type_WORD word111 2862 uint32_t fw_post_status; 2863 uint32_t hba_mtu[8]; 2864 uint32_t word121; 2865 uint32_t reserved1[3]; 2866 uint32_t word125; 2867 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 2868 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 2869 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 2870 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 2871 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 2872 #define lpfc_cntl_attr_pci_device_id_WORD word125 2873 uint32_t word126; 2874 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 2875 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 2876 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 2877 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 2878 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 2879 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 2880 uint32_t word127; 2881 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 2882 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 2883 #define lpfc_cntl_attr_pci_bus_num_WORD word127 2884 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 2885 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 2886 #define lpfc_cntl_attr_pci_dev_num_WORD word127 2887 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 2888 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 2889 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 2890 #define lpfc_cntl_attr_inf_type_SHIFT 24 2891 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 2892 #define lpfc_cntl_attr_inf_type_WORD word127 2893 uint32_t unique_id[2]; 2894 uint32_t word130; 2895 #define lpfc_cntl_attr_num_netfil_SHIFT 0 2896 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 2897 #define lpfc_cntl_attr_num_netfil_WORD word130 2898 uint32_t reserved2[4]; 2899 }; 2900 2901 struct lpfc_mbx_get_cntl_attributes { 2902 union lpfc_sli4_cfg_shdr cfg_shdr; 2903 struct lpfc_controller_attribute cntl_attr; 2904 }; 2905 2906 struct lpfc_mbx_get_port_name { 2907 struct mbox_header header; 2908 union { 2909 struct { 2910 uint32_t word4; 2911 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 2912 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 2913 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 2914 } request; 2915 struct { 2916 uint32_t word4; 2917 #define lpfc_mbx_get_port_name_name0_SHIFT 0 2918 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 2919 #define lpfc_mbx_get_port_name_name0_WORD word4 2920 #define lpfc_mbx_get_port_name_name1_SHIFT 8 2921 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 2922 #define lpfc_mbx_get_port_name_name1_WORD word4 2923 #define lpfc_mbx_get_port_name_name2_SHIFT 16 2924 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 2925 #define lpfc_mbx_get_port_name_name2_WORD word4 2926 #define lpfc_mbx_get_port_name_name3_SHIFT 24 2927 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 2928 #define lpfc_mbx_get_port_name_name3_WORD word4 2929 #define LPFC_LINK_NUMBER_0 0 2930 #define LPFC_LINK_NUMBER_1 1 2931 #define LPFC_LINK_NUMBER_2 2 2932 #define LPFC_LINK_NUMBER_3 3 2933 } response; 2934 } u; 2935 }; 2936 2937 /* Mailbox Completion Queue Error Messages */ 2938 #define MB_CQE_STATUS_SUCCESS 0x0 2939 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2940 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2941 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2942 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2943 #define MB_CQE_STATUS_DMA_FAILED 0x5 2944 2945 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 2946 struct lpfc_mbx_wr_object { 2947 struct mbox_header header; 2948 union { 2949 struct { 2950 uint32_t word4; 2951 #define lpfc_wr_object_eof_SHIFT 31 2952 #define lpfc_wr_object_eof_MASK 0x00000001 2953 #define lpfc_wr_object_eof_WORD word4 2954 #define lpfc_wr_object_write_length_SHIFT 0 2955 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 2956 #define lpfc_wr_object_write_length_WORD word4 2957 uint32_t write_offset; 2958 uint32_t object_name[26]; 2959 uint32_t bde_count; 2960 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 2961 } request; 2962 struct { 2963 uint32_t actual_write_length; 2964 } response; 2965 } u; 2966 }; 2967 2968 /* mailbox queue entry structure */ 2969 struct lpfc_mqe { 2970 uint32_t word0; 2971 #define lpfc_mqe_status_SHIFT 16 2972 #define lpfc_mqe_status_MASK 0x0000FFFF 2973 #define lpfc_mqe_status_WORD word0 2974 #define lpfc_mqe_command_SHIFT 8 2975 #define lpfc_mqe_command_MASK 0x000000FF 2976 #define lpfc_mqe_command_WORD word0 2977 union { 2978 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2979 /* sli4 mailbox commands */ 2980 struct lpfc_mbx_sli4_config sli4_config; 2981 struct lpfc_mbx_init_vfi init_vfi; 2982 struct lpfc_mbx_reg_vfi reg_vfi; 2983 struct lpfc_mbx_reg_vfi unreg_vfi; 2984 struct lpfc_mbx_init_vpi init_vpi; 2985 struct lpfc_mbx_resume_rpi resume_rpi; 2986 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2987 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2988 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2989 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2990 struct lpfc_mbx_reg_fcfi reg_fcfi; 2991 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2992 struct lpfc_mbx_mq_create mq_create; 2993 struct lpfc_mbx_mq_create_ext mq_create_ext; 2994 struct lpfc_mbx_eq_create eq_create; 2995 struct lpfc_mbx_modify_eq_delay eq_delay; 2996 struct lpfc_mbx_cq_create cq_create; 2997 struct lpfc_mbx_wq_create wq_create; 2998 struct lpfc_mbx_rq_create rq_create; 2999 struct lpfc_mbx_mq_destroy mq_destroy; 3000 struct lpfc_mbx_eq_destroy eq_destroy; 3001 struct lpfc_mbx_cq_destroy cq_destroy; 3002 struct lpfc_mbx_wq_destroy wq_destroy; 3003 struct lpfc_mbx_rq_destroy rq_destroy; 3004 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3005 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3006 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3007 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3008 struct lpfc_mbx_nembed_cmd nembed_cmd; 3009 struct lpfc_mbx_read_rev read_rev; 3010 struct lpfc_mbx_read_vpi read_vpi; 3011 struct lpfc_mbx_read_config rd_config; 3012 struct lpfc_mbx_request_features req_ftrs; 3013 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3014 struct lpfc_mbx_query_fw_config query_fw_cfg; 3015 struct lpfc_mbx_supp_pages supp_pages; 3016 struct lpfc_mbx_pc_sli4_params sli4_params; 3017 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3018 struct lpfc_mbx_set_link_diag_state link_diag_state; 3019 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3020 struct lpfc_mbx_run_link_diag_test link_diag_test; 3021 struct lpfc_mbx_get_func_cfg get_func_cfg; 3022 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3023 struct lpfc_mbx_wr_object wr_object; 3024 struct lpfc_mbx_get_port_name get_port_name; 3025 struct lpfc_mbx_nop nop; 3026 } un; 3027 }; 3028 3029 struct lpfc_mcqe { 3030 uint32_t word0; 3031 #define lpfc_mcqe_status_SHIFT 0 3032 #define lpfc_mcqe_status_MASK 0x0000FFFF 3033 #define lpfc_mcqe_status_WORD word0 3034 #define lpfc_mcqe_ext_status_SHIFT 16 3035 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3036 #define lpfc_mcqe_ext_status_WORD word0 3037 uint32_t mcqe_tag0; 3038 uint32_t mcqe_tag1; 3039 uint32_t trailer; 3040 #define lpfc_trailer_valid_SHIFT 31 3041 #define lpfc_trailer_valid_MASK 0x00000001 3042 #define lpfc_trailer_valid_WORD trailer 3043 #define lpfc_trailer_async_SHIFT 30 3044 #define lpfc_trailer_async_MASK 0x00000001 3045 #define lpfc_trailer_async_WORD trailer 3046 #define lpfc_trailer_hpi_SHIFT 29 3047 #define lpfc_trailer_hpi_MASK 0x00000001 3048 #define lpfc_trailer_hpi_WORD trailer 3049 #define lpfc_trailer_completed_SHIFT 28 3050 #define lpfc_trailer_completed_MASK 0x00000001 3051 #define lpfc_trailer_completed_WORD trailer 3052 #define lpfc_trailer_consumed_SHIFT 27 3053 #define lpfc_trailer_consumed_MASK 0x00000001 3054 #define lpfc_trailer_consumed_WORD trailer 3055 #define lpfc_trailer_type_SHIFT 16 3056 #define lpfc_trailer_type_MASK 0x000000FF 3057 #define lpfc_trailer_type_WORD trailer 3058 #define lpfc_trailer_code_SHIFT 8 3059 #define lpfc_trailer_code_MASK 0x000000FF 3060 #define lpfc_trailer_code_WORD trailer 3061 #define LPFC_TRAILER_CODE_LINK 0x1 3062 #define LPFC_TRAILER_CODE_FCOE 0x2 3063 #define LPFC_TRAILER_CODE_DCBX 0x3 3064 #define LPFC_TRAILER_CODE_GRP5 0x5 3065 #define LPFC_TRAILER_CODE_FC 0x10 3066 #define LPFC_TRAILER_CODE_SLI 0x11 3067 }; 3068 3069 struct lpfc_acqe_link { 3070 uint32_t word0; 3071 #define lpfc_acqe_link_speed_SHIFT 24 3072 #define lpfc_acqe_link_speed_MASK 0x000000FF 3073 #define lpfc_acqe_link_speed_WORD word0 3074 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3075 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3076 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3077 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3078 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3079 #define lpfc_acqe_link_duplex_SHIFT 16 3080 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3081 #define lpfc_acqe_link_duplex_WORD word0 3082 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3083 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3084 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3085 #define lpfc_acqe_link_status_SHIFT 8 3086 #define lpfc_acqe_link_status_MASK 0x000000FF 3087 #define lpfc_acqe_link_status_WORD word0 3088 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3089 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3090 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3091 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3092 #define lpfc_acqe_link_type_SHIFT 6 3093 #define lpfc_acqe_link_type_MASK 0x00000003 3094 #define lpfc_acqe_link_type_WORD word0 3095 #define lpfc_acqe_link_number_SHIFT 0 3096 #define lpfc_acqe_link_number_MASK 0x0000003F 3097 #define lpfc_acqe_link_number_WORD word0 3098 uint32_t word1; 3099 #define lpfc_acqe_link_fault_SHIFT 0 3100 #define lpfc_acqe_link_fault_MASK 0x000000FF 3101 #define lpfc_acqe_link_fault_WORD word1 3102 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3103 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3104 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3105 #define lpfc_acqe_logical_link_speed_SHIFT 16 3106 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3107 #define lpfc_acqe_logical_link_speed_WORD word1 3108 uint32_t event_tag; 3109 uint32_t trailer; 3110 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3111 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3112 }; 3113 3114 struct lpfc_acqe_fip { 3115 uint32_t index; 3116 uint32_t word1; 3117 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3118 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3119 #define lpfc_acqe_fip_fcf_count_WORD word1 3120 #define lpfc_acqe_fip_event_type_SHIFT 16 3121 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3122 #define lpfc_acqe_fip_event_type_WORD word1 3123 uint32_t event_tag; 3124 uint32_t trailer; 3125 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3126 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3127 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3128 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3129 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3130 }; 3131 3132 struct lpfc_acqe_dcbx { 3133 uint32_t tlv_ttl; 3134 uint32_t reserved; 3135 uint32_t event_tag; 3136 uint32_t trailer; 3137 }; 3138 3139 struct lpfc_acqe_grp5 { 3140 uint32_t word0; 3141 #define lpfc_acqe_grp5_type_SHIFT 6 3142 #define lpfc_acqe_grp5_type_MASK 0x00000003 3143 #define lpfc_acqe_grp5_type_WORD word0 3144 #define lpfc_acqe_grp5_number_SHIFT 0 3145 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3146 #define lpfc_acqe_grp5_number_WORD word0 3147 uint32_t word1; 3148 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3149 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3150 #define lpfc_acqe_grp5_llink_spd_WORD word1 3151 uint32_t event_tag; 3152 uint32_t trailer; 3153 }; 3154 3155 struct lpfc_acqe_fc_la { 3156 uint32_t word0; 3157 #define lpfc_acqe_fc_la_speed_SHIFT 24 3158 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3159 #define lpfc_acqe_fc_la_speed_WORD word0 3160 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 3161 #define LPFC_FC_LA_SPEED_1G 0x1 3162 #define LPFC_FC_LA_SPEED_2G 0x2 3163 #define LPFC_FC_LA_SPEED_4G 0x4 3164 #define LPFC_FC_LA_SPEED_8G 0x8 3165 #define LPFC_FC_LA_SPEED_10G 0xA 3166 #define LPFC_FC_LA_SPEED_16G 0x10 3167 #define lpfc_acqe_fc_la_topology_SHIFT 16 3168 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3169 #define lpfc_acqe_fc_la_topology_WORD word0 3170 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3171 #define LPFC_FC_LA_TOP_P2P 0x1 3172 #define LPFC_FC_LA_TOP_FCAL 0x2 3173 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3174 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3175 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3176 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3177 #define lpfc_acqe_fc_la_att_type_WORD word0 3178 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3179 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3180 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3181 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3182 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3183 #define lpfc_acqe_fc_la_port_type_WORD word0 3184 #define LPFC_LINK_TYPE_ETHERNET 0x0 3185 #define LPFC_LINK_TYPE_FC 0x1 3186 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3187 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3188 #define lpfc_acqe_fc_la_port_number_WORD word0 3189 uint32_t word1; 3190 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3191 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3192 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3193 #define lpfc_acqe_fc_la_fault_SHIFT 0 3194 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3195 #define lpfc_acqe_fc_la_fault_WORD word1 3196 #define LPFC_FC_LA_FAULT_NONE 0x0 3197 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3198 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3199 uint32_t event_tag; 3200 uint32_t trailer; 3201 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3202 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3203 }; 3204 3205 struct lpfc_acqe_misconfigured_event { 3206 struct { 3207 uint32_t word0; 3208 #define lpfc_sli_misconfigured_port0_SHIFT 0 3209 #define lpfc_sli_misconfigured_port0_MASK 0x000000FF 3210 #define lpfc_sli_misconfigured_port0_WORD word0 3211 #define lpfc_sli_misconfigured_port1_SHIFT 8 3212 #define lpfc_sli_misconfigured_port1_MASK 0x000000FF 3213 #define lpfc_sli_misconfigured_port1_WORD word0 3214 #define lpfc_sli_misconfigured_port2_SHIFT 16 3215 #define lpfc_sli_misconfigured_port2_MASK 0x000000FF 3216 #define lpfc_sli_misconfigured_port2_WORD word0 3217 #define lpfc_sli_misconfigured_port3_SHIFT 24 3218 #define lpfc_sli_misconfigured_port3_MASK 0x000000FF 3219 #define lpfc_sli_misconfigured_port3_WORD word0 3220 } theEvent; 3221 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 3222 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 3223 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 3224 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 3225 }; 3226 3227 struct lpfc_acqe_sli { 3228 uint32_t event_data1; 3229 uint32_t event_data2; 3230 uint32_t reserved; 3231 uint32_t trailer; 3232 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3233 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3234 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3235 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3236 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3237 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 3238 }; 3239 3240 /* 3241 * Define the bootstrap mailbox (bmbx) region used to communicate 3242 * mailbox command between the host and port. The mailbox consists 3243 * of a payload area of 256 bytes and a completion queue of length 3244 * 16 bytes. 3245 */ 3246 struct lpfc_bmbx_create { 3247 struct lpfc_mqe mqe; 3248 struct lpfc_mcqe mcqe; 3249 }; 3250 3251 #define SGL_ALIGN_SZ 64 3252 #define SGL_PAGE_SIZE 4096 3253 /* align SGL addr on a size boundary - adjust address up */ 3254 #define NO_XRI 0xffff 3255 3256 struct wqe_common { 3257 uint32_t word6; 3258 #define wqe_xri_tag_SHIFT 0 3259 #define wqe_xri_tag_MASK 0x0000FFFF 3260 #define wqe_xri_tag_WORD word6 3261 #define wqe_ctxt_tag_SHIFT 16 3262 #define wqe_ctxt_tag_MASK 0x0000FFFF 3263 #define wqe_ctxt_tag_WORD word6 3264 uint32_t word7; 3265 #define wqe_dif_SHIFT 0 3266 #define wqe_dif_MASK 0x00000003 3267 #define wqe_dif_WORD word7 3268 #define LPFC_WQE_DIF_PASSTHRU 1 3269 #define LPFC_WQE_DIF_STRIP 2 3270 #define LPFC_WQE_DIF_INSERT 3 3271 #define wqe_ct_SHIFT 2 3272 #define wqe_ct_MASK 0x00000003 3273 #define wqe_ct_WORD word7 3274 #define wqe_status_SHIFT 4 3275 #define wqe_status_MASK 0x0000000f 3276 #define wqe_status_WORD word7 3277 #define wqe_cmnd_SHIFT 8 3278 #define wqe_cmnd_MASK 0x000000ff 3279 #define wqe_cmnd_WORD word7 3280 #define wqe_class_SHIFT 16 3281 #define wqe_class_MASK 0x00000007 3282 #define wqe_class_WORD word7 3283 #define wqe_ar_SHIFT 19 3284 #define wqe_ar_MASK 0x00000001 3285 #define wqe_ar_WORD word7 3286 #define wqe_ag_SHIFT wqe_ar_SHIFT 3287 #define wqe_ag_MASK wqe_ar_MASK 3288 #define wqe_ag_WORD wqe_ar_WORD 3289 #define wqe_pu_SHIFT 20 3290 #define wqe_pu_MASK 0x00000003 3291 #define wqe_pu_WORD word7 3292 #define wqe_erp_SHIFT 22 3293 #define wqe_erp_MASK 0x00000001 3294 #define wqe_erp_WORD word7 3295 #define wqe_conf_SHIFT wqe_erp_SHIFT 3296 #define wqe_conf_MASK wqe_erp_MASK 3297 #define wqe_conf_WORD wqe_erp_WORD 3298 #define wqe_lnk_SHIFT 23 3299 #define wqe_lnk_MASK 0x00000001 3300 #define wqe_lnk_WORD word7 3301 #define wqe_tmo_SHIFT 24 3302 #define wqe_tmo_MASK 0x000000ff 3303 #define wqe_tmo_WORD word7 3304 uint32_t abort_tag; /* word 8 in WQE */ 3305 uint32_t word9; 3306 #define wqe_reqtag_SHIFT 0 3307 #define wqe_reqtag_MASK 0x0000FFFF 3308 #define wqe_reqtag_WORD word9 3309 #define wqe_temp_rpi_SHIFT 16 3310 #define wqe_temp_rpi_MASK 0x0000FFFF 3311 #define wqe_temp_rpi_WORD word9 3312 #define wqe_rcvoxid_SHIFT 16 3313 #define wqe_rcvoxid_MASK 0x0000FFFF 3314 #define wqe_rcvoxid_WORD word9 3315 uint32_t word10; 3316 #define wqe_ebde_cnt_SHIFT 0 3317 #define wqe_ebde_cnt_MASK 0x0000000f 3318 #define wqe_ebde_cnt_WORD word10 3319 #define wqe_lenloc_SHIFT 7 3320 #define wqe_lenloc_MASK 0x00000003 3321 #define wqe_lenloc_WORD word10 3322 #define LPFC_WQE_LENLOC_NONE 0 3323 #define LPFC_WQE_LENLOC_WORD3 1 3324 #define LPFC_WQE_LENLOC_WORD12 2 3325 #define LPFC_WQE_LENLOC_WORD4 3 3326 #define wqe_qosd_SHIFT 9 3327 #define wqe_qosd_MASK 0x00000001 3328 #define wqe_qosd_WORD word10 3329 #define wqe_xbl_SHIFT 11 3330 #define wqe_xbl_MASK 0x00000001 3331 #define wqe_xbl_WORD word10 3332 #define wqe_iod_SHIFT 13 3333 #define wqe_iod_MASK 0x00000001 3334 #define wqe_iod_WORD word10 3335 #define LPFC_WQE_IOD_WRITE 0 3336 #define LPFC_WQE_IOD_READ 1 3337 #define wqe_dbde_SHIFT 14 3338 #define wqe_dbde_MASK 0x00000001 3339 #define wqe_dbde_WORD word10 3340 #define wqe_wqes_SHIFT 15 3341 #define wqe_wqes_MASK 0x00000001 3342 #define wqe_wqes_WORD word10 3343 /* Note that this field overlaps above fields */ 3344 #define wqe_wqid_SHIFT 1 3345 #define wqe_wqid_MASK 0x00007fff 3346 #define wqe_wqid_WORD word10 3347 #define wqe_pri_SHIFT 16 3348 #define wqe_pri_MASK 0x00000007 3349 #define wqe_pri_WORD word10 3350 #define wqe_pv_SHIFT 19 3351 #define wqe_pv_MASK 0x00000001 3352 #define wqe_pv_WORD word10 3353 #define wqe_xc_SHIFT 21 3354 #define wqe_xc_MASK 0x00000001 3355 #define wqe_xc_WORD word10 3356 #define wqe_sr_SHIFT 22 3357 #define wqe_sr_MASK 0x00000001 3358 #define wqe_sr_WORD word10 3359 #define wqe_ccpe_SHIFT 23 3360 #define wqe_ccpe_MASK 0x00000001 3361 #define wqe_ccpe_WORD word10 3362 #define wqe_ccp_SHIFT 24 3363 #define wqe_ccp_MASK 0x000000ff 3364 #define wqe_ccp_WORD word10 3365 uint32_t word11; 3366 #define wqe_cmd_type_SHIFT 0 3367 #define wqe_cmd_type_MASK 0x0000000f 3368 #define wqe_cmd_type_WORD word11 3369 #define wqe_els_id_SHIFT 4 3370 #define wqe_els_id_MASK 0x00000003 3371 #define wqe_els_id_WORD word11 3372 #define LPFC_ELS_ID_FLOGI 3 3373 #define LPFC_ELS_ID_FDISC 2 3374 #define LPFC_ELS_ID_LOGO 1 3375 #define LPFC_ELS_ID_DEFAULT 0 3376 #define wqe_wqec_SHIFT 7 3377 #define wqe_wqec_MASK 0x00000001 3378 #define wqe_wqec_WORD word11 3379 #define wqe_cqid_SHIFT 16 3380 #define wqe_cqid_MASK 0x0000ffff 3381 #define wqe_cqid_WORD word11 3382 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3383 }; 3384 3385 struct wqe_did { 3386 uint32_t word5; 3387 #define wqe_els_did_SHIFT 0 3388 #define wqe_els_did_MASK 0x00FFFFFF 3389 #define wqe_els_did_WORD word5 3390 #define wqe_xmit_bls_pt_SHIFT 28 3391 #define wqe_xmit_bls_pt_MASK 0x00000003 3392 #define wqe_xmit_bls_pt_WORD word5 3393 #define wqe_xmit_bls_ar_SHIFT 30 3394 #define wqe_xmit_bls_ar_MASK 0x00000001 3395 #define wqe_xmit_bls_ar_WORD word5 3396 #define wqe_xmit_bls_xo_SHIFT 31 3397 #define wqe_xmit_bls_xo_MASK 0x00000001 3398 #define wqe_xmit_bls_xo_WORD word5 3399 }; 3400 3401 struct lpfc_wqe_generic{ 3402 struct ulp_bde64 bde; 3403 uint32_t word3; 3404 uint32_t word4; 3405 uint32_t word5; 3406 struct wqe_common wqe_com; 3407 uint32_t payload[4]; 3408 }; 3409 3410 struct els_request64_wqe { 3411 struct ulp_bde64 bde; 3412 uint32_t payload_len; 3413 uint32_t word4; 3414 #define els_req64_sid_SHIFT 0 3415 #define els_req64_sid_MASK 0x00FFFFFF 3416 #define els_req64_sid_WORD word4 3417 #define els_req64_sp_SHIFT 24 3418 #define els_req64_sp_MASK 0x00000001 3419 #define els_req64_sp_WORD word4 3420 #define els_req64_vf_SHIFT 25 3421 #define els_req64_vf_MASK 0x00000001 3422 #define els_req64_vf_WORD word4 3423 struct wqe_did wqe_dest; 3424 struct wqe_common wqe_com; /* words 6-11 */ 3425 uint32_t word12; 3426 #define els_req64_vfid_SHIFT 1 3427 #define els_req64_vfid_MASK 0x00000FFF 3428 #define els_req64_vfid_WORD word12 3429 #define els_req64_pri_SHIFT 13 3430 #define els_req64_pri_MASK 0x00000007 3431 #define els_req64_pri_WORD word12 3432 uint32_t word13; 3433 #define els_req64_hopcnt_SHIFT 24 3434 #define els_req64_hopcnt_MASK 0x000000ff 3435 #define els_req64_hopcnt_WORD word13 3436 uint32_t reserved[2]; 3437 }; 3438 3439 struct xmit_els_rsp64_wqe { 3440 struct ulp_bde64 bde; 3441 uint32_t response_payload_len; 3442 uint32_t word4; 3443 #define els_rsp64_sid_SHIFT 0 3444 #define els_rsp64_sid_MASK 0x00FFFFFF 3445 #define els_rsp64_sid_WORD word4 3446 #define els_rsp64_sp_SHIFT 24 3447 #define els_rsp64_sp_MASK 0x00000001 3448 #define els_rsp64_sp_WORD word4 3449 struct wqe_did wqe_dest; 3450 struct wqe_common wqe_com; /* words 6-11 */ 3451 uint32_t word12; 3452 #define wqe_rsp_temp_rpi_SHIFT 0 3453 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3454 #define wqe_rsp_temp_rpi_WORD word12 3455 uint32_t rsvd_13_15[3]; 3456 }; 3457 3458 struct xmit_bls_rsp64_wqe { 3459 uint32_t payload0; 3460 /* Payload0 for BA_ACC */ 3461 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3462 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3463 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3464 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3465 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3466 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3467 /* Payload0 for BA_RJT */ 3468 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3469 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3470 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3471 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3472 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3473 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3474 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3475 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3476 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3477 uint32_t word1; 3478 #define xmit_bls_rsp64_rxid_SHIFT 0 3479 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3480 #define xmit_bls_rsp64_rxid_WORD word1 3481 #define xmit_bls_rsp64_oxid_SHIFT 16 3482 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3483 #define xmit_bls_rsp64_oxid_WORD word1 3484 uint32_t word2; 3485 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3486 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3487 #define xmit_bls_rsp64_seqcnthi_WORD word2 3488 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3489 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3490 #define xmit_bls_rsp64_seqcntlo_WORD word2 3491 uint32_t rsrvd3; 3492 uint32_t rsrvd4; 3493 struct wqe_did wqe_dest; 3494 struct wqe_common wqe_com; /* words 6-11 */ 3495 uint32_t word12; 3496 #define xmit_bls_rsp64_temprpi_SHIFT 0 3497 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3498 #define xmit_bls_rsp64_temprpi_WORD word12 3499 uint32_t rsvd_13_15[3]; 3500 }; 3501 3502 struct wqe_rctl_dfctl { 3503 uint32_t word5; 3504 #define wqe_si_SHIFT 2 3505 #define wqe_si_MASK 0x000000001 3506 #define wqe_si_WORD word5 3507 #define wqe_la_SHIFT 3 3508 #define wqe_la_MASK 0x000000001 3509 #define wqe_la_WORD word5 3510 #define wqe_xo_SHIFT 6 3511 #define wqe_xo_MASK 0x000000001 3512 #define wqe_xo_WORD word5 3513 #define wqe_ls_SHIFT 7 3514 #define wqe_ls_MASK 0x000000001 3515 #define wqe_ls_WORD word5 3516 #define wqe_dfctl_SHIFT 8 3517 #define wqe_dfctl_MASK 0x0000000ff 3518 #define wqe_dfctl_WORD word5 3519 #define wqe_type_SHIFT 16 3520 #define wqe_type_MASK 0x0000000ff 3521 #define wqe_type_WORD word5 3522 #define wqe_rctl_SHIFT 24 3523 #define wqe_rctl_MASK 0x0000000ff 3524 #define wqe_rctl_WORD word5 3525 }; 3526 3527 struct xmit_seq64_wqe { 3528 struct ulp_bde64 bde; 3529 uint32_t rsvd3; 3530 uint32_t relative_offset; 3531 struct wqe_rctl_dfctl wge_ctl; 3532 struct wqe_common wqe_com; /* words 6-11 */ 3533 uint32_t xmit_len; 3534 uint32_t rsvd_12_15[3]; 3535 }; 3536 struct xmit_bcast64_wqe { 3537 struct ulp_bde64 bde; 3538 uint32_t seq_payload_len; 3539 uint32_t rsvd4; 3540 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3541 struct wqe_common wqe_com; /* words 6-11 */ 3542 uint32_t rsvd_12_15[4]; 3543 }; 3544 3545 struct gen_req64_wqe { 3546 struct ulp_bde64 bde; 3547 uint32_t request_payload_len; 3548 uint32_t relative_offset; 3549 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3550 struct wqe_common wqe_com; /* words 6-11 */ 3551 uint32_t rsvd_12_15[4]; 3552 }; 3553 3554 struct create_xri_wqe { 3555 uint32_t rsrvd[5]; /* words 0-4 */ 3556 struct wqe_did wqe_dest; /* word 5 */ 3557 struct wqe_common wqe_com; /* words 6-11 */ 3558 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3559 }; 3560 3561 #define T_REQUEST_TAG 3 3562 #define T_XRI_TAG 1 3563 3564 struct abort_cmd_wqe { 3565 uint32_t rsrvd[3]; 3566 uint32_t word3; 3567 #define abort_cmd_ia_SHIFT 0 3568 #define abort_cmd_ia_MASK 0x000000001 3569 #define abort_cmd_ia_WORD word3 3570 #define abort_cmd_criteria_SHIFT 8 3571 #define abort_cmd_criteria_MASK 0x0000000ff 3572 #define abort_cmd_criteria_WORD word3 3573 uint32_t rsrvd4; 3574 uint32_t rsrvd5; 3575 struct wqe_common wqe_com; /* words 6-11 */ 3576 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3577 }; 3578 3579 struct fcp_iwrite64_wqe { 3580 struct ulp_bde64 bde; 3581 uint32_t payload_offset_len; 3582 uint32_t total_xfer_len; 3583 uint32_t initial_xfer_len; 3584 struct wqe_common wqe_com; /* words 6-11 */ 3585 uint32_t rsrvd12; 3586 struct ulp_bde64 ph_bde; /* words 13-15 */ 3587 }; 3588 3589 struct fcp_iread64_wqe { 3590 struct ulp_bde64 bde; 3591 uint32_t payload_offset_len; /* word 3 */ 3592 uint32_t total_xfer_len; /* word 4 */ 3593 uint32_t rsrvd5; /* word 5 */ 3594 struct wqe_common wqe_com; /* words 6-11 */ 3595 uint32_t rsrvd12; 3596 struct ulp_bde64 ph_bde; /* words 13-15 */ 3597 }; 3598 3599 struct fcp_icmnd64_wqe { 3600 struct ulp_bde64 bde; /* words 0-2 */ 3601 uint32_t rsrvd3; /* word 3 */ 3602 uint32_t rsrvd4; /* word 4 */ 3603 uint32_t rsrvd5; /* word 5 */ 3604 struct wqe_common wqe_com; /* words 6-11 */ 3605 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3606 }; 3607 3608 3609 union lpfc_wqe { 3610 uint32_t words[16]; 3611 struct lpfc_wqe_generic generic; 3612 struct fcp_icmnd64_wqe fcp_icmd; 3613 struct fcp_iread64_wqe fcp_iread; 3614 struct fcp_iwrite64_wqe fcp_iwrite; 3615 struct abort_cmd_wqe abort_cmd; 3616 struct create_xri_wqe create_xri; 3617 struct xmit_bcast64_wqe xmit_bcast64; 3618 struct xmit_seq64_wqe xmit_sequence; 3619 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3620 struct xmit_els_rsp64_wqe xmit_els_rsp; 3621 struct els_request64_wqe els_req; 3622 struct gen_req64_wqe gen_req; 3623 }; 3624 3625 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3626 #define LPFC_FILE_TYPE_GROUP 0xf7 3627 #define LPFC_FILE_ID_GROUP 0xa2 3628 struct lpfc_grp_hdr { 3629 uint32_t size; 3630 uint32_t magic_number; 3631 uint32_t word2; 3632 #define lpfc_grp_hdr_file_type_SHIFT 24 3633 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3634 #define lpfc_grp_hdr_file_type_WORD word2 3635 #define lpfc_grp_hdr_id_SHIFT 16 3636 #define lpfc_grp_hdr_id_MASK 0x000000FF 3637 #define lpfc_grp_hdr_id_WORD word2 3638 uint8_t rev_name[128]; 3639 uint8_t date[12]; 3640 uint8_t revision[32]; 3641 }; 3642 3643 #define FCP_COMMAND 0x0 3644 #define FCP_COMMAND_DATA_OUT 0x1 3645 #define ELS_COMMAND_NON_FIP 0xC 3646 #define ELS_COMMAND_FIP 0xD 3647 #define OTHER_COMMAND 0x8 3648 3649 #define LPFC_FW_DUMP 1 3650 #define LPFC_FW_RESET 2 3651 #define LPFC_DV_RESET 3 3652