1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 /* Macros to deal with bit fields. Each bit field must have 3 #defines 24 * associated with it (_SHIFT, _MASK, and _WORD). 25 * EG. For a bit field that is in the 7th bit of the "field4" field of a 26 * structure and is 2 bits in size the following #defines must exist: 27 * struct temp { 28 * uint32_t field1; 29 * uint32_t field2; 30 * uint32_t field3; 31 * uint32_t field4; 32 * #define example_bit_field_SHIFT 7 33 * #define example_bit_field_MASK 0x03 34 * #define example_bit_field_WORD field4 35 * uint32_t field5; 36 * }; 37 * Then the macros below may be used to get or set the value of that field. 38 * EG. To get the value of the bit field from the above example: 39 * struct temp t1; 40 * value = bf_get(example_bit_field, &t1); 41 * And then to set that bit field: 42 * bf_set(example_bit_field, &t1, 2); 43 * Or clear that bit field: 44 * bf_set(example_bit_field, &t1, 0); 45 */ 46 #define bf_get_be32(name, ptr) \ 47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get_le32(name, ptr) \ 49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get(name, ptr) \ 51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 52 #define bf_set_le32(name, ptr, value) \ 53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 55 ~(name##_MASK << name##_SHIFT))))) 56 #define bf_set(name, ptr, value) \ 57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 59 60 struct dma_address { 61 uint32_t addr_lo; 62 uint32_t addr_hi; 63 }; 64 65 struct lpfc_sli_intf { 66 uint32_t word0; 67 #define lpfc_sli_intf_valid_SHIFT 29 68 #define lpfc_sli_intf_valid_MASK 0x00000007 69 #define lpfc_sli_intf_valid_WORD word0 70 #define LPFC_SLI_INTF_VALID 6 71 #define lpfc_sli_intf_sli_hint2_SHIFT 24 72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 73 #define lpfc_sli_intf_sli_hint2_WORD word0 74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 75 #define lpfc_sli_intf_sli_hint1_SHIFT 16 76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 77 #define lpfc_sli_intf_sli_hint1_WORD word0 78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 79 #define LPFC_SLI_INTF_SLI_HINT1_1 1 80 #define LPFC_SLI_INTF_SLI_HINT1_2 2 81 #define lpfc_sli_intf_if_type_SHIFT 12 82 #define lpfc_sli_intf_if_type_MASK 0x0000000F 83 #define lpfc_sli_intf_if_type_WORD word0 84 #define LPFC_SLI_INTF_IF_TYPE_0 0 85 #define LPFC_SLI_INTF_IF_TYPE_1 1 86 #define LPFC_SLI_INTF_IF_TYPE_2 2 87 #define LPFC_SLI_INTF_IF_TYPE_6 6 88 #define lpfc_sli_intf_sli_family_SHIFT 8 89 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 90 #define lpfc_sli_intf_sli_family_WORD word0 91 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 92 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 95 #define lpfc_sli_intf_slirev_SHIFT 4 96 #define lpfc_sli_intf_slirev_MASK 0x0000000F 97 #define lpfc_sli_intf_slirev_WORD word0 98 #define LPFC_SLI_INTF_REV_SLI3 3 99 #define LPFC_SLI_INTF_REV_SLI4 4 100 #define lpfc_sli_intf_func_type_SHIFT 0 101 #define lpfc_sli_intf_func_type_MASK 0x00000001 102 #define lpfc_sli_intf_func_type_WORD word0 103 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 104 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 105 }; 106 107 #define LPFC_SLI4_MBX_EMBED true 108 #define LPFC_SLI4_MBX_NEMBED false 109 110 #define LPFC_SLI4_MB_WORD_COUNT 64 111 #define LPFC_MAX_MQ_PAGE 8 112 #define LPFC_MAX_WQ_PAGE_V0 4 113 #define LPFC_MAX_WQ_PAGE 8 114 #define LPFC_MAX_RQ_PAGE 8 115 #define LPFC_MAX_CQ_PAGE 4 116 #define LPFC_MAX_EQ_PAGE 8 117 118 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 119 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 120 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 121 122 /* Define SLI4 Alignment requirements. */ 123 #define LPFC_ALIGN_16_BYTE 16 124 #define LPFC_ALIGN_64_BYTE 64 125 126 /* Define SLI4 specific definitions. */ 127 #define LPFC_MQ_CQE_BYTE_OFFSET 256 128 #define LPFC_MBX_CMD_HDR_LENGTH 16 129 #define LPFC_MBX_ERROR_RANGE 0x4000 130 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 131 #define LPFC_BMBX_BIT1_ADDR_LO 0 132 #define LPFC_RPI_HDR_COUNT 64 133 #define LPFC_HDR_TEMPLATE_SIZE 4096 134 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 135 #define LPFC_FCF_RECORD_WD_CNT 132 136 #define LPFC_ENTIRE_FCF_DATABASE 0 137 #define LPFC_DFLT_FCF_INDEX 0 138 139 /* Virtual function numbers */ 140 #define LPFC_VF0 0 141 #define LPFC_VF1 1 142 #define LPFC_VF2 2 143 #define LPFC_VF3 3 144 #define LPFC_VF4 4 145 #define LPFC_VF5 5 146 #define LPFC_VF6 6 147 #define LPFC_VF7 7 148 #define LPFC_VF8 8 149 #define LPFC_VF9 9 150 #define LPFC_VF10 10 151 #define LPFC_VF11 11 152 #define LPFC_VF12 12 153 #define LPFC_VF13 13 154 #define LPFC_VF14 14 155 #define LPFC_VF15 15 156 #define LPFC_VF16 16 157 #define LPFC_VF17 17 158 #define LPFC_VF18 18 159 #define LPFC_VF19 19 160 #define LPFC_VF20 20 161 #define LPFC_VF21 21 162 #define LPFC_VF22 22 163 #define LPFC_VF23 23 164 #define LPFC_VF24 24 165 #define LPFC_VF25 25 166 #define LPFC_VF26 26 167 #define LPFC_VF27 27 168 #define LPFC_VF28 28 169 #define LPFC_VF29 29 170 #define LPFC_VF30 30 171 #define LPFC_VF31 31 172 173 /* PCI function numbers */ 174 #define LPFC_PCI_FUNC0 0 175 #define LPFC_PCI_FUNC1 1 176 #define LPFC_PCI_FUNC2 2 177 #define LPFC_PCI_FUNC3 3 178 #define LPFC_PCI_FUNC4 4 179 180 /* SLI4 interface type-2 PDEV_CTL register */ 181 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 182 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 183 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 184 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 185 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 186 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 188 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 189 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 190 191 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 192 193 /* Active interrupt test count */ 194 #define LPFC_ACT_INTR_CNT 4 195 196 /* Algrithmns for scheduling FCP commands to WQs */ 197 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 198 #define LPFC_FCP_SCHED_BY_CPU 1 199 200 /* Algrithmns for NameServer Query after RSCN */ 201 #define LPFC_NS_QUERY_GID_FT 0 202 #define LPFC_NS_QUERY_GID_PT 1 203 204 /* Delay Multiplier constant */ 205 #define LPFC_DMULT_CONST 651042 206 #define LPFC_DMULT_MAX 1023 207 208 /* Configuration of Interrupts / sec for entire HBA port */ 209 #define LPFC_MIN_IMAX 5000 210 #define LPFC_MAX_IMAX 5000000 211 #define LPFC_DEF_IMAX 150000 212 213 #define LPFC_MIN_CPU_MAP 0 214 #define LPFC_MAX_CPU_MAP 2 215 #define LPFC_HBA_CPU_MAP 1 216 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 217 218 /* PORT_CAPABILITIES constants. */ 219 #define LPFC_MAX_SUPPORTED_PAGES 8 220 221 struct ulp_bde64 { 222 union ULP_BDE_TUS { 223 uint32_t w; 224 struct { 225 #ifdef __BIG_ENDIAN_BITFIELD 226 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 227 VALUE !! */ 228 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 229 #else /* __LITTLE_ENDIAN_BITFIELD */ 230 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 231 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 232 VALUE !! */ 233 #endif 234 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 235 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 236 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 237 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 238 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 239 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 240 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 241 } f; 242 } tus; 243 uint32_t addrLow; 244 uint32_t addrHigh; 245 }; 246 247 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 248 #define LPFC_MAX_BDE_IMM_SIZE 64 249 250 struct lpfc_sli4_flags { 251 uint32_t word0; 252 #define lpfc_idx_rsrc_rdy_SHIFT 0 253 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 254 #define lpfc_idx_rsrc_rdy_WORD word0 255 #define LPFC_IDX_RSRC_RDY 1 256 #define lpfc_rpi_rsrc_rdy_SHIFT 1 257 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 258 #define lpfc_rpi_rsrc_rdy_WORD word0 259 #define LPFC_RPI_RSRC_RDY 1 260 #define lpfc_vpi_rsrc_rdy_SHIFT 2 261 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 262 #define lpfc_vpi_rsrc_rdy_WORD word0 263 #define LPFC_VPI_RSRC_RDY 1 264 #define lpfc_vfi_rsrc_rdy_SHIFT 3 265 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 266 #define lpfc_vfi_rsrc_rdy_WORD word0 267 #define LPFC_VFI_RSRC_RDY 1 268 }; 269 270 struct sli4_bls_rsp { 271 uint32_t word0_rsvd; /* Word0 must be reserved */ 272 uint32_t word1; 273 #define lpfc_abts_orig_SHIFT 0 274 #define lpfc_abts_orig_MASK 0x00000001 275 #define lpfc_abts_orig_WORD word1 276 #define LPFC_ABTS_UNSOL_RSP 1 277 #define LPFC_ABTS_UNSOL_INT 0 278 uint32_t word2; 279 #define lpfc_abts_rxid_SHIFT 0 280 #define lpfc_abts_rxid_MASK 0x0000FFFF 281 #define lpfc_abts_rxid_WORD word2 282 #define lpfc_abts_oxid_SHIFT 16 283 #define lpfc_abts_oxid_MASK 0x0000FFFF 284 #define lpfc_abts_oxid_WORD word2 285 uint32_t word3; 286 #define lpfc_vndr_code_SHIFT 0 287 #define lpfc_vndr_code_MASK 0x000000FF 288 #define lpfc_vndr_code_WORD word3 289 #define lpfc_rsn_expln_SHIFT 8 290 #define lpfc_rsn_expln_MASK 0x000000FF 291 #define lpfc_rsn_expln_WORD word3 292 #define lpfc_rsn_code_SHIFT 16 293 #define lpfc_rsn_code_MASK 0x000000FF 294 #define lpfc_rsn_code_WORD word3 295 296 uint32_t word4; 297 uint32_t word5_rsvd; /* Word5 must be reserved */ 298 }; 299 300 /* event queue entry structure */ 301 struct lpfc_eqe { 302 uint32_t word0; 303 #define lpfc_eqe_resource_id_SHIFT 16 304 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 305 #define lpfc_eqe_resource_id_WORD word0 306 #define lpfc_eqe_minor_code_SHIFT 4 307 #define lpfc_eqe_minor_code_MASK 0x00000FFF 308 #define lpfc_eqe_minor_code_WORD word0 309 #define lpfc_eqe_major_code_SHIFT 1 310 #define lpfc_eqe_major_code_MASK 0x00000007 311 #define lpfc_eqe_major_code_WORD word0 312 #define lpfc_eqe_valid_SHIFT 0 313 #define lpfc_eqe_valid_MASK 0x00000001 314 #define lpfc_eqe_valid_WORD word0 315 }; 316 317 /* completion queue entry structure (common fields for all cqe types) */ 318 struct lpfc_cqe { 319 uint32_t reserved0; 320 uint32_t reserved1; 321 uint32_t reserved2; 322 uint32_t word3; 323 #define lpfc_cqe_valid_SHIFT 31 324 #define lpfc_cqe_valid_MASK 0x00000001 325 #define lpfc_cqe_valid_WORD word3 326 #define lpfc_cqe_code_SHIFT 16 327 #define lpfc_cqe_code_MASK 0x000000FF 328 #define lpfc_cqe_code_WORD word3 329 }; 330 331 /* Completion Queue Entry Status Codes */ 332 #define CQE_STATUS_SUCCESS 0x0 333 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 334 #define CQE_STATUS_REMOTE_STOP 0x2 335 #define CQE_STATUS_LOCAL_REJECT 0x3 336 #define CQE_STATUS_NPORT_RJT 0x4 337 #define CQE_STATUS_FABRIC_RJT 0x5 338 #define CQE_STATUS_NPORT_BSY 0x6 339 #define CQE_STATUS_FABRIC_BSY 0x7 340 #define CQE_STATUS_INTERMED_RSP 0x8 341 #define CQE_STATUS_LS_RJT 0x9 342 #define CQE_STATUS_CMD_REJECT 0xb 343 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 344 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 345 #define CQE_STATUS_DI_ERROR 0x16 346 347 /* Used when mapping CQE status to IOCB */ 348 #define LPFC_IOCB_STATUS_MASK 0xf 349 350 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 351 #define CQE_HW_STATUS_NO_ERR 0x0 352 #define CQE_HW_STATUS_UNDERRUN 0x1 353 #define CQE_HW_STATUS_OVERRUN 0x2 354 355 /* Completion Queue Entry Codes */ 356 #define CQE_CODE_COMPL_WQE 0x1 357 #define CQE_CODE_RELEASE_WQE 0x2 358 #define CQE_CODE_RECEIVE 0x4 359 #define CQE_CODE_XRI_ABORTED 0x5 360 #define CQE_CODE_RECEIVE_V1 0x9 361 #define CQE_CODE_NVME_ERSP 0xd 362 363 /* 364 * Define mask value for xri_aborted and wcqe completed CQE extended status. 365 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 366 */ 367 #define WCQE_PARAM_MASK 0x1FF 368 369 /* completion queue entry for wqe completions */ 370 struct lpfc_wcqe_complete { 371 uint32_t word0; 372 #define lpfc_wcqe_c_request_tag_SHIFT 16 373 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 374 #define lpfc_wcqe_c_request_tag_WORD word0 375 #define lpfc_wcqe_c_status_SHIFT 8 376 #define lpfc_wcqe_c_status_MASK 0x000000FF 377 #define lpfc_wcqe_c_status_WORD word0 378 #define lpfc_wcqe_c_hw_status_SHIFT 0 379 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 380 #define lpfc_wcqe_c_hw_status_WORD word0 381 #define lpfc_wcqe_c_ersp0_SHIFT 0 382 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 383 #define lpfc_wcqe_c_ersp0_WORD word0 384 uint32_t total_data_placed; 385 uint32_t parameter; 386 #define lpfc_wcqe_c_bg_edir_SHIFT 5 387 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 388 #define lpfc_wcqe_c_bg_edir_WORD parameter 389 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 390 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 391 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 392 #define lpfc_wcqe_c_bg_re_SHIFT 2 393 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 394 #define lpfc_wcqe_c_bg_re_WORD parameter 395 #define lpfc_wcqe_c_bg_ae_SHIFT 1 396 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 397 #define lpfc_wcqe_c_bg_ae_WORD parameter 398 #define lpfc_wcqe_c_bg_ge_SHIFT 0 399 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 400 #define lpfc_wcqe_c_bg_ge_WORD parameter 401 uint32_t word3; 402 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 403 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 404 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 405 #define lpfc_wcqe_c_xb_SHIFT 28 406 #define lpfc_wcqe_c_xb_MASK 0x00000001 407 #define lpfc_wcqe_c_xb_WORD word3 408 #define lpfc_wcqe_c_pv_SHIFT 27 409 #define lpfc_wcqe_c_pv_MASK 0x00000001 410 #define lpfc_wcqe_c_pv_WORD word3 411 #define lpfc_wcqe_c_priority_SHIFT 24 412 #define lpfc_wcqe_c_priority_MASK 0x00000007 413 #define lpfc_wcqe_c_priority_WORD word3 414 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 415 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 416 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 417 #define lpfc_wcqe_c_sqhead_SHIFT 0 418 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 419 #define lpfc_wcqe_c_sqhead_WORD word3 420 }; 421 422 /* completion queue entry for wqe release */ 423 struct lpfc_wcqe_release { 424 uint32_t reserved0; 425 uint32_t reserved1; 426 uint32_t word2; 427 #define lpfc_wcqe_r_wq_id_SHIFT 16 428 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 429 #define lpfc_wcqe_r_wq_id_WORD word2 430 #define lpfc_wcqe_r_wqe_index_SHIFT 0 431 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 432 #define lpfc_wcqe_r_wqe_index_WORD word2 433 uint32_t word3; 434 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 435 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 436 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 437 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 438 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 439 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 440 }; 441 442 struct sli4_wcqe_xri_aborted { 443 uint32_t word0; 444 #define lpfc_wcqe_xa_status_SHIFT 8 445 #define lpfc_wcqe_xa_status_MASK 0x000000FF 446 #define lpfc_wcqe_xa_status_WORD word0 447 uint32_t parameter; 448 uint32_t word2; 449 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 450 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 451 #define lpfc_wcqe_xa_remote_xid_WORD word2 452 #define lpfc_wcqe_xa_xri_SHIFT 0 453 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 454 #define lpfc_wcqe_xa_xri_WORD word2 455 uint32_t word3; 456 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 457 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 458 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 459 #define lpfc_wcqe_xa_ia_SHIFT 30 460 #define lpfc_wcqe_xa_ia_MASK 0x00000001 461 #define lpfc_wcqe_xa_ia_WORD word3 462 #define CQE_XRI_ABORTED_IA_REMOTE 0 463 #define CQE_XRI_ABORTED_IA_LOCAL 1 464 #define lpfc_wcqe_xa_br_SHIFT 29 465 #define lpfc_wcqe_xa_br_MASK 0x00000001 466 #define lpfc_wcqe_xa_br_WORD word3 467 #define CQE_XRI_ABORTED_BR_BA_ACC 0 468 #define CQE_XRI_ABORTED_BR_BA_RJT 1 469 #define lpfc_wcqe_xa_eo_SHIFT 28 470 #define lpfc_wcqe_xa_eo_MASK 0x00000001 471 #define lpfc_wcqe_xa_eo_WORD word3 472 #define CQE_XRI_ABORTED_EO_REMOTE 0 473 #define CQE_XRI_ABORTED_EO_LOCAL 1 474 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 475 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 476 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 477 }; 478 479 /* completion queue entry structure for rqe completion */ 480 struct lpfc_rcqe { 481 uint32_t word0; 482 #define lpfc_rcqe_bindex_SHIFT 16 483 #define lpfc_rcqe_bindex_MASK 0x0000FFF 484 #define lpfc_rcqe_bindex_WORD word0 485 #define lpfc_rcqe_status_SHIFT 8 486 #define lpfc_rcqe_status_MASK 0x000000FF 487 #define lpfc_rcqe_status_WORD word0 488 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 489 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 490 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 491 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 492 uint32_t word1; 493 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 494 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 495 #define lpfc_rcqe_fcf_id_v1_WORD word1 496 uint32_t word2; 497 #define lpfc_rcqe_length_SHIFT 16 498 #define lpfc_rcqe_length_MASK 0x0000FFFF 499 #define lpfc_rcqe_length_WORD word2 500 #define lpfc_rcqe_rq_id_SHIFT 6 501 #define lpfc_rcqe_rq_id_MASK 0x000003FF 502 #define lpfc_rcqe_rq_id_WORD word2 503 #define lpfc_rcqe_fcf_id_SHIFT 0 504 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 505 #define lpfc_rcqe_fcf_id_WORD word2 506 #define lpfc_rcqe_rq_id_v1_SHIFT 0 507 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 508 #define lpfc_rcqe_rq_id_v1_WORD word2 509 uint32_t word3; 510 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 511 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 512 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 513 #define lpfc_rcqe_port_SHIFT 30 514 #define lpfc_rcqe_port_MASK 0x00000001 515 #define lpfc_rcqe_port_WORD word3 516 #define lpfc_rcqe_hdr_length_SHIFT 24 517 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 518 #define lpfc_rcqe_hdr_length_WORD word3 519 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 520 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 521 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 522 #define lpfc_rcqe_eof_SHIFT 8 523 #define lpfc_rcqe_eof_MASK 0x000000FF 524 #define lpfc_rcqe_eof_WORD word3 525 #define FCOE_EOFn 0x41 526 #define FCOE_EOFt 0x42 527 #define FCOE_EOFni 0x49 528 #define FCOE_EOFa 0x50 529 #define lpfc_rcqe_sof_SHIFT 0 530 #define lpfc_rcqe_sof_MASK 0x000000FF 531 #define lpfc_rcqe_sof_WORD word3 532 #define FCOE_SOFi2 0x2d 533 #define FCOE_SOFi3 0x2e 534 #define FCOE_SOFn2 0x35 535 #define FCOE_SOFn3 0x36 536 }; 537 538 struct lpfc_rqe { 539 uint32_t address_hi; 540 uint32_t address_lo; 541 }; 542 543 /* buffer descriptors */ 544 struct lpfc_bde4 { 545 uint32_t addr_hi; 546 uint32_t addr_lo; 547 uint32_t word2; 548 #define lpfc_bde4_last_SHIFT 31 549 #define lpfc_bde4_last_MASK 0x00000001 550 #define lpfc_bde4_last_WORD word2 551 #define lpfc_bde4_sge_offset_SHIFT 0 552 #define lpfc_bde4_sge_offset_MASK 0x000003FF 553 #define lpfc_bde4_sge_offset_WORD word2 554 uint32_t word3; 555 #define lpfc_bde4_length_SHIFT 0 556 #define lpfc_bde4_length_MASK 0x000000FF 557 #define lpfc_bde4_length_WORD word3 558 }; 559 560 struct lpfc_register { 561 uint32_t word0; 562 }; 563 564 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 565 #define LPFC_PORT_SEM_MASK 0xF000 566 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 567 #define LPFC_UERR_STATUS_HI 0x00A4 568 #define LPFC_UERR_STATUS_LO 0x00A0 569 #define LPFC_UE_MASK_HI 0x00AC 570 #define LPFC_UE_MASK_LO 0x00A8 571 572 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 573 #define LPFC_SLI_INTF 0x0058 574 #define LPFC_SLI_ASIC_VER 0x009C 575 576 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 577 #define lpfc_port_smphr_perr_SHIFT 31 578 #define lpfc_port_smphr_perr_MASK 0x1 579 #define lpfc_port_smphr_perr_WORD word0 580 #define lpfc_port_smphr_sfi_SHIFT 30 581 #define lpfc_port_smphr_sfi_MASK 0x1 582 #define lpfc_port_smphr_sfi_WORD word0 583 #define lpfc_port_smphr_nip_SHIFT 29 584 #define lpfc_port_smphr_nip_MASK 0x1 585 #define lpfc_port_smphr_nip_WORD word0 586 #define lpfc_port_smphr_ipc_SHIFT 28 587 #define lpfc_port_smphr_ipc_MASK 0x1 588 #define lpfc_port_smphr_ipc_WORD word0 589 #define lpfc_port_smphr_scr1_SHIFT 27 590 #define lpfc_port_smphr_scr1_MASK 0x1 591 #define lpfc_port_smphr_scr1_WORD word0 592 #define lpfc_port_smphr_scr2_SHIFT 26 593 #define lpfc_port_smphr_scr2_MASK 0x1 594 #define lpfc_port_smphr_scr2_WORD word0 595 #define lpfc_port_smphr_host_scratch_SHIFT 16 596 #define lpfc_port_smphr_host_scratch_MASK 0xFF 597 #define lpfc_port_smphr_host_scratch_WORD word0 598 #define lpfc_port_smphr_port_status_SHIFT 0 599 #define lpfc_port_smphr_port_status_MASK 0xFFFF 600 #define lpfc_port_smphr_port_status_WORD word0 601 602 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 603 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 604 #define LPFC_POST_STAGE_HOST_RDY 0x0002 605 #define LPFC_POST_STAGE_BE_RESET 0x0003 606 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 607 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 608 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 609 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 610 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 611 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 612 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 613 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 614 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 615 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 616 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 617 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 618 #define LPFC_POST_STAGE_ARMFW_START 0x0800 619 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 620 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 621 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 622 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 623 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 624 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 625 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 626 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 627 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 628 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 629 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 630 #define LPFC_POST_STAGE_RC_DONE 0x0B07 631 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 632 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 633 #define LPFC_POST_STAGE_PORT_READY 0xC000 634 #define LPFC_POST_STAGE_PORT_UE 0xF000 635 636 #define LPFC_CTL_PORT_STA_OFFSET 0x404 637 #define lpfc_sliport_status_err_SHIFT 31 638 #define lpfc_sliport_status_err_MASK 0x1 639 #define lpfc_sliport_status_err_WORD word0 640 #define lpfc_sliport_status_end_SHIFT 30 641 #define lpfc_sliport_status_end_MASK 0x1 642 #define lpfc_sliport_status_end_WORD word0 643 #define lpfc_sliport_status_oti_SHIFT 29 644 #define lpfc_sliport_status_oti_MASK 0x1 645 #define lpfc_sliport_status_oti_WORD word0 646 #define lpfc_sliport_status_rn_SHIFT 24 647 #define lpfc_sliport_status_rn_MASK 0x1 648 #define lpfc_sliport_status_rn_WORD word0 649 #define lpfc_sliport_status_rdy_SHIFT 23 650 #define lpfc_sliport_status_rdy_MASK 0x1 651 #define lpfc_sliport_status_rdy_WORD word0 652 #define MAX_IF_TYPE_2_RESETS 6 653 654 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 655 #define lpfc_sliport_ctrl_end_SHIFT 30 656 #define lpfc_sliport_ctrl_end_MASK 0x1 657 #define lpfc_sliport_ctrl_end_WORD word0 658 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 659 #define LPFC_SLIPORT_BIG_ENDIAN 1 660 #define lpfc_sliport_ctrl_ip_SHIFT 27 661 #define lpfc_sliport_ctrl_ip_MASK 0x1 662 #define lpfc_sliport_ctrl_ip_WORD word0 663 #define LPFC_SLIPORT_INIT_PORT 1 664 665 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 666 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 667 668 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 669 #define lpfc_sliport_eqdelay_delay_SHIFT 16 670 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 671 #define lpfc_sliport_eqdelay_delay_WORD word0 672 #define lpfc_sliport_eqdelay_id_SHIFT 0 673 #define lpfc_sliport_eqdelay_id_MASK 0xfff 674 #define lpfc_sliport_eqdelay_id_WORD word0 675 #define LPFC_SEC_TO_USEC 1000000 676 677 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 678 * reside in BAR 2. 679 */ 680 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 681 682 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 683 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 684 685 #define LPFC_HST_ISR0 0x0C18 686 #define LPFC_HST_ISR1 0x0C1C 687 #define LPFC_HST_ISR2 0x0C20 688 #define LPFC_HST_ISR3 0x0C24 689 #define LPFC_HST_ISR4 0x0C28 690 691 #define LPFC_HST_IMR0 0x0C48 692 #define LPFC_HST_IMR1 0x0C4C 693 #define LPFC_HST_IMR2 0x0C50 694 #define LPFC_HST_IMR3 0x0C54 695 #define LPFC_HST_IMR4 0x0C58 696 697 #define LPFC_HST_ISCR0 0x0C78 698 #define LPFC_HST_ISCR1 0x0C7C 699 #define LPFC_HST_ISCR2 0x0C80 700 #define LPFC_HST_ISCR3 0x0C84 701 #define LPFC_HST_ISCR4 0x0C88 702 703 #define LPFC_SLI4_INTR0 BIT0 704 #define LPFC_SLI4_INTR1 BIT1 705 #define LPFC_SLI4_INTR2 BIT2 706 #define LPFC_SLI4_INTR3 BIT3 707 #define LPFC_SLI4_INTR4 BIT4 708 #define LPFC_SLI4_INTR5 BIT5 709 #define LPFC_SLI4_INTR6 BIT6 710 #define LPFC_SLI4_INTR7 BIT7 711 #define LPFC_SLI4_INTR8 BIT8 712 #define LPFC_SLI4_INTR9 BIT9 713 #define LPFC_SLI4_INTR10 BIT10 714 #define LPFC_SLI4_INTR11 BIT11 715 #define LPFC_SLI4_INTR12 BIT12 716 #define LPFC_SLI4_INTR13 BIT13 717 #define LPFC_SLI4_INTR14 BIT14 718 #define LPFC_SLI4_INTR15 BIT15 719 #define LPFC_SLI4_INTR16 BIT16 720 #define LPFC_SLI4_INTR17 BIT17 721 #define LPFC_SLI4_INTR18 BIT18 722 #define LPFC_SLI4_INTR19 BIT19 723 #define LPFC_SLI4_INTR20 BIT20 724 #define LPFC_SLI4_INTR21 BIT21 725 #define LPFC_SLI4_INTR22 BIT22 726 #define LPFC_SLI4_INTR23 BIT23 727 #define LPFC_SLI4_INTR24 BIT24 728 #define LPFC_SLI4_INTR25 BIT25 729 #define LPFC_SLI4_INTR26 BIT26 730 #define LPFC_SLI4_INTR27 BIT27 731 #define LPFC_SLI4_INTR28 BIT28 732 #define LPFC_SLI4_INTR29 BIT29 733 #define LPFC_SLI4_INTR30 BIT30 734 #define LPFC_SLI4_INTR31 BIT31 735 736 /* 737 * The Doorbell registers defined here exist in different BAR 738 * register sets depending on the UCNA Port's reported if_type 739 * value. For UCNA ports running SLI4 and if_type 0, they reside in 740 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 741 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 742 * BAR2. The offsets and base address are different, so the driver 743 * has to compute the register addresses accordingly 744 */ 745 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 746 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 747 #define LPFC_IF6_RQ_DOORBELL 0x0080 748 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 749 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 750 #define lpfc_rq_db_list_fm_num_posted_WORD word0 751 #define lpfc_rq_db_list_fm_index_SHIFT 16 752 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 753 #define lpfc_rq_db_list_fm_index_WORD word0 754 #define lpfc_rq_db_list_fm_id_SHIFT 0 755 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 756 #define lpfc_rq_db_list_fm_id_WORD word0 757 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 758 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 759 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 760 #define lpfc_rq_db_ring_fm_id_SHIFT 0 761 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 762 #define lpfc_rq_db_ring_fm_id_WORD word0 763 764 #define LPFC_ULP0_WQ_DOORBELL 0x0040 765 #define LPFC_ULP1_WQ_DOORBELL 0x0060 766 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 767 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 768 #define lpfc_wq_db_list_fm_num_posted_WORD word0 769 #define lpfc_wq_db_list_fm_index_SHIFT 16 770 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 771 #define lpfc_wq_db_list_fm_index_WORD word0 772 #define lpfc_wq_db_list_fm_id_SHIFT 0 773 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 774 #define lpfc_wq_db_list_fm_id_WORD word0 775 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 776 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 777 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 778 #define lpfc_wq_db_ring_fm_id_SHIFT 0 779 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 780 #define lpfc_wq_db_ring_fm_id_WORD word0 781 782 #define LPFC_IF6_WQ_DOORBELL 0x0040 783 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 784 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 785 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 786 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 787 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 788 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 789 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 790 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 791 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 792 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 793 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 794 #define lpfc_if6_wq_db_list_fm_id_WORD word0 795 796 #define LPFC_EQCQ_DOORBELL 0x0120 797 #define lpfc_eqcq_doorbell_se_SHIFT 31 798 #define lpfc_eqcq_doorbell_se_MASK 0x0001 799 #define lpfc_eqcq_doorbell_se_WORD word0 800 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 801 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 802 #define lpfc_eqcq_doorbell_arm_SHIFT 29 803 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 804 #define lpfc_eqcq_doorbell_arm_WORD word0 805 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 806 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 807 #define lpfc_eqcq_doorbell_num_released_WORD word0 808 #define lpfc_eqcq_doorbell_qt_SHIFT 10 809 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 810 #define lpfc_eqcq_doorbell_qt_WORD word0 811 #define LPFC_QUEUE_TYPE_COMPLETION 0 812 #define LPFC_QUEUE_TYPE_EVENT 1 813 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 814 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 815 #define lpfc_eqcq_doorbell_eqci_WORD word0 816 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 817 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 818 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 819 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 820 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 821 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 822 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 823 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 824 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 825 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 826 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 827 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 828 #define LPFC_CQID_HI_FIELD_SHIFT 10 829 #define LPFC_EQID_HI_FIELD_SHIFT 9 830 831 #define LPFC_IF6_CQ_DOORBELL 0x00C0 832 #define lpfc_if6_cq_doorbell_se_SHIFT 31 833 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 834 #define lpfc_if6_cq_doorbell_se_WORD word0 835 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 836 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 837 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 838 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 839 #define lpfc_if6_cq_doorbell_arm_WORD word0 840 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 841 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 842 #define lpfc_if6_cq_doorbell_num_released_WORD word0 843 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 844 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 845 #define lpfc_if6_cq_doorbell_cqid_WORD word0 846 847 #define LPFC_IF6_EQ_DOORBELL 0x0120 848 #define lpfc_if6_eq_doorbell_io_SHIFT 31 849 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 850 #define lpfc_if6_eq_doorbell_io_WORD word0 851 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 852 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 853 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 854 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 855 #define lpfc_if6_eq_doorbell_arm_WORD word0 856 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 857 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 858 #define lpfc_if6_eq_doorbell_num_released_WORD word0 859 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 860 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 861 #define lpfc_if6_eq_doorbell_eqid_WORD word0 862 863 #define LPFC_BMBX 0x0160 864 #define lpfc_bmbx_addr_SHIFT 2 865 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 866 #define lpfc_bmbx_addr_WORD word0 867 #define lpfc_bmbx_hi_SHIFT 1 868 #define lpfc_bmbx_hi_MASK 0x0001 869 #define lpfc_bmbx_hi_WORD word0 870 #define lpfc_bmbx_rdy_SHIFT 0 871 #define lpfc_bmbx_rdy_MASK 0x0001 872 #define lpfc_bmbx_rdy_WORD word0 873 874 #define LPFC_MQ_DOORBELL 0x0140 875 #define LPFC_IF6_MQ_DOORBELL 0x0160 876 #define lpfc_mq_doorbell_num_posted_SHIFT 16 877 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 878 #define lpfc_mq_doorbell_num_posted_WORD word0 879 #define lpfc_mq_doorbell_id_SHIFT 0 880 #define lpfc_mq_doorbell_id_MASK 0xFFFF 881 #define lpfc_mq_doorbell_id_WORD word0 882 883 struct lpfc_sli4_cfg_mhdr { 884 uint32_t word1; 885 #define lpfc_mbox_hdr_emb_SHIFT 0 886 #define lpfc_mbox_hdr_emb_MASK 0x00000001 887 #define lpfc_mbox_hdr_emb_WORD word1 888 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 889 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 890 #define lpfc_mbox_hdr_sge_cnt_WORD word1 891 uint32_t payload_length; 892 uint32_t tag_lo; 893 uint32_t tag_hi; 894 uint32_t reserved5; 895 }; 896 897 union lpfc_sli4_cfg_shdr { 898 struct { 899 uint32_t word6; 900 #define lpfc_mbox_hdr_opcode_SHIFT 0 901 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 902 #define lpfc_mbox_hdr_opcode_WORD word6 903 #define lpfc_mbox_hdr_subsystem_SHIFT 8 904 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 905 #define lpfc_mbox_hdr_subsystem_WORD word6 906 #define lpfc_mbox_hdr_port_number_SHIFT 16 907 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 908 #define lpfc_mbox_hdr_port_number_WORD word6 909 #define lpfc_mbox_hdr_domain_SHIFT 24 910 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 911 #define lpfc_mbox_hdr_domain_WORD word6 912 uint32_t timeout; 913 uint32_t request_length; 914 uint32_t word9; 915 #define lpfc_mbox_hdr_version_SHIFT 0 916 #define lpfc_mbox_hdr_version_MASK 0x000000FF 917 #define lpfc_mbox_hdr_version_WORD word9 918 #define lpfc_mbox_hdr_pf_num_SHIFT 16 919 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 920 #define lpfc_mbox_hdr_pf_num_WORD word9 921 #define lpfc_mbox_hdr_vh_num_SHIFT 24 922 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 923 #define lpfc_mbox_hdr_vh_num_WORD word9 924 #define LPFC_Q_CREATE_VERSION_2 2 925 #define LPFC_Q_CREATE_VERSION_1 1 926 #define LPFC_Q_CREATE_VERSION_0 0 927 #define LPFC_OPCODE_VERSION_0 0 928 #define LPFC_OPCODE_VERSION_1 1 929 } request; 930 struct { 931 uint32_t word6; 932 #define lpfc_mbox_hdr_opcode_SHIFT 0 933 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 934 #define lpfc_mbox_hdr_opcode_WORD word6 935 #define lpfc_mbox_hdr_subsystem_SHIFT 8 936 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 937 #define lpfc_mbox_hdr_subsystem_WORD word6 938 #define lpfc_mbox_hdr_domain_SHIFT 24 939 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 940 #define lpfc_mbox_hdr_domain_WORD word6 941 uint32_t word7; 942 #define lpfc_mbox_hdr_status_SHIFT 0 943 #define lpfc_mbox_hdr_status_MASK 0x000000FF 944 #define lpfc_mbox_hdr_status_WORD word7 945 #define lpfc_mbox_hdr_add_status_SHIFT 8 946 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 947 #define lpfc_mbox_hdr_add_status_WORD word7 948 uint32_t response_length; 949 uint32_t actual_response_length; 950 } response; 951 }; 952 953 /* Mailbox Header structures. 954 * struct mbox_header is defined for first generation SLI4_CFG mailbox 955 * calls deployed for BE-based ports. 956 * 957 * struct sli4_mbox_header is defined for second generation SLI4 958 * ports that don't deploy the SLI4_CFG mechanism. 959 */ 960 struct mbox_header { 961 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 962 union lpfc_sli4_cfg_shdr cfg_shdr; 963 }; 964 965 #define LPFC_EXTENT_LOCAL 0 966 #define LPFC_TIMEOUT_DEFAULT 0 967 #define LPFC_EXTENT_VERSION_DEFAULT 0 968 969 /* Subsystem Definitions */ 970 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 971 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 972 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 973 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 974 975 /* Device Specific Definitions */ 976 977 /* The HOST ENDIAN defines are in Big Endian format. */ 978 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 979 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 980 981 /* Common Opcodes */ 982 #define LPFC_MBOX_OPCODE_NA 0x00 983 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 984 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 985 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 986 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 987 #define LPFC_MBOX_OPCODE_NOP 0x21 988 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 989 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 990 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 991 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 992 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 993 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 994 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 995 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 996 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 997 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 998 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 999 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1000 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1001 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1002 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1003 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1004 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1005 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1006 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1007 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1008 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1009 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1010 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1011 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1012 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1013 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1014 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1015 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1016 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1017 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1018 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1019 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1020 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1021 1022 /* FCoE Opcodes */ 1023 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1024 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1025 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1026 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1027 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1028 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1029 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1030 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1031 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1032 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1033 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1034 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1035 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1036 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1037 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1038 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1039 1040 /* Low level Opcodes */ 1041 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1042 1043 /* Mailbox command structures */ 1044 struct eq_context { 1045 uint32_t word0; 1046 #define lpfc_eq_context_size_SHIFT 31 1047 #define lpfc_eq_context_size_MASK 0x00000001 1048 #define lpfc_eq_context_size_WORD word0 1049 #define LPFC_EQE_SIZE_4 0x0 1050 #define LPFC_EQE_SIZE_16 0x1 1051 #define lpfc_eq_context_valid_SHIFT 29 1052 #define lpfc_eq_context_valid_MASK 0x00000001 1053 #define lpfc_eq_context_valid_WORD word0 1054 #define lpfc_eq_context_autovalid_SHIFT 28 1055 #define lpfc_eq_context_autovalid_MASK 0x00000001 1056 #define lpfc_eq_context_autovalid_WORD word0 1057 uint32_t word1; 1058 #define lpfc_eq_context_count_SHIFT 26 1059 #define lpfc_eq_context_count_MASK 0x00000003 1060 #define lpfc_eq_context_count_WORD word1 1061 #define LPFC_EQ_CNT_256 0x0 1062 #define LPFC_EQ_CNT_512 0x1 1063 #define LPFC_EQ_CNT_1024 0x2 1064 #define LPFC_EQ_CNT_2048 0x3 1065 #define LPFC_EQ_CNT_4096 0x4 1066 uint32_t word2; 1067 #define lpfc_eq_context_delay_multi_SHIFT 13 1068 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1069 #define lpfc_eq_context_delay_multi_WORD word2 1070 uint32_t reserved3; 1071 }; 1072 1073 struct eq_delay_info { 1074 uint32_t eq_id; 1075 uint32_t phase; 1076 uint32_t delay_multi; 1077 }; 1078 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1079 1080 struct sgl_page_pairs { 1081 uint32_t sgl_pg0_addr_lo; 1082 uint32_t sgl_pg0_addr_hi; 1083 uint32_t sgl_pg1_addr_lo; 1084 uint32_t sgl_pg1_addr_hi; 1085 }; 1086 1087 struct lpfc_mbx_post_sgl_pages { 1088 struct mbox_header header; 1089 uint32_t word0; 1090 #define lpfc_post_sgl_pages_xri_SHIFT 0 1091 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1092 #define lpfc_post_sgl_pages_xri_WORD word0 1093 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1094 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1095 #define lpfc_post_sgl_pages_xricnt_WORD word0 1096 struct sgl_page_pairs sgl_pg_pairs[1]; 1097 }; 1098 1099 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1100 struct lpfc_mbx_post_uembed_sgl_page1 { 1101 union lpfc_sli4_cfg_shdr cfg_shdr; 1102 uint32_t word0; 1103 struct sgl_page_pairs sgl_pg_pairs; 1104 }; 1105 1106 struct lpfc_mbx_sge { 1107 uint32_t pa_lo; 1108 uint32_t pa_hi; 1109 uint32_t length; 1110 }; 1111 1112 struct lpfc_mbx_nembed_cmd { 1113 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1114 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1115 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1116 }; 1117 1118 struct lpfc_mbx_nembed_sge_virt { 1119 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1120 }; 1121 1122 struct lpfc_mbx_eq_create { 1123 struct mbox_header header; 1124 union { 1125 struct { 1126 uint32_t word0; 1127 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1128 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1129 #define lpfc_mbx_eq_create_num_pages_WORD word0 1130 struct eq_context context; 1131 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1132 } request; 1133 struct { 1134 uint32_t word0; 1135 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1136 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1137 #define lpfc_mbx_eq_create_q_id_WORD word0 1138 } response; 1139 } u; 1140 }; 1141 1142 struct lpfc_mbx_modify_eq_delay { 1143 struct mbox_header header; 1144 union { 1145 struct { 1146 uint32_t num_eq; 1147 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1148 } request; 1149 struct { 1150 uint32_t word0; 1151 } response; 1152 } u; 1153 }; 1154 1155 struct lpfc_mbx_eq_destroy { 1156 struct mbox_header header; 1157 union { 1158 struct { 1159 uint32_t word0; 1160 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1161 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1162 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1163 } request; 1164 struct { 1165 uint32_t word0; 1166 } response; 1167 } u; 1168 }; 1169 1170 struct lpfc_mbx_nop { 1171 struct mbox_header header; 1172 uint32_t context[2]; 1173 }; 1174 1175 1176 1177 struct lpfc_mbx_set_ras_fwlog { 1178 struct mbox_header header; 1179 union { 1180 struct { 1181 uint32_t word4; 1182 #define lpfc_fwlog_enable_SHIFT 0 1183 #define lpfc_fwlog_enable_MASK 0x00000001 1184 #define lpfc_fwlog_enable_WORD word4 1185 #define lpfc_fwlog_loglvl_SHIFT 8 1186 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1187 #define lpfc_fwlog_loglvl_WORD word4 1188 #define lpfc_fwlog_ra_SHIFT 15 1189 #define lpfc_fwlog_ra_WORD 0x00000008 1190 #define lpfc_fwlog_buffcnt_SHIFT 16 1191 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1192 #define lpfc_fwlog_buffcnt_WORD word4 1193 #define lpfc_fwlog_buffsz_SHIFT 24 1194 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1195 #define lpfc_fwlog_buffsz_WORD word4 1196 uint32_t word5; 1197 #define lpfc_fwlog_acqe_SHIFT 0 1198 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1199 #define lpfc_fwlog_acqe_WORD word5 1200 #define lpfc_fwlog_cqid_SHIFT 16 1201 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1202 #define lpfc_fwlog_cqid_WORD word5 1203 #define LPFC_MAX_FWLOG_PAGE 16 1204 struct dma_address lwpd; 1205 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1206 } request; 1207 struct { 1208 uint32_t word0; 1209 } response; 1210 } u; 1211 }; 1212 1213 1214 struct cq_context { 1215 uint32_t word0; 1216 #define lpfc_cq_context_event_SHIFT 31 1217 #define lpfc_cq_context_event_MASK 0x00000001 1218 #define lpfc_cq_context_event_WORD word0 1219 #define lpfc_cq_context_valid_SHIFT 29 1220 #define lpfc_cq_context_valid_MASK 0x00000001 1221 #define lpfc_cq_context_valid_WORD word0 1222 #define lpfc_cq_context_count_SHIFT 27 1223 #define lpfc_cq_context_count_MASK 0x00000003 1224 #define lpfc_cq_context_count_WORD word0 1225 #define LPFC_CQ_CNT_256 0x0 1226 #define LPFC_CQ_CNT_512 0x1 1227 #define LPFC_CQ_CNT_1024 0x2 1228 #define LPFC_CQ_CNT_WORD7 0x3 1229 #define lpfc_cq_context_autovalid_SHIFT 15 1230 #define lpfc_cq_context_autovalid_MASK 0x00000001 1231 #define lpfc_cq_context_autovalid_WORD word0 1232 uint32_t word1; 1233 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1234 #define lpfc_cq_eq_id_MASK 0x000000FF 1235 #define lpfc_cq_eq_id_WORD word1 1236 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1237 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1238 #define lpfc_cq_eq_id_2_WORD word1 1239 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1240 uint32_t reserved1; 1241 }; 1242 1243 struct lpfc_mbx_cq_create { 1244 struct mbox_header header; 1245 union { 1246 struct { 1247 uint32_t word0; 1248 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1249 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1250 #define lpfc_mbx_cq_create_page_size_WORD word0 1251 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1252 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1253 #define lpfc_mbx_cq_create_num_pages_WORD word0 1254 struct cq_context context; 1255 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1256 } request; 1257 struct { 1258 uint32_t word0; 1259 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1260 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1261 #define lpfc_mbx_cq_create_q_id_WORD word0 1262 } response; 1263 } u; 1264 }; 1265 1266 struct lpfc_mbx_cq_create_set { 1267 union lpfc_sli4_cfg_shdr cfg_shdr; 1268 union { 1269 struct { 1270 uint32_t word0; 1271 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1272 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1273 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1274 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1275 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1276 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1277 uint32_t word1; 1278 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1279 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1280 #define lpfc_mbx_cq_create_set_evt_WORD word1 1281 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1282 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1283 #define lpfc_mbx_cq_create_set_valid_WORD word1 1284 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1285 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1286 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1287 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1288 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1289 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1290 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1291 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1292 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1293 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1294 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1295 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1296 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1297 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1298 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1299 uint32_t word2; 1300 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1301 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1302 #define lpfc_mbx_cq_create_set_arm_WORD word2 1303 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1304 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1305 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1306 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1307 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1308 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1309 uint32_t word3; 1310 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1311 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1312 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1313 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1314 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1315 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1316 uint32_t word4; 1317 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1318 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1319 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1320 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1321 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1322 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1323 uint32_t word5; 1324 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1325 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1326 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1327 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1328 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1329 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1330 uint32_t word6; 1331 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1332 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1333 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1334 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1335 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1336 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1337 uint32_t word7; 1338 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1339 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1340 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1341 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1342 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1343 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1344 uint32_t word8; 1345 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1346 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1347 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1348 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1349 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1350 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1351 uint32_t word9; 1352 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1353 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1354 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1355 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1356 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1357 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1358 uint32_t word10; 1359 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1360 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1361 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1362 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1363 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1364 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1365 struct dma_address page[1]; 1366 } request; 1367 struct { 1368 uint32_t word0; 1369 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1370 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1371 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1372 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1373 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1374 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1375 } response; 1376 } u; 1377 }; 1378 1379 struct lpfc_mbx_cq_destroy { 1380 struct mbox_header header; 1381 union { 1382 struct { 1383 uint32_t word0; 1384 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1385 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1386 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1387 } request; 1388 struct { 1389 uint32_t word0; 1390 } response; 1391 } u; 1392 }; 1393 1394 struct wq_context { 1395 uint32_t reserved0; 1396 uint32_t reserved1; 1397 uint32_t reserved2; 1398 uint32_t reserved3; 1399 }; 1400 1401 struct lpfc_mbx_wq_create { 1402 struct mbox_header header; 1403 union { 1404 struct { /* Version 0 Request */ 1405 uint32_t word0; 1406 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1407 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1408 #define lpfc_mbx_wq_create_num_pages_WORD word0 1409 #define lpfc_mbx_wq_create_dua_SHIFT 8 1410 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1411 #define lpfc_mbx_wq_create_dua_WORD word0 1412 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1413 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1414 #define lpfc_mbx_wq_create_cq_id_WORD word0 1415 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1416 uint32_t word9; 1417 #define lpfc_mbx_wq_create_bua_SHIFT 0 1418 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1419 #define lpfc_mbx_wq_create_bua_WORD word9 1420 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1421 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1422 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1423 } request; 1424 struct { /* Version 1 Request */ 1425 uint32_t word0; /* Word 0 is the same as in v0 */ 1426 uint32_t word1; 1427 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1428 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1429 #define lpfc_mbx_wq_create_page_size_WORD word1 1430 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1431 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1432 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1433 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1434 #define lpfc_mbx_wq_create_doe_SHIFT 14 1435 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1436 #define lpfc_mbx_wq_create_doe_WORD word1 1437 #define lpfc_mbx_wq_create_toe_SHIFT 13 1438 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1439 #define lpfc_mbx_wq_create_toe_WORD word1 1440 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1441 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1442 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1443 #define LPFC_WQ_WQE_SIZE_64 0x5 1444 #define LPFC_WQ_WQE_SIZE_128 0x6 1445 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1446 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1447 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1448 uint32_t word2; 1449 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1450 } request_1; 1451 struct { 1452 uint32_t word0; 1453 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1454 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1455 #define lpfc_mbx_wq_create_q_id_WORD word0 1456 uint32_t doorbell_offset; 1457 uint32_t word2; 1458 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1459 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1460 #define lpfc_mbx_wq_create_bar_set_WORD word2 1461 #define WQ_PCI_BAR_0_AND_1 0x00 1462 #define WQ_PCI_BAR_2_AND_3 0x01 1463 #define WQ_PCI_BAR_4_AND_5 0x02 1464 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1465 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1466 #define lpfc_mbx_wq_create_db_format_WORD word2 1467 } response; 1468 struct { 1469 uint32_t word0; 1470 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1471 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1472 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1473 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1474 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1475 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1476 uint32_t word1; 1477 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1478 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1479 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1480 uint32_t doorbell_offset; 1481 uint32_t word3; 1482 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1483 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1484 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1485 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1486 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1487 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1488 uint32_t dpp_offset; 1489 } response_1; 1490 } u; 1491 }; 1492 1493 struct lpfc_mbx_wq_destroy { 1494 struct mbox_header header; 1495 union { 1496 struct { 1497 uint32_t word0; 1498 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1499 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1500 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1501 } request; 1502 struct { 1503 uint32_t word0; 1504 } response; 1505 } u; 1506 }; 1507 1508 #define LPFC_HDR_BUF_SIZE 128 1509 #define LPFC_DATA_BUF_SIZE 2048 1510 #define LPFC_NVMET_DATA_BUF_SIZE 128 1511 struct rq_context { 1512 uint32_t word0; 1513 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1514 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1515 #define lpfc_rq_context_rqe_count_WORD word0 1516 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1517 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1518 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1519 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1520 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1521 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1522 #define lpfc_rq_context_rqe_count_1_WORD word0 1523 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1524 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1525 #define lpfc_rq_context_rqe_size_WORD word0 1526 #define LPFC_RQE_SIZE_8 2 1527 #define LPFC_RQE_SIZE_16 3 1528 #define LPFC_RQE_SIZE_32 4 1529 #define LPFC_RQE_SIZE_64 5 1530 #define LPFC_RQE_SIZE_128 6 1531 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1532 #define lpfc_rq_context_page_size_MASK 0x000000FF 1533 #define lpfc_rq_context_page_size_WORD word0 1534 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1535 uint32_t word1; 1536 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1537 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1538 #define lpfc_rq_context_data_size_WORD word1 1539 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1540 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1541 #define lpfc_rq_context_hdr_size_WORD word1 1542 uint32_t word2; 1543 #define lpfc_rq_context_cq_id_SHIFT 16 1544 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1545 #define lpfc_rq_context_cq_id_WORD word2 1546 #define lpfc_rq_context_buf_size_SHIFT 0 1547 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1548 #define lpfc_rq_context_buf_size_WORD word2 1549 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1550 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1551 #define lpfc_rq_context_base_cq_WORD word2 1552 uint32_t buffer_size; /* Version 1 Only */ 1553 }; 1554 1555 struct lpfc_mbx_rq_create { 1556 struct mbox_header header; 1557 union { 1558 struct { 1559 uint32_t word0; 1560 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1561 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1562 #define lpfc_mbx_rq_create_num_pages_WORD word0 1563 #define lpfc_mbx_rq_create_dua_SHIFT 16 1564 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1565 #define lpfc_mbx_rq_create_dua_WORD word0 1566 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1567 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1568 #define lpfc_mbx_rq_create_bqu_WORD word0 1569 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1570 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1571 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1572 struct rq_context context; 1573 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1574 } request; 1575 struct { 1576 uint32_t word0; 1577 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1578 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1579 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1580 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1581 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1582 #define lpfc_mbx_rq_create_q_id_WORD word0 1583 uint32_t doorbell_offset; 1584 uint32_t word2; 1585 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1586 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1587 #define lpfc_mbx_rq_create_bar_set_WORD word2 1588 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1589 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1590 #define lpfc_mbx_rq_create_db_format_WORD word2 1591 } response; 1592 } u; 1593 }; 1594 1595 struct lpfc_mbx_rq_create_v2 { 1596 union lpfc_sli4_cfg_shdr cfg_shdr; 1597 union { 1598 struct { 1599 uint32_t word0; 1600 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1601 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1602 #define lpfc_mbx_rq_create_num_pages_WORD word0 1603 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1604 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1605 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1606 #define lpfc_mbx_rq_create_dua_SHIFT 16 1607 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1608 #define lpfc_mbx_rq_create_dua_WORD word0 1609 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1610 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1611 #define lpfc_mbx_rq_create_bqu_WORD word0 1612 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1613 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1614 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1615 #define lpfc_mbx_rq_create_dim_SHIFT 29 1616 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1617 #define lpfc_mbx_rq_create_dim_WORD word0 1618 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1619 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1620 #define lpfc_mbx_rq_create_dfd_WORD word0 1621 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1622 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1623 #define lpfc_mbx_rq_create_dnb_WORD word0 1624 struct rq_context context; 1625 struct dma_address page[1]; 1626 } request; 1627 struct { 1628 uint32_t word0; 1629 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1630 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1631 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1632 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1633 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1634 #define lpfc_mbx_rq_create_q_id_WORD word0 1635 uint32_t doorbell_offset; 1636 uint32_t word2; 1637 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1638 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1639 #define lpfc_mbx_rq_create_bar_set_WORD word2 1640 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1641 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1642 #define lpfc_mbx_rq_create_db_format_WORD word2 1643 } response; 1644 } u; 1645 }; 1646 1647 struct lpfc_mbx_rq_destroy { 1648 struct mbox_header header; 1649 union { 1650 struct { 1651 uint32_t word0; 1652 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1653 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1654 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1655 } request; 1656 struct { 1657 uint32_t word0; 1658 } response; 1659 } u; 1660 }; 1661 1662 struct mq_context { 1663 uint32_t word0; 1664 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1665 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1666 #define lpfc_mq_context_cq_id_WORD word0 1667 #define lpfc_mq_context_ring_size_SHIFT 16 1668 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1669 #define lpfc_mq_context_ring_size_WORD word0 1670 #define LPFC_MQ_RING_SIZE_16 0x5 1671 #define LPFC_MQ_RING_SIZE_32 0x6 1672 #define LPFC_MQ_RING_SIZE_64 0x7 1673 #define LPFC_MQ_RING_SIZE_128 0x8 1674 uint32_t word1; 1675 #define lpfc_mq_context_valid_SHIFT 31 1676 #define lpfc_mq_context_valid_MASK 0x00000001 1677 #define lpfc_mq_context_valid_WORD word1 1678 uint32_t reserved2; 1679 uint32_t reserved3; 1680 }; 1681 1682 struct lpfc_mbx_mq_create { 1683 struct mbox_header header; 1684 union { 1685 struct { 1686 uint32_t word0; 1687 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1688 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1689 #define lpfc_mbx_mq_create_num_pages_WORD word0 1690 struct mq_context context; 1691 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1692 } request; 1693 struct { 1694 uint32_t word0; 1695 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1696 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1697 #define lpfc_mbx_mq_create_q_id_WORD word0 1698 } response; 1699 } u; 1700 }; 1701 1702 struct lpfc_mbx_mq_create_ext { 1703 struct mbox_header header; 1704 union { 1705 struct { 1706 uint32_t word0; 1707 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1708 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1709 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1710 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1711 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1712 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1713 uint32_t async_evt_bmap; 1714 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1715 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1716 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1717 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1718 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1719 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1720 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1721 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1722 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1723 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1724 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1725 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1726 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1727 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1728 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1729 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1730 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1731 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1732 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1733 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1734 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1735 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1736 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1737 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1738 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1739 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1740 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1741 struct mq_context context; 1742 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1743 } request; 1744 struct { 1745 uint32_t word0; 1746 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1747 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1748 #define lpfc_mbx_mq_create_q_id_WORD word0 1749 } response; 1750 } u; 1751 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1752 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1753 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1754 }; 1755 1756 struct lpfc_mbx_mq_destroy { 1757 struct mbox_header header; 1758 union { 1759 struct { 1760 uint32_t word0; 1761 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1762 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1763 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1764 } request; 1765 struct { 1766 uint32_t word0; 1767 } response; 1768 } u; 1769 }; 1770 1771 /* Start Gen 2 SLI4 Mailbox definitions: */ 1772 1773 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1774 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1775 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1776 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1777 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1778 1779 struct lpfc_mbx_get_rsrc_extent_info { 1780 struct mbox_header header; 1781 union { 1782 struct { 1783 uint32_t word4; 1784 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1785 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1786 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1787 } req; 1788 struct { 1789 uint32_t word4; 1790 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1791 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1792 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1793 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1794 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1795 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1796 } rsp; 1797 } u; 1798 }; 1799 1800 struct lpfc_mbx_query_fw_config { 1801 struct mbox_header header; 1802 struct { 1803 uint32_t config_number; 1804 #define LPFC_FC_FCOE 0x00000007 1805 uint32_t asic_revision; 1806 uint32_t physical_port; 1807 uint32_t function_mode; 1808 #define LPFC_FCOE_INI_MODE 0x00000040 1809 #define LPFC_FCOE_TGT_MODE 0x00000080 1810 #define LPFC_DUA_MODE 0x00000800 1811 uint32_t ulp0_mode; 1812 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1813 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1814 uint32_t ulp0_nap_words[12]; 1815 uint32_t ulp1_mode; 1816 uint32_t ulp1_nap_words[12]; 1817 uint32_t function_capabilities; 1818 uint32_t cqid_base; 1819 uint32_t cqid_tot; 1820 uint32_t eqid_base; 1821 uint32_t eqid_tot; 1822 uint32_t ulp0_nap2_words[2]; 1823 uint32_t ulp1_nap2_words[2]; 1824 } rsp; 1825 }; 1826 1827 struct lpfc_mbx_set_beacon_config { 1828 struct mbox_header header; 1829 uint32_t word4; 1830 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1831 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1832 #define lpfc_mbx_set_beacon_port_num_WORD word4 1833 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1834 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1835 #define lpfc_mbx_set_beacon_port_type_WORD word4 1836 #define lpfc_mbx_set_beacon_state_SHIFT 8 1837 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1838 #define lpfc_mbx_set_beacon_state_WORD word4 1839 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1840 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1841 #define lpfc_mbx_set_beacon_duration_WORD word4 1842 1843 /* COMMON_SET_BEACON_CONFIG_V1 */ 1844 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1845 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1846 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1847 uint32_t word5; /* RESERVED */ 1848 }; 1849 1850 struct lpfc_id_range { 1851 uint32_t word5; 1852 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1853 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1854 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1855 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1856 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1857 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1858 }; 1859 1860 struct lpfc_mbx_set_link_diag_state { 1861 struct mbox_header header; 1862 union { 1863 struct { 1864 uint32_t word0; 1865 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1866 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1867 #define lpfc_mbx_set_diag_state_diag_WORD word0 1868 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1869 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1870 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1871 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1872 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1873 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1874 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1875 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1876 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1877 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1878 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1879 } req; 1880 struct { 1881 uint32_t word0; 1882 } rsp; 1883 } u; 1884 }; 1885 1886 struct lpfc_mbx_set_link_diag_loopback { 1887 struct mbox_header header; 1888 union { 1889 struct { 1890 uint32_t word0; 1891 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1892 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1893 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1894 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1895 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1896 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1897 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1898 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1899 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1900 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1901 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1902 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1903 } req; 1904 struct { 1905 uint32_t word0; 1906 } rsp; 1907 } u; 1908 }; 1909 1910 struct lpfc_mbx_run_link_diag_test { 1911 struct mbox_header header; 1912 union { 1913 struct { 1914 uint32_t word0; 1915 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1916 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1917 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1918 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1919 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1920 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1921 uint32_t word1; 1922 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1923 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1924 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1925 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1926 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1927 #define lpfc_mbx_run_diag_test_loops_WORD word1 1928 uint32_t word2; 1929 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1930 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1931 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1932 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1933 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1934 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1935 } req; 1936 struct { 1937 uint32_t word0; 1938 } rsp; 1939 } u; 1940 }; 1941 1942 /* 1943 * struct lpfc_mbx_alloc_rsrc_extents: 1944 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1945 * 6 words of header + 4 words of shared subcommand header + 1946 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1947 * 1948 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1949 * for extents payload. 1950 * 1951 * 212/2 (bytes per extent) = 106 extents. 1952 * 106/2 (extents per word) = 53 words. 1953 * lpfc_id_range id is statically size to 53. 1954 * 1955 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1956 * extent ranges. For ALLOC, the type and cnt are required. 1957 * For GET_ALLOCATED, only the type is required. 1958 */ 1959 struct lpfc_mbx_alloc_rsrc_extents { 1960 struct mbox_header header; 1961 union { 1962 struct { 1963 uint32_t word4; 1964 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1965 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1966 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1967 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1968 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1969 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1970 } req; 1971 struct { 1972 uint32_t word4; 1973 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1974 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1975 #define lpfc_mbx_rsrc_cnt_WORD word4 1976 struct lpfc_id_range id[53]; 1977 } rsp; 1978 } u; 1979 }; 1980 1981 /* 1982 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1983 * structure shares the same SHIFT/MASK/WORD defines provided in the 1984 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1985 * the structures defined above. This non-embedded structure provides for the 1986 * maximum number of extents supported by the port. 1987 */ 1988 struct lpfc_mbx_nembed_rsrc_extent { 1989 union lpfc_sli4_cfg_shdr cfg_shdr; 1990 uint32_t word4; 1991 struct lpfc_id_range id; 1992 }; 1993 1994 struct lpfc_mbx_dealloc_rsrc_extents { 1995 struct mbox_header header; 1996 struct { 1997 uint32_t word4; 1998 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1999 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2000 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2001 } req; 2002 2003 }; 2004 2005 /* Start SLI4 FCoE specific mbox structures. */ 2006 2007 struct lpfc_mbx_post_hdr_tmpl { 2008 struct mbox_header header; 2009 uint32_t word10; 2010 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2011 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2012 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2013 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2014 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2015 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2016 uint32_t rpi_paddr_lo; 2017 uint32_t rpi_paddr_hi; 2018 }; 2019 2020 struct sli4_sge { /* SLI-4 */ 2021 uint32_t addr_hi; 2022 uint32_t addr_lo; 2023 2024 uint32_t word2; 2025 #define lpfc_sli4_sge_offset_SHIFT 0 2026 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2027 #define lpfc_sli4_sge_offset_WORD word2 2028 #define lpfc_sli4_sge_type_SHIFT 27 2029 #define lpfc_sli4_sge_type_MASK 0x0000000F 2030 #define lpfc_sli4_sge_type_WORD word2 2031 #define LPFC_SGE_TYPE_DATA 0x0 2032 #define LPFC_SGE_TYPE_DIF 0x4 2033 #define LPFC_SGE_TYPE_LSP 0x5 2034 #define LPFC_SGE_TYPE_PEDIF 0x6 2035 #define LPFC_SGE_TYPE_PESEED 0x7 2036 #define LPFC_SGE_TYPE_DISEED 0x8 2037 #define LPFC_SGE_TYPE_ENC 0x9 2038 #define LPFC_SGE_TYPE_ATM 0xA 2039 #define LPFC_SGE_TYPE_SKIP 0xC 2040 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2041 #define lpfc_sli4_sge_last_MASK 0x00000001 2042 #define lpfc_sli4_sge_last_WORD word2 2043 uint32_t sge_len; 2044 }; 2045 2046 struct sli4_sge_diseed { /* SLI-4 */ 2047 uint32_t ref_tag; 2048 uint32_t ref_tag_tran; 2049 2050 uint32_t word2; 2051 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2052 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2053 #define lpfc_sli4_sge_dif_apptran_WORD word2 2054 #define lpfc_sli4_sge_dif_af_SHIFT 24 2055 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2056 #define lpfc_sli4_sge_dif_af_WORD word2 2057 #define lpfc_sli4_sge_dif_na_SHIFT 25 2058 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2059 #define lpfc_sli4_sge_dif_na_WORD word2 2060 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2061 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2062 #define lpfc_sli4_sge_dif_hi_WORD word2 2063 #define lpfc_sli4_sge_dif_type_SHIFT 27 2064 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2065 #define lpfc_sli4_sge_dif_type_WORD word2 2066 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2067 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2068 #define lpfc_sli4_sge_dif_last_WORD word2 2069 uint32_t word3; 2070 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2071 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2072 #define lpfc_sli4_sge_dif_apptag_WORD word3 2073 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2074 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2075 #define lpfc_sli4_sge_dif_bs_WORD word3 2076 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2077 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2078 #define lpfc_sli4_sge_dif_ai_WORD word3 2079 #define lpfc_sli4_sge_dif_me_SHIFT 20 2080 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2081 #define lpfc_sli4_sge_dif_me_WORD word3 2082 #define lpfc_sli4_sge_dif_re_SHIFT 21 2083 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2084 #define lpfc_sli4_sge_dif_re_WORD word3 2085 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2086 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2087 #define lpfc_sli4_sge_dif_ce_WORD word3 2088 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2089 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2090 #define lpfc_sli4_sge_dif_nr_WORD word3 2091 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2092 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2093 #define lpfc_sli4_sge_dif_oprx_WORD word3 2094 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2095 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2096 #define lpfc_sli4_sge_dif_optx_WORD word3 2097 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2098 }; 2099 2100 struct fcf_record { 2101 uint32_t max_rcv_size; 2102 uint32_t fka_adv_period; 2103 uint32_t fip_priority; 2104 uint32_t word3; 2105 #define lpfc_fcf_record_mac_0_SHIFT 0 2106 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2107 #define lpfc_fcf_record_mac_0_WORD word3 2108 #define lpfc_fcf_record_mac_1_SHIFT 8 2109 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2110 #define lpfc_fcf_record_mac_1_WORD word3 2111 #define lpfc_fcf_record_mac_2_SHIFT 16 2112 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2113 #define lpfc_fcf_record_mac_2_WORD word3 2114 #define lpfc_fcf_record_mac_3_SHIFT 24 2115 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2116 #define lpfc_fcf_record_mac_3_WORD word3 2117 uint32_t word4; 2118 #define lpfc_fcf_record_mac_4_SHIFT 0 2119 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2120 #define lpfc_fcf_record_mac_4_WORD word4 2121 #define lpfc_fcf_record_mac_5_SHIFT 8 2122 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2123 #define lpfc_fcf_record_mac_5_WORD word4 2124 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2125 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2126 #define lpfc_fcf_record_fcf_avail_WORD word4 2127 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2128 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2129 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2130 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2131 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2132 uint32_t word5; 2133 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2134 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2135 #define lpfc_fcf_record_fab_name_0_WORD word5 2136 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2137 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2138 #define lpfc_fcf_record_fab_name_1_WORD word5 2139 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2140 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2141 #define lpfc_fcf_record_fab_name_2_WORD word5 2142 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2143 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2144 #define lpfc_fcf_record_fab_name_3_WORD word5 2145 uint32_t word6; 2146 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2147 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2148 #define lpfc_fcf_record_fab_name_4_WORD word6 2149 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2150 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2151 #define lpfc_fcf_record_fab_name_5_WORD word6 2152 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2153 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2154 #define lpfc_fcf_record_fab_name_6_WORD word6 2155 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2156 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2157 #define lpfc_fcf_record_fab_name_7_WORD word6 2158 uint32_t word7; 2159 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2160 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2161 #define lpfc_fcf_record_fc_map_0_WORD word7 2162 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2163 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2164 #define lpfc_fcf_record_fc_map_1_WORD word7 2165 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2166 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2167 #define lpfc_fcf_record_fc_map_2_WORD word7 2168 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2169 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2170 #define lpfc_fcf_record_fcf_valid_WORD word7 2171 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2172 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2173 #define lpfc_fcf_record_fcf_fc_WORD word7 2174 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2175 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2176 #define lpfc_fcf_record_fcf_sol_WORD word7 2177 uint32_t word8; 2178 #define lpfc_fcf_record_fcf_index_SHIFT 0 2179 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2180 #define lpfc_fcf_record_fcf_index_WORD word8 2181 #define lpfc_fcf_record_fcf_state_SHIFT 16 2182 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2183 #define lpfc_fcf_record_fcf_state_WORD word8 2184 uint8_t vlan_bitmap[512]; 2185 uint32_t word137; 2186 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2187 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2188 #define lpfc_fcf_record_switch_name_0_WORD word137 2189 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2190 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2191 #define lpfc_fcf_record_switch_name_1_WORD word137 2192 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2193 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2194 #define lpfc_fcf_record_switch_name_2_WORD word137 2195 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2196 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2197 #define lpfc_fcf_record_switch_name_3_WORD word137 2198 uint32_t word138; 2199 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2200 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2201 #define lpfc_fcf_record_switch_name_4_WORD word138 2202 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2203 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2204 #define lpfc_fcf_record_switch_name_5_WORD word138 2205 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2206 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2207 #define lpfc_fcf_record_switch_name_6_WORD word138 2208 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2209 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2210 #define lpfc_fcf_record_switch_name_7_WORD word138 2211 }; 2212 2213 struct lpfc_mbx_read_fcf_tbl { 2214 union lpfc_sli4_cfg_shdr cfg_shdr; 2215 union { 2216 struct { 2217 uint32_t word10; 2218 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2219 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2220 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2221 } request; 2222 struct { 2223 uint32_t eventag; 2224 } response; 2225 } u; 2226 uint32_t word11; 2227 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2228 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2229 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2230 }; 2231 2232 struct lpfc_mbx_add_fcf_tbl_entry { 2233 union lpfc_sli4_cfg_shdr cfg_shdr; 2234 uint32_t word10; 2235 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2236 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2237 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2238 struct lpfc_mbx_sge fcf_sge; 2239 }; 2240 2241 struct lpfc_mbx_del_fcf_tbl_entry { 2242 struct mbox_header header; 2243 uint32_t word10; 2244 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2245 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2246 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2247 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2248 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2249 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2250 }; 2251 2252 struct lpfc_mbx_redisc_fcf_tbl { 2253 struct mbox_header header; 2254 uint32_t word10; 2255 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2256 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2257 #define lpfc_mbx_redisc_fcf_count_WORD word10 2258 uint32_t resvd; 2259 uint32_t word12; 2260 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2261 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2262 #define lpfc_mbx_redisc_fcf_index_WORD word12 2263 }; 2264 2265 /* Status field for embedded SLI_CONFIG mailbox command */ 2266 #define STATUS_SUCCESS 0x0 2267 #define STATUS_FAILED 0x1 2268 #define STATUS_ILLEGAL_REQUEST 0x2 2269 #define STATUS_ILLEGAL_FIELD 0x3 2270 #define STATUS_INSUFFICIENT_BUFFER 0x4 2271 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2272 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2273 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2274 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2275 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2276 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2277 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2278 #define STATUS_ASSERT_FAILED 0x1e 2279 #define STATUS_INVALID_SESSION 0x1f 2280 #define STATUS_INVALID_CONNECTION 0x20 2281 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2282 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2283 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2284 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2285 #define STATUS_FLASHROM_READ_FAILED 0x27 2286 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2287 #define STATUS_ERROR_ACITMAIN 0x2a 2288 #define STATUS_REBOOT_REQUIRED 0x2c 2289 #define STATUS_FCF_IN_USE 0x3a 2290 #define STATUS_FCF_TABLE_EMPTY 0x43 2291 2292 /* 2293 * Additional status field for embedded SLI_CONFIG mailbox 2294 * command. 2295 */ 2296 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2297 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2298 #define ADD_STATUS_INVALID_REQUEST 0x4B 2299 2300 struct lpfc_mbx_sli4_config { 2301 struct mbox_header header; 2302 }; 2303 2304 struct lpfc_mbx_init_vfi { 2305 uint32_t word1; 2306 #define lpfc_init_vfi_vr_SHIFT 31 2307 #define lpfc_init_vfi_vr_MASK 0x00000001 2308 #define lpfc_init_vfi_vr_WORD word1 2309 #define lpfc_init_vfi_vt_SHIFT 30 2310 #define lpfc_init_vfi_vt_MASK 0x00000001 2311 #define lpfc_init_vfi_vt_WORD word1 2312 #define lpfc_init_vfi_vf_SHIFT 29 2313 #define lpfc_init_vfi_vf_MASK 0x00000001 2314 #define lpfc_init_vfi_vf_WORD word1 2315 #define lpfc_init_vfi_vp_SHIFT 28 2316 #define lpfc_init_vfi_vp_MASK 0x00000001 2317 #define lpfc_init_vfi_vp_WORD word1 2318 #define lpfc_init_vfi_vfi_SHIFT 0 2319 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2320 #define lpfc_init_vfi_vfi_WORD word1 2321 uint32_t word2; 2322 #define lpfc_init_vfi_vpi_SHIFT 16 2323 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2324 #define lpfc_init_vfi_vpi_WORD word2 2325 #define lpfc_init_vfi_fcfi_SHIFT 0 2326 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2327 #define lpfc_init_vfi_fcfi_WORD word2 2328 uint32_t word3; 2329 #define lpfc_init_vfi_pri_SHIFT 13 2330 #define lpfc_init_vfi_pri_MASK 0x00000007 2331 #define lpfc_init_vfi_pri_WORD word3 2332 #define lpfc_init_vfi_vf_id_SHIFT 1 2333 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2334 #define lpfc_init_vfi_vf_id_WORD word3 2335 uint32_t word4; 2336 #define lpfc_init_vfi_hop_count_SHIFT 24 2337 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2338 #define lpfc_init_vfi_hop_count_WORD word4 2339 }; 2340 #define MBX_VFI_IN_USE 0x9F02 2341 2342 2343 struct lpfc_mbx_reg_vfi { 2344 uint32_t word1; 2345 #define lpfc_reg_vfi_upd_SHIFT 29 2346 #define lpfc_reg_vfi_upd_MASK 0x00000001 2347 #define lpfc_reg_vfi_upd_WORD word1 2348 #define lpfc_reg_vfi_vp_SHIFT 28 2349 #define lpfc_reg_vfi_vp_MASK 0x00000001 2350 #define lpfc_reg_vfi_vp_WORD word1 2351 #define lpfc_reg_vfi_vfi_SHIFT 0 2352 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2353 #define lpfc_reg_vfi_vfi_WORD word1 2354 uint32_t word2; 2355 #define lpfc_reg_vfi_vpi_SHIFT 16 2356 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2357 #define lpfc_reg_vfi_vpi_WORD word2 2358 #define lpfc_reg_vfi_fcfi_SHIFT 0 2359 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2360 #define lpfc_reg_vfi_fcfi_WORD word2 2361 uint32_t wwn[2]; 2362 struct ulp_bde64 bde; 2363 uint32_t e_d_tov; 2364 uint32_t r_a_tov; 2365 uint32_t word10; 2366 #define lpfc_reg_vfi_nport_id_SHIFT 0 2367 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2368 #define lpfc_reg_vfi_nport_id_WORD word10 2369 #define lpfc_reg_vfi_bbcr_SHIFT 27 2370 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2371 #define lpfc_reg_vfi_bbcr_WORD word10 2372 #define lpfc_reg_vfi_bbscn_SHIFT 28 2373 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2374 #define lpfc_reg_vfi_bbscn_WORD word10 2375 }; 2376 2377 struct lpfc_mbx_init_vpi { 2378 uint32_t word1; 2379 #define lpfc_init_vpi_vfi_SHIFT 16 2380 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2381 #define lpfc_init_vpi_vfi_WORD word1 2382 #define lpfc_init_vpi_vpi_SHIFT 0 2383 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2384 #define lpfc_init_vpi_vpi_WORD word1 2385 }; 2386 2387 struct lpfc_mbx_read_vpi { 2388 uint32_t word1_rsvd; 2389 uint32_t word2; 2390 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2391 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2392 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2393 uint32_t word3_rsvd; 2394 uint32_t word4; 2395 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2396 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2397 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2398 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2399 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2400 #define lpfc_mbx_read_vpi_pb_WORD word4 2401 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2402 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2403 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2404 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2405 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2406 #define lpfc_mbx_read_vpi_ns_WORD word4 2407 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2408 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2409 #define lpfc_mbx_read_vpi_hl_WORD word4 2410 uint32_t word5_rsvd; 2411 uint32_t word6; 2412 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2413 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2414 #define lpfc_mbx_read_vpi_vpi_WORD word6 2415 uint32_t word7; 2416 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2417 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2418 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2419 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2420 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2421 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2422 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2423 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2424 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2425 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2426 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2427 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2428 uint32_t word8; 2429 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2430 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2431 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2432 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2433 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2434 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2435 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2436 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2437 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2438 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2439 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2440 #define lpfc_mbx_read_vpi_vv_WORD word8 2441 }; 2442 2443 struct lpfc_mbx_unreg_vfi { 2444 uint32_t word1_rsvd; 2445 uint32_t word2; 2446 #define lpfc_unreg_vfi_vfi_SHIFT 0 2447 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2448 #define lpfc_unreg_vfi_vfi_WORD word2 2449 }; 2450 2451 struct lpfc_mbx_resume_rpi { 2452 uint32_t word1; 2453 #define lpfc_resume_rpi_index_SHIFT 0 2454 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2455 #define lpfc_resume_rpi_index_WORD word1 2456 #define lpfc_resume_rpi_ii_SHIFT 30 2457 #define lpfc_resume_rpi_ii_MASK 0x00000003 2458 #define lpfc_resume_rpi_ii_WORD word1 2459 #define RESUME_INDEX_RPI 0 2460 #define RESUME_INDEX_VPI 1 2461 #define RESUME_INDEX_VFI 2 2462 #define RESUME_INDEX_FCFI 3 2463 uint32_t event_tag; 2464 }; 2465 2466 #define REG_FCF_INVALID_QID 0xFFFF 2467 struct lpfc_mbx_reg_fcfi { 2468 uint32_t word1; 2469 #define lpfc_reg_fcfi_info_index_SHIFT 0 2470 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2471 #define lpfc_reg_fcfi_info_index_WORD word1 2472 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2473 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2474 #define lpfc_reg_fcfi_fcfi_WORD word1 2475 uint32_t word2; 2476 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2477 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2478 #define lpfc_reg_fcfi_rq_id1_WORD word2 2479 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2480 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2481 #define lpfc_reg_fcfi_rq_id0_WORD word2 2482 uint32_t word3; 2483 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2484 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2485 #define lpfc_reg_fcfi_rq_id3_WORD word3 2486 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2487 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2488 #define lpfc_reg_fcfi_rq_id2_WORD word3 2489 uint32_t word4; 2490 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2491 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2492 #define lpfc_reg_fcfi_type_match0_WORD word4 2493 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2494 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2495 #define lpfc_reg_fcfi_type_mask0_WORD word4 2496 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2497 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2498 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2499 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2500 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2501 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2502 uint32_t word5; 2503 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2504 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2505 #define lpfc_reg_fcfi_type_match1_WORD word5 2506 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2507 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2508 #define lpfc_reg_fcfi_type_mask1_WORD word5 2509 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2510 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2511 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2512 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2513 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2514 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2515 uint32_t word6; 2516 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2517 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2518 #define lpfc_reg_fcfi_type_match2_WORD word6 2519 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2520 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2521 #define lpfc_reg_fcfi_type_mask2_WORD word6 2522 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2523 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2524 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2525 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2526 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2527 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2528 uint32_t word7; 2529 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2530 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2531 #define lpfc_reg_fcfi_type_match3_WORD word7 2532 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2533 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2534 #define lpfc_reg_fcfi_type_mask3_WORD word7 2535 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2536 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2537 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2538 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2539 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2540 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2541 uint32_t word8; 2542 #define lpfc_reg_fcfi_mam_SHIFT 13 2543 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2544 #define lpfc_reg_fcfi_mam_WORD word8 2545 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2546 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2547 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2548 #define lpfc_reg_fcfi_vv_SHIFT 12 2549 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2550 #define lpfc_reg_fcfi_vv_WORD word8 2551 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2552 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2553 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2554 }; 2555 2556 struct lpfc_mbx_reg_fcfi_mrq { 2557 uint32_t word1; 2558 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2559 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2560 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2561 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2562 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2563 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2564 uint32_t word2; 2565 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2566 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2567 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2568 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2569 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2570 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2571 uint32_t word3; 2572 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2573 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2574 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2575 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2576 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2577 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2578 uint32_t word4; 2579 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2580 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2581 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2582 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2583 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2584 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2585 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2586 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2587 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2588 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2589 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2590 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2591 uint32_t word5; 2592 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2593 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2594 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2595 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2596 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2597 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2598 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2599 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2600 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2601 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2602 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2603 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2604 uint32_t word6; 2605 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2606 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2607 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2608 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2609 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2610 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2611 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2612 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2613 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2614 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2615 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2616 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2617 uint32_t word7; 2618 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2619 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2620 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2621 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2622 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2623 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2624 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2625 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2626 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2627 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2628 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2629 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2630 uint32_t word8; 2631 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2632 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2633 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2634 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2635 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2636 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2637 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2638 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2639 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2640 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2641 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2642 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2643 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2644 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2645 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2646 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2647 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2648 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2649 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2650 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2651 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2652 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2653 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2654 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2655 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2656 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2657 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2658 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2659 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2660 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2661 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2662 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2663 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2664 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2665 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2666 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2667 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2668 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2669 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2670 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2671 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2672 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2673 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2674 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2675 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2676 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2677 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2678 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2679 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2680 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2681 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2682 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2683 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2684 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2685 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2686 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2687 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2688 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2689 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2690 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2691 uint32_t word9; 2692 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2693 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2694 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2695 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2696 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2697 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2698 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2699 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2700 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2701 uint32_t word10; 2702 uint32_t word11; 2703 uint32_t word12; 2704 uint32_t word13; 2705 uint32_t word14; 2706 uint32_t word15; 2707 uint32_t word16; 2708 }; 2709 2710 struct lpfc_mbx_unreg_fcfi { 2711 uint32_t word1_rsv; 2712 uint32_t word2; 2713 #define lpfc_unreg_fcfi_SHIFT 0 2714 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2715 #define lpfc_unreg_fcfi_WORD word2 2716 }; 2717 2718 struct lpfc_mbx_read_rev { 2719 uint32_t word1; 2720 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2721 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2722 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2723 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2724 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2725 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2726 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2727 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2728 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2729 #define LPFC_PREDCBX_CEE_MODE 0 2730 #define LPFC_DCBX_CEE_MODE 1 2731 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2732 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2733 #define lpfc_mbx_rd_rev_vpd_WORD word1 2734 uint32_t first_hw_rev; 2735 #define LPFC_G7_ASIC_1 0xd 2736 uint32_t second_hw_rev; 2737 uint32_t word4_rsvd; 2738 uint32_t third_hw_rev; 2739 uint32_t word6; 2740 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2741 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2742 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2743 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2744 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2745 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2746 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2747 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2748 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2749 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2750 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2751 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2752 uint32_t word7_rsvd; 2753 uint32_t fw_id_rev; 2754 uint8_t fw_name[16]; 2755 uint32_t ulp_fw_id_rev; 2756 uint8_t ulp_fw_name[16]; 2757 uint32_t word18_47_rsvd[30]; 2758 uint32_t word48; 2759 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2760 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2761 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2762 uint32_t vpd_paddr_low; 2763 uint32_t vpd_paddr_high; 2764 uint32_t avail_vpd_len; 2765 uint32_t rsvd_52_63[12]; 2766 }; 2767 2768 struct lpfc_mbx_read_config { 2769 uint32_t word1; 2770 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2771 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2772 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2773 uint32_t word2; 2774 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2775 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2776 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2777 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2778 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2779 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2780 #define LPFC_LNK_TYPE_GE 0 2781 #define LPFC_LNK_TYPE_FC 1 2782 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2783 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2784 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2785 #define lpfc_mbx_rd_conf_trunk_SHIFT 12 2786 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2787 #define lpfc_mbx_rd_conf_trunk_WORD word2 2788 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2789 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2790 #define lpfc_mbx_rd_conf_topology_WORD word2 2791 uint32_t rsvd_3; 2792 uint32_t word4; 2793 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2794 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2795 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2796 uint32_t rsvd_5; 2797 uint32_t word6; 2798 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2799 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2800 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2801 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2802 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2803 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2804 uint32_t rsvd_7; 2805 uint32_t word8; 2806 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2807 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2808 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2809 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2810 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2811 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2812 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2813 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2814 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2815 uint32_t word9; 2816 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2817 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2818 #define lpfc_mbx_rd_conf_lmt_WORD word9 2819 uint32_t rsvd_10; 2820 uint32_t rsvd_11; 2821 uint32_t word12; 2822 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2823 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2824 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2825 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2826 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2827 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2828 uint32_t word13; 2829 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2830 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2831 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2832 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2833 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2834 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2835 uint32_t word14; 2836 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2837 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2838 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2839 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2840 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2841 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2842 uint32_t word15; 2843 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2844 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2845 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2846 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2847 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2848 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2849 uint32_t word16; 2850 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2851 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2852 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2853 uint32_t word17; 2854 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2855 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2856 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2857 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2858 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2859 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2860 uint32_t word18; 2861 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2862 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2863 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2864 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2865 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2866 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2867 }; 2868 2869 struct lpfc_mbx_request_features { 2870 uint32_t word1; 2871 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2872 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2873 #define lpfc_mbx_rq_ftr_qry_WORD word1 2874 uint32_t word2; 2875 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2876 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2877 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2878 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2879 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2880 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2881 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2882 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2883 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2884 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2885 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2886 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2887 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2888 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2889 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2890 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2891 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2892 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2893 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2894 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2895 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2896 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2897 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2898 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2899 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2900 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2901 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2902 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2903 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2904 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2905 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2906 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2907 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2908 uint32_t word3; 2909 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2910 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2911 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2912 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2913 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2914 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2915 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2916 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2917 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2918 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2919 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2920 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2921 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2922 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2923 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2924 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2925 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2926 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2927 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2928 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2929 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2930 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2931 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2932 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2933 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2934 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2935 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2936 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2937 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2938 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2939 }; 2940 2941 struct lpfc_mbx_supp_pages { 2942 uint32_t word1; 2943 #define qs_SHIFT 0 2944 #define qs_MASK 0x00000001 2945 #define qs_WORD word1 2946 #define wr_SHIFT 1 2947 #define wr_MASK 0x00000001 2948 #define wr_WORD word1 2949 #define pf_SHIFT 8 2950 #define pf_MASK 0x000000ff 2951 #define pf_WORD word1 2952 #define cpn_SHIFT 16 2953 #define cpn_MASK 0x000000ff 2954 #define cpn_WORD word1 2955 uint32_t word2; 2956 #define list_offset_SHIFT 0 2957 #define list_offset_MASK 0x000000ff 2958 #define list_offset_WORD word2 2959 #define next_offset_SHIFT 8 2960 #define next_offset_MASK 0x000000ff 2961 #define next_offset_WORD word2 2962 #define elem_cnt_SHIFT 16 2963 #define elem_cnt_MASK 0x000000ff 2964 #define elem_cnt_WORD word2 2965 uint32_t word3; 2966 #define pn_0_SHIFT 24 2967 #define pn_0_MASK 0x000000ff 2968 #define pn_0_WORD word3 2969 #define pn_1_SHIFT 16 2970 #define pn_1_MASK 0x000000ff 2971 #define pn_1_WORD word3 2972 #define pn_2_SHIFT 8 2973 #define pn_2_MASK 0x000000ff 2974 #define pn_2_WORD word3 2975 #define pn_3_SHIFT 0 2976 #define pn_3_MASK 0x000000ff 2977 #define pn_3_WORD word3 2978 uint32_t word4; 2979 #define pn_4_SHIFT 24 2980 #define pn_4_MASK 0x000000ff 2981 #define pn_4_WORD word4 2982 #define pn_5_SHIFT 16 2983 #define pn_5_MASK 0x000000ff 2984 #define pn_5_WORD word4 2985 #define pn_6_SHIFT 8 2986 #define pn_6_MASK 0x000000ff 2987 #define pn_6_WORD word4 2988 #define pn_7_SHIFT 0 2989 #define pn_7_MASK 0x000000ff 2990 #define pn_7_WORD word4 2991 uint32_t rsvd[27]; 2992 #define LPFC_SUPP_PAGES 0 2993 #define LPFC_BLOCK_GUARD_PROFILES 1 2994 #define LPFC_SLI4_PARAMETERS 2 2995 }; 2996 2997 struct lpfc_mbx_memory_dump_type3 { 2998 uint32_t word1; 2999 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3000 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3001 #define lpfc_mbx_memory_dump_type3_type_WORD word1 3002 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3003 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3004 #define lpfc_mbx_memory_dump_type3_link_WORD word1 3005 uint32_t word2; 3006 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3007 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3008 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3009 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3010 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3011 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3012 uint32_t word3; 3013 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3014 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3015 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3016 uint32_t addr_lo; 3017 uint32_t addr_hi; 3018 uint32_t return_len; 3019 }; 3020 3021 #define DMP_PAGE_A0 0xa0 3022 #define DMP_PAGE_A2 0xa2 3023 #define DMP_SFF_PAGE_A0_SIZE 256 3024 #define DMP_SFF_PAGE_A2_SIZE 256 3025 3026 #define SFP_WAVELENGTH_LC1310 1310 3027 #define SFP_WAVELENGTH_LL1550 1550 3028 3029 3030 /* 3031 * * SFF-8472 TABLE 3.4 3032 * */ 3033 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3034 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3035 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3036 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3037 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3038 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3039 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3040 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3041 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3042 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3043 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3044 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3045 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3046 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3047 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3048 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3049 3050 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3051 3052 #define SSF_IDENTIFIER 0 3053 #define SSF_EXT_IDENTIFIER 1 3054 #define SSF_CONNECTOR 2 3055 #define SSF_TRANSCEIVER_CODE_B0 3 3056 #define SSF_TRANSCEIVER_CODE_B1 4 3057 #define SSF_TRANSCEIVER_CODE_B2 5 3058 #define SSF_TRANSCEIVER_CODE_B3 6 3059 #define SSF_TRANSCEIVER_CODE_B4 7 3060 #define SSF_TRANSCEIVER_CODE_B5 8 3061 #define SSF_TRANSCEIVER_CODE_B6 9 3062 #define SSF_TRANSCEIVER_CODE_B7 10 3063 #define SSF_ENCODING 11 3064 #define SSF_BR_NOMINAL 12 3065 #define SSF_RATE_IDENTIFIER 13 3066 #define SSF_LENGTH_9UM_KM 14 3067 #define SSF_LENGTH_9UM 15 3068 #define SSF_LENGTH_50UM_OM2 16 3069 #define SSF_LENGTH_62UM_OM1 17 3070 #define SFF_LENGTH_COPPER 18 3071 #define SSF_LENGTH_50UM_OM3 19 3072 #define SSF_VENDOR_NAME 20 3073 #define SSF_VENDOR_OUI 36 3074 #define SSF_VENDOR_PN 40 3075 #define SSF_VENDOR_REV 56 3076 #define SSF_WAVELENGTH_B1 60 3077 #define SSF_WAVELENGTH_B0 61 3078 #define SSF_CC_BASE 63 3079 #define SSF_OPTIONS_B1 64 3080 #define SSF_OPTIONS_B0 65 3081 #define SSF_BR_MAX 66 3082 #define SSF_BR_MIN 67 3083 #define SSF_VENDOR_SN 68 3084 #define SSF_DATE_CODE 84 3085 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3086 #define SSF_ENHANCED_OPTIONS 93 3087 #define SFF_8472_COMPLIANCE 94 3088 #define SSF_CC_EXT 95 3089 #define SSF_A0_VENDOR_SPECIFIC 96 3090 3091 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3092 3093 #define SSF_TEMP_HIGH_ALARM 0 3094 #define SSF_TEMP_LOW_ALARM 2 3095 #define SSF_TEMP_HIGH_WARNING 4 3096 #define SSF_TEMP_LOW_WARNING 6 3097 #define SSF_VOLTAGE_HIGH_ALARM 8 3098 #define SSF_VOLTAGE_LOW_ALARM 10 3099 #define SSF_VOLTAGE_HIGH_WARNING 12 3100 #define SSF_VOLTAGE_LOW_WARNING 14 3101 #define SSF_BIAS_HIGH_ALARM 16 3102 #define SSF_BIAS_LOW_ALARM 18 3103 #define SSF_BIAS_HIGH_WARNING 20 3104 #define SSF_BIAS_LOW_WARNING 22 3105 #define SSF_TXPOWER_HIGH_ALARM 24 3106 #define SSF_TXPOWER_LOW_ALARM 26 3107 #define SSF_TXPOWER_HIGH_WARNING 28 3108 #define SSF_TXPOWER_LOW_WARNING 30 3109 #define SSF_RXPOWER_HIGH_ALARM 32 3110 #define SSF_RXPOWER_LOW_ALARM 34 3111 #define SSF_RXPOWER_HIGH_WARNING 36 3112 #define SSF_RXPOWER_LOW_WARNING 38 3113 #define SSF_EXT_CAL_CONSTANTS 56 3114 #define SSF_CC_DMI 95 3115 #define SFF_TEMPERATURE_B1 96 3116 #define SFF_TEMPERATURE_B0 97 3117 #define SFF_VCC_B1 98 3118 #define SFF_VCC_B0 99 3119 #define SFF_TX_BIAS_CURRENT_B1 100 3120 #define SFF_TX_BIAS_CURRENT_B0 101 3121 #define SFF_TXPOWER_B1 102 3122 #define SFF_TXPOWER_B0 103 3123 #define SFF_RXPOWER_B1 104 3124 #define SFF_RXPOWER_B0 105 3125 #define SSF_STATUS_CONTROL 110 3126 #define SSF_ALARM_FLAGS 112 3127 #define SSF_WARNING_FLAGS 116 3128 #define SSF_EXT_TATUS_CONTROL_B1 118 3129 #define SSF_EXT_TATUS_CONTROL_B0 119 3130 #define SSF_A2_VENDOR_SPECIFIC 120 3131 #define SSF_USER_EEPROM 128 3132 #define SSF_VENDOR_CONTROL 148 3133 3134 3135 /* 3136 * Tranceiver codes Fibre Channel SFF-8472 3137 * Table 3.5. 3138 */ 3139 3140 struct sff_trasnceiver_codes_byte0 { 3141 uint8_t inifiband:4; 3142 uint8_t teng_ethernet:4; 3143 }; 3144 3145 struct sff_trasnceiver_codes_byte1 { 3146 uint8_t sonet:6; 3147 uint8_t escon:2; 3148 }; 3149 3150 struct sff_trasnceiver_codes_byte2 { 3151 uint8_t soNet:8; 3152 }; 3153 3154 struct sff_trasnceiver_codes_byte3 { 3155 uint8_t ethernet:8; 3156 }; 3157 3158 struct sff_trasnceiver_codes_byte4 { 3159 uint8_t fc_el_lo:1; 3160 uint8_t fc_lw_laser:1; 3161 uint8_t fc_sw_laser:1; 3162 uint8_t fc_md_distance:1; 3163 uint8_t fc_lg_distance:1; 3164 uint8_t fc_int_distance:1; 3165 uint8_t fc_short_distance:1; 3166 uint8_t fc_vld_distance:1; 3167 }; 3168 3169 struct sff_trasnceiver_codes_byte5 { 3170 uint8_t reserved1:1; 3171 uint8_t reserved2:1; 3172 uint8_t fc_sfp_active:1; /* Active cable */ 3173 uint8_t fc_sfp_passive:1; /* Passive cable */ 3174 uint8_t fc_lw_laser:1; /* Longwave laser */ 3175 uint8_t fc_sw_laser_sl:1; 3176 uint8_t fc_sw_laser_sn:1; 3177 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3178 }; 3179 3180 struct sff_trasnceiver_codes_byte6 { 3181 uint8_t fc_tm_sm:1; /* Single Mode */ 3182 uint8_t reserved:1; 3183 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3184 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3185 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3186 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3187 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3188 }; 3189 3190 struct sff_trasnceiver_codes_byte7 { 3191 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3192 uint8_t reserve:1; 3193 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3194 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3195 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3196 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3197 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3198 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3199 }; 3200 3201 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3202 struct user_eeprom { 3203 uint8_t vendor_name[16]; 3204 uint8_t vendor_oui[3]; 3205 uint8_t vendor_pn[816]; 3206 uint8_t vendor_rev[4]; 3207 uint8_t vendor_sn[16]; 3208 uint8_t datecode[6]; 3209 uint8_t lot_code[2]; 3210 uint8_t reserved191[57]; 3211 }; 3212 3213 struct lpfc_mbx_pc_sli4_params { 3214 uint32_t word1; 3215 #define qs_SHIFT 0 3216 #define qs_MASK 0x00000001 3217 #define qs_WORD word1 3218 #define wr_SHIFT 1 3219 #define wr_MASK 0x00000001 3220 #define wr_WORD word1 3221 #define pf_SHIFT 8 3222 #define pf_MASK 0x000000ff 3223 #define pf_WORD word1 3224 #define cpn_SHIFT 16 3225 #define cpn_MASK 0x000000ff 3226 #define cpn_WORD word1 3227 uint32_t word2; 3228 #define if_type_SHIFT 0 3229 #define if_type_MASK 0x00000007 3230 #define if_type_WORD word2 3231 #define sli_rev_SHIFT 4 3232 #define sli_rev_MASK 0x0000000f 3233 #define sli_rev_WORD word2 3234 #define sli_family_SHIFT 8 3235 #define sli_family_MASK 0x000000ff 3236 #define sli_family_WORD word2 3237 #define featurelevel_1_SHIFT 16 3238 #define featurelevel_1_MASK 0x000000ff 3239 #define featurelevel_1_WORD word2 3240 #define featurelevel_2_SHIFT 24 3241 #define featurelevel_2_MASK 0x0000001f 3242 #define featurelevel_2_WORD word2 3243 uint32_t word3; 3244 #define fcoe_SHIFT 0 3245 #define fcoe_MASK 0x00000001 3246 #define fcoe_WORD word3 3247 #define fc_SHIFT 1 3248 #define fc_MASK 0x00000001 3249 #define fc_WORD word3 3250 #define nic_SHIFT 2 3251 #define nic_MASK 0x00000001 3252 #define nic_WORD word3 3253 #define iscsi_SHIFT 3 3254 #define iscsi_MASK 0x00000001 3255 #define iscsi_WORD word3 3256 #define rdma_SHIFT 4 3257 #define rdma_MASK 0x00000001 3258 #define rdma_WORD word3 3259 uint32_t sge_supp_len; 3260 #define SLI4_PAGE_SIZE 4096 3261 uint32_t word5; 3262 #define if_page_sz_SHIFT 0 3263 #define if_page_sz_MASK 0x0000ffff 3264 #define if_page_sz_WORD word5 3265 #define loopbk_scope_SHIFT 24 3266 #define loopbk_scope_MASK 0x0000000f 3267 #define loopbk_scope_WORD word5 3268 #define rq_db_window_SHIFT 28 3269 #define rq_db_window_MASK 0x0000000f 3270 #define rq_db_window_WORD word5 3271 uint32_t word6; 3272 #define eq_pages_SHIFT 0 3273 #define eq_pages_MASK 0x0000000f 3274 #define eq_pages_WORD word6 3275 #define eqe_size_SHIFT 8 3276 #define eqe_size_MASK 0x000000ff 3277 #define eqe_size_WORD word6 3278 uint32_t word7; 3279 #define cq_pages_SHIFT 0 3280 #define cq_pages_MASK 0x0000000f 3281 #define cq_pages_WORD word7 3282 #define cqe_size_SHIFT 8 3283 #define cqe_size_MASK 0x000000ff 3284 #define cqe_size_WORD word7 3285 uint32_t word8; 3286 #define mq_pages_SHIFT 0 3287 #define mq_pages_MASK 0x0000000f 3288 #define mq_pages_WORD word8 3289 #define mqe_size_SHIFT 8 3290 #define mqe_size_MASK 0x000000ff 3291 #define mqe_size_WORD word8 3292 #define mq_elem_cnt_SHIFT 16 3293 #define mq_elem_cnt_MASK 0x000000ff 3294 #define mq_elem_cnt_WORD word8 3295 uint32_t word9; 3296 #define wq_pages_SHIFT 0 3297 #define wq_pages_MASK 0x0000ffff 3298 #define wq_pages_WORD word9 3299 #define wqe_size_SHIFT 8 3300 #define wqe_size_MASK 0x000000ff 3301 #define wqe_size_WORD word9 3302 uint32_t word10; 3303 #define rq_pages_SHIFT 0 3304 #define rq_pages_MASK 0x0000ffff 3305 #define rq_pages_WORD word10 3306 #define rqe_size_SHIFT 8 3307 #define rqe_size_MASK 0x000000ff 3308 #define rqe_size_WORD word10 3309 uint32_t word11; 3310 #define hdr_pages_SHIFT 0 3311 #define hdr_pages_MASK 0x0000000f 3312 #define hdr_pages_WORD word11 3313 #define hdr_size_SHIFT 8 3314 #define hdr_size_MASK 0x0000000f 3315 #define hdr_size_WORD word11 3316 #define hdr_pp_align_SHIFT 16 3317 #define hdr_pp_align_MASK 0x0000ffff 3318 #define hdr_pp_align_WORD word11 3319 uint32_t word12; 3320 #define sgl_pages_SHIFT 0 3321 #define sgl_pages_MASK 0x0000000f 3322 #define sgl_pages_WORD word12 3323 #define sgl_pp_align_SHIFT 16 3324 #define sgl_pp_align_MASK 0x0000ffff 3325 #define sgl_pp_align_WORD word12 3326 uint32_t rsvd_13_63[51]; 3327 }; 3328 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3329 &(~((SLI4_PAGE_SIZE)-1))) 3330 3331 struct lpfc_sli4_parameters { 3332 uint32_t word0; 3333 #define cfg_prot_type_SHIFT 0 3334 #define cfg_prot_type_MASK 0x000000FF 3335 #define cfg_prot_type_WORD word0 3336 uint32_t word1; 3337 #define cfg_ft_SHIFT 0 3338 #define cfg_ft_MASK 0x00000001 3339 #define cfg_ft_WORD word1 3340 #define cfg_sli_rev_SHIFT 4 3341 #define cfg_sli_rev_MASK 0x0000000f 3342 #define cfg_sli_rev_WORD word1 3343 #define cfg_sli_family_SHIFT 8 3344 #define cfg_sli_family_MASK 0x0000000f 3345 #define cfg_sli_family_WORD word1 3346 #define cfg_if_type_SHIFT 12 3347 #define cfg_if_type_MASK 0x0000000f 3348 #define cfg_if_type_WORD word1 3349 #define cfg_sli_hint_1_SHIFT 16 3350 #define cfg_sli_hint_1_MASK 0x000000ff 3351 #define cfg_sli_hint_1_WORD word1 3352 #define cfg_sli_hint_2_SHIFT 24 3353 #define cfg_sli_hint_2_MASK 0x0000001f 3354 #define cfg_sli_hint_2_WORD word1 3355 uint32_t word2; 3356 #define cfg_eqav_SHIFT 31 3357 #define cfg_eqav_MASK 0x00000001 3358 #define cfg_eqav_WORD word2 3359 uint32_t word3; 3360 uint32_t word4; 3361 #define cfg_cqv_SHIFT 14 3362 #define cfg_cqv_MASK 0x00000003 3363 #define cfg_cqv_WORD word4 3364 #define cfg_cqpsize_SHIFT 16 3365 #define cfg_cqpsize_MASK 0x000000ff 3366 #define cfg_cqpsize_WORD word4 3367 #define cfg_cqav_SHIFT 31 3368 #define cfg_cqav_MASK 0x00000001 3369 #define cfg_cqav_WORD word4 3370 uint32_t word5; 3371 uint32_t word6; 3372 #define cfg_mqv_SHIFT 14 3373 #define cfg_mqv_MASK 0x00000003 3374 #define cfg_mqv_WORD word6 3375 uint32_t word7; 3376 uint32_t word8; 3377 #define cfg_wqpcnt_SHIFT 0 3378 #define cfg_wqpcnt_MASK 0x0000000f 3379 #define cfg_wqpcnt_WORD word8 3380 #define cfg_wqsize_SHIFT 8 3381 #define cfg_wqsize_MASK 0x0000000f 3382 #define cfg_wqsize_WORD word8 3383 #define cfg_wqv_SHIFT 14 3384 #define cfg_wqv_MASK 0x00000003 3385 #define cfg_wqv_WORD word8 3386 #define cfg_wqpsize_SHIFT 16 3387 #define cfg_wqpsize_MASK 0x000000ff 3388 #define cfg_wqpsize_WORD word8 3389 uint32_t word9; 3390 uint32_t word10; 3391 #define cfg_rqv_SHIFT 14 3392 #define cfg_rqv_MASK 0x00000003 3393 #define cfg_rqv_WORD word10 3394 uint32_t word11; 3395 #define cfg_rq_db_window_SHIFT 28 3396 #define cfg_rq_db_window_MASK 0x0000000f 3397 #define cfg_rq_db_window_WORD word11 3398 uint32_t word12; 3399 #define cfg_fcoe_SHIFT 0 3400 #define cfg_fcoe_MASK 0x00000001 3401 #define cfg_fcoe_WORD word12 3402 #define cfg_ext_SHIFT 1 3403 #define cfg_ext_MASK 0x00000001 3404 #define cfg_ext_WORD word12 3405 #define cfg_hdrr_SHIFT 2 3406 #define cfg_hdrr_MASK 0x00000001 3407 #define cfg_hdrr_WORD word12 3408 #define cfg_phwq_SHIFT 15 3409 #define cfg_phwq_MASK 0x00000001 3410 #define cfg_phwq_WORD word12 3411 #define cfg_oas_SHIFT 25 3412 #define cfg_oas_MASK 0x00000001 3413 #define cfg_oas_WORD word12 3414 #define cfg_loopbk_scope_SHIFT 28 3415 #define cfg_loopbk_scope_MASK 0x0000000f 3416 #define cfg_loopbk_scope_WORD word12 3417 uint32_t sge_supp_len; 3418 uint32_t word14; 3419 #define cfg_sgl_page_cnt_SHIFT 0 3420 #define cfg_sgl_page_cnt_MASK 0x0000000f 3421 #define cfg_sgl_page_cnt_WORD word14 3422 #define cfg_sgl_page_size_SHIFT 8 3423 #define cfg_sgl_page_size_MASK 0x000000ff 3424 #define cfg_sgl_page_size_WORD word14 3425 #define cfg_sgl_pp_align_SHIFT 16 3426 #define cfg_sgl_pp_align_MASK 0x000000ff 3427 #define cfg_sgl_pp_align_WORD word14 3428 uint32_t word15; 3429 uint32_t word16; 3430 uint32_t word17; 3431 uint32_t word18; 3432 uint32_t word19; 3433 #define cfg_ext_embed_cb_SHIFT 0 3434 #define cfg_ext_embed_cb_MASK 0x00000001 3435 #define cfg_ext_embed_cb_WORD word19 3436 #define cfg_mds_diags_SHIFT 1 3437 #define cfg_mds_diags_MASK 0x00000001 3438 #define cfg_mds_diags_WORD word19 3439 #define cfg_nvme_SHIFT 3 3440 #define cfg_nvme_MASK 0x00000001 3441 #define cfg_nvme_WORD word19 3442 #define cfg_xib_SHIFT 4 3443 #define cfg_xib_MASK 0x00000001 3444 #define cfg_xib_WORD word19 3445 #define cfg_eqdr_SHIFT 8 3446 #define cfg_eqdr_MASK 0x00000001 3447 #define cfg_eqdr_WORD word19 3448 #define cfg_nosr_SHIFT 9 3449 #define cfg_nosr_MASK 0x00000001 3450 #define cfg_nosr_WORD word19 3451 3452 #define cfg_bv1s_SHIFT 10 3453 #define cfg_bv1s_MASK 0x00000001 3454 #define cfg_bv1s_WORD word19 3455 3456 uint32_t word20; 3457 #define cfg_max_tow_xri_SHIFT 0 3458 #define cfg_max_tow_xri_MASK 0x0000ffff 3459 #define cfg_max_tow_xri_WORD word20 3460 3461 uint32_t word21; /* RESERVED */ 3462 uint32_t word22; /* RESERVED */ 3463 uint32_t word23; /* RESERVED */ 3464 3465 uint32_t word24; 3466 #define cfg_frag_field_offset_SHIFT 0 3467 #define cfg_frag_field_offset_MASK 0x0000ffff 3468 #define cfg_frag_field_offset_WORD word24 3469 3470 #define cfg_frag_field_size_SHIFT 16 3471 #define cfg_frag_field_size_MASK 0x0000ffff 3472 #define cfg_frag_field_size_WORD word24 3473 3474 uint32_t word25; 3475 #define cfg_sgl_field_offset_SHIFT 0 3476 #define cfg_sgl_field_offset_MASK 0x0000ffff 3477 #define cfg_sgl_field_offset_WORD word25 3478 3479 #define cfg_sgl_field_size_SHIFT 16 3480 #define cfg_sgl_field_size_MASK 0x0000ffff 3481 #define cfg_sgl_field_size_WORD word25 3482 3483 uint32_t word26; /* Chain SGE initial value LOW */ 3484 uint32_t word27; /* Chain SGE initial value HIGH */ 3485 #define LPFC_NODELAY_MAX_IO 32 3486 }; 3487 3488 #define LPFC_SET_UE_RECOVERY 0x10 3489 #define LPFC_SET_MDS_DIAGS 0x11 3490 struct lpfc_mbx_set_feature { 3491 struct mbox_header header; 3492 uint32_t feature; 3493 uint32_t param_len; 3494 uint32_t word6; 3495 #define lpfc_mbx_set_feature_UER_SHIFT 0 3496 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3497 #define lpfc_mbx_set_feature_UER_WORD word6 3498 #define lpfc_mbx_set_feature_mds_SHIFT 0 3499 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3500 #define lpfc_mbx_set_feature_mds_WORD word6 3501 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3502 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3503 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3504 uint32_t word7; 3505 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3506 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3507 #define lpfc_mbx_set_feature_UERP_WORD word7 3508 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3509 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3510 #define lpfc_mbx_set_feature_UESR_WORD word7 3511 }; 3512 3513 3514 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3515 struct lpfc_mbx_set_host_data { 3516 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3517 struct mbox_header header; 3518 uint32_t param_id; 3519 uint32_t param_len; 3520 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3521 }; 3522 3523 struct lpfc_mbx_set_trunk_mode { 3524 struct mbox_header header; 3525 uint32_t word0; 3526 #define lpfc_mbx_set_trunk_mode_WORD word0 3527 #define lpfc_mbx_set_trunk_mode_SHIFT 0 3528 #define lpfc_mbx_set_trunk_mode_MASK 0xFF 3529 uint32_t word1; 3530 uint32_t word2; 3531 }; 3532 3533 struct lpfc_mbx_get_sli4_parameters { 3534 struct mbox_header header; 3535 struct lpfc_sli4_parameters sli4_parameters; 3536 }; 3537 3538 struct lpfc_rscr_desc_generic { 3539 #define LPFC_RSRC_DESC_WSIZE 22 3540 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3541 }; 3542 3543 struct lpfc_rsrc_desc_pcie { 3544 uint32_t word0; 3545 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3546 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3547 #define lpfc_rsrc_desc_pcie_type_WORD word0 3548 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3549 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3550 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3551 #define lpfc_rsrc_desc_pcie_length_WORD word0 3552 uint32_t word1; 3553 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3554 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3555 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3556 uint32_t reserved; 3557 uint32_t word3; 3558 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3559 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3560 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3561 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3562 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3563 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3564 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3565 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3566 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3567 uint32_t word4; 3568 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3569 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3570 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3571 }; 3572 3573 struct lpfc_rsrc_desc_fcfcoe { 3574 uint32_t word0; 3575 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3576 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3577 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3578 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3579 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3580 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3581 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3582 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3583 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3584 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3585 uint32_t word1; 3586 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3587 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3588 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3589 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3590 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3591 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3592 uint32_t word2; 3593 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3594 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3595 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3596 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3597 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3598 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3599 uint32_t word3; 3600 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3601 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3602 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3603 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3604 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3605 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3606 uint32_t word4; 3607 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3608 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3609 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3610 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3611 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3612 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3613 uint32_t word5; 3614 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3615 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3616 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3617 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3618 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3619 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3620 uint32_t word6; 3621 uint32_t word7; 3622 uint32_t word8; 3623 uint32_t word9; 3624 uint32_t word10; 3625 uint32_t word11; 3626 uint32_t word12; 3627 uint32_t word13; 3628 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3629 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3630 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3631 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3632 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3633 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3634 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3635 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3636 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3637 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3638 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3639 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3640 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3641 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3642 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3643 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3644 uint32_t bw_min; 3645 uint32_t bw_max; 3646 uint32_t iops_min; 3647 uint32_t iops_max; 3648 uint32_t reserved[4]; 3649 }; 3650 3651 struct lpfc_func_cfg { 3652 #define LPFC_RSRC_DESC_MAX_NUM 2 3653 uint32_t rsrc_desc_count; 3654 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3655 }; 3656 3657 struct lpfc_mbx_get_func_cfg { 3658 struct mbox_header header; 3659 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3660 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3661 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3662 struct lpfc_func_cfg func_cfg; 3663 }; 3664 3665 struct lpfc_prof_cfg { 3666 #define LPFC_RSRC_DESC_MAX_NUM 2 3667 uint32_t rsrc_desc_count; 3668 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3669 }; 3670 3671 struct lpfc_mbx_get_prof_cfg { 3672 struct mbox_header header; 3673 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3674 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3675 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3676 union { 3677 struct { 3678 uint32_t word10; 3679 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3680 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3681 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3682 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3683 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3684 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3685 } request; 3686 struct { 3687 struct lpfc_prof_cfg prof_cfg; 3688 } response; 3689 } u; 3690 }; 3691 3692 struct lpfc_controller_attribute { 3693 uint32_t version_string[8]; 3694 uint32_t manufacturer_name[8]; 3695 uint32_t supported_modes; 3696 uint32_t word17; 3697 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3698 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3699 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3700 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3701 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3702 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3703 uint32_t mbx_da_struct_ver; 3704 uint32_t ep_fw_da_struct_ver; 3705 uint32_t ncsi_ver_str[3]; 3706 uint32_t dflt_ext_timeout; 3707 uint32_t model_number[8]; 3708 uint32_t description[16]; 3709 uint32_t serial_number[8]; 3710 uint32_t ip_ver_str[8]; 3711 uint32_t fw_ver_str[8]; 3712 uint32_t bios_ver_str[8]; 3713 uint32_t redboot_ver_str[8]; 3714 uint32_t driver_ver_str[8]; 3715 uint32_t flash_fw_ver_str[8]; 3716 uint32_t functionality; 3717 uint32_t word105; 3718 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3719 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3720 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3721 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3722 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3723 #define lpfc_cntl_attr_asic_rev_WORD word105 3724 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3725 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3726 #define lpfc_cntl_attr_gen_guid0_WORD word105 3727 uint32_t gen_guid1_12[3]; 3728 uint32_t word109; 3729 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3730 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3731 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3732 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3733 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3734 #define lpfc_cntl_attr_gen_guid15_WORD word109 3735 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3736 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3737 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3738 uint32_t word110; 3739 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3740 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3741 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3742 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3743 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3744 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3745 uint32_t word111; 3746 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3747 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3748 #define lpfc_cntl_attr_cache_valid_WORD word111 3749 #define lpfc_cntl_attr_hba_status_SHIFT 8 3750 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3751 #define lpfc_cntl_attr_hba_status_WORD word111 3752 #define lpfc_cntl_attr_max_domain_SHIFT 16 3753 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3754 #define lpfc_cntl_attr_max_domain_WORD word111 3755 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3756 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3757 #define lpfc_cntl_attr_lnk_numb_WORD word111 3758 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3759 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3760 #define lpfc_cntl_attr_lnk_type_WORD word111 3761 uint32_t fw_post_status; 3762 uint32_t hba_mtu[8]; 3763 uint32_t word121; 3764 uint32_t reserved1[3]; 3765 uint32_t word125; 3766 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3767 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3768 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3769 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3770 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3771 #define lpfc_cntl_attr_pci_device_id_WORD word125 3772 uint32_t word126; 3773 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3774 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3775 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3776 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3777 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3778 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3779 uint32_t word127; 3780 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3781 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3782 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3783 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3784 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3785 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3786 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3787 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3788 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3789 #define lpfc_cntl_attr_inf_type_SHIFT 24 3790 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3791 #define lpfc_cntl_attr_inf_type_WORD word127 3792 uint32_t unique_id[2]; 3793 uint32_t word130; 3794 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3795 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3796 #define lpfc_cntl_attr_num_netfil_WORD word130 3797 uint32_t reserved2[4]; 3798 }; 3799 3800 struct lpfc_mbx_get_cntl_attributes { 3801 union lpfc_sli4_cfg_shdr cfg_shdr; 3802 struct lpfc_controller_attribute cntl_attr; 3803 }; 3804 3805 struct lpfc_mbx_get_port_name { 3806 struct mbox_header header; 3807 union { 3808 struct { 3809 uint32_t word4; 3810 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3811 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3812 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3813 } request; 3814 struct { 3815 uint32_t word4; 3816 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3817 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3818 #define lpfc_mbx_get_port_name_name0_WORD word4 3819 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3820 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3821 #define lpfc_mbx_get_port_name_name1_WORD word4 3822 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3823 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3824 #define lpfc_mbx_get_port_name_name2_WORD word4 3825 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3826 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3827 #define lpfc_mbx_get_port_name_name3_WORD word4 3828 #define LPFC_LINK_NUMBER_0 0 3829 #define LPFC_LINK_NUMBER_1 1 3830 #define LPFC_LINK_NUMBER_2 2 3831 #define LPFC_LINK_NUMBER_3 3 3832 } response; 3833 } u; 3834 }; 3835 3836 /* Mailbox Completion Queue Error Messages */ 3837 #define MB_CQE_STATUS_SUCCESS 0x0 3838 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3839 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3840 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3841 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3842 #define MB_CQE_STATUS_DMA_FAILED 0x5 3843 3844 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3845 struct lpfc_mbx_wr_object { 3846 struct mbox_header header; 3847 union { 3848 struct { 3849 uint32_t word4; 3850 #define lpfc_wr_object_eof_SHIFT 31 3851 #define lpfc_wr_object_eof_MASK 0x00000001 3852 #define lpfc_wr_object_eof_WORD word4 3853 #define lpfc_wr_object_eas_SHIFT 29 3854 #define lpfc_wr_object_eas_MASK 0x00000001 3855 #define lpfc_wr_object_eas_WORD word4 3856 #define lpfc_wr_object_write_length_SHIFT 0 3857 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3858 #define lpfc_wr_object_write_length_WORD word4 3859 uint32_t write_offset; 3860 uint32_t object_name[26]; 3861 uint32_t bde_count; 3862 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3863 } request; 3864 struct { 3865 uint32_t actual_write_length; 3866 uint32_t word5; 3867 #define lpfc_wr_object_change_status_SHIFT 0 3868 #define lpfc_wr_object_change_status_MASK 0x000000FF 3869 #define lpfc_wr_object_change_status_WORD word5 3870 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3871 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3872 #define LPFC_CHANGE_STATUS_FW_RESET 0x02 3873 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3874 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3875 } response; 3876 } u; 3877 }; 3878 3879 /* mailbox queue entry structure */ 3880 struct lpfc_mqe { 3881 uint32_t word0; 3882 #define lpfc_mqe_status_SHIFT 16 3883 #define lpfc_mqe_status_MASK 0x0000FFFF 3884 #define lpfc_mqe_status_WORD word0 3885 #define lpfc_mqe_command_SHIFT 8 3886 #define lpfc_mqe_command_MASK 0x000000FF 3887 #define lpfc_mqe_command_WORD word0 3888 union { 3889 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3890 /* sli4 mailbox commands */ 3891 struct lpfc_mbx_sli4_config sli4_config; 3892 struct lpfc_mbx_init_vfi init_vfi; 3893 struct lpfc_mbx_reg_vfi reg_vfi; 3894 struct lpfc_mbx_reg_vfi unreg_vfi; 3895 struct lpfc_mbx_init_vpi init_vpi; 3896 struct lpfc_mbx_resume_rpi resume_rpi; 3897 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3898 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3899 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3900 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3901 struct lpfc_mbx_reg_fcfi reg_fcfi; 3902 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3903 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3904 struct lpfc_mbx_mq_create mq_create; 3905 struct lpfc_mbx_mq_create_ext mq_create_ext; 3906 struct lpfc_mbx_eq_create eq_create; 3907 struct lpfc_mbx_modify_eq_delay eq_delay; 3908 struct lpfc_mbx_cq_create cq_create; 3909 struct lpfc_mbx_cq_create_set cq_create_set; 3910 struct lpfc_mbx_wq_create wq_create; 3911 struct lpfc_mbx_rq_create rq_create; 3912 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3913 struct lpfc_mbx_mq_destroy mq_destroy; 3914 struct lpfc_mbx_eq_destroy eq_destroy; 3915 struct lpfc_mbx_cq_destroy cq_destroy; 3916 struct lpfc_mbx_wq_destroy wq_destroy; 3917 struct lpfc_mbx_rq_destroy rq_destroy; 3918 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3919 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3920 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3921 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3922 struct lpfc_mbx_nembed_cmd nembed_cmd; 3923 struct lpfc_mbx_read_rev read_rev; 3924 struct lpfc_mbx_read_vpi read_vpi; 3925 struct lpfc_mbx_read_config rd_config; 3926 struct lpfc_mbx_request_features req_ftrs; 3927 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3928 struct lpfc_mbx_query_fw_config query_fw_cfg; 3929 struct lpfc_mbx_set_beacon_config beacon_config; 3930 struct lpfc_mbx_supp_pages supp_pages; 3931 struct lpfc_mbx_pc_sli4_params sli4_params; 3932 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3933 struct lpfc_mbx_set_link_diag_state link_diag_state; 3934 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3935 struct lpfc_mbx_run_link_diag_test link_diag_test; 3936 struct lpfc_mbx_get_func_cfg get_func_cfg; 3937 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3938 struct lpfc_mbx_wr_object wr_object; 3939 struct lpfc_mbx_get_port_name get_port_name; 3940 struct lpfc_mbx_set_feature set_feature; 3941 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3942 struct lpfc_mbx_set_host_data set_host_data; 3943 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 3944 struct lpfc_mbx_nop nop; 3945 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 3946 } un; 3947 }; 3948 3949 struct lpfc_mcqe { 3950 uint32_t word0; 3951 #define lpfc_mcqe_status_SHIFT 0 3952 #define lpfc_mcqe_status_MASK 0x0000FFFF 3953 #define lpfc_mcqe_status_WORD word0 3954 #define lpfc_mcqe_ext_status_SHIFT 16 3955 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3956 #define lpfc_mcqe_ext_status_WORD word0 3957 uint32_t mcqe_tag0; 3958 uint32_t mcqe_tag1; 3959 uint32_t trailer; 3960 #define lpfc_trailer_valid_SHIFT 31 3961 #define lpfc_trailer_valid_MASK 0x00000001 3962 #define lpfc_trailer_valid_WORD trailer 3963 #define lpfc_trailer_async_SHIFT 30 3964 #define lpfc_trailer_async_MASK 0x00000001 3965 #define lpfc_trailer_async_WORD trailer 3966 #define lpfc_trailer_hpi_SHIFT 29 3967 #define lpfc_trailer_hpi_MASK 0x00000001 3968 #define lpfc_trailer_hpi_WORD trailer 3969 #define lpfc_trailer_completed_SHIFT 28 3970 #define lpfc_trailer_completed_MASK 0x00000001 3971 #define lpfc_trailer_completed_WORD trailer 3972 #define lpfc_trailer_consumed_SHIFT 27 3973 #define lpfc_trailer_consumed_MASK 0x00000001 3974 #define lpfc_trailer_consumed_WORD trailer 3975 #define lpfc_trailer_type_SHIFT 16 3976 #define lpfc_trailer_type_MASK 0x000000FF 3977 #define lpfc_trailer_type_WORD trailer 3978 #define lpfc_trailer_code_SHIFT 8 3979 #define lpfc_trailer_code_MASK 0x000000FF 3980 #define lpfc_trailer_code_WORD trailer 3981 #define LPFC_TRAILER_CODE_LINK 0x1 3982 #define LPFC_TRAILER_CODE_FCOE 0x2 3983 #define LPFC_TRAILER_CODE_DCBX 0x3 3984 #define LPFC_TRAILER_CODE_GRP5 0x5 3985 #define LPFC_TRAILER_CODE_FC 0x10 3986 #define LPFC_TRAILER_CODE_SLI 0x11 3987 }; 3988 3989 struct lpfc_acqe_link { 3990 uint32_t word0; 3991 #define lpfc_acqe_link_speed_SHIFT 24 3992 #define lpfc_acqe_link_speed_MASK 0x000000FF 3993 #define lpfc_acqe_link_speed_WORD word0 3994 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3995 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3996 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3997 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3998 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3999 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4000 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4001 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4002 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4003 #define lpfc_acqe_link_duplex_SHIFT 16 4004 #define lpfc_acqe_link_duplex_MASK 0x000000FF 4005 #define lpfc_acqe_link_duplex_WORD word0 4006 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4007 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4008 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4009 #define lpfc_acqe_link_status_SHIFT 8 4010 #define lpfc_acqe_link_status_MASK 0x000000FF 4011 #define lpfc_acqe_link_status_WORD word0 4012 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4013 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 4014 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4015 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4016 #define lpfc_acqe_link_type_SHIFT 6 4017 #define lpfc_acqe_link_type_MASK 0x00000003 4018 #define lpfc_acqe_link_type_WORD word0 4019 #define lpfc_acqe_link_number_SHIFT 0 4020 #define lpfc_acqe_link_number_MASK 0x0000003F 4021 #define lpfc_acqe_link_number_WORD word0 4022 uint32_t word1; 4023 #define lpfc_acqe_link_fault_SHIFT 0 4024 #define lpfc_acqe_link_fault_MASK 0x000000FF 4025 #define lpfc_acqe_link_fault_WORD word1 4026 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4027 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4028 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4029 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4030 #define lpfc_acqe_logical_link_speed_SHIFT 16 4031 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4032 #define lpfc_acqe_logical_link_speed_WORD word1 4033 uint32_t event_tag; 4034 uint32_t trailer; 4035 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4036 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4037 }; 4038 4039 struct lpfc_acqe_fip { 4040 uint32_t index; 4041 uint32_t word1; 4042 #define lpfc_acqe_fip_fcf_count_SHIFT 0 4043 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4044 #define lpfc_acqe_fip_fcf_count_WORD word1 4045 #define lpfc_acqe_fip_event_type_SHIFT 16 4046 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4047 #define lpfc_acqe_fip_event_type_WORD word1 4048 uint32_t event_tag; 4049 uint32_t trailer; 4050 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4051 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4052 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4053 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 4054 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4055 }; 4056 4057 struct lpfc_acqe_dcbx { 4058 uint32_t tlv_ttl; 4059 uint32_t reserved; 4060 uint32_t event_tag; 4061 uint32_t trailer; 4062 }; 4063 4064 struct lpfc_acqe_grp5 { 4065 uint32_t word0; 4066 #define lpfc_acqe_grp5_type_SHIFT 6 4067 #define lpfc_acqe_grp5_type_MASK 0x00000003 4068 #define lpfc_acqe_grp5_type_WORD word0 4069 #define lpfc_acqe_grp5_number_SHIFT 0 4070 #define lpfc_acqe_grp5_number_MASK 0x0000003F 4071 #define lpfc_acqe_grp5_number_WORD word0 4072 uint32_t word1; 4073 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 4074 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4075 #define lpfc_acqe_grp5_llink_spd_WORD word1 4076 uint32_t event_tag; 4077 uint32_t trailer; 4078 }; 4079 4080 static char *const trunk_errmsg[] = { /* map errcode */ 4081 "", /* There is no such error code at index 0*/ 4082 "link negotiated speed does not match existing" 4083 " trunk - link was \"low\" speed", 4084 "link negotiated speed does not match" 4085 " existing trunk - link was \"middle\" speed", 4086 "link negotiated speed does not match existing" 4087 " trunk - link was \"high\" speed", 4088 "Attached to non-trunking port - F_Port", 4089 "Attached to non-trunking port - N_Port", 4090 "FLOGI response timeout", 4091 "non-FLOGI frame received", 4092 "Invalid FLOGI response", 4093 "Trunking initialization protocol", 4094 "Trunk peer device mismatch", 4095 }; 4096 4097 struct lpfc_acqe_fc_la { 4098 uint32_t word0; 4099 #define lpfc_acqe_fc_la_speed_SHIFT 24 4100 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4101 #define lpfc_acqe_fc_la_speed_WORD word0 4102 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4103 #define LPFC_FC_LA_SPEED_1G 0x1 4104 #define LPFC_FC_LA_SPEED_2G 0x2 4105 #define LPFC_FC_LA_SPEED_4G 0x4 4106 #define LPFC_FC_LA_SPEED_8G 0x8 4107 #define LPFC_FC_LA_SPEED_10G 0xA 4108 #define LPFC_FC_LA_SPEED_16G 0x10 4109 #define LPFC_FC_LA_SPEED_32G 0x20 4110 #define LPFC_FC_LA_SPEED_64G 0x21 4111 #define LPFC_FC_LA_SPEED_128G 0x22 4112 #define LPFC_FC_LA_SPEED_256G 0x23 4113 #define lpfc_acqe_fc_la_topology_SHIFT 16 4114 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4115 #define lpfc_acqe_fc_la_topology_WORD word0 4116 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4117 #define LPFC_FC_LA_TOP_P2P 0x1 4118 #define LPFC_FC_LA_TOP_FCAL 0x2 4119 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4120 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4121 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4122 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4123 #define lpfc_acqe_fc_la_att_type_WORD word0 4124 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4125 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4126 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4127 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4128 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4129 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4130 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4131 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4132 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4133 #define lpfc_acqe_fc_la_port_type_WORD word0 4134 #define LPFC_LINK_TYPE_ETHERNET 0x0 4135 #define LPFC_LINK_TYPE_FC 0x1 4136 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4137 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4138 #define lpfc_acqe_fc_la_port_number_WORD word0 4139 4140 /* Attention Type is 0x07 (Trunking Event) word0 */ 4141 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4142 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4143 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4144 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4145 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4146 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4147 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4148 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4149 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4150 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4151 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4152 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4153 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4154 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4155 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4156 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4157 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4158 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4159 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4160 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4161 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4162 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4163 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4164 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4165 uint32_t word1; 4166 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4167 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4168 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4169 #define lpfc_acqe_fc_la_fault_SHIFT 0 4170 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4171 #define lpfc_acqe_fc_la_fault_WORD word1 4172 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4173 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4174 #define lpfc_acqe_fc_la_trunk_fault_WORD word1 4175 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4176 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4177 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4178 #define LPFC_FC_LA_FAULT_NONE 0x0 4179 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4180 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4181 uint32_t event_tag; 4182 uint32_t trailer; 4183 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4184 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4185 }; 4186 4187 struct lpfc_acqe_misconfigured_event { 4188 struct { 4189 uint32_t word0; 4190 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4191 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4192 #define lpfc_sli_misconfigured_port0_state_WORD word0 4193 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4194 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4195 #define lpfc_sli_misconfigured_port1_state_WORD word0 4196 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4197 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4198 #define lpfc_sli_misconfigured_port2_state_WORD word0 4199 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4200 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4201 #define lpfc_sli_misconfigured_port3_state_WORD word0 4202 uint32_t word1; 4203 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4204 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4205 #define lpfc_sli_misconfigured_port0_op_WORD word1 4206 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4207 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4208 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4209 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4210 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4211 #define lpfc_sli_misconfigured_port1_op_WORD word1 4212 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4213 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4214 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4215 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4216 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4217 #define lpfc_sli_misconfigured_port2_op_WORD word1 4218 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4219 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4220 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4221 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4222 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4223 #define lpfc_sli_misconfigured_port3_op_WORD word1 4224 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4225 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4226 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4227 } theEvent; 4228 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4229 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4230 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4231 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4232 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4233 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4234 }; 4235 4236 struct lpfc_acqe_sli { 4237 uint32_t event_data1; 4238 uint32_t event_data2; 4239 uint32_t reserved; 4240 uint32_t trailer; 4241 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4242 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4243 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4244 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4245 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4246 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4247 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4248 }; 4249 4250 /* 4251 * Define the bootstrap mailbox (bmbx) region used to communicate 4252 * mailbox command between the host and port. The mailbox consists 4253 * of a payload area of 256 bytes and a completion queue of length 4254 * 16 bytes. 4255 */ 4256 struct lpfc_bmbx_create { 4257 struct lpfc_mqe mqe; 4258 struct lpfc_mcqe mcqe; 4259 }; 4260 4261 #define SGL_ALIGN_SZ 64 4262 #define SGL_PAGE_SIZE 4096 4263 /* align SGL addr on a size boundary - adjust address up */ 4264 #define NO_XRI 0xffff 4265 4266 struct wqe_common { 4267 uint32_t word6; 4268 #define wqe_xri_tag_SHIFT 0 4269 #define wqe_xri_tag_MASK 0x0000FFFF 4270 #define wqe_xri_tag_WORD word6 4271 #define wqe_ctxt_tag_SHIFT 16 4272 #define wqe_ctxt_tag_MASK 0x0000FFFF 4273 #define wqe_ctxt_tag_WORD word6 4274 uint32_t word7; 4275 #define wqe_dif_SHIFT 0 4276 #define wqe_dif_MASK 0x00000003 4277 #define wqe_dif_WORD word7 4278 #define LPFC_WQE_DIF_PASSTHRU 1 4279 #define LPFC_WQE_DIF_STRIP 2 4280 #define LPFC_WQE_DIF_INSERT 3 4281 #define wqe_ct_SHIFT 2 4282 #define wqe_ct_MASK 0x00000003 4283 #define wqe_ct_WORD word7 4284 #define wqe_status_SHIFT 4 4285 #define wqe_status_MASK 0x0000000f 4286 #define wqe_status_WORD word7 4287 #define wqe_cmnd_SHIFT 8 4288 #define wqe_cmnd_MASK 0x000000ff 4289 #define wqe_cmnd_WORD word7 4290 #define wqe_class_SHIFT 16 4291 #define wqe_class_MASK 0x00000007 4292 #define wqe_class_WORD word7 4293 #define wqe_ar_SHIFT 19 4294 #define wqe_ar_MASK 0x00000001 4295 #define wqe_ar_WORD word7 4296 #define wqe_ag_SHIFT wqe_ar_SHIFT 4297 #define wqe_ag_MASK wqe_ar_MASK 4298 #define wqe_ag_WORD wqe_ar_WORD 4299 #define wqe_pu_SHIFT 20 4300 #define wqe_pu_MASK 0x00000003 4301 #define wqe_pu_WORD word7 4302 #define wqe_erp_SHIFT 22 4303 #define wqe_erp_MASK 0x00000001 4304 #define wqe_erp_WORD word7 4305 #define wqe_conf_SHIFT wqe_erp_SHIFT 4306 #define wqe_conf_MASK wqe_erp_MASK 4307 #define wqe_conf_WORD wqe_erp_WORD 4308 #define wqe_lnk_SHIFT 23 4309 #define wqe_lnk_MASK 0x00000001 4310 #define wqe_lnk_WORD word7 4311 #define wqe_tmo_SHIFT 24 4312 #define wqe_tmo_MASK 0x000000ff 4313 #define wqe_tmo_WORD word7 4314 uint32_t abort_tag; /* word 8 in WQE */ 4315 uint32_t word9; 4316 #define wqe_reqtag_SHIFT 0 4317 #define wqe_reqtag_MASK 0x0000FFFF 4318 #define wqe_reqtag_WORD word9 4319 #define wqe_temp_rpi_SHIFT 16 4320 #define wqe_temp_rpi_MASK 0x0000FFFF 4321 #define wqe_temp_rpi_WORD word9 4322 #define wqe_rcvoxid_SHIFT 16 4323 #define wqe_rcvoxid_MASK 0x0000FFFF 4324 #define wqe_rcvoxid_WORD word9 4325 uint32_t word10; 4326 #define wqe_ebde_cnt_SHIFT 0 4327 #define wqe_ebde_cnt_MASK 0x0000000f 4328 #define wqe_ebde_cnt_WORD word10 4329 #define wqe_nvme_SHIFT 4 4330 #define wqe_nvme_MASK 0x00000001 4331 #define wqe_nvme_WORD word10 4332 #define wqe_oas_SHIFT 6 4333 #define wqe_oas_MASK 0x00000001 4334 #define wqe_oas_WORD word10 4335 #define wqe_lenloc_SHIFT 7 4336 #define wqe_lenloc_MASK 0x00000003 4337 #define wqe_lenloc_WORD word10 4338 #define LPFC_WQE_LENLOC_NONE 0 4339 #define LPFC_WQE_LENLOC_WORD3 1 4340 #define LPFC_WQE_LENLOC_WORD12 2 4341 #define LPFC_WQE_LENLOC_WORD4 3 4342 #define wqe_qosd_SHIFT 9 4343 #define wqe_qosd_MASK 0x00000001 4344 #define wqe_qosd_WORD word10 4345 #define wqe_xbl_SHIFT 11 4346 #define wqe_xbl_MASK 0x00000001 4347 #define wqe_xbl_WORD word10 4348 #define wqe_iod_SHIFT 13 4349 #define wqe_iod_MASK 0x00000001 4350 #define wqe_iod_WORD word10 4351 #define LPFC_WQE_IOD_NONE 0 4352 #define LPFC_WQE_IOD_WRITE 0 4353 #define LPFC_WQE_IOD_READ 1 4354 #define wqe_dbde_SHIFT 14 4355 #define wqe_dbde_MASK 0x00000001 4356 #define wqe_dbde_WORD word10 4357 #define wqe_wqes_SHIFT 15 4358 #define wqe_wqes_MASK 0x00000001 4359 #define wqe_wqes_WORD word10 4360 /* Note that this field overlaps above fields */ 4361 #define wqe_wqid_SHIFT 1 4362 #define wqe_wqid_MASK 0x00007fff 4363 #define wqe_wqid_WORD word10 4364 #define wqe_pri_SHIFT 16 4365 #define wqe_pri_MASK 0x00000007 4366 #define wqe_pri_WORD word10 4367 #define wqe_pv_SHIFT 19 4368 #define wqe_pv_MASK 0x00000001 4369 #define wqe_pv_WORD word10 4370 #define wqe_xc_SHIFT 21 4371 #define wqe_xc_MASK 0x00000001 4372 #define wqe_xc_WORD word10 4373 #define wqe_sr_SHIFT 22 4374 #define wqe_sr_MASK 0x00000001 4375 #define wqe_sr_WORD word10 4376 #define wqe_ccpe_SHIFT 23 4377 #define wqe_ccpe_MASK 0x00000001 4378 #define wqe_ccpe_WORD word10 4379 #define wqe_ccp_SHIFT 24 4380 #define wqe_ccp_MASK 0x000000ff 4381 #define wqe_ccp_WORD word10 4382 uint32_t word11; 4383 #define wqe_cmd_type_SHIFT 0 4384 #define wqe_cmd_type_MASK 0x0000000f 4385 #define wqe_cmd_type_WORD word11 4386 #define wqe_els_id_SHIFT 4 4387 #define wqe_els_id_MASK 0x00000003 4388 #define wqe_els_id_WORD word11 4389 #define LPFC_ELS_ID_FLOGI 3 4390 #define LPFC_ELS_ID_FDISC 2 4391 #define LPFC_ELS_ID_LOGO 1 4392 #define LPFC_ELS_ID_DEFAULT 0 4393 #define wqe_irsp_SHIFT 4 4394 #define wqe_irsp_MASK 0x00000001 4395 #define wqe_irsp_WORD word11 4396 #define wqe_pbde_SHIFT 5 4397 #define wqe_pbde_MASK 0x00000001 4398 #define wqe_pbde_WORD word11 4399 #define wqe_sup_SHIFT 6 4400 #define wqe_sup_MASK 0x00000001 4401 #define wqe_sup_WORD word11 4402 #define wqe_wqec_SHIFT 7 4403 #define wqe_wqec_MASK 0x00000001 4404 #define wqe_wqec_WORD word11 4405 #define wqe_irsplen_SHIFT 8 4406 #define wqe_irsplen_MASK 0x0000000f 4407 #define wqe_irsplen_WORD word11 4408 #define wqe_cqid_SHIFT 16 4409 #define wqe_cqid_MASK 0x0000ffff 4410 #define wqe_cqid_WORD word11 4411 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4412 }; 4413 4414 struct wqe_did { 4415 uint32_t word5; 4416 #define wqe_els_did_SHIFT 0 4417 #define wqe_els_did_MASK 0x00FFFFFF 4418 #define wqe_els_did_WORD word5 4419 #define wqe_xmit_bls_pt_SHIFT 28 4420 #define wqe_xmit_bls_pt_MASK 0x00000003 4421 #define wqe_xmit_bls_pt_WORD word5 4422 #define wqe_xmit_bls_ar_SHIFT 30 4423 #define wqe_xmit_bls_ar_MASK 0x00000001 4424 #define wqe_xmit_bls_ar_WORD word5 4425 #define wqe_xmit_bls_xo_SHIFT 31 4426 #define wqe_xmit_bls_xo_MASK 0x00000001 4427 #define wqe_xmit_bls_xo_WORD word5 4428 }; 4429 4430 struct lpfc_wqe_generic{ 4431 struct ulp_bde64 bde; 4432 uint32_t word3; 4433 uint32_t word4; 4434 uint32_t word5; 4435 struct wqe_common wqe_com; 4436 uint32_t payload[4]; 4437 }; 4438 4439 struct els_request64_wqe { 4440 struct ulp_bde64 bde; 4441 uint32_t payload_len; 4442 uint32_t word4; 4443 #define els_req64_sid_SHIFT 0 4444 #define els_req64_sid_MASK 0x00FFFFFF 4445 #define els_req64_sid_WORD word4 4446 #define els_req64_sp_SHIFT 24 4447 #define els_req64_sp_MASK 0x00000001 4448 #define els_req64_sp_WORD word4 4449 #define els_req64_vf_SHIFT 25 4450 #define els_req64_vf_MASK 0x00000001 4451 #define els_req64_vf_WORD word4 4452 struct wqe_did wqe_dest; 4453 struct wqe_common wqe_com; /* words 6-11 */ 4454 uint32_t word12; 4455 #define els_req64_vfid_SHIFT 1 4456 #define els_req64_vfid_MASK 0x00000FFF 4457 #define els_req64_vfid_WORD word12 4458 #define els_req64_pri_SHIFT 13 4459 #define els_req64_pri_MASK 0x00000007 4460 #define els_req64_pri_WORD word12 4461 uint32_t word13; 4462 #define els_req64_hopcnt_SHIFT 24 4463 #define els_req64_hopcnt_MASK 0x000000ff 4464 #define els_req64_hopcnt_WORD word13 4465 uint32_t word14; 4466 uint32_t max_response_payload_len; 4467 }; 4468 4469 struct xmit_els_rsp64_wqe { 4470 struct ulp_bde64 bde; 4471 uint32_t response_payload_len; 4472 uint32_t word4; 4473 #define els_rsp64_sid_SHIFT 0 4474 #define els_rsp64_sid_MASK 0x00FFFFFF 4475 #define els_rsp64_sid_WORD word4 4476 #define els_rsp64_sp_SHIFT 24 4477 #define els_rsp64_sp_MASK 0x00000001 4478 #define els_rsp64_sp_WORD word4 4479 struct wqe_did wqe_dest; 4480 struct wqe_common wqe_com; /* words 6-11 */ 4481 uint32_t word12; 4482 #define wqe_rsp_temp_rpi_SHIFT 0 4483 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4484 #define wqe_rsp_temp_rpi_WORD word12 4485 uint32_t rsvd_13_15[3]; 4486 }; 4487 4488 struct xmit_bls_rsp64_wqe { 4489 uint32_t payload0; 4490 /* Payload0 for BA_ACC */ 4491 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4492 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4493 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4494 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4495 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4496 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4497 /* Payload0 for BA_RJT */ 4498 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4499 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4500 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4501 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4502 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4503 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4504 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4505 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4506 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4507 uint32_t word1; 4508 #define xmit_bls_rsp64_rxid_SHIFT 0 4509 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4510 #define xmit_bls_rsp64_rxid_WORD word1 4511 #define xmit_bls_rsp64_oxid_SHIFT 16 4512 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4513 #define xmit_bls_rsp64_oxid_WORD word1 4514 uint32_t word2; 4515 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4516 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4517 #define xmit_bls_rsp64_seqcnthi_WORD word2 4518 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4519 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4520 #define xmit_bls_rsp64_seqcntlo_WORD word2 4521 uint32_t rsrvd3; 4522 uint32_t rsrvd4; 4523 struct wqe_did wqe_dest; 4524 struct wqe_common wqe_com; /* words 6-11 */ 4525 uint32_t word12; 4526 #define xmit_bls_rsp64_temprpi_SHIFT 0 4527 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4528 #define xmit_bls_rsp64_temprpi_WORD word12 4529 uint32_t rsvd_13_15[3]; 4530 }; 4531 4532 struct wqe_rctl_dfctl { 4533 uint32_t word5; 4534 #define wqe_si_SHIFT 2 4535 #define wqe_si_MASK 0x000000001 4536 #define wqe_si_WORD word5 4537 #define wqe_la_SHIFT 3 4538 #define wqe_la_MASK 0x000000001 4539 #define wqe_la_WORD word5 4540 #define wqe_xo_SHIFT 6 4541 #define wqe_xo_MASK 0x000000001 4542 #define wqe_xo_WORD word5 4543 #define wqe_ls_SHIFT 7 4544 #define wqe_ls_MASK 0x000000001 4545 #define wqe_ls_WORD word5 4546 #define wqe_dfctl_SHIFT 8 4547 #define wqe_dfctl_MASK 0x0000000ff 4548 #define wqe_dfctl_WORD word5 4549 #define wqe_type_SHIFT 16 4550 #define wqe_type_MASK 0x0000000ff 4551 #define wqe_type_WORD word5 4552 #define wqe_rctl_SHIFT 24 4553 #define wqe_rctl_MASK 0x0000000ff 4554 #define wqe_rctl_WORD word5 4555 }; 4556 4557 struct xmit_seq64_wqe { 4558 struct ulp_bde64 bde; 4559 uint32_t rsvd3; 4560 uint32_t relative_offset; 4561 struct wqe_rctl_dfctl wge_ctl; 4562 struct wqe_common wqe_com; /* words 6-11 */ 4563 uint32_t xmit_len; 4564 uint32_t rsvd_12_15[3]; 4565 }; 4566 struct xmit_bcast64_wqe { 4567 struct ulp_bde64 bde; 4568 uint32_t seq_payload_len; 4569 uint32_t rsvd4; 4570 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4571 struct wqe_common wqe_com; /* words 6-11 */ 4572 uint32_t rsvd_12_15[4]; 4573 }; 4574 4575 struct gen_req64_wqe { 4576 struct ulp_bde64 bde; 4577 uint32_t request_payload_len; 4578 uint32_t relative_offset; 4579 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4580 struct wqe_common wqe_com; /* words 6-11 */ 4581 uint32_t rsvd_12_14[3]; 4582 uint32_t max_response_payload_len; 4583 }; 4584 4585 /* Define NVME PRLI request to fabric. NVME is a 4586 * fabric-only protocol. 4587 * Updated to red-lined v1.08 on Sept 16, 2016 4588 */ 4589 struct lpfc_nvme_prli { 4590 uint32_t word1; 4591 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4592 #define prli_acc_rsp_code_SHIFT 8 4593 #define prli_acc_rsp_code_MASK 0x0000000f 4594 #define prli_acc_rsp_code_WORD word1 4595 #define prli_estabImagePair_SHIFT 13 4596 #define prli_estabImagePair_MASK 0x00000001 4597 #define prli_estabImagePair_WORD word1 4598 #define prli_type_code_ext_SHIFT 16 4599 #define prli_type_code_ext_MASK 0x000000ff 4600 #define prli_type_code_ext_WORD word1 4601 #define prli_type_code_SHIFT 24 4602 #define prli_type_code_MASK 0x000000ff 4603 #define prli_type_code_WORD word1 4604 uint32_t word_rsvd2; 4605 uint32_t word_rsvd3; 4606 uint32_t word4; 4607 #define prli_fba_SHIFT 0 4608 #define prli_fba_MASK 0x00000001 4609 #define prli_fba_WORD word4 4610 #define prli_disc_SHIFT 3 4611 #define prli_disc_MASK 0x00000001 4612 #define prli_disc_WORD word4 4613 #define prli_tgt_SHIFT 4 4614 #define prli_tgt_MASK 0x00000001 4615 #define prli_tgt_WORD word4 4616 #define prli_init_SHIFT 5 4617 #define prli_init_MASK 0x00000001 4618 #define prli_init_WORD word4 4619 #define prli_conf_SHIFT 7 4620 #define prli_conf_MASK 0x00000001 4621 #define prli_conf_WORD word4 4622 uint32_t word5; 4623 #define prli_fb_sz_SHIFT 0 4624 #define prli_fb_sz_MASK 0x0000ffff 4625 #define prli_fb_sz_WORD word5 4626 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4627 }; 4628 4629 struct create_xri_wqe { 4630 uint32_t rsrvd[5]; /* words 0-4 */ 4631 struct wqe_did wqe_dest; /* word 5 */ 4632 struct wqe_common wqe_com; /* words 6-11 */ 4633 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4634 }; 4635 4636 #define T_REQUEST_TAG 3 4637 #define T_XRI_TAG 1 4638 4639 struct abort_cmd_wqe { 4640 uint32_t rsrvd[3]; 4641 uint32_t word3; 4642 #define abort_cmd_ia_SHIFT 0 4643 #define abort_cmd_ia_MASK 0x000000001 4644 #define abort_cmd_ia_WORD word3 4645 #define abort_cmd_criteria_SHIFT 8 4646 #define abort_cmd_criteria_MASK 0x0000000ff 4647 #define abort_cmd_criteria_WORD word3 4648 uint32_t rsrvd4; 4649 uint32_t rsrvd5; 4650 struct wqe_common wqe_com; /* words 6-11 */ 4651 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4652 }; 4653 4654 struct fcp_iwrite64_wqe { 4655 struct ulp_bde64 bde; 4656 uint32_t word3; 4657 #define cmd_buff_len_SHIFT 16 4658 #define cmd_buff_len_MASK 0x00000ffff 4659 #define cmd_buff_len_WORD word3 4660 #define payload_offset_len_SHIFT 0 4661 #define payload_offset_len_MASK 0x0000ffff 4662 #define payload_offset_len_WORD word3 4663 uint32_t total_xfer_len; 4664 uint32_t initial_xfer_len; 4665 struct wqe_common wqe_com; /* words 6-11 */ 4666 uint32_t rsrvd12; 4667 struct ulp_bde64 ph_bde; /* words 13-15 */ 4668 }; 4669 4670 struct fcp_iread64_wqe { 4671 struct ulp_bde64 bde; 4672 uint32_t word3; 4673 #define cmd_buff_len_SHIFT 16 4674 #define cmd_buff_len_MASK 0x00000ffff 4675 #define cmd_buff_len_WORD word3 4676 #define payload_offset_len_SHIFT 0 4677 #define payload_offset_len_MASK 0x0000ffff 4678 #define payload_offset_len_WORD word3 4679 uint32_t total_xfer_len; /* word 4 */ 4680 uint32_t rsrvd5; /* word 5 */ 4681 struct wqe_common wqe_com; /* words 6-11 */ 4682 uint32_t rsrvd12; 4683 struct ulp_bde64 ph_bde; /* words 13-15 */ 4684 }; 4685 4686 struct fcp_icmnd64_wqe { 4687 struct ulp_bde64 bde; /* words 0-2 */ 4688 uint32_t word3; 4689 #define cmd_buff_len_SHIFT 16 4690 #define cmd_buff_len_MASK 0x00000ffff 4691 #define cmd_buff_len_WORD word3 4692 #define payload_offset_len_SHIFT 0 4693 #define payload_offset_len_MASK 0x0000ffff 4694 #define payload_offset_len_WORD word3 4695 uint32_t rsrvd4; /* word 4 */ 4696 uint32_t rsrvd5; /* word 5 */ 4697 struct wqe_common wqe_com; /* words 6-11 */ 4698 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4699 }; 4700 4701 struct fcp_trsp64_wqe { 4702 struct ulp_bde64 bde; 4703 uint32_t response_len; 4704 uint32_t rsvd_4_5[2]; 4705 struct wqe_common wqe_com; /* words 6-11 */ 4706 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4707 }; 4708 4709 struct fcp_tsend64_wqe { 4710 struct ulp_bde64 bde; 4711 uint32_t payload_offset_len; 4712 uint32_t relative_offset; 4713 uint32_t reserved; 4714 struct wqe_common wqe_com; /* words 6-11 */ 4715 uint32_t fcp_data_len; /* word 12 */ 4716 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4717 }; 4718 4719 struct fcp_treceive64_wqe { 4720 struct ulp_bde64 bde; 4721 uint32_t payload_offset_len; 4722 uint32_t relative_offset; 4723 uint32_t reserved; 4724 struct wqe_common wqe_com; /* words 6-11 */ 4725 uint32_t fcp_data_len; /* word 12 */ 4726 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4727 }; 4728 #define TXRDY_PAYLOAD_LEN 12 4729 4730 #define CMD_SEND_FRAME 0xE1 4731 4732 struct send_frame_wqe { 4733 struct ulp_bde64 bde; /* words 0-2 */ 4734 uint32_t frame_len; /* word 3 */ 4735 uint32_t fc_hdr_wd0; /* word 4 */ 4736 uint32_t fc_hdr_wd1; /* word 5 */ 4737 struct wqe_common wqe_com; /* words 6-11 */ 4738 uint32_t fc_hdr_wd2; /* word 12 */ 4739 uint32_t fc_hdr_wd3; /* word 13 */ 4740 uint32_t fc_hdr_wd4; /* word 14 */ 4741 uint32_t fc_hdr_wd5; /* word 15 */ 4742 }; 4743 4744 union lpfc_wqe { 4745 uint32_t words[16]; 4746 struct lpfc_wqe_generic generic; 4747 struct fcp_icmnd64_wqe fcp_icmd; 4748 struct fcp_iread64_wqe fcp_iread; 4749 struct fcp_iwrite64_wqe fcp_iwrite; 4750 struct abort_cmd_wqe abort_cmd; 4751 struct create_xri_wqe create_xri; 4752 struct xmit_bcast64_wqe xmit_bcast64; 4753 struct xmit_seq64_wqe xmit_sequence; 4754 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4755 struct xmit_els_rsp64_wqe xmit_els_rsp; 4756 struct els_request64_wqe els_req; 4757 struct gen_req64_wqe gen_req; 4758 struct fcp_trsp64_wqe fcp_trsp; 4759 struct fcp_tsend64_wqe fcp_tsend; 4760 struct fcp_treceive64_wqe fcp_treceive; 4761 struct send_frame_wqe send_frame; 4762 }; 4763 4764 union lpfc_wqe128 { 4765 uint32_t words[32]; 4766 struct lpfc_wqe_generic generic; 4767 struct fcp_icmnd64_wqe fcp_icmd; 4768 struct fcp_iread64_wqe fcp_iread; 4769 struct fcp_iwrite64_wqe fcp_iwrite; 4770 struct abort_cmd_wqe abort_cmd; 4771 struct create_xri_wqe create_xri; 4772 struct xmit_bcast64_wqe xmit_bcast64; 4773 struct xmit_seq64_wqe xmit_sequence; 4774 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4775 struct xmit_els_rsp64_wqe xmit_els_rsp; 4776 struct els_request64_wqe els_req; 4777 struct gen_req64_wqe gen_req; 4778 struct fcp_trsp64_wqe fcp_trsp; 4779 struct fcp_tsend64_wqe fcp_tsend; 4780 struct fcp_treceive64_wqe fcp_treceive; 4781 struct send_frame_wqe send_frame; 4782 }; 4783 4784 #define MAGIC_NUMER_G6 0xFEAA0003 4785 #define MAGIC_NUMER_G7 0xFEAA0005 4786 4787 struct lpfc_grp_hdr { 4788 uint32_t size; 4789 uint32_t magic_number; 4790 uint32_t word2; 4791 #define lpfc_grp_hdr_file_type_SHIFT 24 4792 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4793 #define lpfc_grp_hdr_file_type_WORD word2 4794 #define lpfc_grp_hdr_id_SHIFT 16 4795 #define lpfc_grp_hdr_id_MASK 0x000000FF 4796 #define lpfc_grp_hdr_id_WORD word2 4797 uint8_t rev_name[128]; 4798 uint8_t date[12]; 4799 uint8_t revision[32]; 4800 }; 4801 4802 /* Defines for WQE command type */ 4803 #define FCP_COMMAND 0x0 4804 #define NVME_READ_CMD 0x0 4805 #define FCP_COMMAND_DATA_OUT 0x1 4806 #define NVME_WRITE_CMD 0x1 4807 #define FCP_COMMAND_TRECEIVE 0x2 4808 #define FCP_COMMAND_TRSP 0x3 4809 #define FCP_COMMAND_TSEND 0x7 4810 #define OTHER_COMMAND 0x8 4811 #define ELS_COMMAND_NON_FIP 0xC 4812 #define ELS_COMMAND_FIP 0xD 4813 4814 #define LPFC_NVME_EMBED_CMD 0x0 4815 #define LPFC_NVME_EMBED_WRITE 0x1 4816 #define LPFC_NVME_EMBED_READ 0x2 4817 4818 /* WQE Commands */ 4819 #define CMD_ABORT_XRI_WQE 0x0F 4820 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4821 #define CMD_XMIT_BCAST64_WQE 0x84 4822 #define CMD_ELS_REQUEST64_WQE 0x8A 4823 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4824 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4825 #define CMD_FCP_IWRITE64_WQE 0x98 4826 #define CMD_FCP_IREAD64_WQE 0x9A 4827 #define CMD_FCP_ICMND64_WQE 0x9C 4828 #define CMD_FCP_TSEND64_WQE 0x9F 4829 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4830 #define CMD_FCP_TRSP64_WQE 0xA3 4831 #define CMD_GEN_REQUEST64_WQE 0xC2 4832 4833 #define CMD_WQE_MASK 0xff 4834 4835 4836 #define LPFC_FW_DUMP 1 4837 #define LPFC_FW_RESET 2 4838 #define LPFC_DV_RESET 3 4839