1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #include <uapi/scsi/fc/fc_fs.h> 24 #include <uapi/scsi/fc/fc_els.h> 25 26 /* Macros to deal with bit fields. Each bit field must have 3 #defines 27 * associated with it (_SHIFT, _MASK, and _WORD). 28 * EG. For a bit field that is in the 7th bit of the "field4" field of a 29 * structure and is 2 bits in size the following #defines must exist: 30 * struct temp { 31 * uint32_t field1; 32 * uint32_t field2; 33 * uint32_t field3; 34 * uint32_t field4; 35 * #define example_bit_field_SHIFT 7 36 * #define example_bit_field_MASK 0x03 37 * #define example_bit_field_WORD field4 38 * uint32_t field5; 39 * }; 40 * Then the macros below may be used to get or set the value of that field. 41 * EG. To get the value of the bit field from the above example: 42 * struct temp t1; 43 * value = bf_get(example_bit_field, &t1); 44 * And then to set that bit field: 45 * bf_set(example_bit_field, &t1, 2); 46 * Or clear that bit field: 47 * bf_set(example_bit_field, &t1, 0); 48 */ 49 #define bf_get_be32(name, ptr) \ 50 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 51 #define bf_get_le32(name, ptr) \ 52 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 53 #define bf_get(name, ptr) \ 54 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 55 #define bf_set_le32(name, ptr, value) \ 56 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 57 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 58 ~(name##_MASK << name##_SHIFT))))) 59 #define bf_set(name, ptr, value) \ 60 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 61 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 62 63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF) 64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF) 65 66 #define get_job_ulpword(x, y) ((x)->iocb.un.ulpWord[y]) 67 68 #define set_job_ulpstatus(x, y) bf_set(lpfc_wcqe_c_status, &(x)->wcqe_cmpl, y) 69 #define set_job_ulpword4(x, y) ((&(x)->wcqe_cmpl)->parameter = y) 70 71 struct dma_address { 72 uint32_t addr_lo; 73 uint32_t addr_hi; 74 }; 75 76 struct lpfc_sli_intf { 77 uint32_t word0; 78 #define lpfc_sli_intf_valid_SHIFT 29 79 #define lpfc_sli_intf_valid_MASK 0x00000007 80 #define lpfc_sli_intf_valid_WORD word0 81 #define LPFC_SLI_INTF_VALID 6 82 #define lpfc_sli_intf_sli_hint2_SHIFT 24 83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 84 #define lpfc_sli_intf_sli_hint2_WORD word0 85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 86 #define lpfc_sli_intf_sli_hint1_SHIFT 16 87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 88 #define lpfc_sli_intf_sli_hint1_WORD word0 89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 90 #define LPFC_SLI_INTF_SLI_HINT1_1 1 91 #define LPFC_SLI_INTF_SLI_HINT1_2 2 92 #define lpfc_sli_intf_if_type_SHIFT 12 93 #define lpfc_sli_intf_if_type_MASK 0x0000000F 94 #define lpfc_sli_intf_if_type_WORD word0 95 #define LPFC_SLI_INTF_IF_TYPE_0 0 96 #define LPFC_SLI_INTF_IF_TYPE_1 1 97 #define LPFC_SLI_INTF_IF_TYPE_2 2 98 #define LPFC_SLI_INTF_IF_TYPE_6 6 99 #define lpfc_sli_intf_sli_family_SHIFT 8 100 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 101 #define lpfc_sli_intf_sli_family_WORD word0 102 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 103 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 104 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 105 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 106 #define LPFC_SLI_INTF_FAMILY_G6 0xc 107 #define LPFC_SLI_INTF_FAMILY_G7 0xd 108 #define LPFC_SLI_INTF_FAMILY_G7P 0xe 109 #define lpfc_sli_intf_slirev_SHIFT 4 110 #define lpfc_sli_intf_slirev_MASK 0x0000000F 111 #define lpfc_sli_intf_slirev_WORD word0 112 #define LPFC_SLI_INTF_REV_SLI3 3 113 #define LPFC_SLI_INTF_REV_SLI4 4 114 #define lpfc_sli_intf_func_type_SHIFT 0 115 #define lpfc_sli_intf_func_type_MASK 0x00000001 116 #define lpfc_sli_intf_func_type_WORD word0 117 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 118 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 119 }; 120 121 #define LPFC_SLI4_MBX_EMBED true 122 #define LPFC_SLI4_MBX_NEMBED false 123 124 #define LPFC_SLI4_MB_WORD_COUNT 64 125 #define LPFC_MAX_MQ_PAGE 8 126 #define LPFC_MAX_WQ_PAGE_V0 4 127 #define LPFC_MAX_WQ_PAGE 8 128 #define LPFC_MAX_RQ_PAGE 8 129 #define LPFC_MAX_CQ_PAGE 4 130 #define LPFC_MAX_EQ_PAGE 8 131 132 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 133 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 134 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 135 136 /* Define SLI4 Alignment requirements. */ 137 #define LPFC_ALIGN_16_BYTE 16 138 #define LPFC_ALIGN_64_BYTE 64 139 #define SLI4_PAGE_SIZE 4096 140 141 /* Define SLI4 specific definitions. */ 142 #define LPFC_MQ_CQE_BYTE_OFFSET 256 143 #define LPFC_MBX_CMD_HDR_LENGTH 16 144 #define LPFC_MBX_ERROR_RANGE 0x4000 145 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 146 #define LPFC_BMBX_BIT1_ADDR_LO 0 147 #define LPFC_RPI_HDR_COUNT 64 148 #define LPFC_HDR_TEMPLATE_SIZE 4096 149 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 150 #define LPFC_FCF_RECORD_WD_CNT 132 151 #define LPFC_ENTIRE_FCF_DATABASE 0 152 #define LPFC_DFLT_FCF_INDEX 0 153 154 /* Virtual function numbers */ 155 #define LPFC_VF0 0 156 #define LPFC_VF1 1 157 #define LPFC_VF2 2 158 #define LPFC_VF3 3 159 #define LPFC_VF4 4 160 #define LPFC_VF5 5 161 #define LPFC_VF6 6 162 #define LPFC_VF7 7 163 #define LPFC_VF8 8 164 #define LPFC_VF9 9 165 #define LPFC_VF10 10 166 #define LPFC_VF11 11 167 #define LPFC_VF12 12 168 #define LPFC_VF13 13 169 #define LPFC_VF14 14 170 #define LPFC_VF15 15 171 #define LPFC_VF16 16 172 #define LPFC_VF17 17 173 #define LPFC_VF18 18 174 #define LPFC_VF19 19 175 #define LPFC_VF20 20 176 #define LPFC_VF21 21 177 #define LPFC_VF22 22 178 #define LPFC_VF23 23 179 #define LPFC_VF24 24 180 #define LPFC_VF25 25 181 #define LPFC_VF26 26 182 #define LPFC_VF27 27 183 #define LPFC_VF28 28 184 #define LPFC_VF29 29 185 #define LPFC_VF30 30 186 #define LPFC_VF31 31 187 188 /* PCI function numbers */ 189 #define LPFC_PCI_FUNC0 0 190 #define LPFC_PCI_FUNC1 1 191 #define LPFC_PCI_FUNC2 2 192 #define LPFC_PCI_FUNC3 3 193 #define LPFC_PCI_FUNC4 4 194 195 /* SLI4 interface type-2 PDEV_CTL register */ 196 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 197 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 198 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 199 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 200 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 201 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 202 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 203 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 204 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 205 206 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 207 208 /* Active interrupt test count */ 209 #define LPFC_ACT_INTR_CNT 4 210 211 /* Algrithmns for scheduling FCP commands to WQs */ 212 #define LPFC_FCP_SCHED_BY_HDWQ 0 213 #define LPFC_FCP_SCHED_BY_CPU 1 214 215 /* Algrithmns for NameServer Query after RSCN */ 216 #define LPFC_NS_QUERY_GID_FT 0 217 #define LPFC_NS_QUERY_GID_PT 1 218 219 /* Delay Multiplier constant */ 220 #define LPFC_DMULT_CONST 651042 221 #define LPFC_DMULT_MAX 1023 222 223 /* Configuration of Interrupts / sec for entire HBA port */ 224 #define LPFC_MIN_IMAX 5000 225 #define LPFC_MAX_IMAX 5000000 226 #define LPFC_DEF_IMAX 0 227 228 #define LPFC_MAX_AUTO_EQ_DELAY 120 229 #define LPFC_EQ_DELAY_STEP 15 230 #define LPFC_EQD_ISR_TRIGGER 20000 231 /* 1s intervals */ 232 #define LPFC_EQ_DELAY_MSECS 1000 233 234 #define LPFC_MIN_CPU_MAP 0 235 #define LPFC_MAX_CPU_MAP 1 236 #define LPFC_HBA_CPU_MAP 1 237 238 /* PORT_CAPABILITIES constants. */ 239 #define LPFC_MAX_SUPPORTED_PAGES 8 240 241 enum ulp_bde64_word3 { 242 ULP_BDE64_SIZE_MASK = 0xffffff, 243 244 ULP_BDE64_TYPE_SHIFT = 24, 245 ULP_BDE64_TYPE_MASK = (0xff << ULP_BDE64_TYPE_SHIFT), 246 247 /* BDE (Host_resident) */ 248 ULP_BDE64_TYPE_BDE_64 = (0x00 << ULP_BDE64_TYPE_SHIFT), 249 /* Immediate Data BDE */ 250 ULP_BDE64_TYPE_BDE_IMMED = (0x01 << ULP_BDE64_TYPE_SHIFT), 251 /* BDE (Port-resident) */ 252 ULP_BDE64_TYPE_BDE_64P = (0x02 << ULP_BDE64_TYPE_SHIFT), 253 /* Input BDE (Host-resident) */ 254 ULP_BDE64_TYPE_BDE_64I = (0x08 << ULP_BDE64_TYPE_SHIFT), 255 /* Input BDE (Port-resident) */ 256 ULP_BDE64_TYPE_BDE_64IP = (0x0A << ULP_BDE64_TYPE_SHIFT), 257 /* BLP (Host-resident) */ 258 ULP_BDE64_TYPE_BLP_64 = (0x40 << ULP_BDE64_TYPE_SHIFT), 259 /* BLP (Port-resident) */ 260 ULP_BDE64_TYPE_BLP_64P = (0x42 << ULP_BDE64_TYPE_SHIFT), 261 }; 262 263 struct ulp_bde64_le { 264 __le32 type_size; /* type 31:24, size 23:0 */ 265 __le32 addr_low; 266 __le32 addr_high; 267 }; 268 269 struct ulp_bde64 { 270 union ULP_BDE_TUS { 271 uint32_t w; 272 struct { 273 #ifdef __BIG_ENDIAN_BITFIELD 274 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 275 VALUE !! */ 276 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 277 #else /* __LITTLE_ENDIAN_BITFIELD */ 278 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 279 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 280 VALUE !! */ 281 #endif 282 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 283 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 284 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 285 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 286 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 287 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 288 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 289 } f; 290 } tus; 291 uint32_t addrLow; 292 uint32_t addrHigh; 293 }; 294 295 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 296 #define LPFC_MAX_BDE_IMM_SIZE 64 297 298 struct lpfc_sli4_flags { 299 uint32_t word0; 300 #define lpfc_idx_rsrc_rdy_SHIFT 0 301 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 302 #define lpfc_idx_rsrc_rdy_WORD word0 303 #define LPFC_IDX_RSRC_RDY 1 304 #define lpfc_rpi_rsrc_rdy_SHIFT 1 305 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 306 #define lpfc_rpi_rsrc_rdy_WORD word0 307 #define LPFC_RPI_RSRC_RDY 1 308 #define lpfc_vpi_rsrc_rdy_SHIFT 2 309 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 310 #define lpfc_vpi_rsrc_rdy_WORD word0 311 #define LPFC_VPI_RSRC_RDY 1 312 #define lpfc_vfi_rsrc_rdy_SHIFT 3 313 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 314 #define lpfc_vfi_rsrc_rdy_WORD word0 315 #define LPFC_VFI_RSRC_RDY 1 316 #define lpfc_ftr_ashdr_SHIFT 4 317 #define lpfc_ftr_ashdr_MASK 0x00000001 318 #define lpfc_ftr_ashdr_WORD word0 319 }; 320 321 struct sli4_bls_rsp { 322 uint32_t word0_rsvd; /* Word0 must be reserved */ 323 uint32_t word1; 324 #define lpfc_abts_orig_SHIFT 0 325 #define lpfc_abts_orig_MASK 0x00000001 326 #define lpfc_abts_orig_WORD word1 327 #define LPFC_ABTS_UNSOL_RSP 1 328 #define LPFC_ABTS_UNSOL_INT 0 329 uint32_t word2; 330 #define lpfc_abts_rxid_SHIFT 0 331 #define lpfc_abts_rxid_MASK 0x0000FFFF 332 #define lpfc_abts_rxid_WORD word2 333 #define lpfc_abts_oxid_SHIFT 16 334 #define lpfc_abts_oxid_MASK 0x0000FFFF 335 #define lpfc_abts_oxid_WORD word2 336 uint32_t word3; 337 #define lpfc_vndr_code_SHIFT 0 338 #define lpfc_vndr_code_MASK 0x000000FF 339 #define lpfc_vndr_code_WORD word3 340 #define lpfc_rsn_expln_SHIFT 8 341 #define lpfc_rsn_expln_MASK 0x000000FF 342 #define lpfc_rsn_expln_WORD word3 343 #define lpfc_rsn_code_SHIFT 16 344 #define lpfc_rsn_code_MASK 0x000000FF 345 #define lpfc_rsn_code_WORD word3 346 347 uint32_t word4; 348 uint32_t word5_rsvd; /* Word5 must be reserved */ 349 }; 350 351 /* event queue entry structure */ 352 struct lpfc_eqe { 353 uint32_t word0; 354 #define lpfc_eqe_resource_id_SHIFT 16 355 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 356 #define lpfc_eqe_resource_id_WORD word0 357 #define lpfc_eqe_minor_code_SHIFT 4 358 #define lpfc_eqe_minor_code_MASK 0x00000FFF 359 #define lpfc_eqe_minor_code_WORD word0 360 #define lpfc_eqe_major_code_SHIFT 1 361 #define lpfc_eqe_major_code_MASK 0x00000007 362 #define lpfc_eqe_major_code_WORD word0 363 #define lpfc_eqe_valid_SHIFT 0 364 #define lpfc_eqe_valid_MASK 0x00000001 365 #define lpfc_eqe_valid_WORD word0 366 }; 367 368 /* completion queue entry structure (common fields for all cqe types) */ 369 struct lpfc_cqe { 370 uint32_t reserved0; 371 uint32_t reserved1; 372 uint32_t reserved2; 373 uint32_t word3; 374 #define lpfc_cqe_valid_SHIFT 31 375 #define lpfc_cqe_valid_MASK 0x00000001 376 #define lpfc_cqe_valid_WORD word3 377 #define lpfc_cqe_code_SHIFT 16 378 #define lpfc_cqe_code_MASK 0x000000FF 379 #define lpfc_cqe_code_WORD word3 380 }; 381 382 /* Completion Queue Entry Status Codes */ 383 #define CQE_STATUS_SUCCESS 0x0 384 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 385 #define CQE_STATUS_REMOTE_STOP 0x2 386 #define CQE_STATUS_LOCAL_REJECT 0x3 387 #define CQE_STATUS_NPORT_RJT 0x4 388 #define CQE_STATUS_FABRIC_RJT 0x5 389 #define CQE_STATUS_NPORT_BSY 0x6 390 #define CQE_STATUS_FABRIC_BSY 0x7 391 #define CQE_STATUS_INTERMED_RSP 0x8 392 #define CQE_STATUS_LS_RJT 0x9 393 #define CQE_STATUS_CMD_REJECT 0xb 394 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 395 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 396 #define CQE_STATUS_DI_ERROR 0x16 397 398 /* Used when mapping CQE status to IOCB */ 399 #define LPFC_IOCB_STATUS_MASK 0xf 400 401 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 402 #define CQE_HW_STATUS_NO_ERR 0x0 403 #define CQE_HW_STATUS_UNDERRUN 0x1 404 #define CQE_HW_STATUS_OVERRUN 0x2 405 406 /* Completion Queue Entry Codes */ 407 #define CQE_CODE_COMPL_WQE 0x1 408 #define CQE_CODE_RELEASE_WQE 0x2 409 #define CQE_CODE_RECEIVE 0x4 410 #define CQE_CODE_XRI_ABORTED 0x5 411 #define CQE_CODE_RECEIVE_V1 0x9 412 #define CQE_CODE_NVME_ERSP 0xd 413 414 /* 415 * Define mask value for xri_aborted and wcqe completed CQE extended status. 416 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 417 */ 418 #define WCQE_PARAM_MASK 0x1FF 419 420 /* completion queue entry for wqe completions */ 421 struct lpfc_wcqe_complete { 422 uint32_t word0; 423 #define lpfc_wcqe_c_request_tag_SHIFT 16 424 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 425 #define lpfc_wcqe_c_request_tag_WORD word0 426 #define lpfc_wcqe_c_status_SHIFT 8 427 #define lpfc_wcqe_c_status_MASK 0x000000FF 428 #define lpfc_wcqe_c_status_WORD word0 429 #define lpfc_wcqe_c_hw_status_SHIFT 0 430 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 431 #define lpfc_wcqe_c_hw_status_WORD word0 432 #define lpfc_wcqe_c_ersp0_SHIFT 0 433 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 434 #define lpfc_wcqe_c_ersp0_WORD word0 435 uint32_t total_data_placed; 436 #define lpfc_wcqe_c_cmf_cg_SHIFT 31 437 #define lpfc_wcqe_c_cmf_cg_MASK 0x00000001 438 #define lpfc_wcqe_c_cmf_cg_WORD total_data_placed 439 #define lpfc_wcqe_c_cmf_bw_SHIFT 0 440 #define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF 441 #define lpfc_wcqe_c_cmf_bw_WORD total_data_placed 442 uint32_t parameter; 443 #define lpfc_wcqe_c_bg_edir_SHIFT 5 444 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 445 #define lpfc_wcqe_c_bg_edir_WORD parameter 446 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 447 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 448 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 449 #define lpfc_wcqe_c_bg_re_SHIFT 2 450 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 451 #define lpfc_wcqe_c_bg_re_WORD parameter 452 #define lpfc_wcqe_c_bg_ae_SHIFT 1 453 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 454 #define lpfc_wcqe_c_bg_ae_WORD parameter 455 #define lpfc_wcqe_c_bg_ge_SHIFT 0 456 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 457 #define lpfc_wcqe_c_bg_ge_WORD parameter 458 uint32_t word3; 459 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 460 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 461 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 462 #define lpfc_wcqe_c_xb_SHIFT 28 463 #define lpfc_wcqe_c_xb_MASK 0x00000001 464 #define lpfc_wcqe_c_xb_WORD word3 465 #define lpfc_wcqe_c_pv_SHIFT 27 466 #define lpfc_wcqe_c_pv_MASK 0x00000001 467 #define lpfc_wcqe_c_pv_WORD word3 468 #define lpfc_wcqe_c_priority_SHIFT 24 469 #define lpfc_wcqe_c_priority_MASK 0x00000007 470 #define lpfc_wcqe_c_priority_WORD word3 471 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 472 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 473 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 474 #define lpfc_wcqe_c_sqhead_SHIFT 0 475 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 476 #define lpfc_wcqe_c_sqhead_WORD word3 477 }; 478 479 /* completion queue entry for wqe release */ 480 struct lpfc_wcqe_release { 481 uint32_t reserved0; 482 uint32_t reserved1; 483 uint32_t word2; 484 #define lpfc_wcqe_r_wq_id_SHIFT 16 485 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 486 #define lpfc_wcqe_r_wq_id_WORD word2 487 #define lpfc_wcqe_r_wqe_index_SHIFT 0 488 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 489 #define lpfc_wcqe_r_wqe_index_WORD word2 490 uint32_t word3; 491 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 492 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 493 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 494 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 495 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 496 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 497 }; 498 499 struct sli4_wcqe_xri_aborted { 500 uint32_t word0; 501 #define lpfc_wcqe_xa_status_SHIFT 8 502 #define lpfc_wcqe_xa_status_MASK 0x000000FF 503 #define lpfc_wcqe_xa_status_WORD word0 504 uint32_t parameter; 505 uint32_t word2; 506 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 507 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 508 #define lpfc_wcqe_xa_remote_xid_WORD word2 509 #define lpfc_wcqe_xa_xri_SHIFT 0 510 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 511 #define lpfc_wcqe_xa_xri_WORD word2 512 uint32_t word3; 513 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 514 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 515 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 516 #define lpfc_wcqe_xa_ia_SHIFT 30 517 #define lpfc_wcqe_xa_ia_MASK 0x00000001 518 #define lpfc_wcqe_xa_ia_WORD word3 519 #define CQE_XRI_ABORTED_IA_REMOTE 0 520 #define CQE_XRI_ABORTED_IA_LOCAL 1 521 #define lpfc_wcqe_xa_br_SHIFT 29 522 #define lpfc_wcqe_xa_br_MASK 0x00000001 523 #define lpfc_wcqe_xa_br_WORD word3 524 #define CQE_XRI_ABORTED_BR_BA_ACC 0 525 #define CQE_XRI_ABORTED_BR_BA_RJT 1 526 #define lpfc_wcqe_xa_eo_SHIFT 28 527 #define lpfc_wcqe_xa_eo_MASK 0x00000001 528 #define lpfc_wcqe_xa_eo_WORD word3 529 #define CQE_XRI_ABORTED_EO_REMOTE 0 530 #define CQE_XRI_ABORTED_EO_LOCAL 1 531 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 532 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 533 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 534 }; 535 536 /* completion queue entry structure for rqe completion */ 537 struct lpfc_rcqe { 538 uint32_t word0; 539 #define lpfc_rcqe_bindex_SHIFT 16 540 #define lpfc_rcqe_bindex_MASK 0x0000FFF 541 #define lpfc_rcqe_bindex_WORD word0 542 #define lpfc_rcqe_status_SHIFT 8 543 #define lpfc_rcqe_status_MASK 0x000000FF 544 #define lpfc_rcqe_status_WORD word0 545 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 546 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 547 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 548 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 549 uint32_t word1; 550 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 551 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 552 #define lpfc_rcqe_fcf_id_v1_WORD word1 553 uint32_t word2; 554 #define lpfc_rcqe_length_SHIFT 16 555 #define lpfc_rcqe_length_MASK 0x0000FFFF 556 #define lpfc_rcqe_length_WORD word2 557 #define lpfc_rcqe_rq_id_SHIFT 6 558 #define lpfc_rcqe_rq_id_MASK 0x000003FF 559 #define lpfc_rcqe_rq_id_WORD word2 560 #define lpfc_rcqe_fcf_id_SHIFT 0 561 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 562 #define lpfc_rcqe_fcf_id_WORD word2 563 #define lpfc_rcqe_rq_id_v1_SHIFT 0 564 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 565 #define lpfc_rcqe_rq_id_v1_WORD word2 566 uint32_t word3; 567 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 568 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 569 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 570 #define lpfc_rcqe_port_SHIFT 30 571 #define lpfc_rcqe_port_MASK 0x00000001 572 #define lpfc_rcqe_port_WORD word3 573 #define lpfc_rcqe_hdr_length_SHIFT 24 574 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 575 #define lpfc_rcqe_hdr_length_WORD word3 576 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 577 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 578 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 579 #define lpfc_rcqe_eof_SHIFT 8 580 #define lpfc_rcqe_eof_MASK 0x000000FF 581 #define lpfc_rcqe_eof_WORD word3 582 #define FCOE_EOFn 0x41 583 #define FCOE_EOFt 0x42 584 #define FCOE_EOFni 0x49 585 #define FCOE_EOFa 0x50 586 #define lpfc_rcqe_sof_SHIFT 0 587 #define lpfc_rcqe_sof_MASK 0x000000FF 588 #define lpfc_rcqe_sof_WORD word3 589 #define FCOE_SOFi2 0x2d 590 #define FCOE_SOFi3 0x2e 591 #define FCOE_SOFn2 0x35 592 #define FCOE_SOFn3 0x36 593 }; 594 595 struct lpfc_rqe { 596 uint32_t address_hi; 597 uint32_t address_lo; 598 }; 599 600 /* buffer descriptors */ 601 struct lpfc_bde4 { 602 uint32_t addr_hi; 603 uint32_t addr_lo; 604 uint32_t word2; 605 #define lpfc_bde4_last_SHIFT 31 606 #define lpfc_bde4_last_MASK 0x00000001 607 #define lpfc_bde4_last_WORD word2 608 #define lpfc_bde4_sge_offset_SHIFT 0 609 #define lpfc_bde4_sge_offset_MASK 0x000003FF 610 #define lpfc_bde4_sge_offset_WORD word2 611 uint32_t word3; 612 #define lpfc_bde4_length_SHIFT 0 613 #define lpfc_bde4_length_MASK 0x000000FF 614 #define lpfc_bde4_length_WORD word3 615 }; 616 617 struct lpfc_register { 618 uint32_t word0; 619 }; 620 621 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 622 #define LPFC_PORT_SEM_MASK 0xF000 623 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 624 #define LPFC_UERR_STATUS_HI 0x00A4 625 #define LPFC_UERR_STATUS_LO 0x00A0 626 #define LPFC_UE_MASK_HI 0x00AC 627 #define LPFC_UE_MASK_LO 0x00A8 628 629 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 630 #define LPFC_SLI_INTF 0x0058 631 #define LPFC_SLI_ASIC_VER 0x009C 632 633 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 634 #define lpfc_port_smphr_perr_SHIFT 31 635 #define lpfc_port_smphr_perr_MASK 0x1 636 #define lpfc_port_smphr_perr_WORD word0 637 #define lpfc_port_smphr_sfi_SHIFT 30 638 #define lpfc_port_smphr_sfi_MASK 0x1 639 #define lpfc_port_smphr_sfi_WORD word0 640 #define lpfc_port_smphr_nip_SHIFT 29 641 #define lpfc_port_smphr_nip_MASK 0x1 642 #define lpfc_port_smphr_nip_WORD word0 643 #define lpfc_port_smphr_ipc_SHIFT 28 644 #define lpfc_port_smphr_ipc_MASK 0x1 645 #define lpfc_port_smphr_ipc_WORD word0 646 #define lpfc_port_smphr_scr1_SHIFT 27 647 #define lpfc_port_smphr_scr1_MASK 0x1 648 #define lpfc_port_smphr_scr1_WORD word0 649 #define lpfc_port_smphr_scr2_SHIFT 26 650 #define lpfc_port_smphr_scr2_MASK 0x1 651 #define lpfc_port_smphr_scr2_WORD word0 652 #define lpfc_port_smphr_host_scratch_SHIFT 16 653 #define lpfc_port_smphr_host_scratch_MASK 0xFF 654 #define lpfc_port_smphr_host_scratch_WORD word0 655 #define lpfc_port_smphr_port_status_SHIFT 0 656 #define lpfc_port_smphr_port_status_MASK 0xFFFF 657 #define lpfc_port_smphr_port_status_WORD word0 658 659 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 660 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 661 #define LPFC_POST_STAGE_HOST_RDY 0x0002 662 #define LPFC_POST_STAGE_BE_RESET 0x0003 663 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 664 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 665 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 666 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 667 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 668 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 669 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 670 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 671 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 672 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 673 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 674 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 675 #define LPFC_POST_STAGE_ARMFW_START 0x0800 676 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 677 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 678 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 679 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 680 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 681 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 682 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 683 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 684 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 685 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 686 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 687 #define LPFC_POST_STAGE_RC_DONE 0x0B07 688 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 689 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 690 #define LPFC_POST_STAGE_PORT_READY 0xC000 691 #define LPFC_POST_STAGE_PORT_UE 0xF000 692 693 #define LPFC_CTL_PORT_STA_OFFSET 0x404 694 #define lpfc_sliport_status_err_SHIFT 31 695 #define lpfc_sliport_status_err_MASK 0x1 696 #define lpfc_sliport_status_err_WORD word0 697 #define lpfc_sliport_status_end_SHIFT 30 698 #define lpfc_sliport_status_end_MASK 0x1 699 #define lpfc_sliport_status_end_WORD word0 700 #define lpfc_sliport_status_oti_SHIFT 29 701 #define lpfc_sliport_status_oti_MASK 0x1 702 #define lpfc_sliport_status_oti_WORD word0 703 #define lpfc_sliport_status_dip_SHIFT 25 704 #define lpfc_sliport_status_dip_MASK 0x1 705 #define lpfc_sliport_status_dip_WORD word0 706 #define lpfc_sliport_status_rn_SHIFT 24 707 #define lpfc_sliport_status_rn_MASK 0x1 708 #define lpfc_sliport_status_rn_WORD word0 709 #define lpfc_sliport_status_rdy_SHIFT 23 710 #define lpfc_sliport_status_rdy_MASK 0x1 711 #define lpfc_sliport_status_rdy_WORD word0 712 #define lpfc_sliport_status_pldv_SHIFT 0 713 #define lpfc_sliport_status_pldv_MASK 0x1 714 #define lpfc_sliport_status_pldv_WORD word0 715 #define CFG_PLD 0x3C 716 #define MAX_IF_TYPE_2_RESETS 6 717 718 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 719 #define lpfc_sliport_ctrl_end_SHIFT 30 720 #define lpfc_sliport_ctrl_end_MASK 0x1 721 #define lpfc_sliport_ctrl_end_WORD word0 722 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 723 #define LPFC_SLIPORT_BIG_ENDIAN 1 724 #define lpfc_sliport_ctrl_ip_SHIFT 27 725 #define lpfc_sliport_ctrl_ip_MASK 0x1 726 #define lpfc_sliport_ctrl_ip_WORD word0 727 #define LPFC_SLIPORT_INIT_PORT 1 728 729 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 730 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 731 732 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 733 #define lpfc_sliport_eqdelay_delay_SHIFT 16 734 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 735 #define lpfc_sliport_eqdelay_delay_WORD word0 736 #define lpfc_sliport_eqdelay_id_SHIFT 0 737 #define lpfc_sliport_eqdelay_id_MASK 0xfff 738 #define lpfc_sliport_eqdelay_id_WORD word0 739 #define LPFC_SEC_TO_USEC 1000000 740 #define LPFC_SEC_TO_MSEC 1000 741 #define LPFC_MSECS_TO_SECS(msecs) ((msecs) / 1000) 742 743 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 744 * reside in BAR 2. 745 */ 746 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 747 748 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 749 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 750 751 #define LPFC_HST_ISR0 0x0C18 752 #define LPFC_HST_ISR1 0x0C1C 753 #define LPFC_HST_ISR2 0x0C20 754 #define LPFC_HST_ISR3 0x0C24 755 #define LPFC_HST_ISR4 0x0C28 756 757 #define LPFC_HST_IMR0 0x0C48 758 #define LPFC_HST_IMR1 0x0C4C 759 #define LPFC_HST_IMR2 0x0C50 760 #define LPFC_HST_IMR3 0x0C54 761 #define LPFC_HST_IMR4 0x0C58 762 763 #define LPFC_HST_ISCR0 0x0C78 764 #define LPFC_HST_ISCR1 0x0C7C 765 #define LPFC_HST_ISCR2 0x0C80 766 #define LPFC_HST_ISCR3 0x0C84 767 #define LPFC_HST_ISCR4 0x0C88 768 769 #define LPFC_SLI4_INTR0 BIT0 770 #define LPFC_SLI4_INTR1 BIT1 771 #define LPFC_SLI4_INTR2 BIT2 772 #define LPFC_SLI4_INTR3 BIT3 773 #define LPFC_SLI4_INTR4 BIT4 774 #define LPFC_SLI4_INTR5 BIT5 775 #define LPFC_SLI4_INTR6 BIT6 776 #define LPFC_SLI4_INTR7 BIT7 777 #define LPFC_SLI4_INTR8 BIT8 778 #define LPFC_SLI4_INTR9 BIT9 779 #define LPFC_SLI4_INTR10 BIT10 780 #define LPFC_SLI4_INTR11 BIT11 781 #define LPFC_SLI4_INTR12 BIT12 782 #define LPFC_SLI4_INTR13 BIT13 783 #define LPFC_SLI4_INTR14 BIT14 784 #define LPFC_SLI4_INTR15 BIT15 785 #define LPFC_SLI4_INTR16 BIT16 786 #define LPFC_SLI4_INTR17 BIT17 787 #define LPFC_SLI4_INTR18 BIT18 788 #define LPFC_SLI4_INTR19 BIT19 789 #define LPFC_SLI4_INTR20 BIT20 790 #define LPFC_SLI4_INTR21 BIT21 791 #define LPFC_SLI4_INTR22 BIT22 792 #define LPFC_SLI4_INTR23 BIT23 793 #define LPFC_SLI4_INTR24 BIT24 794 #define LPFC_SLI4_INTR25 BIT25 795 #define LPFC_SLI4_INTR26 BIT26 796 #define LPFC_SLI4_INTR27 BIT27 797 #define LPFC_SLI4_INTR28 BIT28 798 #define LPFC_SLI4_INTR29 BIT29 799 #define LPFC_SLI4_INTR30 BIT30 800 #define LPFC_SLI4_INTR31 BIT31 801 802 /* 803 * The Doorbell registers defined here exist in different BAR 804 * register sets depending on the UCNA Port's reported if_type 805 * value. For UCNA ports running SLI4 and if_type 0, they reside in 806 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 807 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 808 * BAR2. The offsets and base address are different, so the driver 809 * has to compute the register addresses accordingly 810 */ 811 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 812 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 813 #define LPFC_IF6_RQ_DOORBELL 0x0080 814 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 815 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 816 #define lpfc_rq_db_list_fm_num_posted_WORD word0 817 #define lpfc_rq_db_list_fm_index_SHIFT 16 818 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 819 #define lpfc_rq_db_list_fm_index_WORD word0 820 #define lpfc_rq_db_list_fm_id_SHIFT 0 821 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 822 #define lpfc_rq_db_list_fm_id_WORD word0 823 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 824 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 825 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 826 #define lpfc_rq_db_ring_fm_id_SHIFT 0 827 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 828 #define lpfc_rq_db_ring_fm_id_WORD word0 829 830 #define LPFC_ULP0_WQ_DOORBELL 0x0040 831 #define LPFC_ULP1_WQ_DOORBELL 0x0060 832 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 833 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 834 #define lpfc_wq_db_list_fm_num_posted_WORD word0 835 #define lpfc_wq_db_list_fm_index_SHIFT 16 836 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 837 #define lpfc_wq_db_list_fm_index_WORD word0 838 #define lpfc_wq_db_list_fm_id_SHIFT 0 839 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 840 #define lpfc_wq_db_list_fm_id_WORD word0 841 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 842 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 843 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 844 #define lpfc_wq_db_ring_fm_id_SHIFT 0 845 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 846 #define lpfc_wq_db_ring_fm_id_WORD word0 847 848 #define LPFC_IF6_WQ_DOORBELL 0x0040 849 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 850 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 851 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 852 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 853 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 854 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 855 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 856 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 857 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 858 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 859 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 860 #define lpfc_if6_wq_db_list_fm_id_WORD word0 861 862 #define LPFC_EQCQ_DOORBELL 0x0120 863 #define lpfc_eqcq_doorbell_se_SHIFT 31 864 #define lpfc_eqcq_doorbell_se_MASK 0x0001 865 #define lpfc_eqcq_doorbell_se_WORD word0 866 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 867 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 868 #define lpfc_eqcq_doorbell_arm_SHIFT 29 869 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 870 #define lpfc_eqcq_doorbell_arm_WORD word0 871 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 872 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 873 #define lpfc_eqcq_doorbell_num_released_WORD word0 874 #define lpfc_eqcq_doorbell_qt_SHIFT 10 875 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 876 #define lpfc_eqcq_doorbell_qt_WORD word0 877 #define LPFC_QUEUE_TYPE_COMPLETION 0 878 #define LPFC_QUEUE_TYPE_EVENT 1 879 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 880 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 881 #define lpfc_eqcq_doorbell_eqci_WORD word0 882 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 883 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 884 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 885 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 886 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 887 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 888 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 889 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 890 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 891 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 892 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 893 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 894 #define LPFC_CQID_HI_FIELD_SHIFT 10 895 #define LPFC_EQID_HI_FIELD_SHIFT 9 896 897 #define LPFC_IF6_CQ_DOORBELL 0x00C0 898 #define lpfc_if6_cq_doorbell_se_SHIFT 31 899 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 900 #define lpfc_if6_cq_doorbell_se_WORD word0 901 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 902 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 903 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 904 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 905 #define lpfc_if6_cq_doorbell_arm_WORD word0 906 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 907 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 908 #define lpfc_if6_cq_doorbell_num_released_WORD word0 909 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 910 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 911 #define lpfc_if6_cq_doorbell_cqid_WORD word0 912 913 #define LPFC_IF6_EQ_DOORBELL 0x0120 914 #define lpfc_if6_eq_doorbell_io_SHIFT 31 915 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 916 #define lpfc_if6_eq_doorbell_io_WORD word0 917 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 918 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 919 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 920 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 921 #define lpfc_if6_eq_doorbell_arm_WORD word0 922 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 923 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 924 #define lpfc_if6_eq_doorbell_num_released_WORD word0 925 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 926 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 927 #define lpfc_if6_eq_doorbell_eqid_WORD word0 928 929 #define LPFC_BMBX 0x0160 930 #define lpfc_bmbx_addr_SHIFT 2 931 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 932 #define lpfc_bmbx_addr_WORD word0 933 #define lpfc_bmbx_hi_SHIFT 1 934 #define lpfc_bmbx_hi_MASK 0x0001 935 #define lpfc_bmbx_hi_WORD word0 936 #define lpfc_bmbx_rdy_SHIFT 0 937 #define lpfc_bmbx_rdy_MASK 0x0001 938 #define lpfc_bmbx_rdy_WORD word0 939 940 #define LPFC_MQ_DOORBELL 0x0140 941 #define LPFC_IF6_MQ_DOORBELL 0x0160 942 #define lpfc_mq_doorbell_num_posted_SHIFT 16 943 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 944 #define lpfc_mq_doorbell_num_posted_WORD word0 945 #define lpfc_mq_doorbell_id_SHIFT 0 946 #define lpfc_mq_doorbell_id_MASK 0xFFFF 947 #define lpfc_mq_doorbell_id_WORD word0 948 949 struct lpfc_sli4_cfg_mhdr { 950 uint32_t word1; 951 #define lpfc_mbox_hdr_emb_SHIFT 0 952 #define lpfc_mbox_hdr_emb_MASK 0x00000001 953 #define lpfc_mbox_hdr_emb_WORD word1 954 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 955 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 956 #define lpfc_mbox_hdr_sge_cnt_WORD word1 957 uint32_t payload_length; 958 uint32_t tag_lo; 959 uint32_t tag_hi; 960 uint32_t reserved5; 961 }; 962 963 union lpfc_sli4_cfg_shdr { 964 struct { 965 uint32_t word6; 966 #define lpfc_mbox_hdr_opcode_SHIFT 0 967 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 968 #define lpfc_mbox_hdr_opcode_WORD word6 969 #define lpfc_mbox_hdr_subsystem_SHIFT 8 970 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 971 #define lpfc_mbox_hdr_subsystem_WORD word6 972 #define lpfc_mbox_hdr_port_number_SHIFT 16 973 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 974 #define lpfc_mbox_hdr_port_number_WORD word6 975 #define lpfc_mbox_hdr_domain_SHIFT 24 976 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 977 #define lpfc_mbox_hdr_domain_WORD word6 978 uint32_t timeout; 979 uint32_t request_length; 980 uint32_t word9; 981 #define lpfc_mbox_hdr_version_SHIFT 0 982 #define lpfc_mbox_hdr_version_MASK 0x000000FF 983 #define lpfc_mbox_hdr_version_WORD word9 984 #define lpfc_mbox_hdr_pf_num_SHIFT 16 985 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 986 #define lpfc_mbox_hdr_pf_num_WORD word9 987 #define lpfc_mbox_hdr_vh_num_SHIFT 24 988 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 989 #define lpfc_mbox_hdr_vh_num_WORD word9 990 #define LPFC_Q_CREATE_VERSION_2 2 991 #define LPFC_Q_CREATE_VERSION_1 1 992 #define LPFC_Q_CREATE_VERSION_0 0 993 #define LPFC_OPCODE_VERSION_0 0 994 #define LPFC_OPCODE_VERSION_1 1 995 } request; 996 struct { 997 uint32_t word6; 998 #define lpfc_mbox_hdr_opcode_SHIFT 0 999 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 1000 #define lpfc_mbox_hdr_opcode_WORD word6 1001 #define lpfc_mbox_hdr_subsystem_SHIFT 8 1002 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 1003 #define lpfc_mbox_hdr_subsystem_WORD word6 1004 #define lpfc_mbox_hdr_domain_SHIFT 24 1005 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 1006 #define lpfc_mbox_hdr_domain_WORD word6 1007 uint32_t word7; 1008 #define lpfc_mbox_hdr_status_SHIFT 0 1009 #define lpfc_mbox_hdr_status_MASK 0x000000FF 1010 #define lpfc_mbox_hdr_status_WORD word7 1011 #define lpfc_mbox_hdr_add_status_SHIFT 8 1012 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 1013 #define lpfc_mbox_hdr_add_status_WORD word7 1014 #define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2 1015 #define lpfc_mbox_hdr_add_status_2_SHIFT 16 1016 #define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF 1017 #define lpfc_mbox_hdr_add_status_2_WORD word7 1018 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01 1019 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02 1020 uint32_t response_length; 1021 uint32_t actual_response_length; 1022 } response; 1023 }; 1024 1025 /* Mailbox Header structures. 1026 * struct mbox_header is defined for first generation SLI4_CFG mailbox 1027 * calls deployed for BE-based ports. 1028 * 1029 * struct sli4_mbox_header is defined for second generation SLI4 1030 * ports that don't deploy the SLI4_CFG mechanism. 1031 */ 1032 struct mbox_header { 1033 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1034 union lpfc_sli4_cfg_shdr cfg_shdr; 1035 }; 1036 1037 #define LPFC_EXTENT_LOCAL 0 1038 #define LPFC_TIMEOUT_DEFAULT 0 1039 #define LPFC_EXTENT_VERSION_DEFAULT 0 1040 1041 /* Subsystem Definitions */ 1042 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 1043 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 1044 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 1045 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 1046 1047 /* Device Specific Definitions */ 1048 1049 /* The HOST ENDIAN defines are in Big Endian format. */ 1050 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 1051 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 1052 1053 /* Common Opcodes */ 1054 #define LPFC_MBOX_OPCODE_NA 0x00 1055 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 1056 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 1057 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1058 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1059 #define LPFC_MBOX_OPCODE_NOP 0x21 1060 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1061 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1062 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1063 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1064 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1065 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1066 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1067 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1068 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1069 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1070 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1071 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1072 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1073 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1074 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1075 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1076 #define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E 1077 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1078 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1079 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1080 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1081 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1082 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1083 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1084 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1085 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1086 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1087 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1088 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1089 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1090 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1091 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1092 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1093 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1094 1095 /* FCoE Opcodes */ 1096 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1097 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1098 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1099 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1100 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1101 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1102 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1103 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1104 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1105 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1106 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1107 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1108 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1109 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1110 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1111 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1112 1113 /* Low level Opcodes */ 1114 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1115 1116 /* Mailbox command structures */ 1117 struct eq_context { 1118 uint32_t word0; 1119 #define lpfc_eq_context_size_SHIFT 31 1120 #define lpfc_eq_context_size_MASK 0x00000001 1121 #define lpfc_eq_context_size_WORD word0 1122 #define LPFC_EQE_SIZE_4 0x0 1123 #define LPFC_EQE_SIZE_16 0x1 1124 #define lpfc_eq_context_valid_SHIFT 29 1125 #define lpfc_eq_context_valid_MASK 0x00000001 1126 #define lpfc_eq_context_valid_WORD word0 1127 #define lpfc_eq_context_autovalid_SHIFT 28 1128 #define lpfc_eq_context_autovalid_MASK 0x00000001 1129 #define lpfc_eq_context_autovalid_WORD word0 1130 uint32_t word1; 1131 #define lpfc_eq_context_count_SHIFT 26 1132 #define lpfc_eq_context_count_MASK 0x00000003 1133 #define lpfc_eq_context_count_WORD word1 1134 #define LPFC_EQ_CNT_256 0x0 1135 #define LPFC_EQ_CNT_512 0x1 1136 #define LPFC_EQ_CNT_1024 0x2 1137 #define LPFC_EQ_CNT_2048 0x3 1138 #define LPFC_EQ_CNT_4096 0x4 1139 uint32_t word2; 1140 #define lpfc_eq_context_delay_multi_SHIFT 13 1141 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1142 #define lpfc_eq_context_delay_multi_WORD word2 1143 uint32_t reserved3; 1144 }; 1145 1146 struct eq_delay_info { 1147 uint32_t eq_id; 1148 uint32_t phase; 1149 uint32_t delay_multi; 1150 }; 1151 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1152 1153 struct sgl_page_pairs { 1154 uint32_t sgl_pg0_addr_lo; 1155 uint32_t sgl_pg0_addr_hi; 1156 uint32_t sgl_pg1_addr_lo; 1157 uint32_t sgl_pg1_addr_hi; 1158 }; 1159 1160 struct lpfc_mbx_post_sgl_pages { 1161 struct mbox_header header; 1162 uint32_t word0; 1163 #define lpfc_post_sgl_pages_xri_SHIFT 0 1164 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1165 #define lpfc_post_sgl_pages_xri_WORD word0 1166 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1167 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1168 #define lpfc_post_sgl_pages_xricnt_WORD word0 1169 struct sgl_page_pairs sgl_pg_pairs[1]; 1170 }; 1171 1172 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1173 struct lpfc_mbx_post_uembed_sgl_page1 { 1174 union lpfc_sli4_cfg_shdr cfg_shdr; 1175 uint32_t word0; 1176 struct sgl_page_pairs sgl_pg_pairs; 1177 }; 1178 1179 struct lpfc_mbx_sge { 1180 uint32_t pa_lo; 1181 uint32_t pa_hi; 1182 uint32_t length; 1183 }; 1184 1185 struct lpfc_mbx_host_buf { 1186 uint32_t length; 1187 uint32_t pa_lo; 1188 uint32_t pa_hi; 1189 }; 1190 1191 struct lpfc_mbx_nembed_cmd { 1192 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1193 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1194 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1195 }; 1196 1197 struct lpfc_mbx_nembed_sge_virt { 1198 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1199 }; 1200 1201 #define LPFC_MBX_OBJECT_NAME_LEN_DW 26 1202 struct lpfc_mbx_read_object { /* Version 0 */ 1203 struct mbox_header header; 1204 union { 1205 struct { 1206 uint32_t word0; 1207 #define lpfc_mbx_rd_object_rlen_SHIFT 0 1208 #define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF 1209 #define lpfc_mbx_rd_object_rlen_WORD word0 1210 uint32_t rd_object_offset; 1211 __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 1212 #define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */ 1213 uint32_t rd_object_cnt; 1214 struct lpfc_mbx_host_buf rd_object_hbuf[4]; 1215 } request; 1216 struct { 1217 uint32_t rd_object_actual_rlen; 1218 uint32_t word1; 1219 #define lpfc_mbx_rd_object_eof_SHIFT 31 1220 #define lpfc_mbx_rd_object_eof_MASK 0x1 1221 #define lpfc_mbx_rd_object_eof_WORD word1 1222 } response; 1223 } u; 1224 }; 1225 1226 struct lpfc_mbx_eq_create { 1227 struct mbox_header header; 1228 union { 1229 struct { 1230 uint32_t word0; 1231 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1232 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1233 #define lpfc_mbx_eq_create_num_pages_WORD word0 1234 struct eq_context context; 1235 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1236 } request; 1237 struct { 1238 uint32_t word0; 1239 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1240 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1241 #define lpfc_mbx_eq_create_q_id_WORD word0 1242 } response; 1243 } u; 1244 }; 1245 1246 struct lpfc_mbx_modify_eq_delay { 1247 struct mbox_header header; 1248 union { 1249 struct { 1250 uint32_t num_eq; 1251 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1252 } request; 1253 struct { 1254 uint32_t word0; 1255 } response; 1256 } u; 1257 }; 1258 1259 struct lpfc_mbx_eq_destroy { 1260 struct mbox_header header; 1261 union { 1262 struct { 1263 uint32_t word0; 1264 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1265 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1266 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1267 } request; 1268 struct { 1269 uint32_t word0; 1270 } response; 1271 } u; 1272 }; 1273 1274 struct lpfc_mbx_nop { 1275 struct mbox_header header; 1276 uint32_t context[2]; 1277 }; 1278 1279 1280 1281 struct lpfc_mbx_set_ras_fwlog { 1282 struct mbox_header header; 1283 union { 1284 struct { 1285 uint32_t word4; 1286 #define lpfc_fwlog_enable_SHIFT 0 1287 #define lpfc_fwlog_enable_MASK 0x00000001 1288 #define lpfc_fwlog_enable_WORD word4 1289 #define lpfc_fwlog_loglvl_SHIFT 8 1290 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1291 #define lpfc_fwlog_loglvl_WORD word4 1292 #define lpfc_fwlog_ra_SHIFT 15 1293 #define lpfc_fwlog_ra_WORD 0x00000008 1294 #define lpfc_fwlog_buffcnt_SHIFT 16 1295 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1296 #define lpfc_fwlog_buffcnt_WORD word4 1297 #define lpfc_fwlog_buffsz_SHIFT 24 1298 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1299 #define lpfc_fwlog_buffsz_WORD word4 1300 uint32_t word5; 1301 #define lpfc_fwlog_acqe_SHIFT 0 1302 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1303 #define lpfc_fwlog_acqe_WORD word5 1304 #define lpfc_fwlog_cqid_SHIFT 16 1305 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1306 #define lpfc_fwlog_cqid_WORD word5 1307 #define LPFC_MAX_FWLOG_PAGE 16 1308 struct dma_address lwpd; 1309 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1310 } request; 1311 struct { 1312 uint32_t word0; 1313 } response; 1314 } u; 1315 }; 1316 1317 1318 struct cq_context { 1319 uint32_t word0; 1320 #define lpfc_cq_context_event_SHIFT 31 1321 #define lpfc_cq_context_event_MASK 0x00000001 1322 #define lpfc_cq_context_event_WORD word0 1323 #define lpfc_cq_context_valid_SHIFT 29 1324 #define lpfc_cq_context_valid_MASK 0x00000001 1325 #define lpfc_cq_context_valid_WORD word0 1326 #define lpfc_cq_context_count_SHIFT 27 1327 #define lpfc_cq_context_count_MASK 0x00000003 1328 #define lpfc_cq_context_count_WORD word0 1329 #define LPFC_CQ_CNT_256 0x0 1330 #define LPFC_CQ_CNT_512 0x1 1331 #define LPFC_CQ_CNT_1024 0x2 1332 #define LPFC_CQ_CNT_WORD7 0x3 1333 #define lpfc_cq_context_autovalid_SHIFT 15 1334 #define lpfc_cq_context_autovalid_MASK 0x00000001 1335 #define lpfc_cq_context_autovalid_WORD word0 1336 uint32_t word1; 1337 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1338 #define lpfc_cq_eq_id_MASK 0x000000FF 1339 #define lpfc_cq_eq_id_WORD word1 1340 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1341 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1342 #define lpfc_cq_eq_id_2_WORD word1 1343 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1344 uint32_t reserved1; 1345 }; 1346 1347 struct lpfc_mbx_cq_create { 1348 struct mbox_header header; 1349 union { 1350 struct { 1351 uint32_t word0; 1352 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1353 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1354 #define lpfc_mbx_cq_create_page_size_WORD word0 1355 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1356 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1357 #define lpfc_mbx_cq_create_num_pages_WORD word0 1358 struct cq_context context; 1359 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1360 } request; 1361 struct { 1362 uint32_t word0; 1363 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1364 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1365 #define lpfc_mbx_cq_create_q_id_WORD word0 1366 } response; 1367 } u; 1368 }; 1369 1370 struct lpfc_mbx_cq_create_set { 1371 union lpfc_sli4_cfg_shdr cfg_shdr; 1372 union { 1373 struct { 1374 uint32_t word0; 1375 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1376 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1377 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1378 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1379 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1380 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1381 uint32_t word1; 1382 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1383 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1384 #define lpfc_mbx_cq_create_set_evt_WORD word1 1385 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1386 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1387 #define lpfc_mbx_cq_create_set_valid_WORD word1 1388 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1389 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1390 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1391 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1392 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1393 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1394 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1395 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1396 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1397 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1398 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1399 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1400 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1401 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1402 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1403 uint32_t word2; 1404 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1405 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1406 #define lpfc_mbx_cq_create_set_arm_WORD word2 1407 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1408 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1409 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1410 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1411 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1412 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1413 uint32_t word3; 1414 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1415 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1416 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1417 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1418 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1419 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1420 uint32_t word4; 1421 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1422 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1423 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1424 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1425 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1426 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1427 uint32_t word5; 1428 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1429 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1430 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1431 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1432 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1433 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1434 uint32_t word6; 1435 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1436 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1437 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1438 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1439 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1440 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1441 uint32_t word7; 1442 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1443 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1444 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1445 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1446 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1447 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1448 uint32_t word8; 1449 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1450 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1451 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1452 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1453 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1454 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1455 uint32_t word9; 1456 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1457 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1458 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1459 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1460 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1461 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1462 uint32_t word10; 1463 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1464 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1465 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1466 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1467 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1468 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1469 struct dma_address page[1]; 1470 } request; 1471 struct { 1472 uint32_t word0; 1473 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1474 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1475 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1476 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1477 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1478 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1479 } response; 1480 } u; 1481 }; 1482 1483 struct lpfc_mbx_cq_destroy { 1484 struct mbox_header header; 1485 union { 1486 struct { 1487 uint32_t word0; 1488 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1489 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1490 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1491 } request; 1492 struct { 1493 uint32_t word0; 1494 } response; 1495 } u; 1496 }; 1497 1498 struct wq_context { 1499 uint32_t reserved0; 1500 uint32_t reserved1; 1501 uint32_t reserved2; 1502 uint32_t reserved3; 1503 }; 1504 1505 struct lpfc_mbx_wq_create { 1506 struct mbox_header header; 1507 union { 1508 struct { /* Version 0 Request */ 1509 uint32_t word0; 1510 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1511 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1512 #define lpfc_mbx_wq_create_num_pages_WORD word0 1513 #define lpfc_mbx_wq_create_dua_SHIFT 8 1514 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1515 #define lpfc_mbx_wq_create_dua_WORD word0 1516 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1517 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1518 #define lpfc_mbx_wq_create_cq_id_WORD word0 1519 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1520 uint32_t word9; 1521 #define lpfc_mbx_wq_create_bua_SHIFT 0 1522 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1523 #define lpfc_mbx_wq_create_bua_WORD word9 1524 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1525 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1526 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1527 } request; 1528 struct { /* Version 1 Request */ 1529 uint32_t word0; /* Word 0 is the same as in v0 */ 1530 uint32_t word1; 1531 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1532 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1533 #define lpfc_mbx_wq_create_page_size_WORD word1 1534 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1535 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1536 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1537 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1538 #define lpfc_mbx_wq_create_doe_SHIFT 14 1539 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1540 #define lpfc_mbx_wq_create_doe_WORD word1 1541 #define lpfc_mbx_wq_create_toe_SHIFT 13 1542 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1543 #define lpfc_mbx_wq_create_toe_WORD word1 1544 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1545 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1546 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1547 #define LPFC_WQ_WQE_SIZE_64 0x5 1548 #define LPFC_WQ_WQE_SIZE_128 0x6 1549 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1550 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1551 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1552 uint32_t word2; 1553 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1554 } request_1; 1555 struct { 1556 uint32_t word0; 1557 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1558 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1559 #define lpfc_mbx_wq_create_q_id_WORD word0 1560 uint32_t doorbell_offset; 1561 uint32_t word2; 1562 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1563 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1564 #define lpfc_mbx_wq_create_bar_set_WORD word2 1565 #define WQ_PCI_BAR_0_AND_1 0x00 1566 #define WQ_PCI_BAR_2_AND_3 0x01 1567 #define WQ_PCI_BAR_4_AND_5 0x02 1568 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1569 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1570 #define lpfc_mbx_wq_create_db_format_WORD word2 1571 } response; 1572 struct { 1573 uint32_t word0; 1574 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1575 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1576 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1577 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1578 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1579 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1580 uint32_t word1; 1581 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1582 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1583 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1584 uint32_t doorbell_offset; 1585 uint32_t word3; 1586 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1587 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1588 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1589 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1590 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1591 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1592 uint32_t dpp_offset; 1593 } response_1; 1594 } u; 1595 }; 1596 1597 struct lpfc_mbx_wq_destroy { 1598 struct mbox_header header; 1599 union { 1600 struct { 1601 uint32_t word0; 1602 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1603 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1604 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1605 } request; 1606 struct { 1607 uint32_t word0; 1608 } response; 1609 } u; 1610 }; 1611 1612 #define LPFC_HDR_BUF_SIZE 128 1613 #define LPFC_DATA_BUF_SIZE 2048 1614 #define LPFC_NVMET_DATA_BUF_SIZE 128 1615 struct rq_context { 1616 uint32_t word0; 1617 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1618 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1619 #define lpfc_rq_context_rqe_count_WORD word0 1620 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1621 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1622 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1623 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1624 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1625 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1626 #define lpfc_rq_context_rqe_count_1_WORD word0 1627 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1628 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1629 #define lpfc_rq_context_rqe_size_WORD word0 1630 #define LPFC_RQE_SIZE_8 2 1631 #define LPFC_RQE_SIZE_16 3 1632 #define LPFC_RQE_SIZE_32 4 1633 #define LPFC_RQE_SIZE_64 5 1634 #define LPFC_RQE_SIZE_128 6 1635 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1636 #define lpfc_rq_context_page_size_MASK 0x000000FF 1637 #define lpfc_rq_context_page_size_WORD word0 1638 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1639 uint32_t word1; 1640 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1641 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1642 #define lpfc_rq_context_data_size_WORD word1 1643 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1644 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1645 #define lpfc_rq_context_hdr_size_WORD word1 1646 uint32_t word2; 1647 #define lpfc_rq_context_cq_id_SHIFT 16 1648 #define lpfc_rq_context_cq_id_MASK 0x0000FFFF 1649 #define lpfc_rq_context_cq_id_WORD word2 1650 #define lpfc_rq_context_buf_size_SHIFT 0 1651 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1652 #define lpfc_rq_context_buf_size_WORD word2 1653 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1654 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1655 #define lpfc_rq_context_base_cq_WORD word2 1656 uint32_t buffer_size; /* Version 1 Only */ 1657 }; 1658 1659 struct lpfc_mbx_rq_create { 1660 struct mbox_header header; 1661 union { 1662 struct { 1663 uint32_t word0; 1664 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1665 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1666 #define lpfc_mbx_rq_create_num_pages_WORD word0 1667 #define lpfc_mbx_rq_create_dua_SHIFT 16 1668 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1669 #define lpfc_mbx_rq_create_dua_WORD word0 1670 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1671 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1672 #define lpfc_mbx_rq_create_bqu_WORD word0 1673 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1674 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1675 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1676 struct rq_context context; 1677 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1678 } request; 1679 struct { 1680 uint32_t word0; 1681 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1682 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1683 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1684 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1685 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1686 #define lpfc_mbx_rq_create_q_id_WORD word0 1687 uint32_t doorbell_offset; 1688 uint32_t word2; 1689 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1690 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1691 #define lpfc_mbx_rq_create_bar_set_WORD word2 1692 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1693 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1694 #define lpfc_mbx_rq_create_db_format_WORD word2 1695 } response; 1696 } u; 1697 }; 1698 1699 struct lpfc_mbx_rq_create_v2 { 1700 union lpfc_sli4_cfg_shdr cfg_shdr; 1701 union { 1702 struct { 1703 uint32_t word0; 1704 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1705 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1706 #define lpfc_mbx_rq_create_num_pages_WORD word0 1707 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1708 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1709 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1710 #define lpfc_mbx_rq_create_dua_SHIFT 16 1711 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1712 #define lpfc_mbx_rq_create_dua_WORD word0 1713 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1714 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1715 #define lpfc_mbx_rq_create_bqu_WORD word0 1716 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1717 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1718 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1719 #define lpfc_mbx_rq_create_dim_SHIFT 29 1720 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1721 #define lpfc_mbx_rq_create_dim_WORD word0 1722 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1723 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1724 #define lpfc_mbx_rq_create_dfd_WORD word0 1725 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1726 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1727 #define lpfc_mbx_rq_create_dnb_WORD word0 1728 struct rq_context context; 1729 struct dma_address page[1]; 1730 } request; 1731 struct { 1732 uint32_t word0; 1733 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1734 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1735 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1736 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1737 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1738 #define lpfc_mbx_rq_create_q_id_WORD word0 1739 uint32_t doorbell_offset; 1740 uint32_t word2; 1741 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1742 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1743 #define lpfc_mbx_rq_create_bar_set_WORD word2 1744 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1745 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1746 #define lpfc_mbx_rq_create_db_format_WORD word2 1747 } response; 1748 } u; 1749 }; 1750 1751 struct lpfc_mbx_rq_destroy { 1752 struct mbox_header header; 1753 union { 1754 struct { 1755 uint32_t word0; 1756 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1757 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1758 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1759 } request; 1760 struct { 1761 uint32_t word0; 1762 } response; 1763 } u; 1764 }; 1765 1766 struct mq_context { 1767 uint32_t word0; 1768 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1769 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1770 #define lpfc_mq_context_cq_id_WORD word0 1771 #define lpfc_mq_context_ring_size_SHIFT 16 1772 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1773 #define lpfc_mq_context_ring_size_WORD word0 1774 #define LPFC_MQ_RING_SIZE_16 0x5 1775 #define LPFC_MQ_RING_SIZE_32 0x6 1776 #define LPFC_MQ_RING_SIZE_64 0x7 1777 #define LPFC_MQ_RING_SIZE_128 0x8 1778 uint32_t word1; 1779 #define lpfc_mq_context_valid_SHIFT 31 1780 #define lpfc_mq_context_valid_MASK 0x00000001 1781 #define lpfc_mq_context_valid_WORD word1 1782 uint32_t reserved2; 1783 uint32_t reserved3; 1784 }; 1785 1786 struct lpfc_mbx_mq_create { 1787 struct mbox_header header; 1788 union { 1789 struct { 1790 uint32_t word0; 1791 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1792 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1793 #define lpfc_mbx_mq_create_num_pages_WORD word0 1794 struct mq_context context; 1795 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1796 } request; 1797 struct { 1798 uint32_t word0; 1799 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1800 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1801 #define lpfc_mbx_mq_create_q_id_WORD word0 1802 } response; 1803 } u; 1804 }; 1805 1806 struct lpfc_mbx_mq_create_ext { 1807 struct mbox_header header; 1808 union { 1809 struct { 1810 uint32_t word0; 1811 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1812 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1813 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1814 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1815 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1816 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1817 uint32_t async_evt_bmap; 1818 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1819 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1820 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1821 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1822 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1823 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1824 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1825 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1826 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1827 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1828 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1829 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1830 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1831 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1832 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1833 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1834 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1835 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1836 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1837 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1838 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1839 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1840 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1841 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1842 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1843 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1844 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1845 struct mq_context context; 1846 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1847 } request; 1848 struct { 1849 uint32_t word0; 1850 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1851 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1852 #define lpfc_mbx_mq_create_q_id_WORD word0 1853 } response; 1854 } u; 1855 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1856 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1857 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1858 }; 1859 1860 struct lpfc_mbx_mq_destroy { 1861 struct mbox_header header; 1862 union { 1863 struct { 1864 uint32_t word0; 1865 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1866 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1867 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1868 } request; 1869 struct { 1870 uint32_t word0; 1871 } response; 1872 } u; 1873 }; 1874 1875 /* Start Gen 2 SLI4 Mailbox definitions: */ 1876 1877 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1878 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1879 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1880 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1881 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1882 1883 struct lpfc_mbx_get_rsrc_extent_info { 1884 struct mbox_header header; 1885 union { 1886 struct { 1887 uint32_t word4; 1888 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1889 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1890 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1891 } req; 1892 struct { 1893 uint32_t word4; 1894 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1895 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1896 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1897 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1898 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1899 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1900 } rsp; 1901 } u; 1902 }; 1903 1904 struct lpfc_mbx_query_fw_config { 1905 struct mbox_header header; 1906 struct { 1907 uint32_t config_number; 1908 #define LPFC_FC_FCOE 0x00000007 1909 uint32_t asic_revision; 1910 uint32_t physical_port; 1911 uint32_t function_mode; 1912 #define LPFC_FCOE_INI_MODE 0x00000040 1913 #define LPFC_FCOE_TGT_MODE 0x00000080 1914 #define LPFC_DUA_MODE 0x00000800 1915 uint32_t ulp0_mode; 1916 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1917 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1918 uint32_t ulp0_nap_words[12]; 1919 uint32_t ulp1_mode; 1920 uint32_t ulp1_nap_words[12]; 1921 uint32_t function_capabilities; 1922 uint32_t cqid_base; 1923 uint32_t cqid_tot; 1924 uint32_t eqid_base; 1925 uint32_t eqid_tot; 1926 uint32_t ulp0_nap2_words[2]; 1927 uint32_t ulp1_nap2_words[2]; 1928 } rsp; 1929 }; 1930 1931 struct lpfc_mbx_set_beacon_config { 1932 struct mbox_header header; 1933 uint32_t word4; 1934 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1935 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1936 #define lpfc_mbx_set_beacon_port_num_WORD word4 1937 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1938 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1939 #define lpfc_mbx_set_beacon_port_type_WORD word4 1940 #define lpfc_mbx_set_beacon_state_SHIFT 8 1941 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1942 #define lpfc_mbx_set_beacon_state_WORD word4 1943 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1944 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1945 #define lpfc_mbx_set_beacon_duration_WORD word4 1946 1947 /* COMMON_SET_BEACON_CONFIG_V1 */ 1948 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1949 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1950 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1951 uint32_t word5; /* RESERVED */ 1952 }; 1953 1954 struct lpfc_id_range { 1955 uint32_t word5; 1956 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1957 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1958 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1959 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1960 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1961 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1962 }; 1963 1964 struct lpfc_mbx_set_link_diag_state { 1965 struct mbox_header header; 1966 union { 1967 struct { 1968 uint32_t word0; 1969 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1970 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1971 #define lpfc_mbx_set_diag_state_diag_WORD word0 1972 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1973 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1974 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1975 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1976 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1977 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1978 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1979 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1980 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1981 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1982 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1983 } req; 1984 struct { 1985 uint32_t word0; 1986 } rsp; 1987 } u; 1988 }; 1989 1990 struct lpfc_mbx_set_link_diag_loopback { 1991 struct mbox_header header; 1992 union { 1993 struct { 1994 uint32_t word0; 1995 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1996 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1997 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1998 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1999 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 2000 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 2001 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 2002 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 2003 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 2004 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 2005 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 2006 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 2007 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 2008 } req; 2009 struct { 2010 uint32_t word0; 2011 } rsp; 2012 } u; 2013 }; 2014 2015 struct lpfc_mbx_run_link_diag_test { 2016 struct mbox_header header; 2017 union { 2018 struct { 2019 uint32_t word0; 2020 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 2021 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 2022 #define lpfc_mbx_run_diag_test_link_num_WORD word0 2023 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 2024 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 2025 #define lpfc_mbx_run_diag_test_link_type_WORD word0 2026 uint32_t word1; 2027 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 2028 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 2029 #define lpfc_mbx_run_diag_test_test_id_WORD word1 2030 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 2031 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 2032 #define lpfc_mbx_run_diag_test_loops_WORD word1 2033 uint32_t word2; 2034 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 2035 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 2036 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 2037 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 2038 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 2039 #define lpfc_mbx_run_diag_test_err_act_WORD word2 2040 } req; 2041 struct { 2042 uint32_t word0; 2043 } rsp; 2044 } u; 2045 }; 2046 2047 /* 2048 * struct lpfc_mbx_alloc_rsrc_extents: 2049 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 2050 * 6 words of header + 4 words of shared subcommand header + 2051 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 2052 * 2053 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 2054 * for extents payload. 2055 * 2056 * 212/2 (bytes per extent) = 106 extents. 2057 * 106/2 (extents per word) = 53 words. 2058 * lpfc_id_range id is statically size to 53. 2059 * 2060 * This mailbox definition is used for ALLOC or GET_ALLOCATED 2061 * extent ranges. For ALLOC, the type and cnt are required. 2062 * For GET_ALLOCATED, only the type is required. 2063 */ 2064 struct lpfc_mbx_alloc_rsrc_extents { 2065 struct mbox_header header; 2066 union { 2067 struct { 2068 uint32_t word4; 2069 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 2070 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 2071 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 2072 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 2073 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 2074 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 2075 } req; 2076 struct { 2077 uint32_t word4; 2078 #define lpfc_mbx_rsrc_cnt_SHIFT 0 2079 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 2080 #define lpfc_mbx_rsrc_cnt_WORD word4 2081 struct lpfc_id_range id[53]; 2082 } rsp; 2083 } u; 2084 }; 2085 2086 /* 2087 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 2088 * structure shares the same SHIFT/MASK/WORD defines provided in the 2089 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2090 * the structures defined above. This non-embedded structure provides for the 2091 * maximum number of extents supported by the port. 2092 */ 2093 struct lpfc_mbx_nembed_rsrc_extent { 2094 union lpfc_sli4_cfg_shdr cfg_shdr; 2095 uint32_t word4; 2096 struct lpfc_id_range id; 2097 }; 2098 2099 struct lpfc_mbx_dealloc_rsrc_extents { 2100 struct mbox_header header; 2101 struct { 2102 uint32_t word4; 2103 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2104 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2105 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2106 } req; 2107 2108 }; 2109 2110 /* Start SLI4 FCoE specific mbox structures. */ 2111 2112 struct lpfc_mbx_post_hdr_tmpl { 2113 struct mbox_header header; 2114 uint32_t word10; 2115 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2116 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2117 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2118 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2119 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2120 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2121 uint32_t rpi_paddr_lo; 2122 uint32_t rpi_paddr_hi; 2123 }; 2124 2125 struct sli4_sge { /* SLI-4 */ 2126 uint32_t addr_hi; 2127 uint32_t addr_lo; 2128 2129 uint32_t word2; 2130 #define lpfc_sli4_sge_offset_SHIFT 0 2131 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2132 #define lpfc_sli4_sge_offset_WORD word2 2133 #define lpfc_sli4_sge_type_SHIFT 27 2134 #define lpfc_sli4_sge_type_MASK 0x0000000F 2135 #define lpfc_sli4_sge_type_WORD word2 2136 #define LPFC_SGE_TYPE_DATA 0x0 2137 #define LPFC_SGE_TYPE_DIF 0x4 2138 #define LPFC_SGE_TYPE_LSP 0x5 2139 #define LPFC_SGE_TYPE_PEDIF 0x6 2140 #define LPFC_SGE_TYPE_PESEED 0x7 2141 #define LPFC_SGE_TYPE_DISEED 0x8 2142 #define LPFC_SGE_TYPE_ENC 0x9 2143 #define LPFC_SGE_TYPE_ATM 0xA 2144 #define LPFC_SGE_TYPE_SKIP 0xC 2145 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2146 #define lpfc_sli4_sge_last_MASK 0x00000001 2147 #define lpfc_sli4_sge_last_WORD word2 2148 uint32_t sge_len; 2149 }; 2150 2151 struct sli4_hybrid_sgl { 2152 struct list_head list_node; 2153 struct sli4_sge *dma_sgl; 2154 dma_addr_t dma_phys_sgl; 2155 }; 2156 2157 struct fcp_cmd_rsp_buf { 2158 struct list_head list_node; 2159 2160 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2161 struct fcp_cmnd *fcp_cmnd; 2162 struct fcp_rsp *fcp_rsp; 2163 2164 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2165 dma_addr_t fcp_cmd_rsp_dma_handle; 2166 }; 2167 2168 struct sli4_sge_diseed { /* SLI-4 */ 2169 uint32_t ref_tag; 2170 uint32_t ref_tag_tran; 2171 2172 uint32_t word2; 2173 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2174 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2175 #define lpfc_sli4_sge_dif_apptran_WORD word2 2176 #define lpfc_sli4_sge_dif_af_SHIFT 24 2177 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2178 #define lpfc_sli4_sge_dif_af_WORD word2 2179 #define lpfc_sli4_sge_dif_na_SHIFT 25 2180 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2181 #define lpfc_sli4_sge_dif_na_WORD word2 2182 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2183 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2184 #define lpfc_sli4_sge_dif_hi_WORD word2 2185 #define lpfc_sli4_sge_dif_type_SHIFT 27 2186 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2187 #define lpfc_sli4_sge_dif_type_WORD word2 2188 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2189 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2190 #define lpfc_sli4_sge_dif_last_WORD word2 2191 uint32_t word3; 2192 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2193 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2194 #define lpfc_sli4_sge_dif_apptag_WORD word3 2195 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2196 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2197 #define lpfc_sli4_sge_dif_bs_WORD word3 2198 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2199 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2200 #define lpfc_sli4_sge_dif_ai_WORD word3 2201 #define lpfc_sli4_sge_dif_me_SHIFT 20 2202 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2203 #define lpfc_sli4_sge_dif_me_WORD word3 2204 #define lpfc_sli4_sge_dif_re_SHIFT 21 2205 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2206 #define lpfc_sli4_sge_dif_re_WORD word3 2207 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2208 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2209 #define lpfc_sli4_sge_dif_ce_WORD word3 2210 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2211 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2212 #define lpfc_sli4_sge_dif_nr_WORD word3 2213 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2214 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2215 #define lpfc_sli4_sge_dif_oprx_WORD word3 2216 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2217 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2218 #define lpfc_sli4_sge_dif_optx_WORD word3 2219 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2220 }; 2221 2222 struct fcf_record { 2223 uint32_t max_rcv_size; 2224 uint32_t fka_adv_period; 2225 uint32_t fip_priority; 2226 uint32_t word3; 2227 #define lpfc_fcf_record_mac_0_SHIFT 0 2228 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2229 #define lpfc_fcf_record_mac_0_WORD word3 2230 #define lpfc_fcf_record_mac_1_SHIFT 8 2231 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2232 #define lpfc_fcf_record_mac_1_WORD word3 2233 #define lpfc_fcf_record_mac_2_SHIFT 16 2234 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2235 #define lpfc_fcf_record_mac_2_WORD word3 2236 #define lpfc_fcf_record_mac_3_SHIFT 24 2237 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2238 #define lpfc_fcf_record_mac_3_WORD word3 2239 uint32_t word4; 2240 #define lpfc_fcf_record_mac_4_SHIFT 0 2241 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2242 #define lpfc_fcf_record_mac_4_WORD word4 2243 #define lpfc_fcf_record_mac_5_SHIFT 8 2244 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2245 #define lpfc_fcf_record_mac_5_WORD word4 2246 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2247 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2248 #define lpfc_fcf_record_fcf_avail_WORD word4 2249 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2250 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2251 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2252 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2253 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2254 uint32_t word5; 2255 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2256 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2257 #define lpfc_fcf_record_fab_name_0_WORD word5 2258 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2259 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2260 #define lpfc_fcf_record_fab_name_1_WORD word5 2261 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2262 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2263 #define lpfc_fcf_record_fab_name_2_WORD word5 2264 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2265 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2266 #define lpfc_fcf_record_fab_name_3_WORD word5 2267 uint32_t word6; 2268 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2269 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2270 #define lpfc_fcf_record_fab_name_4_WORD word6 2271 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2272 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2273 #define lpfc_fcf_record_fab_name_5_WORD word6 2274 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2275 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2276 #define lpfc_fcf_record_fab_name_6_WORD word6 2277 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2278 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2279 #define lpfc_fcf_record_fab_name_7_WORD word6 2280 uint32_t word7; 2281 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2282 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2283 #define lpfc_fcf_record_fc_map_0_WORD word7 2284 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2285 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2286 #define lpfc_fcf_record_fc_map_1_WORD word7 2287 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2288 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2289 #define lpfc_fcf_record_fc_map_2_WORD word7 2290 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2291 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2292 #define lpfc_fcf_record_fcf_valid_WORD word7 2293 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2294 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2295 #define lpfc_fcf_record_fcf_fc_WORD word7 2296 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2297 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2298 #define lpfc_fcf_record_fcf_sol_WORD word7 2299 uint32_t word8; 2300 #define lpfc_fcf_record_fcf_index_SHIFT 0 2301 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2302 #define lpfc_fcf_record_fcf_index_WORD word8 2303 #define lpfc_fcf_record_fcf_state_SHIFT 16 2304 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2305 #define lpfc_fcf_record_fcf_state_WORD word8 2306 uint8_t vlan_bitmap[512]; 2307 uint32_t word137; 2308 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2309 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2310 #define lpfc_fcf_record_switch_name_0_WORD word137 2311 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2312 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2313 #define lpfc_fcf_record_switch_name_1_WORD word137 2314 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2315 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2316 #define lpfc_fcf_record_switch_name_2_WORD word137 2317 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2318 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2319 #define lpfc_fcf_record_switch_name_3_WORD word137 2320 uint32_t word138; 2321 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2322 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2323 #define lpfc_fcf_record_switch_name_4_WORD word138 2324 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2325 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2326 #define lpfc_fcf_record_switch_name_5_WORD word138 2327 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2328 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2329 #define lpfc_fcf_record_switch_name_6_WORD word138 2330 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2331 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2332 #define lpfc_fcf_record_switch_name_7_WORD word138 2333 }; 2334 2335 struct lpfc_mbx_read_fcf_tbl { 2336 union lpfc_sli4_cfg_shdr cfg_shdr; 2337 union { 2338 struct { 2339 uint32_t word10; 2340 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2341 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2342 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2343 } request; 2344 struct { 2345 uint32_t eventag; 2346 } response; 2347 } u; 2348 uint32_t word11; 2349 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2350 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2351 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2352 }; 2353 2354 struct lpfc_mbx_add_fcf_tbl_entry { 2355 union lpfc_sli4_cfg_shdr cfg_shdr; 2356 uint32_t word10; 2357 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2358 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2359 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2360 struct lpfc_mbx_sge fcf_sge; 2361 }; 2362 2363 struct lpfc_mbx_del_fcf_tbl_entry { 2364 struct mbox_header header; 2365 uint32_t word10; 2366 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2367 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2368 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2369 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2370 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2371 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2372 }; 2373 2374 struct lpfc_mbx_redisc_fcf_tbl { 2375 struct mbox_header header; 2376 uint32_t word10; 2377 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2378 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2379 #define lpfc_mbx_redisc_fcf_count_WORD word10 2380 uint32_t resvd; 2381 uint32_t word12; 2382 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2383 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2384 #define lpfc_mbx_redisc_fcf_index_WORD word12 2385 }; 2386 2387 /* Status field for embedded SLI_CONFIG mailbox command */ 2388 #define STATUS_SUCCESS 0x0 2389 #define STATUS_FAILED 0x1 2390 #define STATUS_ILLEGAL_REQUEST 0x2 2391 #define STATUS_ILLEGAL_FIELD 0x3 2392 #define STATUS_INSUFFICIENT_BUFFER 0x4 2393 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2394 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2395 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2396 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2397 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2398 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2399 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2400 #define STATUS_ASSERT_FAILED 0x1e 2401 #define STATUS_INVALID_SESSION 0x1f 2402 #define STATUS_INVALID_CONNECTION 0x20 2403 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2404 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2405 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2406 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2407 #define STATUS_FLASHROM_READ_FAILED 0x27 2408 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2409 #define STATUS_ERROR_ACITMAIN 0x2a 2410 #define STATUS_REBOOT_REQUIRED 0x2c 2411 #define STATUS_FCF_IN_USE 0x3a 2412 #define STATUS_FCF_TABLE_EMPTY 0x43 2413 2414 /* 2415 * Additional status field for embedded SLI_CONFIG mailbox 2416 * command. 2417 */ 2418 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2419 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2420 #define ADD_STATUS_INVALID_REQUEST 0x4B 2421 #define ADD_STATUS_INVALID_OBJECT_NAME 0xA0 2422 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2423 2424 struct lpfc_mbx_sli4_config { 2425 struct mbox_header header; 2426 }; 2427 2428 struct lpfc_mbx_init_vfi { 2429 uint32_t word1; 2430 #define lpfc_init_vfi_vr_SHIFT 31 2431 #define lpfc_init_vfi_vr_MASK 0x00000001 2432 #define lpfc_init_vfi_vr_WORD word1 2433 #define lpfc_init_vfi_vt_SHIFT 30 2434 #define lpfc_init_vfi_vt_MASK 0x00000001 2435 #define lpfc_init_vfi_vt_WORD word1 2436 #define lpfc_init_vfi_vf_SHIFT 29 2437 #define lpfc_init_vfi_vf_MASK 0x00000001 2438 #define lpfc_init_vfi_vf_WORD word1 2439 #define lpfc_init_vfi_vp_SHIFT 28 2440 #define lpfc_init_vfi_vp_MASK 0x00000001 2441 #define lpfc_init_vfi_vp_WORD word1 2442 #define lpfc_init_vfi_vfi_SHIFT 0 2443 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2444 #define lpfc_init_vfi_vfi_WORD word1 2445 uint32_t word2; 2446 #define lpfc_init_vfi_vpi_SHIFT 16 2447 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2448 #define lpfc_init_vfi_vpi_WORD word2 2449 #define lpfc_init_vfi_fcfi_SHIFT 0 2450 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2451 #define lpfc_init_vfi_fcfi_WORD word2 2452 uint32_t word3; 2453 #define lpfc_init_vfi_pri_SHIFT 13 2454 #define lpfc_init_vfi_pri_MASK 0x00000007 2455 #define lpfc_init_vfi_pri_WORD word3 2456 #define lpfc_init_vfi_vf_id_SHIFT 1 2457 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2458 #define lpfc_init_vfi_vf_id_WORD word3 2459 uint32_t word4; 2460 #define lpfc_init_vfi_hop_count_SHIFT 24 2461 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2462 #define lpfc_init_vfi_hop_count_WORD word4 2463 }; 2464 #define MBX_VFI_IN_USE 0x9F02 2465 2466 2467 struct lpfc_mbx_reg_vfi { 2468 uint32_t word1; 2469 #define lpfc_reg_vfi_upd_SHIFT 29 2470 #define lpfc_reg_vfi_upd_MASK 0x00000001 2471 #define lpfc_reg_vfi_upd_WORD word1 2472 #define lpfc_reg_vfi_vp_SHIFT 28 2473 #define lpfc_reg_vfi_vp_MASK 0x00000001 2474 #define lpfc_reg_vfi_vp_WORD word1 2475 #define lpfc_reg_vfi_vfi_SHIFT 0 2476 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2477 #define lpfc_reg_vfi_vfi_WORD word1 2478 uint32_t word2; 2479 #define lpfc_reg_vfi_vpi_SHIFT 16 2480 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2481 #define lpfc_reg_vfi_vpi_WORD word2 2482 #define lpfc_reg_vfi_fcfi_SHIFT 0 2483 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2484 #define lpfc_reg_vfi_fcfi_WORD word2 2485 uint32_t wwn[2]; 2486 struct ulp_bde64 bde; 2487 uint32_t e_d_tov; 2488 uint32_t r_a_tov; 2489 uint32_t word10; 2490 #define lpfc_reg_vfi_nport_id_SHIFT 0 2491 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2492 #define lpfc_reg_vfi_nport_id_WORD word10 2493 #define lpfc_reg_vfi_bbcr_SHIFT 27 2494 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2495 #define lpfc_reg_vfi_bbcr_WORD word10 2496 #define lpfc_reg_vfi_bbscn_SHIFT 28 2497 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2498 #define lpfc_reg_vfi_bbscn_WORD word10 2499 }; 2500 2501 struct lpfc_mbx_init_vpi { 2502 uint32_t word1; 2503 #define lpfc_init_vpi_vfi_SHIFT 16 2504 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2505 #define lpfc_init_vpi_vfi_WORD word1 2506 #define lpfc_init_vpi_vpi_SHIFT 0 2507 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2508 #define lpfc_init_vpi_vpi_WORD word1 2509 }; 2510 2511 struct lpfc_mbx_read_vpi { 2512 uint32_t word1_rsvd; 2513 uint32_t word2; 2514 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2515 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2516 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2517 uint32_t word3_rsvd; 2518 uint32_t word4; 2519 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2520 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2521 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2522 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2523 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2524 #define lpfc_mbx_read_vpi_pb_WORD word4 2525 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2526 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2527 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2528 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2529 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2530 #define lpfc_mbx_read_vpi_ns_WORD word4 2531 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2532 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2533 #define lpfc_mbx_read_vpi_hl_WORD word4 2534 uint32_t word5_rsvd; 2535 uint32_t word6; 2536 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2537 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2538 #define lpfc_mbx_read_vpi_vpi_WORD word6 2539 uint32_t word7; 2540 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2541 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2542 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2543 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2544 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2545 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2546 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2547 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2548 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2549 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2550 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2551 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2552 uint32_t word8; 2553 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2554 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2555 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2556 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2557 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2558 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2559 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2560 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2561 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2562 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2563 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2564 #define lpfc_mbx_read_vpi_vv_WORD word8 2565 }; 2566 2567 struct lpfc_mbx_unreg_vfi { 2568 uint32_t word1_rsvd; 2569 uint32_t word2; 2570 #define lpfc_unreg_vfi_vfi_SHIFT 0 2571 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2572 #define lpfc_unreg_vfi_vfi_WORD word2 2573 }; 2574 2575 struct lpfc_mbx_resume_rpi { 2576 uint32_t word1; 2577 #define lpfc_resume_rpi_index_SHIFT 0 2578 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2579 #define lpfc_resume_rpi_index_WORD word1 2580 #define lpfc_resume_rpi_ii_SHIFT 30 2581 #define lpfc_resume_rpi_ii_MASK 0x00000003 2582 #define lpfc_resume_rpi_ii_WORD word1 2583 #define RESUME_INDEX_RPI 0 2584 #define RESUME_INDEX_VPI 1 2585 #define RESUME_INDEX_VFI 2 2586 #define RESUME_INDEX_FCFI 3 2587 uint32_t event_tag; 2588 }; 2589 2590 #define REG_FCF_INVALID_QID 0xFFFF 2591 struct lpfc_mbx_reg_fcfi { 2592 uint32_t word1; 2593 #define lpfc_reg_fcfi_info_index_SHIFT 0 2594 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2595 #define lpfc_reg_fcfi_info_index_WORD word1 2596 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2597 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2598 #define lpfc_reg_fcfi_fcfi_WORD word1 2599 uint32_t word2; 2600 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2601 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2602 #define lpfc_reg_fcfi_rq_id1_WORD word2 2603 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2604 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2605 #define lpfc_reg_fcfi_rq_id0_WORD word2 2606 uint32_t word3; 2607 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2608 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2609 #define lpfc_reg_fcfi_rq_id3_WORD word3 2610 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2611 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2612 #define lpfc_reg_fcfi_rq_id2_WORD word3 2613 uint32_t word4; 2614 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2615 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2616 #define lpfc_reg_fcfi_type_match0_WORD word4 2617 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2618 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2619 #define lpfc_reg_fcfi_type_mask0_WORD word4 2620 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2621 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2622 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2623 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2624 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2625 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2626 uint32_t word5; 2627 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2628 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2629 #define lpfc_reg_fcfi_type_match1_WORD word5 2630 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2631 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2632 #define lpfc_reg_fcfi_type_mask1_WORD word5 2633 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2634 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2635 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2636 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2637 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2638 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2639 uint32_t word6; 2640 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2641 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2642 #define lpfc_reg_fcfi_type_match2_WORD word6 2643 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2644 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2645 #define lpfc_reg_fcfi_type_mask2_WORD word6 2646 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2647 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2648 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2649 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2650 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2651 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2652 uint32_t word7; 2653 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2654 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2655 #define lpfc_reg_fcfi_type_match3_WORD word7 2656 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2657 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2658 #define lpfc_reg_fcfi_type_mask3_WORD word7 2659 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2660 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2661 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2662 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2663 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2664 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2665 uint32_t word8; 2666 #define lpfc_reg_fcfi_mam_SHIFT 13 2667 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2668 #define lpfc_reg_fcfi_mam_WORD word8 2669 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2670 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2671 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2672 #define lpfc_reg_fcfi_vv_SHIFT 12 2673 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2674 #define lpfc_reg_fcfi_vv_WORD word8 2675 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2676 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2677 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2678 }; 2679 2680 struct lpfc_mbx_reg_fcfi_mrq { 2681 uint32_t word1; 2682 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2683 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2684 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2685 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2686 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2687 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2688 uint32_t word2; 2689 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2690 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2691 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2692 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2693 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2694 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2695 uint32_t word3; 2696 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2697 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2698 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2699 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2700 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2701 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2702 uint32_t word4; 2703 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2704 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2705 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2706 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2707 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2708 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2709 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2710 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2711 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2712 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2713 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2714 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2715 uint32_t word5; 2716 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2717 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2718 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2719 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2720 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2721 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2722 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2723 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2724 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2725 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2726 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2727 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2728 uint32_t word6; 2729 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2730 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2731 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2732 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2733 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2734 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2735 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2736 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2737 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2738 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2739 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2740 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2741 uint32_t word7; 2742 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2743 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2744 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2745 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2746 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2747 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2748 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2749 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2750 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2751 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2752 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2753 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2754 uint32_t word8; 2755 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2756 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2757 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2758 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2759 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2760 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2761 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2762 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2763 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2764 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2765 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2766 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2767 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2768 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2769 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2770 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2771 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2772 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2773 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2774 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2775 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2776 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2777 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2778 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2779 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2780 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2781 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2782 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2783 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2784 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2785 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2786 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2787 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2788 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2789 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2790 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2791 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2792 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2793 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2794 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2795 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2796 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2797 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2798 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2799 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2800 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2801 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2802 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2803 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2804 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2805 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2806 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2807 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2808 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2809 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2810 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2811 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2812 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2813 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2814 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2815 uint32_t word9; 2816 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2817 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2818 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2819 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2820 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2821 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2822 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2823 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2824 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2825 uint32_t word10; 2826 uint32_t word11; 2827 uint32_t word12; 2828 uint32_t word13; 2829 uint32_t word14; 2830 uint32_t word15; 2831 uint32_t word16; 2832 }; 2833 2834 struct lpfc_mbx_unreg_fcfi { 2835 uint32_t word1_rsv; 2836 uint32_t word2; 2837 #define lpfc_unreg_fcfi_SHIFT 0 2838 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2839 #define lpfc_unreg_fcfi_WORD word2 2840 }; 2841 2842 struct lpfc_mbx_read_rev { 2843 uint32_t word1; 2844 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2845 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2846 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2847 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2848 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2849 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2850 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2851 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2852 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2853 #define LPFC_PREDCBX_CEE_MODE 0 2854 #define LPFC_DCBX_CEE_MODE 1 2855 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2856 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2857 #define lpfc_mbx_rd_rev_vpd_WORD word1 2858 uint32_t first_hw_rev; 2859 #define LPFC_G7_ASIC_1 0xd 2860 uint32_t second_hw_rev; 2861 uint32_t word4_rsvd; 2862 uint32_t third_hw_rev; 2863 uint32_t word6; 2864 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2865 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2866 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2867 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2868 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2869 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2870 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2871 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2872 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2873 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2874 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2875 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2876 uint32_t word7_rsvd; 2877 uint32_t fw_id_rev; 2878 uint8_t fw_name[16]; 2879 uint32_t ulp_fw_id_rev; 2880 uint8_t ulp_fw_name[16]; 2881 uint32_t word18_47_rsvd[30]; 2882 uint32_t word48; 2883 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2884 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2885 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2886 uint32_t vpd_paddr_low; 2887 uint32_t vpd_paddr_high; 2888 uint32_t avail_vpd_len; 2889 uint32_t rsvd_52_63[12]; 2890 }; 2891 2892 struct lpfc_mbx_read_config { 2893 uint32_t word1; 2894 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2895 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2896 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2897 #define lpfc_mbx_rd_conf_fawwpn_SHIFT 30 2898 #define lpfc_mbx_rd_conf_fawwpn_MASK 0x00000001 2899 #define lpfc_mbx_rd_conf_fawwpn_WORD word1 2900 #define lpfc_mbx_rd_conf_wcs_SHIFT 28 /* warning signaling */ 2901 #define lpfc_mbx_rd_conf_wcs_MASK 0x00000001 2902 #define lpfc_mbx_rd_conf_wcs_WORD word1 2903 #define lpfc_mbx_rd_conf_acs_SHIFT 27 /* alarm signaling */ 2904 #define lpfc_mbx_rd_conf_acs_MASK 0x00000001 2905 #define lpfc_mbx_rd_conf_acs_WORD word1 2906 uint32_t word2; 2907 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2908 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2909 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2910 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2911 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2912 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2913 #define LPFC_LNK_TYPE_GE 0 2914 #define LPFC_LNK_TYPE_FC 1 2915 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2916 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2917 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2918 #define lpfc_mbx_rd_conf_trunk_SHIFT 12 2919 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2920 #define lpfc_mbx_rd_conf_trunk_WORD word2 2921 #define lpfc_mbx_rd_conf_pt_SHIFT 20 2922 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2923 #define lpfc_mbx_rd_conf_pt_WORD word2 2924 #define lpfc_mbx_rd_conf_tf_SHIFT 22 2925 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2926 #define lpfc_mbx_rd_conf_tf_WORD word2 2927 #define lpfc_mbx_rd_conf_ptv_SHIFT 23 2928 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2929 #define lpfc_mbx_rd_conf_ptv_WORD word2 2930 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2931 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2932 #define lpfc_mbx_rd_conf_topology_WORD word2 2933 uint32_t rsvd_3; 2934 uint32_t word4; 2935 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2936 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2937 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2938 uint32_t rsvd_5; 2939 uint32_t word6; 2940 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2941 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2942 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2943 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2944 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2945 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2946 uint32_t rsvd_7; 2947 uint32_t word8; 2948 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2949 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2950 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2951 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2952 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2953 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2954 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2955 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2956 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2957 uint32_t word9; 2958 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2959 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2960 #define lpfc_mbx_rd_conf_lmt_WORD word9 2961 uint32_t rsvd_10; 2962 uint32_t rsvd_11; 2963 uint32_t word12; 2964 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2965 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2966 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2967 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2968 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2969 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2970 uint32_t word13; 2971 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2972 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2973 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2974 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2975 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2976 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2977 uint32_t word14; 2978 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2979 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2980 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2981 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2982 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2983 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2984 uint32_t word15; 2985 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2986 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2987 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2988 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2989 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2990 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2991 uint32_t word16; 2992 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2993 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2994 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2995 uint32_t word17; 2996 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2997 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2998 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2999 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 3000 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 3001 #define lpfc_mbx_rd_conf_eq_count_WORD word17 3002 uint32_t word18; 3003 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 3004 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 3005 #define lpfc_mbx_rd_conf_wq_count_WORD word18 3006 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 3007 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 3008 #define lpfc_mbx_rd_conf_cq_count_WORD word18 3009 }; 3010 3011 struct lpfc_mbx_request_features { 3012 uint32_t word1; 3013 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 3014 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 3015 #define lpfc_mbx_rq_ftr_qry_WORD word1 3016 uint32_t word2; 3017 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 3018 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 3019 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 3020 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 3021 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 3022 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 3023 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 3024 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 3025 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 3026 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 3027 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 3028 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 3029 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 3030 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 3031 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 3032 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 3033 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 3034 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 3035 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 3036 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 3037 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 3038 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 3039 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 3040 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 3041 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 3042 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 3043 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 3044 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 3045 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 3046 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 3047 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 3048 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 3049 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 3050 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 3051 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 3052 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 3053 uint32_t word3; 3054 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 3055 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 3056 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 3057 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 3058 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 3059 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 3060 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 3061 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 3062 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 3063 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 3064 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 3065 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 3066 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 3067 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 3068 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 3069 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 3070 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 3071 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 3072 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 3073 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 3074 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 3075 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 3076 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 3077 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 3078 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 3079 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 3080 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 3081 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 3082 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 3083 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 3084 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 3085 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 3086 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 3087 }; 3088 3089 struct lpfc_mbx_memory_dump_type3 { 3090 uint32_t word1; 3091 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3092 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3093 #define lpfc_mbx_memory_dump_type3_type_WORD word1 3094 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3095 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3096 #define lpfc_mbx_memory_dump_type3_link_WORD word1 3097 uint32_t word2; 3098 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3099 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3100 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3101 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3102 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3103 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3104 uint32_t word3; 3105 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3106 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3107 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3108 uint32_t addr_lo; 3109 uint32_t addr_hi; 3110 uint32_t return_len; 3111 }; 3112 3113 #define DMP_PAGE_A0 0xa0 3114 #define DMP_PAGE_A2 0xa2 3115 #define DMP_SFF_PAGE_A0_SIZE 256 3116 #define DMP_SFF_PAGE_A2_SIZE 256 3117 3118 #define SFP_WAVELENGTH_LC1310 1310 3119 #define SFP_WAVELENGTH_LL1550 1550 3120 3121 3122 /* 3123 * * SFF-8472 TABLE 3.4 3124 * */ 3125 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3126 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3127 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3128 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3129 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3130 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3131 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3132 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3133 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3134 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3135 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3136 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3137 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3138 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3139 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3140 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3141 3142 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3143 3144 #define SSF_IDENTIFIER 0 3145 #define SSF_EXT_IDENTIFIER 1 3146 #define SSF_CONNECTOR 2 3147 #define SSF_TRANSCEIVER_CODE_B0 3 3148 #define SSF_TRANSCEIVER_CODE_B1 4 3149 #define SSF_TRANSCEIVER_CODE_B2 5 3150 #define SSF_TRANSCEIVER_CODE_B3 6 3151 #define SSF_TRANSCEIVER_CODE_B4 7 3152 #define SSF_TRANSCEIVER_CODE_B5 8 3153 #define SSF_TRANSCEIVER_CODE_B6 9 3154 #define SSF_TRANSCEIVER_CODE_B7 10 3155 #define SSF_ENCODING 11 3156 #define SSF_BR_NOMINAL 12 3157 #define SSF_RATE_IDENTIFIER 13 3158 #define SSF_LENGTH_9UM_KM 14 3159 #define SSF_LENGTH_9UM 15 3160 #define SSF_LENGTH_50UM_OM2 16 3161 #define SSF_LENGTH_62UM_OM1 17 3162 #define SFF_LENGTH_COPPER 18 3163 #define SSF_LENGTH_50UM_OM3 19 3164 #define SSF_VENDOR_NAME 20 3165 #define SSF_TRANSCEIVER2 36 3166 #define SSF_VENDOR_OUI 37 3167 #define SSF_VENDOR_PN 40 3168 #define SSF_VENDOR_REV 56 3169 #define SSF_WAVELENGTH_B1 60 3170 #define SSF_WAVELENGTH_B0 61 3171 #define SSF_CC_BASE 63 3172 #define SSF_OPTIONS_B1 64 3173 #define SSF_OPTIONS_B0 65 3174 #define SSF_BR_MAX 66 3175 #define SSF_BR_MIN 67 3176 #define SSF_VENDOR_SN 68 3177 #define SSF_DATE_CODE 84 3178 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3179 #define SSF_ENHANCED_OPTIONS 93 3180 #define SFF_8472_COMPLIANCE 94 3181 #define SSF_CC_EXT 95 3182 #define SSF_A0_VENDOR_SPECIFIC 96 3183 3184 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3185 3186 #define SSF_TEMP_HIGH_ALARM 0 3187 #define SSF_TEMP_LOW_ALARM 2 3188 #define SSF_TEMP_HIGH_WARNING 4 3189 #define SSF_TEMP_LOW_WARNING 6 3190 #define SSF_VOLTAGE_HIGH_ALARM 8 3191 #define SSF_VOLTAGE_LOW_ALARM 10 3192 #define SSF_VOLTAGE_HIGH_WARNING 12 3193 #define SSF_VOLTAGE_LOW_WARNING 14 3194 #define SSF_BIAS_HIGH_ALARM 16 3195 #define SSF_BIAS_LOW_ALARM 18 3196 #define SSF_BIAS_HIGH_WARNING 20 3197 #define SSF_BIAS_LOW_WARNING 22 3198 #define SSF_TXPOWER_HIGH_ALARM 24 3199 #define SSF_TXPOWER_LOW_ALARM 26 3200 #define SSF_TXPOWER_HIGH_WARNING 28 3201 #define SSF_TXPOWER_LOW_WARNING 30 3202 #define SSF_RXPOWER_HIGH_ALARM 32 3203 #define SSF_RXPOWER_LOW_ALARM 34 3204 #define SSF_RXPOWER_HIGH_WARNING 36 3205 #define SSF_RXPOWER_LOW_WARNING 38 3206 #define SSF_EXT_CAL_CONSTANTS 56 3207 #define SSF_CC_DMI 95 3208 #define SFF_TEMPERATURE_B1 96 3209 #define SFF_TEMPERATURE_B0 97 3210 #define SFF_VCC_B1 98 3211 #define SFF_VCC_B0 99 3212 #define SFF_TX_BIAS_CURRENT_B1 100 3213 #define SFF_TX_BIAS_CURRENT_B0 101 3214 #define SFF_TXPOWER_B1 102 3215 #define SFF_TXPOWER_B0 103 3216 #define SFF_RXPOWER_B1 104 3217 #define SFF_RXPOWER_B0 105 3218 #define SSF_STATUS_CONTROL 110 3219 #define SSF_ALARM_FLAGS 112 3220 #define SSF_WARNING_FLAGS 116 3221 #define SSF_EXT_TATUS_CONTROL_B1 118 3222 #define SSF_EXT_TATUS_CONTROL_B0 119 3223 #define SSF_A2_VENDOR_SPECIFIC 120 3224 #define SSF_USER_EEPROM 128 3225 #define SSF_VENDOR_CONTROL 148 3226 3227 3228 /* 3229 * Tranceiver codes Fibre Channel SFF-8472 3230 * Table 3.5. 3231 */ 3232 3233 struct sff_trasnceiver_codes_byte0 { 3234 uint8_t inifiband:4; 3235 uint8_t teng_ethernet:4; 3236 }; 3237 3238 struct sff_trasnceiver_codes_byte1 { 3239 uint8_t sonet:6; 3240 uint8_t escon:2; 3241 }; 3242 3243 struct sff_trasnceiver_codes_byte2 { 3244 uint8_t soNet:8; 3245 }; 3246 3247 struct sff_trasnceiver_codes_byte3 { 3248 uint8_t ethernet:8; 3249 }; 3250 3251 struct sff_trasnceiver_codes_byte4 { 3252 uint8_t fc_el_lo:1; 3253 uint8_t fc_lw_laser:1; 3254 uint8_t fc_sw_laser:1; 3255 uint8_t fc_md_distance:1; 3256 uint8_t fc_lg_distance:1; 3257 uint8_t fc_int_distance:1; 3258 uint8_t fc_short_distance:1; 3259 uint8_t fc_vld_distance:1; 3260 }; 3261 3262 struct sff_trasnceiver_codes_byte5 { 3263 uint8_t reserved1:1; 3264 uint8_t reserved2:1; 3265 uint8_t fc_sfp_active:1; /* Active cable */ 3266 uint8_t fc_sfp_passive:1; /* Passive cable */ 3267 uint8_t fc_lw_laser:1; /* Longwave laser */ 3268 uint8_t fc_sw_laser_sl:1; 3269 uint8_t fc_sw_laser_sn:1; 3270 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3271 }; 3272 3273 struct sff_trasnceiver_codes_byte6 { 3274 uint8_t fc_tm_sm:1; /* Single Mode */ 3275 uint8_t reserved:1; 3276 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3277 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3278 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3279 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3280 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3281 }; 3282 3283 struct sff_trasnceiver_codes_byte7 { 3284 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3285 uint8_t speed_chk_ecc:1; 3286 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3287 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3288 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3289 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3290 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3291 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3292 }; 3293 3294 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3295 struct user_eeprom { 3296 uint8_t vendor_name[16]; 3297 uint8_t vendor_oui[3]; 3298 uint8_t vendor_pn[816]; 3299 uint8_t vendor_rev[4]; 3300 uint8_t vendor_sn[16]; 3301 uint8_t datecode[6]; 3302 uint8_t lot_code[2]; 3303 uint8_t reserved191[57]; 3304 }; 3305 3306 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3307 &(~((SLI4_PAGE_SIZE)-1))) 3308 3309 struct lpfc_sli4_parameters { 3310 uint32_t word0; 3311 #define cfg_prot_type_SHIFT 0 3312 #define cfg_prot_type_MASK 0x000000FF 3313 #define cfg_prot_type_WORD word0 3314 uint32_t word1; 3315 #define cfg_ft_SHIFT 0 3316 #define cfg_ft_MASK 0x00000001 3317 #define cfg_ft_WORD word1 3318 #define cfg_sli_rev_SHIFT 4 3319 #define cfg_sli_rev_MASK 0x0000000f 3320 #define cfg_sli_rev_WORD word1 3321 #define cfg_sli_family_SHIFT 8 3322 #define cfg_sli_family_MASK 0x0000000f 3323 #define cfg_sli_family_WORD word1 3324 #define cfg_if_type_SHIFT 12 3325 #define cfg_if_type_MASK 0x0000000f 3326 #define cfg_if_type_WORD word1 3327 #define cfg_sli_hint_1_SHIFT 16 3328 #define cfg_sli_hint_1_MASK 0x000000ff 3329 #define cfg_sli_hint_1_WORD word1 3330 #define cfg_sli_hint_2_SHIFT 24 3331 #define cfg_sli_hint_2_MASK 0x0000001f 3332 #define cfg_sli_hint_2_WORD word1 3333 uint32_t word2; 3334 #define cfg_eqav_SHIFT 31 3335 #define cfg_eqav_MASK 0x00000001 3336 #define cfg_eqav_WORD word2 3337 uint32_t word3; 3338 uint32_t word4; 3339 #define cfg_cqv_SHIFT 14 3340 #define cfg_cqv_MASK 0x00000003 3341 #define cfg_cqv_WORD word4 3342 #define cfg_cqpsize_SHIFT 16 3343 #define cfg_cqpsize_MASK 0x000000ff 3344 #define cfg_cqpsize_WORD word4 3345 #define cfg_cqav_SHIFT 31 3346 #define cfg_cqav_MASK 0x00000001 3347 #define cfg_cqav_WORD word4 3348 uint32_t word5; 3349 uint32_t word6; 3350 #define cfg_mqv_SHIFT 14 3351 #define cfg_mqv_MASK 0x00000003 3352 #define cfg_mqv_WORD word6 3353 uint32_t word7; 3354 uint32_t word8; 3355 #define cfg_wqpcnt_SHIFT 0 3356 #define cfg_wqpcnt_MASK 0x0000000f 3357 #define cfg_wqpcnt_WORD word8 3358 #define cfg_wqsize_SHIFT 8 3359 #define cfg_wqsize_MASK 0x0000000f 3360 #define cfg_wqsize_WORD word8 3361 #define cfg_wqv_SHIFT 14 3362 #define cfg_wqv_MASK 0x00000003 3363 #define cfg_wqv_WORD word8 3364 #define cfg_wqpsize_SHIFT 16 3365 #define cfg_wqpsize_MASK 0x000000ff 3366 #define cfg_wqpsize_WORD word8 3367 uint32_t word9; 3368 uint32_t word10; 3369 #define cfg_rqv_SHIFT 14 3370 #define cfg_rqv_MASK 0x00000003 3371 #define cfg_rqv_WORD word10 3372 uint32_t word11; 3373 #define cfg_rq_db_window_SHIFT 28 3374 #define cfg_rq_db_window_MASK 0x0000000f 3375 #define cfg_rq_db_window_WORD word11 3376 uint32_t word12; 3377 #define cfg_fcoe_SHIFT 0 3378 #define cfg_fcoe_MASK 0x00000001 3379 #define cfg_fcoe_WORD word12 3380 #define cfg_ext_SHIFT 1 3381 #define cfg_ext_MASK 0x00000001 3382 #define cfg_ext_WORD word12 3383 #define cfg_hdrr_SHIFT 2 3384 #define cfg_hdrr_MASK 0x00000001 3385 #define cfg_hdrr_WORD word12 3386 #define cfg_phwq_SHIFT 15 3387 #define cfg_phwq_MASK 0x00000001 3388 #define cfg_phwq_WORD word12 3389 #define cfg_oas_SHIFT 25 3390 #define cfg_oas_MASK 0x00000001 3391 #define cfg_oas_WORD word12 3392 #define cfg_loopbk_scope_SHIFT 28 3393 #define cfg_loopbk_scope_MASK 0x0000000f 3394 #define cfg_loopbk_scope_WORD word12 3395 uint32_t sge_supp_len; 3396 uint32_t word14; 3397 #define cfg_sgl_page_cnt_SHIFT 0 3398 #define cfg_sgl_page_cnt_MASK 0x0000000f 3399 #define cfg_sgl_page_cnt_WORD word14 3400 #define cfg_sgl_page_size_SHIFT 8 3401 #define cfg_sgl_page_size_MASK 0x000000ff 3402 #define cfg_sgl_page_size_WORD word14 3403 #define cfg_sgl_pp_align_SHIFT 16 3404 #define cfg_sgl_pp_align_MASK 0x000000ff 3405 #define cfg_sgl_pp_align_WORD word14 3406 uint32_t word15; 3407 uint32_t word16; 3408 uint32_t word17; 3409 uint32_t word18; 3410 uint32_t word19; 3411 #define cfg_ext_embed_cb_SHIFT 0 3412 #define cfg_ext_embed_cb_MASK 0x00000001 3413 #define cfg_ext_embed_cb_WORD word19 3414 #define cfg_mds_diags_SHIFT 1 3415 #define cfg_mds_diags_MASK 0x00000001 3416 #define cfg_mds_diags_WORD word19 3417 #define cfg_nvme_SHIFT 3 3418 #define cfg_nvme_MASK 0x00000001 3419 #define cfg_nvme_WORD word19 3420 #define cfg_xib_SHIFT 4 3421 #define cfg_xib_MASK 0x00000001 3422 #define cfg_xib_WORD word19 3423 #define cfg_xpsgl_SHIFT 6 3424 #define cfg_xpsgl_MASK 0x00000001 3425 #define cfg_xpsgl_WORD word19 3426 #define cfg_eqdr_SHIFT 8 3427 #define cfg_eqdr_MASK 0x00000001 3428 #define cfg_eqdr_WORD word19 3429 #define cfg_nosr_SHIFT 9 3430 #define cfg_nosr_MASK 0x00000001 3431 #define cfg_nosr_WORD word19 3432 #define cfg_bv1s_SHIFT 10 3433 #define cfg_bv1s_MASK 0x00000001 3434 #define cfg_bv1s_WORD word19 3435 3436 #define cfg_nsler_SHIFT 12 3437 #define cfg_nsler_MASK 0x00000001 3438 #define cfg_nsler_WORD word19 3439 #define cfg_pvl_SHIFT 13 3440 #define cfg_pvl_MASK 0x00000001 3441 #define cfg_pvl_WORD word19 3442 3443 #define cfg_pbde_SHIFT 20 3444 #define cfg_pbde_MASK 0x00000001 3445 #define cfg_pbde_WORD word19 3446 3447 uint32_t word20; 3448 #define cfg_max_tow_xri_SHIFT 0 3449 #define cfg_max_tow_xri_MASK 0x0000ffff 3450 #define cfg_max_tow_xri_WORD word20 3451 3452 uint32_t word21; 3453 #define cfg_mi_ver_SHIFT 0 3454 #define cfg_mi_ver_MASK 0x0000ffff 3455 #define cfg_mi_ver_WORD word21 3456 #define cfg_cmf_SHIFT 24 3457 #define cfg_cmf_MASK 0x000000ff 3458 #define cfg_cmf_WORD word21 3459 3460 uint32_t mib_size; 3461 uint32_t word23; /* RESERVED */ 3462 3463 uint32_t word24; 3464 #define cfg_frag_field_offset_SHIFT 0 3465 #define cfg_frag_field_offset_MASK 0x0000ffff 3466 #define cfg_frag_field_offset_WORD word24 3467 3468 #define cfg_frag_field_size_SHIFT 16 3469 #define cfg_frag_field_size_MASK 0x0000ffff 3470 #define cfg_frag_field_size_WORD word24 3471 3472 uint32_t word25; 3473 #define cfg_sgl_field_offset_SHIFT 0 3474 #define cfg_sgl_field_offset_MASK 0x0000ffff 3475 #define cfg_sgl_field_offset_WORD word25 3476 3477 #define cfg_sgl_field_size_SHIFT 16 3478 #define cfg_sgl_field_size_MASK 0x0000ffff 3479 #define cfg_sgl_field_size_WORD word25 3480 3481 uint32_t word26; /* Chain SGE initial value LOW */ 3482 uint32_t word27; /* Chain SGE initial value HIGH */ 3483 #define LPFC_NODELAY_MAX_IO 32 3484 }; 3485 3486 #define LPFC_SET_UE_RECOVERY 0x10 3487 #define LPFC_SET_MDS_DIAGS 0x12 3488 #define LPFC_SET_DUAL_DUMP 0x1e 3489 #define LPFC_SET_CGN_SIGNAL 0x1f 3490 #define LPFC_SET_ENABLE_MI 0x21 3491 #define LPFC_SET_LD_SIGNAL 0x23 3492 #define LPFC_SET_ENABLE_CMF 0x24 3493 struct lpfc_mbx_set_feature { 3494 struct mbox_header header; 3495 uint32_t feature; 3496 uint32_t param_len; 3497 uint32_t word6; 3498 #define lpfc_mbx_set_feature_UER_SHIFT 0 3499 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3500 #define lpfc_mbx_set_feature_UER_WORD word6 3501 #define lpfc_mbx_set_feature_mds_SHIFT 2 3502 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3503 #define lpfc_mbx_set_feature_mds_WORD word6 3504 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3505 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3506 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3507 #define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0 3508 #define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff 3509 #define lpfc_mbx_set_feature_CGN_warn_freq_WORD word6 3510 #define lpfc_mbx_set_feature_dd_SHIFT 0 3511 #define lpfc_mbx_set_feature_dd_MASK 0x00000001 3512 #define lpfc_mbx_set_feature_dd_WORD word6 3513 #define lpfc_mbx_set_feature_ddquery_SHIFT 1 3514 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3515 #define lpfc_mbx_set_feature_ddquery_WORD word6 3516 #define LPFC_DISABLE_DUAL_DUMP 0 3517 #define LPFC_ENABLE_DUAL_DUMP 1 3518 #define LPFC_QUERY_OP_DUAL_DUMP 2 3519 #define lpfc_mbx_set_feature_cmf_SHIFT 0 3520 #define lpfc_mbx_set_feature_cmf_MASK 0x00000001 3521 #define lpfc_mbx_set_feature_cmf_WORD word6 3522 #define lpfc_mbx_set_feature_lds_qry_SHIFT 0 3523 #define lpfc_mbx_set_feature_lds_qry_MASK 0x00000001 3524 #define lpfc_mbx_set_feature_lds_qry_WORD word6 3525 #define LPFC_QUERY_LDS_OP 1 3526 #define lpfc_mbx_set_feature_mi_SHIFT 0 3527 #define lpfc_mbx_set_feature_mi_MASK 0x0000ffff 3528 #define lpfc_mbx_set_feature_mi_WORD word6 3529 #define lpfc_mbx_set_feature_milunq_SHIFT 16 3530 #define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff 3531 #define lpfc_mbx_set_feature_milunq_WORD word6 3532 u32 word7; 3533 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3534 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3535 #define lpfc_mbx_set_feature_UERP_WORD word7 3536 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3537 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3538 #define lpfc_mbx_set_feature_UESR_WORD word7 3539 #define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0 3540 #define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff 3541 #define lpfc_mbx_set_feature_CGN_alarm_freq_WORD word7 3542 u32 word8; 3543 #define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0 3544 #define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff 3545 #define lpfc_mbx_set_feature_CGN_acqe_freq_WORD word8 3546 u32 word9; 3547 u32 word10; 3548 }; 3549 3550 3551 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3552 #define LPFC_SET_HOST_DATE_TIME 0x4 3553 3554 struct lpfc_mbx_set_host_date_time { 3555 uint32_t word6; 3556 #define lpfc_mbx_set_host_month_WORD word6 3557 #define lpfc_mbx_set_host_month_SHIFT 16 3558 #define lpfc_mbx_set_host_month_MASK 0xFF 3559 #define lpfc_mbx_set_host_day_WORD word6 3560 #define lpfc_mbx_set_host_day_SHIFT 8 3561 #define lpfc_mbx_set_host_day_MASK 0xFF 3562 #define lpfc_mbx_set_host_year_WORD word6 3563 #define lpfc_mbx_set_host_year_SHIFT 0 3564 #define lpfc_mbx_set_host_year_MASK 0xFF 3565 uint32_t word7; 3566 #define lpfc_mbx_set_host_hour_WORD word7 3567 #define lpfc_mbx_set_host_hour_SHIFT 16 3568 #define lpfc_mbx_set_host_hour_MASK 0xFF 3569 #define lpfc_mbx_set_host_min_WORD word7 3570 #define lpfc_mbx_set_host_min_SHIFT 8 3571 #define lpfc_mbx_set_host_min_MASK 0xFF 3572 #define lpfc_mbx_set_host_sec_WORD word7 3573 #define lpfc_mbx_set_host_sec_SHIFT 0 3574 #define lpfc_mbx_set_host_sec_MASK 0xFF 3575 }; 3576 3577 struct lpfc_mbx_set_host_data { 3578 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3579 struct mbox_header header; 3580 uint32_t param_id; 3581 uint32_t param_len; 3582 union { 3583 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3584 struct lpfc_mbx_set_host_date_time tm; 3585 } un; 3586 }; 3587 3588 struct lpfc_mbx_set_trunk_mode { 3589 struct mbox_header header; 3590 uint32_t word0; 3591 #define lpfc_mbx_set_trunk_mode_WORD word0 3592 #define lpfc_mbx_set_trunk_mode_SHIFT 0 3593 #define lpfc_mbx_set_trunk_mode_MASK 0xFF 3594 uint32_t word1; 3595 uint32_t word2; 3596 }; 3597 3598 struct lpfc_mbx_get_sli4_parameters { 3599 struct mbox_header header; 3600 struct lpfc_sli4_parameters sli4_parameters; 3601 }; 3602 3603 struct lpfc_mbx_reg_congestion_buf { 3604 struct mbox_header header; 3605 uint32_t word0; 3606 #define lpfc_mbx_reg_cgn_buf_type_WORD word0 3607 #define lpfc_mbx_reg_cgn_buf_type_SHIFT 0 3608 #define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF 3609 #define lpfc_mbx_reg_cgn_buf_cnt_WORD word0 3610 #define lpfc_mbx_reg_cgn_buf_cnt_SHIFT 16 3611 #define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF 3612 uint32_t word1; 3613 uint32_t length; 3614 uint32_t addr_lo; 3615 uint32_t addr_hi; 3616 }; 3617 3618 struct lpfc_rscr_desc_generic { 3619 #define LPFC_RSRC_DESC_WSIZE 22 3620 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3621 }; 3622 3623 struct lpfc_rsrc_desc_pcie { 3624 uint32_t word0; 3625 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3626 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3627 #define lpfc_rsrc_desc_pcie_type_WORD word0 3628 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3629 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3630 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3631 #define lpfc_rsrc_desc_pcie_length_WORD word0 3632 uint32_t word1; 3633 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3634 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3635 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3636 uint32_t reserved; 3637 uint32_t word3; 3638 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3639 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3640 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3641 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3642 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3643 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3644 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3645 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3646 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3647 uint32_t word4; 3648 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3649 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3650 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3651 }; 3652 3653 struct lpfc_rsrc_desc_fcfcoe { 3654 uint32_t word0; 3655 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3656 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3657 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3658 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3659 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3660 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3661 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3662 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3663 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3664 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3665 uint32_t word1; 3666 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3667 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3668 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3669 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3670 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3671 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3672 uint32_t word2; 3673 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3674 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3675 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3676 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3677 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3678 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3679 uint32_t word3; 3680 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3681 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3682 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3683 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3684 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3685 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3686 uint32_t word4; 3687 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3688 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3689 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3690 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3691 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3692 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3693 uint32_t word5; 3694 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3695 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3696 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3697 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3698 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3699 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3700 uint32_t word6; 3701 uint32_t word7; 3702 uint32_t word8; 3703 uint32_t word9; 3704 uint32_t word10; 3705 uint32_t word11; 3706 uint32_t word12; 3707 uint32_t word13; 3708 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3709 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3710 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3711 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3712 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3713 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3714 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3715 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3716 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3717 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3718 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3719 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3720 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3721 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3722 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3723 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3724 uint32_t bw_min; 3725 uint32_t bw_max; 3726 uint32_t iops_min; 3727 uint32_t iops_max; 3728 uint32_t reserved[4]; 3729 }; 3730 3731 struct lpfc_func_cfg { 3732 #define LPFC_RSRC_DESC_MAX_NUM 2 3733 uint32_t rsrc_desc_count; 3734 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3735 }; 3736 3737 struct lpfc_mbx_get_func_cfg { 3738 struct mbox_header header; 3739 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3740 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3741 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3742 struct lpfc_func_cfg func_cfg; 3743 }; 3744 3745 struct lpfc_prof_cfg { 3746 #define LPFC_RSRC_DESC_MAX_NUM 2 3747 uint32_t rsrc_desc_count; 3748 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3749 }; 3750 3751 struct lpfc_mbx_get_prof_cfg { 3752 struct mbox_header header; 3753 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3754 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3755 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3756 union { 3757 struct { 3758 uint32_t word10; 3759 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3760 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3761 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3762 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3763 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3764 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3765 } request; 3766 struct { 3767 struct lpfc_prof_cfg prof_cfg; 3768 } response; 3769 } u; 3770 }; 3771 3772 struct lpfc_controller_attribute { 3773 uint32_t version_string[8]; 3774 uint32_t manufacturer_name[8]; 3775 uint32_t supported_modes; 3776 uint32_t word17; 3777 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3778 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3779 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3780 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3781 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3782 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3783 #define lpfc_cntl_attr_flash_id_SHIFT 16 3784 #define lpfc_cntl_attr_flash_id_MASK 0x000000ff 3785 #define lpfc_cntl_attr_flash_id_WORD word17 3786 uint32_t mbx_da_struct_ver; 3787 uint32_t ep_fw_da_struct_ver; 3788 uint32_t ncsi_ver_str[3]; 3789 uint32_t dflt_ext_timeout; 3790 uint32_t model_number[8]; 3791 uint32_t description[16]; 3792 uint32_t serial_number[8]; 3793 uint32_t ip_ver_str[8]; 3794 uint32_t fw_ver_str[8]; 3795 uint32_t bios_ver_str[8]; 3796 uint32_t redboot_ver_str[8]; 3797 uint32_t driver_ver_str[8]; 3798 uint32_t flash_fw_ver_str[8]; 3799 uint32_t functionality; 3800 uint32_t word105; 3801 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3802 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3803 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3804 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3805 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3806 #define lpfc_cntl_attr_asic_rev_WORD word105 3807 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3808 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3809 #define lpfc_cntl_attr_gen_guid0_WORD word105 3810 uint32_t gen_guid1_12[3]; 3811 uint32_t word109; 3812 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3813 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3814 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3815 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3816 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3817 #define lpfc_cntl_attr_gen_guid15_WORD word109 3818 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3819 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3820 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3821 uint32_t word110; 3822 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3823 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3824 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3825 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3826 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3827 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3828 uint32_t word111; 3829 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3830 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3831 #define lpfc_cntl_attr_cache_valid_WORD word111 3832 #define lpfc_cntl_attr_hba_status_SHIFT 8 3833 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3834 #define lpfc_cntl_attr_hba_status_WORD word111 3835 #define lpfc_cntl_attr_max_domain_SHIFT 16 3836 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3837 #define lpfc_cntl_attr_max_domain_WORD word111 3838 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3839 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3840 #define lpfc_cntl_attr_lnk_numb_WORD word111 3841 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3842 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3843 #define lpfc_cntl_attr_lnk_type_WORD word111 3844 uint32_t fw_post_status; 3845 uint32_t hba_mtu[8]; 3846 uint32_t word121; 3847 uint32_t reserved1[3]; 3848 uint32_t word125; 3849 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3850 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3851 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3852 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3853 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3854 #define lpfc_cntl_attr_pci_device_id_WORD word125 3855 uint32_t word126; 3856 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3857 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3858 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3859 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3860 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3861 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3862 uint32_t word127; 3863 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3864 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3865 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3866 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3867 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3868 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3869 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3870 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3871 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3872 #define lpfc_cntl_attr_inf_type_SHIFT 24 3873 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3874 #define lpfc_cntl_attr_inf_type_WORD word127 3875 uint32_t unique_id[2]; 3876 uint32_t word130; 3877 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3878 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3879 #define lpfc_cntl_attr_num_netfil_WORD word130 3880 uint32_t reserved2[4]; 3881 }; 3882 3883 struct lpfc_mbx_get_cntl_attributes { 3884 union lpfc_sli4_cfg_shdr cfg_shdr; 3885 struct lpfc_controller_attribute cntl_attr; 3886 }; 3887 3888 struct lpfc_mbx_get_port_name { 3889 struct mbox_header header; 3890 union { 3891 struct { 3892 uint32_t word4; 3893 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3894 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3895 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3896 } request; 3897 struct { 3898 uint32_t word4; 3899 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3900 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3901 #define lpfc_mbx_get_port_name_name0_WORD word4 3902 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3903 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3904 #define lpfc_mbx_get_port_name_name1_WORD word4 3905 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3906 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3907 #define lpfc_mbx_get_port_name_name2_WORD word4 3908 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3909 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3910 #define lpfc_mbx_get_port_name_name3_WORD word4 3911 #define LPFC_LINK_NUMBER_0 0 3912 #define LPFC_LINK_NUMBER_1 1 3913 #define LPFC_LINK_NUMBER_2 2 3914 #define LPFC_LINK_NUMBER_3 3 3915 } response; 3916 } u; 3917 }; 3918 3919 /* Mailbox Completion Queue Error Messages */ 3920 #define MB_CQE_STATUS_SUCCESS 0x0 3921 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3922 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3923 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3924 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3925 #define MB_CQE_STATUS_DMA_FAILED 0x5 3926 3927 3928 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3929 struct lpfc_mbx_wr_object { 3930 struct mbox_header header; 3931 union { 3932 struct { 3933 uint32_t word4; 3934 #define lpfc_wr_object_eof_SHIFT 31 3935 #define lpfc_wr_object_eof_MASK 0x00000001 3936 #define lpfc_wr_object_eof_WORD word4 3937 #define lpfc_wr_object_eas_SHIFT 29 3938 #define lpfc_wr_object_eas_MASK 0x00000001 3939 #define lpfc_wr_object_eas_WORD word4 3940 #define lpfc_wr_object_write_length_SHIFT 0 3941 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3942 #define lpfc_wr_object_write_length_WORD word4 3943 uint32_t write_offset; 3944 uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW]; 3945 uint32_t bde_count; 3946 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3947 } request; 3948 struct { 3949 uint32_t actual_write_length; 3950 uint32_t word5; 3951 #define lpfc_wr_object_change_status_SHIFT 0 3952 #define lpfc_wr_object_change_status_MASK 0x000000FF 3953 #define lpfc_wr_object_change_status_WORD word5 3954 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3955 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3956 #define LPFC_CHANGE_STATUS_FW_RESET 0x02 3957 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3958 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3959 #define lpfc_wr_object_csf_SHIFT 8 3960 #define lpfc_wr_object_csf_MASK 0x00000001 3961 #define lpfc_wr_object_csf_WORD word5 3962 } response; 3963 } u; 3964 }; 3965 3966 /* mailbox queue entry structure */ 3967 struct lpfc_mqe { 3968 uint32_t word0; 3969 #define lpfc_mqe_status_SHIFT 16 3970 #define lpfc_mqe_status_MASK 0x0000FFFF 3971 #define lpfc_mqe_status_WORD word0 3972 #define lpfc_mqe_command_SHIFT 8 3973 #define lpfc_mqe_command_MASK 0x000000FF 3974 #define lpfc_mqe_command_WORD word0 3975 union { 3976 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3977 /* sli4 mailbox commands */ 3978 struct lpfc_mbx_sli4_config sli4_config; 3979 struct lpfc_mbx_init_vfi init_vfi; 3980 struct lpfc_mbx_reg_vfi reg_vfi; 3981 struct lpfc_mbx_reg_vfi unreg_vfi; 3982 struct lpfc_mbx_init_vpi init_vpi; 3983 struct lpfc_mbx_resume_rpi resume_rpi; 3984 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3985 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3986 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3987 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3988 struct lpfc_mbx_reg_fcfi reg_fcfi; 3989 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3990 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3991 struct lpfc_mbx_mq_create mq_create; 3992 struct lpfc_mbx_mq_create_ext mq_create_ext; 3993 struct lpfc_mbx_read_object read_object; 3994 struct lpfc_mbx_eq_create eq_create; 3995 struct lpfc_mbx_modify_eq_delay eq_delay; 3996 struct lpfc_mbx_cq_create cq_create; 3997 struct lpfc_mbx_cq_create_set cq_create_set; 3998 struct lpfc_mbx_wq_create wq_create; 3999 struct lpfc_mbx_rq_create rq_create; 4000 struct lpfc_mbx_rq_create_v2 rq_create_v2; 4001 struct lpfc_mbx_mq_destroy mq_destroy; 4002 struct lpfc_mbx_eq_destroy eq_destroy; 4003 struct lpfc_mbx_cq_destroy cq_destroy; 4004 struct lpfc_mbx_wq_destroy wq_destroy; 4005 struct lpfc_mbx_rq_destroy rq_destroy; 4006 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 4007 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 4008 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 4009 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 4010 struct lpfc_mbx_nembed_cmd nembed_cmd; 4011 struct lpfc_mbx_read_rev read_rev; 4012 struct lpfc_mbx_read_vpi read_vpi; 4013 struct lpfc_mbx_read_config rd_config; 4014 struct lpfc_mbx_request_features req_ftrs; 4015 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 4016 struct lpfc_mbx_query_fw_config query_fw_cfg; 4017 struct lpfc_mbx_set_beacon_config beacon_config; 4018 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 4019 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf; 4020 struct lpfc_mbx_set_link_diag_state link_diag_state; 4021 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 4022 struct lpfc_mbx_run_link_diag_test link_diag_test; 4023 struct lpfc_mbx_get_func_cfg get_func_cfg; 4024 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 4025 struct lpfc_mbx_wr_object wr_object; 4026 struct lpfc_mbx_get_port_name get_port_name; 4027 struct lpfc_mbx_set_feature set_feature; 4028 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 4029 struct lpfc_mbx_set_host_data set_host_data; 4030 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 4031 struct lpfc_mbx_nop nop; 4032 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 4033 } un; 4034 }; 4035 4036 struct lpfc_mcqe { 4037 uint32_t word0; 4038 #define lpfc_mcqe_status_SHIFT 0 4039 #define lpfc_mcqe_status_MASK 0x0000FFFF 4040 #define lpfc_mcqe_status_WORD word0 4041 #define lpfc_mcqe_ext_status_SHIFT 16 4042 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 4043 #define lpfc_mcqe_ext_status_WORD word0 4044 uint32_t mcqe_tag0; 4045 uint32_t mcqe_tag1; 4046 uint32_t trailer; 4047 #define lpfc_trailer_valid_SHIFT 31 4048 #define lpfc_trailer_valid_MASK 0x00000001 4049 #define lpfc_trailer_valid_WORD trailer 4050 #define lpfc_trailer_async_SHIFT 30 4051 #define lpfc_trailer_async_MASK 0x00000001 4052 #define lpfc_trailer_async_WORD trailer 4053 #define lpfc_trailer_hpi_SHIFT 29 4054 #define lpfc_trailer_hpi_MASK 0x00000001 4055 #define lpfc_trailer_hpi_WORD trailer 4056 #define lpfc_trailer_completed_SHIFT 28 4057 #define lpfc_trailer_completed_MASK 0x00000001 4058 #define lpfc_trailer_completed_WORD trailer 4059 #define lpfc_trailer_consumed_SHIFT 27 4060 #define lpfc_trailer_consumed_MASK 0x00000001 4061 #define lpfc_trailer_consumed_WORD trailer 4062 #define lpfc_trailer_type_SHIFT 16 4063 #define lpfc_trailer_type_MASK 0x000000FF 4064 #define lpfc_trailer_type_WORD trailer 4065 #define lpfc_trailer_code_SHIFT 8 4066 #define lpfc_trailer_code_MASK 0x000000FF 4067 #define lpfc_trailer_code_WORD trailer 4068 #define LPFC_TRAILER_CODE_LINK 0x1 4069 #define LPFC_TRAILER_CODE_FCOE 0x2 4070 #define LPFC_TRAILER_CODE_DCBX 0x3 4071 #define LPFC_TRAILER_CODE_GRP5 0x5 4072 #define LPFC_TRAILER_CODE_FC 0x10 4073 #define LPFC_TRAILER_CODE_SLI 0x11 4074 #define LPFC_TRAILER_CODE_CMSTAT 0x13 4075 }; 4076 4077 struct lpfc_acqe_link { 4078 uint32_t word0; 4079 #define lpfc_acqe_link_speed_SHIFT 24 4080 #define lpfc_acqe_link_speed_MASK 0x000000FF 4081 #define lpfc_acqe_link_speed_WORD word0 4082 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 4083 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 4084 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 4085 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 4086 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 4087 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 4088 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 4089 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 4090 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 4091 #define lpfc_acqe_link_duplex_SHIFT 16 4092 #define lpfc_acqe_link_duplex_MASK 0x000000FF 4093 #define lpfc_acqe_link_duplex_WORD word0 4094 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 4095 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 4096 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 4097 #define lpfc_acqe_link_status_SHIFT 8 4098 #define lpfc_acqe_link_status_MASK 0x000000FF 4099 #define lpfc_acqe_link_status_WORD word0 4100 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 4101 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 4102 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 4103 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 4104 #define lpfc_acqe_link_type_SHIFT 6 4105 #define lpfc_acqe_link_type_MASK 0x00000003 4106 #define lpfc_acqe_link_type_WORD word0 4107 #define lpfc_acqe_link_number_SHIFT 0 4108 #define lpfc_acqe_link_number_MASK 0x0000003F 4109 #define lpfc_acqe_link_number_WORD word0 4110 uint32_t word1; 4111 #define lpfc_acqe_link_fault_SHIFT 0 4112 #define lpfc_acqe_link_fault_MASK 0x000000FF 4113 #define lpfc_acqe_link_fault_WORD word1 4114 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 4115 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 4116 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 4117 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4118 #define lpfc_acqe_logical_link_speed_SHIFT 16 4119 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4120 #define lpfc_acqe_logical_link_speed_WORD word1 4121 uint32_t event_tag; 4122 uint32_t trailer; 4123 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4124 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4125 }; 4126 4127 struct lpfc_acqe_fip { 4128 uint32_t index; 4129 uint32_t word1; 4130 #define lpfc_acqe_fip_fcf_count_SHIFT 0 4131 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4132 #define lpfc_acqe_fip_fcf_count_WORD word1 4133 #define lpfc_acqe_fip_event_type_SHIFT 16 4134 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4135 #define lpfc_acqe_fip_event_type_WORD word1 4136 uint32_t event_tag; 4137 uint32_t trailer; 4138 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4139 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4140 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4141 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 4142 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4143 }; 4144 4145 struct lpfc_acqe_dcbx { 4146 uint32_t tlv_ttl; 4147 uint32_t reserved; 4148 uint32_t event_tag; 4149 uint32_t trailer; 4150 }; 4151 4152 struct lpfc_acqe_grp5 { 4153 uint32_t word0; 4154 #define lpfc_acqe_grp5_type_SHIFT 6 4155 #define lpfc_acqe_grp5_type_MASK 0x00000003 4156 #define lpfc_acqe_grp5_type_WORD word0 4157 #define lpfc_acqe_grp5_number_SHIFT 0 4158 #define lpfc_acqe_grp5_number_MASK 0x0000003F 4159 #define lpfc_acqe_grp5_number_WORD word0 4160 uint32_t word1; 4161 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 4162 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4163 #define lpfc_acqe_grp5_llink_spd_WORD word1 4164 uint32_t event_tag; 4165 uint32_t trailer; 4166 }; 4167 4168 extern const char *const trunk_errmsg[]; 4169 4170 struct lpfc_acqe_fc_la { 4171 uint32_t word0; 4172 #define lpfc_acqe_fc_la_speed_SHIFT 24 4173 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4174 #define lpfc_acqe_fc_la_speed_WORD word0 4175 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4176 #define LPFC_FC_LA_SPEED_1G 0x1 4177 #define LPFC_FC_LA_SPEED_2G 0x2 4178 #define LPFC_FC_LA_SPEED_4G 0x4 4179 #define LPFC_FC_LA_SPEED_8G 0x8 4180 #define LPFC_FC_LA_SPEED_10G 0xA 4181 #define LPFC_FC_LA_SPEED_16G 0x10 4182 #define LPFC_FC_LA_SPEED_32G 0x20 4183 #define LPFC_FC_LA_SPEED_64G 0x21 4184 #define LPFC_FC_LA_SPEED_128G 0x22 4185 #define LPFC_FC_LA_SPEED_256G 0x23 4186 #define lpfc_acqe_fc_la_topology_SHIFT 16 4187 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4188 #define lpfc_acqe_fc_la_topology_WORD word0 4189 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4190 #define LPFC_FC_LA_TOP_P2P 0x1 4191 #define LPFC_FC_LA_TOP_FCAL 0x2 4192 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4193 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4194 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4195 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4196 #define lpfc_acqe_fc_la_att_type_WORD word0 4197 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4198 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4199 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4200 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4201 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4202 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4203 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4204 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4205 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4206 #define lpfc_acqe_fc_la_port_type_WORD word0 4207 #define LPFC_LINK_TYPE_ETHERNET 0x0 4208 #define LPFC_LINK_TYPE_FC 0x1 4209 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4210 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4211 #define lpfc_acqe_fc_la_port_number_WORD word0 4212 4213 /* Attention Type is 0x07 (Trunking Event) word0 */ 4214 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4215 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4216 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4217 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4218 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4219 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4220 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4221 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4222 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4223 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4224 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4225 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4226 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4227 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4228 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4229 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4230 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4231 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4232 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4233 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4234 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4235 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4236 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4237 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4238 uint32_t word1; 4239 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4240 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4241 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4242 #define lpfc_acqe_fc_la_fault_SHIFT 0 4243 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4244 #define lpfc_acqe_fc_la_fault_WORD word1 4245 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4246 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4247 #define lpfc_acqe_fc_la_trunk_fault_WORD word1 4248 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4249 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4250 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4251 #define LPFC_FC_LA_FAULT_NONE 0x0 4252 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4253 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4254 uint32_t event_tag; 4255 uint32_t trailer; 4256 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4257 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4258 }; 4259 4260 struct lpfc_acqe_misconfigured_event { 4261 struct { 4262 uint32_t word0; 4263 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4264 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4265 #define lpfc_sli_misconfigured_port0_state_WORD word0 4266 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4267 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4268 #define lpfc_sli_misconfigured_port1_state_WORD word0 4269 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4270 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4271 #define lpfc_sli_misconfigured_port2_state_WORD word0 4272 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4273 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4274 #define lpfc_sli_misconfigured_port3_state_WORD word0 4275 uint32_t word1; 4276 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4277 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4278 #define lpfc_sli_misconfigured_port0_op_WORD word1 4279 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4280 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4281 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4282 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4283 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4284 #define lpfc_sli_misconfigured_port1_op_WORD word1 4285 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4286 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4287 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4288 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4289 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4290 #define lpfc_sli_misconfigured_port2_op_WORD word1 4291 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4292 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4293 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4294 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4295 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4296 #define lpfc_sli_misconfigured_port3_op_WORD word1 4297 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4298 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4299 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4300 } theEvent; 4301 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4302 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4303 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4304 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4305 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4306 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4307 }; 4308 4309 struct lpfc_acqe_cgn_signal { 4310 u32 word0; 4311 #define lpfc_warn_acqe_SHIFT 0 4312 #define lpfc_warn_acqe_MASK 0x7FFFFFFF 4313 #define lpfc_warn_acqe_WORD word0 4314 #define lpfc_imm_acqe_SHIFT 31 4315 #define lpfc_imm_acqe_MASK 0x1 4316 #define lpfc_imm_acqe_WORD word0 4317 u32 alarm_cnt; 4318 u32 word2; 4319 u32 trailer; 4320 }; 4321 4322 struct lpfc_acqe_sli { 4323 uint32_t event_data1; 4324 uint32_t event_data2; 4325 uint32_t event_data3; 4326 uint32_t trailer; 4327 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4328 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4329 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4330 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4331 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4332 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4333 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4334 #define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE 4335 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4336 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4337 #define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11 4338 #define LPFC_SLI_EVENT_TYPE_RD_SIGNAL 0x12 4339 }; 4340 4341 /* 4342 * Define the bootstrap mailbox (bmbx) region used to communicate 4343 * mailbox command between the host and port. The mailbox consists 4344 * of a payload area of 256 bytes and a completion queue of length 4345 * 16 bytes. 4346 */ 4347 struct lpfc_bmbx_create { 4348 struct lpfc_mqe mqe; 4349 struct lpfc_mcqe mcqe; 4350 }; 4351 4352 #define SGL_ALIGN_SZ 64 4353 #define SGL_PAGE_SIZE 4096 4354 /* align SGL addr on a size boundary - adjust address up */ 4355 #define NO_XRI 0xffff 4356 4357 struct wqe_common { 4358 uint32_t word6; 4359 #define wqe_xri_tag_SHIFT 0 4360 #define wqe_xri_tag_MASK 0x0000FFFF 4361 #define wqe_xri_tag_WORD word6 4362 #define wqe_ctxt_tag_SHIFT 16 4363 #define wqe_ctxt_tag_MASK 0x0000FFFF 4364 #define wqe_ctxt_tag_WORD word6 4365 uint32_t word7; 4366 #define wqe_dif_SHIFT 0 4367 #define wqe_dif_MASK 0x00000003 4368 #define wqe_dif_WORD word7 4369 #define LPFC_WQE_DIF_PASSTHRU 1 4370 #define LPFC_WQE_DIF_STRIP 2 4371 #define LPFC_WQE_DIF_INSERT 3 4372 #define wqe_ct_SHIFT 2 4373 #define wqe_ct_MASK 0x00000003 4374 #define wqe_ct_WORD word7 4375 #define wqe_status_SHIFT 4 4376 #define wqe_status_MASK 0x0000000f 4377 #define wqe_status_WORD word7 4378 #define wqe_cmnd_SHIFT 8 4379 #define wqe_cmnd_MASK 0x000000ff 4380 #define wqe_cmnd_WORD word7 4381 #define wqe_class_SHIFT 16 4382 #define wqe_class_MASK 0x00000007 4383 #define wqe_class_WORD word7 4384 #define wqe_ar_SHIFT 19 4385 #define wqe_ar_MASK 0x00000001 4386 #define wqe_ar_WORD word7 4387 #define wqe_ag_SHIFT wqe_ar_SHIFT 4388 #define wqe_ag_MASK wqe_ar_MASK 4389 #define wqe_ag_WORD wqe_ar_WORD 4390 #define wqe_pu_SHIFT 20 4391 #define wqe_pu_MASK 0x00000003 4392 #define wqe_pu_WORD word7 4393 #define wqe_erp_SHIFT 22 4394 #define wqe_erp_MASK 0x00000001 4395 #define wqe_erp_WORD word7 4396 #define wqe_conf_SHIFT wqe_erp_SHIFT 4397 #define wqe_conf_MASK wqe_erp_MASK 4398 #define wqe_conf_WORD wqe_erp_WORD 4399 #define wqe_lnk_SHIFT 23 4400 #define wqe_lnk_MASK 0x00000001 4401 #define wqe_lnk_WORD word7 4402 #define wqe_tmo_SHIFT 24 4403 #define wqe_tmo_MASK 0x000000ff 4404 #define wqe_tmo_WORD word7 4405 uint32_t abort_tag; /* word 8 in WQE */ 4406 uint32_t word9; 4407 #define wqe_reqtag_SHIFT 0 4408 #define wqe_reqtag_MASK 0x0000FFFF 4409 #define wqe_reqtag_WORD word9 4410 #define wqe_temp_rpi_SHIFT 16 4411 #define wqe_temp_rpi_MASK 0x0000FFFF 4412 #define wqe_temp_rpi_WORD word9 4413 #define wqe_rcvoxid_SHIFT 16 4414 #define wqe_rcvoxid_MASK 0x0000FFFF 4415 #define wqe_rcvoxid_WORD word9 4416 #define wqe_sof_SHIFT 24 4417 #define wqe_sof_MASK 0x000000FF 4418 #define wqe_sof_WORD word9 4419 #define wqe_eof_SHIFT 16 4420 #define wqe_eof_MASK 0x000000FF 4421 #define wqe_eof_WORD word9 4422 uint32_t word10; 4423 #define wqe_ebde_cnt_SHIFT 0 4424 #define wqe_ebde_cnt_MASK 0x0000000f 4425 #define wqe_ebde_cnt_WORD word10 4426 #define wqe_xchg_SHIFT 4 4427 #define wqe_xchg_MASK 0x00000001 4428 #define wqe_xchg_WORD word10 4429 #define LPFC_SCSI_XCHG 0x0 4430 #define LPFC_NVME_XCHG 0x1 4431 #define wqe_appid_SHIFT 5 4432 #define wqe_appid_MASK 0x00000001 4433 #define wqe_appid_WORD word10 4434 #define wqe_oas_SHIFT 6 4435 #define wqe_oas_MASK 0x00000001 4436 #define wqe_oas_WORD word10 4437 #define wqe_lenloc_SHIFT 7 4438 #define wqe_lenloc_MASK 0x00000003 4439 #define wqe_lenloc_WORD word10 4440 #define LPFC_WQE_LENLOC_NONE 0 4441 #define LPFC_WQE_LENLOC_WORD3 1 4442 #define LPFC_WQE_LENLOC_WORD12 2 4443 #define LPFC_WQE_LENLOC_WORD4 3 4444 #define wqe_qosd_SHIFT 9 4445 #define wqe_qosd_MASK 0x00000001 4446 #define wqe_qosd_WORD word10 4447 #define wqe_xbl_SHIFT 11 4448 #define wqe_xbl_MASK 0x00000001 4449 #define wqe_xbl_WORD word10 4450 #define wqe_iod_SHIFT 13 4451 #define wqe_iod_MASK 0x00000001 4452 #define wqe_iod_WORD word10 4453 #define LPFC_WQE_IOD_NONE 0 4454 #define LPFC_WQE_IOD_WRITE 0 4455 #define LPFC_WQE_IOD_READ 1 4456 #define wqe_dbde_SHIFT 14 4457 #define wqe_dbde_MASK 0x00000001 4458 #define wqe_dbde_WORD word10 4459 #define wqe_wqes_SHIFT 15 4460 #define wqe_wqes_MASK 0x00000001 4461 #define wqe_wqes_WORD word10 4462 /* Note that this field overlaps above fields */ 4463 #define wqe_wqid_SHIFT 1 4464 #define wqe_wqid_MASK 0x00007fff 4465 #define wqe_wqid_WORD word10 4466 #define wqe_pri_SHIFT 16 4467 #define wqe_pri_MASK 0x00000007 4468 #define wqe_pri_WORD word10 4469 #define wqe_pv_SHIFT 19 4470 #define wqe_pv_MASK 0x00000001 4471 #define wqe_pv_WORD word10 4472 #define wqe_xc_SHIFT 21 4473 #define wqe_xc_MASK 0x00000001 4474 #define wqe_xc_WORD word10 4475 #define wqe_sr_SHIFT 22 4476 #define wqe_sr_MASK 0x00000001 4477 #define wqe_sr_WORD word10 4478 #define wqe_ccpe_SHIFT 23 4479 #define wqe_ccpe_MASK 0x00000001 4480 #define wqe_ccpe_WORD word10 4481 #define wqe_ccp_SHIFT 24 4482 #define wqe_ccp_MASK 0x000000ff 4483 #define wqe_ccp_WORD word10 4484 uint32_t word11; 4485 #define wqe_cmd_type_SHIFT 0 4486 #define wqe_cmd_type_MASK 0x0000000f 4487 #define wqe_cmd_type_WORD word11 4488 #define wqe_els_id_SHIFT 4 4489 #define wqe_els_id_MASK 0x00000007 4490 #define wqe_els_id_WORD word11 4491 #define wqe_irsp_SHIFT 4 4492 #define wqe_irsp_MASK 0x00000001 4493 #define wqe_irsp_WORD word11 4494 #define wqe_pbde_SHIFT 5 4495 #define wqe_pbde_MASK 0x00000001 4496 #define wqe_pbde_WORD word11 4497 #define wqe_sup_SHIFT 6 4498 #define wqe_sup_MASK 0x00000001 4499 #define wqe_sup_WORD word11 4500 #define wqe_ffrq_SHIFT 6 4501 #define wqe_ffrq_MASK 0x00000001 4502 #define wqe_ffrq_WORD word11 4503 #define wqe_wqec_SHIFT 7 4504 #define wqe_wqec_MASK 0x00000001 4505 #define wqe_wqec_WORD word11 4506 #define wqe_irsplen_SHIFT 8 4507 #define wqe_irsplen_MASK 0x0000000f 4508 #define wqe_irsplen_WORD word11 4509 #define wqe_cqid_SHIFT 16 4510 #define wqe_cqid_MASK 0x0000ffff 4511 #define wqe_cqid_WORD word11 4512 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4513 }; 4514 4515 struct wqe_did { 4516 uint32_t word5; 4517 #define wqe_els_did_SHIFT 0 4518 #define wqe_els_did_MASK 0x00FFFFFF 4519 #define wqe_els_did_WORD word5 4520 #define wqe_xmit_bls_pt_SHIFT 28 4521 #define wqe_xmit_bls_pt_MASK 0x00000003 4522 #define wqe_xmit_bls_pt_WORD word5 4523 #define wqe_xmit_bls_ar_SHIFT 30 4524 #define wqe_xmit_bls_ar_MASK 0x00000001 4525 #define wqe_xmit_bls_ar_WORD word5 4526 #define wqe_xmit_bls_xo_SHIFT 31 4527 #define wqe_xmit_bls_xo_MASK 0x00000001 4528 #define wqe_xmit_bls_xo_WORD word5 4529 }; 4530 4531 struct lpfc_wqe_generic{ 4532 struct ulp_bde64 bde; 4533 uint32_t word3; 4534 uint32_t word4; 4535 uint32_t word5; 4536 struct wqe_common wqe_com; 4537 uint32_t payload[4]; 4538 }; 4539 4540 enum els_request64_wqe_word11 { 4541 LPFC_ELS_ID_DEFAULT, 4542 LPFC_ELS_ID_LOGO, 4543 LPFC_ELS_ID_FDISC, 4544 LPFC_ELS_ID_FLOGI, 4545 LPFC_ELS_ID_PLOGI, 4546 }; 4547 4548 struct els_request64_wqe { 4549 struct ulp_bde64 bde; 4550 uint32_t payload_len; 4551 uint32_t word4; 4552 #define els_req64_sid_SHIFT 0 4553 #define els_req64_sid_MASK 0x00FFFFFF 4554 #define els_req64_sid_WORD word4 4555 #define els_req64_sp_SHIFT 24 4556 #define els_req64_sp_MASK 0x00000001 4557 #define els_req64_sp_WORD word4 4558 #define els_req64_vf_SHIFT 25 4559 #define els_req64_vf_MASK 0x00000001 4560 #define els_req64_vf_WORD word4 4561 struct wqe_did wqe_dest; 4562 struct wqe_common wqe_com; /* words 6-11 */ 4563 uint32_t word12; 4564 #define els_req64_vfid_SHIFT 1 4565 #define els_req64_vfid_MASK 0x00000FFF 4566 #define els_req64_vfid_WORD word12 4567 #define els_req64_pri_SHIFT 13 4568 #define els_req64_pri_MASK 0x00000007 4569 #define els_req64_pri_WORD word12 4570 uint32_t word13; 4571 #define els_req64_hopcnt_SHIFT 24 4572 #define els_req64_hopcnt_MASK 0x000000ff 4573 #define els_req64_hopcnt_WORD word13 4574 uint32_t word14; 4575 uint32_t max_response_payload_len; 4576 }; 4577 4578 struct xmit_els_rsp64_wqe { 4579 struct ulp_bde64 bde; 4580 uint32_t response_payload_len; 4581 uint32_t word4; 4582 #define els_rsp64_sid_SHIFT 0 4583 #define els_rsp64_sid_MASK 0x00FFFFFF 4584 #define els_rsp64_sid_WORD word4 4585 #define els_rsp64_sp_SHIFT 24 4586 #define els_rsp64_sp_MASK 0x00000001 4587 #define els_rsp64_sp_WORD word4 4588 struct wqe_did wqe_dest; 4589 struct wqe_common wqe_com; /* words 6-11 */ 4590 uint32_t word12; 4591 #define wqe_rsp_temp_rpi_SHIFT 0 4592 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4593 #define wqe_rsp_temp_rpi_WORD word12 4594 uint32_t rsvd_13_15[3]; 4595 }; 4596 4597 struct xmit_bls_rsp64_wqe { 4598 uint32_t payload0; 4599 /* Payload0 for BA_ACC */ 4600 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4601 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4602 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4603 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4604 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4605 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4606 /* Payload0 for BA_RJT */ 4607 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4608 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4609 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4610 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4611 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4612 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4613 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4614 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4615 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4616 uint32_t word1; 4617 #define xmit_bls_rsp64_rxid_SHIFT 0 4618 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4619 #define xmit_bls_rsp64_rxid_WORD word1 4620 #define xmit_bls_rsp64_oxid_SHIFT 16 4621 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4622 #define xmit_bls_rsp64_oxid_WORD word1 4623 uint32_t word2; 4624 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4625 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4626 #define xmit_bls_rsp64_seqcnthi_WORD word2 4627 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4628 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4629 #define xmit_bls_rsp64_seqcntlo_WORD word2 4630 uint32_t rsrvd3; 4631 uint32_t rsrvd4; 4632 struct wqe_did wqe_dest; 4633 struct wqe_common wqe_com; /* words 6-11 */ 4634 uint32_t word12; 4635 #define xmit_bls_rsp64_temprpi_SHIFT 0 4636 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4637 #define xmit_bls_rsp64_temprpi_WORD word12 4638 uint32_t rsvd_13_15[3]; 4639 }; 4640 4641 struct wqe_rctl_dfctl { 4642 uint32_t word5; 4643 #define wqe_si_SHIFT 2 4644 #define wqe_si_MASK 0x000000001 4645 #define wqe_si_WORD word5 4646 #define wqe_la_SHIFT 3 4647 #define wqe_la_MASK 0x000000001 4648 #define wqe_la_WORD word5 4649 #define wqe_xo_SHIFT 6 4650 #define wqe_xo_MASK 0x000000001 4651 #define wqe_xo_WORD word5 4652 #define wqe_ls_SHIFT 7 4653 #define wqe_ls_MASK 0x000000001 4654 #define wqe_ls_WORD word5 4655 #define wqe_dfctl_SHIFT 8 4656 #define wqe_dfctl_MASK 0x0000000ff 4657 #define wqe_dfctl_WORD word5 4658 #define wqe_type_SHIFT 16 4659 #define wqe_type_MASK 0x0000000ff 4660 #define wqe_type_WORD word5 4661 #define wqe_rctl_SHIFT 24 4662 #define wqe_rctl_MASK 0x0000000ff 4663 #define wqe_rctl_WORD word5 4664 }; 4665 4666 struct xmit_seq64_wqe { 4667 struct ulp_bde64 bde; 4668 uint32_t rsvd3; 4669 uint32_t relative_offset; 4670 struct wqe_rctl_dfctl wge_ctl; 4671 struct wqe_common wqe_com; /* words 6-11 */ 4672 uint32_t xmit_len; 4673 uint32_t rsvd_12_15[3]; 4674 }; 4675 struct xmit_bcast64_wqe { 4676 struct ulp_bde64 bde; 4677 uint32_t seq_payload_len; 4678 uint32_t rsvd4; 4679 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4680 struct wqe_common wqe_com; /* words 6-11 */ 4681 uint32_t rsvd_12_15[4]; 4682 }; 4683 4684 struct gen_req64_wqe { 4685 struct ulp_bde64 bde; 4686 uint32_t request_payload_len; 4687 uint32_t relative_offset; 4688 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4689 struct wqe_common wqe_com; /* words 6-11 */ 4690 uint32_t rsvd_12_14[3]; 4691 uint32_t max_response_payload_len; 4692 }; 4693 4694 /* Define NVME PRLI request to fabric. NVME is a 4695 * fabric-only protocol. 4696 * Updated to red-lined v1.08 on Sept 16, 2016 4697 */ 4698 struct lpfc_nvme_prli { 4699 uint32_t word1; 4700 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4701 #define prli_acc_rsp_code_SHIFT 8 4702 #define prli_acc_rsp_code_MASK 0x0000000f 4703 #define prli_acc_rsp_code_WORD word1 4704 #define prli_estabImagePair_SHIFT 13 4705 #define prli_estabImagePair_MASK 0x00000001 4706 #define prli_estabImagePair_WORD word1 4707 #define prli_type_code_ext_SHIFT 16 4708 #define prli_type_code_ext_MASK 0x000000ff 4709 #define prli_type_code_ext_WORD word1 4710 #define prli_type_code_SHIFT 24 4711 #define prli_type_code_MASK 0x000000ff 4712 #define prli_type_code_WORD word1 4713 uint32_t word_rsvd2; 4714 uint32_t word_rsvd3; 4715 4716 uint32_t word4; 4717 #define prli_fba_SHIFT 0 4718 #define prli_fba_MASK 0x00000001 4719 #define prli_fba_WORD word4 4720 #define prli_disc_SHIFT 3 4721 #define prli_disc_MASK 0x00000001 4722 #define prli_disc_WORD word4 4723 #define prli_tgt_SHIFT 4 4724 #define prli_tgt_MASK 0x00000001 4725 #define prli_tgt_WORD word4 4726 #define prli_init_SHIFT 5 4727 #define prli_init_MASK 0x00000001 4728 #define prli_init_WORD word4 4729 #define prli_conf_SHIFT 7 4730 #define prli_conf_MASK 0x00000001 4731 #define prli_conf_WORD word4 4732 #define prli_nsler_SHIFT 8 4733 #define prli_nsler_MASK 0x00000001 4734 #define prli_nsler_WORD word4 4735 uint32_t word5; 4736 #define prli_fb_sz_SHIFT 0 4737 #define prli_fb_sz_MASK 0x0000ffff 4738 #define prli_fb_sz_WORD word5 4739 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4740 }; 4741 4742 struct create_xri_wqe { 4743 uint32_t rsrvd[5]; /* words 0-4 */ 4744 struct wqe_did wqe_dest; /* word 5 */ 4745 struct wqe_common wqe_com; /* words 6-11 */ 4746 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4747 }; 4748 4749 #define T_REQUEST_TAG 3 4750 #define T_XRI_TAG 1 4751 4752 struct cmf_sync_wqe { 4753 uint32_t rsrvd[3]; 4754 uint32_t word3; 4755 #define cmf_sync_interval_SHIFT 0 4756 #define cmf_sync_interval_MASK 0x00000ffff 4757 #define cmf_sync_interval_WORD word3 4758 #define cmf_sync_afpin_SHIFT 16 4759 #define cmf_sync_afpin_MASK 0x000000001 4760 #define cmf_sync_afpin_WORD word3 4761 #define cmf_sync_asig_SHIFT 17 4762 #define cmf_sync_asig_MASK 0x000000001 4763 #define cmf_sync_asig_WORD word3 4764 #define cmf_sync_op_SHIFT 20 4765 #define cmf_sync_op_MASK 0x00000000f 4766 #define cmf_sync_op_WORD word3 4767 #define cmf_sync_ver_SHIFT 24 4768 #define cmf_sync_ver_MASK 0x0000000ff 4769 #define cmf_sync_ver_WORD word3 4770 #define LPFC_CMF_SYNC_VER 1 4771 uint32_t event_tag; 4772 uint32_t word5; 4773 #define cmf_sync_wsigmax_SHIFT 0 4774 #define cmf_sync_wsigmax_MASK 0x00000ffff 4775 #define cmf_sync_wsigmax_WORD word5 4776 #define cmf_sync_wsigcnt_SHIFT 16 4777 #define cmf_sync_wsigcnt_MASK 0x00000ffff 4778 #define cmf_sync_wsigcnt_WORD word5 4779 uint32_t word6; 4780 uint32_t word7; 4781 #define cmf_sync_cmnd_SHIFT 8 4782 #define cmf_sync_cmnd_MASK 0x0000000ff 4783 #define cmf_sync_cmnd_WORD word7 4784 uint32_t word8; 4785 uint32_t word9; 4786 #define cmf_sync_reqtag_SHIFT 0 4787 #define cmf_sync_reqtag_MASK 0x00000ffff 4788 #define cmf_sync_reqtag_WORD word9 4789 #define cmf_sync_wfpinmax_SHIFT 16 4790 #define cmf_sync_wfpinmax_MASK 0x0000000ff 4791 #define cmf_sync_wfpinmax_WORD word9 4792 #define cmf_sync_wfpincnt_SHIFT 24 4793 #define cmf_sync_wfpincnt_MASK 0x0000000ff 4794 #define cmf_sync_wfpincnt_WORD word9 4795 uint32_t word10; 4796 #define cmf_sync_qosd_SHIFT 9 4797 #define cmf_sync_qosd_MASK 0x00000001 4798 #define cmf_sync_qosd_WORD word10 4799 uint32_t word11; 4800 #define cmf_sync_cmd_type_SHIFT 0 4801 #define cmf_sync_cmd_type_MASK 0x0000000f 4802 #define cmf_sync_cmd_type_WORD word11 4803 #define cmf_sync_wqec_SHIFT 7 4804 #define cmf_sync_wqec_MASK 0x00000001 4805 #define cmf_sync_wqec_WORD word11 4806 #define cmf_sync_cqid_SHIFT 16 4807 #define cmf_sync_cqid_MASK 0x0000ffff 4808 #define cmf_sync_cqid_WORD word11 4809 uint32_t read_bytes; 4810 uint32_t word13; 4811 #define cmf_sync_period_SHIFT 16 4812 #define cmf_sync_period_MASK 0x0000ffff 4813 #define cmf_sync_period_WORD word13 4814 uint32_t word14; 4815 uint32_t word15; 4816 }; 4817 4818 struct abort_cmd_wqe { 4819 uint32_t rsrvd[3]; 4820 uint32_t word3; 4821 #define abort_cmd_ia_SHIFT 0 4822 #define abort_cmd_ia_MASK 0x000000001 4823 #define abort_cmd_ia_WORD word3 4824 #define abort_cmd_criteria_SHIFT 8 4825 #define abort_cmd_criteria_MASK 0x0000000ff 4826 #define abort_cmd_criteria_WORD word3 4827 uint32_t rsrvd4; 4828 uint32_t rsrvd5; 4829 struct wqe_common wqe_com; /* words 6-11 */ 4830 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4831 }; 4832 4833 struct fcp_iwrite64_wqe { 4834 struct ulp_bde64 bde; 4835 uint32_t word3; 4836 #define cmd_buff_len_SHIFT 16 4837 #define cmd_buff_len_MASK 0x00000ffff 4838 #define cmd_buff_len_WORD word3 4839 #define payload_offset_len_SHIFT 0 4840 #define payload_offset_len_MASK 0x0000ffff 4841 #define payload_offset_len_WORD word3 4842 uint32_t total_xfer_len; 4843 uint32_t initial_xfer_len; 4844 struct wqe_common wqe_com; /* words 6-11 */ 4845 uint32_t rsrvd12; 4846 struct ulp_bde64 ph_bde; /* words 13-15 */ 4847 }; 4848 4849 struct fcp_iread64_wqe { 4850 struct ulp_bde64 bde; 4851 uint32_t word3; 4852 #define cmd_buff_len_SHIFT 16 4853 #define cmd_buff_len_MASK 0x00000ffff 4854 #define cmd_buff_len_WORD word3 4855 #define payload_offset_len_SHIFT 0 4856 #define payload_offset_len_MASK 0x0000ffff 4857 #define payload_offset_len_WORD word3 4858 uint32_t total_xfer_len; /* word 4 */ 4859 uint32_t rsrvd5; /* word 5 */ 4860 struct wqe_common wqe_com; /* words 6-11 */ 4861 uint32_t rsrvd12; 4862 struct ulp_bde64 ph_bde; /* words 13-15 */ 4863 }; 4864 4865 struct fcp_icmnd64_wqe { 4866 struct ulp_bde64 bde; /* words 0-2 */ 4867 uint32_t word3; 4868 #define cmd_buff_len_SHIFT 16 4869 #define cmd_buff_len_MASK 0x00000ffff 4870 #define cmd_buff_len_WORD word3 4871 #define payload_offset_len_SHIFT 0 4872 #define payload_offset_len_MASK 0x0000ffff 4873 #define payload_offset_len_WORD word3 4874 uint32_t rsrvd4; /* word 4 */ 4875 uint32_t rsrvd5; /* word 5 */ 4876 struct wqe_common wqe_com; /* words 6-11 */ 4877 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4878 }; 4879 4880 struct fcp_trsp64_wqe { 4881 struct ulp_bde64 bde; 4882 uint32_t response_len; 4883 uint32_t rsvd_4_5[2]; 4884 struct wqe_common wqe_com; /* words 6-11 */ 4885 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4886 }; 4887 4888 struct fcp_tsend64_wqe { 4889 struct ulp_bde64 bde; 4890 uint32_t payload_offset_len; 4891 uint32_t relative_offset; 4892 uint32_t reserved; 4893 struct wqe_common wqe_com; /* words 6-11 */ 4894 uint32_t fcp_data_len; /* word 12 */ 4895 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4896 }; 4897 4898 struct fcp_treceive64_wqe { 4899 struct ulp_bde64 bde; 4900 uint32_t payload_offset_len; 4901 uint32_t relative_offset; 4902 uint32_t reserved; 4903 struct wqe_common wqe_com; /* words 6-11 */ 4904 uint32_t fcp_data_len; /* word 12 */ 4905 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4906 }; 4907 #define TXRDY_PAYLOAD_LEN 12 4908 4909 #define CMD_SEND_FRAME 0xE1 4910 4911 struct send_frame_wqe { 4912 struct ulp_bde64 bde; /* words 0-2 */ 4913 uint32_t frame_len; /* word 3 */ 4914 uint32_t fc_hdr_wd0; /* word 4 */ 4915 uint32_t fc_hdr_wd1; /* word 5 */ 4916 struct wqe_common wqe_com; /* words 6-11 */ 4917 uint32_t fc_hdr_wd2; /* word 12 */ 4918 uint32_t fc_hdr_wd3; /* word 13 */ 4919 uint32_t fc_hdr_wd4; /* word 14 */ 4920 uint32_t fc_hdr_wd5; /* word 15 */ 4921 }; 4922 4923 #define ELS_RDF_REG_TAG_CNT 4 4924 struct lpfc_els_rdf_reg_desc { 4925 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */ 4926 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4927 /* tags in reg_desc */ 4928 }; 4929 4930 struct lpfc_els_rdf_req { 4931 struct fc_els_rdf rdf; /* hdr up to descriptors */ 4932 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4933 }; 4934 4935 struct lpfc_els_rdf_rsp { 4936 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */ 4937 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4938 }; 4939 4940 union lpfc_wqe { 4941 uint32_t words[16]; 4942 struct lpfc_wqe_generic generic; 4943 struct fcp_icmnd64_wqe fcp_icmd; 4944 struct fcp_iread64_wqe fcp_iread; 4945 struct fcp_iwrite64_wqe fcp_iwrite; 4946 struct abort_cmd_wqe abort_cmd; 4947 struct cmf_sync_wqe cmf_sync; 4948 struct create_xri_wqe create_xri; 4949 struct xmit_bcast64_wqe xmit_bcast64; 4950 struct xmit_seq64_wqe xmit_sequence; 4951 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4952 struct xmit_els_rsp64_wqe xmit_els_rsp; 4953 struct els_request64_wqe els_req; 4954 struct gen_req64_wqe gen_req; 4955 struct fcp_trsp64_wqe fcp_trsp; 4956 struct fcp_tsend64_wqe fcp_tsend; 4957 struct fcp_treceive64_wqe fcp_treceive; 4958 struct send_frame_wqe send_frame; 4959 }; 4960 4961 union lpfc_wqe128 { 4962 uint32_t words[32]; 4963 struct lpfc_wqe_generic generic; 4964 struct fcp_icmnd64_wqe fcp_icmd; 4965 struct fcp_iread64_wqe fcp_iread; 4966 struct fcp_iwrite64_wqe fcp_iwrite; 4967 struct abort_cmd_wqe abort_cmd; 4968 struct cmf_sync_wqe cmf_sync; 4969 struct create_xri_wqe create_xri; 4970 struct xmit_bcast64_wqe xmit_bcast64; 4971 struct xmit_seq64_wqe xmit_sequence; 4972 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4973 struct xmit_els_rsp64_wqe xmit_els_rsp; 4974 struct els_request64_wqe els_req; 4975 struct gen_req64_wqe gen_req; 4976 struct fcp_trsp64_wqe fcp_trsp; 4977 struct fcp_tsend64_wqe fcp_tsend; 4978 struct fcp_treceive64_wqe fcp_treceive; 4979 struct send_frame_wqe send_frame; 4980 }; 4981 4982 #define MAGIC_NUMBER_G6 0xFEAA0003 4983 #define MAGIC_NUMBER_G7 0xFEAA0005 4984 #define MAGIC_NUMBER_G7P 0xFEAA0020 4985 4986 struct lpfc_grp_hdr { 4987 uint32_t size; 4988 uint32_t magic_number; 4989 uint32_t word2; 4990 #define lpfc_grp_hdr_file_type_SHIFT 24 4991 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4992 #define lpfc_grp_hdr_file_type_WORD word2 4993 #define lpfc_grp_hdr_id_SHIFT 16 4994 #define lpfc_grp_hdr_id_MASK 0x000000FF 4995 #define lpfc_grp_hdr_id_WORD word2 4996 uint8_t rev_name[128]; 4997 uint8_t date[12]; 4998 uint8_t revision[32]; 4999 }; 5000 5001 /* Defines for WQE command type */ 5002 #define FCP_COMMAND 0x0 5003 #define NVME_READ_CMD 0x0 5004 #define FCP_COMMAND_DATA_OUT 0x1 5005 #define NVME_WRITE_CMD 0x1 5006 #define COMMAND_DATA_IN 0x0 5007 #define COMMAND_DATA_OUT 0x1 5008 #define FCP_COMMAND_TRECEIVE 0x2 5009 #define FCP_COMMAND_TRSP 0x3 5010 #define FCP_COMMAND_TSEND 0x7 5011 #define OTHER_COMMAND 0x8 5012 #define CMF_SYNC_COMMAND 0xA 5013 #define ELS_COMMAND_NON_FIP 0xC 5014 #define ELS_COMMAND_FIP 0xD 5015 5016 #define LPFC_NVME_EMBED_CMD 0x0 5017 #define LPFC_NVME_EMBED_WRITE 0x1 5018 #define LPFC_NVME_EMBED_READ 0x2 5019 5020 /* WQE Commands */ 5021 #define CMD_ABORT_XRI_WQE 0x0F 5022 #define CMD_XMIT_SEQUENCE64_WQE 0x82 5023 #define CMD_XMIT_BCAST64_WQE 0x84 5024 #define CMD_ELS_REQUEST64_WQE 0x8A 5025 #define CMD_XMIT_ELS_RSP64_WQE 0x95 5026 #define CMD_XMIT_BLS_RSP64_WQE 0x97 5027 #define CMD_FCP_IWRITE64_WQE 0x98 5028 #define CMD_FCP_IREAD64_WQE 0x9A 5029 #define CMD_FCP_ICMND64_WQE 0x9C 5030 #define CMD_FCP_TSEND64_WQE 0x9F 5031 #define CMD_FCP_TRECEIVE64_WQE 0xA1 5032 #define CMD_FCP_TRSP64_WQE 0xA3 5033 #define CMD_GEN_REQUEST64_WQE 0xC2 5034 #define CMD_CMF_SYNC_WQE 0xE8 5035 5036 #define CMD_WQE_MASK 0xff 5037 5038 5039 #define LPFC_FW_DUMP 1 5040 #define LPFC_FW_RESET 2 5041 #define LPFC_DV_RESET 3 5042 5043 /* On some kernels, enum fc_ls_tlv_dtag does not have 5044 * these 2 enums defined, on other kernels it does. 5045 * To get aound this we need to add these 2 defines here. 5046 */ 5047 #ifndef ELS_DTAG_LNK_FAULT_CAP 5048 #define ELS_DTAG_LNK_FAULT_CAP 0x0001000D 5049 #endif 5050 #ifndef ELS_DTAG_CG_SIGNAL_CAP 5051 #define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F 5052 #endif 5053 5054 /* 5055 * Initializer useful for decoding FPIN string table. 5056 */ 5057 #define FC_FPIN_CONGN_SEVERITY_INIT { \ 5058 { FPIN_CONGN_SEVERITY_WARNING, "Warning" }, \ 5059 { FPIN_CONGN_SEVERITY_ERROR, "Alarm" }, \ 5060 } 5061 5062 /* Used for logging FPIN messages */ 5063 #define LPFC_FPIN_WWPN_LINE_SZ 128 5064 #define LPFC_FPIN_WWPN_LINE_CNT 6 5065 #define LPFC_FPIN_WWPN_NUM_LINE 6 5066