1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2021 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #include <uapi/scsi/fc/fc_els.h> 24 25 /* Macros to deal with bit fields. Each bit field must have 3 #defines 26 * associated with it (_SHIFT, _MASK, and _WORD). 27 * EG. For a bit field that is in the 7th bit of the "field4" field of a 28 * structure and is 2 bits in size the following #defines must exist: 29 * struct temp { 30 * uint32_t field1; 31 * uint32_t field2; 32 * uint32_t field3; 33 * uint32_t field4; 34 * #define example_bit_field_SHIFT 7 35 * #define example_bit_field_MASK 0x03 36 * #define example_bit_field_WORD field4 37 * uint32_t field5; 38 * }; 39 * Then the macros below may be used to get or set the value of that field. 40 * EG. To get the value of the bit field from the above example: 41 * struct temp t1; 42 * value = bf_get(example_bit_field, &t1); 43 * And then to set that bit field: 44 * bf_set(example_bit_field, &t1, 2); 45 * Or clear that bit field: 46 * bf_set(example_bit_field, &t1, 0); 47 */ 48 #define bf_get_be32(name, ptr) \ 49 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get_le32(name, ptr) \ 51 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 52 #define bf_get(name, ptr) \ 53 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 54 #define bf_set_le32(name, ptr, value) \ 55 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 56 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 57 ~(name##_MASK << name##_SHIFT))))) 58 #define bf_set(name, ptr, value) \ 59 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 60 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 61 62 struct dma_address { 63 uint32_t addr_lo; 64 uint32_t addr_hi; 65 }; 66 67 struct lpfc_sli_intf { 68 uint32_t word0; 69 #define lpfc_sli_intf_valid_SHIFT 29 70 #define lpfc_sli_intf_valid_MASK 0x00000007 71 #define lpfc_sli_intf_valid_WORD word0 72 #define LPFC_SLI_INTF_VALID 6 73 #define lpfc_sli_intf_sli_hint2_SHIFT 24 74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 75 #define lpfc_sli_intf_sli_hint2_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 77 #define lpfc_sli_intf_sli_hint1_SHIFT 16 78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 79 #define lpfc_sli_intf_sli_hint1_WORD word0 80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 81 #define LPFC_SLI_INTF_SLI_HINT1_1 1 82 #define LPFC_SLI_INTF_SLI_HINT1_2 2 83 #define lpfc_sli_intf_if_type_SHIFT 12 84 #define lpfc_sli_intf_if_type_MASK 0x0000000F 85 #define lpfc_sli_intf_if_type_WORD word0 86 #define LPFC_SLI_INTF_IF_TYPE_0 0 87 #define LPFC_SLI_INTF_IF_TYPE_1 1 88 #define LPFC_SLI_INTF_IF_TYPE_2 2 89 #define LPFC_SLI_INTF_IF_TYPE_6 6 90 #define lpfc_sli_intf_sli_family_SHIFT 8 91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 92 #define lpfc_sli_intf_sli_family_WORD word0 93 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 94 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 95 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 96 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 97 #define lpfc_sli_intf_slirev_SHIFT 4 98 #define lpfc_sli_intf_slirev_MASK 0x0000000F 99 #define lpfc_sli_intf_slirev_WORD word0 100 #define LPFC_SLI_INTF_REV_SLI3 3 101 #define LPFC_SLI_INTF_REV_SLI4 4 102 #define lpfc_sli_intf_func_type_SHIFT 0 103 #define lpfc_sli_intf_func_type_MASK 0x00000001 104 #define lpfc_sli_intf_func_type_WORD word0 105 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 106 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 107 }; 108 109 #define LPFC_SLI4_MBX_EMBED true 110 #define LPFC_SLI4_MBX_NEMBED false 111 112 #define LPFC_SLI4_MB_WORD_COUNT 64 113 #define LPFC_MAX_MQ_PAGE 8 114 #define LPFC_MAX_WQ_PAGE_V0 4 115 #define LPFC_MAX_WQ_PAGE 8 116 #define LPFC_MAX_RQ_PAGE 8 117 #define LPFC_MAX_CQ_PAGE 4 118 #define LPFC_MAX_EQ_PAGE 8 119 120 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 121 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 122 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 123 124 /* Define SLI4 Alignment requirements. */ 125 #define LPFC_ALIGN_16_BYTE 16 126 #define LPFC_ALIGN_64_BYTE 64 127 #define SLI4_PAGE_SIZE 4096 128 129 /* Define SLI4 specific definitions. */ 130 #define LPFC_MQ_CQE_BYTE_OFFSET 256 131 #define LPFC_MBX_CMD_HDR_LENGTH 16 132 #define LPFC_MBX_ERROR_RANGE 0x4000 133 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 134 #define LPFC_BMBX_BIT1_ADDR_LO 0 135 #define LPFC_RPI_HDR_COUNT 64 136 #define LPFC_HDR_TEMPLATE_SIZE 4096 137 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 138 #define LPFC_FCF_RECORD_WD_CNT 132 139 #define LPFC_ENTIRE_FCF_DATABASE 0 140 #define LPFC_DFLT_FCF_INDEX 0 141 142 /* Virtual function numbers */ 143 #define LPFC_VF0 0 144 #define LPFC_VF1 1 145 #define LPFC_VF2 2 146 #define LPFC_VF3 3 147 #define LPFC_VF4 4 148 #define LPFC_VF5 5 149 #define LPFC_VF6 6 150 #define LPFC_VF7 7 151 #define LPFC_VF8 8 152 #define LPFC_VF9 9 153 #define LPFC_VF10 10 154 #define LPFC_VF11 11 155 #define LPFC_VF12 12 156 #define LPFC_VF13 13 157 #define LPFC_VF14 14 158 #define LPFC_VF15 15 159 #define LPFC_VF16 16 160 #define LPFC_VF17 17 161 #define LPFC_VF18 18 162 #define LPFC_VF19 19 163 #define LPFC_VF20 20 164 #define LPFC_VF21 21 165 #define LPFC_VF22 22 166 #define LPFC_VF23 23 167 #define LPFC_VF24 24 168 #define LPFC_VF25 25 169 #define LPFC_VF26 26 170 #define LPFC_VF27 27 171 #define LPFC_VF28 28 172 #define LPFC_VF29 29 173 #define LPFC_VF30 30 174 #define LPFC_VF31 31 175 176 /* PCI function numbers */ 177 #define LPFC_PCI_FUNC0 0 178 #define LPFC_PCI_FUNC1 1 179 #define LPFC_PCI_FUNC2 2 180 #define LPFC_PCI_FUNC3 3 181 #define LPFC_PCI_FUNC4 4 182 183 /* SLI4 interface type-2 PDEV_CTL register */ 184 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 185 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 186 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 187 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 188 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 189 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 190 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 191 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 192 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 193 194 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 195 196 /* Active interrupt test count */ 197 #define LPFC_ACT_INTR_CNT 4 198 199 /* Algrithmns for scheduling FCP commands to WQs */ 200 #define LPFC_FCP_SCHED_BY_HDWQ 0 201 #define LPFC_FCP_SCHED_BY_CPU 1 202 203 /* Algrithmns for NameServer Query after RSCN */ 204 #define LPFC_NS_QUERY_GID_FT 0 205 #define LPFC_NS_QUERY_GID_PT 1 206 207 /* Delay Multiplier constant */ 208 #define LPFC_DMULT_CONST 651042 209 #define LPFC_DMULT_MAX 1023 210 211 /* Configuration of Interrupts / sec for entire HBA port */ 212 #define LPFC_MIN_IMAX 5000 213 #define LPFC_MAX_IMAX 5000000 214 #define LPFC_DEF_IMAX 0 215 216 #define LPFC_MAX_AUTO_EQ_DELAY 120 217 #define LPFC_EQ_DELAY_STEP 15 218 #define LPFC_EQD_ISR_TRIGGER 20000 219 /* 1s intervals */ 220 #define LPFC_EQ_DELAY_MSECS 1000 221 222 #define LPFC_MIN_CPU_MAP 0 223 #define LPFC_MAX_CPU_MAP 1 224 #define LPFC_HBA_CPU_MAP 1 225 226 /* PORT_CAPABILITIES constants. */ 227 #define LPFC_MAX_SUPPORTED_PAGES 8 228 229 struct ulp_bde64 { 230 union ULP_BDE_TUS { 231 uint32_t w; 232 struct { 233 #ifdef __BIG_ENDIAN_BITFIELD 234 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 235 VALUE !! */ 236 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 237 #else /* __LITTLE_ENDIAN_BITFIELD */ 238 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 239 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 240 VALUE !! */ 241 #endif 242 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 243 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 244 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 245 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 246 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 247 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 248 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 249 } f; 250 } tus; 251 uint32_t addrLow; 252 uint32_t addrHigh; 253 }; 254 255 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 256 #define LPFC_MAX_BDE_IMM_SIZE 64 257 258 struct lpfc_sli4_flags { 259 uint32_t word0; 260 #define lpfc_idx_rsrc_rdy_SHIFT 0 261 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 262 #define lpfc_idx_rsrc_rdy_WORD word0 263 #define LPFC_IDX_RSRC_RDY 1 264 #define lpfc_rpi_rsrc_rdy_SHIFT 1 265 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 266 #define lpfc_rpi_rsrc_rdy_WORD word0 267 #define LPFC_RPI_RSRC_RDY 1 268 #define lpfc_vpi_rsrc_rdy_SHIFT 2 269 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 270 #define lpfc_vpi_rsrc_rdy_WORD word0 271 #define LPFC_VPI_RSRC_RDY 1 272 #define lpfc_vfi_rsrc_rdy_SHIFT 3 273 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 274 #define lpfc_vfi_rsrc_rdy_WORD word0 275 #define LPFC_VFI_RSRC_RDY 1 276 #define lpfc_ftr_ashdr_SHIFT 4 277 #define lpfc_ftr_ashdr_MASK 0x00000001 278 #define lpfc_ftr_ashdr_WORD word0 279 }; 280 281 struct sli4_bls_rsp { 282 uint32_t word0_rsvd; /* Word0 must be reserved */ 283 uint32_t word1; 284 #define lpfc_abts_orig_SHIFT 0 285 #define lpfc_abts_orig_MASK 0x00000001 286 #define lpfc_abts_orig_WORD word1 287 #define LPFC_ABTS_UNSOL_RSP 1 288 #define LPFC_ABTS_UNSOL_INT 0 289 uint32_t word2; 290 #define lpfc_abts_rxid_SHIFT 0 291 #define lpfc_abts_rxid_MASK 0x0000FFFF 292 #define lpfc_abts_rxid_WORD word2 293 #define lpfc_abts_oxid_SHIFT 16 294 #define lpfc_abts_oxid_MASK 0x0000FFFF 295 #define lpfc_abts_oxid_WORD word2 296 uint32_t word3; 297 #define lpfc_vndr_code_SHIFT 0 298 #define lpfc_vndr_code_MASK 0x000000FF 299 #define lpfc_vndr_code_WORD word3 300 #define lpfc_rsn_expln_SHIFT 8 301 #define lpfc_rsn_expln_MASK 0x000000FF 302 #define lpfc_rsn_expln_WORD word3 303 #define lpfc_rsn_code_SHIFT 16 304 #define lpfc_rsn_code_MASK 0x000000FF 305 #define lpfc_rsn_code_WORD word3 306 307 uint32_t word4; 308 uint32_t word5_rsvd; /* Word5 must be reserved */ 309 }; 310 311 /* event queue entry structure */ 312 struct lpfc_eqe { 313 uint32_t word0; 314 #define lpfc_eqe_resource_id_SHIFT 16 315 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 316 #define lpfc_eqe_resource_id_WORD word0 317 #define lpfc_eqe_minor_code_SHIFT 4 318 #define lpfc_eqe_minor_code_MASK 0x00000FFF 319 #define lpfc_eqe_minor_code_WORD word0 320 #define lpfc_eqe_major_code_SHIFT 1 321 #define lpfc_eqe_major_code_MASK 0x00000007 322 #define lpfc_eqe_major_code_WORD word0 323 #define lpfc_eqe_valid_SHIFT 0 324 #define lpfc_eqe_valid_MASK 0x00000001 325 #define lpfc_eqe_valid_WORD word0 326 }; 327 328 /* completion queue entry structure (common fields for all cqe types) */ 329 struct lpfc_cqe { 330 uint32_t reserved0; 331 uint32_t reserved1; 332 uint32_t reserved2; 333 uint32_t word3; 334 #define lpfc_cqe_valid_SHIFT 31 335 #define lpfc_cqe_valid_MASK 0x00000001 336 #define lpfc_cqe_valid_WORD word3 337 #define lpfc_cqe_code_SHIFT 16 338 #define lpfc_cqe_code_MASK 0x000000FF 339 #define lpfc_cqe_code_WORD word3 340 }; 341 342 /* Completion Queue Entry Status Codes */ 343 #define CQE_STATUS_SUCCESS 0x0 344 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 345 #define CQE_STATUS_REMOTE_STOP 0x2 346 #define CQE_STATUS_LOCAL_REJECT 0x3 347 #define CQE_STATUS_NPORT_RJT 0x4 348 #define CQE_STATUS_FABRIC_RJT 0x5 349 #define CQE_STATUS_NPORT_BSY 0x6 350 #define CQE_STATUS_FABRIC_BSY 0x7 351 #define CQE_STATUS_INTERMED_RSP 0x8 352 #define CQE_STATUS_LS_RJT 0x9 353 #define CQE_STATUS_CMD_REJECT 0xb 354 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 355 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 356 #define CQE_STATUS_DI_ERROR 0x16 357 358 /* Used when mapping CQE status to IOCB */ 359 #define LPFC_IOCB_STATUS_MASK 0xf 360 361 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 362 #define CQE_HW_STATUS_NO_ERR 0x0 363 #define CQE_HW_STATUS_UNDERRUN 0x1 364 #define CQE_HW_STATUS_OVERRUN 0x2 365 366 /* Completion Queue Entry Codes */ 367 #define CQE_CODE_COMPL_WQE 0x1 368 #define CQE_CODE_RELEASE_WQE 0x2 369 #define CQE_CODE_RECEIVE 0x4 370 #define CQE_CODE_XRI_ABORTED 0x5 371 #define CQE_CODE_RECEIVE_V1 0x9 372 #define CQE_CODE_NVME_ERSP 0xd 373 374 /* 375 * Define mask value for xri_aborted and wcqe completed CQE extended status. 376 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 377 */ 378 #define WCQE_PARAM_MASK 0x1FF 379 380 /* completion queue entry for wqe completions */ 381 struct lpfc_wcqe_complete { 382 uint32_t word0; 383 #define lpfc_wcqe_c_request_tag_SHIFT 16 384 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 385 #define lpfc_wcqe_c_request_tag_WORD word0 386 #define lpfc_wcqe_c_status_SHIFT 8 387 #define lpfc_wcqe_c_status_MASK 0x000000FF 388 #define lpfc_wcqe_c_status_WORD word0 389 #define lpfc_wcqe_c_hw_status_SHIFT 0 390 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 391 #define lpfc_wcqe_c_hw_status_WORD word0 392 #define lpfc_wcqe_c_ersp0_SHIFT 0 393 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 394 #define lpfc_wcqe_c_ersp0_WORD word0 395 uint32_t total_data_placed; 396 uint32_t parameter; 397 #define lpfc_wcqe_c_bg_edir_SHIFT 5 398 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 399 #define lpfc_wcqe_c_bg_edir_WORD parameter 400 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 401 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 402 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 403 #define lpfc_wcqe_c_bg_re_SHIFT 2 404 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 405 #define lpfc_wcqe_c_bg_re_WORD parameter 406 #define lpfc_wcqe_c_bg_ae_SHIFT 1 407 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 408 #define lpfc_wcqe_c_bg_ae_WORD parameter 409 #define lpfc_wcqe_c_bg_ge_SHIFT 0 410 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 411 #define lpfc_wcqe_c_bg_ge_WORD parameter 412 uint32_t word3; 413 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 414 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 415 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 416 #define lpfc_wcqe_c_xb_SHIFT 28 417 #define lpfc_wcqe_c_xb_MASK 0x00000001 418 #define lpfc_wcqe_c_xb_WORD word3 419 #define lpfc_wcqe_c_pv_SHIFT 27 420 #define lpfc_wcqe_c_pv_MASK 0x00000001 421 #define lpfc_wcqe_c_pv_WORD word3 422 #define lpfc_wcqe_c_priority_SHIFT 24 423 #define lpfc_wcqe_c_priority_MASK 0x00000007 424 #define lpfc_wcqe_c_priority_WORD word3 425 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 426 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 427 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 428 #define lpfc_wcqe_c_sqhead_SHIFT 0 429 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 430 #define lpfc_wcqe_c_sqhead_WORD word3 431 }; 432 433 /* completion queue entry for wqe release */ 434 struct lpfc_wcqe_release { 435 uint32_t reserved0; 436 uint32_t reserved1; 437 uint32_t word2; 438 #define lpfc_wcqe_r_wq_id_SHIFT 16 439 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 440 #define lpfc_wcqe_r_wq_id_WORD word2 441 #define lpfc_wcqe_r_wqe_index_SHIFT 0 442 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 443 #define lpfc_wcqe_r_wqe_index_WORD word2 444 uint32_t word3; 445 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 446 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 447 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 448 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 449 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 450 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 451 }; 452 453 struct sli4_wcqe_xri_aborted { 454 uint32_t word0; 455 #define lpfc_wcqe_xa_status_SHIFT 8 456 #define lpfc_wcqe_xa_status_MASK 0x000000FF 457 #define lpfc_wcqe_xa_status_WORD word0 458 uint32_t parameter; 459 uint32_t word2; 460 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 461 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 462 #define lpfc_wcqe_xa_remote_xid_WORD word2 463 #define lpfc_wcqe_xa_xri_SHIFT 0 464 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 465 #define lpfc_wcqe_xa_xri_WORD word2 466 uint32_t word3; 467 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 468 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 469 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 470 #define lpfc_wcqe_xa_ia_SHIFT 30 471 #define lpfc_wcqe_xa_ia_MASK 0x00000001 472 #define lpfc_wcqe_xa_ia_WORD word3 473 #define CQE_XRI_ABORTED_IA_REMOTE 0 474 #define CQE_XRI_ABORTED_IA_LOCAL 1 475 #define lpfc_wcqe_xa_br_SHIFT 29 476 #define lpfc_wcqe_xa_br_MASK 0x00000001 477 #define lpfc_wcqe_xa_br_WORD word3 478 #define CQE_XRI_ABORTED_BR_BA_ACC 0 479 #define CQE_XRI_ABORTED_BR_BA_RJT 1 480 #define lpfc_wcqe_xa_eo_SHIFT 28 481 #define lpfc_wcqe_xa_eo_MASK 0x00000001 482 #define lpfc_wcqe_xa_eo_WORD word3 483 #define CQE_XRI_ABORTED_EO_REMOTE 0 484 #define CQE_XRI_ABORTED_EO_LOCAL 1 485 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 486 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 487 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 488 }; 489 490 /* completion queue entry structure for rqe completion */ 491 struct lpfc_rcqe { 492 uint32_t word0; 493 #define lpfc_rcqe_bindex_SHIFT 16 494 #define lpfc_rcqe_bindex_MASK 0x0000FFF 495 #define lpfc_rcqe_bindex_WORD word0 496 #define lpfc_rcqe_status_SHIFT 8 497 #define lpfc_rcqe_status_MASK 0x000000FF 498 #define lpfc_rcqe_status_WORD word0 499 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 500 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 501 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 502 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 503 uint32_t word1; 504 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 505 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 506 #define lpfc_rcqe_fcf_id_v1_WORD word1 507 uint32_t word2; 508 #define lpfc_rcqe_length_SHIFT 16 509 #define lpfc_rcqe_length_MASK 0x0000FFFF 510 #define lpfc_rcqe_length_WORD word2 511 #define lpfc_rcqe_rq_id_SHIFT 6 512 #define lpfc_rcqe_rq_id_MASK 0x000003FF 513 #define lpfc_rcqe_rq_id_WORD word2 514 #define lpfc_rcqe_fcf_id_SHIFT 0 515 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 516 #define lpfc_rcqe_fcf_id_WORD word2 517 #define lpfc_rcqe_rq_id_v1_SHIFT 0 518 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 519 #define lpfc_rcqe_rq_id_v1_WORD word2 520 uint32_t word3; 521 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 522 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 523 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 524 #define lpfc_rcqe_port_SHIFT 30 525 #define lpfc_rcqe_port_MASK 0x00000001 526 #define lpfc_rcqe_port_WORD word3 527 #define lpfc_rcqe_hdr_length_SHIFT 24 528 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 529 #define lpfc_rcqe_hdr_length_WORD word3 530 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 531 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 532 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 533 #define lpfc_rcqe_eof_SHIFT 8 534 #define lpfc_rcqe_eof_MASK 0x000000FF 535 #define lpfc_rcqe_eof_WORD word3 536 #define FCOE_EOFn 0x41 537 #define FCOE_EOFt 0x42 538 #define FCOE_EOFni 0x49 539 #define FCOE_EOFa 0x50 540 #define lpfc_rcqe_sof_SHIFT 0 541 #define lpfc_rcqe_sof_MASK 0x000000FF 542 #define lpfc_rcqe_sof_WORD word3 543 #define FCOE_SOFi2 0x2d 544 #define FCOE_SOFi3 0x2e 545 #define FCOE_SOFn2 0x35 546 #define FCOE_SOFn3 0x36 547 }; 548 549 struct lpfc_rqe { 550 uint32_t address_hi; 551 uint32_t address_lo; 552 }; 553 554 /* buffer descriptors */ 555 struct lpfc_bde4 { 556 uint32_t addr_hi; 557 uint32_t addr_lo; 558 uint32_t word2; 559 #define lpfc_bde4_last_SHIFT 31 560 #define lpfc_bde4_last_MASK 0x00000001 561 #define lpfc_bde4_last_WORD word2 562 #define lpfc_bde4_sge_offset_SHIFT 0 563 #define lpfc_bde4_sge_offset_MASK 0x000003FF 564 #define lpfc_bde4_sge_offset_WORD word2 565 uint32_t word3; 566 #define lpfc_bde4_length_SHIFT 0 567 #define lpfc_bde4_length_MASK 0x000000FF 568 #define lpfc_bde4_length_WORD word3 569 }; 570 571 struct lpfc_register { 572 uint32_t word0; 573 }; 574 575 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 576 #define LPFC_PORT_SEM_MASK 0xF000 577 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 578 #define LPFC_UERR_STATUS_HI 0x00A4 579 #define LPFC_UERR_STATUS_LO 0x00A0 580 #define LPFC_UE_MASK_HI 0x00AC 581 #define LPFC_UE_MASK_LO 0x00A8 582 583 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 584 #define LPFC_SLI_INTF 0x0058 585 #define LPFC_SLI_ASIC_VER 0x009C 586 587 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 588 #define lpfc_port_smphr_perr_SHIFT 31 589 #define lpfc_port_smphr_perr_MASK 0x1 590 #define lpfc_port_smphr_perr_WORD word0 591 #define lpfc_port_smphr_sfi_SHIFT 30 592 #define lpfc_port_smphr_sfi_MASK 0x1 593 #define lpfc_port_smphr_sfi_WORD word0 594 #define lpfc_port_smphr_nip_SHIFT 29 595 #define lpfc_port_smphr_nip_MASK 0x1 596 #define lpfc_port_smphr_nip_WORD word0 597 #define lpfc_port_smphr_ipc_SHIFT 28 598 #define lpfc_port_smphr_ipc_MASK 0x1 599 #define lpfc_port_smphr_ipc_WORD word0 600 #define lpfc_port_smphr_scr1_SHIFT 27 601 #define lpfc_port_smphr_scr1_MASK 0x1 602 #define lpfc_port_smphr_scr1_WORD word0 603 #define lpfc_port_smphr_scr2_SHIFT 26 604 #define lpfc_port_smphr_scr2_MASK 0x1 605 #define lpfc_port_smphr_scr2_WORD word0 606 #define lpfc_port_smphr_host_scratch_SHIFT 16 607 #define lpfc_port_smphr_host_scratch_MASK 0xFF 608 #define lpfc_port_smphr_host_scratch_WORD word0 609 #define lpfc_port_smphr_port_status_SHIFT 0 610 #define lpfc_port_smphr_port_status_MASK 0xFFFF 611 #define lpfc_port_smphr_port_status_WORD word0 612 613 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 614 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 615 #define LPFC_POST_STAGE_HOST_RDY 0x0002 616 #define LPFC_POST_STAGE_BE_RESET 0x0003 617 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 618 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 619 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 620 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 621 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 622 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 623 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 624 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 625 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 626 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 627 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 628 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 629 #define LPFC_POST_STAGE_ARMFW_START 0x0800 630 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 631 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 632 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 633 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 634 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 635 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 636 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 637 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 638 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 639 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 640 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 641 #define LPFC_POST_STAGE_RC_DONE 0x0B07 642 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 643 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 644 #define LPFC_POST_STAGE_PORT_READY 0xC000 645 #define LPFC_POST_STAGE_PORT_UE 0xF000 646 647 #define LPFC_CTL_PORT_STA_OFFSET 0x404 648 #define lpfc_sliport_status_err_SHIFT 31 649 #define lpfc_sliport_status_err_MASK 0x1 650 #define lpfc_sliport_status_err_WORD word0 651 #define lpfc_sliport_status_end_SHIFT 30 652 #define lpfc_sliport_status_end_MASK 0x1 653 #define lpfc_sliport_status_end_WORD word0 654 #define lpfc_sliport_status_oti_SHIFT 29 655 #define lpfc_sliport_status_oti_MASK 0x1 656 #define lpfc_sliport_status_oti_WORD word0 657 #define lpfc_sliport_status_dip_SHIFT 25 658 #define lpfc_sliport_status_dip_MASK 0x1 659 #define lpfc_sliport_status_dip_WORD word0 660 #define lpfc_sliport_status_rn_SHIFT 24 661 #define lpfc_sliport_status_rn_MASK 0x1 662 #define lpfc_sliport_status_rn_WORD word0 663 #define lpfc_sliport_status_rdy_SHIFT 23 664 #define lpfc_sliport_status_rdy_MASK 0x1 665 #define lpfc_sliport_status_rdy_WORD word0 666 #define MAX_IF_TYPE_2_RESETS 6 667 668 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 669 #define lpfc_sliport_ctrl_end_SHIFT 30 670 #define lpfc_sliport_ctrl_end_MASK 0x1 671 #define lpfc_sliport_ctrl_end_WORD word0 672 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 673 #define LPFC_SLIPORT_BIG_ENDIAN 1 674 #define lpfc_sliport_ctrl_ip_SHIFT 27 675 #define lpfc_sliport_ctrl_ip_MASK 0x1 676 #define lpfc_sliport_ctrl_ip_WORD word0 677 #define LPFC_SLIPORT_INIT_PORT 1 678 679 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 680 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 681 682 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 683 #define lpfc_sliport_eqdelay_delay_SHIFT 16 684 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 685 #define lpfc_sliport_eqdelay_delay_WORD word0 686 #define lpfc_sliport_eqdelay_id_SHIFT 0 687 #define lpfc_sliport_eqdelay_id_MASK 0xfff 688 #define lpfc_sliport_eqdelay_id_WORD word0 689 #define LPFC_SEC_TO_USEC 1000000 690 691 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 692 * reside in BAR 2. 693 */ 694 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 695 696 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 697 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 698 699 #define LPFC_HST_ISR0 0x0C18 700 #define LPFC_HST_ISR1 0x0C1C 701 #define LPFC_HST_ISR2 0x0C20 702 #define LPFC_HST_ISR3 0x0C24 703 #define LPFC_HST_ISR4 0x0C28 704 705 #define LPFC_HST_IMR0 0x0C48 706 #define LPFC_HST_IMR1 0x0C4C 707 #define LPFC_HST_IMR2 0x0C50 708 #define LPFC_HST_IMR3 0x0C54 709 #define LPFC_HST_IMR4 0x0C58 710 711 #define LPFC_HST_ISCR0 0x0C78 712 #define LPFC_HST_ISCR1 0x0C7C 713 #define LPFC_HST_ISCR2 0x0C80 714 #define LPFC_HST_ISCR3 0x0C84 715 #define LPFC_HST_ISCR4 0x0C88 716 717 #define LPFC_SLI4_INTR0 BIT0 718 #define LPFC_SLI4_INTR1 BIT1 719 #define LPFC_SLI4_INTR2 BIT2 720 #define LPFC_SLI4_INTR3 BIT3 721 #define LPFC_SLI4_INTR4 BIT4 722 #define LPFC_SLI4_INTR5 BIT5 723 #define LPFC_SLI4_INTR6 BIT6 724 #define LPFC_SLI4_INTR7 BIT7 725 #define LPFC_SLI4_INTR8 BIT8 726 #define LPFC_SLI4_INTR9 BIT9 727 #define LPFC_SLI4_INTR10 BIT10 728 #define LPFC_SLI4_INTR11 BIT11 729 #define LPFC_SLI4_INTR12 BIT12 730 #define LPFC_SLI4_INTR13 BIT13 731 #define LPFC_SLI4_INTR14 BIT14 732 #define LPFC_SLI4_INTR15 BIT15 733 #define LPFC_SLI4_INTR16 BIT16 734 #define LPFC_SLI4_INTR17 BIT17 735 #define LPFC_SLI4_INTR18 BIT18 736 #define LPFC_SLI4_INTR19 BIT19 737 #define LPFC_SLI4_INTR20 BIT20 738 #define LPFC_SLI4_INTR21 BIT21 739 #define LPFC_SLI4_INTR22 BIT22 740 #define LPFC_SLI4_INTR23 BIT23 741 #define LPFC_SLI4_INTR24 BIT24 742 #define LPFC_SLI4_INTR25 BIT25 743 #define LPFC_SLI4_INTR26 BIT26 744 #define LPFC_SLI4_INTR27 BIT27 745 #define LPFC_SLI4_INTR28 BIT28 746 #define LPFC_SLI4_INTR29 BIT29 747 #define LPFC_SLI4_INTR30 BIT30 748 #define LPFC_SLI4_INTR31 BIT31 749 750 /* 751 * The Doorbell registers defined here exist in different BAR 752 * register sets depending on the UCNA Port's reported if_type 753 * value. For UCNA ports running SLI4 and if_type 0, they reside in 754 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 755 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 756 * BAR2. The offsets and base address are different, so the driver 757 * has to compute the register addresses accordingly 758 */ 759 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 760 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 761 #define LPFC_IF6_RQ_DOORBELL 0x0080 762 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 763 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 764 #define lpfc_rq_db_list_fm_num_posted_WORD word0 765 #define lpfc_rq_db_list_fm_index_SHIFT 16 766 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 767 #define lpfc_rq_db_list_fm_index_WORD word0 768 #define lpfc_rq_db_list_fm_id_SHIFT 0 769 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 770 #define lpfc_rq_db_list_fm_id_WORD word0 771 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 772 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 773 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 774 #define lpfc_rq_db_ring_fm_id_SHIFT 0 775 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 776 #define lpfc_rq_db_ring_fm_id_WORD word0 777 778 #define LPFC_ULP0_WQ_DOORBELL 0x0040 779 #define LPFC_ULP1_WQ_DOORBELL 0x0060 780 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 781 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 782 #define lpfc_wq_db_list_fm_num_posted_WORD word0 783 #define lpfc_wq_db_list_fm_index_SHIFT 16 784 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 785 #define lpfc_wq_db_list_fm_index_WORD word0 786 #define lpfc_wq_db_list_fm_id_SHIFT 0 787 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 788 #define lpfc_wq_db_list_fm_id_WORD word0 789 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 790 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 791 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 792 #define lpfc_wq_db_ring_fm_id_SHIFT 0 793 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 794 #define lpfc_wq_db_ring_fm_id_WORD word0 795 796 #define LPFC_IF6_WQ_DOORBELL 0x0040 797 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 798 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 799 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 800 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 801 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 802 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 803 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 804 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 805 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 806 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 807 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 808 #define lpfc_if6_wq_db_list_fm_id_WORD word0 809 810 #define LPFC_EQCQ_DOORBELL 0x0120 811 #define lpfc_eqcq_doorbell_se_SHIFT 31 812 #define lpfc_eqcq_doorbell_se_MASK 0x0001 813 #define lpfc_eqcq_doorbell_se_WORD word0 814 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 815 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 816 #define lpfc_eqcq_doorbell_arm_SHIFT 29 817 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 818 #define lpfc_eqcq_doorbell_arm_WORD word0 819 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 820 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 821 #define lpfc_eqcq_doorbell_num_released_WORD word0 822 #define lpfc_eqcq_doorbell_qt_SHIFT 10 823 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 824 #define lpfc_eqcq_doorbell_qt_WORD word0 825 #define LPFC_QUEUE_TYPE_COMPLETION 0 826 #define LPFC_QUEUE_TYPE_EVENT 1 827 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 828 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 829 #define lpfc_eqcq_doorbell_eqci_WORD word0 830 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 831 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 832 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 833 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 834 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 835 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 836 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 837 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 838 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 839 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 840 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 841 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 842 #define LPFC_CQID_HI_FIELD_SHIFT 10 843 #define LPFC_EQID_HI_FIELD_SHIFT 9 844 845 #define LPFC_IF6_CQ_DOORBELL 0x00C0 846 #define lpfc_if6_cq_doorbell_se_SHIFT 31 847 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 848 #define lpfc_if6_cq_doorbell_se_WORD word0 849 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 850 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 851 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 852 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 853 #define lpfc_if6_cq_doorbell_arm_WORD word0 854 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 855 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 856 #define lpfc_if6_cq_doorbell_num_released_WORD word0 857 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 858 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 859 #define lpfc_if6_cq_doorbell_cqid_WORD word0 860 861 #define LPFC_IF6_EQ_DOORBELL 0x0120 862 #define lpfc_if6_eq_doorbell_io_SHIFT 31 863 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 864 #define lpfc_if6_eq_doorbell_io_WORD word0 865 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 866 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 867 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 868 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 869 #define lpfc_if6_eq_doorbell_arm_WORD word0 870 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 871 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 872 #define lpfc_if6_eq_doorbell_num_released_WORD word0 873 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 874 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 875 #define lpfc_if6_eq_doorbell_eqid_WORD word0 876 877 #define LPFC_BMBX 0x0160 878 #define lpfc_bmbx_addr_SHIFT 2 879 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 880 #define lpfc_bmbx_addr_WORD word0 881 #define lpfc_bmbx_hi_SHIFT 1 882 #define lpfc_bmbx_hi_MASK 0x0001 883 #define lpfc_bmbx_hi_WORD word0 884 #define lpfc_bmbx_rdy_SHIFT 0 885 #define lpfc_bmbx_rdy_MASK 0x0001 886 #define lpfc_bmbx_rdy_WORD word0 887 888 #define LPFC_MQ_DOORBELL 0x0140 889 #define LPFC_IF6_MQ_DOORBELL 0x0160 890 #define lpfc_mq_doorbell_num_posted_SHIFT 16 891 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 892 #define lpfc_mq_doorbell_num_posted_WORD word0 893 #define lpfc_mq_doorbell_id_SHIFT 0 894 #define lpfc_mq_doorbell_id_MASK 0xFFFF 895 #define lpfc_mq_doorbell_id_WORD word0 896 897 struct lpfc_sli4_cfg_mhdr { 898 uint32_t word1; 899 #define lpfc_mbox_hdr_emb_SHIFT 0 900 #define lpfc_mbox_hdr_emb_MASK 0x00000001 901 #define lpfc_mbox_hdr_emb_WORD word1 902 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 903 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 904 #define lpfc_mbox_hdr_sge_cnt_WORD word1 905 uint32_t payload_length; 906 uint32_t tag_lo; 907 uint32_t tag_hi; 908 uint32_t reserved5; 909 }; 910 911 union lpfc_sli4_cfg_shdr { 912 struct { 913 uint32_t word6; 914 #define lpfc_mbox_hdr_opcode_SHIFT 0 915 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 916 #define lpfc_mbox_hdr_opcode_WORD word6 917 #define lpfc_mbox_hdr_subsystem_SHIFT 8 918 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 919 #define lpfc_mbox_hdr_subsystem_WORD word6 920 #define lpfc_mbox_hdr_port_number_SHIFT 16 921 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 922 #define lpfc_mbox_hdr_port_number_WORD word6 923 #define lpfc_mbox_hdr_domain_SHIFT 24 924 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 925 #define lpfc_mbox_hdr_domain_WORD word6 926 uint32_t timeout; 927 uint32_t request_length; 928 uint32_t word9; 929 #define lpfc_mbox_hdr_version_SHIFT 0 930 #define lpfc_mbox_hdr_version_MASK 0x000000FF 931 #define lpfc_mbox_hdr_version_WORD word9 932 #define lpfc_mbox_hdr_pf_num_SHIFT 16 933 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 934 #define lpfc_mbox_hdr_pf_num_WORD word9 935 #define lpfc_mbox_hdr_vh_num_SHIFT 24 936 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 937 #define lpfc_mbox_hdr_vh_num_WORD word9 938 #define LPFC_Q_CREATE_VERSION_2 2 939 #define LPFC_Q_CREATE_VERSION_1 1 940 #define LPFC_Q_CREATE_VERSION_0 0 941 #define LPFC_OPCODE_VERSION_0 0 942 #define LPFC_OPCODE_VERSION_1 1 943 } request; 944 struct { 945 uint32_t word6; 946 #define lpfc_mbox_hdr_opcode_SHIFT 0 947 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 948 #define lpfc_mbox_hdr_opcode_WORD word6 949 #define lpfc_mbox_hdr_subsystem_SHIFT 8 950 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 951 #define lpfc_mbox_hdr_subsystem_WORD word6 952 #define lpfc_mbox_hdr_domain_SHIFT 24 953 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 954 #define lpfc_mbox_hdr_domain_WORD word6 955 uint32_t word7; 956 #define lpfc_mbox_hdr_status_SHIFT 0 957 #define lpfc_mbox_hdr_status_MASK 0x000000FF 958 #define lpfc_mbox_hdr_status_WORD word7 959 #define lpfc_mbox_hdr_add_status_SHIFT 8 960 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 961 #define lpfc_mbox_hdr_add_status_WORD word7 962 uint32_t response_length; 963 uint32_t actual_response_length; 964 } response; 965 }; 966 967 /* Mailbox Header structures. 968 * struct mbox_header is defined for first generation SLI4_CFG mailbox 969 * calls deployed for BE-based ports. 970 * 971 * struct sli4_mbox_header is defined for second generation SLI4 972 * ports that don't deploy the SLI4_CFG mechanism. 973 */ 974 struct mbox_header { 975 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 976 union lpfc_sli4_cfg_shdr cfg_shdr; 977 }; 978 979 #define LPFC_EXTENT_LOCAL 0 980 #define LPFC_TIMEOUT_DEFAULT 0 981 #define LPFC_EXTENT_VERSION_DEFAULT 0 982 983 /* Subsystem Definitions */ 984 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 985 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 986 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 987 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 988 989 /* Device Specific Definitions */ 990 991 /* The HOST ENDIAN defines are in Big Endian format. */ 992 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 993 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 994 995 /* Common Opcodes */ 996 #define LPFC_MBOX_OPCODE_NA 0x00 997 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 998 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 999 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1000 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1001 #define LPFC_MBOX_OPCODE_NOP 0x21 1002 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1003 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1004 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1005 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1006 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1007 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1008 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1009 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1010 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1011 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1012 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1013 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1014 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1015 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1016 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1017 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1018 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1019 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1020 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1021 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1022 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1023 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1024 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1025 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1026 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1027 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1028 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1029 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1030 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1031 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1032 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1033 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1034 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1035 1036 /* FCoE Opcodes */ 1037 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1038 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1039 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1040 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1041 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1042 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1043 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1044 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1045 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1046 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1047 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1048 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1049 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1050 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1051 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1052 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1053 1054 /* Low level Opcodes */ 1055 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1056 1057 /* Mailbox command structures */ 1058 struct eq_context { 1059 uint32_t word0; 1060 #define lpfc_eq_context_size_SHIFT 31 1061 #define lpfc_eq_context_size_MASK 0x00000001 1062 #define lpfc_eq_context_size_WORD word0 1063 #define LPFC_EQE_SIZE_4 0x0 1064 #define LPFC_EQE_SIZE_16 0x1 1065 #define lpfc_eq_context_valid_SHIFT 29 1066 #define lpfc_eq_context_valid_MASK 0x00000001 1067 #define lpfc_eq_context_valid_WORD word0 1068 #define lpfc_eq_context_autovalid_SHIFT 28 1069 #define lpfc_eq_context_autovalid_MASK 0x00000001 1070 #define lpfc_eq_context_autovalid_WORD word0 1071 uint32_t word1; 1072 #define lpfc_eq_context_count_SHIFT 26 1073 #define lpfc_eq_context_count_MASK 0x00000003 1074 #define lpfc_eq_context_count_WORD word1 1075 #define LPFC_EQ_CNT_256 0x0 1076 #define LPFC_EQ_CNT_512 0x1 1077 #define LPFC_EQ_CNT_1024 0x2 1078 #define LPFC_EQ_CNT_2048 0x3 1079 #define LPFC_EQ_CNT_4096 0x4 1080 uint32_t word2; 1081 #define lpfc_eq_context_delay_multi_SHIFT 13 1082 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1083 #define lpfc_eq_context_delay_multi_WORD word2 1084 uint32_t reserved3; 1085 }; 1086 1087 struct eq_delay_info { 1088 uint32_t eq_id; 1089 uint32_t phase; 1090 uint32_t delay_multi; 1091 }; 1092 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1093 1094 struct sgl_page_pairs { 1095 uint32_t sgl_pg0_addr_lo; 1096 uint32_t sgl_pg0_addr_hi; 1097 uint32_t sgl_pg1_addr_lo; 1098 uint32_t sgl_pg1_addr_hi; 1099 }; 1100 1101 struct lpfc_mbx_post_sgl_pages { 1102 struct mbox_header header; 1103 uint32_t word0; 1104 #define lpfc_post_sgl_pages_xri_SHIFT 0 1105 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1106 #define lpfc_post_sgl_pages_xri_WORD word0 1107 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1108 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1109 #define lpfc_post_sgl_pages_xricnt_WORD word0 1110 struct sgl_page_pairs sgl_pg_pairs[1]; 1111 }; 1112 1113 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1114 struct lpfc_mbx_post_uembed_sgl_page1 { 1115 union lpfc_sli4_cfg_shdr cfg_shdr; 1116 uint32_t word0; 1117 struct sgl_page_pairs sgl_pg_pairs; 1118 }; 1119 1120 struct lpfc_mbx_sge { 1121 uint32_t pa_lo; 1122 uint32_t pa_hi; 1123 uint32_t length; 1124 }; 1125 1126 struct lpfc_mbx_nembed_cmd { 1127 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1128 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1129 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1130 }; 1131 1132 struct lpfc_mbx_nembed_sge_virt { 1133 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1134 }; 1135 1136 struct lpfc_mbx_eq_create { 1137 struct mbox_header header; 1138 union { 1139 struct { 1140 uint32_t word0; 1141 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1142 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1143 #define lpfc_mbx_eq_create_num_pages_WORD word0 1144 struct eq_context context; 1145 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1146 } request; 1147 struct { 1148 uint32_t word0; 1149 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1150 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1151 #define lpfc_mbx_eq_create_q_id_WORD word0 1152 } response; 1153 } u; 1154 }; 1155 1156 struct lpfc_mbx_modify_eq_delay { 1157 struct mbox_header header; 1158 union { 1159 struct { 1160 uint32_t num_eq; 1161 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1162 } request; 1163 struct { 1164 uint32_t word0; 1165 } response; 1166 } u; 1167 }; 1168 1169 struct lpfc_mbx_eq_destroy { 1170 struct mbox_header header; 1171 union { 1172 struct { 1173 uint32_t word0; 1174 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1175 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1176 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1177 } request; 1178 struct { 1179 uint32_t word0; 1180 } response; 1181 } u; 1182 }; 1183 1184 struct lpfc_mbx_nop { 1185 struct mbox_header header; 1186 uint32_t context[2]; 1187 }; 1188 1189 1190 1191 struct lpfc_mbx_set_ras_fwlog { 1192 struct mbox_header header; 1193 union { 1194 struct { 1195 uint32_t word4; 1196 #define lpfc_fwlog_enable_SHIFT 0 1197 #define lpfc_fwlog_enable_MASK 0x00000001 1198 #define lpfc_fwlog_enable_WORD word4 1199 #define lpfc_fwlog_loglvl_SHIFT 8 1200 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1201 #define lpfc_fwlog_loglvl_WORD word4 1202 #define lpfc_fwlog_ra_SHIFT 15 1203 #define lpfc_fwlog_ra_WORD 0x00000008 1204 #define lpfc_fwlog_buffcnt_SHIFT 16 1205 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1206 #define lpfc_fwlog_buffcnt_WORD word4 1207 #define lpfc_fwlog_buffsz_SHIFT 24 1208 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1209 #define lpfc_fwlog_buffsz_WORD word4 1210 uint32_t word5; 1211 #define lpfc_fwlog_acqe_SHIFT 0 1212 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1213 #define lpfc_fwlog_acqe_WORD word5 1214 #define lpfc_fwlog_cqid_SHIFT 16 1215 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1216 #define lpfc_fwlog_cqid_WORD word5 1217 #define LPFC_MAX_FWLOG_PAGE 16 1218 struct dma_address lwpd; 1219 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1220 } request; 1221 struct { 1222 uint32_t word0; 1223 } response; 1224 } u; 1225 }; 1226 1227 1228 struct cq_context { 1229 uint32_t word0; 1230 #define lpfc_cq_context_event_SHIFT 31 1231 #define lpfc_cq_context_event_MASK 0x00000001 1232 #define lpfc_cq_context_event_WORD word0 1233 #define lpfc_cq_context_valid_SHIFT 29 1234 #define lpfc_cq_context_valid_MASK 0x00000001 1235 #define lpfc_cq_context_valid_WORD word0 1236 #define lpfc_cq_context_count_SHIFT 27 1237 #define lpfc_cq_context_count_MASK 0x00000003 1238 #define lpfc_cq_context_count_WORD word0 1239 #define LPFC_CQ_CNT_256 0x0 1240 #define LPFC_CQ_CNT_512 0x1 1241 #define LPFC_CQ_CNT_1024 0x2 1242 #define LPFC_CQ_CNT_WORD7 0x3 1243 #define lpfc_cq_context_autovalid_SHIFT 15 1244 #define lpfc_cq_context_autovalid_MASK 0x00000001 1245 #define lpfc_cq_context_autovalid_WORD word0 1246 uint32_t word1; 1247 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1248 #define lpfc_cq_eq_id_MASK 0x000000FF 1249 #define lpfc_cq_eq_id_WORD word1 1250 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1251 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1252 #define lpfc_cq_eq_id_2_WORD word1 1253 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1254 uint32_t reserved1; 1255 }; 1256 1257 struct lpfc_mbx_cq_create { 1258 struct mbox_header header; 1259 union { 1260 struct { 1261 uint32_t word0; 1262 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1263 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1264 #define lpfc_mbx_cq_create_page_size_WORD word0 1265 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1266 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1267 #define lpfc_mbx_cq_create_num_pages_WORD word0 1268 struct cq_context context; 1269 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1270 } request; 1271 struct { 1272 uint32_t word0; 1273 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1274 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1275 #define lpfc_mbx_cq_create_q_id_WORD word0 1276 } response; 1277 } u; 1278 }; 1279 1280 struct lpfc_mbx_cq_create_set { 1281 union lpfc_sli4_cfg_shdr cfg_shdr; 1282 union { 1283 struct { 1284 uint32_t word0; 1285 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1286 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1287 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1288 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1289 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1290 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1291 uint32_t word1; 1292 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1293 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1294 #define lpfc_mbx_cq_create_set_evt_WORD word1 1295 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1296 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1297 #define lpfc_mbx_cq_create_set_valid_WORD word1 1298 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1299 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1300 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1301 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1302 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1303 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1304 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1305 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1306 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1307 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1308 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1309 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1310 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1311 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1312 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1313 uint32_t word2; 1314 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1315 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1316 #define lpfc_mbx_cq_create_set_arm_WORD word2 1317 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1318 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1319 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1320 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1321 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1322 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1323 uint32_t word3; 1324 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1325 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1326 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1327 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1328 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1329 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1330 uint32_t word4; 1331 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1332 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1333 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1334 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1335 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1336 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1337 uint32_t word5; 1338 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1339 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1340 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1341 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1342 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1343 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1344 uint32_t word6; 1345 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1346 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1347 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1348 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1349 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1350 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1351 uint32_t word7; 1352 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1353 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1354 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1355 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1356 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1357 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1358 uint32_t word8; 1359 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1360 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1361 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1362 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1363 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1364 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1365 uint32_t word9; 1366 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1367 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1368 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1369 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1370 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1371 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1372 uint32_t word10; 1373 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1374 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1375 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1376 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1377 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1378 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1379 struct dma_address page[1]; 1380 } request; 1381 struct { 1382 uint32_t word0; 1383 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1384 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1385 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1386 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1387 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1388 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1389 } response; 1390 } u; 1391 }; 1392 1393 struct lpfc_mbx_cq_destroy { 1394 struct mbox_header header; 1395 union { 1396 struct { 1397 uint32_t word0; 1398 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1399 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1400 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1401 } request; 1402 struct { 1403 uint32_t word0; 1404 } response; 1405 } u; 1406 }; 1407 1408 struct wq_context { 1409 uint32_t reserved0; 1410 uint32_t reserved1; 1411 uint32_t reserved2; 1412 uint32_t reserved3; 1413 }; 1414 1415 struct lpfc_mbx_wq_create { 1416 struct mbox_header header; 1417 union { 1418 struct { /* Version 0 Request */ 1419 uint32_t word0; 1420 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1421 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1422 #define lpfc_mbx_wq_create_num_pages_WORD word0 1423 #define lpfc_mbx_wq_create_dua_SHIFT 8 1424 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1425 #define lpfc_mbx_wq_create_dua_WORD word0 1426 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1427 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1428 #define lpfc_mbx_wq_create_cq_id_WORD word0 1429 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1430 uint32_t word9; 1431 #define lpfc_mbx_wq_create_bua_SHIFT 0 1432 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1433 #define lpfc_mbx_wq_create_bua_WORD word9 1434 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1435 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1436 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1437 } request; 1438 struct { /* Version 1 Request */ 1439 uint32_t word0; /* Word 0 is the same as in v0 */ 1440 uint32_t word1; 1441 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1442 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1443 #define lpfc_mbx_wq_create_page_size_WORD word1 1444 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1445 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1446 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1447 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1448 #define lpfc_mbx_wq_create_doe_SHIFT 14 1449 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1450 #define lpfc_mbx_wq_create_doe_WORD word1 1451 #define lpfc_mbx_wq_create_toe_SHIFT 13 1452 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1453 #define lpfc_mbx_wq_create_toe_WORD word1 1454 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1455 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1456 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1457 #define LPFC_WQ_WQE_SIZE_64 0x5 1458 #define LPFC_WQ_WQE_SIZE_128 0x6 1459 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1460 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1461 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1462 uint32_t word2; 1463 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1464 } request_1; 1465 struct { 1466 uint32_t word0; 1467 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1468 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1469 #define lpfc_mbx_wq_create_q_id_WORD word0 1470 uint32_t doorbell_offset; 1471 uint32_t word2; 1472 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1473 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1474 #define lpfc_mbx_wq_create_bar_set_WORD word2 1475 #define WQ_PCI_BAR_0_AND_1 0x00 1476 #define WQ_PCI_BAR_2_AND_3 0x01 1477 #define WQ_PCI_BAR_4_AND_5 0x02 1478 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1479 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1480 #define lpfc_mbx_wq_create_db_format_WORD word2 1481 } response; 1482 struct { 1483 uint32_t word0; 1484 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1485 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1486 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1487 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1488 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1489 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1490 uint32_t word1; 1491 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1492 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1493 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1494 uint32_t doorbell_offset; 1495 uint32_t word3; 1496 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1497 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1498 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1499 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1500 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1501 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1502 uint32_t dpp_offset; 1503 } response_1; 1504 } u; 1505 }; 1506 1507 struct lpfc_mbx_wq_destroy { 1508 struct mbox_header header; 1509 union { 1510 struct { 1511 uint32_t word0; 1512 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1513 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1514 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1515 } request; 1516 struct { 1517 uint32_t word0; 1518 } response; 1519 } u; 1520 }; 1521 1522 #define LPFC_HDR_BUF_SIZE 128 1523 #define LPFC_DATA_BUF_SIZE 2048 1524 #define LPFC_NVMET_DATA_BUF_SIZE 128 1525 struct rq_context { 1526 uint32_t word0; 1527 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1528 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1529 #define lpfc_rq_context_rqe_count_WORD word0 1530 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1531 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1532 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1533 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1534 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1535 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1536 #define lpfc_rq_context_rqe_count_1_WORD word0 1537 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1538 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1539 #define lpfc_rq_context_rqe_size_WORD word0 1540 #define LPFC_RQE_SIZE_8 2 1541 #define LPFC_RQE_SIZE_16 3 1542 #define LPFC_RQE_SIZE_32 4 1543 #define LPFC_RQE_SIZE_64 5 1544 #define LPFC_RQE_SIZE_128 6 1545 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1546 #define lpfc_rq_context_page_size_MASK 0x000000FF 1547 #define lpfc_rq_context_page_size_WORD word0 1548 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1549 uint32_t word1; 1550 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1551 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1552 #define lpfc_rq_context_data_size_WORD word1 1553 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1554 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1555 #define lpfc_rq_context_hdr_size_WORD word1 1556 uint32_t word2; 1557 #define lpfc_rq_context_cq_id_SHIFT 16 1558 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1559 #define lpfc_rq_context_cq_id_WORD word2 1560 #define lpfc_rq_context_buf_size_SHIFT 0 1561 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1562 #define lpfc_rq_context_buf_size_WORD word2 1563 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1564 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1565 #define lpfc_rq_context_base_cq_WORD word2 1566 uint32_t buffer_size; /* Version 1 Only */ 1567 }; 1568 1569 struct lpfc_mbx_rq_create { 1570 struct mbox_header header; 1571 union { 1572 struct { 1573 uint32_t word0; 1574 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1575 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1576 #define lpfc_mbx_rq_create_num_pages_WORD word0 1577 #define lpfc_mbx_rq_create_dua_SHIFT 16 1578 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1579 #define lpfc_mbx_rq_create_dua_WORD word0 1580 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1581 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1582 #define lpfc_mbx_rq_create_bqu_WORD word0 1583 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1584 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1585 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1586 struct rq_context context; 1587 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1588 } request; 1589 struct { 1590 uint32_t word0; 1591 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1592 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1593 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1594 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1595 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1596 #define lpfc_mbx_rq_create_q_id_WORD word0 1597 uint32_t doorbell_offset; 1598 uint32_t word2; 1599 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1600 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1601 #define lpfc_mbx_rq_create_bar_set_WORD word2 1602 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1603 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1604 #define lpfc_mbx_rq_create_db_format_WORD word2 1605 } response; 1606 } u; 1607 }; 1608 1609 struct lpfc_mbx_rq_create_v2 { 1610 union lpfc_sli4_cfg_shdr cfg_shdr; 1611 union { 1612 struct { 1613 uint32_t word0; 1614 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1615 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1616 #define lpfc_mbx_rq_create_num_pages_WORD word0 1617 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1618 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1619 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1620 #define lpfc_mbx_rq_create_dua_SHIFT 16 1621 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1622 #define lpfc_mbx_rq_create_dua_WORD word0 1623 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1624 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1625 #define lpfc_mbx_rq_create_bqu_WORD word0 1626 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1627 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1628 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1629 #define lpfc_mbx_rq_create_dim_SHIFT 29 1630 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1631 #define lpfc_mbx_rq_create_dim_WORD word0 1632 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1633 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1634 #define lpfc_mbx_rq_create_dfd_WORD word0 1635 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1636 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1637 #define lpfc_mbx_rq_create_dnb_WORD word0 1638 struct rq_context context; 1639 struct dma_address page[1]; 1640 } request; 1641 struct { 1642 uint32_t word0; 1643 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1644 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1645 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1646 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1647 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1648 #define lpfc_mbx_rq_create_q_id_WORD word0 1649 uint32_t doorbell_offset; 1650 uint32_t word2; 1651 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1652 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1653 #define lpfc_mbx_rq_create_bar_set_WORD word2 1654 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1655 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1656 #define lpfc_mbx_rq_create_db_format_WORD word2 1657 } response; 1658 } u; 1659 }; 1660 1661 struct lpfc_mbx_rq_destroy { 1662 struct mbox_header header; 1663 union { 1664 struct { 1665 uint32_t word0; 1666 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1667 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1668 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1669 } request; 1670 struct { 1671 uint32_t word0; 1672 } response; 1673 } u; 1674 }; 1675 1676 struct mq_context { 1677 uint32_t word0; 1678 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1679 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1680 #define lpfc_mq_context_cq_id_WORD word0 1681 #define lpfc_mq_context_ring_size_SHIFT 16 1682 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1683 #define lpfc_mq_context_ring_size_WORD word0 1684 #define LPFC_MQ_RING_SIZE_16 0x5 1685 #define LPFC_MQ_RING_SIZE_32 0x6 1686 #define LPFC_MQ_RING_SIZE_64 0x7 1687 #define LPFC_MQ_RING_SIZE_128 0x8 1688 uint32_t word1; 1689 #define lpfc_mq_context_valid_SHIFT 31 1690 #define lpfc_mq_context_valid_MASK 0x00000001 1691 #define lpfc_mq_context_valid_WORD word1 1692 uint32_t reserved2; 1693 uint32_t reserved3; 1694 }; 1695 1696 struct lpfc_mbx_mq_create { 1697 struct mbox_header header; 1698 union { 1699 struct { 1700 uint32_t word0; 1701 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1702 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1703 #define lpfc_mbx_mq_create_num_pages_WORD word0 1704 struct mq_context context; 1705 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1706 } request; 1707 struct { 1708 uint32_t word0; 1709 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1710 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1711 #define lpfc_mbx_mq_create_q_id_WORD word0 1712 } response; 1713 } u; 1714 }; 1715 1716 struct lpfc_mbx_mq_create_ext { 1717 struct mbox_header header; 1718 union { 1719 struct { 1720 uint32_t word0; 1721 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1722 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1723 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1724 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1725 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1726 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1727 uint32_t async_evt_bmap; 1728 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1729 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1730 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1731 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1732 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1733 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1734 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1735 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1736 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1737 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1738 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1739 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1740 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1741 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1742 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1743 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1744 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1745 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1746 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1747 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1748 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1749 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1750 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1751 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1752 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1753 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1754 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1755 struct mq_context context; 1756 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1757 } request; 1758 struct { 1759 uint32_t word0; 1760 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1761 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1762 #define lpfc_mbx_mq_create_q_id_WORD word0 1763 } response; 1764 } u; 1765 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1766 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1767 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1768 }; 1769 1770 struct lpfc_mbx_mq_destroy { 1771 struct mbox_header header; 1772 union { 1773 struct { 1774 uint32_t word0; 1775 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1776 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1777 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1778 } request; 1779 struct { 1780 uint32_t word0; 1781 } response; 1782 } u; 1783 }; 1784 1785 /* Start Gen 2 SLI4 Mailbox definitions: */ 1786 1787 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1788 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1789 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1790 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1791 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1792 1793 struct lpfc_mbx_get_rsrc_extent_info { 1794 struct mbox_header header; 1795 union { 1796 struct { 1797 uint32_t word4; 1798 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1799 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1800 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1801 } req; 1802 struct { 1803 uint32_t word4; 1804 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1805 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1806 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1807 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1808 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1809 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1810 } rsp; 1811 } u; 1812 }; 1813 1814 struct lpfc_mbx_query_fw_config { 1815 struct mbox_header header; 1816 struct { 1817 uint32_t config_number; 1818 #define LPFC_FC_FCOE 0x00000007 1819 uint32_t asic_revision; 1820 uint32_t physical_port; 1821 uint32_t function_mode; 1822 #define LPFC_FCOE_INI_MODE 0x00000040 1823 #define LPFC_FCOE_TGT_MODE 0x00000080 1824 #define LPFC_DUA_MODE 0x00000800 1825 uint32_t ulp0_mode; 1826 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1827 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1828 uint32_t ulp0_nap_words[12]; 1829 uint32_t ulp1_mode; 1830 uint32_t ulp1_nap_words[12]; 1831 uint32_t function_capabilities; 1832 uint32_t cqid_base; 1833 uint32_t cqid_tot; 1834 uint32_t eqid_base; 1835 uint32_t eqid_tot; 1836 uint32_t ulp0_nap2_words[2]; 1837 uint32_t ulp1_nap2_words[2]; 1838 } rsp; 1839 }; 1840 1841 struct lpfc_mbx_set_beacon_config { 1842 struct mbox_header header; 1843 uint32_t word4; 1844 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1845 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1846 #define lpfc_mbx_set_beacon_port_num_WORD word4 1847 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1848 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1849 #define lpfc_mbx_set_beacon_port_type_WORD word4 1850 #define lpfc_mbx_set_beacon_state_SHIFT 8 1851 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1852 #define lpfc_mbx_set_beacon_state_WORD word4 1853 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1854 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1855 #define lpfc_mbx_set_beacon_duration_WORD word4 1856 1857 /* COMMON_SET_BEACON_CONFIG_V1 */ 1858 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1859 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1860 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1861 uint32_t word5; /* RESERVED */ 1862 }; 1863 1864 struct lpfc_id_range { 1865 uint32_t word5; 1866 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1867 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1868 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1869 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1870 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1871 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1872 }; 1873 1874 struct lpfc_mbx_set_link_diag_state { 1875 struct mbox_header header; 1876 union { 1877 struct { 1878 uint32_t word0; 1879 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1880 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1881 #define lpfc_mbx_set_diag_state_diag_WORD word0 1882 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1883 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1884 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1885 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1886 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1887 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1888 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1889 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1890 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1891 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1892 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1893 } req; 1894 struct { 1895 uint32_t word0; 1896 } rsp; 1897 } u; 1898 }; 1899 1900 struct lpfc_mbx_set_link_diag_loopback { 1901 struct mbox_header header; 1902 union { 1903 struct { 1904 uint32_t word0; 1905 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1906 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1907 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1908 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1909 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1910 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1911 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 1912 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1913 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1914 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1915 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1916 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1917 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1918 } req; 1919 struct { 1920 uint32_t word0; 1921 } rsp; 1922 } u; 1923 }; 1924 1925 struct lpfc_mbx_run_link_diag_test { 1926 struct mbox_header header; 1927 union { 1928 struct { 1929 uint32_t word0; 1930 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1931 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1932 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1933 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1934 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1935 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1936 uint32_t word1; 1937 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1938 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1939 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1940 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1941 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1942 #define lpfc_mbx_run_diag_test_loops_WORD word1 1943 uint32_t word2; 1944 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1945 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1946 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1947 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1948 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1949 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1950 } req; 1951 struct { 1952 uint32_t word0; 1953 } rsp; 1954 } u; 1955 }; 1956 1957 /* 1958 * struct lpfc_mbx_alloc_rsrc_extents: 1959 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1960 * 6 words of header + 4 words of shared subcommand header + 1961 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1962 * 1963 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1964 * for extents payload. 1965 * 1966 * 212/2 (bytes per extent) = 106 extents. 1967 * 106/2 (extents per word) = 53 words. 1968 * lpfc_id_range id is statically size to 53. 1969 * 1970 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1971 * extent ranges. For ALLOC, the type and cnt are required. 1972 * For GET_ALLOCATED, only the type is required. 1973 */ 1974 struct lpfc_mbx_alloc_rsrc_extents { 1975 struct mbox_header header; 1976 union { 1977 struct { 1978 uint32_t word4; 1979 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1980 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1981 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1982 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1983 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1984 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1985 } req; 1986 struct { 1987 uint32_t word4; 1988 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1989 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1990 #define lpfc_mbx_rsrc_cnt_WORD word4 1991 struct lpfc_id_range id[53]; 1992 } rsp; 1993 } u; 1994 }; 1995 1996 /* 1997 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1998 * structure shares the same SHIFT/MASK/WORD defines provided in the 1999 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2000 * the structures defined above. This non-embedded structure provides for the 2001 * maximum number of extents supported by the port. 2002 */ 2003 struct lpfc_mbx_nembed_rsrc_extent { 2004 union lpfc_sli4_cfg_shdr cfg_shdr; 2005 uint32_t word4; 2006 struct lpfc_id_range id; 2007 }; 2008 2009 struct lpfc_mbx_dealloc_rsrc_extents { 2010 struct mbox_header header; 2011 struct { 2012 uint32_t word4; 2013 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2014 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2015 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2016 } req; 2017 2018 }; 2019 2020 /* Start SLI4 FCoE specific mbox structures. */ 2021 2022 struct lpfc_mbx_post_hdr_tmpl { 2023 struct mbox_header header; 2024 uint32_t word10; 2025 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2026 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2027 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2028 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2029 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2030 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2031 uint32_t rpi_paddr_lo; 2032 uint32_t rpi_paddr_hi; 2033 }; 2034 2035 struct sli4_sge { /* SLI-4 */ 2036 uint32_t addr_hi; 2037 uint32_t addr_lo; 2038 2039 uint32_t word2; 2040 #define lpfc_sli4_sge_offset_SHIFT 0 2041 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2042 #define lpfc_sli4_sge_offset_WORD word2 2043 #define lpfc_sli4_sge_type_SHIFT 27 2044 #define lpfc_sli4_sge_type_MASK 0x0000000F 2045 #define lpfc_sli4_sge_type_WORD word2 2046 #define LPFC_SGE_TYPE_DATA 0x0 2047 #define LPFC_SGE_TYPE_DIF 0x4 2048 #define LPFC_SGE_TYPE_LSP 0x5 2049 #define LPFC_SGE_TYPE_PEDIF 0x6 2050 #define LPFC_SGE_TYPE_PESEED 0x7 2051 #define LPFC_SGE_TYPE_DISEED 0x8 2052 #define LPFC_SGE_TYPE_ENC 0x9 2053 #define LPFC_SGE_TYPE_ATM 0xA 2054 #define LPFC_SGE_TYPE_SKIP 0xC 2055 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2056 #define lpfc_sli4_sge_last_MASK 0x00000001 2057 #define lpfc_sli4_sge_last_WORD word2 2058 uint32_t sge_len; 2059 }; 2060 2061 struct sli4_hybrid_sgl { 2062 struct list_head list_node; 2063 struct sli4_sge *dma_sgl; 2064 dma_addr_t dma_phys_sgl; 2065 }; 2066 2067 struct fcp_cmd_rsp_buf { 2068 struct list_head list_node; 2069 2070 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2071 struct fcp_cmnd *fcp_cmnd; 2072 struct fcp_rsp *fcp_rsp; 2073 2074 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2075 dma_addr_t fcp_cmd_rsp_dma_handle; 2076 }; 2077 2078 struct sli4_sge_diseed { /* SLI-4 */ 2079 uint32_t ref_tag; 2080 uint32_t ref_tag_tran; 2081 2082 uint32_t word2; 2083 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2084 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2085 #define lpfc_sli4_sge_dif_apptran_WORD word2 2086 #define lpfc_sli4_sge_dif_af_SHIFT 24 2087 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2088 #define lpfc_sli4_sge_dif_af_WORD word2 2089 #define lpfc_sli4_sge_dif_na_SHIFT 25 2090 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2091 #define lpfc_sli4_sge_dif_na_WORD word2 2092 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2093 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2094 #define lpfc_sli4_sge_dif_hi_WORD word2 2095 #define lpfc_sli4_sge_dif_type_SHIFT 27 2096 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2097 #define lpfc_sli4_sge_dif_type_WORD word2 2098 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2099 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2100 #define lpfc_sli4_sge_dif_last_WORD word2 2101 uint32_t word3; 2102 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2103 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2104 #define lpfc_sli4_sge_dif_apptag_WORD word3 2105 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2106 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2107 #define lpfc_sli4_sge_dif_bs_WORD word3 2108 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2109 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2110 #define lpfc_sli4_sge_dif_ai_WORD word3 2111 #define lpfc_sli4_sge_dif_me_SHIFT 20 2112 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2113 #define lpfc_sli4_sge_dif_me_WORD word3 2114 #define lpfc_sli4_sge_dif_re_SHIFT 21 2115 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2116 #define lpfc_sli4_sge_dif_re_WORD word3 2117 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2118 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2119 #define lpfc_sli4_sge_dif_ce_WORD word3 2120 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2121 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2122 #define lpfc_sli4_sge_dif_nr_WORD word3 2123 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2124 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2125 #define lpfc_sli4_sge_dif_oprx_WORD word3 2126 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2127 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2128 #define lpfc_sli4_sge_dif_optx_WORD word3 2129 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2130 }; 2131 2132 struct fcf_record { 2133 uint32_t max_rcv_size; 2134 uint32_t fka_adv_period; 2135 uint32_t fip_priority; 2136 uint32_t word3; 2137 #define lpfc_fcf_record_mac_0_SHIFT 0 2138 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2139 #define lpfc_fcf_record_mac_0_WORD word3 2140 #define lpfc_fcf_record_mac_1_SHIFT 8 2141 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2142 #define lpfc_fcf_record_mac_1_WORD word3 2143 #define lpfc_fcf_record_mac_2_SHIFT 16 2144 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2145 #define lpfc_fcf_record_mac_2_WORD word3 2146 #define lpfc_fcf_record_mac_3_SHIFT 24 2147 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2148 #define lpfc_fcf_record_mac_3_WORD word3 2149 uint32_t word4; 2150 #define lpfc_fcf_record_mac_4_SHIFT 0 2151 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2152 #define lpfc_fcf_record_mac_4_WORD word4 2153 #define lpfc_fcf_record_mac_5_SHIFT 8 2154 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2155 #define lpfc_fcf_record_mac_5_WORD word4 2156 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2157 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2158 #define lpfc_fcf_record_fcf_avail_WORD word4 2159 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2160 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2161 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2162 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2163 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2164 uint32_t word5; 2165 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2166 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2167 #define lpfc_fcf_record_fab_name_0_WORD word5 2168 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2169 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2170 #define lpfc_fcf_record_fab_name_1_WORD word5 2171 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2172 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2173 #define lpfc_fcf_record_fab_name_2_WORD word5 2174 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2175 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2176 #define lpfc_fcf_record_fab_name_3_WORD word5 2177 uint32_t word6; 2178 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2179 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2180 #define lpfc_fcf_record_fab_name_4_WORD word6 2181 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2182 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2183 #define lpfc_fcf_record_fab_name_5_WORD word6 2184 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2185 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2186 #define lpfc_fcf_record_fab_name_6_WORD word6 2187 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2188 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2189 #define lpfc_fcf_record_fab_name_7_WORD word6 2190 uint32_t word7; 2191 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2192 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2193 #define lpfc_fcf_record_fc_map_0_WORD word7 2194 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2195 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2196 #define lpfc_fcf_record_fc_map_1_WORD word7 2197 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2198 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2199 #define lpfc_fcf_record_fc_map_2_WORD word7 2200 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2201 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2202 #define lpfc_fcf_record_fcf_valid_WORD word7 2203 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2204 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2205 #define lpfc_fcf_record_fcf_fc_WORD word7 2206 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2207 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2208 #define lpfc_fcf_record_fcf_sol_WORD word7 2209 uint32_t word8; 2210 #define lpfc_fcf_record_fcf_index_SHIFT 0 2211 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2212 #define lpfc_fcf_record_fcf_index_WORD word8 2213 #define lpfc_fcf_record_fcf_state_SHIFT 16 2214 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2215 #define lpfc_fcf_record_fcf_state_WORD word8 2216 uint8_t vlan_bitmap[512]; 2217 uint32_t word137; 2218 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2219 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2220 #define lpfc_fcf_record_switch_name_0_WORD word137 2221 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2222 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2223 #define lpfc_fcf_record_switch_name_1_WORD word137 2224 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2225 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2226 #define lpfc_fcf_record_switch_name_2_WORD word137 2227 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2228 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2229 #define lpfc_fcf_record_switch_name_3_WORD word137 2230 uint32_t word138; 2231 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2232 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2233 #define lpfc_fcf_record_switch_name_4_WORD word138 2234 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2235 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2236 #define lpfc_fcf_record_switch_name_5_WORD word138 2237 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2238 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2239 #define lpfc_fcf_record_switch_name_6_WORD word138 2240 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2241 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2242 #define lpfc_fcf_record_switch_name_7_WORD word138 2243 }; 2244 2245 struct lpfc_mbx_read_fcf_tbl { 2246 union lpfc_sli4_cfg_shdr cfg_shdr; 2247 union { 2248 struct { 2249 uint32_t word10; 2250 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2251 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2252 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2253 } request; 2254 struct { 2255 uint32_t eventag; 2256 } response; 2257 } u; 2258 uint32_t word11; 2259 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2260 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2261 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2262 }; 2263 2264 struct lpfc_mbx_add_fcf_tbl_entry { 2265 union lpfc_sli4_cfg_shdr cfg_shdr; 2266 uint32_t word10; 2267 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2268 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2269 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2270 struct lpfc_mbx_sge fcf_sge; 2271 }; 2272 2273 struct lpfc_mbx_del_fcf_tbl_entry { 2274 struct mbox_header header; 2275 uint32_t word10; 2276 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2277 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2278 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2279 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2280 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2281 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2282 }; 2283 2284 struct lpfc_mbx_redisc_fcf_tbl { 2285 struct mbox_header header; 2286 uint32_t word10; 2287 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2288 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2289 #define lpfc_mbx_redisc_fcf_count_WORD word10 2290 uint32_t resvd; 2291 uint32_t word12; 2292 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2293 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2294 #define lpfc_mbx_redisc_fcf_index_WORD word12 2295 }; 2296 2297 /* Status field for embedded SLI_CONFIG mailbox command */ 2298 #define STATUS_SUCCESS 0x0 2299 #define STATUS_FAILED 0x1 2300 #define STATUS_ILLEGAL_REQUEST 0x2 2301 #define STATUS_ILLEGAL_FIELD 0x3 2302 #define STATUS_INSUFFICIENT_BUFFER 0x4 2303 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2304 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2305 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2306 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2307 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2308 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2309 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2310 #define STATUS_ASSERT_FAILED 0x1e 2311 #define STATUS_INVALID_SESSION 0x1f 2312 #define STATUS_INVALID_CONNECTION 0x20 2313 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2314 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2315 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2316 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2317 #define STATUS_FLASHROM_READ_FAILED 0x27 2318 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2319 #define STATUS_ERROR_ACITMAIN 0x2a 2320 #define STATUS_REBOOT_REQUIRED 0x2c 2321 #define STATUS_FCF_IN_USE 0x3a 2322 #define STATUS_FCF_TABLE_EMPTY 0x43 2323 2324 /* 2325 * Additional status field for embedded SLI_CONFIG mailbox 2326 * command. 2327 */ 2328 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2329 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2330 #define ADD_STATUS_INVALID_REQUEST 0x4B 2331 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2332 2333 struct lpfc_mbx_sli4_config { 2334 struct mbox_header header; 2335 }; 2336 2337 struct lpfc_mbx_init_vfi { 2338 uint32_t word1; 2339 #define lpfc_init_vfi_vr_SHIFT 31 2340 #define lpfc_init_vfi_vr_MASK 0x00000001 2341 #define lpfc_init_vfi_vr_WORD word1 2342 #define lpfc_init_vfi_vt_SHIFT 30 2343 #define lpfc_init_vfi_vt_MASK 0x00000001 2344 #define lpfc_init_vfi_vt_WORD word1 2345 #define lpfc_init_vfi_vf_SHIFT 29 2346 #define lpfc_init_vfi_vf_MASK 0x00000001 2347 #define lpfc_init_vfi_vf_WORD word1 2348 #define lpfc_init_vfi_vp_SHIFT 28 2349 #define lpfc_init_vfi_vp_MASK 0x00000001 2350 #define lpfc_init_vfi_vp_WORD word1 2351 #define lpfc_init_vfi_vfi_SHIFT 0 2352 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2353 #define lpfc_init_vfi_vfi_WORD word1 2354 uint32_t word2; 2355 #define lpfc_init_vfi_vpi_SHIFT 16 2356 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2357 #define lpfc_init_vfi_vpi_WORD word2 2358 #define lpfc_init_vfi_fcfi_SHIFT 0 2359 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2360 #define lpfc_init_vfi_fcfi_WORD word2 2361 uint32_t word3; 2362 #define lpfc_init_vfi_pri_SHIFT 13 2363 #define lpfc_init_vfi_pri_MASK 0x00000007 2364 #define lpfc_init_vfi_pri_WORD word3 2365 #define lpfc_init_vfi_vf_id_SHIFT 1 2366 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2367 #define lpfc_init_vfi_vf_id_WORD word3 2368 uint32_t word4; 2369 #define lpfc_init_vfi_hop_count_SHIFT 24 2370 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2371 #define lpfc_init_vfi_hop_count_WORD word4 2372 }; 2373 #define MBX_VFI_IN_USE 0x9F02 2374 2375 2376 struct lpfc_mbx_reg_vfi { 2377 uint32_t word1; 2378 #define lpfc_reg_vfi_upd_SHIFT 29 2379 #define lpfc_reg_vfi_upd_MASK 0x00000001 2380 #define lpfc_reg_vfi_upd_WORD word1 2381 #define lpfc_reg_vfi_vp_SHIFT 28 2382 #define lpfc_reg_vfi_vp_MASK 0x00000001 2383 #define lpfc_reg_vfi_vp_WORD word1 2384 #define lpfc_reg_vfi_vfi_SHIFT 0 2385 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2386 #define lpfc_reg_vfi_vfi_WORD word1 2387 uint32_t word2; 2388 #define lpfc_reg_vfi_vpi_SHIFT 16 2389 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2390 #define lpfc_reg_vfi_vpi_WORD word2 2391 #define lpfc_reg_vfi_fcfi_SHIFT 0 2392 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2393 #define lpfc_reg_vfi_fcfi_WORD word2 2394 uint32_t wwn[2]; 2395 struct ulp_bde64 bde; 2396 uint32_t e_d_tov; 2397 uint32_t r_a_tov; 2398 uint32_t word10; 2399 #define lpfc_reg_vfi_nport_id_SHIFT 0 2400 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2401 #define lpfc_reg_vfi_nport_id_WORD word10 2402 #define lpfc_reg_vfi_bbcr_SHIFT 27 2403 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2404 #define lpfc_reg_vfi_bbcr_WORD word10 2405 #define lpfc_reg_vfi_bbscn_SHIFT 28 2406 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2407 #define lpfc_reg_vfi_bbscn_WORD word10 2408 }; 2409 2410 struct lpfc_mbx_init_vpi { 2411 uint32_t word1; 2412 #define lpfc_init_vpi_vfi_SHIFT 16 2413 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2414 #define lpfc_init_vpi_vfi_WORD word1 2415 #define lpfc_init_vpi_vpi_SHIFT 0 2416 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2417 #define lpfc_init_vpi_vpi_WORD word1 2418 }; 2419 2420 struct lpfc_mbx_read_vpi { 2421 uint32_t word1_rsvd; 2422 uint32_t word2; 2423 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2424 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2425 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2426 uint32_t word3_rsvd; 2427 uint32_t word4; 2428 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2429 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2430 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2431 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2432 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2433 #define lpfc_mbx_read_vpi_pb_WORD word4 2434 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2435 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2436 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2437 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2438 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2439 #define lpfc_mbx_read_vpi_ns_WORD word4 2440 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2441 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2442 #define lpfc_mbx_read_vpi_hl_WORD word4 2443 uint32_t word5_rsvd; 2444 uint32_t word6; 2445 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2446 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2447 #define lpfc_mbx_read_vpi_vpi_WORD word6 2448 uint32_t word7; 2449 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2450 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2451 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2452 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2453 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2454 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2455 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2456 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2457 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2458 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2459 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2460 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2461 uint32_t word8; 2462 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2463 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2464 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2465 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2466 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2467 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2468 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2469 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2470 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2471 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2472 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2473 #define lpfc_mbx_read_vpi_vv_WORD word8 2474 }; 2475 2476 struct lpfc_mbx_unreg_vfi { 2477 uint32_t word1_rsvd; 2478 uint32_t word2; 2479 #define lpfc_unreg_vfi_vfi_SHIFT 0 2480 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2481 #define lpfc_unreg_vfi_vfi_WORD word2 2482 }; 2483 2484 struct lpfc_mbx_resume_rpi { 2485 uint32_t word1; 2486 #define lpfc_resume_rpi_index_SHIFT 0 2487 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2488 #define lpfc_resume_rpi_index_WORD word1 2489 #define lpfc_resume_rpi_ii_SHIFT 30 2490 #define lpfc_resume_rpi_ii_MASK 0x00000003 2491 #define lpfc_resume_rpi_ii_WORD word1 2492 #define RESUME_INDEX_RPI 0 2493 #define RESUME_INDEX_VPI 1 2494 #define RESUME_INDEX_VFI 2 2495 #define RESUME_INDEX_FCFI 3 2496 uint32_t event_tag; 2497 }; 2498 2499 #define REG_FCF_INVALID_QID 0xFFFF 2500 struct lpfc_mbx_reg_fcfi { 2501 uint32_t word1; 2502 #define lpfc_reg_fcfi_info_index_SHIFT 0 2503 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2504 #define lpfc_reg_fcfi_info_index_WORD word1 2505 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2506 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2507 #define lpfc_reg_fcfi_fcfi_WORD word1 2508 uint32_t word2; 2509 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2510 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2511 #define lpfc_reg_fcfi_rq_id1_WORD word2 2512 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2513 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2514 #define lpfc_reg_fcfi_rq_id0_WORD word2 2515 uint32_t word3; 2516 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2517 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2518 #define lpfc_reg_fcfi_rq_id3_WORD word3 2519 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2520 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2521 #define lpfc_reg_fcfi_rq_id2_WORD word3 2522 uint32_t word4; 2523 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2524 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2525 #define lpfc_reg_fcfi_type_match0_WORD word4 2526 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2527 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2528 #define lpfc_reg_fcfi_type_mask0_WORD word4 2529 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2530 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2531 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2532 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2533 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2534 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2535 uint32_t word5; 2536 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2537 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2538 #define lpfc_reg_fcfi_type_match1_WORD word5 2539 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2540 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2541 #define lpfc_reg_fcfi_type_mask1_WORD word5 2542 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2543 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2544 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2545 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2546 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2547 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2548 uint32_t word6; 2549 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2550 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2551 #define lpfc_reg_fcfi_type_match2_WORD word6 2552 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2553 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2554 #define lpfc_reg_fcfi_type_mask2_WORD word6 2555 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2556 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2557 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2558 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2559 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2560 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2561 uint32_t word7; 2562 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2563 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2564 #define lpfc_reg_fcfi_type_match3_WORD word7 2565 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2566 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2567 #define lpfc_reg_fcfi_type_mask3_WORD word7 2568 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2569 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2570 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2571 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2572 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2573 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2574 uint32_t word8; 2575 #define lpfc_reg_fcfi_mam_SHIFT 13 2576 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2577 #define lpfc_reg_fcfi_mam_WORD word8 2578 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2579 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2580 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2581 #define lpfc_reg_fcfi_vv_SHIFT 12 2582 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2583 #define lpfc_reg_fcfi_vv_WORD word8 2584 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2585 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2586 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2587 }; 2588 2589 struct lpfc_mbx_reg_fcfi_mrq { 2590 uint32_t word1; 2591 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2592 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2593 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2594 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2595 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2596 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2597 uint32_t word2; 2598 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2599 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2600 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2601 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2602 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2603 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2604 uint32_t word3; 2605 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2606 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2607 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2608 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2609 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2610 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2611 uint32_t word4; 2612 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2613 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2614 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2615 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2616 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2617 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2618 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2619 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2620 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2621 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2622 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2623 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2624 uint32_t word5; 2625 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2626 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2627 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2628 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2629 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2630 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2631 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2632 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2633 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2634 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2635 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2636 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2637 uint32_t word6; 2638 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2639 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2640 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2641 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2642 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2643 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2644 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2645 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2646 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2647 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2648 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2649 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2650 uint32_t word7; 2651 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2652 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2653 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2654 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2655 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2656 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2657 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2658 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2659 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2660 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2661 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2662 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2663 uint32_t word8; 2664 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2665 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2666 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2667 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2668 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2669 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2670 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2671 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2672 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2673 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2674 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2675 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2676 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2677 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2678 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2679 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2680 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2681 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2682 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2683 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2684 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2685 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2686 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2687 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2688 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2689 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2690 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2691 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2692 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2693 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2694 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2695 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2696 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2697 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2698 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2699 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2700 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2701 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2702 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2703 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2704 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2705 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2706 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2707 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2708 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2709 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2710 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2711 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2712 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2713 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2714 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2715 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2716 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2717 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2718 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2719 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2720 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2721 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2722 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2723 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2724 uint32_t word9; 2725 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2726 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2727 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2728 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2729 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2730 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2731 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2732 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2733 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2734 uint32_t word10; 2735 uint32_t word11; 2736 uint32_t word12; 2737 uint32_t word13; 2738 uint32_t word14; 2739 uint32_t word15; 2740 uint32_t word16; 2741 }; 2742 2743 struct lpfc_mbx_unreg_fcfi { 2744 uint32_t word1_rsv; 2745 uint32_t word2; 2746 #define lpfc_unreg_fcfi_SHIFT 0 2747 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2748 #define lpfc_unreg_fcfi_WORD word2 2749 }; 2750 2751 struct lpfc_mbx_read_rev { 2752 uint32_t word1; 2753 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2754 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2755 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2756 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2757 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2758 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2759 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2760 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2761 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2762 #define LPFC_PREDCBX_CEE_MODE 0 2763 #define LPFC_DCBX_CEE_MODE 1 2764 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2765 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2766 #define lpfc_mbx_rd_rev_vpd_WORD word1 2767 uint32_t first_hw_rev; 2768 #define LPFC_G7_ASIC_1 0xd 2769 uint32_t second_hw_rev; 2770 uint32_t word4_rsvd; 2771 uint32_t third_hw_rev; 2772 uint32_t word6; 2773 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2774 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2775 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2776 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2777 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2778 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2779 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2780 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2781 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2782 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2783 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2784 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2785 uint32_t word7_rsvd; 2786 uint32_t fw_id_rev; 2787 uint8_t fw_name[16]; 2788 uint32_t ulp_fw_id_rev; 2789 uint8_t ulp_fw_name[16]; 2790 uint32_t word18_47_rsvd[30]; 2791 uint32_t word48; 2792 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2793 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2794 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2795 uint32_t vpd_paddr_low; 2796 uint32_t vpd_paddr_high; 2797 uint32_t avail_vpd_len; 2798 uint32_t rsvd_52_63[12]; 2799 }; 2800 2801 struct lpfc_mbx_read_config { 2802 uint32_t word1; 2803 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2804 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2805 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2806 uint32_t word2; 2807 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2808 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2809 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2810 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2811 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2812 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2813 #define LPFC_LNK_TYPE_GE 0 2814 #define LPFC_LNK_TYPE_FC 1 2815 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2816 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2817 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2818 #define lpfc_mbx_rd_conf_trunk_SHIFT 12 2819 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2820 #define lpfc_mbx_rd_conf_trunk_WORD word2 2821 #define lpfc_mbx_rd_conf_pt_SHIFT 20 2822 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2823 #define lpfc_mbx_rd_conf_pt_WORD word2 2824 #define lpfc_mbx_rd_conf_tf_SHIFT 22 2825 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2826 #define lpfc_mbx_rd_conf_tf_WORD word2 2827 #define lpfc_mbx_rd_conf_ptv_SHIFT 23 2828 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2829 #define lpfc_mbx_rd_conf_ptv_WORD word2 2830 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2831 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2832 #define lpfc_mbx_rd_conf_topology_WORD word2 2833 uint32_t rsvd_3; 2834 uint32_t word4; 2835 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2836 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2837 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2838 uint32_t rsvd_5; 2839 uint32_t word6; 2840 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2841 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2842 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2843 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2844 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2845 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2846 uint32_t rsvd_7; 2847 uint32_t word8; 2848 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2849 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2850 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2851 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2852 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2853 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2854 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2855 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2856 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2857 uint32_t word9; 2858 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2859 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2860 #define lpfc_mbx_rd_conf_lmt_WORD word9 2861 uint32_t rsvd_10; 2862 uint32_t rsvd_11; 2863 uint32_t word12; 2864 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2865 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2866 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2867 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2868 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2869 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2870 uint32_t word13; 2871 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2872 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2873 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2874 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2875 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2876 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2877 uint32_t word14; 2878 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2879 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2880 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2881 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2882 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2883 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2884 uint32_t word15; 2885 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2886 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2887 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2888 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2889 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2890 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2891 uint32_t word16; 2892 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2893 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2894 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2895 uint32_t word17; 2896 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2897 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2898 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2899 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2900 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2901 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2902 uint32_t word18; 2903 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2904 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2905 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2906 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2907 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2908 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2909 }; 2910 2911 struct lpfc_mbx_request_features { 2912 uint32_t word1; 2913 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2914 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2915 #define lpfc_mbx_rq_ftr_qry_WORD word1 2916 uint32_t word2; 2917 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2918 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2919 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2920 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2921 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2922 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2923 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2924 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2925 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2926 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2927 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2928 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2929 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2930 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2931 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2932 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2933 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2934 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2935 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2936 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2937 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2938 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2939 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2940 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2941 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2942 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2943 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2944 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2945 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2946 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2947 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2948 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2949 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2950 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 2951 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 2952 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 2953 uint32_t word3; 2954 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2955 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2956 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2957 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2958 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2959 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2960 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2961 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2962 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2963 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2964 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2965 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2966 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2967 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2968 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2969 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2970 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2971 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2972 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2973 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2974 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2975 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2976 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2977 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2978 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2979 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2980 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2981 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2982 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2983 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2984 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 2985 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 2986 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 2987 }; 2988 2989 struct lpfc_mbx_memory_dump_type3 { 2990 uint32_t word1; 2991 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2992 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2993 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2994 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2995 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2996 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2997 uint32_t word2; 2998 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2999 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3000 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3001 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3002 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3003 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3004 uint32_t word3; 3005 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3006 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3007 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3008 uint32_t addr_lo; 3009 uint32_t addr_hi; 3010 uint32_t return_len; 3011 }; 3012 3013 #define DMP_PAGE_A0 0xa0 3014 #define DMP_PAGE_A2 0xa2 3015 #define DMP_SFF_PAGE_A0_SIZE 256 3016 #define DMP_SFF_PAGE_A2_SIZE 256 3017 3018 #define SFP_WAVELENGTH_LC1310 1310 3019 #define SFP_WAVELENGTH_LL1550 1550 3020 3021 3022 /* 3023 * * SFF-8472 TABLE 3.4 3024 * */ 3025 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3026 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3027 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3028 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3029 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3030 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3031 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3032 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3033 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3034 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3035 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3036 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3037 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3038 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3039 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3040 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3041 3042 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3043 3044 #define SSF_IDENTIFIER 0 3045 #define SSF_EXT_IDENTIFIER 1 3046 #define SSF_CONNECTOR 2 3047 #define SSF_TRANSCEIVER_CODE_B0 3 3048 #define SSF_TRANSCEIVER_CODE_B1 4 3049 #define SSF_TRANSCEIVER_CODE_B2 5 3050 #define SSF_TRANSCEIVER_CODE_B3 6 3051 #define SSF_TRANSCEIVER_CODE_B4 7 3052 #define SSF_TRANSCEIVER_CODE_B5 8 3053 #define SSF_TRANSCEIVER_CODE_B6 9 3054 #define SSF_TRANSCEIVER_CODE_B7 10 3055 #define SSF_ENCODING 11 3056 #define SSF_BR_NOMINAL 12 3057 #define SSF_RATE_IDENTIFIER 13 3058 #define SSF_LENGTH_9UM_KM 14 3059 #define SSF_LENGTH_9UM 15 3060 #define SSF_LENGTH_50UM_OM2 16 3061 #define SSF_LENGTH_62UM_OM1 17 3062 #define SFF_LENGTH_COPPER 18 3063 #define SSF_LENGTH_50UM_OM3 19 3064 #define SSF_VENDOR_NAME 20 3065 #define SSF_VENDOR_OUI 36 3066 #define SSF_VENDOR_PN 40 3067 #define SSF_VENDOR_REV 56 3068 #define SSF_WAVELENGTH_B1 60 3069 #define SSF_WAVELENGTH_B0 61 3070 #define SSF_CC_BASE 63 3071 #define SSF_OPTIONS_B1 64 3072 #define SSF_OPTIONS_B0 65 3073 #define SSF_BR_MAX 66 3074 #define SSF_BR_MIN 67 3075 #define SSF_VENDOR_SN 68 3076 #define SSF_DATE_CODE 84 3077 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3078 #define SSF_ENHANCED_OPTIONS 93 3079 #define SFF_8472_COMPLIANCE 94 3080 #define SSF_CC_EXT 95 3081 #define SSF_A0_VENDOR_SPECIFIC 96 3082 3083 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3084 3085 #define SSF_TEMP_HIGH_ALARM 0 3086 #define SSF_TEMP_LOW_ALARM 2 3087 #define SSF_TEMP_HIGH_WARNING 4 3088 #define SSF_TEMP_LOW_WARNING 6 3089 #define SSF_VOLTAGE_HIGH_ALARM 8 3090 #define SSF_VOLTAGE_LOW_ALARM 10 3091 #define SSF_VOLTAGE_HIGH_WARNING 12 3092 #define SSF_VOLTAGE_LOW_WARNING 14 3093 #define SSF_BIAS_HIGH_ALARM 16 3094 #define SSF_BIAS_LOW_ALARM 18 3095 #define SSF_BIAS_HIGH_WARNING 20 3096 #define SSF_BIAS_LOW_WARNING 22 3097 #define SSF_TXPOWER_HIGH_ALARM 24 3098 #define SSF_TXPOWER_LOW_ALARM 26 3099 #define SSF_TXPOWER_HIGH_WARNING 28 3100 #define SSF_TXPOWER_LOW_WARNING 30 3101 #define SSF_RXPOWER_HIGH_ALARM 32 3102 #define SSF_RXPOWER_LOW_ALARM 34 3103 #define SSF_RXPOWER_HIGH_WARNING 36 3104 #define SSF_RXPOWER_LOW_WARNING 38 3105 #define SSF_EXT_CAL_CONSTANTS 56 3106 #define SSF_CC_DMI 95 3107 #define SFF_TEMPERATURE_B1 96 3108 #define SFF_TEMPERATURE_B0 97 3109 #define SFF_VCC_B1 98 3110 #define SFF_VCC_B0 99 3111 #define SFF_TX_BIAS_CURRENT_B1 100 3112 #define SFF_TX_BIAS_CURRENT_B0 101 3113 #define SFF_TXPOWER_B1 102 3114 #define SFF_TXPOWER_B0 103 3115 #define SFF_RXPOWER_B1 104 3116 #define SFF_RXPOWER_B0 105 3117 #define SSF_STATUS_CONTROL 110 3118 #define SSF_ALARM_FLAGS 112 3119 #define SSF_WARNING_FLAGS 116 3120 #define SSF_EXT_TATUS_CONTROL_B1 118 3121 #define SSF_EXT_TATUS_CONTROL_B0 119 3122 #define SSF_A2_VENDOR_SPECIFIC 120 3123 #define SSF_USER_EEPROM 128 3124 #define SSF_VENDOR_CONTROL 148 3125 3126 3127 /* 3128 * Tranceiver codes Fibre Channel SFF-8472 3129 * Table 3.5. 3130 */ 3131 3132 struct sff_trasnceiver_codes_byte0 { 3133 uint8_t inifiband:4; 3134 uint8_t teng_ethernet:4; 3135 }; 3136 3137 struct sff_trasnceiver_codes_byte1 { 3138 uint8_t sonet:6; 3139 uint8_t escon:2; 3140 }; 3141 3142 struct sff_trasnceiver_codes_byte2 { 3143 uint8_t soNet:8; 3144 }; 3145 3146 struct sff_trasnceiver_codes_byte3 { 3147 uint8_t ethernet:8; 3148 }; 3149 3150 struct sff_trasnceiver_codes_byte4 { 3151 uint8_t fc_el_lo:1; 3152 uint8_t fc_lw_laser:1; 3153 uint8_t fc_sw_laser:1; 3154 uint8_t fc_md_distance:1; 3155 uint8_t fc_lg_distance:1; 3156 uint8_t fc_int_distance:1; 3157 uint8_t fc_short_distance:1; 3158 uint8_t fc_vld_distance:1; 3159 }; 3160 3161 struct sff_trasnceiver_codes_byte5 { 3162 uint8_t reserved1:1; 3163 uint8_t reserved2:1; 3164 uint8_t fc_sfp_active:1; /* Active cable */ 3165 uint8_t fc_sfp_passive:1; /* Passive cable */ 3166 uint8_t fc_lw_laser:1; /* Longwave laser */ 3167 uint8_t fc_sw_laser_sl:1; 3168 uint8_t fc_sw_laser_sn:1; 3169 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3170 }; 3171 3172 struct sff_trasnceiver_codes_byte6 { 3173 uint8_t fc_tm_sm:1; /* Single Mode */ 3174 uint8_t reserved:1; 3175 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3176 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3177 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3178 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3179 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3180 }; 3181 3182 struct sff_trasnceiver_codes_byte7 { 3183 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3184 uint8_t reserve:1; 3185 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3186 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3187 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3188 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3189 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3190 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3191 }; 3192 3193 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3194 struct user_eeprom { 3195 uint8_t vendor_name[16]; 3196 uint8_t vendor_oui[3]; 3197 uint8_t vendor_pn[816]; 3198 uint8_t vendor_rev[4]; 3199 uint8_t vendor_sn[16]; 3200 uint8_t datecode[6]; 3201 uint8_t lot_code[2]; 3202 uint8_t reserved191[57]; 3203 }; 3204 3205 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3206 &(~((SLI4_PAGE_SIZE)-1))) 3207 3208 struct lpfc_sli4_parameters { 3209 uint32_t word0; 3210 #define cfg_prot_type_SHIFT 0 3211 #define cfg_prot_type_MASK 0x000000FF 3212 #define cfg_prot_type_WORD word0 3213 uint32_t word1; 3214 #define cfg_ft_SHIFT 0 3215 #define cfg_ft_MASK 0x00000001 3216 #define cfg_ft_WORD word1 3217 #define cfg_sli_rev_SHIFT 4 3218 #define cfg_sli_rev_MASK 0x0000000f 3219 #define cfg_sli_rev_WORD word1 3220 #define cfg_sli_family_SHIFT 8 3221 #define cfg_sli_family_MASK 0x0000000f 3222 #define cfg_sli_family_WORD word1 3223 #define cfg_if_type_SHIFT 12 3224 #define cfg_if_type_MASK 0x0000000f 3225 #define cfg_if_type_WORD word1 3226 #define cfg_sli_hint_1_SHIFT 16 3227 #define cfg_sli_hint_1_MASK 0x000000ff 3228 #define cfg_sli_hint_1_WORD word1 3229 #define cfg_sli_hint_2_SHIFT 24 3230 #define cfg_sli_hint_2_MASK 0x0000001f 3231 #define cfg_sli_hint_2_WORD word1 3232 uint32_t word2; 3233 #define cfg_eqav_SHIFT 31 3234 #define cfg_eqav_MASK 0x00000001 3235 #define cfg_eqav_WORD word2 3236 uint32_t word3; 3237 uint32_t word4; 3238 #define cfg_cqv_SHIFT 14 3239 #define cfg_cqv_MASK 0x00000003 3240 #define cfg_cqv_WORD word4 3241 #define cfg_cqpsize_SHIFT 16 3242 #define cfg_cqpsize_MASK 0x000000ff 3243 #define cfg_cqpsize_WORD word4 3244 #define cfg_cqav_SHIFT 31 3245 #define cfg_cqav_MASK 0x00000001 3246 #define cfg_cqav_WORD word4 3247 uint32_t word5; 3248 uint32_t word6; 3249 #define cfg_mqv_SHIFT 14 3250 #define cfg_mqv_MASK 0x00000003 3251 #define cfg_mqv_WORD word6 3252 uint32_t word7; 3253 uint32_t word8; 3254 #define cfg_wqpcnt_SHIFT 0 3255 #define cfg_wqpcnt_MASK 0x0000000f 3256 #define cfg_wqpcnt_WORD word8 3257 #define cfg_wqsize_SHIFT 8 3258 #define cfg_wqsize_MASK 0x0000000f 3259 #define cfg_wqsize_WORD word8 3260 #define cfg_wqv_SHIFT 14 3261 #define cfg_wqv_MASK 0x00000003 3262 #define cfg_wqv_WORD word8 3263 #define cfg_wqpsize_SHIFT 16 3264 #define cfg_wqpsize_MASK 0x000000ff 3265 #define cfg_wqpsize_WORD word8 3266 uint32_t word9; 3267 uint32_t word10; 3268 #define cfg_rqv_SHIFT 14 3269 #define cfg_rqv_MASK 0x00000003 3270 #define cfg_rqv_WORD word10 3271 uint32_t word11; 3272 #define cfg_rq_db_window_SHIFT 28 3273 #define cfg_rq_db_window_MASK 0x0000000f 3274 #define cfg_rq_db_window_WORD word11 3275 uint32_t word12; 3276 #define cfg_fcoe_SHIFT 0 3277 #define cfg_fcoe_MASK 0x00000001 3278 #define cfg_fcoe_WORD word12 3279 #define cfg_ext_SHIFT 1 3280 #define cfg_ext_MASK 0x00000001 3281 #define cfg_ext_WORD word12 3282 #define cfg_hdrr_SHIFT 2 3283 #define cfg_hdrr_MASK 0x00000001 3284 #define cfg_hdrr_WORD word12 3285 #define cfg_phwq_SHIFT 15 3286 #define cfg_phwq_MASK 0x00000001 3287 #define cfg_phwq_WORD word12 3288 #define cfg_oas_SHIFT 25 3289 #define cfg_oas_MASK 0x00000001 3290 #define cfg_oas_WORD word12 3291 #define cfg_loopbk_scope_SHIFT 28 3292 #define cfg_loopbk_scope_MASK 0x0000000f 3293 #define cfg_loopbk_scope_WORD word12 3294 uint32_t sge_supp_len; 3295 uint32_t word14; 3296 #define cfg_sgl_page_cnt_SHIFT 0 3297 #define cfg_sgl_page_cnt_MASK 0x0000000f 3298 #define cfg_sgl_page_cnt_WORD word14 3299 #define cfg_sgl_page_size_SHIFT 8 3300 #define cfg_sgl_page_size_MASK 0x000000ff 3301 #define cfg_sgl_page_size_WORD word14 3302 #define cfg_sgl_pp_align_SHIFT 16 3303 #define cfg_sgl_pp_align_MASK 0x000000ff 3304 #define cfg_sgl_pp_align_WORD word14 3305 uint32_t word15; 3306 uint32_t word16; 3307 uint32_t word17; 3308 uint32_t word18; 3309 uint32_t word19; 3310 #define cfg_ext_embed_cb_SHIFT 0 3311 #define cfg_ext_embed_cb_MASK 0x00000001 3312 #define cfg_ext_embed_cb_WORD word19 3313 #define cfg_mds_diags_SHIFT 1 3314 #define cfg_mds_diags_MASK 0x00000001 3315 #define cfg_mds_diags_WORD word19 3316 #define cfg_nvme_SHIFT 3 3317 #define cfg_nvme_MASK 0x00000001 3318 #define cfg_nvme_WORD word19 3319 #define cfg_xib_SHIFT 4 3320 #define cfg_xib_MASK 0x00000001 3321 #define cfg_xib_WORD word19 3322 #define cfg_xpsgl_SHIFT 6 3323 #define cfg_xpsgl_MASK 0x00000001 3324 #define cfg_xpsgl_WORD word19 3325 #define cfg_eqdr_SHIFT 8 3326 #define cfg_eqdr_MASK 0x00000001 3327 #define cfg_eqdr_WORD word19 3328 #define cfg_nosr_SHIFT 9 3329 #define cfg_nosr_MASK 0x00000001 3330 #define cfg_nosr_WORD word19 3331 3332 #define cfg_bv1s_SHIFT 10 3333 #define cfg_bv1s_MASK 0x00000001 3334 #define cfg_bv1s_WORD word19 3335 #define cfg_pvl_SHIFT 13 3336 #define cfg_pvl_MASK 0x00000001 3337 #define cfg_pvl_WORD word19 3338 3339 #define cfg_nsler_SHIFT 12 3340 #define cfg_nsler_MASK 0x00000001 3341 #define cfg_nsler_WORD word19 3342 3343 uint32_t word20; 3344 #define cfg_max_tow_xri_SHIFT 0 3345 #define cfg_max_tow_xri_MASK 0x0000ffff 3346 #define cfg_max_tow_xri_WORD word20 3347 3348 uint32_t word21; 3349 #define cfg_mib_bde_cnt_SHIFT 16 3350 #define cfg_mib_bde_cnt_MASK 0x000000ff 3351 #define cfg_mib_bde_cnt_WORD word21 3352 #define cfg_mi_ver_SHIFT 0 3353 #define cfg_mi_ver_MASK 0x0000ffff 3354 #define cfg_mi_ver_WORD word21 3355 uint32_t mib_size; 3356 uint32_t word23; /* RESERVED */ 3357 3358 uint32_t word24; 3359 #define cfg_frag_field_offset_SHIFT 0 3360 #define cfg_frag_field_offset_MASK 0x0000ffff 3361 #define cfg_frag_field_offset_WORD word24 3362 3363 #define cfg_frag_field_size_SHIFT 16 3364 #define cfg_frag_field_size_MASK 0x0000ffff 3365 #define cfg_frag_field_size_WORD word24 3366 3367 uint32_t word25; 3368 #define cfg_sgl_field_offset_SHIFT 0 3369 #define cfg_sgl_field_offset_MASK 0x0000ffff 3370 #define cfg_sgl_field_offset_WORD word25 3371 3372 #define cfg_sgl_field_size_SHIFT 16 3373 #define cfg_sgl_field_size_MASK 0x0000ffff 3374 #define cfg_sgl_field_size_WORD word25 3375 3376 uint32_t word26; /* Chain SGE initial value LOW */ 3377 uint32_t word27; /* Chain SGE initial value HIGH */ 3378 #define LPFC_NODELAY_MAX_IO 32 3379 }; 3380 3381 #define LPFC_SET_UE_RECOVERY 0x10 3382 #define LPFC_SET_MDS_DIAGS 0x12 3383 #define LPFC_SET_DUAL_DUMP 0x1e 3384 struct lpfc_mbx_set_feature { 3385 struct mbox_header header; 3386 uint32_t feature; 3387 uint32_t param_len; 3388 uint32_t word6; 3389 #define lpfc_mbx_set_feature_UER_SHIFT 0 3390 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3391 #define lpfc_mbx_set_feature_UER_WORD word6 3392 #define lpfc_mbx_set_feature_mds_SHIFT 2 3393 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3394 #define lpfc_mbx_set_feature_mds_WORD word6 3395 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3396 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3397 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3398 #define lpfc_mbx_set_feature_dd_SHIFT 0 3399 #define lpfc_mbx_set_feature_dd_MASK 0x00000001 3400 #define lpfc_mbx_set_feature_dd_WORD word6 3401 #define lpfc_mbx_set_feature_ddquery_SHIFT 1 3402 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3403 #define lpfc_mbx_set_feature_ddquery_WORD word6 3404 #define LPFC_DISABLE_DUAL_DUMP 0 3405 #define LPFC_ENABLE_DUAL_DUMP 1 3406 #define LPFC_QUERY_OP_DUAL_DUMP 2 3407 uint32_t word7; 3408 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3409 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3410 #define lpfc_mbx_set_feature_UERP_WORD word7 3411 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3412 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3413 #define lpfc_mbx_set_feature_UESR_WORD word7 3414 }; 3415 3416 3417 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3418 struct lpfc_mbx_set_host_data { 3419 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3420 struct mbox_header header; 3421 uint32_t param_id; 3422 uint32_t param_len; 3423 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3424 }; 3425 3426 struct lpfc_mbx_set_trunk_mode { 3427 struct mbox_header header; 3428 uint32_t word0; 3429 #define lpfc_mbx_set_trunk_mode_WORD word0 3430 #define lpfc_mbx_set_trunk_mode_SHIFT 0 3431 #define lpfc_mbx_set_trunk_mode_MASK 0xFF 3432 uint32_t word1; 3433 uint32_t word2; 3434 }; 3435 3436 struct lpfc_mbx_get_sli4_parameters { 3437 struct mbox_header header; 3438 struct lpfc_sli4_parameters sli4_parameters; 3439 }; 3440 3441 struct lpfc_rscr_desc_generic { 3442 #define LPFC_RSRC_DESC_WSIZE 22 3443 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3444 }; 3445 3446 struct lpfc_rsrc_desc_pcie { 3447 uint32_t word0; 3448 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3449 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3450 #define lpfc_rsrc_desc_pcie_type_WORD word0 3451 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3452 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3453 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3454 #define lpfc_rsrc_desc_pcie_length_WORD word0 3455 uint32_t word1; 3456 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3457 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3458 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3459 uint32_t reserved; 3460 uint32_t word3; 3461 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3462 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3463 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3464 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3465 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3466 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3467 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3468 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3469 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3470 uint32_t word4; 3471 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3472 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3473 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3474 }; 3475 3476 struct lpfc_rsrc_desc_fcfcoe { 3477 uint32_t word0; 3478 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3479 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3480 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3481 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3482 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3483 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3484 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3485 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3486 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3487 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3488 uint32_t word1; 3489 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3490 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3491 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3492 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3493 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3494 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3495 uint32_t word2; 3496 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3497 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3498 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3499 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3500 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3501 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3502 uint32_t word3; 3503 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3504 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3505 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3506 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3507 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3508 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3509 uint32_t word4; 3510 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3511 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3512 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3513 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3514 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3515 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3516 uint32_t word5; 3517 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3518 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3519 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3520 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3521 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3522 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3523 uint32_t word6; 3524 uint32_t word7; 3525 uint32_t word8; 3526 uint32_t word9; 3527 uint32_t word10; 3528 uint32_t word11; 3529 uint32_t word12; 3530 uint32_t word13; 3531 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3532 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3533 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3534 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3535 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3536 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3537 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3538 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3539 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3540 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3541 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3542 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3543 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3544 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3545 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3546 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3547 uint32_t bw_min; 3548 uint32_t bw_max; 3549 uint32_t iops_min; 3550 uint32_t iops_max; 3551 uint32_t reserved[4]; 3552 }; 3553 3554 struct lpfc_func_cfg { 3555 #define LPFC_RSRC_DESC_MAX_NUM 2 3556 uint32_t rsrc_desc_count; 3557 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3558 }; 3559 3560 struct lpfc_mbx_get_func_cfg { 3561 struct mbox_header header; 3562 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3563 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3564 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3565 struct lpfc_func_cfg func_cfg; 3566 }; 3567 3568 struct lpfc_prof_cfg { 3569 #define LPFC_RSRC_DESC_MAX_NUM 2 3570 uint32_t rsrc_desc_count; 3571 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3572 }; 3573 3574 struct lpfc_mbx_get_prof_cfg { 3575 struct mbox_header header; 3576 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3577 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3578 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3579 union { 3580 struct { 3581 uint32_t word10; 3582 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3583 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3584 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3585 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3586 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3587 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3588 } request; 3589 struct { 3590 struct lpfc_prof_cfg prof_cfg; 3591 } response; 3592 } u; 3593 }; 3594 3595 struct lpfc_controller_attribute { 3596 uint32_t version_string[8]; 3597 uint32_t manufacturer_name[8]; 3598 uint32_t supported_modes; 3599 uint32_t word17; 3600 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3601 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3602 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3603 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3604 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3605 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3606 uint32_t mbx_da_struct_ver; 3607 uint32_t ep_fw_da_struct_ver; 3608 uint32_t ncsi_ver_str[3]; 3609 uint32_t dflt_ext_timeout; 3610 uint32_t model_number[8]; 3611 uint32_t description[16]; 3612 uint32_t serial_number[8]; 3613 uint32_t ip_ver_str[8]; 3614 uint32_t fw_ver_str[8]; 3615 uint32_t bios_ver_str[8]; 3616 uint32_t redboot_ver_str[8]; 3617 uint32_t driver_ver_str[8]; 3618 uint32_t flash_fw_ver_str[8]; 3619 uint32_t functionality; 3620 uint32_t word105; 3621 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3622 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3623 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3624 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3625 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3626 #define lpfc_cntl_attr_asic_rev_WORD word105 3627 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3628 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3629 #define lpfc_cntl_attr_gen_guid0_WORD word105 3630 uint32_t gen_guid1_12[3]; 3631 uint32_t word109; 3632 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3633 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3634 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3635 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3636 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3637 #define lpfc_cntl_attr_gen_guid15_WORD word109 3638 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3639 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3640 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3641 uint32_t word110; 3642 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3643 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3644 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3645 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3646 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3647 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3648 uint32_t word111; 3649 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3650 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3651 #define lpfc_cntl_attr_cache_valid_WORD word111 3652 #define lpfc_cntl_attr_hba_status_SHIFT 8 3653 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3654 #define lpfc_cntl_attr_hba_status_WORD word111 3655 #define lpfc_cntl_attr_max_domain_SHIFT 16 3656 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3657 #define lpfc_cntl_attr_max_domain_WORD word111 3658 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3659 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3660 #define lpfc_cntl_attr_lnk_numb_WORD word111 3661 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3662 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3663 #define lpfc_cntl_attr_lnk_type_WORD word111 3664 uint32_t fw_post_status; 3665 uint32_t hba_mtu[8]; 3666 uint32_t word121; 3667 uint32_t reserved1[3]; 3668 uint32_t word125; 3669 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3670 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3671 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3672 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3673 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3674 #define lpfc_cntl_attr_pci_device_id_WORD word125 3675 uint32_t word126; 3676 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3677 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3678 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3679 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3680 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3681 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3682 uint32_t word127; 3683 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3684 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3685 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3686 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3687 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3688 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3689 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3690 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3691 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3692 #define lpfc_cntl_attr_inf_type_SHIFT 24 3693 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3694 #define lpfc_cntl_attr_inf_type_WORD word127 3695 uint32_t unique_id[2]; 3696 uint32_t word130; 3697 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3698 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3699 #define lpfc_cntl_attr_num_netfil_WORD word130 3700 uint32_t reserved2[4]; 3701 }; 3702 3703 struct lpfc_mbx_get_cntl_attributes { 3704 union lpfc_sli4_cfg_shdr cfg_shdr; 3705 struct lpfc_controller_attribute cntl_attr; 3706 }; 3707 3708 struct lpfc_mbx_get_port_name { 3709 struct mbox_header header; 3710 union { 3711 struct { 3712 uint32_t word4; 3713 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3714 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3715 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3716 } request; 3717 struct { 3718 uint32_t word4; 3719 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3720 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3721 #define lpfc_mbx_get_port_name_name0_WORD word4 3722 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3723 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3724 #define lpfc_mbx_get_port_name_name1_WORD word4 3725 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3726 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3727 #define lpfc_mbx_get_port_name_name2_WORD word4 3728 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3729 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3730 #define lpfc_mbx_get_port_name_name3_WORD word4 3731 #define LPFC_LINK_NUMBER_0 0 3732 #define LPFC_LINK_NUMBER_1 1 3733 #define LPFC_LINK_NUMBER_2 2 3734 #define LPFC_LINK_NUMBER_3 3 3735 } response; 3736 } u; 3737 }; 3738 3739 /* Mailbox Completion Queue Error Messages */ 3740 #define MB_CQE_STATUS_SUCCESS 0x0 3741 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3742 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3743 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3744 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3745 #define MB_CQE_STATUS_DMA_FAILED 0x5 3746 3747 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3748 struct lpfc_mbx_wr_object { 3749 struct mbox_header header; 3750 union { 3751 struct { 3752 uint32_t word4; 3753 #define lpfc_wr_object_eof_SHIFT 31 3754 #define lpfc_wr_object_eof_MASK 0x00000001 3755 #define lpfc_wr_object_eof_WORD word4 3756 #define lpfc_wr_object_eas_SHIFT 29 3757 #define lpfc_wr_object_eas_MASK 0x00000001 3758 #define lpfc_wr_object_eas_WORD word4 3759 #define lpfc_wr_object_write_length_SHIFT 0 3760 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3761 #define lpfc_wr_object_write_length_WORD word4 3762 uint32_t write_offset; 3763 uint32_t object_name[26]; 3764 uint32_t bde_count; 3765 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3766 } request; 3767 struct { 3768 uint32_t actual_write_length; 3769 uint32_t word5; 3770 #define lpfc_wr_object_change_status_SHIFT 0 3771 #define lpfc_wr_object_change_status_MASK 0x000000FF 3772 #define lpfc_wr_object_change_status_WORD word5 3773 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3774 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3775 #define LPFC_CHANGE_STATUS_FW_RESET 0x02 3776 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3777 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3778 #define lpfc_wr_object_csf_SHIFT 8 3779 #define lpfc_wr_object_csf_MASK 0x00000001 3780 #define lpfc_wr_object_csf_WORD word5 3781 } response; 3782 } u; 3783 }; 3784 3785 /* mailbox queue entry structure */ 3786 struct lpfc_mqe { 3787 uint32_t word0; 3788 #define lpfc_mqe_status_SHIFT 16 3789 #define lpfc_mqe_status_MASK 0x0000FFFF 3790 #define lpfc_mqe_status_WORD word0 3791 #define lpfc_mqe_command_SHIFT 8 3792 #define lpfc_mqe_command_MASK 0x000000FF 3793 #define lpfc_mqe_command_WORD word0 3794 union { 3795 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3796 /* sli4 mailbox commands */ 3797 struct lpfc_mbx_sli4_config sli4_config; 3798 struct lpfc_mbx_init_vfi init_vfi; 3799 struct lpfc_mbx_reg_vfi reg_vfi; 3800 struct lpfc_mbx_reg_vfi unreg_vfi; 3801 struct lpfc_mbx_init_vpi init_vpi; 3802 struct lpfc_mbx_resume_rpi resume_rpi; 3803 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3804 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3805 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3806 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3807 struct lpfc_mbx_reg_fcfi reg_fcfi; 3808 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3809 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3810 struct lpfc_mbx_mq_create mq_create; 3811 struct lpfc_mbx_mq_create_ext mq_create_ext; 3812 struct lpfc_mbx_eq_create eq_create; 3813 struct lpfc_mbx_modify_eq_delay eq_delay; 3814 struct lpfc_mbx_cq_create cq_create; 3815 struct lpfc_mbx_cq_create_set cq_create_set; 3816 struct lpfc_mbx_wq_create wq_create; 3817 struct lpfc_mbx_rq_create rq_create; 3818 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3819 struct lpfc_mbx_mq_destroy mq_destroy; 3820 struct lpfc_mbx_eq_destroy eq_destroy; 3821 struct lpfc_mbx_cq_destroy cq_destroy; 3822 struct lpfc_mbx_wq_destroy wq_destroy; 3823 struct lpfc_mbx_rq_destroy rq_destroy; 3824 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3825 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3826 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3827 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3828 struct lpfc_mbx_nembed_cmd nembed_cmd; 3829 struct lpfc_mbx_read_rev read_rev; 3830 struct lpfc_mbx_read_vpi read_vpi; 3831 struct lpfc_mbx_read_config rd_config; 3832 struct lpfc_mbx_request_features req_ftrs; 3833 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3834 struct lpfc_mbx_query_fw_config query_fw_cfg; 3835 struct lpfc_mbx_set_beacon_config beacon_config; 3836 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3837 struct lpfc_mbx_set_link_diag_state link_diag_state; 3838 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3839 struct lpfc_mbx_run_link_diag_test link_diag_test; 3840 struct lpfc_mbx_get_func_cfg get_func_cfg; 3841 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3842 struct lpfc_mbx_wr_object wr_object; 3843 struct lpfc_mbx_get_port_name get_port_name; 3844 struct lpfc_mbx_set_feature set_feature; 3845 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3846 struct lpfc_mbx_set_host_data set_host_data; 3847 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 3848 struct lpfc_mbx_nop nop; 3849 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 3850 } un; 3851 }; 3852 3853 struct lpfc_mcqe { 3854 uint32_t word0; 3855 #define lpfc_mcqe_status_SHIFT 0 3856 #define lpfc_mcqe_status_MASK 0x0000FFFF 3857 #define lpfc_mcqe_status_WORD word0 3858 #define lpfc_mcqe_ext_status_SHIFT 16 3859 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3860 #define lpfc_mcqe_ext_status_WORD word0 3861 uint32_t mcqe_tag0; 3862 uint32_t mcqe_tag1; 3863 uint32_t trailer; 3864 #define lpfc_trailer_valid_SHIFT 31 3865 #define lpfc_trailer_valid_MASK 0x00000001 3866 #define lpfc_trailer_valid_WORD trailer 3867 #define lpfc_trailer_async_SHIFT 30 3868 #define lpfc_trailer_async_MASK 0x00000001 3869 #define lpfc_trailer_async_WORD trailer 3870 #define lpfc_trailer_hpi_SHIFT 29 3871 #define lpfc_trailer_hpi_MASK 0x00000001 3872 #define lpfc_trailer_hpi_WORD trailer 3873 #define lpfc_trailer_completed_SHIFT 28 3874 #define lpfc_trailer_completed_MASK 0x00000001 3875 #define lpfc_trailer_completed_WORD trailer 3876 #define lpfc_trailer_consumed_SHIFT 27 3877 #define lpfc_trailer_consumed_MASK 0x00000001 3878 #define lpfc_trailer_consumed_WORD trailer 3879 #define lpfc_trailer_type_SHIFT 16 3880 #define lpfc_trailer_type_MASK 0x000000FF 3881 #define lpfc_trailer_type_WORD trailer 3882 #define lpfc_trailer_code_SHIFT 8 3883 #define lpfc_trailer_code_MASK 0x000000FF 3884 #define lpfc_trailer_code_WORD trailer 3885 #define LPFC_TRAILER_CODE_LINK 0x1 3886 #define LPFC_TRAILER_CODE_FCOE 0x2 3887 #define LPFC_TRAILER_CODE_DCBX 0x3 3888 #define LPFC_TRAILER_CODE_GRP5 0x5 3889 #define LPFC_TRAILER_CODE_FC 0x10 3890 #define LPFC_TRAILER_CODE_SLI 0x11 3891 }; 3892 3893 struct lpfc_acqe_link { 3894 uint32_t word0; 3895 #define lpfc_acqe_link_speed_SHIFT 24 3896 #define lpfc_acqe_link_speed_MASK 0x000000FF 3897 #define lpfc_acqe_link_speed_WORD word0 3898 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3899 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3900 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3901 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3902 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3903 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3904 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3905 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3906 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3907 #define lpfc_acqe_link_duplex_SHIFT 16 3908 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3909 #define lpfc_acqe_link_duplex_WORD word0 3910 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3911 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3912 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3913 #define lpfc_acqe_link_status_SHIFT 8 3914 #define lpfc_acqe_link_status_MASK 0x000000FF 3915 #define lpfc_acqe_link_status_WORD word0 3916 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3917 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3918 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3919 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3920 #define lpfc_acqe_link_type_SHIFT 6 3921 #define lpfc_acqe_link_type_MASK 0x00000003 3922 #define lpfc_acqe_link_type_WORD word0 3923 #define lpfc_acqe_link_number_SHIFT 0 3924 #define lpfc_acqe_link_number_MASK 0x0000003F 3925 #define lpfc_acqe_link_number_WORD word0 3926 uint32_t word1; 3927 #define lpfc_acqe_link_fault_SHIFT 0 3928 #define lpfc_acqe_link_fault_MASK 0x000000FF 3929 #define lpfc_acqe_link_fault_WORD word1 3930 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3931 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3932 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3933 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 3934 #define lpfc_acqe_logical_link_speed_SHIFT 16 3935 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3936 #define lpfc_acqe_logical_link_speed_WORD word1 3937 uint32_t event_tag; 3938 uint32_t trailer; 3939 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3940 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3941 }; 3942 3943 struct lpfc_acqe_fip { 3944 uint32_t index; 3945 uint32_t word1; 3946 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3947 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3948 #define lpfc_acqe_fip_fcf_count_WORD word1 3949 #define lpfc_acqe_fip_event_type_SHIFT 16 3950 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3951 #define lpfc_acqe_fip_event_type_WORD word1 3952 uint32_t event_tag; 3953 uint32_t trailer; 3954 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3955 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3956 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3957 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3958 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3959 }; 3960 3961 struct lpfc_acqe_dcbx { 3962 uint32_t tlv_ttl; 3963 uint32_t reserved; 3964 uint32_t event_tag; 3965 uint32_t trailer; 3966 }; 3967 3968 struct lpfc_acqe_grp5 { 3969 uint32_t word0; 3970 #define lpfc_acqe_grp5_type_SHIFT 6 3971 #define lpfc_acqe_grp5_type_MASK 0x00000003 3972 #define lpfc_acqe_grp5_type_WORD word0 3973 #define lpfc_acqe_grp5_number_SHIFT 0 3974 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3975 #define lpfc_acqe_grp5_number_WORD word0 3976 uint32_t word1; 3977 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3978 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3979 #define lpfc_acqe_grp5_llink_spd_WORD word1 3980 uint32_t event_tag; 3981 uint32_t trailer; 3982 }; 3983 3984 extern const char *const trunk_errmsg[]; 3985 3986 struct lpfc_acqe_fc_la { 3987 uint32_t word0; 3988 #define lpfc_acqe_fc_la_speed_SHIFT 24 3989 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3990 #define lpfc_acqe_fc_la_speed_WORD word0 3991 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 3992 #define LPFC_FC_LA_SPEED_1G 0x1 3993 #define LPFC_FC_LA_SPEED_2G 0x2 3994 #define LPFC_FC_LA_SPEED_4G 0x4 3995 #define LPFC_FC_LA_SPEED_8G 0x8 3996 #define LPFC_FC_LA_SPEED_10G 0xA 3997 #define LPFC_FC_LA_SPEED_16G 0x10 3998 #define LPFC_FC_LA_SPEED_32G 0x20 3999 #define LPFC_FC_LA_SPEED_64G 0x21 4000 #define LPFC_FC_LA_SPEED_128G 0x22 4001 #define LPFC_FC_LA_SPEED_256G 0x23 4002 #define lpfc_acqe_fc_la_topology_SHIFT 16 4003 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4004 #define lpfc_acqe_fc_la_topology_WORD word0 4005 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4006 #define LPFC_FC_LA_TOP_P2P 0x1 4007 #define LPFC_FC_LA_TOP_FCAL 0x2 4008 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4009 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4010 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4011 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4012 #define lpfc_acqe_fc_la_att_type_WORD word0 4013 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4014 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4015 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4016 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4017 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4018 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4019 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4020 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4021 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4022 #define lpfc_acqe_fc_la_port_type_WORD word0 4023 #define LPFC_LINK_TYPE_ETHERNET 0x0 4024 #define LPFC_LINK_TYPE_FC 0x1 4025 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4026 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4027 #define lpfc_acqe_fc_la_port_number_WORD word0 4028 4029 /* Attention Type is 0x07 (Trunking Event) word0 */ 4030 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4031 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4032 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4033 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4034 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4035 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4036 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4037 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4038 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4039 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4040 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4041 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4042 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4043 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4044 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4045 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4046 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4047 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4048 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4049 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4050 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4051 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4052 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4053 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4054 uint32_t word1; 4055 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4056 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4057 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4058 #define lpfc_acqe_fc_la_fault_SHIFT 0 4059 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4060 #define lpfc_acqe_fc_la_fault_WORD word1 4061 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4062 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4063 #define lpfc_acqe_fc_la_trunk_fault_WORD word1 4064 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4065 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4066 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4067 #define LPFC_FC_LA_FAULT_NONE 0x0 4068 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4069 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4070 uint32_t event_tag; 4071 uint32_t trailer; 4072 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4073 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4074 }; 4075 4076 struct lpfc_acqe_misconfigured_event { 4077 struct { 4078 uint32_t word0; 4079 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4080 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4081 #define lpfc_sli_misconfigured_port0_state_WORD word0 4082 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4083 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4084 #define lpfc_sli_misconfigured_port1_state_WORD word0 4085 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4086 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4087 #define lpfc_sli_misconfigured_port2_state_WORD word0 4088 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4089 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4090 #define lpfc_sli_misconfigured_port3_state_WORD word0 4091 uint32_t word1; 4092 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4093 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4094 #define lpfc_sli_misconfigured_port0_op_WORD word1 4095 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4096 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4097 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4098 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4099 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4100 #define lpfc_sli_misconfigured_port1_op_WORD word1 4101 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4102 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4103 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4104 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4105 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4106 #define lpfc_sli_misconfigured_port2_op_WORD word1 4107 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4108 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4109 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4110 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4111 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4112 #define lpfc_sli_misconfigured_port3_op_WORD word1 4113 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4114 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4115 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4116 } theEvent; 4117 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4118 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4119 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4120 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4121 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4122 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4123 }; 4124 4125 struct lpfc_acqe_sli { 4126 uint32_t event_data1; 4127 uint32_t event_data2; 4128 uint32_t reserved; 4129 uint32_t trailer; 4130 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4131 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4132 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4133 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4134 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4135 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4136 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4137 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4138 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4139 }; 4140 4141 /* 4142 * Define the bootstrap mailbox (bmbx) region used to communicate 4143 * mailbox command between the host and port. The mailbox consists 4144 * of a payload area of 256 bytes and a completion queue of length 4145 * 16 bytes. 4146 */ 4147 struct lpfc_bmbx_create { 4148 struct lpfc_mqe mqe; 4149 struct lpfc_mcqe mcqe; 4150 }; 4151 4152 #define SGL_ALIGN_SZ 64 4153 #define SGL_PAGE_SIZE 4096 4154 /* align SGL addr on a size boundary - adjust address up */ 4155 #define NO_XRI 0xffff 4156 4157 struct wqe_common { 4158 uint32_t word6; 4159 #define wqe_xri_tag_SHIFT 0 4160 #define wqe_xri_tag_MASK 0x0000FFFF 4161 #define wqe_xri_tag_WORD word6 4162 #define wqe_ctxt_tag_SHIFT 16 4163 #define wqe_ctxt_tag_MASK 0x0000FFFF 4164 #define wqe_ctxt_tag_WORD word6 4165 uint32_t word7; 4166 #define wqe_dif_SHIFT 0 4167 #define wqe_dif_MASK 0x00000003 4168 #define wqe_dif_WORD word7 4169 #define LPFC_WQE_DIF_PASSTHRU 1 4170 #define LPFC_WQE_DIF_STRIP 2 4171 #define LPFC_WQE_DIF_INSERT 3 4172 #define wqe_ct_SHIFT 2 4173 #define wqe_ct_MASK 0x00000003 4174 #define wqe_ct_WORD word7 4175 #define wqe_status_SHIFT 4 4176 #define wqe_status_MASK 0x0000000f 4177 #define wqe_status_WORD word7 4178 #define wqe_cmnd_SHIFT 8 4179 #define wqe_cmnd_MASK 0x000000ff 4180 #define wqe_cmnd_WORD word7 4181 #define wqe_class_SHIFT 16 4182 #define wqe_class_MASK 0x00000007 4183 #define wqe_class_WORD word7 4184 #define wqe_ar_SHIFT 19 4185 #define wqe_ar_MASK 0x00000001 4186 #define wqe_ar_WORD word7 4187 #define wqe_ag_SHIFT wqe_ar_SHIFT 4188 #define wqe_ag_MASK wqe_ar_MASK 4189 #define wqe_ag_WORD wqe_ar_WORD 4190 #define wqe_pu_SHIFT 20 4191 #define wqe_pu_MASK 0x00000003 4192 #define wqe_pu_WORD word7 4193 #define wqe_erp_SHIFT 22 4194 #define wqe_erp_MASK 0x00000001 4195 #define wqe_erp_WORD word7 4196 #define wqe_conf_SHIFT wqe_erp_SHIFT 4197 #define wqe_conf_MASK wqe_erp_MASK 4198 #define wqe_conf_WORD wqe_erp_WORD 4199 #define wqe_lnk_SHIFT 23 4200 #define wqe_lnk_MASK 0x00000001 4201 #define wqe_lnk_WORD word7 4202 #define wqe_tmo_SHIFT 24 4203 #define wqe_tmo_MASK 0x000000ff 4204 #define wqe_tmo_WORD word7 4205 uint32_t abort_tag; /* word 8 in WQE */ 4206 uint32_t word9; 4207 #define wqe_reqtag_SHIFT 0 4208 #define wqe_reqtag_MASK 0x0000FFFF 4209 #define wqe_reqtag_WORD word9 4210 #define wqe_temp_rpi_SHIFT 16 4211 #define wqe_temp_rpi_MASK 0x0000FFFF 4212 #define wqe_temp_rpi_WORD word9 4213 #define wqe_rcvoxid_SHIFT 16 4214 #define wqe_rcvoxid_MASK 0x0000FFFF 4215 #define wqe_rcvoxid_WORD word9 4216 #define wqe_sof_SHIFT 24 4217 #define wqe_sof_MASK 0x000000FF 4218 #define wqe_sof_WORD word9 4219 #define wqe_eof_SHIFT 16 4220 #define wqe_eof_MASK 0x000000FF 4221 #define wqe_eof_WORD word9 4222 uint32_t word10; 4223 #define wqe_ebde_cnt_SHIFT 0 4224 #define wqe_ebde_cnt_MASK 0x0000000f 4225 #define wqe_ebde_cnt_WORD word10 4226 #define wqe_xchg_SHIFT 4 4227 #define wqe_xchg_MASK 0x00000001 4228 #define wqe_xchg_WORD word10 4229 #define LPFC_SCSI_XCHG 0x0 4230 #define LPFC_NVME_XCHG 0x1 4231 #define wqe_appid_SHIFT 5 4232 #define wqe_appid_MASK 0x00000001 4233 #define wqe_appid_WORD word10 4234 #define wqe_oas_SHIFT 6 4235 #define wqe_oas_MASK 0x00000001 4236 #define wqe_oas_WORD word10 4237 #define wqe_lenloc_SHIFT 7 4238 #define wqe_lenloc_MASK 0x00000003 4239 #define wqe_lenloc_WORD word10 4240 #define LPFC_WQE_LENLOC_NONE 0 4241 #define LPFC_WQE_LENLOC_WORD3 1 4242 #define LPFC_WQE_LENLOC_WORD12 2 4243 #define LPFC_WQE_LENLOC_WORD4 3 4244 #define wqe_qosd_SHIFT 9 4245 #define wqe_qosd_MASK 0x00000001 4246 #define wqe_qosd_WORD word10 4247 #define wqe_xbl_SHIFT 11 4248 #define wqe_xbl_MASK 0x00000001 4249 #define wqe_xbl_WORD word10 4250 #define wqe_iod_SHIFT 13 4251 #define wqe_iod_MASK 0x00000001 4252 #define wqe_iod_WORD word10 4253 #define LPFC_WQE_IOD_NONE 0 4254 #define LPFC_WQE_IOD_WRITE 0 4255 #define LPFC_WQE_IOD_READ 1 4256 #define wqe_dbde_SHIFT 14 4257 #define wqe_dbde_MASK 0x00000001 4258 #define wqe_dbde_WORD word10 4259 #define wqe_wqes_SHIFT 15 4260 #define wqe_wqes_MASK 0x00000001 4261 #define wqe_wqes_WORD word10 4262 /* Note that this field overlaps above fields */ 4263 #define wqe_wqid_SHIFT 1 4264 #define wqe_wqid_MASK 0x00007fff 4265 #define wqe_wqid_WORD word10 4266 #define wqe_pri_SHIFT 16 4267 #define wqe_pri_MASK 0x00000007 4268 #define wqe_pri_WORD word10 4269 #define wqe_pv_SHIFT 19 4270 #define wqe_pv_MASK 0x00000001 4271 #define wqe_pv_WORD word10 4272 #define wqe_xc_SHIFT 21 4273 #define wqe_xc_MASK 0x00000001 4274 #define wqe_xc_WORD word10 4275 #define wqe_sr_SHIFT 22 4276 #define wqe_sr_MASK 0x00000001 4277 #define wqe_sr_WORD word10 4278 #define wqe_ccpe_SHIFT 23 4279 #define wqe_ccpe_MASK 0x00000001 4280 #define wqe_ccpe_WORD word10 4281 #define wqe_ccp_SHIFT 24 4282 #define wqe_ccp_MASK 0x000000ff 4283 #define wqe_ccp_WORD word10 4284 uint32_t word11; 4285 #define wqe_cmd_type_SHIFT 0 4286 #define wqe_cmd_type_MASK 0x0000000f 4287 #define wqe_cmd_type_WORD word11 4288 #define wqe_els_id_SHIFT 4 4289 #define wqe_els_id_MASK 0x00000003 4290 #define wqe_els_id_WORD word11 4291 #define LPFC_ELS_ID_FLOGI 3 4292 #define LPFC_ELS_ID_FDISC 2 4293 #define LPFC_ELS_ID_LOGO 1 4294 #define LPFC_ELS_ID_DEFAULT 0 4295 #define wqe_irsp_SHIFT 4 4296 #define wqe_irsp_MASK 0x00000001 4297 #define wqe_irsp_WORD word11 4298 #define wqe_pbde_SHIFT 5 4299 #define wqe_pbde_MASK 0x00000001 4300 #define wqe_pbde_WORD word11 4301 #define wqe_sup_SHIFT 6 4302 #define wqe_sup_MASK 0x00000001 4303 #define wqe_sup_WORD word11 4304 #define wqe_wqec_SHIFT 7 4305 #define wqe_wqec_MASK 0x00000001 4306 #define wqe_wqec_WORD word11 4307 #define wqe_irsplen_SHIFT 8 4308 #define wqe_irsplen_MASK 0x0000000f 4309 #define wqe_irsplen_WORD word11 4310 #define wqe_cqid_SHIFT 16 4311 #define wqe_cqid_MASK 0x0000ffff 4312 #define wqe_cqid_WORD word11 4313 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4314 }; 4315 4316 struct wqe_did { 4317 uint32_t word5; 4318 #define wqe_els_did_SHIFT 0 4319 #define wqe_els_did_MASK 0x00FFFFFF 4320 #define wqe_els_did_WORD word5 4321 #define wqe_xmit_bls_pt_SHIFT 28 4322 #define wqe_xmit_bls_pt_MASK 0x00000003 4323 #define wqe_xmit_bls_pt_WORD word5 4324 #define wqe_xmit_bls_ar_SHIFT 30 4325 #define wqe_xmit_bls_ar_MASK 0x00000001 4326 #define wqe_xmit_bls_ar_WORD word5 4327 #define wqe_xmit_bls_xo_SHIFT 31 4328 #define wqe_xmit_bls_xo_MASK 0x00000001 4329 #define wqe_xmit_bls_xo_WORD word5 4330 }; 4331 4332 struct lpfc_wqe_generic{ 4333 struct ulp_bde64 bde; 4334 uint32_t word3; 4335 uint32_t word4; 4336 uint32_t word5; 4337 struct wqe_common wqe_com; 4338 uint32_t payload[4]; 4339 }; 4340 4341 struct els_request64_wqe { 4342 struct ulp_bde64 bde; 4343 uint32_t payload_len; 4344 uint32_t word4; 4345 #define els_req64_sid_SHIFT 0 4346 #define els_req64_sid_MASK 0x00FFFFFF 4347 #define els_req64_sid_WORD word4 4348 #define els_req64_sp_SHIFT 24 4349 #define els_req64_sp_MASK 0x00000001 4350 #define els_req64_sp_WORD word4 4351 #define els_req64_vf_SHIFT 25 4352 #define els_req64_vf_MASK 0x00000001 4353 #define els_req64_vf_WORD word4 4354 struct wqe_did wqe_dest; 4355 struct wqe_common wqe_com; /* words 6-11 */ 4356 uint32_t word12; 4357 #define els_req64_vfid_SHIFT 1 4358 #define els_req64_vfid_MASK 0x00000FFF 4359 #define els_req64_vfid_WORD word12 4360 #define els_req64_pri_SHIFT 13 4361 #define els_req64_pri_MASK 0x00000007 4362 #define els_req64_pri_WORD word12 4363 uint32_t word13; 4364 #define els_req64_hopcnt_SHIFT 24 4365 #define els_req64_hopcnt_MASK 0x000000ff 4366 #define els_req64_hopcnt_WORD word13 4367 uint32_t word14; 4368 uint32_t max_response_payload_len; 4369 }; 4370 4371 struct xmit_els_rsp64_wqe { 4372 struct ulp_bde64 bde; 4373 uint32_t response_payload_len; 4374 uint32_t word4; 4375 #define els_rsp64_sid_SHIFT 0 4376 #define els_rsp64_sid_MASK 0x00FFFFFF 4377 #define els_rsp64_sid_WORD word4 4378 #define els_rsp64_sp_SHIFT 24 4379 #define els_rsp64_sp_MASK 0x00000001 4380 #define els_rsp64_sp_WORD word4 4381 struct wqe_did wqe_dest; 4382 struct wqe_common wqe_com; /* words 6-11 */ 4383 uint32_t word12; 4384 #define wqe_rsp_temp_rpi_SHIFT 0 4385 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4386 #define wqe_rsp_temp_rpi_WORD word12 4387 uint32_t rsvd_13_15[3]; 4388 }; 4389 4390 struct xmit_bls_rsp64_wqe { 4391 uint32_t payload0; 4392 /* Payload0 for BA_ACC */ 4393 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4394 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4395 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4396 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4397 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4398 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4399 /* Payload0 for BA_RJT */ 4400 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4401 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4402 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4403 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4404 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4405 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4406 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4407 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4408 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4409 uint32_t word1; 4410 #define xmit_bls_rsp64_rxid_SHIFT 0 4411 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4412 #define xmit_bls_rsp64_rxid_WORD word1 4413 #define xmit_bls_rsp64_oxid_SHIFT 16 4414 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4415 #define xmit_bls_rsp64_oxid_WORD word1 4416 uint32_t word2; 4417 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4418 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4419 #define xmit_bls_rsp64_seqcnthi_WORD word2 4420 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4421 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4422 #define xmit_bls_rsp64_seqcntlo_WORD word2 4423 uint32_t rsrvd3; 4424 uint32_t rsrvd4; 4425 struct wqe_did wqe_dest; 4426 struct wqe_common wqe_com; /* words 6-11 */ 4427 uint32_t word12; 4428 #define xmit_bls_rsp64_temprpi_SHIFT 0 4429 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4430 #define xmit_bls_rsp64_temprpi_WORD word12 4431 uint32_t rsvd_13_15[3]; 4432 }; 4433 4434 struct wqe_rctl_dfctl { 4435 uint32_t word5; 4436 #define wqe_si_SHIFT 2 4437 #define wqe_si_MASK 0x000000001 4438 #define wqe_si_WORD word5 4439 #define wqe_la_SHIFT 3 4440 #define wqe_la_MASK 0x000000001 4441 #define wqe_la_WORD word5 4442 #define wqe_xo_SHIFT 6 4443 #define wqe_xo_MASK 0x000000001 4444 #define wqe_xo_WORD word5 4445 #define wqe_ls_SHIFT 7 4446 #define wqe_ls_MASK 0x000000001 4447 #define wqe_ls_WORD word5 4448 #define wqe_dfctl_SHIFT 8 4449 #define wqe_dfctl_MASK 0x0000000ff 4450 #define wqe_dfctl_WORD word5 4451 #define wqe_type_SHIFT 16 4452 #define wqe_type_MASK 0x0000000ff 4453 #define wqe_type_WORD word5 4454 #define wqe_rctl_SHIFT 24 4455 #define wqe_rctl_MASK 0x0000000ff 4456 #define wqe_rctl_WORD word5 4457 }; 4458 4459 struct xmit_seq64_wqe { 4460 struct ulp_bde64 bde; 4461 uint32_t rsvd3; 4462 uint32_t relative_offset; 4463 struct wqe_rctl_dfctl wge_ctl; 4464 struct wqe_common wqe_com; /* words 6-11 */ 4465 uint32_t xmit_len; 4466 uint32_t rsvd_12_15[3]; 4467 }; 4468 struct xmit_bcast64_wqe { 4469 struct ulp_bde64 bde; 4470 uint32_t seq_payload_len; 4471 uint32_t rsvd4; 4472 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4473 struct wqe_common wqe_com; /* words 6-11 */ 4474 uint32_t rsvd_12_15[4]; 4475 }; 4476 4477 struct gen_req64_wqe { 4478 struct ulp_bde64 bde; 4479 uint32_t request_payload_len; 4480 uint32_t relative_offset; 4481 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4482 struct wqe_common wqe_com; /* words 6-11 */ 4483 uint32_t rsvd_12_14[3]; 4484 uint32_t max_response_payload_len; 4485 }; 4486 4487 /* Define NVME PRLI request to fabric. NVME is a 4488 * fabric-only protocol. 4489 * Updated to red-lined v1.08 on Sept 16, 2016 4490 */ 4491 struct lpfc_nvme_prli { 4492 uint32_t word1; 4493 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4494 #define prli_acc_rsp_code_SHIFT 8 4495 #define prli_acc_rsp_code_MASK 0x0000000f 4496 #define prli_acc_rsp_code_WORD word1 4497 #define prli_estabImagePair_SHIFT 13 4498 #define prli_estabImagePair_MASK 0x00000001 4499 #define prli_estabImagePair_WORD word1 4500 #define prli_type_code_ext_SHIFT 16 4501 #define prli_type_code_ext_MASK 0x000000ff 4502 #define prli_type_code_ext_WORD word1 4503 #define prli_type_code_SHIFT 24 4504 #define prli_type_code_MASK 0x000000ff 4505 #define prli_type_code_WORD word1 4506 uint32_t word_rsvd2; 4507 uint32_t word_rsvd3; 4508 4509 uint32_t word4; 4510 #define prli_fba_SHIFT 0 4511 #define prli_fba_MASK 0x00000001 4512 #define prli_fba_WORD word4 4513 #define prli_disc_SHIFT 3 4514 #define prli_disc_MASK 0x00000001 4515 #define prli_disc_WORD word4 4516 #define prli_tgt_SHIFT 4 4517 #define prli_tgt_MASK 0x00000001 4518 #define prli_tgt_WORD word4 4519 #define prli_init_SHIFT 5 4520 #define prli_init_MASK 0x00000001 4521 #define prli_init_WORD word4 4522 #define prli_conf_SHIFT 7 4523 #define prli_conf_MASK 0x00000001 4524 #define prli_conf_WORD word4 4525 #define prli_nsler_SHIFT 8 4526 #define prli_nsler_MASK 0x00000001 4527 #define prli_nsler_WORD word4 4528 uint32_t word5; 4529 #define prli_fb_sz_SHIFT 0 4530 #define prli_fb_sz_MASK 0x0000ffff 4531 #define prli_fb_sz_WORD word5 4532 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4533 }; 4534 4535 struct create_xri_wqe { 4536 uint32_t rsrvd[5]; /* words 0-4 */ 4537 struct wqe_did wqe_dest; /* word 5 */ 4538 struct wqe_common wqe_com; /* words 6-11 */ 4539 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4540 }; 4541 4542 #define INHIBIT_ABORT 1 4543 #define T_REQUEST_TAG 3 4544 #define T_XRI_TAG 1 4545 4546 struct abort_cmd_wqe { 4547 uint32_t rsrvd[3]; 4548 uint32_t word3; 4549 #define abort_cmd_ia_SHIFT 0 4550 #define abort_cmd_ia_MASK 0x000000001 4551 #define abort_cmd_ia_WORD word3 4552 #define abort_cmd_criteria_SHIFT 8 4553 #define abort_cmd_criteria_MASK 0x0000000ff 4554 #define abort_cmd_criteria_WORD word3 4555 uint32_t rsrvd4; 4556 uint32_t rsrvd5; 4557 struct wqe_common wqe_com; /* words 6-11 */ 4558 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4559 }; 4560 4561 struct fcp_iwrite64_wqe { 4562 struct ulp_bde64 bde; 4563 uint32_t word3; 4564 #define cmd_buff_len_SHIFT 16 4565 #define cmd_buff_len_MASK 0x00000ffff 4566 #define cmd_buff_len_WORD word3 4567 #define payload_offset_len_SHIFT 0 4568 #define payload_offset_len_MASK 0x0000ffff 4569 #define payload_offset_len_WORD word3 4570 uint32_t total_xfer_len; 4571 uint32_t initial_xfer_len; 4572 struct wqe_common wqe_com; /* words 6-11 */ 4573 uint32_t rsrvd12; 4574 struct ulp_bde64 ph_bde; /* words 13-15 */ 4575 }; 4576 4577 struct fcp_iread64_wqe { 4578 struct ulp_bde64 bde; 4579 uint32_t word3; 4580 #define cmd_buff_len_SHIFT 16 4581 #define cmd_buff_len_MASK 0x00000ffff 4582 #define cmd_buff_len_WORD word3 4583 #define payload_offset_len_SHIFT 0 4584 #define payload_offset_len_MASK 0x0000ffff 4585 #define payload_offset_len_WORD word3 4586 uint32_t total_xfer_len; /* word 4 */ 4587 uint32_t rsrvd5; /* word 5 */ 4588 struct wqe_common wqe_com; /* words 6-11 */ 4589 uint32_t rsrvd12; 4590 struct ulp_bde64 ph_bde; /* words 13-15 */ 4591 }; 4592 4593 struct fcp_icmnd64_wqe { 4594 struct ulp_bde64 bde; /* words 0-2 */ 4595 uint32_t word3; 4596 #define cmd_buff_len_SHIFT 16 4597 #define cmd_buff_len_MASK 0x00000ffff 4598 #define cmd_buff_len_WORD word3 4599 #define payload_offset_len_SHIFT 0 4600 #define payload_offset_len_MASK 0x0000ffff 4601 #define payload_offset_len_WORD word3 4602 uint32_t rsrvd4; /* word 4 */ 4603 uint32_t rsrvd5; /* word 5 */ 4604 struct wqe_common wqe_com; /* words 6-11 */ 4605 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4606 }; 4607 4608 struct fcp_trsp64_wqe { 4609 struct ulp_bde64 bde; 4610 uint32_t response_len; 4611 uint32_t rsvd_4_5[2]; 4612 struct wqe_common wqe_com; /* words 6-11 */ 4613 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4614 }; 4615 4616 struct fcp_tsend64_wqe { 4617 struct ulp_bde64 bde; 4618 uint32_t payload_offset_len; 4619 uint32_t relative_offset; 4620 uint32_t reserved; 4621 struct wqe_common wqe_com; /* words 6-11 */ 4622 uint32_t fcp_data_len; /* word 12 */ 4623 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4624 }; 4625 4626 struct fcp_treceive64_wqe { 4627 struct ulp_bde64 bde; 4628 uint32_t payload_offset_len; 4629 uint32_t relative_offset; 4630 uint32_t reserved; 4631 struct wqe_common wqe_com; /* words 6-11 */ 4632 uint32_t fcp_data_len; /* word 12 */ 4633 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4634 }; 4635 #define TXRDY_PAYLOAD_LEN 12 4636 4637 #define CMD_SEND_FRAME 0xE1 4638 4639 struct send_frame_wqe { 4640 struct ulp_bde64 bde; /* words 0-2 */ 4641 uint32_t frame_len; /* word 3 */ 4642 uint32_t fc_hdr_wd0; /* word 4 */ 4643 uint32_t fc_hdr_wd1; /* word 5 */ 4644 struct wqe_common wqe_com; /* words 6-11 */ 4645 uint32_t fc_hdr_wd2; /* word 12 */ 4646 uint32_t fc_hdr_wd3; /* word 13 */ 4647 uint32_t fc_hdr_wd4; /* word 14 */ 4648 uint32_t fc_hdr_wd5; /* word 15 */ 4649 }; 4650 4651 #define ELS_RDF_REG_TAG_CNT 4 4652 struct lpfc_els_rdf_reg_desc { 4653 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */ 4654 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4655 /* tags in reg_desc */ 4656 }; 4657 4658 struct lpfc_els_rdf_req { 4659 struct fc_els_rdf rdf; /* hdr up to descriptors */ 4660 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4661 }; 4662 4663 struct lpfc_els_rdf_rsp { 4664 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */ 4665 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4666 }; 4667 4668 union lpfc_wqe { 4669 uint32_t words[16]; 4670 struct lpfc_wqe_generic generic; 4671 struct fcp_icmnd64_wqe fcp_icmd; 4672 struct fcp_iread64_wqe fcp_iread; 4673 struct fcp_iwrite64_wqe fcp_iwrite; 4674 struct abort_cmd_wqe abort_cmd; 4675 struct create_xri_wqe create_xri; 4676 struct xmit_bcast64_wqe xmit_bcast64; 4677 struct xmit_seq64_wqe xmit_sequence; 4678 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4679 struct xmit_els_rsp64_wqe xmit_els_rsp; 4680 struct els_request64_wqe els_req; 4681 struct gen_req64_wqe gen_req; 4682 struct fcp_trsp64_wqe fcp_trsp; 4683 struct fcp_tsend64_wqe fcp_tsend; 4684 struct fcp_treceive64_wqe fcp_treceive; 4685 struct send_frame_wqe send_frame; 4686 }; 4687 4688 union lpfc_wqe128 { 4689 uint32_t words[32]; 4690 struct lpfc_wqe_generic generic; 4691 struct fcp_icmnd64_wqe fcp_icmd; 4692 struct fcp_iread64_wqe fcp_iread; 4693 struct fcp_iwrite64_wqe fcp_iwrite; 4694 struct abort_cmd_wqe abort_cmd; 4695 struct create_xri_wqe create_xri; 4696 struct xmit_bcast64_wqe xmit_bcast64; 4697 struct xmit_seq64_wqe xmit_sequence; 4698 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4699 struct xmit_els_rsp64_wqe xmit_els_rsp; 4700 struct els_request64_wqe els_req; 4701 struct gen_req64_wqe gen_req; 4702 struct fcp_trsp64_wqe fcp_trsp; 4703 struct fcp_tsend64_wqe fcp_tsend; 4704 struct fcp_treceive64_wqe fcp_treceive; 4705 struct send_frame_wqe send_frame; 4706 }; 4707 4708 #define MAGIC_NUMBER_G6 0xFEAA0003 4709 #define MAGIC_NUMBER_G7 0xFEAA0005 4710 4711 struct lpfc_grp_hdr { 4712 uint32_t size; 4713 uint32_t magic_number; 4714 uint32_t word2; 4715 #define lpfc_grp_hdr_file_type_SHIFT 24 4716 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4717 #define lpfc_grp_hdr_file_type_WORD word2 4718 #define lpfc_grp_hdr_id_SHIFT 16 4719 #define lpfc_grp_hdr_id_MASK 0x000000FF 4720 #define lpfc_grp_hdr_id_WORD word2 4721 uint8_t rev_name[128]; 4722 uint8_t date[12]; 4723 uint8_t revision[32]; 4724 }; 4725 4726 /* Defines for WQE command type */ 4727 #define FCP_COMMAND 0x0 4728 #define NVME_READ_CMD 0x0 4729 #define FCP_COMMAND_DATA_OUT 0x1 4730 #define NVME_WRITE_CMD 0x1 4731 #define COMMAND_DATA_IN 0x0 4732 #define COMMAND_DATA_OUT 0x1 4733 #define FCP_COMMAND_TRECEIVE 0x2 4734 #define FCP_COMMAND_TRSP 0x3 4735 #define FCP_COMMAND_TSEND 0x7 4736 #define OTHER_COMMAND 0x8 4737 #define ELS_COMMAND_NON_FIP 0xC 4738 #define ELS_COMMAND_FIP 0xD 4739 4740 #define LPFC_NVME_EMBED_CMD 0x0 4741 #define LPFC_NVME_EMBED_WRITE 0x1 4742 #define LPFC_NVME_EMBED_READ 0x2 4743 4744 /* WQE Commands */ 4745 #define CMD_ABORT_XRI_WQE 0x0F 4746 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4747 #define CMD_XMIT_BCAST64_WQE 0x84 4748 #define CMD_ELS_REQUEST64_WQE 0x8A 4749 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4750 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4751 #define CMD_FCP_IWRITE64_WQE 0x98 4752 #define CMD_FCP_IREAD64_WQE 0x9A 4753 #define CMD_FCP_ICMND64_WQE 0x9C 4754 #define CMD_FCP_TSEND64_WQE 0x9F 4755 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4756 #define CMD_FCP_TRSP64_WQE 0xA3 4757 #define CMD_GEN_REQUEST64_WQE 0xC2 4758 4759 #define CMD_WQE_MASK 0xff 4760 4761 4762 #define LPFC_FW_DUMP 1 4763 #define LPFC_FW_RESET 2 4764 #define LPFC_DV_RESET 3 4765