1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 /* Macros to deal with bit fields. Each bit field must have 3 #defines 24 * associated with it (_SHIFT, _MASK, and _WORD). 25 * EG. For a bit field that is in the 7th bit of the "field4" field of a 26 * structure and is 2 bits in size the following #defines must exist: 27 * struct temp { 28 * uint32_t field1; 29 * uint32_t field2; 30 * uint32_t field3; 31 * uint32_t field4; 32 * #define example_bit_field_SHIFT 7 33 * #define example_bit_field_MASK 0x03 34 * #define example_bit_field_WORD field4 35 * uint32_t field5; 36 * }; 37 * Then the macros below may be used to get or set the value of that field. 38 * EG. To get the value of the bit field from the above example: 39 * struct temp t1; 40 * value = bf_get(example_bit_field, &t1); 41 * And then to set that bit field: 42 * bf_set(example_bit_field, &t1, 2); 43 * Or clear that bit field: 44 * bf_set(example_bit_field, &t1, 0); 45 */ 46 #define bf_get_be32(name, ptr) \ 47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get_le32(name, ptr) \ 49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get(name, ptr) \ 51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 52 #define bf_set_le32(name, ptr, value) \ 53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 55 ~(name##_MASK << name##_SHIFT))))) 56 #define bf_set(name, ptr, value) \ 57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 59 60 struct dma_address { 61 uint32_t addr_lo; 62 uint32_t addr_hi; 63 }; 64 65 struct lpfc_sli_intf { 66 uint32_t word0; 67 #define lpfc_sli_intf_valid_SHIFT 29 68 #define lpfc_sli_intf_valid_MASK 0x00000007 69 #define lpfc_sli_intf_valid_WORD word0 70 #define LPFC_SLI_INTF_VALID 6 71 #define lpfc_sli_intf_sli_hint2_SHIFT 24 72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 73 #define lpfc_sli_intf_sli_hint2_WORD word0 74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 75 #define lpfc_sli_intf_sli_hint1_SHIFT 16 76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 77 #define lpfc_sli_intf_sli_hint1_WORD word0 78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 79 #define LPFC_SLI_INTF_SLI_HINT1_1 1 80 #define LPFC_SLI_INTF_SLI_HINT1_2 2 81 #define lpfc_sli_intf_if_type_SHIFT 12 82 #define lpfc_sli_intf_if_type_MASK 0x0000000F 83 #define lpfc_sli_intf_if_type_WORD word0 84 #define LPFC_SLI_INTF_IF_TYPE_0 0 85 #define LPFC_SLI_INTF_IF_TYPE_1 1 86 #define LPFC_SLI_INTF_IF_TYPE_2 2 87 #define LPFC_SLI_INTF_IF_TYPE_6 6 88 #define lpfc_sli_intf_sli_family_SHIFT 8 89 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 90 #define lpfc_sli_intf_sli_family_WORD word0 91 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 92 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 95 #define lpfc_sli_intf_slirev_SHIFT 4 96 #define lpfc_sli_intf_slirev_MASK 0x0000000F 97 #define lpfc_sli_intf_slirev_WORD word0 98 #define LPFC_SLI_INTF_REV_SLI3 3 99 #define LPFC_SLI_INTF_REV_SLI4 4 100 #define lpfc_sli_intf_func_type_SHIFT 0 101 #define lpfc_sli_intf_func_type_MASK 0x00000001 102 #define lpfc_sli_intf_func_type_WORD word0 103 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 104 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 105 }; 106 107 #define LPFC_SLI4_MBX_EMBED true 108 #define LPFC_SLI4_MBX_NEMBED false 109 110 #define LPFC_SLI4_MB_WORD_COUNT 64 111 #define LPFC_MAX_MQ_PAGE 8 112 #define LPFC_MAX_WQ_PAGE_V0 4 113 #define LPFC_MAX_WQ_PAGE 8 114 #define LPFC_MAX_RQ_PAGE 8 115 #define LPFC_MAX_CQ_PAGE 4 116 #define LPFC_MAX_EQ_PAGE 8 117 118 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 119 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 120 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 121 122 /* Define SLI4 Alignment requirements. */ 123 #define LPFC_ALIGN_16_BYTE 16 124 #define LPFC_ALIGN_64_BYTE 64 125 126 /* Define SLI4 specific definitions. */ 127 #define LPFC_MQ_CQE_BYTE_OFFSET 256 128 #define LPFC_MBX_CMD_HDR_LENGTH 16 129 #define LPFC_MBX_ERROR_RANGE 0x4000 130 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 131 #define LPFC_BMBX_BIT1_ADDR_LO 0 132 #define LPFC_RPI_HDR_COUNT 64 133 #define LPFC_HDR_TEMPLATE_SIZE 4096 134 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 135 #define LPFC_FCF_RECORD_WD_CNT 132 136 #define LPFC_ENTIRE_FCF_DATABASE 0 137 #define LPFC_DFLT_FCF_INDEX 0 138 139 /* Virtual function numbers */ 140 #define LPFC_VF0 0 141 #define LPFC_VF1 1 142 #define LPFC_VF2 2 143 #define LPFC_VF3 3 144 #define LPFC_VF4 4 145 #define LPFC_VF5 5 146 #define LPFC_VF6 6 147 #define LPFC_VF7 7 148 #define LPFC_VF8 8 149 #define LPFC_VF9 9 150 #define LPFC_VF10 10 151 #define LPFC_VF11 11 152 #define LPFC_VF12 12 153 #define LPFC_VF13 13 154 #define LPFC_VF14 14 155 #define LPFC_VF15 15 156 #define LPFC_VF16 16 157 #define LPFC_VF17 17 158 #define LPFC_VF18 18 159 #define LPFC_VF19 19 160 #define LPFC_VF20 20 161 #define LPFC_VF21 21 162 #define LPFC_VF22 22 163 #define LPFC_VF23 23 164 #define LPFC_VF24 24 165 #define LPFC_VF25 25 166 #define LPFC_VF26 26 167 #define LPFC_VF27 27 168 #define LPFC_VF28 28 169 #define LPFC_VF29 29 170 #define LPFC_VF30 30 171 #define LPFC_VF31 31 172 173 /* PCI function numbers */ 174 #define LPFC_PCI_FUNC0 0 175 #define LPFC_PCI_FUNC1 1 176 #define LPFC_PCI_FUNC2 2 177 #define LPFC_PCI_FUNC3 3 178 #define LPFC_PCI_FUNC4 4 179 180 /* SLI4 interface type-2 PDEV_CTL register */ 181 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 182 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 183 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 184 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 185 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 186 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 188 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 189 190 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 191 192 /* Active interrupt test count */ 193 #define LPFC_ACT_INTR_CNT 4 194 195 /* Algrithmns for scheduling FCP commands to WQs */ 196 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 197 #define LPFC_FCP_SCHED_BY_CPU 1 198 199 /* Delay Multiplier constant */ 200 #define LPFC_DMULT_CONST 651042 201 #define LPFC_DMULT_MAX 1023 202 203 /* Configuration of Interrupts / sec for entire HBA port */ 204 #define LPFC_MIN_IMAX 5000 205 #define LPFC_MAX_IMAX 5000000 206 #define LPFC_DEF_IMAX 150000 207 208 #define LPFC_MIN_CPU_MAP 0 209 #define LPFC_MAX_CPU_MAP 2 210 #define LPFC_HBA_CPU_MAP 1 211 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 212 213 /* PORT_CAPABILITIES constants. */ 214 #define LPFC_MAX_SUPPORTED_PAGES 8 215 216 struct ulp_bde64 { 217 union ULP_BDE_TUS { 218 uint32_t w; 219 struct { 220 #ifdef __BIG_ENDIAN_BITFIELD 221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 222 VALUE !! */ 223 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 224 #else /* __LITTLE_ENDIAN_BITFIELD */ 225 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 226 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 227 VALUE !! */ 228 #endif 229 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 230 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 231 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 232 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 233 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 234 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 235 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 236 } f; 237 } tus; 238 uint32_t addrLow; 239 uint32_t addrHigh; 240 }; 241 242 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 243 #define LPFC_MAX_BDE_IMM_SIZE 64 244 245 struct lpfc_sli4_flags { 246 uint32_t word0; 247 #define lpfc_idx_rsrc_rdy_SHIFT 0 248 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 249 #define lpfc_idx_rsrc_rdy_WORD word0 250 #define LPFC_IDX_RSRC_RDY 1 251 #define lpfc_rpi_rsrc_rdy_SHIFT 1 252 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 253 #define lpfc_rpi_rsrc_rdy_WORD word0 254 #define LPFC_RPI_RSRC_RDY 1 255 #define lpfc_vpi_rsrc_rdy_SHIFT 2 256 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 257 #define lpfc_vpi_rsrc_rdy_WORD word0 258 #define LPFC_VPI_RSRC_RDY 1 259 #define lpfc_vfi_rsrc_rdy_SHIFT 3 260 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 261 #define lpfc_vfi_rsrc_rdy_WORD word0 262 #define LPFC_VFI_RSRC_RDY 1 263 }; 264 265 struct sli4_bls_rsp { 266 uint32_t word0_rsvd; /* Word0 must be reserved */ 267 uint32_t word1; 268 #define lpfc_abts_orig_SHIFT 0 269 #define lpfc_abts_orig_MASK 0x00000001 270 #define lpfc_abts_orig_WORD word1 271 #define LPFC_ABTS_UNSOL_RSP 1 272 #define LPFC_ABTS_UNSOL_INT 0 273 uint32_t word2; 274 #define lpfc_abts_rxid_SHIFT 0 275 #define lpfc_abts_rxid_MASK 0x0000FFFF 276 #define lpfc_abts_rxid_WORD word2 277 #define lpfc_abts_oxid_SHIFT 16 278 #define lpfc_abts_oxid_MASK 0x0000FFFF 279 #define lpfc_abts_oxid_WORD word2 280 uint32_t word3; 281 #define lpfc_vndr_code_SHIFT 0 282 #define lpfc_vndr_code_MASK 0x000000FF 283 #define lpfc_vndr_code_WORD word3 284 #define lpfc_rsn_expln_SHIFT 8 285 #define lpfc_rsn_expln_MASK 0x000000FF 286 #define lpfc_rsn_expln_WORD word3 287 #define lpfc_rsn_code_SHIFT 16 288 #define lpfc_rsn_code_MASK 0x000000FF 289 #define lpfc_rsn_code_WORD word3 290 291 uint32_t word4; 292 uint32_t word5_rsvd; /* Word5 must be reserved */ 293 }; 294 295 /* event queue entry structure */ 296 struct lpfc_eqe { 297 uint32_t word0; 298 #define lpfc_eqe_resource_id_SHIFT 16 299 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 300 #define lpfc_eqe_resource_id_WORD word0 301 #define lpfc_eqe_minor_code_SHIFT 4 302 #define lpfc_eqe_minor_code_MASK 0x00000FFF 303 #define lpfc_eqe_minor_code_WORD word0 304 #define lpfc_eqe_major_code_SHIFT 1 305 #define lpfc_eqe_major_code_MASK 0x00000007 306 #define lpfc_eqe_major_code_WORD word0 307 #define lpfc_eqe_valid_SHIFT 0 308 #define lpfc_eqe_valid_MASK 0x00000001 309 #define lpfc_eqe_valid_WORD word0 310 }; 311 312 /* completion queue entry structure (common fields for all cqe types) */ 313 struct lpfc_cqe { 314 uint32_t reserved0; 315 uint32_t reserved1; 316 uint32_t reserved2; 317 uint32_t word3; 318 #define lpfc_cqe_valid_SHIFT 31 319 #define lpfc_cqe_valid_MASK 0x00000001 320 #define lpfc_cqe_valid_WORD word3 321 #define lpfc_cqe_code_SHIFT 16 322 #define lpfc_cqe_code_MASK 0x000000FF 323 #define lpfc_cqe_code_WORD word3 324 }; 325 326 /* Completion Queue Entry Status Codes */ 327 #define CQE_STATUS_SUCCESS 0x0 328 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 329 #define CQE_STATUS_REMOTE_STOP 0x2 330 #define CQE_STATUS_LOCAL_REJECT 0x3 331 #define CQE_STATUS_NPORT_RJT 0x4 332 #define CQE_STATUS_FABRIC_RJT 0x5 333 #define CQE_STATUS_NPORT_BSY 0x6 334 #define CQE_STATUS_FABRIC_BSY 0x7 335 #define CQE_STATUS_INTERMED_RSP 0x8 336 #define CQE_STATUS_LS_RJT 0x9 337 #define CQE_STATUS_CMD_REJECT 0xb 338 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 339 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 340 #define CQE_STATUS_DI_ERROR 0x16 341 342 /* Used when mapping CQE status to IOCB */ 343 #define LPFC_IOCB_STATUS_MASK 0xf 344 345 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 346 #define CQE_HW_STATUS_NO_ERR 0x0 347 #define CQE_HW_STATUS_UNDERRUN 0x1 348 #define CQE_HW_STATUS_OVERRUN 0x2 349 350 /* Completion Queue Entry Codes */ 351 #define CQE_CODE_COMPL_WQE 0x1 352 #define CQE_CODE_RELEASE_WQE 0x2 353 #define CQE_CODE_RECEIVE 0x4 354 #define CQE_CODE_XRI_ABORTED 0x5 355 #define CQE_CODE_RECEIVE_V1 0x9 356 #define CQE_CODE_NVME_ERSP 0xd 357 358 /* 359 * Define mask value for xri_aborted and wcqe completed CQE extended status. 360 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 361 */ 362 #define WCQE_PARAM_MASK 0x1FF 363 364 /* completion queue entry for wqe completions */ 365 struct lpfc_wcqe_complete { 366 uint32_t word0; 367 #define lpfc_wcqe_c_request_tag_SHIFT 16 368 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 369 #define lpfc_wcqe_c_request_tag_WORD word0 370 #define lpfc_wcqe_c_status_SHIFT 8 371 #define lpfc_wcqe_c_status_MASK 0x000000FF 372 #define lpfc_wcqe_c_status_WORD word0 373 #define lpfc_wcqe_c_hw_status_SHIFT 0 374 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 375 #define lpfc_wcqe_c_hw_status_WORD word0 376 #define lpfc_wcqe_c_ersp0_SHIFT 0 377 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 378 #define lpfc_wcqe_c_ersp0_WORD word0 379 uint32_t total_data_placed; 380 uint32_t parameter; 381 #define lpfc_wcqe_c_bg_edir_SHIFT 5 382 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 383 #define lpfc_wcqe_c_bg_edir_WORD parameter 384 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 385 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 386 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 387 #define lpfc_wcqe_c_bg_re_SHIFT 2 388 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 389 #define lpfc_wcqe_c_bg_re_WORD parameter 390 #define lpfc_wcqe_c_bg_ae_SHIFT 1 391 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 392 #define lpfc_wcqe_c_bg_ae_WORD parameter 393 #define lpfc_wcqe_c_bg_ge_SHIFT 0 394 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 395 #define lpfc_wcqe_c_bg_ge_WORD parameter 396 uint32_t word3; 397 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 398 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 399 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 400 #define lpfc_wcqe_c_xb_SHIFT 28 401 #define lpfc_wcqe_c_xb_MASK 0x00000001 402 #define lpfc_wcqe_c_xb_WORD word3 403 #define lpfc_wcqe_c_pv_SHIFT 27 404 #define lpfc_wcqe_c_pv_MASK 0x00000001 405 #define lpfc_wcqe_c_pv_WORD word3 406 #define lpfc_wcqe_c_priority_SHIFT 24 407 #define lpfc_wcqe_c_priority_MASK 0x00000007 408 #define lpfc_wcqe_c_priority_WORD word3 409 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 410 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 411 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 412 #define lpfc_wcqe_c_sqhead_SHIFT 0 413 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 414 #define lpfc_wcqe_c_sqhead_WORD word3 415 }; 416 417 /* completion queue entry for wqe release */ 418 struct lpfc_wcqe_release { 419 uint32_t reserved0; 420 uint32_t reserved1; 421 uint32_t word2; 422 #define lpfc_wcqe_r_wq_id_SHIFT 16 423 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 424 #define lpfc_wcqe_r_wq_id_WORD word2 425 #define lpfc_wcqe_r_wqe_index_SHIFT 0 426 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 427 #define lpfc_wcqe_r_wqe_index_WORD word2 428 uint32_t word3; 429 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 430 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 431 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 432 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 433 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 434 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 435 }; 436 437 struct sli4_wcqe_xri_aborted { 438 uint32_t word0; 439 #define lpfc_wcqe_xa_status_SHIFT 8 440 #define lpfc_wcqe_xa_status_MASK 0x000000FF 441 #define lpfc_wcqe_xa_status_WORD word0 442 uint32_t parameter; 443 uint32_t word2; 444 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 445 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 446 #define lpfc_wcqe_xa_remote_xid_WORD word2 447 #define lpfc_wcqe_xa_xri_SHIFT 0 448 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 449 #define lpfc_wcqe_xa_xri_WORD word2 450 uint32_t word3; 451 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 452 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 453 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 454 #define lpfc_wcqe_xa_ia_SHIFT 30 455 #define lpfc_wcqe_xa_ia_MASK 0x00000001 456 #define lpfc_wcqe_xa_ia_WORD word3 457 #define CQE_XRI_ABORTED_IA_REMOTE 0 458 #define CQE_XRI_ABORTED_IA_LOCAL 1 459 #define lpfc_wcqe_xa_br_SHIFT 29 460 #define lpfc_wcqe_xa_br_MASK 0x00000001 461 #define lpfc_wcqe_xa_br_WORD word3 462 #define CQE_XRI_ABORTED_BR_BA_ACC 0 463 #define CQE_XRI_ABORTED_BR_BA_RJT 1 464 #define lpfc_wcqe_xa_eo_SHIFT 28 465 #define lpfc_wcqe_xa_eo_MASK 0x00000001 466 #define lpfc_wcqe_xa_eo_WORD word3 467 #define CQE_XRI_ABORTED_EO_REMOTE 0 468 #define CQE_XRI_ABORTED_EO_LOCAL 1 469 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 470 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 471 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 472 }; 473 474 /* completion queue entry structure for rqe completion */ 475 struct lpfc_rcqe { 476 uint32_t word0; 477 #define lpfc_rcqe_bindex_SHIFT 16 478 #define lpfc_rcqe_bindex_MASK 0x0000FFF 479 #define lpfc_rcqe_bindex_WORD word0 480 #define lpfc_rcqe_status_SHIFT 8 481 #define lpfc_rcqe_status_MASK 0x000000FF 482 #define lpfc_rcqe_status_WORD word0 483 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 484 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 485 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 486 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 487 uint32_t word1; 488 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 489 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 490 #define lpfc_rcqe_fcf_id_v1_WORD word1 491 uint32_t word2; 492 #define lpfc_rcqe_length_SHIFT 16 493 #define lpfc_rcqe_length_MASK 0x0000FFFF 494 #define lpfc_rcqe_length_WORD word2 495 #define lpfc_rcqe_rq_id_SHIFT 6 496 #define lpfc_rcqe_rq_id_MASK 0x000003FF 497 #define lpfc_rcqe_rq_id_WORD word2 498 #define lpfc_rcqe_fcf_id_SHIFT 0 499 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 500 #define lpfc_rcqe_fcf_id_WORD word2 501 #define lpfc_rcqe_rq_id_v1_SHIFT 0 502 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 503 #define lpfc_rcqe_rq_id_v1_WORD word2 504 uint32_t word3; 505 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 506 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 507 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 508 #define lpfc_rcqe_port_SHIFT 30 509 #define lpfc_rcqe_port_MASK 0x00000001 510 #define lpfc_rcqe_port_WORD word3 511 #define lpfc_rcqe_hdr_length_SHIFT 24 512 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 513 #define lpfc_rcqe_hdr_length_WORD word3 514 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 515 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 516 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 517 #define lpfc_rcqe_eof_SHIFT 8 518 #define lpfc_rcqe_eof_MASK 0x000000FF 519 #define lpfc_rcqe_eof_WORD word3 520 #define FCOE_EOFn 0x41 521 #define FCOE_EOFt 0x42 522 #define FCOE_EOFni 0x49 523 #define FCOE_EOFa 0x50 524 #define lpfc_rcqe_sof_SHIFT 0 525 #define lpfc_rcqe_sof_MASK 0x000000FF 526 #define lpfc_rcqe_sof_WORD word3 527 #define FCOE_SOFi2 0x2d 528 #define FCOE_SOFi3 0x2e 529 #define FCOE_SOFn2 0x35 530 #define FCOE_SOFn3 0x36 531 }; 532 533 struct lpfc_rqe { 534 uint32_t address_hi; 535 uint32_t address_lo; 536 }; 537 538 /* buffer descriptors */ 539 struct lpfc_bde4 { 540 uint32_t addr_hi; 541 uint32_t addr_lo; 542 uint32_t word2; 543 #define lpfc_bde4_last_SHIFT 31 544 #define lpfc_bde4_last_MASK 0x00000001 545 #define lpfc_bde4_last_WORD word2 546 #define lpfc_bde4_sge_offset_SHIFT 0 547 #define lpfc_bde4_sge_offset_MASK 0x000003FF 548 #define lpfc_bde4_sge_offset_WORD word2 549 uint32_t word3; 550 #define lpfc_bde4_length_SHIFT 0 551 #define lpfc_bde4_length_MASK 0x000000FF 552 #define lpfc_bde4_length_WORD word3 553 }; 554 555 struct lpfc_register { 556 uint32_t word0; 557 }; 558 559 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 560 #define LPFC_PORT_SEM_MASK 0xF000 561 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 562 #define LPFC_UERR_STATUS_HI 0x00A4 563 #define LPFC_UERR_STATUS_LO 0x00A0 564 #define LPFC_UE_MASK_HI 0x00AC 565 #define LPFC_UE_MASK_LO 0x00A8 566 567 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 568 #define LPFC_SLI_INTF 0x0058 569 570 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 571 #define lpfc_port_smphr_perr_SHIFT 31 572 #define lpfc_port_smphr_perr_MASK 0x1 573 #define lpfc_port_smphr_perr_WORD word0 574 #define lpfc_port_smphr_sfi_SHIFT 30 575 #define lpfc_port_smphr_sfi_MASK 0x1 576 #define lpfc_port_smphr_sfi_WORD word0 577 #define lpfc_port_smphr_nip_SHIFT 29 578 #define lpfc_port_smphr_nip_MASK 0x1 579 #define lpfc_port_smphr_nip_WORD word0 580 #define lpfc_port_smphr_ipc_SHIFT 28 581 #define lpfc_port_smphr_ipc_MASK 0x1 582 #define lpfc_port_smphr_ipc_WORD word0 583 #define lpfc_port_smphr_scr1_SHIFT 27 584 #define lpfc_port_smphr_scr1_MASK 0x1 585 #define lpfc_port_smphr_scr1_WORD word0 586 #define lpfc_port_smphr_scr2_SHIFT 26 587 #define lpfc_port_smphr_scr2_MASK 0x1 588 #define lpfc_port_smphr_scr2_WORD word0 589 #define lpfc_port_smphr_host_scratch_SHIFT 16 590 #define lpfc_port_smphr_host_scratch_MASK 0xFF 591 #define lpfc_port_smphr_host_scratch_WORD word0 592 #define lpfc_port_smphr_port_status_SHIFT 0 593 #define lpfc_port_smphr_port_status_MASK 0xFFFF 594 #define lpfc_port_smphr_port_status_WORD word0 595 596 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 597 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 598 #define LPFC_POST_STAGE_HOST_RDY 0x0002 599 #define LPFC_POST_STAGE_BE_RESET 0x0003 600 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 601 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 602 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 603 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 604 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 605 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 606 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 607 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 608 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 609 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 610 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 611 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 612 #define LPFC_POST_STAGE_ARMFW_START 0x0800 613 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 614 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 615 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 616 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 617 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 618 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 619 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 620 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 621 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 622 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 623 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 624 #define LPFC_POST_STAGE_RC_DONE 0x0B07 625 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 626 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 627 #define LPFC_POST_STAGE_PORT_READY 0xC000 628 #define LPFC_POST_STAGE_PORT_UE 0xF000 629 630 #define LPFC_CTL_PORT_STA_OFFSET 0x404 631 #define lpfc_sliport_status_err_SHIFT 31 632 #define lpfc_sliport_status_err_MASK 0x1 633 #define lpfc_sliport_status_err_WORD word0 634 #define lpfc_sliport_status_end_SHIFT 30 635 #define lpfc_sliport_status_end_MASK 0x1 636 #define lpfc_sliport_status_end_WORD word0 637 #define lpfc_sliport_status_oti_SHIFT 29 638 #define lpfc_sliport_status_oti_MASK 0x1 639 #define lpfc_sliport_status_oti_WORD word0 640 #define lpfc_sliport_status_rn_SHIFT 24 641 #define lpfc_sliport_status_rn_MASK 0x1 642 #define lpfc_sliport_status_rn_WORD word0 643 #define lpfc_sliport_status_rdy_SHIFT 23 644 #define lpfc_sliport_status_rdy_MASK 0x1 645 #define lpfc_sliport_status_rdy_WORD word0 646 #define MAX_IF_TYPE_2_RESETS 6 647 648 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 649 #define lpfc_sliport_ctrl_end_SHIFT 30 650 #define lpfc_sliport_ctrl_end_MASK 0x1 651 #define lpfc_sliport_ctrl_end_WORD word0 652 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 653 #define LPFC_SLIPORT_BIG_ENDIAN 1 654 #define lpfc_sliport_ctrl_ip_SHIFT 27 655 #define lpfc_sliport_ctrl_ip_MASK 0x1 656 #define lpfc_sliport_ctrl_ip_WORD word0 657 #define LPFC_SLIPORT_INIT_PORT 1 658 659 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 660 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 661 662 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 663 #define lpfc_sliport_eqdelay_delay_SHIFT 16 664 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 665 #define lpfc_sliport_eqdelay_delay_WORD word0 666 #define lpfc_sliport_eqdelay_id_SHIFT 0 667 #define lpfc_sliport_eqdelay_id_MASK 0xfff 668 #define lpfc_sliport_eqdelay_id_WORD word0 669 #define LPFC_SEC_TO_USEC 1000000 670 671 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 672 * reside in BAR 2. 673 */ 674 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 675 676 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 677 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 678 679 #define LPFC_HST_ISR0 0x0C18 680 #define LPFC_HST_ISR1 0x0C1C 681 #define LPFC_HST_ISR2 0x0C20 682 #define LPFC_HST_ISR3 0x0C24 683 #define LPFC_HST_ISR4 0x0C28 684 685 #define LPFC_HST_IMR0 0x0C48 686 #define LPFC_HST_IMR1 0x0C4C 687 #define LPFC_HST_IMR2 0x0C50 688 #define LPFC_HST_IMR3 0x0C54 689 #define LPFC_HST_IMR4 0x0C58 690 691 #define LPFC_HST_ISCR0 0x0C78 692 #define LPFC_HST_ISCR1 0x0C7C 693 #define LPFC_HST_ISCR2 0x0C80 694 #define LPFC_HST_ISCR3 0x0C84 695 #define LPFC_HST_ISCR4 0x0C88 696 697 #define LPFC_SLI4_INTR0 BIT0 698 #define LPFC_SLI4_INTR1 BIT1 699 #define LPFC_SLI4_INTR2 BIT2 700 #define LPFC_SLI4_INTR3 BIT3 701 #define LPFC_SLI4_INTR4 BIT4 702 #define LPFC_SLI4_INTR5 BIT5 703 #define LPFC_SLI4_INTR6 BIT6 704 #define LPFC_SLI4_INTR7 BIT7 705 #define LPFC_SLI4_INTR8 BIT8 706 #define LPFC_SLI4_INTR9 BIT9 707 #define LPFC_SLI4_INTR10 BIT10 708 #define LPFC_SLI4_INTR11 BIT11 709 #define LPFC_SLI4_INTR12 BIT12 710 #define LPFC_SLI4_INTR13 BIT13 711 #define LPFC_SLI4_INTR14 BIT14 712 #define LPFC_SLI4_INTR15 BIT15 713 #define LPFC_SLI4_INTR16 BIT16 714 #define LPFC_SLI4_INTR17 BIT17 715 #define LPFC_SLI4_INTR18 BIT18 716 #define LPFC_SLI4_INTR19 BIT19 717 #define LPFC_SLI4_INTR20 BIT20 718 #define LPFC_SLI4_INTR21 BIT21 719 #define LPFC_SLI4_INTR22 BIT22 720 #define LPFC_SLI4_INTR23 BIT23 721 #define LPFC_SLI4_INTR24 BIT24 722 #define LPFC_SLI4_INTR25 BIT25 723 #define LPFC_SLI4_INTR26 BIT26 724 #define LPFC_SLI4_INTR27 BIT27 725 #define LPFC_SLI4_INTR28 BIT28 726 #define LPFC_SLI4_INTR29 BIT29 727 #define LPFC_SLI4_INTR30 BIT30 728 #define LPFC_SLI4_INTR31 BIT31 729 730 /* 731 * The Doorbell registers defined here exist in different BAR 732 * register sets depending on the UCNA Port's reported if_type 733 * value. For UCNA ports running SLI4 and if_type 0, they reside in 734 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 735 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 736 * BAR2. The offsets and base address are different, so the driver 737 * has to compute the register addresses accordingly 738 */ 739 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 740 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 741 #define LPFC_IF6_RQ_DOORBELL 0x0080 742 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 743 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 744 #define lpfc_rq_db_list_fm_num_posted_WORD word0 745 #define lpfc_rq_db_list_fm_index_SHIFT 16 746 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 747 #define lpfc_rq_db_list_fm_index_WORD word0 748 #define lpfc_rq_db_list_fm_id_SHIFT 0 749 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 750 #define lpfc_rq_db_list_fm_id_WORD word0 751 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 752 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 753 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 754 #define lpfc_rq_db_ring_fm_id_SHIFT 0 755 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 756 #define lpfc_rq_db_ring_fm_id_WORD word0 757 758 #define LPFC_ULP0_WQ_DOORBELL 0x0040 759 #define LPFC_ULP1_WQ_DOORBELL 0x0060 760 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 761 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 762 #define lpfc_wq_db_list_fm_num_posted_WORD word0 763 #define lpfc_wq_db_list_fm_index_SHIFT 16 764 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 765 #define lpfc_wq_db_list_fm_index_WORD word0 766 #define lpfc_wq_db_list_fm_id_SHIFT 0 767 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 768 #define lpfc_wq_db_list_fm_id_WORD word0 769 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 770 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 771 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 772 #define lpfc_wq_db_ring_fm_id_SHIFT 0 773 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 774 #define lpfc_wq_db_ring_fm_id_WORD word0 775 776 #define LPFC_IF6_WQ_DOORBELL 0x0040 777 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 778 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 779 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 780 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 781 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 782 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 783 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 784 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 785 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 786 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 787 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 788 #define lpfc_if6_wq_db_list_fm_id_WORD word0 789 790 #define LPFC_EQCQ_DOORBELL 0x0120 791 #define lpfc_eqcq_doorbell_se_SHIFT 31 792 #define lpfc_eqcq_doorbell_se_MASK 0x0001 793 #define lpfc_eqcq_doorbell_se_WORD word0 794 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 795 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 796 #define lpfc_eqcq_doorbell_arm_SHIFT 29 797 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 798 #define lpfc_eqcq_doorbell_arm_WORD word0 799 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 800 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 801 #define lpfc_eqcq_doorbell_num_released_WORD word0 802 #define lpfc_eqcq_doorbell_qt_SHIFT 10 803 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 804 #define lpfc_eqcq_doorbell_qt_WORD word0 805 #define LPFC_QUEUE_TYPE_COMPLETION 0 806 #define LPFC_QUEUE_TYPE_EVENT 1 807 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 808 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 809 #define lpfc_eqcq_doorbell_eqci_WORD word0 810 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 811 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 812 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 813 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 814 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 815 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 816 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 817 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 818 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 819 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 820 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 821 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 822 #define LPFC_CQID_HI_FIELD_SHIFT 10 823 #define LPFC_EQID_HI_FIELD_SHIFT 9 824 825 #define LPFC_IF6_CQ_DOORBELL 0x00C0 826 #define lpfc_if6_cq_doorbell_se_SHIFT 31 827 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 828 #define lpfc_if6_cq_doorbell_se_WORD word0 829 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 830 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 831 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 832 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 833 #define lpfc_if6_cq_doorbell_arm_WORD word0 834 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 835 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 836 #define lpfc_if6_cq_doorbell_num_released_WORD word0 837 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 838 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 839 #define lpfc_if6_cq_doorbell_cqid_WORD word0 840 841 #define LPFC_IF6_EQ_DOORBELL 0x0120 842 #define lpfc_if6_eq_doorbell_io_SHIFT 31 843 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 844 #define lpfc_if6_eq_doorbell_io_WORD word0 845 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 846 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 847 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 848 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 849 #define lpfc_if6_eq_doorbell_arm_WORD word0 850 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 851 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 852 #define lpfc_if6_eq_doorbell_num_released_WORD word0 853 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 854 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 855 #define lpfc_if6_eq_doorbell_eqid_WORD word0 856 857 #define LPFC_BMBX 0x0160 858 #define lpfc_bmbx_addr_SHIFT 2 859 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 860 #define lpfc_bmbx_addr_WORD word0 861 #define lpfc_bmbx_hi_SHIFT 1 862 #define lpfc_bmbx_hi_MASK 0x0001 863 #define lpfc_bmbx_hi_WORD word0 864 #define lpfc_bmbx_rdy_SHIFT 0 865 #define lpfc_bmbx_rdy_MASK 0x0001 866 #define lpfc_bmbx_rdy_WORD word0 867 868 #define LPFC_MQ_DOORBELL 0x0140 869 #define LPFC_IF6_MQ_DOORBELL 0x0160 870 #define lpfc_mq_doorbell_num_posted_SHIFT 16 871 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 872 #define lpfc_mq_doorbell_num_posted_WORD word0 873 #define lpfc_mq_doorbell_id_SHIFT 0 874 #define lpfc_mq_doorbell_id_MASK 0xFFFF 875 #define lpfc_mq_doorbell_id_WORD word0 876 877 struct lpfc_sli4_cfg_mhdr { 878 uint32_t word1; 879 #define lpfc_mbox_hdr_emb_SHIFT 0 880 #define lpfc_mbox_hdr_emb_MASK 0x00000001 881 #define lpfc_mbox_hdr_emb_WORD word1 882 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 883 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 884 #define lpfc_mbox_hdr_sge_cnt_WORD word1 885 uint32_t payload_length; 886 uint32_t tag_lo; 887 uint32_t tag_hi; 888 uint32_t reserved5; 889 }; 890 891 union lpfc_sli4_cfg_shdr { 892 struct { 893 uint32_t word6; 894 #define lpfc_mbox_hdr_opcode_SHIFT 0 895 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 896 #define lpfc_mbox_hdr_opcode_WORD word6 897 #define lpfc_mbox_hdr_subsystem_SHIFT 8 898 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 899 #define lpfc_mbox_hdr_subsystem_WORD word6 900 #define lpfc_mbox_hdr_port_number_SHIFT 16 901 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 902 #define lpfc_mbox_hdr_port_number_WORD word6 903 #define lpfc_mbox_hdr_domain_SHIFT 24 904 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 905 #define lpfc_mbox_hdr_domain_WORD word6 906 uint32_t timeout; 907 uint32_t request_length; 908 uint32_t word9; 909 #define lpfc_mbox_hdr_version_SHIFT 0 910 #define lpfc_mbox_hdr_version_MASK 0x000000FF 911 #define lpfc_mbox_hdr_version_WORD word9 912 #define lpfc_mbox_hdr_pf_num_SHIFT 16 913 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 914 #define lpfc_mbox_hdr_pf_num_WORD word9 915 #define lpfc_mbox_hdr_vh_num_SHIFT 24 916 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 917 #define lpfc_mbox_hdr_vh_num_WORD word9 918 #define LPFC_Q_CREATE_VERSION_2 2 919 #define LPFC_Q_CREATE_VERSION_1 1 920 #define LPFC_Q_CREATE_VERSION_0 0 921 #define LPFC_OPCODE_VERSION_0 0 922 #define LPFC_OPCODE_VERSION_1 1 923 } request; 924 struct { 925 uint32_t word6; 926 #define lpfc_mbox_hdr_opcode_SHIFT 0 927 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 928 #define lpfc_mbox_hdr_opcode_WORD word6 929 #define lpfc_mbox_hdr_subsystem_SHIFT 8 930 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 931 #define lpfc_mbox_hdr_subsystem_WORD word6 932 #define lpfc_mbox_hdr_domain_SHIFT 24 933 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 934 #define lpfc_mbox_hdr_domain_WORD word6 935 uint32_t word7; 936 #define lpfc_mbox_hdr_status_SHIFT 0 937 #define lpfc_mbox_hdr_status_MASK 0x000000FF 938 #define lpfc_mbox_hdr_status_WORD word7 939 #define lpfc_mbox_hdr_add_status_SHIFT 8 940 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 941 #define lpfc_mbox_hdr_add_status_WORD word7 942 uint32_t response_length; 943 uint32_t actual_response_length; 944 } response; 945 }; 946 947 /* Mailbox Header structures. 948 * struct mbox_header is defined for first generation SLI4_CFG mailbox 949 * calls deployed for BE-based ports. 950 * 951 * struct sli4_mbox_header is defined for second generation SLI4 952 * ports that don't deploy the SLI4_CFG mechanism. 953 */ 954 struct mbox_header { 955 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 956 union lpfc_sli4_cfg_shdr cfg_shdr; 957 }; 958 959 #define LPFC_EXTENT_LOCAL 0 960 #define LPFC_TIMEOUT_DEFAULT 0 961 #define LPFC_EXTENT_VERSION_DEFAULT 0 962 963 /* Subsystem Definitions */ 964 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 965 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 966 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 967 968 /* Device Specific Definitions */ 969 970 /* The HOST ENDIAN defines are in Big Endian format. */ 971 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 972 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 973 974 /* Common Opcodes */ 975 #define LPFC_MBOX_OPCODE_NA 0x00 976 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 977 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 978 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 979 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 980 #define LPFC_MBOX_OPCODE_NOP 0x21 981 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 982 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 983 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 984 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 985 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 986 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 987 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 988 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 989 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 990 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 991 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 992 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 993 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 994 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 995 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 996 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 997 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 998 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 999 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1000 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1001 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1002 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1003 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1004 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1005 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1006 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1007 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1008 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1009 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1010 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1011 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1012 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1013 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1014 1015 /* FCoE Opcodes */ 1016 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1017 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1018 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1019 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1020 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1021 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1022 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1023 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1024 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1025 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1026 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1027 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1028 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1029 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1030 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1031 1032 /* Mailbox command structures */ 1033 struct eq_context { 1034 uint32_t word0; 1035 #define lpfc_eq_context_size_SHIFT 31 1036 #define lpfc_eq_context_size_MASK 0x00000001 1037 #define lpfc_eq_context_size_WORD word0 1038 #define LPFC_EQE_SIZE_4 0x0 1039 #define LPFC_EQE_SIZE_16 0x1 1040 #define lpfc_eq_context_valid_SHIFT 29 1041 #define lpfc_eq_context_valid_MASK 0x00000001 1042 #define lpfc_eq_context_valid_WORD word0 1043 #define lpfc_eq_context_autovalid_SHIFT 28 1044 #define lpfc_eq_context_autovalid_MASK 0x00000001 1045 #define lpfc_eq_context_autovalid_WORD word0 1046 uint32_t word1; 1047 #define lpfc_eq_context_count_SHIFT 26 1048 #define lpfc_eq_context_count_MASK 0x00000003 1049 #define lpfc_eq_context_count_WORD word1 1050 #define LPFC_EQ_CNT_256 0x0 1051 #define LPFC_EQ_CNT_512 0x1 1052 #define LPFC_EQ_CNT_1024 0x2 1053 #define LPFC_EQ_CNT_2048 0x3 1054 #define LPFC_EQ_CNT_4096 0x4 1055 uint32_t word2; 1056 #define lpfc_eq_context_delay_multi_SHIFT 13 1057 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1058 #define lpfc_eq_context_delay_multi_WORD word2 1059 uint32_t reserved3; 1060 }; 1061 1062 struct eq_delay_info { 1063 uint32_t eq_id; 1064 uint32_t phase; 1065 uint32_t delay_multi; 1066 }; 1067 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1068 1069 struct sgl_page_pairs { 1070 uint32_t sgl_pg0_addr_lo; 1071 uint32_t sgl_pg0_addr_hi; 1072 uint32_t sgl_pg1_addr_lo; 1073 uint32_t sgl_pg1_addr_hi; 1074 }; 1075 1076 struct lpfc_mbx_post_sgl_pages { 1077 struct mbox_header header; 1078 uint32_t word0; 1079 #define lpfc_post_sgl_pages_xri_SHIFT 0 1080 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1081 #define lpfc_post_sgl_pages_xri_WORD word0 1082 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1083 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1084 #define lpfc_post_sgl_pages_xricnt_WORD word0 1085 struct sgl_page_pairs sgl_pg_pairs[1]; 1086 }; 1087 1088 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1089 struct lpfc_mbx_post_uembed_sgl_page1 { 1090 union lpfc_sli4_cfg_shdr cfg_shdr; 1091 uint32_t word0; 1092 struct sgl_page_pairs sgl_pg_pairs; 1093 }; 1094 1095 struct lpfc_mbx_sge { 1096 uint32_t pa_lo; 1097 uint32_t pa_hi; 1098 uint32_t length; 1099 }; 1100 1101 struct lpfc_mbx_nembed_cmd { 1102 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1103 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1104 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1105 }; 1106 1107 struct lpfc_mbx_nembed_sge_virt { 1108 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1109 }; 1110 1111 struct lpfc_mbx_eq_create { 1112 struct mbox_header header; 1113 union { 1114 struct { 1115 uint32_t word0; 1116 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1117 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1118 #define lpfc_mbx_eq_create_num_pages_WORD word0 1119 struct eq_context context; 1120 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1121 } request; 1122 struct { 1123 uint32_t word0; 1124 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1125 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1126 #define lpfc_mbx_eq_create_q_id_WORD word0 1127 } response; 1128 } u; 1129 }; 1130 1131 struct lpfc_mbx_modify_eq_delay { 1132 struct mbox_header header; 1133 union { 1134 struct { 1135 uint32_t num_eq; 1136 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1137 } request; 1138 struct { 1139 uint32_t word0; 1140 } response; 1141 } u; 1142 }; 1143 1144 struct lpfc_mbx_eq_destroy { 1145 struct mbox_header header; 1146 union { 1147 struct { 1148 uint32_t word0; 1149 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1150 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1151 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1152 } request; 1153 struct { 1154 uint32_t word0; 1155 } response; 1156 } u; 1157 }; 1158 1159 struct lpfc_mbx_nop { 1160 struct mbox_header header; 1161 uint32_t context[2]; 1162 }; 1163 1164 struct cq_context { 1165 uint32_t word0; 1166 #define lpfc_cq_context_event_SHIFT 31 1167 #define lpfc_cq_context_event_MASK 0x00000001 1168 #define lpfc_cq_context_event_WORD word0 1169 #define lpfc_cq_context_valid_SHIFT 29 1170 #define lpfc_cq_context_valid_MASK 0x00000001 1171 #define lpfc_cq_context_valid_WORD word0 1172 #define lpfc_cq_context_count_SHIFT 27 1173 #define lpfc_cq_context_count_MASK 0x00000003 1174 #define lpfc_cq_context_count_WORD word0 1175 #define LPFC_CQ_CNT_256 0x0 1176 #define LPFC_CQ_CNT_512 0x1 1177 #define LPFC_CQ_CNT_1024 0x2 1178 #define LPFC_CQ_CNT_WORD7 0x3 1179 #define lpfc_cq_context_autovalid_SHIFT 15 1180 #define lpfc_cq_context_autovalid_MASK 0x00000001 1181 #define lpfc_cq_context_autovalid_WORD word0 1182 uint32_t word1; 1183 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1184 #define lpfc_cq_eq_id_MASK 0x000000FF 1185 #define lpfc_cq_eq_id_WORD word1 1186 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1187 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1188 #define lpfc_cq_eq_id_2_WORD word1 1189 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1190 uint32_t reserved1; 1191 }; 1192 1193 struct lpfc_mbx_cq_create { 1194 struct mbox_header header; 1195 union { 1196 struct { 1197 uint32_t word0; 1198 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1199 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1200 #define lpfc_mbx_cq_create_page_size_WORD word0 1201 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1202 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1203 #define lpfc_mbx_cq_create_num_pages_WORD word0 1204 struct cq_context context; 1205 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1206 } request; 1207 struct { 1208 uint32_t word0; 1209 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1210 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1211 #define lpfc_mbx_cq_create_q_id_WORD word0 1212 } response; 1213 } u; 1214 }; 1215 1216 struct lpfc_mbx_cq_create_set { 1217 union lpfc_sli4_cfg_shdr cfg_shdr; 1218 union { 1219 struct { 1220 uint32_t word0; 1221 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1222 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1223 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1224 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1225 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1226 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1227 uint32_t word1; 1228 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1229 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1230 #define lpfc_mbx_cq_create_set_evt_WORD word1 1231 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1232 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1233 #define lpfc_mbx_cq_create_set_valid_WORD word1 1234 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1235 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1236 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1237 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1238 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1239 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1240 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1241 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1242 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1243 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1244 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1245 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1246 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1247 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1248 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1249 uint32_t word2; 1250 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1251 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1252 #define lpfc_mbx_cq_create_set_arm_WORD word2 1253 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1254 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1255 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1256 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1257 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1258 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1259 uint32_t word3; 1260 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1261 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1262 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1263 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1264 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1265 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1266 uint32_t word4; 1267 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1268 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1269 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1270 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1271 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1272 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1273 uint32_t word5; 1274 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1275 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1276 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1277 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1278 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1279 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1280 uint32_t word6; 1281 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1282 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1283 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1284 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1285 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1286 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1287 uint32_t word7; 1288 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1289 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1290 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1291 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1292 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1293 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1294 uint32_t word8; 1295 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1296 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1297 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1298 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1299 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1300 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1301 uint32_t word9; 1302 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1303 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1304 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1305 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1306 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1307 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1308 uint32_t word10; 1309 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1310 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1311 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1312 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1313 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1314 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1315 struct dma_address page[1]; 1316 } request; 1317 struct { 1318 uint32_t word0; 1319 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1320 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1321 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1322 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1323 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1324 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1325 } response; 1326 } u; 1327 }; 1328 1329 struct lpfc_mbx_cq_destroy { 1330 struct mbox_header header; 1331 union { 1332 struct { 1333 uint32_t word0; 1334 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1335 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1336 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1337 } request; 1338 struct { 1339 uint32_t word0; 1340 } response; 1341 } u; 1342 }; 1343 1344 struct wq_context { 1345 uint32_t reserved0; 1346 uint32_t reserved1; 1347 uint32_t reserved2; 1348 uint32_t reserved3; 1349 }; 1350 1351 struct lpfc_mbx_wq_create { 1352 struct mbox_header header; 1353 union { 1354 struct { /* Version 0 Request */ 1355 uint32_t word0; 1356 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1357 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1358 #define lpfc_mbx_wq_create_num_pages_WORD word0 1359 #define lpfc_mbx_wq_create_dua_SHIFT 8 1360 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1361 #define lpfc_mbx_wq_create_dua_WORD word0 1362 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1363 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1364 #define lpfc_mbx_wq_create_cq_id_WORD word0 1365 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1366 uint32_t word9; 1367 #define lpfc_mbx_wq_create_bua_SHIFT 0 1368 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1369 #define lpfc_mbx_wq_create_bua_WORD word9 1370 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1371 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1372 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1373 } request; 1374 struct { /* Version 1 Request */ 1375 uint32_t word0; /* Word 0 is the same as in v0 */ 1376 uint32_t word1; 1377 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1378 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1379 #define lpfc_mbx_wq_create_page_size_WORD word1 1380 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1381 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1382 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1383 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1384 #define lpfc_mbx_wq_create_doe_SHIFT 14 1385 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1386 #define lpfc_mbx_wq_create_doe_WORD word1 1387 #define lpfc_mbx_wq_create_toe_SHIFT 13 1388 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1389 #define lpfc_mbx_wq_create_toe_WORD word1 1390 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1391 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1392 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1393 #define LPFC_WQ_WQE_SIZE_64 0x5 1394 #define LPFC_WQ_WQE_SIZE_128 0x6 1395 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1396 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1397 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1398 uint32_t word2; 1399 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1400 } request_1; 1401 struct { 1402 uint32_t word0; 1403 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1404 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1405 #define lpfc_mbx_wq_create_q_id_WORD word0 1406 uint32_t doorbell_offset; 1407 uint32_t word2; 1408 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1409 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1410 #define lpfc_mbx_wq_create_bar_set_WORD word2 1411 #define WQ_PCI_BAR_0_AND_1 0x00 1412 #define WQ_PCI_BAR_2_AND_3 0x01 1413 #define WQ_PCI_BAR_4_AND_5 0x02 1414 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1415 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1416 #define lpfc_mbx_wq_create_db_format_WORD word2 1417 } response; 1418 struct { 1419 uint32_t word0; 1420 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1421 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1422 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1423 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1424 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1425 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1426 uint32_t word1; 1427 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1428 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1429 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1430 uint32_t doorbell_offset; 1431 uint32_t word3; 1432 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1433 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1434 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1435 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1436 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1437 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1438 uint32_t dpp_offset; 1439 } response_1; 1440 } u; 1441 }; 1442 1443 struct lpfc_mbx_wq_destroy { 1444 struct mbox_header header; 1445 union { 1446 struct { 1447 uint32_t word0; 1448 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1449 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1450 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1451 } request; 1452 struct { 1453 uint32_t word0; 1454 } response; 1455 } u; 1456 }; 1457 1458 #define LPFC_HDR_BUF_SIZE 128 1459 #define LPFC_DATA_BUF_SIZE 2048 1460 #define LPFC_NVMET_DATA_BUF_SIZE 128 1461 struct rq_context { 1462 uint32_t word0; 1463 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1464 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1465 #define lpfc_rq_context_rqe_count_WORD word0 1466 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1467 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1468 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1469 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1470 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1471 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1472 #define lpfc_rq_context_rqe_count_1_WORD word0 1473 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1474 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1475 #define lpfc_rq_context_rqe_size_WORD word0 1476 #define LPFC_RQE_SIZE_8 2 1477 #define LPFC_RQE_SIZE_16 3 1478 #define LPFC_RQE_SIZE_32 4 1479 #define LPFC_RQE_SIZE_64 5 1480 #define LPFC_RQE_SIZE_128 6 1481 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1482 #define lpfc_rq_context_page_size_MASK 0x000000FF 1483 #define lpfc_rq_context_page_size_WORD word0 1484 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1485 uint32_t word1; 1486 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1487 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1488 #define lpfc_rq_context_data_size_WORD word1 1489 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1490 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1491 #define lpfc_rq_context_hdr_size_WORD word1 1492 uint32_t word2; 1493 #define lpfc_rq_context_cq_id_SHIFT 16 1494 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1495 #define lpfc_rq_context_cq_id_WORD word2 1496 #define lpfc_rq_context_buf_size_SHIFT 0 1497 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1498 #define lpfc_rq_context_buf_size_WORD word2 1499 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1500 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1501 #define lpfc_rq_context_base_cq_WORD word2 1502 uint32_t buffer_size; /* Version 1 Only */ 1503 }; 1504 1505 struct lpfc_mbx_rq_create { 1506 struct mbox_header header; 1507 union { 1508 struct { 1509 uint32_t word0; 1510 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1511 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1512 #define lpfc_mbx_rq_create_num_pages_WORD word0 1513 #define lpfc_mbx_rq_create_dua_SHIFT 16 1514 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1515 #define lpfc_mbx_rq_create_dua_WORD word0 1516 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1517 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1518 #define lpfc_mbx_rq_create_bqu_WORD word0 1519 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1520 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1521 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1522 struct rq_context context; 1523 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1524 } request; 1525 struct { 1526 uint32_t word0; 1527 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1528 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1529 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1530 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1531 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1532 #define lpfc_mbx_rq_create_q_id_WORD word0 1533 uint32_t doorbell_offset; 1534 uint32_t word2; 1535 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1536 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1537 #define lpfc_mbx_rq_create_bar_set_WORD word2 1538 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1539 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1540 #define lpfc_mbx_rq_create_db_format_WORD word2 1541 } response; 1542 } u; 1543 }; 1544 1545 struct lpfc_mbx_rq_create_v2 { 1546 union lpfc_sli4_cfg_shdr cfg_shdr; 1547 union { 1548 struct { 1549 uint32_t word0; 1550 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1551 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1552 #define lpfc_mbx_rq_create_num_pages_WORD word0 1553 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1554 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1555 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1556 #define lpfc_mbx_rq_create_dua_SHIFT 16 1557 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1558 #define lpfc_mbx_rq_create_dua_WORD word0 1559 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1560 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1561 #define lpfc_mbx_rq_create_bqu_WORD word0 1562 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1563 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1564 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1565 #define lpfc_mbx_rq_create_dim_SHIFT 29 1566 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1567 #define lpfc_mbx_rq_create_dim_WORD word0 1568 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1569 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1570 #define lpfc_mbx_rq_create_dfd_WORD word0 1571 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1572 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1573 #define lpfc_mbx_rq_create_dnb_WORD word0 1574 struct rq_context context; 1575 struct dma_address page[1]; 1576 } request; 1577 struct { 1578 uint32_t word0; 1579 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1580 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1581 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1582 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1583 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1584 #define lpfc_mbx_rq_create_q_id_WORD word0 1585 uint32_t doorbell_offset; 1586 uint32_t word2; 1587 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1588 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1589 #define lpfc_mbx_rq_create_bar_set_WORD word2 1590 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1591 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1592 #define lpfc_mbx_rq_create_db_format_WORD word2 1593 } response; 1594 } u; 1595 }; 1596 1597 struct lpfc_mbx_rq_destroy { 1598 struct mbox_header header; 1599 union { 1600 struct { 1601 uint32_t word0; 1602 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1603 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1604 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1605 } request; 1606 struct { 1607 uint32_t word0; 1608 } response; 1609 } u; 1610 }; 1611 1612 struct mq_context { 1613 uint32_t word0; 1614 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1615 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1616 #define lpfc_mq_context_cq_id_WORD word0 1617 #define lpfc_mq_context_ring_size_SHIFT 16 1618 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1619 #define lpfc_mq_context_ring_size_WORD word0 1620 #define LPFC_MQ_RING_SIZE_16 0x5 1621 #define LPFC_MQ_RING_SIZE_32 0x6 1622 #define LPFC_MQ_RING_SIZE_64 0x7 1623 #define LPFC_MQ_RING_SIZE_128 0x8 1624 uint32_t word1; 1625 #define lpfc_mq_context_valid_SHIFT 31 1626 #define lpfc_mq_context_valid_MASK 0x00000001 1627 #define lpfc_mq_context_valid_WORD word1 1628 uint32_t reserved2; 1629 uint32_t reserved3; 1630 }; 1631 1632 struct lpfc_mbx_mq_create { 1633 struct mbox_header header; 1634 union { 1635 struct { 1636 uint32_t word0; 1637 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1638 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1639 #define lpfc_mbx_mq_create_num_pages_WORD word0 1640 struct mq_context context; 1641 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1642 } request; 1643 struct { 1644 uint32_t word0; 1645 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1646 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1647 #define lpfc_mbx_mq_create_q_id_WORD word0 1648 } response; 1649 } u; 1650 }; 1651 1652 struct lpfc_mbx_mq_create_ext { 1653 struct mbox_header header; 1654 union { 1655 struct { 1656 uint32_t word0; 1657 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1658 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1659 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1660 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1661 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1662 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1663 uint32_t async_evt_bmap; 1664 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1665 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1666 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1667 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1668 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1669 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1670 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1671 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1672 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1673 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1674 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1675 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1676 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1677 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1678 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1679 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1680 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1681 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1682 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1683 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1684 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1685 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1686 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1687 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1688 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1689 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1690 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1691 struct mq_context context; 1692 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1693 } request; 1694 struct { 1695 uint32_t word0; 1696 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1697 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1698 #define lpfc_mbx_mq_create_q_id_WORD word0 1699 } response; 1700 } u; 1701 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1702 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1703 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1704 }; 1705 1706 struct lpfc_mbx_mq_destroy { 1707 struct mbox_header header; 1708 union { 1709 struct { 1710 uint32_t word0; 1711 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1712 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1713 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1714 } request; 1715 struct { 1716 uint32_t word0; 1717 } response; 1718 } u; 1719 }; 1720 1721 /* Start Gen 2 SLI4 Mailbox definitions: */ 1722 1723 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1724 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1725 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1726 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1727 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1728 1729 struct lpfc_mbx_get_rsrc_extent_info { 1730 struct mbox_header header; 1731 union { 1732 struct { 1733 uint32_t word4; 1734 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1735 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1736 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1737 } req; 1738 struct { 1739 uint32_t word4; 1740 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1741 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1742 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1743 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1744 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1745 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1746 } rsp; 1747 } u; 1748 }; 1749 1750 struct lpfc_mbx_query_fw_config { 1751 struct mbox_header header; 1752 struct { 1753 uint32_t config_number; 1754 #define LPFC_FC_FCOE 0x00000007 1755 uint32_t asic_revision; 1756 uint32_t physical_port; 1757 uint32_t function_mode; 1758 #define LPFC_FCOE_INI_MODE 0x00000040 1759 #define LPFC_FCOE_TGT_MODE 0x00000080 1760 #define LPFC_DUA_MODE 0x00000800 1761 uint32_t ulp0_mode; 1762 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1763 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1764 uint32_t ulp0_nap_words[12]; 1765 uint32_t ulp1_mode; 1766 uint32_t ulp1_nap_words[12]; 1767 uint32_t function_capabilities; 1768 uint32_t cqid_base; 1769 uint32_t cqid_tot; 1770 uint32_t eqid_base; 1771 uint32_t eqid_tot; 1772 uint32_t ulp0_nap2_words[2]; 1773 uint32_t ulp1_nap2_words[2]; 1774 } rsp; 1775 }; 1776 1777 struct lpfc_mbx_set_beacon_config { 1778 struct mbox_header header; 1779 uint32_t word4; 1780 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1781 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1782 #define lpfc_mbx_set_beacon_port_num_WORD word4 1783 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1784 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1785 #define lpfc_mbx_set_beacon_port_type_WORD word4 1786 #define lpfc_mbx_set_beacon_state_SHIFT 8 1787 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1788 #define lpfc_mbx_set_beacon_state_WORD word4 1789 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1790 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1791 #define lpfc_mbx_set_beacon_duration_WORD word4 1792 #define lpfc_mbx_set_beacon_status_duration_SHIFT 24 1793 #define lpfc_mbx_set_beacon_status_duration_MASK 0x000000FF 1794 #define lpfc_mbx_set_beacon_status_duration_WORD word4 1795 }; 1796 1797 struct lpfc_id_range { 1798 uint32_t word5; 1799 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1800 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1801 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1802 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1803 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1804 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1805 }; 1806 1807 struct lpfc_mbx_set_link_diag_state { 1808 struct mbox_header header; 1809 union { 1810 struct { 1811 uint32_t word0; 1812 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1813 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1814 #define lpfc_mbx_set_diag_state_diag_WORD word0 1815 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1816 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1817 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1818 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1819 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1820 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1821 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1822 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1823 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1824 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1825 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1826 } req; 1827 struct { 1828 uint32_t word0; 1829 } rsp; 1830 } u; 1831 }; 1832 1833 struct lpfc_mbx_set_link_diag_loopback { 1834 struct mbox_header header; 1835 union { 1836 struct { 1837 uint32_t word0; 1838 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1839 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1840 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1841 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1842 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1843 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1844 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1845 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1846 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1847 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1848 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1849 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1850 } req; 1851 struct { 1852 uint32_t word0; 1853 } rsp; 1854 } u; 1855 }; 1856 1857 struct lpfc_mbx_run_link_diag_test { 1858 struct mbox_header header; 1859 union { 1860 struct { 1861 uint32_t word0; 1862 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1863 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1864 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1865 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1866 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1867 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1868 uint32_t word1; 1869 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1870 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1871 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1872 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1873 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1874 #define lpfc_mbx_run_diag_test_loops_WORD word1 1875 uint32_t word2; 1876 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1877 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1878 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1879 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1880 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1881 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1882 } req; 1883 struct { 1884 uint32_t word0; 1885 } rsp; 1886 } u; 1887 }; 1888 1889 /* 1890 * struct lpfc_mbx_alloc_rsrc_extents: 1891 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1892 * 6 words of header + 4 words of shared subcommand header + 1893 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1894 * 1895 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1896 * for extents payload. 1897 * 1898 * 212/2 (bytes per extent) = 106 extents. 1899 * 106/2 (extents per word) = 53 words. 1900 * lpfc_id_range id is statically size to 53. 1901 * 1902 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1903 * extent ranges. For ALLOC, the type and cnt are required. 1904 * For GET_ALLOCATED, only the type is required. 1905 */ 1906 struct lpfc_mbx_alloc_rsrc_extents { 1907 struct mbox_header header; 1908 union { 1909 struct { 1910 uint32_t word4; 1911 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1912 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1913 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1914 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1915 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1916 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1917 } req; 1918 struct { 1919 uint32_t word4; 1920 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1921 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1922 #define lpfc_mbx_rsrc_cnt_WORD word4 1923 struct lpfc_id_range id[53]; 1924 } rsp; 1925 } u; 1926 }; 1927 1928 /* 1929 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1930 * structure shares the same SHIFT/MASK/WORD defines provided in the 1931 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1932 * the structures defined above. This non-embedded structure provides for the 1933 * maximum number of extents supported by the port. 1934 */ 1935 struct lpfc_mbx_nembed_rsrc_extent { 1936 union lpfc_sli4_cfg_shdr cfg_shdr; 1937 uint32_t word4; 1938 struct lpfc_id_range id; 1939 }; 1940 1941 struct lpfc_mbx_dealloc_rsrc_extents { 1942 struct mbox_header header; 1943 struct { 1944 uint32_t word4; 1945 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1946 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1947 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1948 } req; 1949 1950 }; 1951 1952 /* Start SLI4 FCoE specific mbox structures. */ 1953 1954 struct lpfc_mbx_post_hdr_tmpl { 1955 struct mbox_header header; 1956 uint32_t word10; 1957 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1958 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1959 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1960 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1961 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1962 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1963 uint32_t rpi_paddr_lo; 1964 uint32_t rpi_paddr_hi; 1965 }; 1966 1967 struct sli4_sge { /* SLI-4 */ 1968 uint32_t addr_hi; 1969 uint32_t addr_lo; 1970 1971 uint32_t word2; 1972 #define lpfc_sli4_sge_offset_SHIFT 0 1973 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1974 #define lpfc_sli4_sge_offset_WORD word2 1975 #define lpfc_sli4_sge_type_SHIFT 27 1976 #define lpfc_sli4_sge_type_MASK 0x0000000F 1977 #define lpfc_sli4_sge_type_WORD word2 1978 #define LPFC_SGE_TYPE_DATA 0x0 1979 #define LPFC_SGE_TYPE_DIF 0x4 1980 #define LPFC_SGE_TYPE_LSP 0x5 1981 #define LPFC_SGE_TYPE_PEDIF 0x6 1982 #define LPFC_SGE_TYPE_PESEED 0x7 1983 #define LPFC_SGE_TYPE_DISEED 0x8 1984 #define LPFC_SGE_TYPE_ENC 0x9 1985 #define LPFC_SGE_TYPE_ATM 0xA 1986 #define LPFC_SGE_TYPE_SKIP 0xC 1987 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1988 #define lpfc_sli4_sge_last_MASK 0x00000001 1989 #define lpfc_sli4_sge_last_WORD word2 1990 uint32_t sge_len; 1991 }; 1992 1993 struct sli4_sge_diseed { /* SLI-4 */ 1994 uint32_t ref_tag; 1995 uint32_t ref_tag_tran; 1996 1997 uint32_t word2; 1998 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1999 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2000 #define lpfc_sli4_sge_dif_apptran_WORD word2 2001 #define lpfc_sli4_sge_dif_af_SHIFT 24 2002 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2003 #define lpfc_sli4_sge_dif_af_WORD word2 2004 #define lpfc_sli4_sge_dif_na_SHIFT 25 2005 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2006 #define lpfc_sli4_sge_dif_na_WORD word2 2007 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2008 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2009 #define lpfc_sli4_sge_dif_hi_WORD word2 2010 #define lpfc_sli4_sge_dif_type_SHIFT 27 2011 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2012 #define lpfc_sli4_sge_dif_type_WORD word2 2013 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2014 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2015 #define lpfc_sli4_sge_dif_last_WORD word2 2016 uint32_t word3; 2017 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2018 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2019 #define lpfc_sli4_sge_dif_apptag_WORD word3 2020 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2021 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2022 #define lpfc_sli4_sge_dif_bs_WORD word3 2023 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2024 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2025 #define lpfc_sli4_sge_dif_ai_WORD word3 2026 #define lpfc_sli4_sge_dif_me_SHIFT 20 2027 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2028 #define lpfc_sli4_sge_dif_me_WORD word3 2029 #define lpfc_sli4_sge_dif_re_SHIFT 21 2030 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2031 #define lpfc_sli4_sge_dif_re_WORD word3 2032 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2033 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2034 #define lpfc_sli4_sge_dif_ce_WORD word3 2035 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2036 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2037 #define lpfc_sli4_sge_dif_nr_WORD word3 2038 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2039 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2040 #define lpfc_sli4_sge_dif_oprx_WORD word3 2041 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2042 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2043 #define lpfc_sli4_sge_dif_optx_WORD word3 2044 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2045 }; 2046 2047 struct fcf_record { 2048 uint32_t max_rcv_size; 2049 uint32_t fka_adv_period; 2050 uint32_t fip_priority; 2051 uint32_t word3; 2052 #define lpfc_fcf_record_mac_0_SHIFT 0 2053 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2054 #define lpfc_fcf_record_mac_0_WORD word3 2055 #define lpfc_fcf_record_mac_1_SHIFT 8 2056 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2057 #define lpfc_fcf_record_mac_1_WORD word3 2058 #define lpfc_fcf_record_mac_2_SHIFT 16 2059 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2060 #define lpfc_fcf_record_mac_2_WORD word3 2061 #define lpfc_fcf_record_mac_3_SHIFT 24 2062 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2063 #define lpfc_fcf_record_mac_3_WORD word3 2064 uint32_t word4; 2065 #define lpfc_fcf_record_mac_4_SHIFT 0 2066 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2067 #define lpfc_fcf_record_mac_4_WORD word4 2068 #define lpfc_fcf_record_mac_5_SHIFT 8 2069 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2070 #define lpfc_fcf_record_mac_5_WORD word4 2071 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2072 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2073 #define lpfc_fcf_record_fcf_avail_WORD word4 2074 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2075 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2076 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2077 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2078 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2079 uint32_t word5; 2080 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2081 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2082 #define lpfc_fcf_record_fab_name_0_WORD word5 2083 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2084 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2085 #define lpfc_fcf_record_fab_name_1_WORD word5 2086 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2087 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2088 #define lpfc_fcf_record_fab_name_2_WORD word5 2089 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2090 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2091 #define lpfc_fcf_record_fab_name_3_WORD word5 2092 uint32_t word6; 2093 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2094 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2095 #define lpfc_fcf_record_fab_name_4_WORD word6 2096 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2097 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2098 #define lpfc_fcf_record_fab_name_5_WORD word6 2099 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2100 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2101 #define lpfc_fcf_record_fab_name_6_WORD word6 2102 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2103 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2104 #define lpfc_fcf_record_fab_name_7_WORD word6 2105 uint32_t word7; 2106 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2107 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2108 #define lpfc_fcf_record_fc_map_0_WORD word7 2109 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2110 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2111 #define lpfc_fcf_record_fc_map_1_WORD word7 2112 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2113 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2114 #define lpfc_fcf_record_fc_map_2_WORD word7 2115 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2116 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2117 #define lpfc_fcf_record_fcf_valid_WORD word7 2118 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2119 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2120 #define lpfc_fcf_record_fcf_fc_WORD word7 2121 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2122 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2123 #define lpfc_fcf_record_fcf_sol_WORD word7 2124 uint32_t word8; 2125 #define lpfc_fcf_record_fcf_index_SHIFT 0 2126 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2127 #define lpfc_fcf_record_fcf_index_WORD word8 2128 #define lpfc_fcf_record_fcf_state_SHIFT 16 2129 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2130 #define lpfc_fcf_record_fcf_state_WORD word8 2131 uint8_t vlan_bitmap[512]; 2132 uint32_t word137; 2133 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2134 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2135 #define lpfc_fcf_record_switch_name_0_WORD word137 2136 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2137 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2138 #define lpfc_fcf_record_switch_name_1_WORD word137 2139 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2140 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2141 #define lpfc_fcf_record_switch_name_2_WORD word137 2142 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2143 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2144 #define lpfc_fcf_record_switch_name_3_WORD word137 2145 uint32_t word138; 2146 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2147 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2148 #define lpfc_fcf_record_switch_name_4_WORD word138 2149 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2150 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2151 #define lpfc_fcf_record_switch_name_5_WORD word138 2152 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2153 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2154 #define lpfc_fcf_record_switch_name_6_WORD word138 2155 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2156 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2157 #define lpfc_fcf_record_switch_name_7_WORD word138 2158 }; 2159 2160 struct lpfc_mbx_read_fcf_tbl { 2161 union lpfc_sli4_cfg_shdr cfg_shdr; 2162 union { 2163 struct { 2164 uint32_t word10; 2165 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2166 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2167 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2168 } request; 2169 struct { 2170 uint32_t eventag; 2171 } response; 2172 } u; 2173 uint32_t word11; 2174 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2175 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2176 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2177 }; 2178 2179 struct lpfc_mbx_add_fcf_tbl_entry { 2180 union lpfc_sli4_cfg_shdr cfg_shdr; 2181 uint32_t word10; 2182 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2183 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2184 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2185 struct lpfc_mbx_sge fcf_sge; 2186 }; 2187 2188 struct lpfc_mbx_del_fcf_tbl_entry { 2189 struct mbox_header header; 2190 uint32_t word10; 2191 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2192 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2193 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2194 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2195 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2196 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2197 }; 2198 2199 struct lpfc_mbx_redisc_fcf_tbl { 2200 struct mbox_header header; 2201 uint32_t word10; 2202 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2203 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2204 #define lpfc_mbx_redisc_fcf_count_WORD word10 2205 uint32_t resvd; 2206 uint32_t word12; 2207 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2208 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2209 #define lpfc_mbx_redisc_fcf_index_WORD word12 2210 }; 2211 2212 /* Status field for embedded SLI_CONFIG mailbox command */ 2213 #define STATUS_SUCCESS 0x0 2214 #define STATUS_FAILED 0x1 2215 #define STATUS_ILLEGAL_REQUEST 0x2 2216 #define STATUS_ILLEGAL_FIELD 0x3 2217 #define STATUS_INSUFFICIENT_BUFFER 0x4 2218 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2219 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2220 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2221 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2222 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2223 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2224 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2225 #define STATUS_ASSERT_FAILED 0x1e 2226 #define STATUS_INVALID_SESSION 0x1f 2227 #define STATUS_INVALID_CONNECTION 0x20 2228 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2229 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2230 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2231 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2232 #define STATUS_FLASHROM_READ_FAILED 0x27 2233 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2234 #define STATUS_ERROR_ACITMAIN 0x2a 2235 #define STATUS_REBOOT_REQUIRED 0x2c 2236 #define STATUS_FCF_IN_USE 0x3a 2237 #define STATUS_FCF_TABLE_EMPTY 0x43 2238 2239 /* 2240 * Additional status field for embedded SLI_CONFIG mailbox 2241 * command. 2242 */ 2243 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2244 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2245 2246 struct lpfc_mbx_sli4_config { 2247 struct mbox_header header; 2248 }; 2249 2250 struct lpfc_mbx_init_vfi { 2251 uint32_t word1; 2252 #define lpfc_init_vfi_vr_SHIFT 31 2253 #define lpfc_init_vfi_vr_MASK 0x00000001 2254 #define lpfc_init_vfi_vr_WORD word1 2255 #define lpfc_init_vfi_vt_SHIFT 30 2256 #define lpfc_init_vfi_vt_MASK 0x00000001 2257 #define lpfc_init_vfi_vt_WORD word1 2258 #define lpfc_init_vfi_vf_SHIFT 29 2259 #define lpfc_init_vfi_vf_MASK 0x00000001 2260 #define lpfc_init_vfi_vf_WORD word1 2261 #define lpfc_init_vfi_vp_SHIFT 28 2262 #define lpfc_init_vfi_vp_MASK 0x00000001 2263 #define lpfc_init_vfi_vp_WORD word1 2264 #define lpfc_init_vfi_vfi_SHIFT 0 2265 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2266 #define lpfc_init_vfi_vfi_WORD word1 2267 uint32_t word2; 2268 #define lpfc_init_vfi_vpi_SHIFT 16 2269 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2270 #define lpfc_init_vfi_vpi_WORD word2 2271 #define lpfc_init_vfi_fcfi_SHIFT 0 2272 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2273 #define lpfc_init_vfi_fcfi_WORD word2 2274 uint32_t word3; 2275 #define lpfc_init_vfi_pri_SHIFT 13 2276 #define lpfc_init_vfi_pri_MASK 0x00000007 2277 #define lpfc_init_vfi_pri_WORD word3 2278 #define lpfc_init_vfi_vf_id_SHIFT 1 2279 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2280 #define lpfc_init_vfi_vf_id_WORD word3 2281 uint32_t word4; 2282 #define lpfc_init_vfi_hop_count_SHIFT 24 2283 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2284 #define lpfc_init_vfi_hop_count_WORD word4 2285 }; 2286 #define MBX_VFI_IN_USE 0x9F02 2287 2288 2289 struct lpfc_mbx_reg_vfi { 2290 uint32_t word1; 2291 #define lpfc_reg_vfi_upd_SHIFT 29 2292 #define lpfc_reg_vfi_upd_MASK 0x00000001 2293 #define lpfc_reg_vfi_upd_WORD word1 2294 #define lpfc_reg_vfi_vp_SHIFT 28 2295 #define lpfc_reg_vfi_vp_MASK 0x00000001 2296 #define lpfc_reg_vfi_vp_WORD word1 2297 #define lpfc_reg_vfi_vfi_SHIFT 0 2298 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2299 #define lpfc_reg_vfi_vfi_WORD word1 2300 uint32_t word2; 2301 #define lpfc_reg_vfi_vpi_SHIFT 16 2302 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2303 #define lpfc_reg_vfi_vpi_WORD word2 2304 #define lpfc_reg_vfi_fcfi_SHIFT 0 2305 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2306 #define lpfc_reg_vfi_fcfi_WORD word2 2307 uint32_t wwn[2]; 2308 struct ulp_bde64 bde; 2309 uint32_t e_d_tov; 2310 uint32_t r_a_tov; 2311 uint32_t word10; 2312 #define lpfc_reg_vfi_nport_id_SHIFT 0 2313 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2314 #define lpfc_reg_vfi_nport_id_WORD word10 2315 #define lpfc_reg_vfi_bbcr_SHIFT 27 2316 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2317 #define lpfc_reg_vfi_bbcr_WORD word10 2318 #define lpfc_reg_vfi_bbscn_SHIFT 28 2319 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2320 #define lpfc_reg_vfi_bbscn_WORD word10 2321 }; 2322 2323 struct lpfc_mbx_init_vpi { 2324 uint32_t word1; 2325 #define lpfc_init_vpi_vfi_SHIFT 16 2326 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2327 #define lpfc_init_vpi_vfi_WORD word1 2328 #define lpfc_init_vpi_vpi_SHIFT 0 2329 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2330 #define lpfc_init_vpi_vpi_WORD word1 2331 }; 2332 2333 struct lpfc_mbx_read_vpi { 2334 uint32_t word1_rsvd; 2335 uint32_t word2; 2336 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2337 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2338 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2339 uint32_t word3_rsvd; 2340 uint32_t word4; 2341 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2342 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2343 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2344 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2345 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2346 #define lpfc_mbx_read_vpi_pb_WORD word4 2347 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2348 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2349 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2350 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2351 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2352 #define lpfc_mbx_read_vpi_ns_WORD word4 2353 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2354 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2355 #define lpfc_mbx_read_vpi_hl_WORD word4 2356 uint32_t word5_rsvd; 2357 uint32_t word6; 2358 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2359 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2360 #define lpfc_mbx_read_vpi_vpi_WORD word6 2361 uint32_t word7; 2362 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2363 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2364 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2365 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2366 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2367 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2368 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2369 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2370 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2371 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2372 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2373 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2374 uint32_t word8; 2375 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2376 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2377 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2378 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2379 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2380 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2381 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2382 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2383 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2384 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2385 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2386 #define lpfc_mbx_read_vpi_vv_WORD word8 2387 }; 2388 2389 struct lpfc_mbx_unreg_vfi { 2390 uint32_t word1_rsvd; 2391 uint32_t word2; 2392 #define lpfc_unreg_vfi_vfi_SHIFT 0 2393 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2394 #define lpfc_unreg_vfi_vfi_WORD word2 2395 }; 2396 2397 struct lpfc_mbx_resume_rpi { 2398 uint32_t word1; 2399 #define lpfc_resume_rpi_index_SHIFT 0 2400 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2401 #define lpfc_resume_rpi_index_WORD word1 2402 #define lpfc_resume_rpi_ii_SHIFT 30 2403 #define lpfc_resume_rpi_ii_MASK 0x00000003 2404 #define lpfc_resume_rpi_ii_WORD word1 2405 #define RESUME_INDEX_RPI 0 2406 #define RESUME_INDEX_VPI 1 2407 #define RESUME_INDEX_VFI 2 2408 #define RESUME_INDEX_FCFI 3 2409 uint32_t event_tag; 2410 }; 2411 2412 #define REG_FCF_INVALID_QID 0xFFFF 2413 struct lpfc_mbx_reg_fcfi { 2414 uint32_t word1; 2415 #define lpfc_reg_fcfi_info_index_SHIFT 0 2416 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2417 #define lpfc_reg_fcfi_info_index_WORD word1 2418 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2419 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2420 #define lpfc_reg_fcfi_fcfi_WORD word1 2421 uint32_t word2; 2422 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2423 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2424 #define lpfc_reg_fcfi_rq_id1_WORD word2 2425 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2426 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2427 #define lpfc_reg_fcfi_rq_id0_WORD word2 2428 uint32_t word3; 2429 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2430 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2431 #define lpfc_reg_fcfi_rq_id3_WORD word3 2432 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2433 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2434 #define lpfc_reg_fcfi_rq_id2_WORD word3 2435 uint32_t word4; 2436 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2437 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2438 #define lpfc_reg_fcfi_type_match0_WORD word4 2439 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2440 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2441 #define lpfc_reg_fcfi_type_mask0_WORD word4 2442 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2443 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2444 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2445 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2446 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2447 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2448 uint32_t word5; 2449 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2450 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2451 #define lpfc_reg_fcfi_type_match1_WORD word5 2452 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2453 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2454 #define lpfc_reg_fcfi_type_mask1_WORD word5 2455 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2456 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2457 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2458 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2459 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2460 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2461 uint32_t word6; 2462 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2463 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2464 #define lpfc_reg_fcfi_type_match2_WORD word6 2465 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2466 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2467 #define lpfc_reg_fcfi_type_mask2_WORD word6 2468 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2469 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2470 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2471 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2472 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2473 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2474 uint32_t word7; 2475 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2476 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2477 #define lpfc_reg_fcfi_type_match3_WORD word7 2478 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2479 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2480 #define lpfc_reg_fcfi_type_mask3_WORD word7 2481 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2482 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2483 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2484 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2485 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2486 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2487 uint32_t word8; 2488 #define lpfc_reg_fcfi_mam_SHIFT 13 2489 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2490 #define lpfc_reg_fcfi_mam_WORD word8 2491 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2492 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2493 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2494 #define lpfc_reg_fcfi_vv_SHIFT 12 2495 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2496 #define lpfc_reg_fcfi_vv_WORD word8 2497 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2498 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2499 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2500 }; 2501 2502 struct lpfc_mbx_reg_fcfi_mrq { 2503 uint32_t word1; 2504 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2505 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2506 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2507 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2508 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2509 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2510 uint32_t word2; 2511 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2512 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2513 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2514 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2515 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2516 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2517 uint32_t word3; 2518 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2519 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2520 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2521 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2522 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2523 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2524 uint32_t word4; 2525 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2526 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2527 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2528 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2529 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2530 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2531 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2532 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2533 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2534 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2535 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2536 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2537 uint32_t word5; 2538 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2539 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2540 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2541 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2542 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2543 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2544 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2545 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2546 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2547 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2548 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2549 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2550 uint32_t word6; 2551 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2552 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2553 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2554 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2555 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2556 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2557 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2558 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2559 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2560 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2561 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2562 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2563 uint32_t word7; 2564 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2565 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2566 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2567 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2568 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2569 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2570 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2571 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2572 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2573 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2574 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2575 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2576 uint32_t word8; 2577 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2578 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2579 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2580 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2581 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2582 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2583 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2584 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2585 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2586 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2587 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2588 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2589 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2590 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2591 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2592 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2593 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2594 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2595 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2596 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2597 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2598 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2599 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2600 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2601 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2602 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2603 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2604 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2605 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2606 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2607 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2608 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2609 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2610 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2611 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2612 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2613 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2614 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2615 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2616 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2617 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2618 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2619 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2620 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2621 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2622 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2623 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2624 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2625 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2626 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2627 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2628 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2629 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2630 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2631 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2632 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2633 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2634 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2635 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2636 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2637 uint32_t word9; 2638 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2639 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2640 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2641 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2642 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2643 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2644 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2645 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2646 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2647 uint32_t word10; 2648 uint32_t word11; 2649 uint32_t word12; 2650 uint32_t word13; 2651 uint32_t word14; 2652 uint32_t word15; 2653 uint32_t word16; 2654 }; 2655 2656 struct lpfc_mbx_unreg_fcfi { 2657 uint32_t word1_rsv; 2658 uint32_t word2; 2659 #define lpfc_unreg_fcfi_SHIFT 0 2660 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2661 #define lpfc_unreg_fcfi_WORD word2 2662 }; 2663 2664 struct lpfc_mbx_read_rev { 2665 uint32_t word1; 2666 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2667 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2668 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2669 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2670 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2671 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2672 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2673 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2674 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2675 #define LPFC_PREDCBX_CEE_MODE 0 2676 #define LPFC_DCBX_CEE_MODE 1 2677 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2678 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2679 #define lpfc_mbx_rd_rev_vpd_WORD word1 2680 uint32_t first_hw_rev; 2681 #define LPFC_G7_ASIC_1 0xd 2682 uint32_t second_hw_rev; 2683 uint32_t word4_rsvd; 2684 uint32_t third_hw_rev; 2685 uint32_t word6; 2686 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2687 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2688 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2689 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2690 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2691 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2692 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2693 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2694 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2695 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2696 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2697 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2698 uint32_t word7_rsvd; 2699 uint32_t fw_id_rev; 2700 uint8_t fw_name[16]; 2701 uint32_t ulp_fw_id_rev; 2702 uint8_t ulp_fw_name[16]; 2703 uint32_t word18_47_rsvd[30]; 2704 uint32_t word48; 2705 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2706 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2707 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2708 uint32_t vpd_paddr_low; 2709 uint32_t vpd_paddr_high; 2710 uint32_t avail_vpd_len; 2711 uint32_t rsvd_52_63[12]; 2712 }; 2713 2714 struct lpfc_mbx_read_config { 2715 uint32_t word1; 2716 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2717 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2718 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2719 uint32_t word2; 2720 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2721 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2722 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2723 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2724 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2725 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2726 #define LPFC_LNK_TYPE_GE 0 2727 #define LPFC_LNK_TYPE_FC 1 2728 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2729 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2730 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2731 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2732 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2733 #define lpfc_mbx_rd_conf_topology_WORD word2 2734 uint32_t rsvd_3; 2735 uint32_t word4; 2736 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2737 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2738 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2739 uint32_t rsvd_5; 2740 uint32_t word6; 2741 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2742 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2743 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2744 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2745 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2746 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2747 uint32_t rsvd_7; 2748 uint32_t word8; 2749 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2750 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2751 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2752 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2753 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2754 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2755 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2756 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2757 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2758 uint32_t word9; 2759 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2760 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2761 #define lpfc_mbx_rd_conf_lmt_WORD word9 2762 uint32_t rsvd_10; 2763 uint32_t rsvd_11; 2764 uint32_t word12; 2765 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2766 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2767 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2768 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2769 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2770 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2771 uint32_t word13; 2772 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2773 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2774 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2775 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2776 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2777 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2778 uint32_t word14; 2779 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2780 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2781 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2782 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2783 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2784 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2785 uint32_t word15; 2786 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2787 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2788 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2789 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2790 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2791 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2792 uint32_t word16; 2793 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2794 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2795 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2796 uint32_t word17; 2797 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2798 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2799 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2800 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2801 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2802 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2803 uint32_t word18; 2804 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2805 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2806 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2807 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2808 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2809 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2810 }; 2811 2812 struct lpfc_mbx_request_features { 2813 uint32_t word1; 2814 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2815 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2816 #define lpfc_mbx_rq_ftr_qry_WORD word1 2817 uint32_t word2; 2818 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2819 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2820 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2821 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2822 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2823 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2824 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2825 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2826 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2827 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2828 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2829 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2830 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2831 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2832 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2833 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2834 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2835 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2836 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2837 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2838 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2839 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2840 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2841 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2842 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2843 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2844 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2845 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2846 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2847 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2848 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2849 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2850 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2851 uint32_t word3; 2852 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2853 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2854 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2855 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2856 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2857 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2858 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2859 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2860 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2861 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2862 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2863 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2864 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2865 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2866 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2867 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2868 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2869 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2870 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2871 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2872 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2873 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2874 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2875 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2876 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2877 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2878 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2879 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2880 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2881 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2882 }; 2883 2884 struct lpfc_mbx_supp_pages { 2885 uint32_t word1; 2886 #define qs_SHIFT 0 2887 #define qs_MASK 0x00000001 2888 #define qs_WORD word1 2889 #define wr_SHIFT 1 2890 #define wr_MASK 0x00000001 2891 #define wr_WORD word1 2892 #define pf_SHIFT 8 2893 #define pf_MASK 0x000000ff 2894 #define pf_WORD word1 2895 #define cpn_SHIFT 16 2896 #define cpn_MASK 0x000000ff 2897 #define cpn_WORD word1 2898 uint32_t word2; 2899 #define list_offset_SHIFT 0 2900 #define list_offset_MASK 0x000000ff 2901 #define list_offset_WORD word2 2902 #define next_offset_SHIFT 8 2903 #define next_offset_MASK 0x000000ff 2904 #define next_offset_WORD word2 2905 #define elem_cnt_SHIFT 16 2906 #define elem_cnt_MASK 0x000000ff 2907 #define elem_cnt_WORD word2 2908 uint32_t word3; 2909 #define pn_0_SHIFT 24 2910 #define pn_0_MASK 0x000000ff 2911 #define pn_0_WORD word3 2912 #define pn_1_SHIFT 16 2913 #define pn_1_MASK 0x000000ff 2914 #define pn_1_WORD word3 2915 #define pn_2_SHIFT 8 2916 #define pn_2_MASK 0x000000ff 2917 #define pn_2_WORD word3 2918 #define pn_3_SHIFT 0 2919 #define pn_3_MASK 0x000000ff 2920 #define pn_3_WORD word3 2921 uint32_t word4; 2922 #define pn_4_SHIFT 24 2923 #define pn_4_MASK 0x000000ff 2924 #define pn_4_WORD word4 2925 #define pn_5_SHIFT 16 2926 #define pn_5_MASK 0x000000ff 2927 #define pn_5_WORD word4 2928 #define pn_6_SHIFT 8 2929 #define pn_6_MASK 0x000000ff 2930 #define pn_6_WORD word4 2931 #define pn_7_SHIFT 0 2932 #define pn_7_MASK 0x000000ff 2933 #define pn_7_WORD word4 2934 uint32_t rsvd[27]; 2935 #define LPFC_SUPP_PAGES 0 2936 #define LPFC_BLOCK_GUARD_PROFILES 1 2937 #define LPFC_SLI4_PARAMETERS 2 2938 }; 2939 2940 struct lpfc_mbx_memory_dump_type3 { 2941 uint32_t word1; 2942 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2943 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2944 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2945 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2946 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2947 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2948 uint32_t word2; 2949 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2950 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 2951 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 2952 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 2953 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 2954 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 2955 uint32_t word3; 2956 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 2957 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 2958 #define lpfc_mbx_memory_dump_type3_length_WORD word3 2959 uint32_t addr_lo; 2960 uint32_t addr_hi; 2961 uint32_t return_len; 2962 }; 2963 2964 #define DMP_PAGE_A0 0xa0 2965 #define DMP_PAGE_A2 0xa2 2966 #define DMP_SFF_PAGE_A0_SIZE 256 2967 #define DMP_SFF_PAGE_A2_SIZE 256 2968 2969 #define SFP_WAVELENGTH_LC1310 1310 2970 #define SFP_WAVELENGTH_LL1550 1550 2971 2972 2973 /* 2974 * * SFF-8472 TABLE 3.4 2975 * */ 2976 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 2977 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 2978 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 2979 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 2980 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 2981 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 2982 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 2983 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 2984 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 2985 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 2986 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 2987 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 2988 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 2989 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 2990 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 2991 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 2992 2993 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 2994 2995 #define SSF_IDENTIFIER 0 2996 #define SSF_EXT_IDENTIFIER 1 2997 #define SSF_CONNECTOR 2 2998 #define SSF_TRANSCEIVER_CODE_B0 3 2999 #define SSF_TRANSCEIVER_CODE_B1 4 3000 #define SSF_TRANSCEIVER_CODE_B2 5 3001 #define SSF_TRANSCEIVER_CODE_B3 6 3002 #define SSF_TRANSCEIVER_CODE_B4 7 3003 #define SSF_TRANSCEIVER_CODE_B5 8 3004 #define SSF_TRANSCEIVER_CODE_B6 9 3005 #define SSF_TRANSCEIVER_CODE_B7 10 3006 #define SSF_ENCODING 11 3007 #define SSF_BR_NOMINAL 12 3008 #define SSF_RATE_IDENTIFIER 13 3009 #define SSF_LENGTH_9UM_KM 14 3010 #define SSF_LENGTH_9UM 15 3011 #define SSF_LENGTH_50UM_OM2 16 3012 #define SSF_LENGTH_62UM_OM1 17 3013 #define SFF_LENGTH_COPPER 18 3014 #define SSF_LENGTH_50UM_OM3 19 3015 #define SSF_VENDOR_NAME 20 3016 #define SSF_VENDOR_OUI 36 3017 #define SSF_VENDOR_PN 40 3018 #define SSF_VENDOR_REV 56 3019 #define SSF_WAVELENGTH_B1 60 3020 #define SSF_WAVELENGTH_B0 61 3021 #define SSF_CC_BASE 63 3022 #define SSF_OPTIONS_B1 64 3023 #define SSF_OPTIONS_B0 65 3024 #define SSF_BR_MAX 66 3025 #define SSF_BR_MIN 67 3026 #define SSF_VENDOR_SN 68 3027 #define SSF_DATE_CODE 84 3028 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3029 #define SSF_ENHANCED_OPTIONS 93 3030 #define SFF_8472_COMPLIANCE 94 3031 #define SSF_CC_EXT 95 3032 #define SSF_A0_VENDOR_SPECIFIC 96 3033 3034 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3035 3036 #define SSF_TEMP_HIGH_ALARM 0 3037 #define SSF_TEMP_LOW_ALARM 2 3038 #define SSF_TEMP_HIGH_WARNING 4 3039 #define SSF_TEMP_LOW_WARNING 6 3040 #define SSF_VOLTAGE_HIGH_ALARM 8 3041 #define SSF_VOLTAGE_LOW_ALARM 10 3042 #define SSF_VOLTAGE_HIGH_WARNING 12 3043 #define SSF_VOLTAGE_LOW_WARNING 14 3044 #define SSF_BIAS_HIGH_ALARM 16 3045 #define SSF_BIAS_LOW_ALARM 18 3046 #define SSF_BIAS_HIGH_WARNING 20 3047 #define SSF_BIAS_LOW_WARNING 22 3048 #define SSF_TXPOWER_HIGH_ALARM 24 3049 #define SSF_TXPOWER_LOW_ALARM 26 3050 #define SSF_TXPOWER_HIGH_WARNING 28 3051 #define SSF_TXPOWER_LOW_WARNING 30 3052 #define SSF_RXPOWER_HIGH_ALARM 32 3053 #define SSF_RXPOWER_LOW_ALARM 34 3054 #define SSF_RXPOWER_HIGH_WARNING 36 3055 #define SSF_RXPOWER_LOW_WARNING 38 3056 #define SSF_EXT_CAL_CONSTANTS 56 3057 #define SSF_CC_DMI 95 3058 #define SFF_TEMPERATURE_B1 96 3059 #define SFF_TEMPERATURE_B0 97 3060 #define SFF_VCC_B1 98 3061 #define SFF_VCC_B0 99 3062 #define SFF_TX_BIAS_CURRENT_B1 100 3063 #define SFF_TX_BIAS_CURRENT_B0 101 3064 #define SFF_TXPOWER_B1 102 3065 #define SFF_TXPOWER_B0 103 3066 #define SFF_RXPOWER_B1 104 3067 #define SFF_RXPOWER_B0 105 3068 #define SSF_STATUS_CONTROL 110 3069 #define SSF_ALARM_FLAGS 112 3070 #define SSF_WARNING_FLAGS 116 3071 #define SSF_EXT_TATUS_CONTROL_B1 118 3072 #define SSF_EXT_TATUS_CONTROL_B0 119 3073 #define SSF_A2_VENDOR_SPECIFIC 120 3074 #define SSF_USER_EEPROM 128 3075 #define SSF_VENDOR_CONTROL 148 3076 3077 3078 /* 3079 * Tranceiver codes Fibre Channel SFF-8472 3080 * Table 3.5. 3081 */ 3082 3083 struct sff_trasnceiver_codes_byte0 { 3084 uint8_t inifiband:4; 3085 uint8_t teng_ethernet:4; 3086 }; 3087 3088 struct sff_trasnceiver_codes_byte1 { 3089 uint8_t sonet:6; 3090 uint8_t escon:2; 3091 }; 3092 3093 struct sff_trasnceiver_codes_byte2 { 3094 uint8_t soNet:8; 3095 }; 3096 3097 struct sff_trasnceiver_codes_byte3 { 3098 uint8_t ethernet:8; 3099 }; 3100 3101 struct sff_trasnceiver_codes_byte4 { 3102 uint8_t fc_el_lo:1; 3103 uint8_t fc_lw_laser:1; 3104 uint8_t fc_sw_laser:1; 3105 uint8_t fc_md_distance:1; 3106 uint8_t fc_lg_distance:1; 3107 uint8_t fc_int_distance:1; 3108 uint8_t fc_short_distance:1; 3109 uint8_t fc_vld_distance:1; 3110 }; 3111 3112 struct sff_trasnceiver_codes_byte5 { 3113 uint8_t reserved1:1; 3114 uint8_t reserved2:1; 3115 uint8_t fc_sfp_active:1; /* Active cable */ 3116 uint8_t fc_sfp_passive:1; /* Passive cable */ 3117 uint8_t fc_lw_laser:1; /* Longwave laser */ 3118 uint8_t fc_sw_laser_sl:1; 3119 uint8_t fc_sw_laser_sn:1; 3120 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3121 }; 3122 3123 struct sff_trasnceiver_codes_byte6 { 3124 uint8_t fc_tm_sm:1; /* Single Mode */ 3125 uint8_t reserved:1; 3126 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3127 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3128 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3129 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3130 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3131 }; 3132 3133 struct sff_trasnceiver_codes_byte7 { 3134 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3135 uint8_t reserve:1; 3136 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3137 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3138 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3139 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3140 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3141 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3142 }; 3143 3144 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3145 struct user_eeprom { 3146 uint8_t vendor_name[16]; 3147 uint8_t vendor_oui[3]; 3148 uint8_t vendor_pn[816]; 3149 uint8_t vendor_rev[4]; 3150 uint8_t vendor_sn[16]; 3151 uint8_t datecode[6]; 3152 uint8_t lot_code[2]; 3153 uint8_t reserved191[57]; 3154 }; 3155 3156 struct lpfc_mbx_pc_sli4_params { 3157 uint32_t word1; 3158 #define qs_SHIFT 0 3159 #define qs_MASK 0x00000001 3160 #define qs_WORD word1 3161 #define wr_SHIFT 1 3162 #define wr_MASK 0x00000001 3163 #define wr_WORD word1 3164 #define pf_SHIFT 8 3165 #define pf_MASK 0x000000ff 3166 #define pf_WORD word1 3167 #define cpn_SHIFT 16 3168 #define cpn_MASK 0x000000ff 3169 #define cpn_WORD word1 3170 uint32_t word2; 3171 #define if_type_SHIFT 0 3172 #define if_type_MASK 0x00000007 3173 #define if_type_WORD word2 3174 #define sli_rev_SHIFT 4 3175 #define sli_rev_MASK 0x0000000f 3176 #define sli_rev_WORD word2 3177 #define sli_family_SHIFT 8 3178 #define sli_family_MASK 0x000000ff 3179 #define sli_family_WORD word2 3180 #define featurelevel_1_SHIFT 16 3181 #define featurelevel_1_MASK 0x000000ff 3182 #define featurelevel_1_WORD word2 3183 #define featurelevel_2_SHIFT 24 3184 #define featurelevel_2_MASK 0x0000001f 3185 #define featurelevel_2_WORD word2 3186 uint32_t word3; 3187 #define fcoe_SHIFT 0 3188 #define fcoe_MASK 0x00000001 3189 #define fcoe_WORD word3 3190 #define fc_SHIFT 1 3191 #define fc_MASK 0x00000001 3192 #define fc_WORD word3 3193 #define nic_SHIFT 2 3194 #define nic_MASK 0x00000001 3195 #define nic_WORD word3 3196 #define iscsi_SHIFT 3 3197 #define iscsi_MASK 0x00000001 3198 #define iscsi_WORD word3 3199 #define rdma_SHIFT 4 3200 #define rdma_MASK 0x00000001 3201 #define rdma_WORD word3 3202 uint32_t sge_supp_len; 3203 #define SLI4_PAGE_SIZE 4096 3204 uint32_t word5; 3205 #define if_page_sz_SHIFT 0 3206 #define if_page_sz_MASK 0x0000ffff 3207 #define if_page_sz_WORD word5 3208 #define loopbk_scope_SHIFT 24 3209 #define loopbk_scope_MASK 0x0000000f 3210 #define loopbk_scope_WORD word5 3211 #define rq_db_window_SHIFT 28 3212 #define rq_db_window_MASK 0x0000000f 3213 #define rq_db_window_WORD word5 3214 uint32_t word6; 3215 #define eq_pages_SHIFT 0 3216 #define eq_pages_MASK 0x0000000f 3217 #define eq_pages_WORD word6 3218 #define eqe_size_SHIFT 8 3219 #define eqe_size_MASK 0x000000ff 3220 #define eqe_size_WORD word6 3221 uint32_t word7; 3222 #define cq_pages_SHIFT 0 3223 #define cq_pages_MASK 0x0000000f 3224 #define cq_pages_WORD word7 3225 #define cqe_size_SHIFT 8 3226 #define cqe_size_MASK 0x000000ff 3227 #define cqe_size_WORD word7 3228 uint32_t word8; 3229 #define mq_pages_SHIFT 0 3230 #define mq_pages_MASK 0x0000000f 3231 #define mq_pages_WORD word8 3232 #define mqe_size_SHIFT 8 3233 #define mqe_size_MASK 0x000000ff 3234 #define mqe_size_WORD word8 3235 #define mq_elem_cnt_SHIFT 16 3236 #define mq_elem_cnt_MASK 0x000000ff 3237 #define mq_elem_cnt_WORD word8 3238 uint32_t word9; 3239 #define wq_pages_SHIFT 0 3240 #define wq_pages_MASK 0x0000ffff 3241 #define wq_pages_WORD word9 3242 #define wqe_size_SHIFT 8 3243 #define wqe_size_MASK 0x000000ff 3244 #define wqe_size_WORD word9 3245 uint32_t word10; 3246 #define rq_pages_SHIFT 0 3247 #define rq_pages_MASK 0x0000ffff 3248 #define rq_pages_WORD word10 3249 #define rqe_size_SHIFT 8 3250 #define rqe_size_MASK 0x000000ff 3251 #define rqe_size_WORD word10 3252 uint32_t word11; 3253 #define hdr_pages_SHIFT 0 3254 #define hdr_pages_MASK 0x0000000f 3255 #define hdr_pages_WORD word11 3256 #define hdr_size_SHIFT 8 3257 #define hdr_size_MASK 0x0000000f 3258 #define hdr_size_WORD word11 3259 #define hdr_pp_align_SHIFT 16 3260 #define hdr_pp_align_MASK 0x0000ffff 3261 #define hdr_pp_align_WORD word11 3262 uint32_t word12; 3263 #define sgl_pages_SHIFT 0 3264 #define sgl_pages_MASK 0x0000000f 3265 #define sgl_pages_WORD word12 3266 #define sgl_pp_align_SHIFT 16 3267 #define sgl_pp_align_MASK 0x0000ffff 3268 #define sgl_pp_align_WORD word12 3269 uint32_t rsvd_13_63[51]; 3270 }; 3271 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3272 &(~((SLI4_PAGE_SIZE)-1))) 3273 3274 struct lpfc_sli4_parameters { 3275 uint32_t word0; 3276 #define cfg_prot_type_SHIFT 0 3277 #define cfg_prot_type_MASK 0x000000FF 3278 #define cfg_prot_type_WORD word0 3279 uint32_t word1; 3280 #define cfg_ft_SHIFT 0 3281 #define cfg_ft_MASK 0x00000001 3282 #define cfg_ft_WORD word1 3283 #define cfg_sli_rev_SHIFT 4 3284 #define cfg_sli_rev_MASK 0x0000000f 3285 #define cfg_sli_rev_WORD word1 3286 #define cfg_sli_family_SHIFT 8 3287 #define cfg_sli_family_MASK 0x0000000f 3288 #define cfg_sli_family_WORD word1 3289 #define cfg_if_type_SHIFT 12 3290 #define cfg_if_type_MASK 0x0000000f 3291 #define cfg_if_type_WORD word1 3292 #define cfg_sli_hint_1_SHIFT 16 3293 #define cfg_sli_hint_1_MASK 0x000000ff 3294 #define cfg_sli_hint_1_WORD word1 3295 #define cfg_sli_hint_2_SHIFT 24 3296 #define cfg_sli_hint_2_MASK 0x0000001f 3297 #define cfg_sli_hint_2_WORD word1 3298 uint32_t word2; 3299 #define cfg_eqav_SHIFT 31 3300 #define cfg_eqav_MASK 0x00000001 3301 #define cfg_eqav_WORD word2 3302 uint32_t word3; 3303 uint32_t word4; 3304 #define cfg_cqv_SHIFT 14 3305 #define cfg_cqv_MASK 0x00000003 3306 #define cfg_cqv_WORD word4 3307 #define cfg_cqpsize_SHIFT 16 3308 #define cfg_cqpsize_MASK 0x000000ff 3309 #define cfg_cqpsize_WORD word4 3310 #define cfg_cqav_SHIFT 31 3311 #define cfg_cqav_MASK 0x00000001 3312 #define cfg_cqav_WORD word4 3313 uint32_t word5; 3314 uint32_t word6; 3315 #define cfg_mqv_SHIFT 14 3316 #define cfg_mqv_MASK 0x00000003 3317 #define cfg_mqv_WORD word6 3318 uint32_t word7; 3319 uint32_t word8; 3320 #define cfg_wqpcnt_SHIFT 0 3321 #define cfg_wqpcnt_MASK 0x0000000f 3322 #define cfg_wqpcnt_WORD word8 3323 #define cfg_wqsize_SHIFT 8 3324 #define cfg_wqsize_MASK 0x0000000f 3325 #define cfg_wqsize_WORD word8 3326 #define cfg_wqv_SHIFT 14 3327 #define cfg_wqv_MASK 0x00000003 3328 #define cfg_wqv_WORD word8 3329 #define cfg_wqpsize_SHIFT 16 3330 #define cfg_wqpsize_MASK 0x000000ff 3331 #define cfg_wqpsize_WORD word8 3332 uint32_t word9; 3333 uint32_t word10; 3334 #define cfg_rqv_SHIFT 14 3335 #define cfg_rqv_MASK 0x00000003 3336 #define cfg_rqv_WORD word10 3337 uint32_t word11; 3338 #define cfg_rq_db_window_SHIFT 28 3339 #define cfg_rq_db_window_MASK 0x0000000f 3340 #define cfg_rq_db_window_WORD word11 3341 uint32_t word12; 3342 #define cfg_fcoe_SHIFT 0 3343 #define cfg_fcoe_MASK 0x00000001 3344 #define cfg_fcoe_WORD word12 3345 #define cfg_ext_SHIFT 1 3346 #define cfg_ext_MASK 0x00000001 3347 #define cfg_ext_WORD word12 3348 #define cfg_hdrr_SHIFT 2 3349 #define cfg_hdrr_MASK 0x00000001 3350 #define cfg_hdrr_WORD word12 3351 #define cfg_phwq_SHIFT 15 3352 #define cfg_phwq_MASK 0x00000001 3353 #define cfg_phwq_WORD word12 3354 #define cfg_oas_SHIFT 25 3355 #define cfg_oas_MASK 0x00000001 3356 #define cfg_oas_WORD word12 3357 #define cfg_loopbk_scope_SHIFT 28 3358 #define cfg_loopbk_scope_MASK 0x0000000f 3359 #define cfg_loopbk_scope_WORD word12 3360 uint32_t sge_supp_len; 3361 uint32_t word14; 3362 #define cfg_sgl_page_cnt_SHIFT 0 3363 #define cfg_sgl_page_cnt_MASK 0x0000000f 3364 #define cfg_sgl_page_cnt_WORD word14 3365 #define cfg_sgl_page_size_SHIFT 8 3366 #define cfg_sgl_page_size_MASK 0x000000ff 3367 #define cfg_sgl_page_size_WORD word14 3368 #define cfg_sgl_pp_align_SHIFT 16 3369 #define cfg_sgl_pp_align_MASK 0x000000ff 3370 #define cfg_sgl_pp_align_WORD word14 3371 uint32_t word15; 3372 uint32_t word16; 3373 uint32_t word17; 3374 uint32_t word18; 3375 uint32_t word19; 3376 #define cfg_ext_embed_cb_SHIFT 0 3377 #define cfg_ext_embed_cb_MASK 0x00000001 3378 #define cfg_ext_embed_cb_WORD word19 3379 #define cfg_mds_diags_SHIFT 1 3380 #define cfg_mds_diags_MASK 0x00000001 3381 #define cfg_mds_diags_WORD word19 3382 #define cfg_nvme_SHIFT 3 3383 #define cfg_nvme_MASK 0x00000001 3384 #define cfg_nvme_WORD word19 3385 #define cfg_xib_SHIFT 4 3386 #define cfg_xib_MASK 0x00000001 3387 #define cfg_xib_WORD word19 3388 #define cfg_eqdr_SHIFT 8 3389 #define cfg_eqdr_MASK 0x00000001 3390 #define cfg_eqdr_WORD word19 3391 #define cfg_nosr_SHIFT 9 3392 #define cfg_nosr_MASK 0x00000001 3393 #define cfg_nosr_WORD word19 3394 #define LPFC_NODELAY_MAX_IO 32 3395 }; 3396 3397 #define LPFC_SET_UE_RECOVERY 0x10 3398 #define LPFC_SET_MDS_DIAGS 0x11 3399 struct lpfc_mbx_set_feature { 3400 struct mbox_header header; 3401 uint32_t feature; 3402 uint32_t param_len; 3403 uint32_t word6; 3404 #define lpfc_mbx_set_feature_UER_SHIFT 0 3405 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3406 #define lpfc_mbx_set_feature_UER_WORD word6 3407 #define lpfc_mbx_set_feature_mds_SHIFT 0 3408 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3409 #define lpfc_mbx_set_feature_mds_WORD word6 3410 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3411 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3412 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3413 uint32_t word7; 3414 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3415 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3416 #define lpfc_mbx_set_feature_UERP_WORD word7 3417 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3418 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3419 #define lpfc_mbx_set_feature_UESR_WORD word7 3420 }; 3421 3422 3423 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3424 struct lpfc_mbx_set_host_data { 3425 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3426 struct mbox_header header; 3427 uint32_t param_id; 3428 uint32_t param_len; 3429 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3430 }; 3431 3432 3433 struct lpfc_mbx_get_sli4_parameters { 3434 struct mbox_header header; 3435 struct lpfc_sli4_parameters sli4_parameters; 3436 }; 3437 3438 struct lpfc_rscr_desc_generic { 3439 #define LPFC_RSRC_DESC_WSIZE 22 3440 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3441 }; 3442 3443 struct lpfc_rsrc_desc_pcie { 3444 uint32_t word0; 3445 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3446 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3447 #define lpfc_rsrc_desc_pcie_type_WORD word0 3448 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3449 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3450 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3451 #define lpfc_rsrc_desc_pcie_length_WORD word0 3452 uint32_t word1; 3453 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3454 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3455 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3456 uint32_t reserved; 3457 uint32_t word3; 3458 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3459 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3460 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3461 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3462 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3463 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3464 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3465 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3466 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3467 uint32_t word4; 3468 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3469 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3470 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3471 }; 3472 3473 struct lpfc_rsrc_desc_fcfcoe { 3474 uint32_t word0; 3475 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3476 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3477 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3478 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3479 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3480 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3481 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3482 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3483 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3484 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3485 uint32_t word1; 3486 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3487 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3488 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3489 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3490 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3491 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3492 uint32_t word2; 3493 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3494 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3495 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3496 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3497 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3498 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3499 uint32_t word3; 3500 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3501 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3502 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3503 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3504 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3505 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3506 uint32_t word4; 3507 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3508 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3509 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3510 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3511 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3512 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3513 uint32_t word5; 3514 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3515 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3516 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3517 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3518 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3519 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3520 uint32_t word6; 3521 uint32_t word7; 3522 uint32_t word8; 3523 uint32_t word9; 3524 uint32_t word10; 3525 uint32_t word11; 3526 uint32_t word12; 3527 uint32_t word13; 3528 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3529 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3530 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3531 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3532 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3533 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3534 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3535 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3536 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3537 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3538 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3539 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3540 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3541 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3542 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3543 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3544 uint32_t bw_min; 3545 uint32_t bw_max; 3546 uint32_t iops_min; 3547 uint32_t iops_max; 3548 uint32_t reserved[4]; 3549 }; 3550 3551 struct lpfc_func_cfg { 3552 #define LPFC_RSRC_DESC_MAX_NUM 2 3553 uint32_t rsrc_desc_count; 3554 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3555 }; 3556 3557 struct lpfc_mbx_get_func_cfg { 3558 struct mbox_header header; 3559 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3560 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3561 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3562 struct lpfc_func_cfg func_cfg; 3563 }; 3564 3565 struct lpfc_prof_cfg { 3566 #define LPFC_RSRC_DESC_MAX_NUM 2 3567 uint32_t rsrc_desc_count; 3568 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3569 }; 3570 3571 struct lpfc_mbx_get_prof_cfg { 3572 struct mbox_header header; 3573 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3574 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3575 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3576 union { 3577 struct { 3578 uint32_t word10; 3579 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3580 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3581 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3582 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3583 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3584 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3585 } request; 3586 struct { 3587 struct lpfc_prof_cfg prof_cfg; 3588 } response; 3589 } u; 3590 }; 3591 3592 struct lpfc_controller_attribute { 3593 uint32_t version_string[8]; 3594 uint32_t manufacturer_name[8]; 3595 uint32_t supported_modes; 3596 uint32_t word17; 3597 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3598 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3599 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3600 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3601 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3602 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3603 uint32_t mbx_da_struct_ver; 3604 uint32_t ep_fw_da_struct_ver; 3605 uint32_t ncsi_ver_str[3]; 3606 uint32_t dflt_ext_timeout; 3607 uint32_t model_number[8]; 3608 uint32_t description[16]; 3609 uint32_t serial_number[8]; 3610 uint32_t ip_ver_str[8]; 3611 uint32_t fw_ver_str[8]; 3612 uint32_t bios_ver_str[8]; 3613 uint32_t redboot_ver_str[8]; 3614 uint32_t driver_ver_str[8]; 3615 uint32_t flash_fw_ver_str[8]; 3616 uint32_t functionality; 3617 uint32_t word105; 3618 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3619 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3620 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3621 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3622 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3623 #define lpfc_cntl_attr_asic_rev_WORD word105 3624 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3625 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3626 #define lpfc_cntl_attr_gen_guid0_WORD word105 3627 uint32_t gen_guid1_12[3]; 3628 uint32_t word109; 3629 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3630 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3631 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3632 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3633 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3634 #define lpfc_cntl_attr_gen_guid15_WORD word109 3635 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3636 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3637 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3638 uint32_t word110; 3639 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3640 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3641 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3642 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3643 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3644 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3645 uint32_t word111; 3646 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3647 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3648 #define lpfc_cntl_attr_cache_valid_WORD word111 3649 #define lpfc_cntl_attr_hba_status_SHIFT 8 3650 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3651 #define lpfc_cntl_attr_hba_status_WORD word111 3652 #define lpfc_cntl_attr_max_domain_SHIFT 16 3653 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3654 #define lpfc_cntl_attr_max_domain_WORD word111 3655 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3656 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3657 #define lpfc_cntl_attr_lnk_numb_WORD word111 3658 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3659 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3660 #define lpfc_cntl_attr_lnk_type_WORD word111 3661 uint32_t fw_post_status; 3662 uint32_t hba_mtu[8]; 3663 uint32_t word121; 3664 uint32_t reserved1[3]; 3665 uint32_t word125; 3666 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3667 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3668 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3669 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3670 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3671 #define lpfc_cntl_attr_pci_device_id_WORD word125 3672 uint32_t word126; 3673 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3674 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3675 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3676 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3677 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3678 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3679 uint32_t word127; 3680 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3681 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3682 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3683 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3684 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3685 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3686 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3687 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3688 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3689 #define lpfc_cntl_attr_inf_type_SHIFT 24 3690 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3691 #define lpfc_cntl_attr_inf_type_WORD word127 3692 uint32_t unique_id[2]; 3693 uint32_t word130; 3694 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3695 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3696 #define lpfc_cntl_attr_num_netfil_WORD word130 3697 uint32_t reserved2[4]; 3698 }; 3699 3700 struct lpfc_mbx_get_cntl_attributes { 3701 union lpfc_sli4_cfg_shdr cfg_shdr; 3702 struct lpfc_controller_attribute cntl_attr; 3703 }; 3704 3705 struct lpfc_mbx_get_port_name { 3706 struct mbox_header header; 3707 union { 3708 struct { 3709 uint32_t word4; 3710 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3711 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3712 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3713 } request; 3714 struct { 3715 uint32_t word4; 3716 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3717 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3718 #define lpfc_mbx_get_port_name_name0_WORD word4 3719 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3720 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3721 #define lpfc_mbx_get_port_name_name1_WORD word4 3722 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3723 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3724 #define lpfc_mbx_get_port_name_name2_WORD word4 3725 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3726 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3727 #define lpfc_mbx_get_port_name_name3_WORD word4 3728 #define LPFC_LINK_NUMBER_0 0 3729 #define LPFC_LINK_NUMBER_1 1 3730 #define LPFC_LINK_NUMBER_2 2 3731 #define LPFC_LINK_NUMBER_3 3 3732 } response; 3733 } u; 3734 }; 3735 3736 /* Mailbox Completion Queue Error Messages */ 3737 #define MB_CQE_STATUS_SUCCESS 0x0 3738 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3739 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3740 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3741 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3742 #define MB_CQE_STATUS_DMA_FAILED 0x5 3743 3744 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3745 struct lpfc_mbx_wr_object { 3746 struct mbox_header header; 3747 union { 3748 struct { 3749 uint32_t word4; 3750 #define lpfc_wr_object_eof_SHIFT 31 3751 #define lpfc_wr_object_eof_MASK 0x00000001 3752 #define lpfc_wr_object_eof_WORD word4 3753 #define lpfc_wr_object_write_length_SHIFT 0 3754 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3755 #define lpfc_wr_object_write_length_WORD word4 3756 uint32_t write_offset; 3757 uint32_t object_name[26]; 3758 uint32_t bde_count; 3759 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3760 } request; 3761 struct { 3762 uint32_t actual_write_length; 3763 } response; 3764 } u; 3765 }; 3766 3767 /* mailbox queue entry structure */ 3768 struct lpfc_mqe { 3769 uint32_t word0; 3770 #define lpfc_mqe_status_SHIFT 16 3771 #define lpfc_mqe_status_MASK 0x0000FFFF 3772 #define lpfc_mqe_status_WORD word0 3773 #define lpfc_mqe_command_SHIFT 8 3774 #define lpfc_mqe_command_MASK 0x000000FF 3775 #define lpfc_mqe_command_WORD word0 3776 union { 3777 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3778 /* sli4 mailbox commands */ 3779 struct lpfc_mbx_sli4_config sli4_config; 3780 struct lpfc_mbx_init_vfi init_vfi; 3781 struct lpfc_mbx_reg_vfi reg_vfi; 3782 struct lpfc_mbx_reg_vfi unreg_vfi; 3783 struct lpfc_mbx_init_vpi init_vpi; 3784 struct lpfc_mbx_resume_rpi resume_rpi; 3785 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3786 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3787 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3788 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3789 struct lpfc_mbx_reg_fcfi reg_fcfi; 3790 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3791 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3792 struct lpfc_mbx_mq_create mq_create; 3793 struct lpfc_mbx_mq_create_ext mq_create_ext; 3794 struct lpfc_mbx_eq_create eq_create; 3795 struct lpfc_mbx_modify_eq_delay eq_delay; 3796 struct lpfc_mbx_cq_create cq_create; 3797 struct lpfc_mbx_cq_create_set cq_create_set; 3798 struct lpfc_mbx_wq_create wq_create; 3799 struct lpfc_mbx_rq_create rq_create; 3800 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3801 struct lpfc_mbx_mq_destroy mq_destroy; 3802 struct lpfc_mbx_eq_destroy eq_destroy; 3803 struct lpfc_mbx_cq_destroy cq_destroy; 3804 struct lpfc_mbx_wq_destroy wq_destroy; 3805 struct lpfc_mbx_rq_destroy rq_destroy; 3806 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3807 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3808 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3809 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3810 struct lpfc_mbx_nembed_cmd nembed_cmd; 3811 struct lpfc_mbx_read_rev read_rev; 3812 struct lpfc_mbx_read_vpi read_vpi; 3813 struct lpfc_mbx_read_config rd_config; 3814 struct lpfc_mbx_request_features req_ftrs; 3815 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3816 struct lpfc_mbx_query_fw_config query_fw_cfg; 3817 struct lpfc_mbx_set_beacon_config beacon_config; 3818 struct lpfc_mbx_supp_pages supp_pages; 3819 struct lpfc_mbx_pc_sli4_params sli4_params; 3820 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3821 struct lpfc_mbx_set_link_diag_state link_diag_state; 3822 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3823 struct lpfc_mbx_run_link_diag_test link_diag_test; 3824 struct lpfc_mbx_get_func_cfg get_func_cfg; 3825 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3826 struct lpfc_mbx_wr_object wr_object; 3827 struct lpfc_mbx_get_port_name get_port_name; 3828 struct lpfc_mbx_set_feature set_feature; 3829 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3830 struct lpfc_mbx_set_host_data set_host_data; 3831 struct lpfc_mbx_nop nop; 3832 } un; 3833 }; 3834 3835 struct lpfc_mcqe { 3836 uint32_t word0; 3837 #define lpfc_mcqe_status_SHIFT 0 3838 #define lpfc_mcqe_status_MASK 0x0000FFFF 3839 #define lpfc_mcqe_status_WORD word0 3840 #define lpfc_mcqe_ext_status_SHIFT 16 3841 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3842 #define lpfc_mcqe_ext_status_WORD word0 3843 uint32_t mcqe_tag0; 3844 uint32_t mcqe_tag1; 3845 uint32_t trailer; 3846 #define lpfc_trailer_valid_SHIFT 31 3847 #define lpfc_trailer_valid_MASK 0x00000001 3848 #define lpfc_trailer_valid_WORD trailer 3849 #define lpfc_trailer_async_SHIFT 30 3850 #define lpfc_trailer_async_MASK 0x00000001 3851 #define lpfc_trailer_async_WORD trailer 3852 #define lpfc_trailer_hpi_SHIFT 29 3853 #define lpfc_trailer_hpi_MASK 0x00000001 3854 #define lpfc_trailer_hpi_WORD trailer 3855 #define lpfc_trailer_completed_SHIFT 28 3856 #define lpfc_trailer_completed_MASK 0x00000001 3857 #define lpfc_trailer_completed_WORD trailer 3858 #define lpfc_trailer_consumed_SHIFT 27 3859 #define lpfc_trailer_consumed_MASK 0x00000001 3860 #define lpfc_trailer_consumed_WORD trailer 3861 #define lpfc_trailer_type_SHIFT 16 3862 #define lpfc_trailer_type_MASK 0x000000FF 3863 #define lpfc_trailer_type_WORD trailer 3864 #define lpfc_trailer_code_SHIFT 8 3865 #define lpfc_trailer_code_MASK 0x000000FF 3866 #define lpfc_trailer_code_WORD trailer 3867 #define LPFC_TRAILER_CODE_LINK 0x1 3868 #define LPFC_TRAILER_CODE_FCOE 0x2 3869 #define LPFC_TRAILER_CODE_DCBX 0x3 3870 #define LPFC_TRAILER_CODE_GRP5 0x5 3871 #define LPFC_TRAILER_CODE_FC 0x10 3872 #define LPFC_TRAILER_CODE_SLI 0x11 3873 }; 3874 3875 struct lpfc_acqe_link { 3876 uint32_t word0; 3877 #define lpfc_acqe_link_speed_SHIFT 24 3878 #define lpfc_acqe_link_speed_MASK 0x000000FF 3879 #define lpfc_acqe_link_speed_WORD word0 3880 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3881 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3882 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3883 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3884 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3885 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3886 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3887 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3888 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3889 #define lpfc_acqe_link_duplex_SHIFT 16 3890 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3891 #define lpfc_acqe_link_duplex_WORD word0 3892 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3893 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3894 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3895 #define lpfc_acqe_link_status_SHIFT 8 3896 #define lpfc_acqe_link_status_MASK 0x000000FF 3897 #define lpfc_acqe_link_status_WORD word0 3898 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3899 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3900 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3901 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3902 #define lpfc_acqe_link_type_SHIFT 6 3903 #define lpfc_acqe_link_type_MASK 0x00000003 3904 #define lpfc_acqe_link_type_WORD word0 3905 #define lpfc_acqe_link_number_SHIFT 0 3906 #define lpfc_acqe_link_number_MASK 0x0000003F 3907 #define lpfc_acqe_link_number_WORD word0 3908 uint32_t word1; 3909 #define lpfc_acqe_link_fault_SHIFT 0 3910 #define lpfc_acqe_link_fault_MASK 0x000000FF 3911 #define lpfc_acqe_link_fault_WORD word1 3912 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3913 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3914 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3915 #define lpfc_acqe_logical_link_speed_SHIFT 16 3916 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3917 #define lpfc_acqe_logical_link_speed_WORD word1 3918 uint32_t event_tag; 3919 uint32_t trailer; 3920 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3921 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3922 }; 3923 3924 struct lpfc_acqe_fip { 3925 uint32_t index; 3926 uint32_t word1; 3927 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3928 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3929 #define lpfc_acqe_fip_fcf_count_WORD word1 3930 #define lpfc_acqe_fip_event_type_SHIFT 16 3931 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3932 #define lpfc_acqe_fip_event_type_WORD word1 3933 uint32_t event_tag; 3934 uint32_t trailer; 3935 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3936 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3937 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3938 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3939 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3940 }; 3941 3942 struct lpfc_acqe_dcbx { 3943 uint32_t tlv_ttl; 3944 uint32_t reserved; 3945 uint32_t event_tag; 3946 uint32_t trailer; 3947 }; 3948 3949 struct lpfc_acqe_grp5 { 3950 uint32_t word0; 3951 #define lpfc_acqe_grp5_type_SHIFT 6 3952 #define lpfc_acqe_grp5_type_MASK 0x00000003 3953 #define lpfc_acqe_grp5_type_WORD word0 3954 #define lpfc_acqe_grp5_number_SHIFT 0 3955 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3956 #define lpfc_acqe_grp5_number_WORD word0 3957 uint32_t word1; 3958 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3959 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3960 #define lpfc_acqe_grp5_llink_spd_WORD word1 3961 uint32_t event_tag; 3962 uint32_t trailer; 3963 }; 3964 3965 struct lpfc_acqe_fc_la { 3966 uint32_t word0; 3967 #define lpfc_acqe_fc_la_speed_SHIFT 24 3968 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3969 #define lpfc_acqe_fc_la_speed_WORD word0 3970 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 3971 #define LPFC_FC_LA_SPEED_1G 0x1 3972 #define LPFC_FC_LA_SPEED_2G 0x2 3973 #define LPFC_FC_LA_SPEED_4G 0x4 3974 #define LPFC_FC_LA_SPEED_8G 0x8 3975 #define LPFC_FC_LA_SPEED_10G 0xA 3976 #define LPFC_FC_LA_SPEED_16G 0x10 3977 #define LPFC_FC_LA_SPEED_32G 0x20 3978 #define LPFC_FC_LA_SPEED_64G 0x21 3979 #define LPFC_FC_LA_SPEED_128G 0x22 3980 #define LPFC_FC_LA_SPEED_256G 0x23 3981 #define lpfc_acqe_fc_la_topology_SHIFT 16 3982 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3983 #define lpfc_acqe_fc_la_topology_WORD word0 3984 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3985 #define LPFC_FC_LA_TOP_P2P 0x1 3986 #define LPFC_FC_LA_TOP_FCAL 0x2 3987 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3988 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3989 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3990 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3991 #define lpfc_acqe_fc_la_att_type_WORD word0 3992 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3993 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3994 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3995 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 3996 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 3997 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 3998 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3999 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4000 #define lpfc_acqe_fc_la_port_type_WORD word0 4001 #define LPFC_LINK_TYPE_ETHERNET 0x0 4002 #define LPFC_LINK_TYPE_FC 0x1 4003 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4004 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4005 #define lpfc_acqe_fc_la_port_number_WORD word0 4006 uint32_t word1; 4007 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4008 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4009 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4010 #define lpfc_acqe_fc_la_fault_SHIFT 0 4011 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4012 #define lpfc_acqe_fc_la_fault_WORD word1 4013 #define LPFC_FC_LA_FAULT_NONE 0x0 4014 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4015 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4016 uint32_t event_tag; 4017 uint32_t trailer; 4018 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4019 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4020 }; 4021 4022 struct lpfc_acqe_misconfigured_event { 4023 struct { 4024 uint32_t word0; 4025 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4026 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4027 #define lpfc_sli_misconfigured_port0_state_WORD word0 4028 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4029 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4030 #define lpfc_sli_misconfigured_port1_state_WORD word0 4031 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4032 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4033 #define lpfc_sli_misconfigured_port2_state_WORD word0 4034 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4035 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4036 #define lpfc_sli_misconfigured_port3_state_WORD word0 4037 uint32_t word1; 4038 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4039 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4040 #define lpfc_sli_misconfigured_port0_op_WORD word1 4041 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4042 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4043 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4044 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4045 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4046 #define lpfc_sli_misconfigured_port1_op_WORD word1 4047 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4048 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4049 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4050 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4051 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4052 #define lpfc_sli_misconfigured_port2_op_WORD word1 4053 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4054 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4055 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4056 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4057 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4058 #define lpfc_sli_misconfigured_port3_op_WORD word1 4059 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4060 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4061 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4062 } theEvent; 4063 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4064 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4065 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4066 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4067 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4068 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4069 }; 4070 4071 struct lpfc_acqe_sli { 4072 uint32_t event_data1; 4073 uint32_t event_data2; 4074 uint32_t reserved; 4075 uint32_t trailer; 4076 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4077 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4078 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4079 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4080 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4081 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4082 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4083 }; 4084 4085 /* 4086 * Define the bootstrap mailbox (bmbx) region used to communicate 4087 * mailbox command between the host and port. The mailbox consists 4088 * of a payload area of 256 bytes and a completion queue of length 4089 * 16 bytes. 4090 */ 4091 struct lpfc_bmbx_create { 4092 struct lpfc_mqe mqe; 4093 struct lpfc_mcqe mcqe; 4094 }; 4095 4096 #define SGL_ALIGN_SZ 64 4097 #define SGL_PAGE_SIZE 4096 4098 /* align SGL addr on a size boundary - adjust address up */ 4099 #define NO_XRI 0xffff 4100 4101 struct wqe_common { 4102 uint32_t word6; 4103 #define wqe_xri_tag_SHIFT 0 4104 #define wqe_xri_tag_MASK 0x0000FFFF 4105 #define wqe_xri_tag_WORD word6 4106 #define wqe_ctxt_tag_SHIFT 16 4107 #define wqe_ctxt_tag_MASK 0x0000FFFF 4108 #define wqe_ctxt_tag_WORD word6 4109 uint32_t word7; 4110 #define wqe_dif_SHIFT 0 4111 #define wqe_dif_MASK 0x00000003 4112 #define wqe_dif_WORD word7 4113 #define LPFC_WQE_DIF_PASSTHRU 1 4114 #define LPFC_WQE_DIF_STRIP 2 4115 #define LPFC_WQE_DIF_INSERT 3 4116 #define wqe_ct_SHIFT 2 4117 #define wqe_ct_MASK 0x00000003 4118 #define wqe_ct_WORD word7 4119 #define wqe_status_SHIFT 4 4120 #define wqe_status_MASK 0x0000000f 4121 #define wqe_status_WORD word7 4122 #define wqe_cmnd_SHIFT 8 4123 #define wqe_cmnd_MASK 0x000000ff 4124 #define wqe_cmnd_WORD word7 4125 #define wqe_class_SHIFT 16 4126 #define wqe_class_MASK 0x00000007 4127 #define wqe_class_WORD word7 4128 #define wqe_ar_SHIFT 19 4129 #define wqe_ar_MASK 0x00000001 4130 #define wqe_ar_WORD word7 4131 #define wqe_ag_SHIFT wqe_ar_SHIFT 4132 #define wqe_ag_MASK wqe_ar_MASK 4133 #define wqe_ag_WORD wqe_ar_WORD 4134 #define wqe_pu_SHIFT 20 4135 #define wqe_pu_MASK 0x00000003 4136 #define wqe_pu_WORD word7 4137 #define wqe_erp_SHIFT 22 4138 #define wqe_erp_MASK 0x00000001 4139 #define wqe_erp_WORD word7 4140 #define wqe_conf_SHIFT wqe_erp_SHIFT 4141 #define wqe_conf_MASK wqe_erp_MASK 4142 #define wqe_conf_WORD wqe_erp_WORD 4143 #define wqe_lnk_SHIFT 23 4144 #define wqe_lnk_MASK 0x00000001 4145 #define wqe_lnk_WORD word7 4146 #define wqe_tmo_SHIFT 24 4147 #define wqe_tmo_MASK 0x000000ff 4148 #define wqe_tmo_WORD word7 4149 uint32_t abort_tag; /* word 8 in WQE */ 4150 uint32_t word9; 4151 #define wqe_reqtag_SHIFT 0 4152 #define wqe_reqtag_MASK 0x0000FFFF 4153 #define wqe_reqtag_WORD word9 4154 #define wqe_temp_rpi_SHIFT 16 4155 #define wqe_temp_rpi_MASK 0x0000FFFF 4156 #define wqe_temp_rpi_WORD word9 4157 #define wqe_rcvoxid_SHIFT 16 4158 #define wqe_rcvoxid_MASK 0x0000FFFF 4159 #define wqe_rcvoxid_WORD word9 4160 uint32_t word10; 4161 #define wqe_ebde_cnt_SHIFT 0 4162 #define wqe_ebde_cnt_MASK 0x0000000f 4163 #define wqe_ebde_cnt_WORD word10 4164 #define wqe_nvme_SHIFT 4 4165 #define wqe_nvme_MASK 0x00000001 4166 #define wqe_nvme_WORD word10 4167 #define wqe_oas_SHIFT 6 4168 #define wqe_oas_MASK 0x00000001 4169 #define wqe_oas_WORD word10 4170 #define wqe_lenloc_SHIFT 7 4171 #define wqe_lenloc_MASK 0x00000003 4172 #define wqe_lenloc_WORD word10 4173 #define LPFC_WQE_LENLOC_NONE 0 4174 #define LPFC_WQE_LENLOC_WORD3 1 4175 #define LPFC_WQE_LENLOC_WORD12 2 4176 #define LPFC_WQE_LENLOC_WORD4 3 4177 #define wqe_qosd_SHIFT 9 4178 #define wqe_qosd_MASK 0x00000001 4179 #define wqe_qosd_WORD word10 4180 #define wqe_xbl_SHIFT 11 4181 #define wqe_xbl_MASK 0x00000001 4182 #define wqe_xbl_WORD word10 4183 #define wqe_iod_SHIFT 13 4184 #define wqe_iod_MASK 0x00000001 4185 #define wqe_iod_WORD word10 4186 #define LPFC_WQE_IOD_NONE 0 4187 #define LPFC_WQE_IOD_WRITE 0 4188 #define LPFC_WQE_IOD_READ 1 4189 #define wqe_dbde_SHIFT 14 4190 #define wqe_dbde_MASK 0x00000001 4191 #define wqe_dbde_WORD word10 4192 #define wqe_wqes_SHIFT 15 4193 #define wqe_wqes_MASK 0x00000001 4194 #define wqe_wqes_WORD word10 4195 /* Note that this field overlaps above fields */ 4196 #define wqe_wqid_SHIFT 1 4197 #define wqe_wqid_MASK 0x00007fff 4198 #define wqe_wqid_WORD word10 4199 #define wqe_pri_SHIFT 16 4200 #define wqe_pri_MASK 0x00000007 4201 #define wqe_pri_WORD word10 4202 #define wqe_pv_SHIFT 19 4203 #define wqe_pv_MASK 0x00000001 4204 #define wqe_pv_WORD word10 4205 #define wqe_xc_SHIFT 21 4206 #define wqe_xc_MASK 0x00000001 4207 #define wqe_xc_WORD word10 4208 #define wqe_sr_SHIFT 22 4209 #define wqe_sr_MASK 0x00000001 4210 #define wqe_sr_WORD word10 4211 #define wqe_ccpe_SHIFT 23 4212 #define wqe_ccpe_MASK 0x00000001 4213 #define wqe_ccpe_WORD word10 4214 #define wqe_ccp_SHIFT 24 4215 #define wqe_ccp_MASK 0x000000ff 4216 #define wqe_ccp_WORD word10 4217 uint32_t word11; 4218 #define wqe_cmd_type_SHIFT 0 4219 #define wqe_cmd_type_MASK 0x0000000f 4220 #define wqe_cmd_type_WORD word11 4221 #define wqe_els_id_SHIFT 4 4222 #define wqe_els_id_MASK 0x00000003 4223 #define wqe_els_id_WORD word11 4224 #define LPFC_ELS_ID_FLOGI 3 4225 #define LPFC_ELS_ID_FDISC 2 4226 #define LPFC_ELS_ID_LOGO 1 4227 #define LPFC_ELS_ID_DEFAULT 0 4228 #define wqe_irsp_SHIFT 4 4229 #define wqe_irsp_MASK 0x00000001 4230 #define wqe_irsp_WORD word11 4231 #define wqe_pbde_SHIFT 5 4232 #define wqe_pbde_MASK 0x00000001 4233 #define wqe_pbde_WORD word11 4234 #define wqe_sup_SHIFT 6 4235 #define wqe_sup_MASK 0x00000001 4236 #define wqe_sup_WORD word11 4237 #define wqe_wqec_SHIFT 7 4238 #define wqe_wqec_MASK 0x00000001 4239 #define wqe_wqec_WORD word11 4240 #define wqe_irsplen_SHIFT 8 4241 #define wqe_irsplen_MASK 0x0000000f 4242 #define wqe_irsplen_WORD word11 4243 #define wqe_cqid_SHIFT 16 4244 #define wqe_cqid_MASK 0x0000ffff 4245 #define wqe_cqid_WORD word11 4246 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4247 }; 4248 4249 struct wqe_did { 4250 uint32_t word5; 4251 #define wqe_els_did_SHIFT 0 4252 #define wqe_els_did_MASK 0x00FFFFFF 4253 #define wqe_els_did_WORD word5 4254 #define wqe_xmit_bls_pt_SHIFT 28 4255 #define wqe_xmit_bls_pt_MASK 0x00000003 4256 #define wqe_xmit_bls_pt_WORD word5 4257 #define wqe_xmit_bls_ar_SHIFT 30 4258 #define wqe_xmit_bls_ar_MASK 0x00000001 4259 #define wqe_xmit_bls_ar_WORD word5 4260 #define wqe_xmit_bls_xo_SHIFT 31 4261 #define wqe_xmit_bls_xo_MASK 0x00000001 4262 #define wqe_xmit_bls_xo_WORD word5 4263 }; 4264 4265 struct lpfc_wqe_generic{ 4266 struct ulp_bde64 bde; 4267 uint32_t word3; 4268 uint32_t word4; 4269 uint32_t word5; 4270 struct wqe_common wqe_com; 4271 uint32_t payload[4]; 4272 }; 4273 4274 struct els_request64_wqe { 4275 struct ulp_bde64 bde; 4276 uint32_t payload_len; 4277 uint32_t word4; 4278 #define els_req64_sid_SHIFT 0 4279 #define els_req64_sid_MASK 0x00FFFFFF 4280 #define els_req64_sid_WORD word4 4281 #define els_req64_sp_SHIFT 24 4282 #define els_req64_sp_MASK 0x00000001 4283 #define els_req64_sp_WORD word4 4284 #define els_req64_vf_SHIFT 25 4285 #define els_req64_vf_MASK 0x00000001 4286 #define els_req64_vf_WORD word4 4287 struct wqe_did wqe_dest; 4288 struct wqe_common wqe_com; /* words 6-11 */ 4289 uint32_t word12; 4290 #define els_req64_vfid_SHIFT 1 4291 #define els_req64_vfid_MASK 0x00000FFF 4292 #define els_req64_vfid_WORD word12 4293 #define els_req64_pri_SHIFT 13 4294 #define els_req64_pri_MASK 0x00000007 4295 #define els_req64_pri_WORD word12 4296 uint32_t word13; 4297 #define els_req64_hopcnt_SHIFT 24 4298 #define els_req64_hopcnt_MASK 0x000000ff 4299 #define els_req64_hopcnt_WORD word13 4300 uint32_t word14; 4301 uint32_t max_response_payload_len; 4302 }; 4303 4304 struct xmit_els_rsp64_wqe { 4305 struct ulp_bde64 bde; 4306 uint32_t response_payload_len; 4307 uint32_t word4; 4308 #define els_rsp64_sid_SHIFT 0 4309 #define els_rsp64_sid_MASK 0x00FFFFFF 4310 #define els_rsp64_sid_WORD word4 4311 #define els_rsp64_sp_SHIFT 24 4312 #define els_rsp64_sp_MASK 0x00000001 4313 #define els_rsp64_sp_WORD word4 4314 struct wqe_did wqe_dest; 4315 struct wqe_common wqe_com; /* words 6-11 */ 4316 uint32_t word12; 4317 #define wqe_rsp_temp_rpi_SHIFT 0 4318 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4319 #define wqe_rsp_temp_rpi_WORD word12 4320 uint32_t rsvd_13_15[3]; 4321 }; 4322 4323 struct xmit_bls_rsp64_wqe { 4324 uint32_t payload0; 4325 /* Payload0 for BA_ACC */ 4326 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4327 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4328 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4329 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4330 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4331 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4332 /* Payload0 for BA_RJT */ 4333 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4334 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4335 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4336 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4337 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4338 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4339 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4340 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4341 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4342 uint32_t word1; 4343 #define xmit_bls_rsp64_rxid_SHIFT 0 4344 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4345 #define xmit_bls_rsp64_rxid_WORD word1 4346 #define xmit_bls_rsp64_oxid_SHIFT 16 4347 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4348 #define xmit_bls_rsp64_oxid_WORD word1 4349 uint32_t word2; 4350 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4351 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4352 #define xmit_bls_rsp64_seqcnthi_WORD word2 4353 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4354 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4355 #define xmit_bls_rsp64_seqcntlo_WORD word2 4356 uint32_t rsrvd3; 4357 uint32_t rsrvd4; 4358 struct wqe_did wqe_dest; 4359 struct wqe_common wqe_com; /* words 6-11 */ 4360 uint32_t word12; 4361 #define xmit_bls_rsp64_temprpi_SHIFT 0 4362 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4363 #define xmit_bls_rsp64_temprpi_WORD word12 4364 uint32_t rsvd_13_15[3]; 4365 }; 4366 4367 struct wqe_rctl_dfctl { 4368 uint32_t word5; 4369 #define wqe_si_SHIFT 2 4370 #define wqe_si_MASK 0x000000001 4371 #define wqe_si_WORD word5 4372 #define wqe_la_SHIFT 3 4373 #define wqe_la_MASK 0x000000001 4374 #define wqe_la_WORD word5 4375 #define wqe_xo_SHIFT 6 4376 #define wqe_xo_MASK 0x000000001 4377 #define wqe_xo_WORD word5 4378 #define wqe_ls_SHIFT 7 4379 #define wqe_ls_MASK 0x000000001 4380 #define wqe_ls_WORD word5 4381 #define wqe_dfctl_SHIFT 8 4382 #define wqe_dfctl_MASK 0x0000000ff 4383 #define wqe_dfctl_WORD word5 4384 #define wqe_type_SHIFT 16 4385 #define wqe_type_MASK 0x0000000ff 4386 #define wqe_type_WORD word5 4387 #define wqe_rctl_SHIFT 24 4388 #define wqe_rctl_MASK 0x0000000ff 4389 #define wqe_rctl_WORD word5 4390 }; 4391 4392 struct xmit_seq64_wqe { 4393 struct ulp_bde64 bde; 4394 uint32_t rsvd3; 4395 uint32_t relative_offset; 4396 struct wqe_rctl_dfctl wge_ctl; 4397 struct wqe_common wqe_com; /* words 6-11 */ 4398 uint32_t xmit_len; 4399 uint32_t rsvd_12_15[3]; 4400 }; 4401 struct xmit_bcast64_wqe { 4402 struct ulp_bde64 bde; 4403 uint32_t seq_payload_len; 4404 uint32_t rsvd4; 4405 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4406 struct wqe_common wqe_com; /* words 6-11 */ 4407 uint32_t rsvd_12_15[4]; 4408 }; 4409 4410 struct gen_req64_wqe { 4411 struct ulp_bde64 bde; 4412 uint32_t request_payload_len; 4413 uint32_t relative_offset; 4414 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4415 struct wqe_common wqe_com; /* words 6-11 */ 4416 uint32_t rsvd_12_14[3]; 4417 uint32_t max_response_payload_len; 4418 }; 4419 4420 /* Define NVME PRLI request to fabric. NVME is a 4421 * fabric-only protocol. 4422 * Updated to red-lined v1.08 on Sept 16, 2016 4423 */ 4424 struct lpfc_nvme_prli { 4425 uint32_t word1; 4426 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4427 #define prli_acc_rsp_code_SHIFT 8 4428 #define prli_acc_rsp_code_MASK 0x0000000f 4429 #define prli_acc_rsp_code_WORD word1 4430 #define prli_estabImagePair_SHIFT 13 4431 #define prli_estabImagePair_MASK 0x00000001 4432 #define prli_estabImagePair_WORD word1 4433 #define prli_type_code_ext_SHIFT 16 4434 #define prli_type_code_ext_MASK 0x000000ff 4435 #define prli_type_code_ext_WORD word1 4436 #define prli_type_code_SHIFT 24 4437 #define prli_type_code_MASK 0x000000ff 4438 #define prli_type_code_WORD word1 4439 uint32_t word_rsvd2; 4440 uint32_t word_rsvd3; 4441 uint32_t word4; 4442 #define prli_fba_SHIFT 0 4443 #define prli_fba_MASK 0x00000001 4444 #define prli_fba_WORD word4 4445 #define prli_disc_SHIFT 3 4446 #define prli_disc_MASK 0x00000001 4447 #define prli_disc_WORD word4 4448 #define prli_tgt_SHIFT 4 4449 #define prli_tgt_MASK 0x00000001 4450 #define prli_tgt_WORD word4 4451 #define prli_init_SHIFT 5 4452 #define prli_init_MASK 0x00000001 4453 #define prli_init_WORD word4 4454 #define prli_conf_SHIFT 7 4455 #define prli_conf_MASK 0x00000001 4456 #define prli_conf_WORD word4 4457 uint32_t word5; 4458 #define prli_fb_sz_SHIFT 0 4459 #define prli_fb_sz_MASK 0x0000ffff 4460 #define prli_fb_sz_WORD word5 4461 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4462 }; 4463 4464 struct create_xri_wqe { 4465 uint32_t rsrvd[5]; /* words 0-4 */ 4466 struct wqe_did wqe_dest; /* word 5 */ 4467 struct wqe_common wqe_com; /* words 6-11 */ 4468 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4469 }; 4470 4471 #define T_REQUEST_TAG 3 4472 #define T_XRI_TAG 1 4473 4474 struct abort_cmd_wqe { 4475 uint32_t rsrvd[3]; 4476 uint32_t word3; 4477 #define abort_cmd_ia_SHIFT 0 4478 #define abort_cmd_ia_MASK 0x000000001 4479 #define abort_cmd_ia_WORD word3 4480 #define abort_cmd_criteria_SHIFT 8 4481 #define abort_cmd_criteria_MASK 0x0000000ff 4482 #define abort_cmd_criteria_WORD word3 4483 uint32_t rsrvd4; 4484 uint32_t rsrvd5; 4485 struct wqe_common wqe_com; /* words 6-11 */ 4486 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4487 }; 4488 4489 struct fcp_iwrite64_wqe { 4490 struct ulp_bde64 bde; 4491 uint32_t word3; 4492 #define cmd_buff_len_SHIFT 16 4493 #define cmd_buff_len_MASK 0x00000ffff 4494 #define cmd_buff_len_WORD word3 4495 #define payload_offset_len_SHIFT 0 4496 #define payload_offset_len_MASK 0x0000ffff 4497 #define payload_offset_len_WORD word3 4498 uint32_t total_xfer_len; 4499 uint32_t initial_xfer_len; 4500 struct wqe_common wqe_com; /* words 6-11 */ 4501 uint32_t rsrvd12; 4502 struct ulp_bde64 ph_bde; /* words 13-15 */ 4503 }; 4504 4505 struct fcp_iread64_wqe { 4506 struct ulp_bde64 bde; 4507 uint32_t word3; 4508 #define cmd_buff_len_SHIFT 16 4509 #define cmd_buff_len_MASK 0x00000ffff 4510 #define cmd_buff_len_WORD word3 4511 #define payload_offset_len_SHIFT 0 4512 #define payload_offset_len_MASK 0x0000ffff 4513 #define payload_offset_len_WORD word3 4514 uint32_t total_xfer_len; /* word 4 */ 4515 uint32_t rsrvd5; /* word 5 */ 4516 struct wqe_common wqe_com; /* words 6-11 */ 4517 uint32_t rsrvd12; 4518 struct ulp_bde64 ph_bde; /* words 13-15 */ 4519 }; 4520 4521 struct fcp_icmnd64_wqe { 4522 struct ulp_bde64 bde; /* words 0-2 */ 4523 uint32_t word3; 4524 #define cmd_buff_len_SHIFT 16 4525 #define cmd_buff_len_MASK 0x00000ffff 4526 #define cmd_buff_len_WORD word3 4527 #define payload_offset_len_SHIFT 0 4528 #define payload_offset_len_MASK 0x0000ffff 4529 #define payload_offset_len_WORD word3 4530 uint32_t rsrvd4; /* word 4 */ 4531 uint32_t rsrvd5; /* word 5 */ 4532 struct wqe_common wqe_com; /* words 6-11 */ 4533 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4534 }; 4535 4536 struct fcp_trsp64_wqe { 4537 struct ulp_bde64 bde; 4538 uint32_t response_len; 4539 uint32_t rsvd_4_5[2]; 4540 struct wqe_common wqe_com; /* words 6-11 */ 4541 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4542 }; 4543 4544 struct fcp_tsend64_wqe { 4545 struct ulp_bde64 bde; 4546 uint32_t payload_offset_len; 4547 uint32_t relative_offset; 4548 uint32_t reserved; 4549 struct wqe_common wqe_com; /* words 6-11 */ 4550 uint32_t fcp_data_len; /* word 12 */ 4551 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4552 }; 4553 4554 struct fcp_treceive64_wqe { 4555 struct ulp_bde64 bde; 4556 uint32_t payload_offset_len; 4557 uint32_t relative_offset; 4558 uint32_t reserved; 4559 struct wqe_common wqe_com; /* words 6-11 */ 4560 uint32_t fcp_data_len; /* word 12 */ 4561 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4562 }; 4563 #define TXRDY_PAYLOAD_LEN 12 4564 4565 #define CMD_SEND_FRAME 0xE1 4566 4567 struct send_frame_wqe { 4568 struct ulp_bde64 bde; /* words 0-2 */ 4569 uint32_t frame_len; /* word 3 */ 4570 uint32_t fc_hdr_wd0; /* word 4 */ 4571 uint32_t fc_hdr_wd1; /* word 5 */ 4572 struct wqe_common wqe_com; /* words 6-11 */ 4573 uint32_t fc_hdr_wd2; /* word 12 */ 4574 uint32_t fc_hdr_wd3; /* word 13 */ 4575 uint32_t fc_hdr_wd4; /* word 14 */ 4576 uint32_t fc_hdr_wd5; /* word 15 */ 4577 }; 4578 4579 union lpfc_wqe { 4580 uint32_t words[16]; 4581 struct lpfc_wqe_generic generic; 4582 struct fcp_icmnd64_wqe fcp_icmd; 4583 struct fcp_iread64_wqe fcp_iread; 4584 struct fcp_iwrite64_wqe fcp_iwrite; 4585 struct abort_cmd_wqe abort_cmd; 4586 struct create_xri_wqe create_xri; 4587 struct xmit_bcast64_wqe xmit_bcast64; 4588 struct xmit_seq64_wqe xmit_sequence; 4589 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4590 struct xmit_els_rsp64_wqe xmit_els_rsp; 4591 struct els_request64_wqe els_req; 4592 struct gen_req64_wqe gen_req; 4593 struct fcp_trsp64_wqe fcp_trsp; 4594 struct fcp_tsend64_wqe fcp_tsend; 4595 struct fcp_treceive64_wqe fcp_treceive; 4596 struct send_frame_wqe send_frame; 4597 }; 4598 4599 union lpfc_wqe128 { 4600 uint32_t words[32]; 4601 struct lpfc_wqe_generic generic; 4602 struct fcp_icmnd64_wqe fcp_icmd; 4603 struct fcp_iread64_wqe fcp_iread; 4604 struct fcp_iwrite64_wqe fcp_iwrite; 4605 struct abort_cmd_wqe abort_cmd; 4606 struct create_xri_wqe create_xri; 4607 struct xmit_bcast64_wqe xmit_bcast64; 4608 struct xmit_seq64_wqe xmit_sequence; 4609 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4610 struct xmit_els_rsp64_wqe xmit_els_rsp; 4611 struct els_request64_wqe els_req; 4612 struct gen_req64_wqe gen_req; 4613 struct fcp_trsp64_wqe fcp_trsp; 4614 struct fcp_tsend64_wqe fcp_tsend; 4615 struct fcp_treceive64_wqe fcp_treceive; 4616 struct send_frame_wqe send_frame; 4617 }; 4618 4619 struct lpfc_grp_hdr { 4620 uint32_t size; 4621 uint32_t magic_number; 4622 uint32_t word2; 4623 #define lpfc_grp_hdr_file_type_SHIFT 24 4624 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4625 #define lpfc_grp_hdr_file_type_WORD word2 4626 #define lpfc_grp_hdr_id_SHIFT 16 4627 #define lpfc_grp_hdr_id_MASK 0x000000FF 4628 #define lpfc_grp_hdr_id_WORD word2 4629 uint8_t rev_name[128]; 4630 uint8_t date[12]; 4631 uint8_t revision[32]; 4632 }; 4633 4634 /* Defines for WQE command type */ 4635 #define FCP_COMMAND 0x0 4636 #define NVME_READ_CMD 0x0 4637 #define FCP_COMMAND_DATA_OUT 0x1 4638 #define NVME_WRITE_CMD 0x1 4639 #define FCP_COMMAND_TRECEIVE 0x2 4640 #define FCP_COMMAND_TRSP 0x3 4641 #define FCP_COMMAND_TSEND 0x7 4642 #define OTHER_COMMAND 0x8 4643 #define ELS_COMMAND_NON_FIP 0xC 4644 #define ELS_COMMAND_FIP 0xD 4645 4646 #define LPFC_NVME_EMBED_CMD 0x0 4647 #define LPFC_NVME_EMBED_WRITE 0x1 4648 #define LPFC_NVME_EMBED_READ 0x2 4649 4650 /* WQE Commands */ 4651 #define CMD_ABORT_XRI_WQE 0x0F 4652 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4653 #define CMD_XMIT_BCAST64_WQE 0x84 4654 #define CMD_ELS_REQUEST64_WQE 0x8A 4655 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4656 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4657 #define CMD_FCP_IWRITE64_WQE 0x98 4658 #define CMD_FCP_IREAD64_WQE 0x9A 4659 #define CMD_FCP_ICMND64_WQE 0x9C 4660 #define CMD_FCP_TSEND64_WQE 0x9F 4661 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4662 #define CMD_FCP_TRSP64_WQE 0xA3 4663 #define CMD_GEN_REQUEST64_WQE 0xC2 4664 4665 #define CMD_WQE_MASK 0xff 4666 4667 4668 #define LPFC_FW_DUMP 1 4669 #define LPFC_FW_RESET 2 4670 #define LPFC_DV_RESET 3 4671