1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get(name, ptr) \ 45 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 46 #define bf_set(name, ptr, value) \ 47 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 48 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 49 50 struct dma_address { 51 uint32_t addr_lo; 52 uint32_t addr_hi; 53 }; 54 55 #define LPFC_SLIREV_CONF_WORD 0x58 56 struct lpfc_sli_intf { 57 uint32_t word0; 58 #define lpfc_sli_intf_iftype_MASK 0x00000007 59 #define lpfc_sli_intf_iftype_SHIFT 0 60 #define lpfc_sli_intf_iftype_WORD word0 61 #define lpfc_sli_intf_rev_MASK 0x0000000f 62 #define lpfc_sli_intf_rev_SHIFT 4 63 #define lpfc_sli_intf_rev_WORD word0 64 #define LPFC_SLIREV_CONF_SLI4 4 65 #define lpfc_sli_intf_family_MASK 0x000000ff 66 #define lpfc_sli_intf_family_SHIFT 8 67 #define lpfc_sli_intf_family_WORD word0 68 #define lpfc_sli_intf_feat1_MASK 0x000000ff 69 #define lpfc_sli_intf_feat1_SHIFT 16 70 #define lpfc_sli_intf_feat1_WORD word0 71 #define lpfc_sli_intf_feat2_MASK 0x0000001f 72 #define lpfc_sli_intf_feat2_SHIFT 24 73 #define lpfc_sli_intf_feat2_WORD word0 74 #define lpfc_sli_intf_valid_MASK 0x00000007 75 #define lpfc_sli_intf_valid_SHIFT 29 76 #define lpfc_sli_intf_valid_WORD word0 77 #define LPFC_SLI_INTF_VALID 6 78 }; 79 80 #define LPFC_SLI4_BAR0 1 81 #define LPFC_SLI4_BAR1 2 82 #define LPFC_SLI4_BAR2 4 83 84 #define LPFC_SLI4_MBX_EMBED true 85 #define LPFC_SLI4_MBX_NEMBED false 86 87 #define LPFC_SLI4_MB_WORD_COUNT 64 88 #define LPFC_MAX_MQ_PAGE 8 89 #define LPFC_MAX_WQ_PAGE 8 90 #define LPFC_MAX_CQ_PAGE 4 91 #define LPFC_MAX_EQ_PAGE 8 92 93 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 94 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 95 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 96 97 /* Define SLI4 Alignment requirements. */ 98 #define LPFC_ALIGN_16_BYTE 16 99 #define LPFC_ALIGN_64_BYTE 64 100 101 /* Define SLI4 specific definitions. */ 102 #define LPFC_MQ_CQE_BYTE_OFFSET 256 103 #define LPFC_MBX_CMD_HDR_LENGTH 16 104 #define LPFC_MBX_ERROR_RANGE 0x4000 105 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 106 #define LPFC_BMBX_BIT1_ADDR_LO 0 107 #define LPFC_RPI_HDR_COUNT 64 108 #define LPFC_HDR_TEMPLATE_SIZE 4096 109 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 110 #define LPFC_FCF_RECORD_WD_CNT 132 111 #define LPFC_ENTIRE_FCF_DATABASE 0 112 #define LPFC_DFLT_FCF_INDEX 0 113 114 /* Virtual function numbers */ 115 #define LPFC_VF0 0 116 #define LPFC_VF1 1 117 #define LPFC_VF2 2 118 #define LPFC_VF3 3 119 #define LPFC_VF4 4 120 #define LPFC_VF5 5 121 #define LPFC_VF6 6 122 #define LPFC_VF7 7 123 #define LPFC_VF8 8 124 #define LPFC_VF9 9 125 #define LPFC_VF10 10 126 #define LPFC_VF11 11 127 #define LPFC_VF12 12 128 #define LPFC_VF13 13 129 #define LPFC_VF14 14 130 #define LPFC_VF15 15 131 #define LPFC_VF16 16 132 #define LPFC_VF17 17 133 #define LPFC_VF18 18 134 #define LPFC_VF19 19 135 #define LPFC_VF20 20 136 #define LPFC_VF21 21 137 #define LPFC_VF22 22 138 #define LPFC_VF23 23 139 #define LPFC_VF24 24 140 #define LPFC_VF25 25 141 #define LPFC_VF26 26 142 #define LPFC_VF27 27 143 #define LPFC_VF28 28 144 #define LPFC_VF29 29 145 #define LPFC_VF30 30 146 #define LPFC_VF31 31 147 148 /* PCI function numbers */ 149 #define LPFC_PCI_FUNC0 0 150 #define LPFC_PCI_FUNC1 1 151 #define LPFC_PCI_FUNC2 2 152 #define LPFC_PCI_FUNC3 3 153 #define LPFC_PCI_FUNC4 4 154 155 /* Active interrupt test count */ 156 #define LPFC_ACT_INTR_CNT 4 157 158 /* Delay Multiplier constant */ 159 #define LPFC_DMULT_CONST 651042 160 #define LPFC_MIM_IMAX 636 161 #define LPFC_FP_DEF_IMAX 10000 162 #define LPFC_SP_DEF_IMAX 10000 163 164 struct ulp_bde64 { 165 union ULP_BDE_TUS { 166 uint32_t w; 167 struct { 168 #ifdef __BIG_ENDIAN_BITFIELD 169 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 170 VALUE !! */ 171 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 172 #else /* __LITTLE_ENDIAN_BITFIELD */ 173 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 174 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 175 VALUE !! */ 176 #endif 177 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 178 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 179 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 180 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 181 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 182 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 183 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 184 } f; 185 } tus; 186 uint32_t addrLow; 187 uint32_t addrHigh; 188 }; 189 190 struct lpfc_sli4_flags { 191 uint32_t word0; 192 #define lpfc_fip_flag_SHIFT 0 193 #define lpfc_fip_flag_MASK 0x00000001 194 #define lpfc_fip_flag_WORD word0 195 }; 196 197 struct sli4_bls_acc { 198 uint32_t word0_rsvd; /* Word0 must be reserved */ 199 uint32_t word1; 200 #define lpfc_abts_orig_SHIFT 0 201 #define lpfc_abts_orig_MASK 0x00000001 202 #define lpfc_abts_orig_WORD word1 203 #define LPFC_ABTS_UNSOL_RSP 1 204 #define LPFC_ABTS_UNSOL_INT 0 205 uint32_t word2; 206 #define lpfc_abts_rxid_SHIFT 0 207 #define lpfc_abts_rxid_MASK 0x0000FFFF 208 #define lpfc_abts_rxid_WORD word2 209 #define lpfc_abts_oxid_SHIFT 16 210 #define lpfc_abts_oxid_MASK 0x0000FFFF 211 #define lpfc_abts_oxid_WORD word2 212 uint32_t word3; 213 uint32_t word4; 214 uint32_t word5_rsvd; /* Word5 must be reserved */ 215 }; 216 217 /* event queue entry structure */ 218 struct lpfc_eqe { 219 uint32_t word0; 220 #define lpfc_eqe_resource_id_SHIFT 16 221 #define lpfc_eqe_resource_id_MASK 0x000000FF 222 #define lpfc_eqe_resource_id_WORD word0 223 #define lpfc_eqe_minor_code_SHIFT 4 224 #define lpfc_eqe_minor_code_MASK 0x00000FFF 225 #define lpfc_eqe_minor_code_WORD word0 226 #define lpfc_eqe_major_code_SHIFT 1 227 #define lpfc_eqe_major_code_MASK 0x00000007 228 #define lpfc_eqe_major_code_WORD word0 229 #define lpfc_eqe_valid_SHIFT 0 230 #define lpfc_eqe_valid_MASK 0x00000001 231 #define lpfc_eqe_valid_WORD word0 232 }; 233 234 /* completion queue entry structure (common fields for all cqe types) */ 235 struct lpfc_cqe { 236 uint32_t reserved0; 237 uint32_t reserved1; 238 uint32_t reserved2; 239 uint32_t word3; 240 #define lpfc_cqe_valid_SHIFT 31 241 #define lpfc_cqe_valid_MASK 0x00000001 242 #define lpfc_cqe_valid_WORD word3 243 #define lpfc_cqe_code_SHIFT 16 244 #define lpfc_cqe_code_MASK 0x000000FF 245 #define lpfc_cqe_code_WORD word3 246 }; 247 248 /* Completion Queue Entry Status Codes */ 249 #define CQE_STATUS_SUCCESS 0x0 250 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 251 #define CQE_STATUS_REMOTE_STOP 0x2 252 #define CQE_STATUS_LOCAL_REJECT 0x3 253 #define CQE_STATUS_NPORT_RJT 0x4 254 #define CQE_STATUS_FABRIC_RJT 0x5 255 #define CQE_STATUS_NPORT_BSY 0x6 256 #define CQE_STATUS_FABRIC_BSY 0x7 257 #define CQE_STATUS_INTERMED_RSP 0x8 258 #define CQE_STATUS_LS_RJT 0x9 259 #define CQE_STATUS_CMD_REJECT 0xb 260 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 261 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 262 263 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 264 #define CQE_HW_STATUS_NO_ERR 0x0 265 #define CQE_HW_STATUS_UNDERRUN 0x1 266 #define CQE_HW_STATUS_OVERRUN 0x2 267 268 /* Completion Queue Entry Codes */ 269 #define CQE_CODE_COMPL_WQE 0x1 270 #define CQE_CODE_RELEASE_WQE 0x2 271 #define CQE_CODE_RECEIVE 0x4 272 #define CQE_CODE_XRI_ABORTED 0x5 273 274 /* completion queue entry for wqe completions */ 275 struct lpfc_wcqe_complete { 276 uint32_t word0; 277 #define lpfc_wcqe_c_request_tag_SHIFT 16 278 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 279 #define lpfc_wcqe_c_request_tag_WORD word0 280 #define lpfc_wcqe_c_status_SHIFT 8 281 #define lpfc_wcqe_c_status_MASK 0x000000FF 282 #define lpfc_wcqe_c_status_WORD word0 283 #define lpfc_wcqe_c_hw_status_SHIFT 0 284 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 285 #define lpfc_wcqe_c_hw_status_WORD word0 286 uint32_t total_data_placed; 287 uint32_t parameter; 288 uint32_t word3; 289 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 290 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 291 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 292 #define lpfc_wcqe_c_xb_SHIFT 28 293 #define lpfc_wcqe_c_xb_MASK 0x00000001 294 #define lpfc_wcqe_c_xb_WORD word3 295 #define lpfc_wcqe_c_pv_SHIFT 27 296 #define lpfc_wcqe_c_pv_MASK 0x00000001 297 #define lpfc_wcqe_c_pv_WORD word3 298 #define lpfc_wcqe_c_priority_SHIFT 24 299 #define lpfc_wcqe_c_priority_MASK 0x00000007 300 #define lpfc_wcqe_c_priority_WORD word3 301 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 302 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 303 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 304 }; 305 306 /* completion queue entry for wqe release */ 307 struct lpfc_wcqe_release { 308 uint32_t reserved0; 309 uint32_t reserved1; 310 uint32_t word2; 311 #define lpfc_wcqe_r_wq_id_SHIFT 16 312 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 313 #define lpfc_wcqe_r_wq_id_WORD word2 314 #define lpfc_wcqe_r_wqe_index_SHIFT 0 315 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 316 #define lpfc_wcqe_r_wqe_index_WORD word2 317 uint32_t word3; 318 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 319 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 320 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 321 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 322 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 323 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 324 }; 325 326 struct sli4_wcqe_xri_aborted { 327 uint32_t word0; 328 #define lpfc_wcqe_xa_status_SHIFT 8 329 #define lpfc_wcqe_xa_status_MASK 0x000000FF 330 #define lpfc_wcqe_xa_status_WORD word0 331 uint32_t parameter; 332 uint32_t word2; 333 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 334 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 335 #define lpfc_wcqe_xa_remote_xid_WORD word2 336 #define lpfc_wcqe_xa_xri_SHIFT 0 337 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 338 #define lpfc_wcqe_xa_xri_WORD word2 339 uint32_t word3; 340 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 341 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 342 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 343 #define lpfc_wcqe_xa_ia_SHIFT 30 344 #define lpfc_wcqe_xa_ia_MASK 0x00000001 345 #define lpfc_wcqe_xa_ia_WORD word3 346 #define CQE_XRI_ABORTED_IA_REMOTE 0 347 #define CQE_XRI_ABORTED_IA_LOCAL 1 348 #define lpfc_wcqe_xa_br_SHIFT 29 349 #define lpfc_wcqe_xa_br_MASK 0x00000001 350 #define lpfc_wcqe_xa_br_WORD word3 351 #define CQE_XRI_ABORTED_BR_BA_ACC 0 352 #define CQE_XRI_ABORTED_BR_BA_RJT 1 353 #define lpfc_wcqe_xa_eo_SHIFT 28 354 #define lpfc_wcqe_xa_eo_MASK 0x00000001 355 #define lpfc_wcqe_xa_eo_WORD word3 356 #define CQE_XRI_ABORTED_EO_REMOTE 0 357 #define CQE_XRI_ABORTED_EO_LOCAL 1 358 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 359 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 360 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 361 }; 362 363 /* completion queue entry structure for rqe completion */ 364 struct lpfc_rcqe { 365 uint32_t word0; 366 #define lpfc_rcqe_bindex_SHIFT 16 367 #define lpfc_rcqe_bindex_MASK 0x0000FFF 368 #define lpfc_rcqe_bindex_WORD word0 369 #define lpfc_rcqe_status_SHIFT 8 370 #define lpfc_rcqe_status_MASK 0x000000FF 371 #define lpfc_rcqe_status_WORD word0 372 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 373 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 374 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 375 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 376 uint32_t reserved1; 377 uint32_t word2; 378 #define lpfc_rcqe_length_SHIFT 16 379 #define lpfc_rcqe_length_MASK 0x0000FFFF 380 #define lpfc_rcqe_length_WORD word2 381 #define lpfc_rcqe_rq_id_SHIFT 6 382 #define lpfc_rcqe_rq_id_MASK 0x000003FF 383 #define lpfc_rcqe_rq_id_WORD word2 384 #define lpfc_rcqe_fcf_id_SHIFT 0 385 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 386 #define lpfc_rcqe_fcf_id_WORD word2 387 uint32_t word3; 388 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 389 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 390 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 391 #define lpfc_rcqe_port_SHIFT 30 392 #define lpfc_rcqe_port_MASK 0x00000001 393 #define lpfc_rcqe_port_WORD word3 394 #define lpfc_rcqe_hdr_length_SHIFT 24 395 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 396 #define lpfc_rcqe_hdr_length_WORD word3 397 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 398 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 399 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 400 #define lpfc_rcqe_eof_SHIFT 8 401 #define lpfc_rcqe_eof_MASK 0x000000FF 402 #define lpfc_rcqe_eof_WORD word3 403 #define FCOE_EOFn 0x41 404 #define FCOE_EOFt 0x42 405 #define FCOE_EOFni 0x49 406 #define FCOE_EOFa 0x50 407 #define lpfc_rcqe_sof_SHIFT 0 408 #define lpfc_rcqe_sof_MASK 0x000000FF 409 #define lpfc_rcqe_sof_WORD word3 410 #define FCOE_SOFi2 0x2d 411 #define FCOE_SOFi3 0x2e 412 #define FCOE_SOFn2 0x35 413 #define FCOE_SOFn3 0x36 414 }; 415 416 struct lpfc_wqe_generic{ 417 struct ulp_bde64 bde; 418 uint32_t word3; 419 uint32_t word4; 420 uint32_t word5; 421 uint32_t word6; 422 #define lpfc_wqe_gen_context_SHIFT 16 423 #define lpfc_wqe_gen_context_MASK 0x0000FFFF 424 #define lpfc_wqe_gen_context_WORD word6 425 #define lpfc_wqe_gen_xri_SHIFT 0 426 #define lpfc_wqe_gen_xri_MASK 0x0000FFFF 427 #define lpfc_wqe_gen_xri_WORD word6 428 uint32_t word7; 429 #define lpfc_wqe_gen_lnk_SHIFT 23 430 #define lpfc_wqe_gen_lnk_MASK 0x00000001 431 #define lpfc_wqe_gen_lnk_WORD word7 432 #define lpfc_wqe_gen_erp_SHIFT 22 433 #define lpfc_wqe_gen_erp_MASK 0x00000001 434 #define lpfc_wqe_gen_erp_WORD word7 435 #define lpfc_wqe_gen_pu_SHIFT 20 436 #define lpfc_wqe_gen_pu_MASK 0x00000003 437 #define lpfc_wqe_gen_pu_WORD word7 438 #define lpfc_wqe_gen_class_SHIFT 16 439 #define lpfc_wqe_gen_class_MASK 0x00000007 440 #define lpfc_wqe_gen_class_WORD word7 441 #define lpfc_wqe_gen_command_SHIFT 8 442 #define lpfc_wqe_gen_command_MASK 0x000000FF 443 #define lpfc_wqe_gen_command_WORD word7 444 #define lpfc_wqe_gen_status_SHIFT 4 445 #define lpfc_wqe_gen_status_MASK 0x0000000F 446 #define lpfc_wqe_gen_status_WORD word7 447 #define lpfc_wqe_gen_ct_SHIFT 2 448 #define lpfc_wqe_gen_ct_MASK 0x00000003 449 #define lpfc_wqe_gen_ct_WORD word7 450 uint32_t abort_tag; 451 uint32_t word9; 452 #define lpfc_wqe_gen_request_tag_SHIFT 0 453 #define lpfc_wqe_gen_request_tag_MASK 0x0000FFFF 454 #define lpfc_wqe_gen_request_tag_WORD word9 455 uint32_t word10; 456 #define lpfc_wqe_gen_ccp_SHIFT 24 457 #define lpfc_wqe_gen_ccp_MASK 0x000000FF 458 #define lpfc_wqe_gen_ccp_WORD word10 459 #define lpfc_wqe_gen_ccpe_SHIFT 23 460 #define lpfc_wqe_gen_ccpe_MASK 0x00000001 461 #define lpfc_wqe_gen_ccpe_WORD word10 462 #define lpfc_wqe_gen_pv_SHIFT 19 463 #define lpfc_wqe_gen_pv_MASK 0x00000001 464 #define lpfc_wqe_gen_pv_WORD word10 465 #define lpfc_wqe_gen_pri_SHIFT 16 466 #define lpfc_wqe_gen_pri_MASK 0x00000007 467 #define lpfc_wqe_gen_pri_WORD word10 468 uint32_t word11; 469 #define lpfc_wqe_gen_cq_id_SHIFT 16 470 #define lpfc_wqe_gen_cq_id_MASK 0x0000FFFF 471 #define lpfc_wqe_gen_cq_id_WORD word11 472 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 473 #define lpfc_wqe_gen_wqec_SHIFT 7 474 #define lpfc_wqe_gen_wqec_MASK 0x00000001 475 #define lpfc_wqe_gen_wqec_WORD word11 476 #define ELS_ID_FLOGI 3 477 #define ELS_ID_FDISC 2 478 #define ELS_ID_LOGO 1 479 #define ELS_ID_DEFAULT 0 480 #define lpfc_wqe_gen_els_id_SHIFT 4 481 #define lpfc_wqe_gen_els_id_MASK 0x00000003 482 #define lpfc_wqe_gen_els_id_WORD word11 483 #define lpfc_wqe_gen_cmd_type_SHIFT 0 484 #define lpfc_wqe_gen_cmd_type_MASK 0x0000000F 485 #define lpfc_wqe_gen_cmd_type_WORD word11 486 uint32_t payload[4]; 487 }; 488 489 struct lpfc_rqe { 490 uint32_t address_hi; 491 uint32_t address_lo; 492 }; 493 494 /* buffer descriptors */ 495 struct lpfc_bde4 { 496 uint32_t addr_hi; 497 uint32_t addr_lo; 498 uint32_t word2; 499 #define lpfc_bde4_last_SHIFT 31 500 #define lpfc_bde4_last_MASK 0x00000001 501 #define lpfc_bde4_last_WORD word2 502 #define lpfc_bde4_sge_offset_SHIFT 0 503 #define lpfc_bde4_sge_offset_MASK 0x000003FF 504 #define lpfc_bde4_sge_offset_WORD word2 505 uint32_t word3; 506 #define lpfc_bde4_length_SHIFT 0 507 #define lpfc_bde4_length_MASK 0x000000FF 508 #define lpfc_bde4_length_WORD word3 509 }; 510 511 struct lpfc_register { 512 uint32_t word0; 513 }; 514 515 #define LPFC_UERR_STATUS_HI 0x00A4 516 #define LPFC_UERR_STATUS_LO 0x00A0 517 #define LPFC_UE_MASK_HI 0x00AC 518 #define LPFC_UE_MASK_LO 0x00A8 519 #define LPFC_SCRATCHPAD 0x0058 520 521 /* BAR0 Registers */ 522 #define LPFC_HST_STATE 0x00AC 523 #define lpfc_hst_state_perr_SHIFT 31 524 #define lpfc_hst_state_perr_MASK 0x1 525 #define lpfc_hst_state_perr_WORD word0 526 #define lpfc_hst_state_sfi_SHIFT 30 527 #define lpfc_hst_state_sfi_MASK 0x1 528 #define lpfc_hst_state_sfi_WORD word0 529 #define lpfc_hst_state_nip_SHIFT 29 530 #define lpfc_hst_state_nip_MASK 0x1 531 #define lpfc_hst_state_nip_WORD word0 532 #define lpfc_hst_state_ipc_SHIFT 28 533 #define lpfc_hst_state_ipc_MASK 0x1 534 #define lpfc_hst_state_ipc_WORD word0 535 #define lpfc_hst_state_xrom_SHIFT 27 536 #define lpfc_hst_state_xrom_MASK 0x1 537 #define lpfc_hst_state_xrom_WORD word0 538 #define lpfc_hst_state_dl_SHIFT 26 539 #define lpfc_hst_state_dl_MASK 0x1 540 #define lpfc_hst_state_dl_WORD word0 541 #define lpfc_hst_state_port_status_SHIFT 0 542 #define lpfc_hst_state_port_status_MASK 0xFFFF 543 #define lpfc_hst_state_port_status_WORD word0 544 545 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 546 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 547 #define LPFC_POST_STAGE_HOST_RDY 0x0002 548 #define LPFC_POST_STAGE_BE_RESET 0x0003 549 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 550 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 551 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 552 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 553 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 554 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 555 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 556 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 557 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 558 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 559 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 560 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 561 #define LPFC_POST_STAGE_ARMFW_START 0x0800 562 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 563 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 564 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 565 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 566 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 567 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 568 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 569 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 570 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 571 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 572 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 573 #define LPFC_POST_STAGE_RC_DONE 0x0B07 574 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 575 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 576 #define LPFC_POST_STAGE_ARMFW_READY 0xC000 577 #define LPFC_POST_STAGE_ARMFW_UE 0xF000 578 579 #define lpfc_scratchpad_slirev_SHIFT 4 580 #define lpfc_scratchpad_slirev_MASK 0xF 581 #define lpfc_scratchpad_slirev_WORD word0 582 #define lpfc_scratchpad_chiptype_SHIFT 8 583 #define lpfc_scratchpad_chiptype_MASK 0xFF 584 #define lpfc_scratchpad_chiptype_WORD word0 585 #define lpfc_scratchpad_featurelevel1_SHIFT 16 586 #define lpfc_scratchpad_featurelevel1_MASK 0xFF 587 #define lpfc_scratchpad_featurelevel1_WORD word0 588 #define lpfc_scratchpad_featurelevel2_SHIFT 24 589 #define lpfc_scratchpad_featurelevel2_MASK 0xFF 590 #define lpfc_scratchpad_featurelevel2_WORD word0 591 592 /* BAR1 Registers */ 593 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 594 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 595 596 #define LPFC_HST_ISR0 0x0C18 597 #define LPFC_HST_ISR1 0x0C1C 598 #define LPFC_HST_ISR2 0x0C20 599 #define LPFC_HST_ISR3 0x0C24 600 #define LPFC_HST_ISR4 0x0C28 601 602 #define LPFC_HST_IMR0 0x0C48 603 #define LPFC_HST_IMR1 0x0C4C 604 #define LPFC_HST_IMR2 0x0C50 605 #define LPFC_HST_IMR3 0x0C54 606 #define LPFC_HST_IMR4 0x0C58 607 608 #define LPFC_HST_ISCR0 0x0C78 609 #define LPFC_HST_ISCR1 0x0C7C 610 #define LPFC_HST_ISCR2 0x0C80 611 #define LPFC_HST_ISCR3 0x0C84 612 #define LPFC_HST_ISCR4 0x0C88 613 614 #define LPFC_SLI4_INTR0 BIT0 615 #define LPFC_SLI4_INTR1 BIT1 616 #define LPFC_SLI4_INTR2 BIT2 617 #define LPFC_SLI4_INTR3 BIT3 618 #define LPFC_SLI4_INTR4 BIT4 619 #define LPFC_SLI4_INTR5 BIT5 620 #define LPFC_SLI4_INTR6 BIT6 621 #define LPFC_SLI4_INTR7 BIT7 622 #define LPFC_SLI4_INTR8 BIT8 623 #define LPFC_SLI4_INTR9 BIT9 624 #define LPFC_SLI4_INTR10 BIT10 625 #define LPFC_SLI4_INTR11 BIT11 626 #define LPFC_SLI4_INTR12 BIT12 627 #define LPFC_SLI4_INTR13 BIT13 628 #define LPFC_SLI4_INTR14 BIT14 629 #define LPFC_SLI4_INTR15 BIT15 630 #define LPFC_SLI4_INTR16 BIT16 631 #define LPFC_SLI4_INTR17 BIT17 632 #define LPFC_SLI4_INTR18 BIT18 633 #define LPFC_SLI4_INTR19 BIT19 634 #define LPFC_SLI4_INTR20 BIT20 635 #define LPFC_SLI4_INTR21 BIT21 636 #define LPFC_SLI4_INTR22 BIT22 637 #define LPFC_SLI4_INTR23 BIT23 638 #define LPFC_SLI4_INTR24 BIT24 639 #define LPFC_SLI4_INTR25 BIT25 640 #define LPFC_SLI4_INTR26 BIT26 641 #define LPFC_SLI4_INTR27 BIT27 642 #define LPFC_SLI4_INTR28 BIT28 643 #define LPFC_SLI4_INTR29 BIT29 644 #define LPFC_SLI4_INTR30 BIT30 645 #define LPFC_SLI4_INTR31 BIT31 646 647 /* BAR2 Registers */ 648 #define LPFC_RQ_DOORBELL 0x00A0 649 #define lpfc_rq_doorbell_num_posted_SHIFT 16 650 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 651 #define lpfc_rq_doorbell_num_posted_WORD word0 652 #define LPFC_RQ_POST_BATCH 8 /* RQEs to post at one time */ 653 #define lpfc_rq_doorbell_id_SHIFT 0 654 #define lpfc_rq_doorbell_id_MASK 0x03FF 655 #define lpfc_rq_doorbell_id_WORD word0 656 657 #define LPFC_WQ_DOORBELL 0x0040 658 #define lpfc_wq_doorbell_num_posted_SHIFT 24 659 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF 660 #define lpfc_wq_doorbell_num_posted_WORD word0 661 #define lpfc_wq_doorbell_index_SHIFT 16 662 #define lpfc_wq_doorbell_index_MASK 0x00FF 663 #define lpfc_wq_doorbell_index_WORD word0 664 #define lpfc_wq_doorbell_id_SHIFT 0 665 #define lpfc_wq_doorbell_id_MASK 0xFFFF 666 #define lpfc_wq_doorbell_id_WORD word0 667 668 #define LPFC_EQCQ_DOORBELL 0x0120 669 #define lpfc_eqcq_doorbell_arm_SHIFT 29 670 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 671 #define lpfc_eqcq_doorbell_arm_WORD word0 672 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 673 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 674 #define lpfc_eqcq_doorbell_num_released_WORD word0 675 #define lpfc_eqcq_doorbell_qt_SHIFT 10 676 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 677 #define lpfc_eqcq_doorbell_qt_WORD word0 678 #define LPFC_QUEUE_TYPE_COMPLETION 0 679 #define LPFC_QUEUE_TYPE_EVENT 1 680 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 681 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 682 #define lpfc_eqcq_doorbell_eqci_WORD word0 683 #define lpfc_eqcq_doorbell_cqid_SHIFT 0 684 #define lpfc_eqcq_doorbell_cqid_MASK 0x03FF 685 #define lpfc_eqcq_doorbell_cqid_WORD word0 686 #define lpfc_eqcq_doorbell_eqid_SHIFT 0 687 #define lpfc_eqcq_doorbell_eqid_MASK 0x01FF 688 #define lpfc_eqcq_doorbell_eqid_WORD word0 689 690 #define LPFC_BMBX 0x0160 691 #define lpfc_bmbx_addr_SHIFT 2 692 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 693 #define lpfc_bmbx_addr_WORD word0 694 #define lpfc_bmbx_hi_SHIFT 1 695 #define lpfc_bmbx_hi_MASK 0x0001 696 #define lpfc_bmbx_hi_WORD word0 697 #define lpfc_bmbx_rdy_SHIFT 0 698 #define lpfc_bmbx_rdy_MASK 0x0001 699 #define lpfc_bmbx_rdy_WORD word0 700 701 #define LPFC_MQ_DOORBELL 0x0140 702 #define lpfc_mq_doorbell_num_posted_SHIFT 16 703 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 704 #define lpfc_mq_doorbell_num_posted_WORD word0 705 #define lpfc_mq_doorbell_id_SHIFT 0 706 #define lpfc_mq_doorbell_id_MASK 0x03FF 707 #define lpfc_mq_doorbell_id_WORD word0 708 709 struct lpfc_sli4_cfg_mhdr { 710 uint32_t word1; 711 #define lpfc_mbox_hdr_emb_SHIFT 0 712 #define lpfc_mbox_hdr_emb_MASK 0x00000001 713 #define lpfc_mbox_hdr_emb_WORD word1 714 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 715 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 716 #define lpfc_mbox_hdr_sge_cnt_WORD word1 717 uint32_t payload_length; 718 uint32_t tag_lo; 719 uint32_t tag_hi; 720 uint32_t reserved5; 721 }; 722 723 union lpfc_sli4_cfg_shdr { 724 struct { 725 uint32_t word6; 726 #define lpfc_mbox_hdr_opcode_SHIFT 0 727 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 728 #define lpfc_mbox_hdr_opcode_WORD word6 729 #define lpfc_mbox_hdr_subsystem_SHIFT 8 730 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 731 #define lpfc_mbox_hdr_subsystem_WORD word6 732 #define lpfc_mbox_hdr_port_number_SHIFT 16 733 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 734 #define lpfc_mbox_hdr_port_number_WORD word6 735 #define lpfc_mbox_hdr_domain_SHIFT 24 736 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 737 #define lpfc_mbox_hdr_domain_WORD word6 738 uint32_t timeout; 739 uint32_t request_length; 740 uint32_t reserved9; 741 } request; 742 struct { 743 uint32_t word6; 744 #define lpfc_mbox_hdr_opcode_SHIFT 0 745 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 746 #define lpfc_mbox_hdr_opcode_WORD word6 747 #define lpfc_mbox_hdr_subsystem_SHIFT 8 748 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 749 #define lpfc_mbox_hdr_subsystem_WORD word6 750 #define lpfc_mbox_hdr_domain_SHIFT 24 751 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 752 #define lpfc_mbox_hdr_domain_WORD word6 753 uint32_t word7; 754 #define lpfc_mbox_hdr_status_SHIFT 0 755 #define lpfc_mbox_hdr_status_MASK 0x000000FF 756 #define lpfc_mbox_hdr_status_WORD word7 757 #define lpfc_mbox_hdr_add_status_SHIFT 8 758 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 759 #define lpfc_mbox_hdr_add_status_WORD word7 760 uint32_t response_length; 761 uint32_t actual_response_length; 762 } response; 763 }; 764 765 /* Mailbox structures */ 766 struct mbox_header { 767 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 768 union lpfc_sli4_cfg_shdr cfg_shdr; 769 }; 770 771 /* Subsystem Definitions */ 772 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 773 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 774 775 /* Device Specific Definitions */ 776 777 /* The HOST ENDIAN defines are in Big Endian format. */ 778 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 779 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 780 781 /* Common Opcodes */ 782 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 783 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 784 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 785 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 786 #define LPFC_MBOX_OPCODE_NOP 0x21 787 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 788 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 789 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 790 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 791 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 792 793 /* FCoE Opcodes */ 794 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 795 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 796 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 797 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 798 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 799 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 800 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 801 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 802 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 803 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 804 805 /* Mailbox command structures */ 806 struct eq_context { 807 uint32_t word0; 808 #define lpfc_eq_context_size_SHIFT 31 809 #define lpfc_eq_context_size_MASK 0x00000001 810 #define lpfc_eq_context_size_WORD word0 811 #define LPFC_EQE_SIZE_4 0x0 812 #define LPFC_EQE_SIZE_16 0x1 813 #define lpfc_eq_context_valid_SHIFT 29 814 #define lpfc_eq_context_valid_MASK 0x00000001 815 #define lpfc_eq_context_valid_WORD word0 816 uint32_t word1; 817 #define lpfc_eq_context_count_SHIFT 26 818 #define lpfc_eq_context_count_MASK 0x00000003 819 #define lpfc_eq_context_count_WORD word1 820 #define LPFC_EQ_CNT_256 0x0 821 #define LPFC_EQ_CNT_512 0x1 822 #define LPFC_EQ_CNT_1024 0x2 823 #define LPFC_EQ_CNT_2048 0x3 824 #define LPFC_EQ_CNT_4096 0x4 825 uint32_t word2; 826 #define lpfc_eq_context_delay_multi_SHIFT 13 827 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 828 #define lpfc_eq_context_delay_multi_WORD word2 829 uint32_t reserved3; 830 }; 831 832 struct sgl_page_pairs { 833 uint32_t sgl_pg0_addr_lo; 834 uint32_t sgl_pg0_addr_hi; 835 uint32_t sgl_pg1_addr_lo; 836 uint32_t sgl_pg1_addr_hi; 837 }; 838 839 struct lpfc_mbx_post_sgl_pages { 840 struct mbox_header header; 841 uint32_t word0; 842 #define lpfc_post_sgl_pages_xri_SHIFT 0 843 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 844 #define lpfc_post_sgl_pages_xri_WORD word0 845 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 846 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 847 #define lpfc_post_sgl_pages_xricnt_WORD word0 848 struct sgl_page_pairs sgl_pg_pairs[1]; 849 }; 850 851 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 852 struct lpfc_mbx_post_uembed_sgl_page1 { 853 union lpfc_sli4_cfg_shdr cfg_shdr; 854 uint32_t word0; 855 struct sgl_page_pairs sgl_pg_pairs; 856 }; 857 858 struct lpfc_mbx_sge { 859 uint32_t pa_lo; 860 uint32_t pa_hi; 861 uint32_t length; 862 }; 863 864 struct lpfc_mbx_nembed_cmd { 865 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 866 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 867 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 868 }; 869 870 struct lpfc_mbx_nembed_sge_virt { 871 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 872 }; 873 874 struct lpfc_mbx_eq_create { 875 struct mbox_header header; 876 union { 877 struct { 878 uint32_t word0; 879 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 880 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 881 #define lpfc_mbx_eq_create_num_pages_WORD word0 882 struct eq_context context; 883 struct dma_address page[LPFC_MAX_EQ_PAGE]; 884 } request; 885 struct { 886 uint32_t word0; 887 #define lpfc_mbx_eq_create_q_id_SHIFT 0 888 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 889 #define lpfc_mbx_eq_create_q_id_WORD word0 890 } response; 891 } u; 892 }; 893 894 struct lpfc_mbx_eq_destroy { 895 struct mbox_header header; 896 union { 897 struct { 898 uint32_t word0; 899 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 900 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 901 #define lpfc_mbx_eq_destroy_q_id_WORD word0 902 } request; 903 struct { 904 uint32_t word0; 905 } response; 906 } u; 907 }; 908 909 struct lpfc_mbx_nop { 910 struct mbox_header header; 911 uint32_t context[2]; 912 }; 913 914 struct cq_context { 915 uint32_t word0; 916 #define lpfc_cq_context_event_SHIFT 31 917 #define lpfc_cq_context_event_MASK 0x00000001 918 #define lpfc_cq_context_event_WORD word0 919 #define lpfc_cq_context_valid_SHIFT 29 920 #define lpfc_cq_context_valid_MASK 0x00000001 921 #define lpfc_cq_context_valid_WORD word0 922 #define lpfc_cq_context_count_SHIFT 27 923 #define lpfc_cq_context_count_MASK 0x00000003 924 #define lpfc_cq_context_count_WORD word0 925 #define LPFC_CQ_CNT_256 0x0 926 #define LPFC_CQ_CNT_512 0x1 927 #define LPFC_CQ_CNT_1024 0x2 928 uint32_t word1; 929 #define lpfc_cq_eq_id_SHIFT 22 930 #define lpfc_cq_eq_id_MASK 0x000000FF 931 #define lpfc_cq_eq_id_WORD word1 932 uint32_t reserved0; 933 uint32_t reserved1; 934 }; 935 936 struct lpfc_mbx_cq_create { 937 struct mbox_header header; 938 union { 939 struct { 940 uint32_t word0; 941 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 942 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 943 #define lpfc_mbx_cq_create_num_pages_WORD word0 944 struct cq_context context; 945 struct dma_address page[LPFC_MAX_CQ_PAGE]; 946 } request; 947 struct { 948 uint32_t word0; 949 #define lpfc_mbx_cq_create_q_id_SHIFT 0 950 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 951 #define lpfc_mbx_cq_create_q_id_WORD word0 952 } response; 953 } u; 954 }; 955 956 struct lpfc_mbx_cq_destroy { 957 struct mbox_header header; 958 union { 959 struct { 960 uint32_t word0; 961 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 962 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 963 #define lpfc_mbx_cq_destroy_q_id_WORD word0 964 } request; 965 struct { 966 uint32_t word0; 967 } response; 968 } u; 969 }; 970 971 struct wq_context { 972 uint32_t reserved0; 973 uint32_t reserved1; 974 uint32_t reserved2; 975 uint32_t reserved3; 976 }; 977 978 struct lpfc_mbx_wq_create { 979 struct mbox_header header; 980 union { 981 struct { 982 uint32_t word0; 983 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 984 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF 985 #define lpfc_mbx_wq_create_num_pages_WORD word0 986 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 987 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 988 #define lpfc_mbx_wq_create_cq_id_WORD word0 989 struct dma_address page[LPFC_MAX_WQ_PAGE]; 990 } request; 991 struct { 992 uint32_t word0; 993 #define lpfc_mbx_wq_create_q_id_SHIFT 0 994 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 995 #define lpfc_mbx_wq_create_q_id_WORD word0 996 } response; 997 } u; 998 }; 999 1000 struct lpfc_mbx_wq_destroy { 1001 struct mbox_header header; 1002 union { 1003 struct { 1004 uint32_t word0; 1005 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1006 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1007 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1008 } request; 1009 struct { 1010 uint32_t word0; 1011 } response; 1012 } u; 1013 }; 1014 1015 #define LPFC_HDR_BUF_SIZE 128 1016 #define LPFC_DATA_BUF_SIZE 2048 1017 struct rq_context { 1018 uint32_t word0; 1019 #define lpfc_rq_context_rq_size_SHIFT 16 1020 #define lpfc_rq_context_rq_size_MASK 0x0000000F 1021 #define lpfc_rq_context_rq_size_WORD word0 1022 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1023 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1024 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1025 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1026 uint32_t reserved1; 1027 uint32_t word2; 1028 #define lpfc_rq_context_cq_id_SHIFT 16 1029 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1030 #define lpfc_rq_context_cq_id_WORD word2 1031 #define lpfc_rq_context_buf_size_SHIFT 0 1032 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1033 #define lpfc_rq_context_buf_size_WORD word2 1034 uint32_t reserved3; 1035 }; 1036 1037 struct lpfc_mbx_rq_create { 1038 struct mbox_header header; 1039 union { 1040 struct { 1041 uint32_t word0; 1042 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1043 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1044 #define lpfc_mbx_rq_create_num_pages_WORD word0 1045 struct rq_context context; 1046 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1047 } request; 1048 struct { 1049 uint32_t word0; 1050 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1051 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1052 #define lpfc_mbx_rq_create_q_id_WORD word0 1053 } response; 1054 } u; 1055 }; 1056 1057 struct lpfc_mbx_rq_destroy { 1058 struct mbox_header header; 1059 union { 1060 struct { 1061 uint32_t word0; 1062 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1063 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1064 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1065 } request; 1066 struct { 1067 uint32_t word0; 1068 } response; 1069 } u; 1070 }; 1071 1072 struct mq_context { 1073 uint32_t word0; 1074 #define lpfc_mq_context_cq_id_SHIFT 22 1075 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1076 #define lpfc_mq_context_cq_id_WORD word0 1077 #define lpfc_mq_context_count_SHIFT 16 1078 #define lpfc_mq_context_count_MASK 0x0000000F 1079 #define lpfc_mq_context_count_WORD word0 1080 #define LPFC_MQ_CNT_16 0x5 1081 #define LPFC_MQ_CNT_32 0x6 1082 #define LPFC_MQ_CNT_64 0x7 1083 #define LPFC_MQ_CNT_128 0x8 1084 uint32_t word1; 1085 #define lpfc_mq_context_valid_SHIFT 31 1086 #define lpfc_mq_context_valid_MASK 0x00000001 1087 #define lpfc_mq_context_valid_WORD word1 1088 uint32_t reserved2; 1089 uint32_t reserved3; 1090 }; 1091 1092 struct lpfc_mbx_mq_create { 1093 struct mbox_header header; 1094 union { 1095 struct { 1096 uint32_t word0; 1097 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1098 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1099 #define lpfc_mbx_mq_create_num_pages_WORD word0 1100 struct mq_context context; 1101 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1102 } request; 1103 struct { 1104 uint32_t word0; 1105 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1106 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1107 #define lpfc_mbx_mq_create_q_id_WORD word0 1108 } response; 1109 } u; 1110 }; 1111 1112 struct lpfc_mbx_mq_destroy { 1113 struct mbox_header header; 1114 union { 1115 struct { 1116 uint32_t word0; 1117 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1118 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1119 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1120 } request; 1121 struct { 1122 uint32_t word0; 1123 } response; 1124 } u; 1125 }; 1126 1127 struct lpfc_mbx_post_hdr_tmpl { 1128 struct mbox_header header; 1129 uint32_t word10; 1130 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1131 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1132 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1133 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1134 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1135 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1136 uint32_t rpi_paddr_lo; 1137 uint32_t rpi_paddr_hi; 1138 }; 1139 1140 struct sli4_sge { /* SLI-4 */ 1141 uint32_t addr_hi; 1142 uint32_t addr_lo; 1143 1144 uint32_t word2; 1145 #define lpfc_sli4_sge_offset_SHIFT 0 /* Offset of buffer - Not used*/ 1146 #define lpfc_sli4_sge_offset_MASK 0x00FFFFFF 1147 #define lpfc_sli4_sge_offset_WORD word2 1148 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets 1149 this flag !! */ 1150 #define lpfc_sli4_sge_last_MASK 0x00000001 1151 #define lpfc_sli4_sge_last_WORD word2 1152 uint32_t word3; 1153 #define lpfc_sli4_sge_len_SHIFT 0 1154 #define lpfc_sli4_sge_len_MASK 0x0001FFFF 1155 #define lpfc_sli4_sge_len_WORD word3 1156 }; 1157 1158 struct fcf_record { 1159 uint32_t max_rcv_size; 1160 uint32_t fka_adv_period; 1161 uint32_t fip_priority; 1162 uint32_t word3; 1163 #define lpfc_fcf_record_mac_0_SHIFT 0 1164 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1165 #define lpfc_fcf_record_mac_0_WORD word3 1166 #define lpfc_fcf_record_mac_1_SHIFT 8 1167 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1168 #define lpfc_fcf_record_mac_1_WORD word3 1169 #define lpfc_fcf_record_mac_2_SHIFT 16 1170 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1171 #define lpfc_fcf_record_mac_2_WORD word3 1172 #define lpfc_fcf_record_mac_3_SHIFT 24 1173 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1174 #define lpfc_fcf_record_mac_3_WORD word3 1175 uint32_t word4; 1176 #define lpfc_fcf_record_mac_4_SHIFT 0 1177 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1178 #define lpfc_fcf_record_mac_4_WORD word4 1179 #define lpfc_fcf_record_mac_5_SHIFT 8 1180 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1181 #define lpfc_fcf_record_mac_5_WORD word4 1182 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1183 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1184 #define lpfc_fcf_record_fcf_avail_WORD word4 1185 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1186 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1187 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1188 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1189 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1190 uint32_t word5; 1191 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1192 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1193 #define lpfc_fcf_record_fab_name_0_WORD word5 1194 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1195 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1196 #define lpfc_fcf_record_fab_name_1_WORD word5 1197 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1198 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1199 #define lpfc_fcf_record_fab_name_2_WORD word5 1200 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1201 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1202 #define lpfc_fcf_record_fab_name_3_WORD word5 1203 uint32_t word6; 1204 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1205 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1206 #define lpfc_fcf_record_fab_name_4_WORD word6 1207 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1208 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1209 #define lpfc_fcf_record_fab_name_5_WORD word6 1210 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1211 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1212 #define lpfc_fcf_record_fab_name_6_WORD word6 1213 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1214 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1215 #define lpfc_fcf_record_fab_name_7_WORD word6 1216 uint32_t word7; 1217 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1218 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1219 #define lpfc_fcf_record_fc_map_0_WORD word7 1220 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1221 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1222 #define lpfc_fcf_record_fc_map_1_WORD word7 1223 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1224 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1225 #define lpfc_fcf_record_fc_map_2_WORD word7 1226 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1227 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF 1228 #define lpfc_fcf_record_fcf_valid_WORD word7 1229 uint32_t word8; 1230 #define lpfc_fcf_record_fcf_index_SHIFT 0 1231 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1232 #define lpfc_fcf_record_fcf_index_WORD word8 1233 #define lpfc_fcf_record_fcf_state_SHIFT 16 1234 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1235 #define lpfc_fcf_record_fcf_state_WORD word8 1236 uint8_t vlan_bitmap[512]; 1237 uint32_t word137; 1238 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1239 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1240 #define lpfc_fcf_record_switch_name_0_WORD word137 1241 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1242 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1243 #define lpfc_fcf_record_switch_name_1_WORD word137 1244 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1245 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1246 #define lpfc_fcf_record_switch_name_2_WORD word137 1247 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1248 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1249 #define lpfc_fcf_record_switch_name_3_WORD word137 1250 uint32_t word138; 1251 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1252 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1253 #define lpfc_fcf_record_switch_name_4_WORD word138 1254 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1255 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1256 #define lpfc_fcf_record_switch_name_5_WORD word138 1257 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1258 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1259 #define lpfc_fcf_record_switch_name_6_WORD word138 1260 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1261 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1262 #define lpfc_fcf_record_switch_name_7_WORD word138 1263 }; 1264 1265 struct lpfc_mbx_read_fcf_tbl { 1266 union lpfc_sli4_cfg_shdr cfg_shdr; 1267 union { 1268 struct { 1269 uint32_t word10; 1270 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1271 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1272 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1273 } request; 1274 struct { 1275 uint32_t eventag; 1276 } response; 1277 } u; 1278 uint32_t word11; 1279 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1280 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1281 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1282 }; 1283 1284 struct lpfc_mbx_add_fcf_tbl_entry { 1285 union lpfc_sli4_cfg_shdr cfg_shdr; 1286 uint32_t word10; 1287 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1288 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1289 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1290 struct lpfc_mbx_sge fcf_sge; 1291 }; 1292 1293 struct lpfc_mbx_del_fcf_tbl_entry { 1294 struct mbox_header header; 1295 uint32_t word10; 1296 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1297 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1298 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1299 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1300 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1301 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1302 }; 1303 1304 struct lpfc_mbx_query_fw_cfg { 1305 struct mbox_header header; 1306 uint32_t config_number; 1307 uint32_t asic_rev; 1308 uint32_t phys_port; 1309 uint32_t function_mode; 1310 /* firmware Function Mode */ 1311 #define lpfc_function_mode_toe_SHIFT 0 1312 #define lpfc_function_mode_toe_MASK 0x00000001 1313 #define lpfc_function_mode_toe_WORD function_mode 1314 #define lpfc_function_mode_nic_SHIFT 1 1315 #define lpfc_function_mode_nic_MASK 0x00000001 1316 #define lpfc_function_mode_nic_WORD function_mode 1317 #define lpfc_function_mode_rdma_SHIFT 2 1318 #define lpfc_function_mode_rdma_MASK 0x00000001 1319 #define lpfc_function_mode_rdma_WORD function_mode 1320 #define lpfc_function_mode_vm_SHIFT 3 1321 #define lpfc_function_mode_vm_MASK 0x00000001 1322 #define lpfc_function_mode_vm_WORD function_mode 1323 #define lpfc_function_mode_iscsi_i_SHIFT 4 1324 #define lpfc_function_mode_iscsi_i_MASK 0x00000001 1325 #define lpfc_function_mode_iscsi_i_WORD function_mode 1326 #define lpfc_function_mode_iscsi_t_SHIFT 5 1327 #define lpfc_function_mode_iscsi_t_MASK 0x00000001 1328 #define lpfc_function_mode_iscsi_t_WORD function_mode 1329 #define lpfc_function_mode_fcoe_i_SHIFT 6 1330 #define lpfc_function_mode_fcoe_i_MASK 0x00000001 1331 #define lpfc_function_mode_fcoe_i_WORD function_mode 1332 #define lpfc_function_mode_fcoe_t_SHIFT 7 1333 #define lpfc_function_mode_fcoe_t_MASK 0x00000001 1334 #define lpfc_function_mode_fcoe_t_WORD function_mode 1335 #define lpfc_function_mode_dal_SHIFT 8 1336 #define lpfc_function_mode_dal_MASK 0x00000001 1337 #define lpfc_function_mode_dal_WORD function_mode 1338 #define lpfc_function_mode_lro_SHIFT 9 1339 #define lpfc_function_mode_lro_MASK 0x00000001 1340 #define lpfc_function_mode_lro_WORD function_mode9 1341 #define lpfc_function_mode_flex10_SHIFT 10 1342 #define lpfc_function_mode_flex10_MASK 0x00000001 1343 #define lpfc_function_mode_flex10_WORD function_mode 1344 #define lpfc_function_mode_ncsi_SHIFT 11 1345 #define lpfc_function_mode_ncsi_MASK 0x00000001 1346 #define lpfc_function_mode_ncsi_WORD function_mode 1347 }; 1348 1349 /* Status field for embedded SLI_CONFIG mailbox command */ 1350 #define STATUS_SUCCESS 0x0 1351 #define STATUS_FAILED 0x1 1352 #define STATUS_ILLEGAL_REQUEST 0x2 1353 #define STATUS_ILLEGAL_FIELD 0x3 1354 #define STATUS_INSUFFICIENT_BUFFER 0x4 1355 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1356 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1357 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1358 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1359 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1360 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1361 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1362 #define STATUS_ASSERT_FAILED 0x1e 1363 #define STATUS_INVALID_SESSION 0x1f 1364 #define STATUS_INVALID_CONNECTION 0x20 1365 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1366 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1367 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1368 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1369 #define STATUS_FLASHROM_READ_FAILED 0x27 1370 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1371 #define STATUS_ERROR_ACITMAIN 0x2a 1372 #define STATUS_REBOOT_REQUIRED 0x2c 1373 #define STATUS_FCF_IN_USE 0x3a 1374 #define STATUS_FCF_TABLE_EMPTY 0x43 1375 1376 struct lpfc_mbx_sli4_config { 1377 struct mbox_header header; 1378 }; 1379 1380 struct lpfc_mbx_init_vfi { 1381 uint32_t word1; 1382 #define lpfc_init_vfi_vr_SHIFT 31 1383 #define lpfc_init_vfi_vr_MASK 0x00000001 1384 #define lpfc_init_vfi_vr_WORD word1 1385 #define lpfc_init_vfi_vt_SHIFT 30 1386 #define lpfc_init_vfi_vt_MASK 0x00000001 1387 #define lpfc_init_vfi_vt_WORD word1 1388 #define lpfc_init_vfi_vf_SHIFT 29 1389 #define lpfc_init_vfi_vf_MASK 0x00000001 1390 #define lpfc_init_vfi_vf_WORD word1 1391 #define lpfc_init_vfi_vfi_SHIFT 0 1392 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1393 #define lpfc_init_vfi_vfi_WORD word1 1394 uint32_t word2; 1395 #define lpfc_init_vfi_fcfi_SHIFT 0 1396 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1397 #define lpfc_init_vfi_fcfi_WORD word2 1398 uint32_t word3; 1399 #define lpfc_init_vfi_pri_SHIFT 13 1400 #define lpfc_init_vfi_pri_MASK 0x00000007 1401 #define lpfc_init_vfi_pri_WORD word3 1402 #define lpfc_init_vfi_vf_id_SHIFT 1 1403 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1404 #define lpfc_init_vfi_vf_id_WORD word3 1405 uint32_t word4; 1406 #define lpfc_init_vfi_hop_count_SHIFT 24 1407 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1408 #define lpfc_init_vfi_hop_count_WORD word4 1409 }; 1410 1411 struct lpfc_mbx_reg_vfi { 1412 uint32_t word1; 1413 #define lpfc_reg_vfi_vp_SHIFT 28 1414 #define lpfc_reg_vfi_vp_MASK 0x00000001 1415 #define lpfc_reg_vfi_vp_WORD word1 1416 #define lpfc_reg_vfi_vfi_SHIFT 0 1417 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1418 #define lpfc_reg_vfi_vfi_WORD word1 1419 uint32_t word2; 1420 #define lpfc_reg_vfi_vpi_SHIFT 16 1421 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1422 #define lpfc_reg_vfi_vpi_WORD word2 1423 #define lpfc_reg_vfi_fcfi_SHIFT 0 1424 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1425 #define lpfc_reg_vfi_fcfi_WORD word2 1426 uint32_t wwn[2]; 1427 struct ulp_bde64 bde; 1428 uint32_t word8_rsvd; 1429 uint32_t word9_rsvd; 1430 uint32_t word10; 1431 #define lpfc_reg_vfi_nport_id_SHIFT 0 1432 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1433 #define lpfc_reg_vfi_nport_id_WORD word10 1434 }; 1435 1436 struct lpfc_mbx_init_vpi { 1437 uint32_t word1; 1438 #define lpfc_init_vpi_vfi_SHIFT 16 1439 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1440 #define lpfc_init_vpi_vfi_WORD word1 1441 #define lpfc_init_vpi_vpi_SHIFT 0 1442 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1443 #define lpfc_init_vpi_vpi_WORD word1 1444 }; 1445 1446 struct lpfc_mbx_read_vpi { 1447 uint32_t word1_rsvd; 1448 uint32_t word2; 1449 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 1450 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 1451 #define lpfc_mbx_read_vpi_vnportid_WORD word2 1452 uint32_t word3_rsvd; 1453 uint32_t word4; 1454 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 1455 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 1456 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 1457 #define lpfc_mbx_read_vpi_pb_SHIFT 15 1458 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 1459 #define lpfc_mbx_read_vpi_pb_WORD word4 1460 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 1461 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 1462 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 1463 #define lpfc_mbx_read_vpi_ns_SHIFT 30 1464 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 1465 #define lpfc_mbx_read_vpi_ns_WORD word4 1466 #define lpfc_mbx_read_vpi_hl_SHIFT 31 1467 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 1468 #define lpfc_mbx_read_vpi_hl_WORD word4 1469 uint32_t word5_rsvd; 1470 uint32_t word6; 1471 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 1472 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 1473 #define lpfc_mbx_read_vpi_vpi_WORD word6 1474 uint32_t word7; 1475 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 1476 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 1477 #define lpfc_mbx_read_vpi_mac_0_WORD word7 1478 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 1479 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 1480 #define lpfc_mbx_read_vpi_mac_1_WORD word7 1481 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 1482 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 1483 #define lpfc_mbx_read_vpi_mac_2_WORD word7 1484 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 1485 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 1486 #define lpfc_mbx_read_vpi_mac_3_WORD word7 1487 uint32_t word8; 1488 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 1489 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 1490 #define lpfc_mbx_read_vpi_mac_4_WORD word8 1491 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 1492 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 1493 #define lpfc_mbx_read_vpi_mac_5_WORD word8 1494 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 1495 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 1496 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 1497 #define lpfc_mbx_read_vpi_vv_SHIFT 28 1498 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 1499 #define lpfc_mbx_read_vpi_vv_WORD word8 1500 }; 1501 1502 struct lpfc_mbx_unreg_vfi { 1503 uint32_t word1_rsvd; 1504 uint32_t word2; 1505 #define lpfc_unreg_vfi_vfi_SHIFT 0 1506 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 1507 #define lpfc_unreg_vfi_vfi_WORD word2 1508 }; 1509 1510 struct lpfc_mbx_resume_rpi { 1511 uint32_t word1; 1512 #define lpfc_resume_rpi_index_SHIFT 0 1513 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 1514 #define lpfc_resume_rpi_index_WORD word1 1515 #define lpfc_resume_rpi_ii_SHIFT 30 1516 #define lpfc_resume_rpi_ii_MASK 0x00000003 1517 #define lpfc_resume_rpi_ii_WORD word1 1518 #define RESUME_INDEX_RPI 0 1519 #define RESUME_INDEX_VPI 1 1520 #define RESUME_INDEX_VFI 2 1521 #define RESUME_INDEX_FCFI 3 1522 uint32_t event_tag; 1523 }; 1524 1525 #define REG_FCF_INVALID_QID 0xFFFF 1526 struct lpfc_mbx_reg_fcfi { 1527 uint32_t word1; 1528 #define lpfc_reg_fcfi_info_index_SHIFT 0 1529 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 1530 #define lpfc_reg_fcfi_info_index_WORD word1 1531 #define lpfc_reg_fcfi_fcfi_SHIFT 16 1532 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 1533 #define lpfc_reg_fcfi_fcfi_WORD word1 1534 uint32_t word2; 1535 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 1536 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 1537 #define lpfc_reg_fcfi_rq_id1_WORD word2 1538 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 1539 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 1540 #define lpfc_reg_fcfi_rq_id0_WORD word2 1541 uint32_t word3; 1542 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 1543 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 1544 #define lpfc_reg_fcfi_rq_id3_WORD word3 1545 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 1546 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 1547 #define lpfc_reg_fcfi_rq_id2_WORD word3 1548 uint32_t word4; 1549 #define lpfc_reg_fcfi_type_match0_SHIFT 24 1550 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 1551 #define lpfc_reg_fcfi_type_match0_WORD word4 1552 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 1553 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 1554 #define lpfc_reg_fcfi_type_mask0_WORD word4 1555 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 1556 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 1557 #define lpfc_reg_fcfi_rctl_match0_WORD word4 1558 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 1559 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 1560 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 1561 uint32_t word5; 1562 #define lpfc_reg_fcfi_type_match1_SHIFT 24 1563 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 1564 #define lpfc_reg_fcfi_type_match1_WORD word5 1565 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 1566 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 1567 #define lpfc_reg_fcfi_type_mask1_WORD word5 1568 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 1569 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 1570 #define lpfc_reg_fcfi_rctl_match1_WORD word5 1571 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 1572 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 1573 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 1574 uint32_t word6; 1575 #define lpfc_reg_fcfi_type_match2_SHIFT 24 1576 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 1577 #define lpfc_reg_fcfi_type_match2_WORD word6 1578 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 1579 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 1580 #define lpfc_reg_fcfi_type_mask2_WORD word6 1581 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 1582 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 1583 #define lpfc_reg_fcfi_rctl_match2_WORD word6 1584 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 1585 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 1586 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 1587 uint32_t word7; 1588 #define lpfc_reg_fcfi_type_match3_SHIFT 24 1589 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 1590 #define lpfc_reg_fcfi_type_match3_WORD word7 1591 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 1592 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 1593 #define lpfc_reg_fcfi_type_mask3_WORD word7 1594 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 1595 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 1596 #define lpfc_reg_fcfi_rctl_match3_WORD word7 1597 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 1598 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 1599 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 1600 uint32_t word8; 1601 #define lpfc_reg_fcfi_mam_SHIFT 13 1602 #define lpfc_reg_fcfi_mam_MASK 0x00000003 1603 #define lpfc_reg_fcfi_mam_WORD word8 1604 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 1605 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 1606 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 1607 #define lpfc_reg_fcfi_vv_SHIFT 12 1608 #define lpfc_reg_fcfi_vv_MASK 0x00000001 1609 #define lpfc_reg_fcfi_vv_WORD word8 1610 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 1611 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 1612 #define lpfc_reg_fcfi_vlan_tag_WORD word8 1613 }; 1614 1615 struct lpfc_mbx_unreg_fcfi { 1616 uint32_t word1_rsv; 1617 uint32_t word2; 1618 #define lpfc_unreg_fcfi_SHIFT 0 1619 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 1620 #define lpfc_unreg_fcfi_WORD word2 1621 }; 1622 1623 struct lpfc_mbx_read_rev { 1624 uint32_t word1; 1625 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 1626 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 1627 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 1628 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 1629 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 1630 #define lpfc_mbx_rd_rev_fcoe_WORD word1 1631 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 1632 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 1633 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 1634 #define LPFC_PREDCBX_CEE_MODE 0 1635 #define LPFC_DCBX_CEE_MODE 1 1636 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 1637 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 1638 #define lpfc_mbx_rd_rev_vpd_WORD word1 1639 uint32_t first_hw_rev; 1640 uint32_t second_hw_rev; 1641 uint32_t word4_rsvd; 1642 uint32_t third_hw_rev; 1643 uint32_t word6; 1644 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 1645 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 1646 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 1647 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 1648 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 1649 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 1650 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 1651 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 1652 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 1653 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 1654 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 1655 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 1656 uint32_t word7_rsvd; 1657 uint32_t fw_id_rev; 1658 uint8_t fw_name[16]; 1659 uint32_t ulp_fw_id_rev; 1660 uint8_t ulp_fw_name[16]; 1661 uint32_t word18_47_rsvd[30]; 1662 uint32_t word48; 1663 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 1664 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 1665 #define lpfc_mbx_rd_rev_avail_len_WORD word48 1666 uint32_t vpd_paddr_low; 1667 uint32_t vpd_paddr_high; 1668 uint32_t avail_vpd_len; 1669 uint32_t rsvd_52_63[12]; 1670 }; 1671 1672 struct lpfc_mbx_read_config { 1673 uint32_t word1; 1674 #define lpfc_mbx_rd_conf_max_bbc_SHIFT 0 1675 #define lpfc_mbx_rd_conf_max_bbc_MASK 0x000000FF 1676 #define lpfc_mbx_rd_conf_max_bbc_WORD word1 1677 #define lpfc_mbx_rd_conf_init_bbc_SHIFT 8 1678 #define lpfc_mbx_rd_conf_init_bbc_MASK 0x000000FF 1679 #define lpfc_mbx_rd_conf_init_bbc_WORD word1 1680 uint32_t word2; 1681 #define lpfc_mbx_rd_conf_nport_did_SHIFT 0 1682 #define lpfc_mbx_rd_conf_nport_did_MASK 0x00FFFFFF 1683 #define lpfc_mbx_rd_conf_nport_did_WORD word2 1684 #define lpfc_mbx_rd_conf_topology_SHIFT 24 1685 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 1686 #define lpfc_mbx_rd_conf_topology_WORD word2 1687 uint32_t word3; 1688 #define lpfc_mbx_rd_conf_ao_SHIFT 0 1689 #define lpfc_mbx_rd_conf_ao_MASK 0x00000001 1690 #define lpfc_mbx_rd_conf_ao_WORD word3 1691 #define lpfc_mbx_rd_conf_bb_scn_SHIFT 8 1692 #define lpfc_mbx_rd_conf_bb_scn_MASK 0x0000000F 1693 #define lpfc_mbx_rd_conf_bb_scn_WORD word3 1694 #define lpfc_mbx_rd_conf_cbb_scn_SHIFT 12 1695 #define lpfc_mbx_rd_conf_cbb_scn_MASK 0x0000000F 1696 #define lpfc_mbx_rd_conf_cbb_scn_WORD word3 1697 #define lpfc_mbx_rd_conf_mc_SHIFT 29 1698 #define lpfc_mbx_rd_conf_mc_MASK 0x00000001 1699 #define lpfc_mbx_rd_conf_mc_WORD word3 1700 uint32_t word4; 1701 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 1702 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 1703 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 1704 uint32_t word5; 1705 #define lpfc_mbx_rd_conf_lp_tov_SHIFT 0 1706 #define lpfc_mbx_rd_conf_lp_tov_MASK 0x0000FFFF 1707 #define lpfc_mbx_rd_conf_lp_tov_WORD word5 1708 uint32_t word6; 1709 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 1710 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 1711 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 1712 uint32_t word7; 1713 #define lpfc_mbx_rd_conf_r_t_tov_SHIFT 0 1714 #define lpfc_mbx_rd_conf_r_t_tov_MASK 0x000000FF 1715 #define lpfc_mbx_rd_conf_r_t_tov_WORD word7 1716 uint32_t word8; 1717 #define lpfc_mbx_rd_conf_al_tov_SHIFT 0 1718 #define lpfc_mbx_rd_conf_al_tov_MASK 0x0000000F 1719 #define lpfc_mbx_rd_conf_al_tov_WORD word8 1720 uint32_t word9; 1721 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 1722 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 1723 #define lpfc_mbx_rd_conf_lmt_WORD word9 1724 uint32_t word10; 1725 #define lpfc_mbx_rd_conf_max_alpa_SHIFT 0 1726 #define lpfc_mbx_rd_conf_max_alpa_MASK 0x000000FF 1727 #define lpfc_mbx_rd_conf_max_alpa_WORD word10 1728 uint32_t word11_rsvd; 1729 uint32_t word12; 1730 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 1731 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 1732 #define lpfc_mbx_rd_conf_xri_base_WORD word12 1733 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 1734 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 1735 #define lpfc_mbx_rd_conf_xri_count_WORD word12 1736 uint32_t word13; 1737 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 1738 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 1739 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 1740 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 1741 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 1742 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 1743 uint32_t word14; 1744 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 1745 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 1746 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 1747 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 1748 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 1749 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 1750 uint32_t word15; 1751 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 1752 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 1753 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 1754 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 1755 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 1756 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 1757 uint32_t word16; 1758 #define lpfc_mbx_rd_conf_fcfi_base_SHIFT 0 1759 #define lpfc_mbx_rd_conf_fcfi_base_MASK 0x0000FFFF 1760 #define lpfc_mbx_rd_conf_fcfi_base_WORD word16 1761 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 1762 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 1763 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 1764 uint32_t word17; 1765 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 1766 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 1767 #define lpfc_mbx_rd_conf_rq_count_WORD word17 1768 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 1769 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 1770 #define lpfc_mbx_rd_conf_eq_count_WORD word17 1771 uint32_t word18; 1772 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 1773 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 1774 #define lpfc_mbx_rd_conf_wq_count_WORD word18 1775 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 1776 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 1777 #define lpfc_mbx_rd_conf_cq_count_WORD word18 1778 }; 1779 1780 struct lpfc_mbx_request_features { 1781 uint32_t word1; 1782 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 1783 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 1784 #define lpfc_mbx_rq_ftr_qry_WORD word1 1785 uint32_t word2; 1786 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 1787 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 1788 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 1789 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 1790 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 1791 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 1792 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 1793 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 1794 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 1795 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 1796 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 1797 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 1798 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 1799 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 1800 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 1801 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 1802 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 1803 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 1804 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 1805 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 1806 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 1807 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 1808 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 1809 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 1810 uint32_t word3; 1811 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 1812 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 1813 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 1814 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 1815 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 1816 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 1817 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 1818 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 1819 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 1820 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 1821 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 1822 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 1823 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 1824 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 1825 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 1826 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 1827 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 1828 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 1829 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 1830 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 1831 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 1832 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 1833 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 1834 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 1835 }; 1836 1837 /* Mailbox Completion Queue Error Messages */ 1838 #define MB_CQE_STATUS_SUCCESS 0x0 1839 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 1840 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 1841 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 1842 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 1843 #define MB_CQE_STATUS_DMA_FAILED 0x5 1844 1845 /* mailbox queue entry structure */ 1846 struct lpfc_mqe { 1847 uint32_t word0; 1848 #define lpfc_mqe_status_SHIFT 16 1849 #define lpfc_mqe_status_MASK 0x0000FFFF 1850 #define lpfc_mqe_status_WORD word0 1851 #define lpfc_mqe_command_SHIFT 8 1852 #define lpfc_mqe_command_MASK 0x000000FF 1853 #define lpfc_mqe_command_WORD word0 1854 union { 1855 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 1856 /* sli4 mailbox commands */ 1857 struct lpfc_mbx_sli4_config sli4_config; 1858 struct lpfc_mbx_init_vfi init_vfi; 1859 struct lpfc_mbx_reg_vfi reg_vfi; 1860 struct lpfc_mbx_reg_vfi unreg_vfi; 1861 struct lpfc_mbx_init_vpi init_vpi; 1862 struct lpfc_mbx_resume_rpi resume_rpi; 1863 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 1864 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 1865 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 1866 struct lpfc_mbx_reg_fcfi reg_fcfi; 1867 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 1868 struct lpfc_mbx_mq_create mq_create; 1869 struct lpfc_mbx_eq_create eq_create; 1870 struct lpfc_mbx_cq_create cq_create; 1871 struct lpfc_mbx_wq_create wq_create; 1872 struct lpfc_mbx_rq_create rq_create; 1873 struct lpfc_mbx_mq_destroy mq_destroy; 1874 struct lpfc_mbx_eq_destroy eq_destroy; 1875 struct lpfc_mbx_cq_destroy cq_destroy; 1876 struct lpfc_mbx_wq_destroy wq_destroy; 1877 struct lpfc_mbx_rq_destroy rq_destroy; 1878 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 1879 struct lpfc_mbx_nembed_cmd nembed_cmd; 1880 struct lpfc_mbx_read_rev read_rev; 1881 struct lpfc_mbx_read_vpi read_vpi; 1882 struct lpfc_mbx_read_config rd_config; 1883 struct lpfc_mbx_request_features req_ftrs; 1884 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 1885 struct lpfc_mbx_query_fw_cfg query_fw_cfg; 1886 struct lpfc_mbx_nop nop; 1887 } un; 1888 }; 1889 1890 struct lpfc_mcqe { 1891 uint32_t word0; 1892 #define lpfc_mcqe_status_SHIFT 0 1893 #define lpfc_mcqe_status_MASK 0x0000FFFF 1894 #define lpfc_mcqe_status_WORD word0 1895 #define lpfc_mcqe_ext_status_SHIFT 16 1896 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 1897 #define lpfc_mcqe_ext_status_WORD word0 1898 uint32_t mcqe_tag0; 1899 uint32_t mcqe_tag1; 1900 uint32_t trailer; 1901 #define lpfc_trailer_valid_SHIFT 31 1902 #define lpfc_trailer_valid_MASK 0x00000001 1903 #define lpfc_trailer_valid_WORD trailer 1904 #define lpfc_trailer_async_SHIFT 30 1905 #define lpfc_trailer_async_MASK 0x00000001 1906 #define lpfc_trailer_async_WORD trailer 1907 #define lpfc_trailer_hpi_SHIFT 29 1908 #define lpfc_trailer_hpi_MASK 0x00000001 1909 #define lpfc_trailer_hpi_WORD trailer 1910 #define lpfc_trailer_completed_SHIFT 28 1911 #define lpfc_trailer_completed_MASK 0x00000001 1912 #define lpfc_trailer_completed_WORD trailer 1913 #define lpfc_trailer_consumed_SHIFT 27 1914 #define lpfc_trailer_consumed_MASK 0x00000001 1915 #define lpfc_trailer_consumed_WORD trailer 1916 #define lpfc_trailer_type_SHIFT 16 1917 #define lpfc_trailer_type_MASK 0x000000FF 1918 #define lpfc_trailer_type_WORD trailer 1919 #define lpfc_trailer_code_SHIFT 8 1920 #define lpfc_trailer_code_MASK 0x000000FF 1921 #define lpfc_trailer_code_WORD trailer 1922 #define LPFC_TRAILER_CODE_LINK 0x1 1923 #define LPFC_TRAILER_CODE_FCOE 0x2 1924 #define LPFC_TRAILER_CODE_DCBX 0x3 1925 }; 1926 1927 struct lpfc_acqe_link { 1928 uint32_t word0; 1929 #define lpfc_acqe_link_speed_SHIFT 24 1930 #define lpfc_acqe_link_speed_MASK 0x000000FF 1931 #define lpfc_acqe_link_speed_WORD word0 1932 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 1933 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 1934 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 1935 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 1936 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 1937 #define lpfc_acqe_link_duplex_SHIFT 16 1938 #define lpfc_acqe_link_duplex_MASK 0x000000FF 1939 #define lpfc_acqe_link_duplex_WORD word0 1940 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 1941 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 1942 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 1943 #define lpfc_acqe_link_status_SHIFT 8 1944 #define lpfc_acqe_link_status_MASK 0x000000FF 1945 #define lpfc_acqe_link_status_WORD word0 1946 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 1947 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 1948 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 1949 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 1950 #define lpfc_acqe_link_physical_SHIFT 0 1951 #define lpfc_acqe_link_physical_MASK 0x000000FF 1952 #define lpfc_acqe_link_physical_WORD word0 1953 #define LPFC_ASYNC_LINK_PORT_A 0x0 1954 #define LPFC_ASYNC_LINK_PORT_B 0x1 1955 uint32_t word1; 1956 #define lpfc_acqe_link_fault_SHIFT 0 1957 #define lpfc_acqe_link_fault_MASK 0x000000FF 1958 #define lpfc_acqe_link_fault_WORD word1 1959 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 1960 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 1961 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 1962 uint32_t event_tag; 1963 uint32_t trailer; 1964 }; 1965 1966 struct lpfc_acqe_fcoe { 1967 uint32_t index; 1968 uint32_t word1; 1969 #define lpfc_acqe_fcoe_fcf_count_SHIFT 0 1970 #define lpfc_acqe_fcoe_fcf_count_MASK 0x0000FFFF 1971 #define lpfc_acqe_fcoe_fcf_count_WORD word1 1972 #define lpfc_acqe_fcoe_event_type_SHIFT 16 1973 #define lpfc_acqe_fcoe_event_type_MASK 0x0000FFFF 1974 #define lpfc_acqe_fcoe_event_type_WORD word1 1975 #define LPFC_FCOE_EVENT_TYPE_NEW_FCF 0x1 1976 #define LPFC_FCOE_EVENT_TYPE_FCF_TABLE_FULL 0x2 1977 #define LPFC_FCOE_EVENT_TYPE_FCF_DEAD 0x3 1978 #define LPFC_FCOE_EVENT_TYPE_CVL 0x4 1979 uint32_t event_tag; 1980 uint32_t trailer; 1981 }; 1982 1983 struct lpfc_acqe_dcbx { 1984 uint32_t tlv_ttl; 1985 uint32_t reserved; 1986 uint32_t event_tag; 1987 uint32_t trailer; 1988 }; 1989 1990 /* 1991 * Define the bootstrap mailbox (bmbx) region used to communicate 1992 * mailbox command between the host and port. The mailbox consists 1993 * of a payload area of 256 bytes and a completion queue of length 1994 * 16 bytes. 1995 */ 1996 struct lpfc_bmbx_create { 1997 struct lpfc_mqe mqe; 1998 struct lpfc_mcqe mcqe; 1999 }; 2000 2001 #define SGL_ALIGN_SZ 64 2002 #define SGL_PAGE_SIZE 4096 2003 /* align SGL addr on a size boundary - adjust address up */ 2004 #define NO_XRI ((uint16_t)-1) 2005 2006 struct wqe_common { 2007 uint32_t word6; 2008 #define wqe_xri_tag_SHIFT 0 2009 #define wqe_xri_tag_MASK 0x0000FFFF 2010 #define wqe_xri_tag_WORD word6 2011 #define wqe_ctxt_tag_SHIFT 16 2012 #define wqe_ctxt_tag_MASK 0x0000FFFF 2013 #define wqe_ctxt_tag_WORD word6 2014 uint32_t word7; 2015 #define wqe_ct_SHIFT 2 2016 #define wqe_ct_MASK 0x00000003 2017 #define wqe_ct_WORD word7 2018 #define wqe_status_SHIFT 4 2019 #define wqe_status_MASK 0x0000000f 2020 #define wqe_status_WORD word7 2021 #define wqe_cmnd_SHIFT 8 2022 #define wqe_cmnd_MASK 0x000000ff 2023 #define wqe_cmnd_WORD word7 2024 #define wqe_class_SHIFT 16 2025 #define wqe_class_MASK 0x00000007 2026 #define wqe_class_WORD word7 2027 #define wqe_pu_SHIFT 20 2028 #define wqe_pu_MASK 0x00000003 2029 #define wqe_pu_WORD word7 2030 #define wqe_erp_SHIFT 22 2031 #define wqe_erp_MASK 0x00000001 2032 #define wqe_erp_WORD word7 2033 #define wqe_lnk_SHIFT 23 2034 #define wqe_lnk_MASK 0x00000001 2035 #define wqe_lnk_WORD word7 2036 #define wqe_tmo_SHIFT 24 2037 #define wqe_tmo_MASK 0x000000ff 2038 #define wqe_tmo_WORD word7 2039 uint32_t abort_tag; /* word 8 in WQE */ 2040 uint32_t word9; 2041 #define wqe_reqtag_SHIFT 0 2042 #define wqe_reqtag_MASK 0x0000FFFF 2043 #define wqe_reqtag_WORD word9 2044 #define wqe_rcvoxid_SHIFT 16 2045 #define wqe_rcvoxid_MASK 0x0000FFFF 2046 #define wqe_rcvoxid_WORD word9 2047 uint32_t word10; 2048 #define wqe_pri_SHIFT 16 2049 #define wqe_pri_MASK 0x00000007 2050 #define wqe_pri_WORD word10 2051 #define wqe_pv_SHIFT 19 2052 #define wqe_pv_MASK 0x00000001 2053 #define wqe_pv_WORD word10 2054 #define wqe_xc_SHIFT 21 2055 #define wqe_xc_MASK 0x00000001 2056 #define wqe_xc_WORD word10 2057 #define wqe_ccpe_SHIFT 23 2058 #define wqe_ccpe_MASK 0x00000001 2059 #define wqe_ccpe_WORD word10 2060 #define wqe_ccp_SHIFT 24 2061 #define wqe_ccp_MASK 0x000000ff 2062 #define wqe_ccp_WORD word10 2063 uint32_t word11; 2064 #define wqe_cmd_type_SHIFT 0 2065 #define wqe_cmd_type_MASK 0x0000000f 2066 #define wqe_cmd_type_WORD word11 2067 #define wqe_wqec_SHIFT 7 2068 #define wqe_wqec_MASK 0x00000001 2069 #define wqe_wqec_WORD word11 2070 #define wqe_cqid_SHIFT 16 2071 #define wqe_cqid_MASK 0x0000ffff 2072 #define wqe_cqid_WORD word11 2073 }; 2074 2075 struct wqe_did { 2076 uint32_t word5; 2077 #define wqe_els_did_SHIFT 0 2078 #define wqe_els_did_MASK 0x00FFFFFF 2079 #define wqe_els_did_WORD word5 2080 #define wqe_xmit_bls_pt_SHIFT 28 2081 #define wqe_xmit_bls_pt_MASK 0x00000003 2082 #define wqe_xmit_bls_pt_WORD word5 2083 #define wqe_xmit_bls_ar_SHIFT 30 2084 #define wqe_xmit_bls_ar_MASK 0x00000001 2085 #define wqe_xmit_bls_ar_WORD word5 2086 #define wqe_xmit_bls_xo_SHIFT 31 2087 #define wqe_xmit_bls_xo_MASK 0x00000001 2088 #define wqe_xmit_bls_xo_WORD word5 2089 }; 2090 2091 struct els_request64_wqe { 2092 struct ulp_bde64 bde; 2093 uint32_t payload_len; 2094 uint32_t word4; 2095 #define els_req64_sid_SHIFT 0 2096 #define els_req64_sid_MASK 0x00FFFFFF 2097 #define els_req64_sid_WORD word4 2098 #define els_req64_sp_SHIFT 24 2099 #define els_req64_sp_MASK 0x00000001 2100 #define els_req64_sp_WORD word4 2101 #define els_req64_vf_SHIFT 25 2102 #define els_req64_vf_MASK 0x00000001 2103 #define els_req64_vf_WORD word4 2104 struct wqe_did wqe_dest; 2105 struct wqe_common wqe_com; /* words 6-11 */ 2106 uint32_t word12; 2107 #define els_req64_vfid_SHIFT 1 2108 #define els_req64_vfid_MASK 0x00000FFF 2109 #define els_req64_vfid_WORD word12 2110 #define els_req64_pri_SHIFT 13 2111 #define els_req64_pri_MASK 0x00000007 2112 #define els_req64_pri_WORD word12 2113 uint32_t word13; 2114 #define els_req64_hopcnt_SHIFT 24 2115 #define els_req64_hopcnt_MASK 0x000000ff 2116 #define els_req64_hopcnt_WORD word13 2117 uint32_t reserved[2]; 2118 }; 2119 2120 struct xmit_els_rsp64_wqe { 2121 struct ulp_bde64 bde; 2122 uint32_t rsvd3; 2123 uint32_t rsvd4; 2124 struct wqe_did wqe_dest; 2125 struct wqe_common wqe_com; /* words 6-11 */ 2126 uint32_t rsvd_12_15[4]; 2127 }; 2128 2129 struct xmit_bls_rsp64_wqe { 2130 uint32_t payload0; 2131 /* Payload0 for BA_ACC */ 2132 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 2133 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 2134 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 2135 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 2136 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 2137 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 2138 /* Payload0 for BA_RJT */ 2139 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 2140 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 2141 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 2142 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 2143 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 2144 #define xmit_bls_rsp64_rjt_expc_WORD payload0 2145 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 2146 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 2147 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 2148 uint32_t word1; 2149 #define xmit_bls_rsp64_rxid_SHIFT 0 2150 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 2151 #define xmit_bls_rsp64_rxid_WORD word1 2152 #define xmit_bls_rsp64_oxid_SHIFT 16 2153 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 2154 #define xmit_bls_rsp64_oxid_WORD word1 2155 uint32_t word2; 2156 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 2157 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 2158 #define xmit_bls_rsp64_seqcnthi_WORD word2 2159 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 2160 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 2161 #define xmit_bls_rsp64_seqcntlo_WORD word2 2162 uint32_t rsrvd3; 2163 uint32_t rsrvd4; 2164 struct wqe_did wqe_dest; 2165 struct wqe_common wqe_com; /* words 6-11 */ 2166 uint32_t rsvd_12_15[4]; 2167 }; 2168 2169 struct wqe_rctl_dfctl { 2170 uint32_t word5; 2171 #define wqe_si_SHIFT 2 2172 #define wqe_si_MASK 0x000000001 2173 #define wqe_si_WORD word5 2174 #define wqe_la_SHIFT 3 2175 #define wqe_la_MASK 0x000000001 2176 #define wqe_la_WORD word5 2177 #define wqe_ls_SHIFT 7 2178 #define wqe_ls_MASK 0x000000001 2179 #define wqe_ls_WORD word5 2180 #define wqe_dfctl_SHIFT 8 2181 #define wqe_dfctl_MASK 0x0000000ff 2182 #define wqe_dfctl_WORD word5 2183 #define wqe_type_SHIFT 16 2184 #define wqe_type_MASK 0x0000000ff 2185 #define wqe_type_WORD word5 2186 #define wqe_rctl_SHIFT 24 2187 #define wqe_rctl_MASK 0x0000000ff 2188 #define wqe_rctl_WORD word5 2189 }; 2190 2191 struct xmit_seq64_wqe { 2192 struct ulp_bde64 bde; 2193 uint32_t paylaod_offset; 2194 uint32_t relative_offset; 2195 struct wqe_rctl_dfctl wge_ctl; 2196 struct wqe_common wqe_com; /* words 6-11 */ 2197 /* Note: word10 different REVISIT */ 2198 uint32_t xmit_len; 2199 uint32_t rsvd_12_15[3]; 2200 }; 2201 struct xmit_bcast64_wqe { 2202 struct ulp_bde64 bde; 2203 uint32_t paylaod_len; 2204 uint32_t rsvd4; 2205 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 2206 struct wqe_common wqe_com; /* words 6-11 */ 2207 uint32_t rsvd_12_15[4]; 2208 }; 2209 2210 struct gen_req64_wqe { 2211 struct ulp_bde64 bde; 2212 uint32_t command_len; 2213 uint32_t payload_len; 2214 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 2215 struct wqe_common wqe_com; /* words 6-11 */ 2216 uint32_t rsvd_12_15[4]; 2217 }; 2218 2219 struct create_xri_wqe { 2220 uint32_t rsrvd[5]; /* words 0-4 */ 2221 struct wqe_did wqe_dest; /* word 5 */ 2222 struct wqe_common wqe_com; /* words 6-11 */ 2223 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2224 }; 2225 2226 #define T_REQUEST_TAG 3 2227 #define T_XRI_TAG 1 2228 2229 struct abort_cmd_wqe { 2230 uint32_t rsrvd[3]; 2231 uint32_t word3; 2232 #define abort_cmd_ia_SHIFT 0 2233 #define abort_cmd_ia_MASK 0x000000001 2234 #define abort_cmd_ia_WORD word3 2235 #define abort_cmd_criteria_SHIFT 8 2236 #define abort_cmd_criteria_MASK 0x0000000ff 2237 #define abort_cmd_criteria_WORD word3 2238 uint32_t rsrvd4; 2239 uint32_t rsrvd5; 2240 struct wqe_common wqe_com; /* words 6-11 */ 2241 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2242 }; 2243 2244 struct fcp_iwrite64_wqe { 2245 struct ulp_bde64 bde; 2246 uint32_t payload_len; 2247 uint32_t total_xfer_len; 2248 uint32_t initial_xfer_len; 2249 struct wqe_common wqe_com; /* words 6-11 */ 2250 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2251 }; 2252 2253 struct fcp_iread64_wqe { 2254 struct ulp_bde64 bde; 2255 uint32_t payload_len; /* word 3 */ 2256 uint32_t total_xfer_len; /* word 4 */ 2257 uint32_t rsrvd5; /* word 5 */ 2258 struct wqe_common wqe_com; /* words 6-11 */ 2259 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2260 }; 2261 2262 struct fcp_icmnd64_wqe { 2263 struct ulp_bde64 bde; /* words 0-2 */ 2264 uint32_t rsrvd[3]; /* words 3-5 */ 2265 struct wqe_common wqe_com; /* words 6-11 */ 2266 uint32_t rsvd_12_15[4]; /* word 12-15 */ 2267 }; 2268 2269 2270 union lpfc_wqe { 2271 uint32_t words[16]; 2272 struct lpfc_wqe_generic generic; 2273 struct fcp_icmnd64_wqe fcp_icmd; 2274 struct fcp_iread64_wqe fcp_iread; 2275 struct fcp_iwrite64_wqe fcp_iwrite; 2276 struct abort_cmd_wqe abort_cmd; 2277 struct create_xri_wqe create_xri; 2278 struct xmit_bcast64_wqe xmit_bcast64; 2279 struct xmit_seq64_wqe xmit_sequence; 2280 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 2281 struct xmit_els_rsp64_wqe xmit_els_rsp; 2282 struct els_request64_wqe els_req; 2283 struct gen_req64_wqe gen_req; 2284 }; 2285 2286 #define FCP_COMMAND 0x0 2287 #define FCP_COMMAND_DATA_OUT 0x1 2288 #define ELS_COMMAND_NON_FIP 0xC 2289 #define ELS_COMMAND_FIP 0xD 2290 #define OTHER_COMMAND 0x8 2291 2292