1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE 8 110 #define LPFC_MAX_CQ_PAGE 4 111 #define LPFC_MAX_EQ_PAGE 8 112 113 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 114 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 115 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 116 117 /* Define SLI4 Alignment requirements. */ 118 #define LPFC_ALIGN_16_BYTE 16 119 #define LPFC_ALIGN_64_BYTE 64 120 121 /* Define SLI4 specific definitions. */ 122 #define LPFC_MQ_CQE_BYTE_OFFSET 256 123 #define LPFC_MBX_CMD_HDR_LENGTH 16 124 #define LPFC_MBX_ERROR_RANGE 0x4000 125 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 126 #define LPFC_BMBX_BIT1_ADDR_LO 0 127 #define LPFC_RPI_HDR_COUNT 64 128 #define LPFC_HDR_TEMPLATE_SIZE 4096 129 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 130 #define LPFC_FCF_RECORD_WD_CNT 132 131 #define LPFC_ENTIRE_FCF_DATABASE 0 132 #define LPFC_DFLT_FCF_INDEX 0 133 134 /* Virtual function numbers */ 135 #define LPFC_VF0 0 136 #define LPFC_VF1 1 137 #define LPFC_VF2 2 138 #define LPFC_VF3 3 139 #define LPFC_VF4 4 140 #define LPFC_VF5 5 141 #define LPFC_VF6 6 142 #define LPFC_VF7 7 143 #define LPFC_VF8 8 144 #define LPFC_VF9 9 145 #define LPFC_VF10 10 146 #define LPFC_VF11 11 147 #define LPFC_VF12 12 148 #define LPFC_VF13 13 149 #define LPFC_VF14 14 150 #define LPFC_VF15 15 151 #define LPFC_VF16 16 152 #define LPFC_VF17 17 153 #define LPFC_VF18 18 154 #define LPFC_VF19 19 155 #define LPFC_VF20 20 156 #define LPFC_VF21 21 157 #define LPFC_VF22 22 158 #define LPFC_VF23 23 159 #define LPFC_VF24 24 160 #define LPFC_VF25 25 161 #define LPFC_VF26 26 162 #define LPFC_VF27 27 163 #define LPFC_VF28 28 164 #define LPFC_VF29 29 165 #define LPFC_VF30 30 166 #define LPFC_VF31 31 167 168 /* PCI function numbers */ 169 #define LPFC_PCI_FUNC0 0 170 #define LPFC_PCI_FUNC1 1 171 #define LPFC_PCI_FUNC2 2 172 #define LPFC_PCI_FUNC3 3 173 #define LPFC_PCI_FUNC4 4 174 175 /* SLI4 interface type-2 PDEV_CTL register */ 176 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 177 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 178 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 179 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 180 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 181 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 182 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 183 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 184 185 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 186 187 /* Active interrupt test count */ 188 #define LPFC_ACT_INTR_CNT 4 189 190 /* Delay Multiplier constant */ 191 #define LPFC_DMULT_CONST 651042 192 #define LPFC_MIM_IMAX 636 193 #define LPFC_FP_DEF_IMAX 10000 194 #define LPFC_SP_DEF_IMAX 10000 195 196 /* PORT_CAPABILITIES constants. */ 197 #define LPFC_MAX_SUPPORTED_PAGES 8 198 199 struct ulp_bde64 { 200 union ULP_BDE_TUS { 201 uint32_t w; 202 struct { 203 #ifdef __BIG_ENDIAN_BITFIELD 204 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 205 VALUE !! */ 206 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 207 #else /* __LITTLE_ENDIAN_BITFIELD */ 208 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 209 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 210 VALUE !! */ 211 #endif 212 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 213 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 214 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 215 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 216 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 217 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 218 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 219 } f; 220 } tus; 221 uint32_t addrLow; 222 uint32_t addrHigh; 223 }; 224 225 struct lpfc_sli4_flags { 226 uint32_t word0; 227 #define lpfc_idx_rsrc_rdy_SHIFT 0 228 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 229 #define lpfc_idx_rsrc_rdy_WORD word0 230 #define LPFC_IDX_RSRC_RDY 1 231 #define lpfc_xri_rsrc_rdy_SHIFT 1 232 #define lpfc_xri_rsrc_rdy_MASK 0x00000001 233 #define lpfc_xri_rsrc_rdy_WORD word0 234 #define LPFC_XRI_RSRC_RDY 1 235 #define lpfc_rpi_rsrc_rdy_SHIFT 2 236 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 237 #define lpfc_rpi_rsrc_rdy_WORD word0 238 #define LPFC_RPI_RSRC_RDY 1 239 #define lpfc_vpi_rsrc_rdy_SHIFT 3 240 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 241 #define lpfc_vpi_rsrc_rdy_WORD word0 242 #define LPFC_VPI_RSRC_RDY 1 243 #define lpfc_vfi_rsrc_rdy_SHIFT 4 244 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 245 #define lpfc_vfi_rsrc_rdy_WORD word0 246 #define LPFC_VFI_RSRC_RDY 1 247 }; 248 249 struct sli4_bls_rsp { 250 uint32_t word0_rsvd; /* Word0 must be reserved */ 251 uint32_t word1; 252 #define lpfc_abts_orig_SHIFT 0 253 #define lpfc_abts_orig_MASK 0x00000001 254 #define lpfc_abts_orig_WORD word1 255 #define LPFC_ABTS_UNSOL_RSP 1 256 #define LPFC_ABTS_UNSOL_INT 0 257 uint32_t word2; 258 #define lpfc_abts_rxid_SHIFT 0 259 #define lpfc_abts_rxid_MASK 0x0000FFFF 260 #define lpfc_abts_rxid_WORD word2 261 #define lpfc_abts_oxid_SHIFT 16 262 #define lpfc_abts_oxid_MASK 0x0000FFFF 263 #define lpfc_abts_oxid_WORD word2 264 uint32_t word3; 265 #define lpfc_vndr_code_SHIFT 0 266 #define lpfc_vndr_code_MASK 0x000000FF 267 #define lpfc_vndr_code_WORD word3 268 #define lpfc_rsn_expln_SHIFT 8 269 #define lpfc_rsn_expln_MASK 0x000000FF 270 #define lpfc_rsn_expln_WORD word3 271 #define lpfc_rsn_code_SHIFT 16 272 #define lpfc_rsn_code_MASK 0x000000FF 273 #define lpfc_rsn_code_WORD word3 274 275 uint32_t word4; 276 uint32_t word5_rsvd; /* Word5 must be reserved */ 277 }; 278 279 /* event queue entry structure */ 280 struct lpfc_eqe { 281 uint32_t word0; 282 #define lpfc_eqe_resource_id_SHIFT 16 283 #define lpfc_eqe_resource_id_MASK 0x000000FF 284 #define lpfc_eqe_resource_id_WORD word0 285 #define lpfc_eqe_minor_code_SHIFT 4 286 #define lpfc_eqe_minor_code_MASK 0x00000FFF 287 #define lpfc_eqe_minor_code_WORD word0 288 #define lpfc_eqe_major_code_SHIFT 1 289 #define lpfc_eqe_major_code_MASK 0x00000007 290 #define lpfc_eqe_major_code_WORD word0 291 #define lpfc_eqe_valid_SHIFT 0 292 #define lpfc_eqe_valid_MASK 0x00000001 293 #define lpfc_eqe_valid_WORD word0 294 }; 295 296 /* completion queue entry structure (common fields for all cqe types) */ 297 struct lpfc_cqe { 298 uint32_t reserved0; 299 uint32_t reserved1; 300 uint32_t reserved2; 301 uint32_t word3; 302 #define lpfc_cqe_valid_SHIFT 31 303 #define lpfc_cqe_valid_MASK 0x00000001 304 #define lpfc_cqe_valid_WORD word3 305 #define lpfc_cqe_code_SHIFT 16 306 #define lpfc_cqe_code_MASK 0x000000FF 307 #define lpfc_cqe_code_WORD word3 308 }; 309 310 /* Completion Queue Entry Status Codes */ 311 #define CQE_STATUS_SUCCESS 0x0 312 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 313 #define CQE_STATUS_REMOTE_STOP 0x2 314 #define CQE_STATUS_LOCAL_REJECT 0x3 315 #define CQE_STATUS_NPORT_RJT 0x4 316 #define CQE_STATUS_FABRIC_RJT 0x5 317 #define CQE_STATUS_NPORT_BSY 0x6 318 #define CQE_STATUS_FABRIC_BSY 0x7 319 #define CQE_STATUS_INTERMED_RSP 0x8 320 #define CQE_STATUS_LS_RJT 0x9 321 #define CQE_STATUS_CMD_REJECT 0xb 322 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 323 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 324 #define CQE_STATUS_DI_ERROR 0x16 325 326 /* Used when mapping CQE status to IOCB */ 327 #define LPFC_IOCB_STATUS_MASK 0xf 328 329 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 330 #define CQE_HW_STATUS_NO_ERR 0x0 331 #define CQE_HW_STATUS_UNDERRUN 0x1 332 #define CQE_HW_STATUS_OVERRUN 0x2 333 334 /* Completion Queue Entry Codes */ 335 #define CQE_CODE_COMPL_WQE 0x1 336 #define CQE_CODE_RELEASE_WQE 0x2 337 #define CQE_CODE_RECEIVE 0x4 338 #define CQE_CODE_XRI_ABORTED 0x5 339 #define CQE_CODE_RECEIVE_V1 0x9 340 341 /* completion queue entry for wqe completions */ 342 struct lpfc_wcqe_complete { 343 uint32_t word0; 344 #define lpfc_wcqe_c_request_tag_SHIFT 16 345 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 346 #define lpfc_wcqe_c_request_tag_WORD word0 347 #define lpfc_wcqe_c_status_SHIFT 8 348 #define lpfc_wcqe_c_status_MASK 0x000000FF 349 #define lpfc_wcqe_c_status_WORD word0 350 #define lpfc_wcqe_c_hw_status_SHIFT 0 351 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 352 #define lpfc_wcqe_c_hw_status_WORD word0 353 uint32_t total_data_placed; 354 uint32_t parameter; 355 #define lpfc_wcqe_c_bg_edir_SHIFT 5 356 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 357 #define lpfc_wcqe_c_bg_edir_WORD parameter 358 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 359 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 360 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 361 #define lpfc_wcqe_c_bg_re_SHIFT 2 362 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 363 #define lpfc_wcqe_c_bg_re_WORD parameter 364 #define lpfc_wcqe_c_bg_ae_SHIFT 1 365 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 366 #define lpfc_wcqe_c_bg_ae_WORD parameter 367 #define lpfc_wcqe_c_bg_ge_SHIFT 0 368 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 369 #define lpfc_wcqe_c_bg_ge_WORD parameter 370 uint32_t word3; 371 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 372 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 373 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 374 #define lpfc_wcqe_c_xb_SHIFT 28 375 #define lpfc_wcqe_c_xb_MASK 0x00000001 376 #define lpfc_wcqe_c_xb_WORD word3 377 #define lpfc_wcqe_c_pv_SHIFT 27 378 #define lpfc_wcqe_c_pv_MASK 0x00000001 379 #define lpfc_wcqe_c_pv_WORD word3 380 #define lpfc_wcqe_c_priority_SHIFT 24 381 #define lpfc_wcqe_c_priority_MASK 0x00000007 382 #define lpfc_wcqe_c_priority_WORD word3 383 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 384 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 385 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 386 }; 387 388 /* completion queue entry for wqe release */ 389 struct lpfc_wcqe_release { 390 uint32_t reserved0; 391 uint32_t reserved1; 392 uint32_t word2; 393 #define lpfc_wcqe_r_wq_id_SHIFT 16 394 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 395 #define lpfc_wcqe_r_wq_id_WORD word2 396 #define lpfc_wcqe_r_wqe_index_SHIFT 0 397 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 398 #define lpfc_wcqe_r_wqe_index_WORD word2 399 uint32_t word3; 400 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 401 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 402 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 403 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 404 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 405 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 406 }; 407 408 struct sli4_wcqe_xri_aborted { 409 uint32_t word0; 410 #define lpfc_wcqe_xa_status_SHIFT 8 411 #define lpfc_wcqe_xa_status_MASK 0x000000FF 412 #define lpfc_wcqe_xa_status_WORD word0 413 uint32_t parameter; 414 uint32_t word2; 415 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 416 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 417 #define lpfc_wcqe_xa_remote_xid_WORD word2 418 #define lpfc_wcqe_xa_xri_SHIFT 0 419 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 420 #define lpfc_wcqe_xa_xri_WORD word2 421 uint32_t word3; 422 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 423 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 424 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 425 #define lpfc_wcqe_xa_ia_SHIFT 30 426 #define lpfc_wcqe_xa_ia_MASK 0x00000001 427 #define lpfc_wcqe_xa_ia_WORD word3 428 #define CQE_XRI_ABORTED_IA_REMOTE 0 429 #define CQE_XRI_ABORTED_IA_LOCAL 1 430 #define lpfc_wcqe_xa_br_SHIFT 29 431 #define lpfc_wcqe_xa_br_MASK 0x00000001 432 #define lpfc_wcqe_xa_br_WORD word3 433 #define CQE_XRI_ABORTED_BR_BA_ACC 0 434 #define CQE_XRI_ABORTED_BR_BA_RJT 1 435 #define lpfc_wcqe_xa_eo_SHIFT 28 436 #define lpfc_wcqe_xa_eo_MASK 0x00000001 437 #define lpfc_wcqe_xa_eo_WORD word3 438 #define CQE_XRI_ABORTED_EO_REMOTE 0 439 #define CQE_XRI_ABORTED_EO_LOCAL 1 440 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 441 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 442 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 443 }; 444 445 /* completion queue entry structure for rqe completion */ 446 struct lpfc_rcqe { 447 uint32_t word0; 448 #define lpfc_rcqe_bindex_SHIFT 16 449 #define lpfc_rcqe_bindex_MASK 0x0000FFF 450 #define lpfc_rcqe_bindex_WORD word0 451 #define lpfc_rcqe_status_SHIFT 8 452 #define lpfc_rcqe_status_MASK 0x000000FF 453 #define lpfc_rcqe_status_WORD word0 454 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 455 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 456 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 457 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 458 uint32_t word1; 459 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 460 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 461 #define lpfc_rcqe_fcf_id_v1_WORD word1 462 uint32_t word2; 463 #define lpfc_rcqe_length_SHIFT 16 464 #define lpfc_rcqe_length_MASK 0x0000FFFF 465 #define lpfc_rcqe_length_WORD word2 466 #define lpfc_rcqe_rq_id_SHIFT 6 467 #define lpfc_rcqe_rq_id_MASK 0x000003FF 468 #define lpfc_rcqe_rq_id_WORD word2 469 #define lpfc_rcqe_fcf_id_SHIFT 0 470 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 471 #define lpfc_rcqe_fcf_id_WORD word2 472 #define lpfc_rcqe_rq_id_v1_SHIFT 0 473 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 474 #define lpfc_rcqe_rq_id_v1_WORD word2 475 uint32_t word3; 476 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 477 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 478 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 479 #define lpfc_rcqe_port_SHIFT 30 480 #define lpfc_rcqe_port_MASK 0x00000001 481 #define lpfc_rcqe_port_WORD word3 482 #define lpfc_rcqe_hdr_length_SHIFT 24 483 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 484 #define lpfc_rcqe_hdr_length_WORD word3 485 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 486 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 487 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 488 #define lpfc_rcqe_eof_SHIFT 8 489 #define lpfc_rcqe_eof_MASK 0x000000FF 490 #define lpfc_rcqe_eof_WORD word3 491 #define FCOE_EOFn 0x41 492 #define FCOE_EOFt 0x42 493 #define FCOE_EOFni 0x49 494 #define FCOE_EOFa 0x50 495 #define lpfc_rcqe_sof_SHIFT 0 496 #define lpfc_rcqe_sof_MASK 0x000000FF 497 #define lpfc_rcqe_sof_WORD word3 498 #define FCOE_SOFi2 0x2d 499 #define FCOE_SOFi3 0x2e 500 #define FCOE_SOFn2 0x35 501 #define FCOE_SOFn3 0x36 502 }; 503 504 struct lpfc_rqe { 505 uint32_t address_hi; 506 uint32_t address_lo; 507 }; 508 509 /* buffer descriptors */ 510 struct lpfc_bde4 { 511 uint32_t addr_hi; 512 uint32_t addr_lo; 513 uint32_t word2; 514 #define lpfc_bde4_last_SHIFT 31 515 #define lpfc_bde4_last_MASK 0x00000001 516 #define lpfc_bde4_last_WORD word2 517 #define lpfc_bde4_sge_offset_SHIFT 0 518 #define lpfc_bde4_sge_offset_MASK 0x000003FF 519 #define lpfc_bde4_sge_offset_WORD word2 520 uint32_t word3; 521 #define lpfc_bde4_length_SHIFT 0 522 #define lpfc_bde4_length_MASK 0x000000FF 523 #define lpfc_bde4_length_WORD word3 524 }; 525 526 struct lpfc_register { 527 uint32_t word0; 528 }; 529 530 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 531 #define LPFC_UERR_STATUS_HI 0x00A4 532 #define LPFC_UERR_STATUS_LO 0x00A0 533 #define LPFC_UE_MASK_HI 0x00AC 534 #define LPFC_UE_MASK_LO 0x00A8 535 536 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 537 #define LPFC_SLI_INTF 0x0058 538 539 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 540 #define lpfc_port_smphr_perr_SHIFT 31 541 #define lpfc_port_smphr_perr_MASK 0x1 542 #define lpfc_port_smphr_perr_WORD word0 543 #define lpfc_port_smphr_sfi_SHIFT 30 544 #define lpfc_port_smphr_sfi_MASK 0x1 545 #define lpfc_port_smphr_sfi_WORD word0 546 #define lpfc_port_smphr_nip_SHIFT 29 547 #define lpfc_port_smphr_nip_MASK 0x1 548 #define lpfc_port_smphr_nip_WORD word0 549 #define lpfc_port_smphr_ipc_SHIFT 28 550 #define lpfc_port_smphr_ipc_MASK 0x1 551 #define lpfc_port_smphr_ipc_WORD word0 552 #define lpfc_port_smphr_scr1_SHIFT 27 553 #define lpfc_port_smphr_scr1_MASK 0x1 554 #define lpfc_port_smphr_scr1_WORD word0 555 #define lpfc_port_smphr_scr2_SHIFT 26 556 #define lpfc_port_smphr_scr2_MASK 0x1 557 #define lpfc_port_smphr_scr2_WORD word0 558 #define lpfc_port_smphr_host_scratch_SHIFT 16 559 #define lpfc_port_smphr_host_scratch_MASK 0xFF 560 #define lpfc_port_smphr_host_scratch_WORD word0 561 #define lpfc_port_smphr_port_status_SHIFT 0 562 #define lpfc_port_smphr_port_status_MASK 0xFFFF 563 #define lpfc_port_smphr_port_status_WORD word0 564 565 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 566 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 567 #define LPFC_POST_STAGE_HOST_RDY 0x0002 568 #define LPFC_POST_STAGE_BE_RESET 0x0003 569 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 570 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 571 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 572 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 573 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 574 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 575 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 576 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 577 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 578 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 579 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 580 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 581 #define LPFC_POST_STAGE_ARMFW_START 0x0800 582 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 583 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 584 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 585 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 586 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 587 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 588 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 589 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 590 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 591 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 592 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 593 #define LPFC_POST_STAGE_RC_DONE 0x0B07 594 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 595 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 596 #define LPFC_POST_STAGE_PORT_READY 0xC000 597 #define LPFC_POST_STAGE_PORT_UE 0xF000 598 599 #define LPFC_CTL_PORT_STA_OFFSET 0x404 600 #define lpfc_sliport_status_err_SHIFT 31 601 #define lpfc_sliport_status_err_MASK 0x1 602 #define lpfc_sliport_status_err_WORD word0 603 #define lpfc_sliport_status_end_SHIFT 30 604 #define lpfc_sliport_status_end_MASK 0x1 605 #define lpfc_sliport_status_end_WORD word0 606 #define lpfc_sliport_status_oti_SHIFT 29 607 #define lpfc_sliport_status_oti_MASK 0x1 608 #define lpfc_sliport_status_oti_WORD word0 609 #define lpfc_sliport_status_rn_SHIFT 24 610 #define lpfc_sliport_status_rn_MASK 0x1 611 #define lpfc_sliport_status_rn_WORD word0 612 #define lpfc_sliport_status_rdy_SHIFT 23 613 #define lpfc_sliport_status_rdy_MASK 0x1 614 #define lpfc_sliport_status_rdy_WORD word0 615 #define MAX_IF_TYPE_2_RESETS 1000 616 617 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 618 #define lpfc_sliport_ctrl_end_SHIFT 30 619 #define lpfc_sliport_ctrl_end_MASK 0x1 620 #define lpfc_sliport_ctrl_end_WORD word0 621 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 622 #define LPFC_SLIPORT_BIG_ENDIAN 1 623 #define lpfc_sliport_ctrl_ip_SHIFT 27 624 #define lpfc_sliport_ctrl_ip_MASK 0x1 625 #define lpfc_sliport_ctrl_ip_WORD word0 626 #define LPFC_SLIPORT_INIT_PORT 1 627 628 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 629 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 630 631 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 632 * reside in BAR 2. 633 */ 634 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 635 636 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 637 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 638 639 #define LPFC_HST_ISR0 0x0C18 640 #define LPFC_HST_ISR1 0x0C1C 641 #define LPFC_HST_ISR2 0x0C20 642 #define LPFC_HST_ISR3 0x0C24 643 #define LPFC_HST_ISR4 0x0C28 644 645 #define LPFC_HST_IMR0 0x0C48 646 #define LPFC_HST_IMR1 0x0C4C 647 #define LPFC_HST_IMR2 0x0C50 648 #define LPFC_HST_IMR3 0x0C54 649 #define LPFC_HST_IMR4 0x0C58 650 651 #define LPFC_HST_ISCR0 0x0C78 652 #define LPFC_HST_ISCR1 0x0C7C 653 #define LPFC_HST_ISCR2 0x0C80 654 #define LPFC_HST_ISCR3 0x0C84 655 #define LPFC_HST_ISCR4 0x0C88 656 657 #define LPFC_SLI4_INTR0 BIT0 658 #define LPFC_SLI4_INTR1 BIT1 659 #define LPFC_SLI4_INTR2 BIT2 660 #define LPFC_SLI4_INTR3 BIT3 661 #define LPFC_SLI4_INTR4 BIT4 662 #define LPFC_SLI4_INTR5 BIT5 663 #define LPFC_SLI4_INTR6 BIT6 664 #define LPFC_SLI4_INTR7 BIT7 665 #define LPFC_SLI4_INTR8 BIT8 666 #define LPFC_SLI4_INTR9 BIT9 667 #define LPFC_SLI4_INTR10 BIT10 668 #define LPFC_SLI4_INTR11 BIT11 669 #define LPFC_SLI4_INTR12 BIT12 670 #define LPFC_SLI4_INTR13 BIT13 671 #define LPFC_SLI4_INTR14 BIT14 672 #define LPFC_SLI4_INTR15 BIT15 673 #define LPFC_SLI4_INTR16 BIT16 674 #define LPFC_SLI4_INTR17 BIT17 675 #define LPFC_SLI4_INTR18 BIT18 676 #define LPFC_SLI4_INTR19 BIT19 677 #define LPFC_SLI4_INTR20 BIT20 678 #define LPFC_SLI4_INTR21 BIT21 679 #define LPFC_SLI4_INTR22 BIT22 680 #define LPFC_SLI4_INTR23 BIT23 681 #define LPFC_SLI4_INTR24 BIT24 682 #define LPFC_SLI4_INTR25 BIT25 683 #define LPFC_SLI4_INTR26 BIT26 684 #define LPFC_SLI4_INTR27 BIT27 685 #define LPFC_SLI4_INTR28 BIT28 686 #define LPFC_SLI4_INTR29 BIT29 687 #define LPFC_SLI4_INTR30 BIT30 688 #define LPFC_SLI4_INTR31 BIT31 689 690 /* 691 * The Doorbell registers defined here exist in different BAR 692 * register sets depending on the UCNA Port's reported if_type 693 * value. For UCNA ports running SLI4 and if_type 0, they reside in 694 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 695 * BAR0. The offsets are the same so the driver must account for 696 * any base address difference. 697 */ 698 #define LPFC_RQ_DOORBELL 0x00A0 699 #define lpfc_rq_doorbell_num_posted_SHIFT 16 700 #define lpfc_rq_doorbell_num_posted_MASK 0x3FFF 701 #define lpfc_rq_doorbell_num_posted_WORD word0 702 #define lpfc_rq_doorbell_id_SHIFT 0 703 #define lpfc_rq_doorbell_id_MASK 0xFFFF 704 #define lpfc_rq_doorbell_id_WORD word0 705 706 #define LPFC_WQ_DOORBELL 0x0040 707 #define lpfc_wq_doorbell_num_posted_SHIFT 24 708 #define lpfc_wq_doorbell_num_posted_MASK 0x00FF 709 #define lpfc_wq_doorbell_num_posted_WORD word0 710 #define lpfc_wq_doorbell_index_SHIFT 16 711 #define lpfc_wq_doorbell_index_MASK 0x00FF 712 #define lpfc_wq_doorbell_index_WORD word0 713 #define lpfc_wq_doorbell_id_SHIFT 0 714 #define lpfc_wq_doorbell_id_MASK 0xFFFF 715 #define lpfc_wq_doorbell_id_WORD word0 716 717 #define LPFC_EQCQ_DOORBELL 0x0120 718 #define lpfc_eqcq_doorbell_se_SHIFT 31 719 #define lpfc_eqcq_doorbell_se_MASK 0x0001 720 #define lpfc_eqcq_doorbell_se_WORD word0 721 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 722 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 723 #define lpfc_eqcq_doorbell_arm_SHIFT 29 724 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 725 #define lpfc_eqcq_doorbell_arm_WORD word0 726 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 727 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 728 #define lpfc_eqcq_doorbell_num_released_WORD word0 729 #define lpfc_eqcq_doorbell_qt_SHIFT 10 730 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 731 #define lpfc_eqcq_doorbell_qt_WORD word0 732 #define LPFC_QUEUE_TYPE_COMPLETION 0 733 #define LPFC_QUEUE_TYPE_EVENT 1 734 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 735 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 736 #define lpfc_eqcq_doorbell_eqci_WORD word0 737 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 738 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 739 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 740 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 741 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 742 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 743 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 744 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 745 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 746 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 747 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 748 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 749 #define LPFC_CQID_HI_FIELD_SHIFT 10 750 #define LPFC_EQID_HI_FIELD_SHIFT 9 751 752 #define LPFC_BMBX 0x0160 753 #define lpfc_bmbx_addr_SHIFT 2 754 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 755 #define lpfc_bmbx_addr_WORD word0 756 #define lpfc_bmbx_hi_SHIFT 1 757 #define lpfc_bmbx_hi_MASK 0x0001 758 #define lpfc_bmbx_hi_WORD word0 759 #define lpfc_bmbx_rdy_SHIFT 0 760 #define lpfc_bmbx_rdy_MASK 0x0001 761 #define lpfc_bmbx_rdy_WORD word0 762 763 #define LPFC_MQ_DOORBELL 0x0140 764 #define lpfc_mq_doorbell_num_posted_SHIFT 16 765 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 766 #define lpfc_mq_doorbell_num_posted_WORD word0 767 #define lpfc_mq_doorbell_id_SHIFT 0 768 #define lpfc_mq_doorbell_id_MASK 0xFFFF 769 #define lpfc_mq_doorbell_id_WORD word0 770 771 struct lpfc_sli4_cfg_mhdr { 772 uint32_t word1; 773 #define lpfc_mbox_hdr_emb_SHIFT 0 774 #define lpfc_mbox_hdr_emb_MASK 0x00000001 775 #define lpfc_mbox_hdr_emb_WORD word1 776 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 777 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 778 #define lpfc_mbox_hdr_sge_cnt_WORD word1 779 uint32_t payload_length; 780 uint32_t tag_lo; 781 uint32_t tag_hi; 782 uint32_t reserved5; 783 }; 784 785 union lpfc_sli4_cfg_shdr { 786 struct { 787 uint32_t word6; 788 #define lpfc_mbox_hdr_opcode_SHIFT 0 789 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 790 #define lpfc_mbox_hdr_opcode_WORD word6 791 #define lpfc_mbox_hdr_subsystem_SHIFT 8 792 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 793 #define lpfc_mbox_hdr_subsystem_WORD word6 794 #define lpfc_mbox_hdr_port_number_SHIFT 16 795 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 796 #define lpfc_mbox_hdr_port_number_WORD word6 797 #define lpfc_mbox_hdr_domain_SHIFT 24 798 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 799 #define lpfc_mbox_hdr_domain_WORD word6 800 uint32_t timeout; 801 uint32_t request_length; 802 uint32_t word9; 803 #define lpfc_mbox_hdr_version_SHIFT 0 804 #define lpfc_mbox_hdr_version_MASK 0x000000FF 805 #define lpfc_mbox_hdr_version_WORD word9 806 #define lpfc_mbox_hdr_pf_num_SHIFT 16 807 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 808 #define lpfc_mbox_hdr_pf_num_WORD word9 809 #define lpfc_mbox_hdr_vh_num_SHIFT 24 810 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 811 #define lpfc_mbox_hdr_vh_num_WORD word9 812 #define LPFC_Q_CREATE_VERSION_2 2 813 #define LPFC_Q_CREATE_VERSION_1 1 814 #define LPFC_Q_CREATE_VERSION_0 0 815 #define LPFC_OPCODE_VERSION_0 0 816 #define LPFC_OPCODE_VERSION_1 1 817 } request; 818 struct { 819 uint32_t word6; 820 #define lpfc_mbox_hdr_opcode_SHIFT 0 821 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 822 #define lpfc_mbox_hdr_opcode_WORD word6 823 #define lpfc_mbox_hdr_subsystem_SHIFT 8 824 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 825 #define lpfc_mbox_hdr_subsystem_WORD word6 826 #define lpfc_mbox_hdr_domain_SHIFT 24 827 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 828 #define lpfc_mbox_hdr_domain_WORD word6 829 uint32_t word7; 830 #define lpfc_mbox_hdr_status_SHIFT 0 831 #define lpfc_mbox_hdr_status_MASK 0x000000FF 832 #define lpfc_mbox_hdr_status_WORD word7 833 #define lpfc_mbox_hdr_add_status_SHIFT 8 834 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 835 #define lpfc_mbox_hdr_add_status_WORD word7 836 uint32_t response_length; 837 uint32_t actual_response_length; 838 } response; 839 }; 840 841 /* Mailbox Header structures. 842 * struct mbox_header is defined for first generation SLI4_CFG mailbox 843 * calls deployed for BE-based ports. 844 * 845 * struct sli4_mbox_header is defined for second generation SLI4 846 * ports that don't deploy the SLI4_CFG mechanism. 847 */ 848 struct mbox_header { 849 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 850 union lpfc_sli4_cfg_shdr cfg_shdr; 851 }; 852 853 #define LPFC_EXTENT_LOCAL 0 854 #define LPFC_TIMEOUT_DEFAULT 0 855 #define LPFC_EXTENT_VERSION_DEFAULT 0 856 857 /* Subsystem Definitions */ 858 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 859 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 860 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 861 862 /* Device Specific Definitions */ 863 864 /* The HOST ENDIAN defines are in Big Endian format. */ 865 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 866 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 867 868 /* Common Opcodes */ 869 #define LPFC_MBOX_OPCODE_NA 0x00 870 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 871 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 872 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 873 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 874 #define LPFC_MBOX_OPCODE_NOP 0x21 875 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 876 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 877 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 878 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 879 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 880 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 881 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 882 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 883 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 884 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 885 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 886 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 887 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 888 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 889 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 890 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 891 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 892 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 893 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 894 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 895 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 896 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 897 898 /* FCoE Opcodes */ 899 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 900 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 901 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 902 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 903 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 904 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 905 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 906 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 907 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 908 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 909 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 910 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 911 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 912 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 913 914 /* Mailbox command structures */ 915 struct eq_context { 916 uint32_t word0; 917 #define lpfc_eq_context_size_SHIFT 31 918 #define lpfc_eq_context_size_MASK 0x00000001 919 #define lpfc_eq_context_size_WORD word0 920 #define LPFC_EQE_SIZE_4 0x0 921 #define LPFC_EQE_SIZE_16 0x1 922 #define lpfc_eq_context_valid_SHIFT 29 923 #define lpfc_eq_context_valid_MASK 0x00000001 924 #define lpfc_eq_context_valid_WORD word0 925 uint32_t word1; 926 #define lpfc_eq_context_count_SHIFT 26 927 #define lpfc_eq_context_count_MASK 0x00000003 928 #define lpfc_eq_context_count_WORD word1 929 #define LPFC_EQ_CNT_256 0x0 930 #define LPFC_EQ_CNT_512 0x1 931 #define LPFC_EQ_CNT_1024 0x2 932 #define LPFC_EQ_CNT_2048 0x3 933 #define LPFC_EQ_CNT_4096 0x4 934 uint32_t word2; 935 #define lpfc_eq_context_delay_multi_SHIFT 13 936 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 937 #define lpfc_eq_context_delay_multi_WORD word2 938 uint32_t reserved3; 939 }; 940 941 struct sgl_page_pairs { 942 uint32_t sgl_pg0_addr_lo; 943 uint32_t sgl_pg0_addr_hi; 944 uint32_t sgl_pg1_addr_lo; 945 uint32_t sgl_pg1_addr_hi; 946 }; 947 948 struct lpfc_mbx_post_sgl_pages { 949 struct mbox_header header; 950 uint32_t word0; 951 #define lpfc_post_sgl_pages_xri_SHIFT 0 952 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 953 #define lpfc_post_sgl_pages_xri_WORD word0 954 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 955 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 956 #define lpfc_post_sgl_pages_xricnt_WORD word0 957 struct sgl_page_pairs sgl_pg_pairs[1]; 958 }; 959 960 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 961 struct lpfc_mbx_post_uembed_sgl_page1 { 962 union lpfc_sli4_cfg_shdr cfg_shdr; 963 uint32_t word0; 964 struct sgl_page_pairs sgl_pg_pairs; 965 }; 966 967 struct lpfc_mbx_sge { 968 uint32_t pa_lo; 969 uint32_t pa_hi; 970 uint32_t length; 971 }; 972 973 struct lpfc_mbx_nembed_cmd { 974 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 975 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 976 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 977 }; 978 979 struct lpfc_mbx_nembed_sge_virt { 980 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 981 }; 982 983 struct lpfc_mbx_eq_create { 984 struct mbox_header header; 985 union { 986 struct { 987 uint32_t word0; 988 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 989 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 990 #define lpfc_mbx_eq_create_num_pages_WORD word0 991 struct eq_context context; 992 struct dma_address page[LPFC_MAX_EQ_PAGE]; 993 } request; 994 struct { 995 uint32_t word0; 996 #define lpfc_mbx_eq_create_q_id_SHIFT 0 997 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 998 #define lpfc_mbx_eq_create_q_id_WORD word0 999 } response; 1000 } u; 1001 }; 1002 1003 struct lpfc_mbx_eq_destroy { 1004 struct mbox_header header; 1005 union { 1006 struct { 1007 uint32_t word0; 1008 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1009 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1010 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1011 } request; 1012 struct { 1013 uint32_t word0; 1014 } response; 1015 } u; 1016 }; 1017 1018 struct lpfc_mbx_nop { 1019 struct mbox_header header; 1020 uint32_t context[2]; 1021 }; 1022 1023 struct cq_context { 1024 uint32_t word0; 1025 #define lpfc_cq_context_event_SHIFT 31 1026 #define lpfc_cq_context_event_MASK 0x00000001 1027 #define lpfc_cq_context_event_WORD word0 1028 #define lpfc_cq_context_valid_SHIFT 29 1029 #define lpfc_cq_context_valid_MASK 0x00000001 1030 #define lpfc_cq_context_valid_WORD word0 1031 #define lpfc_cq_context_count_SHIFT 27 1032 #define lpfc_cq_context_count_MASK 0x00000003 1033 #define lpfc_cq_context_count_WORD word0 1034 #define LPFC_CQ_CNT_256 0x0 1035 #define LPFC_CQ_CNT_512 0x1 1036 #define LPFC_CQ_CNT_1024 0x2 1037 uint32_t word1; 1038 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1039 #define lpfc_cq_eq_id_MASK 0x000000FF 1040 #define lpfc_cq_eq_id_WORD word1 1041 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1042 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1043 #define lpfc_cq_eq_id_2_WORD word1 1044 uint32_t reserved0; 1045 uint32_t reserved1; 1046 }; 1047 1048 struct lpfc_mbx_cq_create { 1049 struct mbox_header header; 1050 union { 1051 struct { 1052 uint32_t word0; 1053 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1054 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1055 #define lpfc_mbx_cq_create_page_size_WORD word0 1056 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1057 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1058 #define lpfc_mbx_cq_create_num_pages_WORD word0 1059 struct cq_context context; 1060 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1061 } request; 1062 struct { 1063 uint32_t word0; 1064 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1065 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1066 #define lpfc_mbx_cq_create_q_id_WORD word0 1067 } response; 1068 } u; 1069 }; 1070 1071 struct lpfc_mbx_cq_destroy { 1072 struct mbox_header header; 1073 union { 1074 struct { 1075 uint32_t word0; 1076 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1077 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1078 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1079 } request; 1080 struct { 1081 uint32_t word0; 1082 } response; 1083 } u; 1084 }; 1085 1086 struct wq_context { 1087 uint32_t reserved0; 1088 uint32_t reserved1; 1089 uint32_t reserved2; 1090 uint32_t reserved3; 1091 }; 1092 1093 struct lpfc_mbx_wq_create { 1094 struct mbox_header header; 1095 union { 1096 struct { /* Version 0 Request */ 1097 uint32_t word0; 1098 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1099 #define lpfc_mbx_wq_create_num_pages_MASK 0x0000FFFF 1100 #define lpfc_mbx_wq_create_num_pages_WORD word0 1101 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1102 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1103 #define lpfc_mbx_wq_create_cq_id_WORD word0 1104 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1105 } request; 1106 struct { /* Version 1 Request */ 1107 uint32_t word0; /* Word 0 is the same as in v0 */ 1108 uint32_t word1; 1109 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1110 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1111 #define lpfc_mbx_wq_create_page_size_WORD word1 1112 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1113 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1114 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1115 #define LPFC_WQ_WQE_SIZE_64 0x5 1116 #define LPFC_WQ_WQE_SIZE_128 0x6 1117 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1118 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1119 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1120 uint32_t word2; 1121 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1122 } request_1; 1123 struct { 1124 uint32_t word0; 1125 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1126 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1127 #define lpfc_mbx_wq_create_q_id_WORD word0 1128 } response; 1129 } u; 1130 }; 1131 1132 struct lpfc_mbx_wq_destroy { 1133 struct mbox_header header; 1134 union { 1135 struct { 1136 uint32_t word0; 1137 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1138 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1139 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1140 } request; 1141 struct { 1142 uint32_t word0; 1143 } response; 1144 } u; 1145 }; 1146 1147 #define LPFC_HDR_BUF_SIZE 128 1148 #define LPFC_DATA_BUF_SIZE 2048 1149 struct rq_context { 1150 uint32_t word0; 1151 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1152 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1153 #define lpfc_rq_context_rqe_count_WORD word0 1154 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1155 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1156 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1157 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1158 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1159 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1160 #define lpfc_rq_context_rqe_count_1_WORD word0 1161 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1162 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1163 #define lpfc_rq_context_rqe_size_WORD word0 1164 #define LPFC_RQE_SIZE_8 2 1165 #define LPFC_RQE_SIZE_16 3 1166 #define LPFC_RQE_SIZE_32 4 1167 #define LPFC_RQE_SIZE_64 5 1168 #define LPFC_RQE_SIZE_128 6 1169 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1170 #define lpfc_rq_context_page_size_MASK 0x000000FF 1171 #define lpfc_rq_context_page_size_WORD word0 1172 uint32_t reserved1; 1173 uint32_t word2; 1174 #define lpfc_rq_context_cq_id_SHIFT 16 1175 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1176 #define lpfc_rq_context_cq_id_WORD word2 1177 #define lpfc_rq_context_buf_size_SHIFT 0 1178 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1179 #define lpfc_rq_context_buf_size_WORD word2 1180 uint32_t buffer_size; /* Version 1 Only */ 1181 }; 1182 1183 struct lpfc_mbx_rq_create { 1184 struct mbox_header header; 1185 union { 1186 struct { 1187 uint32_t word0; 1188 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1189 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1190 #define lpfc_mbx_rq_create_num_pages_WORD word0 1191 struct rq_context context; 1192 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1193 } request; 1194 struct { 1195 uint32_t word0; 1196 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1197 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1198 #define lpfc_mbx_rq_create_q_id_WORD word0 1199 } response; 1200 } u; 1201 }; 1202 1203 struct lpfc_mbx_rq_destroy { 1204 struct mbox_header header; 1205 union { 1206 struct { 1207 uint32_t word0; 1208 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1209 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1210 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1211 } request; 1212 struct { 1213 uint32_t word0; 1214 } response; 1215 } u; 1216 }; 1217 1218 struct mq_context { 1219 uint32_t word0; 1220 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1221 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1222 #define lpfc_mq_context_cq_id_WORD word0 1223 #define lpfc_mq_context_ring_size_SHIFT 16 1224 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1225 #define lpfc_mq_context_ring_size_WORD word0 1226 #define LPFC_MQ_RING_SIZE_16 0x5 1227 #define LPFC_MQ_RING_SIZE_32 0x6 1228 #define LPFC_MQ_RING_SIZE_64 0x7 1229 #define LPFC_MQ_RING_SIZE_128 0x8 1230 uint32_t word1; 1231 #define lpfc_mq_context_valid_SHIFT 31 1232 #define lpfc_mq_context_valid_MASK 0x00000001 1233 #define lpfc_mq_context_valid_WORD word1 1234 uint32_t reserved2; 1235 uint32_t reserved3; 1236 }; 1237 1238 struct lpfc_mbx_mq_create { 1239 struct mbox_header header; 1240 union { 1241 struct { 1242 uint32_t word0; 1243 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1244 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1245 #define lpfc_mbx_mq_create_num_pages_WORD word0 1246 struct mq_context context; 1247 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1248 } request; 1249 struct { 1250 uint32_t word0; 1251 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1252 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1253 #define lpfc_mbx_mq_create_q_id_WORD word0 1254 } response; 1255 } u; 1256 }; 1257 1258 struct lpfc_mbx_mq_create_ext { 1259 struct mbox_header header; 1260 union { 1261 struct { 1262 uint32_t word0; 1263 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1264 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1265 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1266 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1267 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1268 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1269 uint32_t async_evt_bmap; 1270 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1271 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1272 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1273 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1274 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1275 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1276 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1277 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1278 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1279 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1280 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1281 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1282 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1283 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1284 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1285 struct mq_context context; 1286 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1287 } request; 1288 struct { 1289 uint32_t word0; 1290 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1291 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1292 #define lpfc_mbx_mq_create_q_id_WORD word0 1293 } response; 1294 } u; 1295 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1296 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1297 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1298 }; 1299 1300 struct lpfc_mbx_mq_destroy { 1301 struct mbox_header header; 1302 union { 1303 struct { 1304 uint32_t word0; 1305 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1306 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1307 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1308 } request; 1309 struct { 1310 uint32_t word0; 1311 } response; 1312 } u; 1313 }; 1314 1315 /* Start Gen 2 SLI4 Mailbox definitions: */ 1316 1317 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1318 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1319 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1320 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1321 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1322 1323 struct lpfc_mbx_get_rsrc_extent_info { 1324 struct mbox_header header; 1325 union { 1326 struct { 1327 uint32_t word4; 1328 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1329 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1330 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1331 } req; 1332 struct { 1333 uint32_t word4; 1334 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1335 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1336 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1337 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1338 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1339 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1340 } rsp; 1341 } u; 1342 }; 1343 1344 struct lpfc_id_range { 1345 uint32_t word5; 1346 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1347 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1348 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1349 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1350 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1351 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1352 }; 1353 1354 struct lpfc_mbx_set_link_diag_state { 1355 struct mbox_header header; 1356 union { 1357 struct { 1358 uint32_t word0; 1359 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1360 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1361 #define lpfc_mbx_set_diag_state_diag_WORD word0 1362 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1363 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1364 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1365 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1366 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1367 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1368 } req; 1369 struct { 1370 uint32_t word0; 1371 } rsp; 1372 } u; 1373 }; 1374 1375 struct lpfc_mbx_set_link_diag_loopback { 1376 struct mbox_header header; 1377 union { 1378 struct { 1379 uint32_t word0; 1380 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1381 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1382 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1383 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1384 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1385 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1386 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1387 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1388 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1389 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1390 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1391 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1392 } req; 1393 struct { 1394 uint32_t word0; 1395 } rsp; 1396 } u; 1397 }; 1398 1399 struct lpfc_mbx_run_link_diag_test { 1400 struct mbox_header header; 1401 union { 1402 struct { 1403 uint32_t word0; 1404 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1405 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1406 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1407 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1408 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1409 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1410 uint32_t word1; 1411 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1412 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1413 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1414 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1415 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1416 #define lpfc_mbx_run_diag_test_loops_WORD word1 1417 uint32_t word2; 1418 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1419 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1420 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1421 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1422 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1423 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1424 } req; 1425 struct { 1426 uint32_t word0; 1427 } rsp; 1428 } u; 1429 }; 1430 1431 /* 1432 * struct lpfc_mbx_alloc_rsrc_extents: 1433 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1434 * 6 words of header + 4 words of shared subcommand header + 1435 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1436 * 1437 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1438 * for extents payload. 1439 * 1440 * 212/2 (bytes per extent) = 106 extents. 1441 * 106/2 (extents per word) = 53 words. 1442 * lpfc_id_range id is statically size to 53. 1443 * 1444 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1445 * extent ranges. For ALLOC, the type and cnt are required. 1446 * For GET_ALLOCATED, only the type is required. 1447 */ 1448 struct lpfc_mbx_alloc_rsrc_extents { 1449 struct mbox_header header; 1450 union { 1451 struct { 1452 uint32_t word4; 1453 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1454 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1455 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1456 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1457 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1458 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1459 } req; 1460 struct { 1461 uint32_t word4; 1462 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1463 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1464 #define lpfc_mbx_rsrc_cnt_WORD word4 1465 struct lpfc_id_range id[53]; 1466 } rsp; 1467 } u; 1468 }; 1469 1470 /* 1471 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1472 * structure shares the same SHIFT/MASK/WORD defines provided in the 1473 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1474 * the structures defined above. This non-embedded structure provides for the 1475 * maximum number of extents supported by the port. 1476 */ 1477 struct lpfc_mbx_nembed_rsrc_extent { 1478 union lpfc_sli4_cfg_shdr cfg_shdr; 1479 uint32_t word4; 1480 struct lpfc_id_range id; 1481 }; 1482 1483 struct lpfc_mbx_dealloc_rsrc_extents { 1484 struct mbox_header header; 1485 struct { 1486 uint32_t word4; 1487 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1488 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1489 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1490 } req; 1491 1492 }; 1493 1494 /* Start SLI4 FCoE specific mbox structures. */ 1495 1496 struct lpfc_mbx_post_hdr_tmpl { 1497 struct mbox_header header; 1498 uint32_t word10; 1499 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1500 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1501 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1502 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1503 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1504 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1505 uint32_t rpi_paddr_lo; 1506 uint32_t rpi_paddr_hi; 1507 }; 1508 1509 struct sli4_sge { /* SLI-4 */ 1510 uint32_t addr_hi; 1511 uint32_t addr_lo; 1512 1513 uint32_t word2; 1514 #define lpfc_sli4_sge_offset_SHIFT 0 1515 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1516 #define lpfc_sli4_sge_offset_WORD word2 1517 #define lpfc_sli4_sge_type_SHIFT 27 1518 #define lpfc_sli4_sge_type_MASK 0x0000000F 1519 #define lpfc_sli4_sge_type_WORD word2 1520 #define LPFC_SGE_TYPE_DATA 0x0 1521 #define LPFC_SGE_TYPE_DIF 0x4 1522 #define LPFC_SGE_TYPE_LSP 0x5 1523 #define LPFC_SGE_TYPE_PEDIF 0x6 1524 #define LPFC_SGE_TYPE_PESEED 0x7 1525 #define LPFC_SGE_TYPE_DISEED 0x8 1526 #define LPFC_SGE_TYPE_ENC 0x9 1527 #define LPFC_SGE_TYPE_ATM 0xA 1528 #define LPFC_SGE_TYPE_SKIP 0xC 1529 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1530 #define lpfc_sli4_sge_last_MASK 0x00000001 1531 #define lpfc_sli4_sge_last_WORD word2 1532 uint32_t sge_len; 1533 }; 1534 1535 struct sli4_sge_diseed { /* SLI-4 */ 1536 uint32_t ref_tag; 1537 uint32_t ref_tag_tran; 1538 1539 uint32_t word2; 1540 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1541 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1542 #define lpfc_sli4_sge_dif_apptran_WORD word2 1543 #define lpfc_sli4_sge_dif_af_SHIFT 24 1544 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1545 #define lpfc_sli4_sge_dif_af_WORD word2 1546 #define lpfc_sli4_sge_dif_na_SHIFT 25 1547 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1548 #define lpfc_sli4_sge_dif_na_WORD word2 1549 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1550 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1551 #define lpfc_sli4_sge_dif_hi_WORD word2 1552 #define lpfc_sli4_sge_dif_type_SHIFT 27 1553 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1554 #define lpfc_sli4_sge_dif_type_WORD word2 1555 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1556 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1557 #define lpfc_sli4_sge_dif_last_WORD word2 1558 uint32_t word3; 1559 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1560 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1561 #define lpfc_sli4_sge_dif_apptag_WORD word3 1562 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1563 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1564 #define lpfc_sli4_sge_dif_bs_WORD word3 1565 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1566 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1567 #define lpfc_sli4_sge_dif_ai_WORD word3 1568 #define lpfc_sli4_sge_dif_me_SHIFT 20 1569 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1570 #define lpfc_sli4_sge_dif_me_WORD word3 1571 #define lpfc_sli4_sge_dif_re_SHIFT 21 1572 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1573 #define lpfc_sli4_sge_dif_re_WORD word3 1574 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1575 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1576 #define lpfc_sli4_sge_dif_ce_WORD word3 1577 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1578 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1579 #define lpfc_sli4_sge_dif_nr_WORD word3 1580 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1581 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1582 #define lpfc_sli4_sge_dif_oprx_WORD word3 1583 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1584 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1585 #define lpfc_sli4_sge_dif_optx_WORD word3 1586 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1587 }; 1588 1589 struct fcf_record { 1590 uint32_t max_rcv_size; 1591 uint32_t fka_adv_period; 1592 uint32_t fip_priority; 1593 uint32_t word3; 1594 #define lpfc_fcf_record_mac_0_SHIFT 0 1595 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1596 #define lpfc_fcf_record_mac_0_WORD word3 1597 #define lpfc_fcf_record_mac_1_SHIFT 8 1598 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1599 #define lpfc_fcf_record_mac_1_WORD word3 1600 #define lpfc_fcf_record_mac_2_SHIFT 16 1601 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1602 #define lpfc_fcf_record_mac_2_WORD word3 1603 #define lpfc_fcf_record_mac_3_SHIFT 24 1604 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1605 #define lpfc_fcf_record_mac_3_WORD word3 1606 uint32_t word4; 1607 #define lpfc_fcf_record_mac_4_SHIFT 0 1608 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1609 #define lpfc_fcf_record_mac_4_WORD word4 1610 #define lpfc_fcf_record_mac_5_SHIFT 8 1611 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1612 #define lpfc_fcf_record_mac_5_WORD word4 1613 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1614 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1615 #define lpfc_fcf_record_fcf_avail_WORD word4 1616 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1617 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1618 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1619 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1620 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1621 uint32_t word5; 1622 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1623 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1624 #define lpfc_fcf_record_fab_name_0_WORD word5 1625 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1626 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1627 #define lpfc_fcf_record_fab_name_1_WORD word5 1628 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1629 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1630 #define lpfc_fcf_record_fab_name_2_WORD word5 1631 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1632 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1633 #define lpfc_fcf_record_fab_name_3_WORD word5 1634 uint32_t word6; 1635 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1636 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1637 #define lpfc_fcf_record_fab_name_4_WORD word6 1638 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1639 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1640 #define lpfc_fcf_record_fab_name_5_WORD word6 1641 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1642 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1643 #define lpfc_fcf_record_fab_name_6_WORD word6 1644 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1645 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1646 #define lpfc_fcf_record_fab_name_7_WORD word6 1647 uint32_t word7; 1648 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1649 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1650 #define lpfc_fcf_record_fc_map_0_WORD word7 1651 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1652 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1653 #define lpfc_fcf_record_fc_map_1_WORD word7 1654 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1655 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1656 #define lpfc_fcf_record_fc_map_2_WORD word7 1657 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1658 #define lpfc_fcf_record_fcf_valid_MASK 0x000000FF 1659 #define lpfc_fcf_record_fcf_valid_WORD word7 1660 uint32_t word8; 1661 #define lpfc_fcf_record_fcf_index_SHIFT 0 1662 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1663 #define lpfc_fcf_record_fcf_index_WORD word8 1664 #define lpfc_fcf_record_fcf_state_SHIFT 16 1665 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1666 #define lpfc_fcf_record_fcf_state_WORD word8 1667 uint8_t vlan_bitmap[512]; 1668 uint32_t word137; 1669 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1670 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1671 #define lpfc_fcf_record_switch_name_0_WORD word137 1672 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1673 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1674 #define lpfc_fcf_record_switch_name_1_WORD word137 1675 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1676 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1677 #define lpfc_fcf_record_switch_name_2_WORD word137 1678 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1679 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1680 #define lpfc_fcf_record_switch_name_3_WORD word137 1681 uint32_t word138; 1682 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1683 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1684 #define lpfc_fcf_record_switch_name_4_WORD word138 1685 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1686 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1687 #define lpfc_fcf_record_switch_name_5_WORD word138 1688 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1689 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1690 #define lpfc_fcf_record_switch_name_6_WORD word138 1691 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1692 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1693 #define lpfc_fcf_record_switch_name_7_WORD word138 1694 }; 1695 1696 struct lpfc_mbx_read_fcf_tbl { 1697 union lpfc_sli4_cfg_shdr cfg_shdr; 1698 union { 1699 struct { 1700 uint32_t word10; 1701 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1702 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1703 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1704 } request; 1705 struct { 1706 uint32_t eventag; 1707 } response; 1708 } u; 1709 uint32_t word11; 1710 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1711 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1712 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1713 }; 1714 1715 struct lpfc_mbx_add_fcf_tbl_entry { 1716 union lpfc_sli4_cfg_shdr cfg_shdr; 1717 uint32_t word10; 1718 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1719 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1720 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1721 struct lpfc_mbx_sge fcf_sge; 1722 }; 1723 1724 struct lpfc_mbx_del_fcf_tbl_entry { 1725 struct mbox_header header; 1726 uint32_t word10; 1727 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1728 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1729 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1730 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1731 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1732 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1733 }; 1734 1735 struct lpfc_mbx_redisc_fcf_tbl { 1736 struct mbox_header header; 1737 uint32_t word10; 1738 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1739 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1740 #define lpfc_mbx_redisc_fcf_count_WORD word10 1741 uint32_t resvd; 1742 uint32_t word12; 1743 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1744 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1745 #define lpfc_mbx_redisc_fcf_index_WORD word12 1746 }; 1747 1748 struct lpfc_mbx_query_fw_cfg { 1749 struct mbox_header header; 1750 uint32_t config_number; 1751 uint32_t asic_rev; 1752 uint32_t phys_port; 1753 uint32_t function_mode; 1754 /* firmware Function Mode */ 1755 #define lpfc_function_mode_toe_SHIFT 0 1756 #define lpfc_function_mode_toe_MASK 0x00000001 1757 #define lpfc_function_mode_toe_WORD function_mode 1758 #define lpfc_function_mode_nic_SHIFT 1 1759 #define lpfc_function_mode_nic_MASK 0x00000001 1760 #define lpfc_function_mode_nic_WORD function_mode 1761 #define lpfc_function_mode_rdma_SHIFT 2 1762 #define lpfc_function_mode_rdma_MASK 0x00000001 1763 #define lpfc_function_mode_rdma_WORD function_mode 1764 #define lpfc_function_mode_vm_SHIFT 3 1765 #define lpfc_function_mode_vm_MASK 0x00000001 1766 #define lpfc_function_mode_vm_WORD function_mode 1767 #define lpfc_function_mode_iscsi_i_SHIFT 4 1768 #define lpfc_function_mode_iscsi_i_MASK 0x00000001 1769 #define lpfc_function_mode_iscsi_i_WORD function_mode 1770 #define lpfc_function_mode_iscsi_t_SHIFT 5 1771 #define lpfc_function_mode_iscsi_t_MASK 0x00000001 1772 #define lpfc_function_mode_iscsi_t_WORD function_mode 1773 #define lpfc_function_mode_fcoe_i_SHIFT 6 1774 #define lpfc_function_mode_fcoe_i_MASK 0x00000001 1775 #define lpfc_function_mode_fcoe_i_WORD function_mode 1776 #define lpfc_function_mode_fcoe_t_SHIFT 7 1777 #define lpfc_function_mode_fcoe_t_MASK 0x00000001 1778 #define lpfc_function_mode_fcoe_t_WORD function_mode 1779 #define lpfc_function_mode_dal_SHIFT 8 1780 #define lpfc_function_mode_dal_MASK 0x00000001 1781 #define lpfc_function_mode_dal_WORD function_mode 1782 #define lpfc_function_mode_lro_SHIFT 9 1783 #define lpfc_function_mode_lro_MASK 0x00000001 1784 #define lpfc_function_mode_lro_WORD function_mode 1785 #define lpfc_function_mode_flex10_SHIFT 10 1786 #define lpfc_function_mode_flex10_MASK 0x00000001 1787 #define lpfc_function_mode_flex10_WORD function_mode 1788 #define lpfc_function_mode_ncsi_SHIFT 11 1789 #define lpfc_function_mode_ncsi_MASK 0x00000001 1790 #define lpfc_function_mode_ncsi_WORD function_mode 1791 }; 1792 1793 /* Status field for embedded SLI_CONFIG mailbox command */ 1794 #define STATUS_SUCCESS 0x0 1795 #define STATUS_FAILED 0x1 1796 #define STATUS_ILLEGAL_REQUEST 0x2 1797 #define STATUS_ILLEGAL_FIELD 0x3 1798 #define STATUS_INSUFFICIENT_BUFFER 0x4 1799 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1800 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1801 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1802 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1803 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1804 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1805 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1806 #define STATUS_ASSERT_FAILED 0x1e 1807 #define STATUS_INVALID_SESSION 0x1f 1808 #define STATUS_INVALID_CONNECTION 0x20 1809 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1810 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1811 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1812 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1813 #define STATUS_FLASHROM_READ_FAILED 0x27 1814 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1815 #define STATUS_ERROR_ACITMAIN 0x2a 1816 #define STATUS_REBOOT_REQUIRED 0x2c 1817 #define STATUS_FCF_IN_USE 0x3a 1818 #define STATUS_FCF_TABLE_EMPTY 0x43 1819 1820 struct lpfc_mbx_sli4_config { 1821 struct mbox_header header; 1822 }; 1823 1824 struct lpfc_mbx_init_vfi { 1825 uint32_t word1; 1826 #define lpfc_init_vfi_vr_SHIFT 31 1827 #define lpfc_init_vfi_vr_MASK 0x00000001 1828 #define lpfc_init_vfi_vr_WORD word1 1829 #define lpfc_init_vfi_vt_SHIFT 30 1830 #define lpfc_init_vfi_vt_MASK 0x00000001 1831 #define lpfc_init_vfi_vt_WORD word1 1832 #define lpfc_init_vfi_vf_SHIFT 29 1833 #define lpfc_init_vfi_vf_MASK 0x00000001 1834 #define lpfc_init_vfi_vf_WORD word1 1835 #define lpfc_init_vfi_vp_SHIFT 28 1836 #define lpfc_init_vfi_vp_MASK 0x00000001 1837 #define lpfc_init_vfi_vp_WORD word1 1838 #define lpfc_init_vfi_vfi_SHIFT 0 1839 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1840 #define lpfc_init_vfi_vfi_WORD word1 1841 uint32_t word2; 1842 #define lpfc_init_vfi_vpi_SHIFT 16 1843 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1844 #define lpfc_init_vfi_vpi_WORD word2 1845 #define lpfc_init_vfi_fcfi_SHIFT 0 1846 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1847 #define lpfc_init_vfi_fcfi_WORD word2 1848 uint32_t word3; 1849 #define lpfc_init_vfi_pri_SHIFT 13 1850 #define lpfc_init_vfi_pri_MASK 0x00000007 1851 #define lpfc_init_vfi_pri_WORD word3 1852 #define lpfc_init_vfi_vf_id_SHIFT 1 1853 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1854 #define lpfc_init_vfi_vf_id_WORD word3 1855 uint32_t word4; 1856 #define lpfc_init_vfi_hop_count_SHIFT 24 1857 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1858 #define lpfc_init_vfi_hop_count_WORD word4 1859 }; 1860 #define MBX_VFI_IN_USE 0x9F02 1861 1862 1863 struct lpfc_mbx_reg_vfi { 1864 uint32_t word1; 1865 #define lpfc_reg_vfi_vp_SHIFT 28 1866 #define lpfc_reg_vfi_vp_MASK 0x00000001 1867 #define lpfc_reg_vfi_vp_WORD word1 1868 #define lpfc_reg_vfi_vfi_SHIFT 0 1869 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1870 #define lpfc_reg_vfi_vfi_WORD word1 1871 uint32_t word2; 1872 #define lpfc_reg_vfi_vpi_SHIFT 16 1873 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1874 #define lpfc_reg_vfi_vpi_WORD word2 1875 #define lpfc_reg_vfi_fcfi_SHIFT 0 1876 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1877 #define lpfc_reg_vfi_fcfi_WORD word2 1878 uint32_t wwn[2]; 1879 struct ulp_bde64 bde; 1880 uint32_t e_d_tov; 1881 uint32_t r_a_tov; 1882 uint32_t word10; 1883 #define lpfc_reg_vfi_nport_id_SHIFT 0 1884 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1885 #define lpfc_reg_vfi_nport_id_WORD word10 1886 }; 1887 1888 struct lpfc_mbx_init_vpi { 1889 uint32_t word1; 1890 #define lpfc_init_vpi_vfi_SHIFT 16 1891 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1892 #define lpfc_init_vpi_vfi_WORD word1 1893 #define lpfc_init_vpi_vpi_SHIFT 0 1894 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 1895 #define lpfc_init_vpi_vpi_WORD word1 1896 }; 1897 1898 struct lpfc_mbx_read_vpi { 1899 uint32_t word1_rsvd; 1900 uint32_t word2; 1901 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 1902 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 1903 #define lpfc_mbx_read_vpi_vnportid_WORD word2 1904 uint32_t word3_rsvd; 1905 uint32_t word4; 1906 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 1907 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 1908 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 1909 #define lpfc_mbx_read_vpi_pb_SHIFT 15 1910 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 1911 #define lpfc_mbx_read_vpi_pb_WORD word4 1912 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 1913 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 1914 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 1915 #define lpfc_mbx_read_vpi_ns_SHIFT 30 1916 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 1917 #define lpfc_mbx_read_vpi_ns_WORD word4 1918 #define lpfc_mbx_read_vpi_hl_SHIFT 31 1919 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 1920 #define lpfc_mbx_read_vpi_hl_WORD word4 1921 uint32_t word5_rsvd; 1922 uint32_t word6; 1923 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 1924 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 1925 #define lpfc_mbx_read_vpi_vpi_WORD word6 1926 uint32_t word7; 1927 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 1928 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 1929 #define lpfc_mbx_read_vpi_mac_0_WORD word7 1930 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 1931 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 1932 #define lpfc_mbx_read_vpi_mac_1_WORD word7 1933 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 1934 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 1935 #define lpfc_mbx_read_vpi_mac_2_WORD word7 1936 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 1937 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 1938 #define lpfc_mbx_read_vpi_mac_3_WORD word7 1939 uint32_t word8; 1940 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 1941 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 1942 #define lpfc_mbx_read_vpi_mac_4_WORD word8 1943 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 1944 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 1945 #define lpfc_mbx_read_vpi_mac_5_WORD word8 1946 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 1947 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 1948 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 1949 #define lpfc_mbx_read_vpi_vv_SHIFT 28 1950 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 1951 #define lpfc_mbx_read_vpi_vv_WORD word8 1952 }; 1953 1954 struct lpfc_mbx_unreg_vfi { 1955 uint32_t word1_rsvd; 1956 uint32_t word2; 1957 #define lpfc_unreg_vfi_vfi_SHIFT 0 1958 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 1959 #define lpfc_unreg_vfi_vfi_WORD word2 1960 }; 1961 1962 struct lpfc_mbx_resume_rpi { 1963 uint32_t word1; 1964 #define lpfc_resume_rpi_index_SHIFT 0 1965 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 1966 #define lpfc_resume_rpi_index_WORD word1 1967 #define lpfc_resume_rpi_ii_SHIFT 30 1968 #define lpfc_resume_rpi_ii_MASK 0x00000003 1969 #define lpfc_resume_rpi_ii_WORD word1 1970 #define RESUME_INDEX_RPI 0 1971 #define RESUME_INDEX_VPI 1 1972 #define RESUME_INDEX_VFI 2 1973 #define RESUME_INDEX_FCFI 3 1974 uint32_t event_tag; 1975 }; 1976 1977 #define REG_FCF_INVALID_QID 0xFFFF 1978 struct lpfc_mbx_reg_fcfi { 1979 uint32_t word1; 1980 #define lpfc_reg_fcfi_info_index_SHIFT 0 1981 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 1982 #define lpfc_reg_fcfi_info_index_WORD word1 1983 #define lpfc_reg_fcfi_fcfi_SHIFT 16 1984 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 1985 #define lpfc_reg_fcfi_fcfi_WORD word1 1986 uint32_t word2; 1987 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 1988 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 1989 #define lpfc_reg_fcfi_rq_id1_WORD word2 1990 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 1991 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 1992 #define lpfc_reg_fcfi_rq_id0_WORD word2 1993 uint32_t word3; 1994 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 1995 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 1996 #define lpfc_reg_fcfi_rq_id3_WORD word3 1997 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 1998 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 1999 #define lpfc_reg_fcfi_rq_id2_WORD word3 2000 uint32_t word4; 2001 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2002 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2003 #define lpfc_reg_fcfi_type_match0_WORD word4 2004 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2005 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2006 #define lpfc_reg_fcfi_type_mask0_WORD word4 2007 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2008 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2009 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2010 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2011 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2012 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2013 uint32_t word5; 2014 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2015 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2016 #define lpfc_reg_fcfi_type_match1_WORD word5 2017 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2018 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2019 #define lpfc_reg_fcfi_type_mask1_WORD word5 2020 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2021 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2022 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2023 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2024 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2025 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2026 uint32_t word6; 2027 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2028 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2029 #define lpfc_reg_fcfi_type_match2_WORD word6 2030 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2031 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2032 #define lpfc_reg_fcfi_type_mask2_WORD word6 2033 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2034 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2035 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2036 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2037 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2038 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2039 uint32_t word7; 2040 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2041 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2042 #define lpfc_reg_fcfi_type_match3_WORD word7 2043 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2044 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2045 #define lpfc_reg_fcfi_type_mask3_WORD word7 2046 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2047 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2048 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2049 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2050 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2051 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2052 uint32_t word8; 2053 #define lpfc_reg_fcfi_mam_SHIFT 13 2054 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2055 #define lpfc_reg_fcfi_mam_WORD word8 2056 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2057 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2058 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2059 #define lpfc_reg_fcfi_vv_SHIFT 12 2060 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2061 #define lpfc_reg_fcfi_vv_WORD word8 2062 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2063 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2064 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2065 }; 2066 2067 struct lpfc_mbx_unreg_fcfi { 2068 uint32_t word1_rsv; 2069 uint32_t word2; 2070 #define lpfc_unreg_fcfi_SHIFT 0 2071 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2072 #define lpfc_unreg_fcfi_WORD word2 2073 }; 2074 2075 struct lpfc_mbx_read_rev { 2076 uint32_t word1; 2077 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2078 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2079 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2080 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2081 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2082 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2083 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2084 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2085 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2086 #define LPFC_PREDCBX_CEE_MODE 0 2087 #define LPFC_DCBX_CEE_MODE 1 2088 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2089 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2090 #define lpfc_mbx_rd_rev_vpd_WORD word1 2091 uint32_t first_hw_rev; 2092 uint32_t second_hw_rev; 2093 uint32_t word4_rsvd; 2094 uint32_t third_hw_rev; 2095 uint32_t word6; 2096 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2097 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2098 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2099 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2100 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2101 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2102 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2103 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2104 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2105 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2106 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2107 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2108 uint32_t word7_rsvd; 2109 uint32_t fw_id_rev; 2110 uint8_t fw_name[16]; 2111 uint32_t ulp_fw_id_rev; 2112 uint8_t ulp_fw_name[16]; 2113 uint32_t word18_47_rsvd[30]; 2114 uint32_t word48; 2115 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2116 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2117 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2118 uint32_t vpd_paddr_low; 2119 uint32_t vpd_paddr_high; 2120 uint32_t avail_vpd_len; 2121 uint32_t rsvd_52_63[12]; 2122 }; 2123 2124 struct lpfc_mbx_read_config { 2125 uint32_t word1; 2126 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2127 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2128 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2129 uint32_t word2; 2130 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2131 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2132 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2133 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2134 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2135 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2136 #define LPFC_LNK_TYPE_GE 0 2137 #define LPFC_LNK_TYPE_FC 1 2138 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2139 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2140 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2141 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2142 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2143 #define lpfc_mbx_rd_conf_topology_WORD word2 2144 uint32_t rsvd_3; 2145 uint32_t word4; 2146 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2147 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2148 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2149 uint32_t rsvd_5; 2150 uint32_t word6; 2151 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2152 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2153 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2154 uint32_t rsvd_7; 2155 uint32_t rsvd_8; 2156 uint32_t word9; 2157 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2158 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2159 #define lpfc_mbx_rd_conf_lmt_WORD word9 2160 uint32_t rsvd_10; 2161 uint32_t rsvd_11; 2162 uint32_t word12; 2163 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2164 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2165 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2166 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2167 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2168 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2169 uint32_t word13; 2170 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2171 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2172 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2173 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2174 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2175 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2176 uint32_t word14; 2177 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2178 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2179 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2180 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2181 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2182 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2183 uint32_t word15; 2184 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2185 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2186 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2187 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2188 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2189 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2190 uint32_t word16; 2191 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2192 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2193 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2194 uint32_t word17; 2195 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2196 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2197 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2198 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2199 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2200 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2201 uint32_t word18; 2202 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2203 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2204 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2205 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2206 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2207 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2208 }; 2209 2210 struct lpfc_mbx_request_features { 2211 uint32_t word1; 2212 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2213 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2214 #define lpfc_mbx_rq_ftr_qry_WORD word1 2215 uint32_t word2; 2216 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2217 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2218 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2219 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2220 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2221 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2222 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2223 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2224 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2225 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2226 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2227 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2228 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2229 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2230 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2231 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2232 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2233 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2234 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2235 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2236 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2237 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2238 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2239 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2240 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2241 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2242 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2243 uint32_t word3; 2244 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2245 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2246 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2247 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2248 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2249 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2250 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2251 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2252 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2253 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2254 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2255 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2256 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2257 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2258 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2259 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2260 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2261 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2262 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2263 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2264 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2265 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2266 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2267 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2268 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2269 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2270 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2271 }; 2272 2273 struct lpfc_mbx_supp_pages { 2274 uint32_t word1; 2275 #define qs_SHIFT 0 2276 #define qs_MASK 0x00000001 2277 #define qs_WORD word1 2278 #define wr_SHIFT 1 2279 #define wr_MASK 0x00000001 2280 #define wr_WORD word1 2281 #define pf_SHIFT 8 2282 #define pf_MASK 0x000000ff 2283 #define pf_WORD word1 2284 #define cpn_SHIFT 16 2285 #define cpn_MASK 0x000000ff 2286 #define cpn_WORD word1 2287 uint32_t word2; 2288 #define list_offset_SHIFT 0 2289 #define list_offset_MASK 0x000000ff 2290 #define list_offset_WORD word2 2291 #define next_offset_SHIFT 8 2292 #define next_offset_MASK 0x000000ff 2293 #define next_offset_WORD word2 2294 #define elem_cnt_SHIFT 16 2295 #define elem_cnt_MASK 0x000000ff 2296 #define elem_cnt_WORD word2 2297 uint32_t word3; 2298 #define pn_0_SHIFT 24 2299 #define pn_0_MASK 0x000000ff 2300 #define pn_0_WORD word3 2301 #define pn_1_SHIFT 16 2302 #define pn_1_MASK 0x000000ff 2303 #define pn_1_WORD word3 2304 #define pn_2_SHIFT 8 2305 #define pn_2_MASK 0x000000ff 2306 #define pn_2_WORD word3 2307 #define pn_3_SHIFT 0 2308 #define pn_3_MASK 0x000000ff 2309 #define pn_3_WORD word3 2310 uint32_t word4; 2311 #define pn_4_SHIFT 24 2312 #define pn_4_MASK 0x000000ff 2313 #define pn_4_WORD word4 2314 #define pn_5_SHIFT 16 2315 #define pn_5_MASK 0x000000ff 2316 #define pn_5_WORD word4 2317 #define pn_6_SHIFT 8 2318 #define pn_6_MASK 0x000000ff 2319 #define pn_6_WORD word4 2320 #define pn_7_SHIFT 0 2321 #define pn_7_MASK 0x000000ff 2322 #define pn_7_WORD word4 2323 uint32_t rsvd[27]; 2324 #define LPFC_SUPP_PAGES 0 2325 #define LPFC_BLOCK_GUARD_PROFILES 1 2326 #define LPFC_SLI4_PARAMETERS 2 2327 }; 2328 2329 struct lpfc_mbx_pc_sli4_params { 2330 uint32_t word1; 2331 #define qs_SHIFT 0 2332 #define qs_MASK 0x00000001 2333 #define qs_WORD word1 2334 #define wr_SHIFT 1 2335 #define wr_MASK 0x00000001 2336 #define wr_WORD word1 2337 #define pf_SHIFT 8 2338 #define pf_MASK 0x000000ff 2339 #define pf_WORD word1 2340 #define cpn_SHIFT 16 2341 #define cpn_MASK 0x000000ff 2342 #define cpn_WORD word1 2343 uint32_t word2; 2344 #define if_type_SHIFT 0 2345 #define if_type_MASK 0x00000007 2346 #define if_type_WORD word2 2347 #define sli_rev_SHIFT 4 2348 #define sli_rev_MASK 0x0000000f 2349 #define sli_rev_WORD word2 2350 #define sli_family_SHIFT 8 2351 #define sli_family_MASK 0x000000ff 2352 #define sli_family_WORD word2 2353 #define featurelevel_1_SHIFT 16 2354 #define featurelevel_1_MASK 0x000000ff 2355 #define featurelevel_1_WORD word2 2356 #define featurelevel_2_SHIFT 24 2357 #define featurelevel_2_MASK 0x0000001f 2358 #define featurelevel_2_WORD word2 2359 uint32_t word3; 2360 #define fcoe_SHIFT 0 2361 #define fcoe_MASK 0x00000001 2362 #define fcoe_WORD word3 2363 #define fc_SHIFT 1 2364 #define fc_MASK 0x00000001 2365 #define fc_WORD word3 2366 #define nic_SHIFT 2 2367 #define nic_MASK 0x00000001 2368 #define nic_WORD word3 2369 #define iscsi_SHIFT 3 2370 #define iscsi_MASK 0x00000001 2371 #define iscsi_WORD word3 2372 #define rdma_SHIFT 4 2373 #define rdma_MASK 0x00000001 2374 #define rdma_WORD word3 2375 uint32_t sge_supp_len; 2376 #define SLI4_PAGE_SIZE 4096 2377 uint32_t word5; 2378 #define if_page_sz_SHIFT 0 2379 #define if_page_sz_MASK 0x0000ffff 2380 #define if_page_sz_WORD word5 2381 #define loopbk_scope_SHIFT 24 2382 #define loopbk_scope_MASK 0x0000000f 2383 #define loopbk_scope_WORD word5 2384 #define rq_db_window_SHIFT 28 2385 #define rq_db_window_MASK 0x0000000f 2386 #define rq_db_window_WORD word5 2387 uint32_t word6; 2388 #define eq_pages_SHIFT 0 2389 #define eq_pages_MASK 0x0000000f 2390 #define eq_pages_WORD word6 2391 #define eqe_size_SHIFT 8 2392 #define eqe_size_MASK 0x000000ff 2393 #define eqe_size_WORD word6 2394 uint32_t word7; 2395 #define cq_pages_SHIFT 0 2396 #define cq_pages_MASK 0x0000000f 2397 #define cq_pages_WORD word7 2398 #define cqe_size_SHIFT 8 2399 #define cqe_size_MASK 0x000000ff 2400 #define cqe_size_WORD word7 2401 uint32_t word8; 2402 #define mq_pages_SHIFT 0 2403 #define mq_pages_MASK 0x0000000f 2404 #define mq_pages_WORD word8 2405 #define mqe_size_SHIFT 8 2406 #define mqe_size_MASK 0x000000ff 2407 #define mqe_size_WORD word8 2408 #define mq_elem_cnt_SHIFT 16 2409 #define mq_elem_cnt_MASK 0x000000ff 2410 #define mq_elem_cnt_WORD word8 2411 uint32_t word9; 2412 #define wq_pages_SHIFT 0 2413 #define wq_pages_MASK 0x0000ffff 2414 #define wq_pages_WORD word9 2415 #define wqe_size_SHIFT 8 2416 #define wqe_size_MASK 0x000000ff 2417 #define wqe_size_WORD word9 2418 uint32_t word10; 2419 #define rq_pages_SHIFT 0 2420 #define rq_pages_MASK 0x0000ffff 2421 #define rq_pages_WORD word10 2422 #define rqe_size_SHIFT 8 2423 #define rqe_size_MASK 0x000000ff 2424 #define rqe_size_WORD word10 2425 uint32_t word11; 2426 #define hdr_pages_SHIFT 0 2427 #define hdr_pages_MASK 0x0000000f 2428 #define hdr_pages_WORD word11 2429 #define hdr_size_SHIFT 8 2430 #define hdr_size_MASK 0x0000000f 2431 #define hdr_size_WORD word11 2432 #define hdr_pp_align_SHIFT 16 2433 #define hdr_pp_align_MASK 0x0000ffff 2434 #define hdr_pp_align_WORD word11 2435 uint32_t word12; 2436 #define sgl_pages_SHIFT 0 2437 #define sgl_pages_MASK 0x0000000f 2438 #define sgl_pages_WORD word12 2439 #define sgl_pp_align_SHIFT 16 2440 #define sgl_pp_align_MASK 0x0000ffff 2441 #define sgl_pp_align_WORD word12 2442 uint32_t rsvd_13_63[51]; 2443 }; 2444 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2445 &(~((SLI4_PAGE_SIZE)-1))) 2446 2447 struct lpfc_sli4_parameters { 2448 uint32_t word0; 2449 #define cfg_prot_type_SHIFT 0 2450 #define cfg_prot_type_MASK 0x000000FF 2451 #define cfg_prot_type_WORD word0 2452 uint32_t word1; 2453 #define cfg_ft_SHIFT 0 2454 #define cfg_ft_MASK 0x00000001 2455 #define cfg_ft_WORD word1 2456 #define cfg_sli_rev_SHIFT 4 2457 #define cfg_sli_rev_MASK 0x0000000f 2458 #define cfg_sli_rev_WORD word1 2459 #define cfg_sli_family_SHIFT 8 2460 #define cfg_sli_family_MASK 0x0000000f 2461 #define cfg_sli_family_WORD word1 2462 #define cfg_if_type_SHIFT 12 2463 #define cfg_if_type_MASK 0x0000000f 2464 #define cfg_if_type_WORD word1 2465 #define cfg_sli_hint_1_SHIFT 16 2466 #define cfg_sli_hint_1_MASK 0x000000ff 2467 #define cfg_sli_hint_1_WORD word1 2468 #define cfg_sli_hint_2_SHIFT 24 2469 #define cfg_sli_hint_2_MASK 0x0000001f 2470 #define cfg_sli_hint_2_WORD word1 2471 uint32_t word2; 2472 uint32_t word3; 2473 uint32_t word4; 2474 #define cfg_cqv_SHIFT 14 2475 #define cfg_cqv_MASK 0x00000003 2476 #define cfg_cqv_WORD word4 2477 uint32_t word5; 2478 uint32_t word6; 2479 #define cfg_mqv_SHIFT 14 2480 #define cfg_mqv_MASK 0x00000003 2481 #define cfg_mqv_WORD word6 2482 uint32_t word7; 2483 uint32_t word8; 2484 #define cfg_wqv_SHIFT 14 2485 #define cfg_wqv_MASK 0x00000003 2486 #define cfg_wqv_WORD word8 2487 uint32_t word9; 2488 uint32_t word10; 2489 #define cfg_rqv_SHIFT 14 2490 #define cfg_rqv_MASK 0x00000003 2491 #define cfg_rqv_WORD word10 2492 uint32_t word11; 2493 #define cfg_rq_db_window_SHIFT 28 2494 #define cfg_rq_db_window_MASK 0x0000000f 2495 #define cfg_rq_db_window_WORD word11 2496 uint32_t word12; 2497 #define cfg_fcoe_SHIFT 0 2498 #define cfg_fcoe_MASK 0x00000001 2499 #define cfg_fcoe_WORD word12 2500 #define cfg_ext_SHIFT 1 2501 #define cfg_ext_MASK 0x00000001 2502 #define cfg_ext_WORD word12 2503 #define cfg_hdrr_SHIFT 2 2504 #define cfg_hdrr_MASK 0x00000001 2505 #define cfg_hdrr_WORD word12 2506 #define cfg_phwq_SHIFT 15 2507 #define cfg_phwq_MASK 0x00000001 2508 #define cfg_phwq_WORD word12 2509 #define cfg_loopbk_scope_SHIFT 28 2510 #define cfg_loopbk_scope_MASK 0x0000000f 2511 #define cfg_loopbk_scope_WORD word12 2512 uint32_t sge_supp_len; 2513 uint32_t word14; 2514 #define cfg_sgl_page_cnt_SHIFT 0 2515 #define cfg_sgl_page_cnt_MASK 0x0000000f 2516 #define cfg_sgl_page_cnt_WORD word14 2517 #define cfg_sgl_page_size_SHIFT 8 2518 #define cfg_sgl_page_size_MASK 0x000000ff 2519 #define cfg_sgl_page_size_WORD word14 2520 #define cfg_sgl_pp_align_SHIFT 16 2521 #define cfg_sgl_pp_align_MASK 0x000000ff 2522 #define cfg_sgl_pp_align_WORD word14 2523 uint32_t word15; 2524 uint32_t word16; 2525 uint32_t word17; 2526 uint32_t word18; 2527 uint32_t word19; 2528 }; 2529 2530 struct lpfc_mbx_get_sli4_parameters { 2531 struct mbox_header header; 2532 struct lpfc_sli4_parameters sli4_parameters; 2533 }; 2534 2535 struct lpfc_rscr_desc_generic { 2536 #define LPFC_RSRC_DESC_WSIZE 18 2537 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2538 }; 2539 2540 struct lpfc_rsrc_desc_pcie { 2541 uint32_t word0; 2542 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2543 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2544 #define lpfc_rsrc_desc_pcie_type_WORD word0 2545 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2546 uint32_t word1; 2547 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2548 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2549 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2550 uint32_t reserved; 2551 uint32_t word3; 2552 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2553 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2554 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2555 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2556 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2557 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2558 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2559 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2560 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2561 uint32_t word4; 2562 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2563 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2564 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2565 }; 2566 2567 struct lpfc_rsrc_desc_fcfcoe { 2568 uint32_t word0; 2569 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2570 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2571 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2572 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2573 uint32_t word1; 2574 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2575 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2576 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2577 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2578 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2579 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2580 uint32_t word2; 2581 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2582 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2583 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2584 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2585 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2586 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2587 uint32_t word3; 2588 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2589 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2590 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2591 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2592 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2593 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2594 uint32_t word4; 2595 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2596 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2597 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2598 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2599 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2600 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2601 uint32_t word5; 2602 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2603 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2604 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2605 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2606 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2607 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2608 uint32_t word6; 2609 uint32_t word7; 2610 uint32_t word8; 2611 uint32_t word9; 2612 uint32_t word10; 2613 uint32_t word11; 2614 uint32_t word12; 2615 uint32_t word13; 2616 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2617 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2618 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2619 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2620 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2621 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2622 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2623 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2624 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2625 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2626 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2627 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2628 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 2629 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 2630 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 2631 }; 2632 2633 struct lpfc_func_cfg { 2634 #define LPFC_RSRC_DESC_MAX_NUM 2 2635 uint32_t rsrc_desc_count; 2636 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2637 }; 2638 2639 struct lpfc_mbx_get_func_cfg { 2640 struct mbox_header header; 2641 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2642 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2643 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2644 struct lpfc_func_cfg func_cfg; 2645 }; 2646 2647 struct lpfc_prof_cfg { 2648 #define LPFC_RSRC_DESC_MAX_NUM 2 2649 uint32_t rsrc_desc_count; 2650 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2651 }; 2652 2653 struct lpfc_mbx_get_prof_cfg { 2654 struct mbox_header header; 2655 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2656 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2657 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2658 union { 2659 struct { 2660 uint32_t word10; 2661 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 2662 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 2663 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 2664 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 2665 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 2666 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 2667 } request; 2668 struct { 2669 struct lpfc_prof_cfg prof_cfg; 2670 } response; 2671 } u; 2672 }; 2673 2674 struct lpfc_controller_attribute { 2675 uint32_t version_string[8]; 2676 uint32_t manufacturer_name[8]; 2677 uint32_t supported_modes; 2678 uint32_t word17; 2679 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 2680 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 2681 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 2682 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 2683 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 2684 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 2685 uint32_t mbx_da_struct_ver; 2686 uint32_t ep_fw_da_struct_ver; 2687 uint32_t ncsi_ver_str[3]; 2688 uint32_t dflt_ext_timeout; 2689 uint32_t model_number[8]; 2690 uint32_t description[16]; 2691 uint32_t serial_number[8]; 2692 uint32_t ip_ver_str[8]; 2693 uint32_t fw_ver_str[8]; 2694 uint32_t bios_ver_str[8]; 2695 uint32_t redboot_ver_str[8]; 2696 uint32_t driver_ver_str[8]; 2697 uint32_t flash_fw_ver_str[8]; 2698 uint32_t functionality; 2699 uint32_t word105; 2700 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 2701 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 2702 #define lpfc_cntl_attr_max_cbd_len_WORD word105 2703 #define lpfc_cntl_attr_asic_rev_SHIFT 16 2704 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 2705 #define lpfc_cntl_attr_asic_rev_WORD word105 2706 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 2707 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 2708 #define lpfc_cntl_attr_gen_guid0_WORD word105 2709 uint32_t gen_guid1_12[3]; 2710 uint32_t word109; 2711 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 2712 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 2713 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 2714 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 2715 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 2716 #define lpfc_cntl_attr_gen_guid15_WORD word109 2717 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 2718 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 2719 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 2720 uint32_t word110; 2721 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 2722 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 2723 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 2724 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 2725 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 2726 #define lpfc_cntl_attr_multi_func_dev_WORD word110 2727 uint32_t word111; 2728 #define lpfc_cntl_attr_cache_valid_SHIFT 0 2729 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 2730 #define lpfc_cntl_attr_cache_valid_WORD word111 2731 #define lpfc_cntl_attr_hba_status_SHIFT 8 2732 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 2733 #define lpfc_cntl_attr_hba_status_WORD word111 2734 #define lpfc_cntl_attr_max_domain_SHIFT 16 2735 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 2736 #define lpfc_cntl_attr_max_domain_WORD word111 2737 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 2738 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 2739 #define lpfc_cntl_attr_lnk_numb_WORD word111 2740 #define lpfc_cntl_attr_lnk_type_SHIFT 30 2741 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 2742 #define lpfc_cntl_attr_lnk_type_WORD word111 2743 uint32_t fw_post_status; 2744 uint32_t hba_mtu[8]; 2745 uint32_t word121; 2746 uint32_t reserved1[3]; 2747 uint32_t word125; 2748 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 2749 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 2750 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 2751 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 2752 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 2753 #define lpfc_cntl_attr_pci_device_id_WORD word125 2754 uint32_t word126; 2755 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 2756 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 2757 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 2758 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 2759 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 2760 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 2761 uint32_t word127; 2762 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 2763 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 2764 #define lpfc_cntl_attr_pci_bus_num_WORD word127 2765 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 2766 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 2767 #define lpfc_cntl_attr_pci_dev_num_WORD word127 2768 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 2769 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 2770 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 2771 #define lpfc_cntl_attr_inf_type_SHIFT 24 2772 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 2773 #define lpfc_cntl_attr_inf_type_WORD word127 2774 uint32_t unique_id[2]; 2775 uint32_t word130; 2776 #define lpfc_cntl_attr_num_netfil_SHIFT 0 2777 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 2778 #define lpfc_cntl_attr_num_netfil_WORD word130 2779 uint32_t reserved2[4]; 2780 }; 2781 2782 struct lpfc_mbx_get_cntl_attributes { 2783 union lpfc_sli4_cfg_shdr cfg_shdr; 2784 struct lpfc_controller_attribute cntl_attr; 2785 }; 2786 2787 struct lpfc_mbx_get_port_name { 2788 struct mbox_header header; 2789 union { 2790 struct { 2791 uint32_t word4; 2792 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 2793 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 2794 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 2795 } request; 2796 struct { 2797 uint32_t word4; 2798 #define lpfc_mbx_get_port_name_name0_SHIFT 0 2799 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 2800 #define lpfc_mbx_get_port_name_name0_WORD word4 2801 #define lpfc_mbx_get_port_name_name1_SHIFT 8 2802 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 2803 #define lpfc_mbx_get_port_name_name1_WORD word4 2804 #define lpfc_mbx_get_port_name_name2_SHIFT 16 2805 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 2806 #define lpfc_mbx_get_port_name_name2_WORD word4 2807 #define lpfc_mbx_get_port_name_name3_SHIFT 24 2808 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 2809 #define lpfc_mbx_get_port_name_name3_WORD word4 2810 #define LPFC_LINK_NUMBER_0 0 2811 #define LPFC_LINK_NUMBER_1 1 2812 #define LPFC_LINK_NUMBER_2 2 2813 #define LPFC_LINK_NUMBER_3 3 2814 } response; 2815 } u; 2816 }; 2817 2818 /* Mailbox Completion Queue Error Messages */ 2819 #define MB_CQE_STATUS_SUCCESS 0x0 2820 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2821 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2822 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2823 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2824 #define MB_CQE_STATUS_DMA_FAILED 0x5 2825 2826 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 2827 struct lpfc_mbx_wr_object { 2828 struct mbox_header header; 2829 union { 2830 struct { 2831 uint32_t word4; 2832 #define lpfc_wr_object_eof_SHIFT 31 2833 #define lpfc_wr_object_eof_MASK 0x00000001 2834 #define lpfc_wr_object_eof_WORD word4 2835 #define lpfc_wr_object_write_length_SHIFT 0 2836 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 2837 #define lpfc_wr_object_write_length_WORD word4 2838 uint32_t write_offset; 2839 uint32_t object_name[26]; 2840 uint32_t bde_count; 2841 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 2842 } request; 2843 struct { 2844 uint32_t actual_write_length; 2845 } response; 2846 } u; 2847 }; 2848 2849 /* mailbox queue entry structure */ 2850 struct lpfc_mqe { 2851 uint32_t word0; 2852 #define lpfc_mqe_status_SHIFT 16 2853 #define lpfc_mqe_status_MASK 0x0000FFFF 2854 #define lpfc_mqe_status_WORD word0 2855 #define lpfc_mqe_command_SHIFT 8 2856 #define lpfc_mqe_command_MASK 0x000000FF 2857 #define lpfc_mqe_command_WORD word0 2858 union { 2859 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2860 /* sli4 mailbox commands */ 2861 struct lpfc_mbx_sli4_config sli4_config; 2862 struct lpfc_mbx_init_vfi init_vfi; 2863 struct lpfc_mbx_reg_vfi reg_vfi; 2864 struct lpfc_mbx_reg_vfi unreg_vfi; 2865 struct lpfc_mbx_init_vpi init_vpi; 2866 struct lpfc_mbx_resume_rpi resume_rpi; 2867 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2868 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2869 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2870 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2871 struct lpfc_mbx_reg_fcfi reg_fcfi; 2872 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2873 struct lpfc_mbx_mq_create mq_create; 2874 struct lpfc_mbx_mq_create_ext mq_create_ext; 2875 struct lpfc_mbx_eq_create eq_create; 2876 struct lpfc_mbx_cq_create cq_create; 2877 struct lpfc_mbx_wq_create wq_create; 2878 struct lpfc_mbx_rq_create rq_create; 2879 struct lpfc_mbx_mq_destroy mq_destroy; 2880 struct lpfc_mbx_eq_destroy eq_destroy; 2881 struct lpfc_mbx_cq_destroy cq_destroy; 2882 struct lpfc_mbx_wq_destroy wq_destroy; 2883 struct lpfc_mbx_rq_destroy rq_destroy; 2884 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 2885 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 2886 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 2887 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 2888 struct lpfc_mbx_nembed_cmd nembed_cmd; 2889 struct lpfc_mbx_read_rev read_rev; 2890 struct lpfc_mbx_read_vpi read_vpi; 2891 struct lpfc_mbx_read_config rd_config; 2892 struct lpfc_mbx_request_features req_ftrs; 2893 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 2894 struct lpfc_mbx_query_fw_cfg query_fw_cfg; 2895 struct lpfc_mbx_supp_pages supp_pages; 2896 struct lpfc_mbx_pc_sli4_params sli4_params; 2897 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 2898 struct lpfc_mbx_set_link_diag_state link_diag_state; 2899 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 2900 struct lpfc_mbx_run_link_diag_test link_diag_test; 2901 struct lpfc_mbx_get_func_cfg get_func_cfg; 2902 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 2903 struct lpfc_mbx_wr_object wr_object; 2904 struct lpfc_mbx_get_port_name get_port_name; 2905 struct lpfc_mbx_nop nop; 2906 } un; 2907 }; 2908 2909 struct lpfc_mcqe { 2910 uint32_t word0; 2911 #define lpfc_mcqe_status_SHIFT 0 2912 #define lpfc_mcqe_status_MASK 0x0000FFFF 2913 #define lpfc_mcqe_status_WORD word0 2914 #define lpfc_mcqe_ext_status_SHIFT 16 2915 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 2916 #define lpfc_mcqe_ext_status_WORD word0 2917 uint32_t mcqe_tag0; 2918 uint32_t mcqe_tag1; 2919 uint32_t trailer; 2920 #define lpfc_trailer_valid_SHIFT 31 2921 #define lpfc_trailer_valid_MASK 0x00000001 2922 #define lpfc_trailer_valid_WORD trailer 2923 #define lpfc_trailer_async_SHIFT 30 2924 #define lpfc_trailer_async_MASK 0x00000001 2925 #define lpfc_trailer_async_WORD trailer 2926 #define lpfc_trailer_hpi_SHIFT 29 2927 #define lpfc_trailer_hpi_MASK 0x00000001 2928 #define lpfc_trailer_hpi_WORD trailer 2929 #define lpfc_trailer_completed_SHIFT 28 2930 #define lpfc_trailer_completed_MASK 0x00000001 2931 #define lpfc_trailer_completed_WORD trailer 2932 #define lpfc_trailer_consumed_SHIFT 27 2933 #define lpfc_trailer_consumed_MASK 0x00000001 2934 #define lpfc_trailer_consumed_WORD trailer 2935 #define lpfc_trailer_type_SHIFT 16 2936 #define lpfc_trailer_type_MASK 0x000000FF 2937 #define lpfc_trailer_type_WORD trailer 2938 #define lpfc_trailer_code_SHIFT 8 2939 #define lpfc_trailer_code_MASK 0x000000FF 2940 #define lpfc_trailer_code_WORD trailer 2941 #define LPFC_TRAILER_CODE_LINK 0x1 2942 #define LPFC_TRAILER_CODE_FCOE 0x2 2943 #define LPFC_TRAILER_CODE_DCBX 0x3 2944 #define LPFC_TRAILER_CODE_GRP5 0x5 2945 #define LPFC_TRAILER_CODE_FC 0x10 2946 #define LPFC_TRAILER_CODE_SLI 0x11 2947 }; 2948 2949 struct lpfc_acqe_link { 2950 uint32_t word0; 2951 #define lpfc_acqe_link_speed_SHIFT 24 2952 #define lpfc_acqe_link_speed_MASK 0x000000FF 2953 #define lpfc_acqe_link_speed_WORD word0 2954 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 2955 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 2956 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 2957 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 2958 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 2959 #define lpfc_acqe_link_duplex_SHIFT 16 2960 #define lpfc_acqe_link_duplex_MASK 0x000000FF 2961 #define lpfc_acqe_link_duplex_WORD word0 2962 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 2963 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 2964 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 2965 #define lpfc_acqe_link_status_SHIFT 8 2966 #define lpfc_acqe_link_status_MASK 0x000000FF 2967 #define lpfc_acqe_link_status_WORD word0 2968 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 2969 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 2970 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 2971 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 2972 #define lpfc_acqe_link_type_SHIFT 6 2973 #define lpfc_acqe_link_type_MASK 0x00000003 2974 #define lpfc_acqe_link_type_WORD word0 2975 #define lpfc_acqe_link_number_SHIFT 0 2976 #define lpfc_acqe_link_number_MASK 0x0000003F 2977 #define lpfc_acqe_link_number_WORD word0 2978 uint32_t word1; 2979 #define lpfc_acqe_link_fault_SHIFT 0 2980 #define lpfc_acqe_link_fault_MASK 0x000000FF 2981 #define lpfc_acqe_link_fault_WORD word1 2982 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 2983 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 2984 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 2985 #define lpfc_acqe_logical_link_speed_SHIFT 16 2986 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 2987 #define lpfc_acqe_logical_link_speed_WORD word1 2988 uint32_t event_tag; 2989 uint32_t trailer; 2990 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 2991 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 2992 }; 2993 2994 struct lpfc_acqe_fip { 2995 uint32_t index; 2996 uint32_t word1; 2997 #define lpfc_acqe_fip_fcf_count_SHIFT 0 2998 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 2999 #define lpfc_acqe_fip_fcf_count_WORD word1 3000 #define lpfc_acqe_fip_event_type_SHIFT 16 3001 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3002 #define lpfc_acqe_fip_event_type_WORD word1 3003 uint32_t event_tag; 3004 uint32_t trailer; 3005 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3006 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3007 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3008 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3009 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3010 }; 3011 3012 struct lpfc_acqe_dcbx { 3013 uint32_t tlv_ttl; 3014 uint32_t reserved; 3015 uint32_t event_tag; 3016 uint32_t trailer; 3017 }; 3018 3019 struct lpfc_acqe_grp5 { 3020 uint32_t word0; 3021 #define lpfc_acqe_grp5_type_SHIFT 6 3022 #define lpfc_acqe_grp5_type_MASK 0x00000003 3023 #define lpfc_acqe_grp5_type_WORD word0 3024 #define lpfc_acqe_grp5_number_SHIFT 0 3025 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3026 #define lpfc_acqe_grp5_number_WORD word0 3027 uint32_t word1; 3028 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3029 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3030 #define lpfc_acqe_grp5_llink_spd_WORD word1 3031 uint32_t event_tag; 3032 uint32_t trailer; 3033 }; 3034 3035 struct lpfc_acqe_fc_la { 3036 uint32_t word0; 3037 #define lpfc_acqe_fc_la_speed_SHIFT 24 3038 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3039 #define lpfc_acqe_fc_la_speed_WORD word0 3040 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 3041 #define LPFC_FC_LA_SPEED_1G 0x1 3042 #define LPFC_FC_LA_SPEED_2G 0x2 3043 #define LPFC_FC_LA_SPEED_4G 0x4 3044 #define LPFC_FC_LA_SPEED_8G 0x8 3045 #define LPFC_FC_LA_SPEED_10G 0xA 3046 #define LPFC_FC_LA_SPEED_16G 0x10 3047 #define lpfc_acqe_fc_la_topology_SHIFT 16 3048 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3049 #define lpfc_acqe_fc_la_topology_WORD word0 3050 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3051 #define LPFC_FC_LA_TOP_P2P 0x1 3052 #define LPFC_FC_LA_TOP_FCAL 0x2 3053 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3054 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3055 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3056 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3057 #define lpfc_acqe_fc_la_att_type_WORD word0 3058 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3059 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3060 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3061 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3062 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3063 #define lpfc_acqe_fc_la_port_type_WORD word0 3064 #define LPFC_LINK_TYPE_ETHERNET 0x0 3065 #define LPFC_LINK_TYPE_FC 0x1 3066 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3067 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3068 #define lpfc_acqe_fc_la_port_number_WORD word0 3069 uint32_t word1; 3070 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3071 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3072 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3073 #define lpfc_acqe_fc_la_fault_SHIFT 0 3074 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3075 #define lpfc_acqe_fc_la_fault_WORD word1 3076 #define LPFC_FC_LA_FAULT_NONE 0x0 3077 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3078 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3079 uint32_t event_tag; 3080 uint32_t trailer; 3081 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3082 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3083 }; 3084 3085 struct lpfc_acqe_sli { 3086 uint32_t event_data1; 3087 uint32_t event_data2; 3088 uint32_t reserved; 3089 uint32_t trailer; 3090 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3091 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3092 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3093 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3094 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3095 }; 3096 3097 /* 3098 * Define the bootstrap mailbox (bmbx) region used to communicate 3099 * mailbox command between the host and port. The mailbox consists 3100 * of a payload area of 256 bytes and a completion queue of length 3101 * 16 bytes. 3102 */ 3103 struct lpfc_bmbx_create { 3104 struct lpfc_mqe mqe; 3105 struct lpfc_mcqe mcqe; 3106 }; 3107 3108 #define SGL_ALIGN_SZ 64 3109 #define SGL_PAGE_SIZE 4096 3110 /* align SGL addr on a size boundary - adjust address up */ 3111 #define NO_XRI 0xffff 3112 3113 struct wqe_common { 3114 uint32_t word6; 3115 #define wqe_xri_tag_SHIFT 0 3116 #define wqe_xri_tag_MASK 0x0000FFFF 3117 #define wqe_xri_tag_WORD word6 3118 #define wqe_ctxt_tag_SHIFT 16 3119 #define wqe_ctxt_tag_MASK 0x0000FFFF 3120 #define wqe_ctxt_tag_WORD word6 3121 uint32_t word7; 3122 #define wqe_dif_SHIFT 0 3123 #define wqe_dif_MASK 0x00000003 3124 #define wqe_dif_WORD word7 3125 #define wqe_ct_SHIFT 2 3126 #define wqe_ct_MASK 0x00000003 3127 #define wqe_ct_WORD word7 3128 #define wqe_status_SHIFT 4 3129 #define wqe_status_MASK 0x0000000f 3130 #define wqe_status_WORD word7 3131 #define wqe_cmnd_SHIFT 8 3132 #define wqe_cmnd_MASK 0x000000ff 3133 #define wqe_cmnd_WORD word7 3134 #define wqe_class_SHIFT 16 3135 #define wqe_class_MASK 0x00000007 3136 #define wqe_class_WORD word7 3137 #define wqe_ar_SHIFT 19 3138 #define wqe_ar_MASK 0x00000001 3139 #define wqe_ar_WORD word7 3140 #define wqe_ag_SHIFT wqe_ar_SHIFT 3141 #define wqe_ag_MASK wqe_ar_MASK 3142 #define wqe_ag_WORD wqe_ar_WORD 3143 #define wqe_pu_SHIFT 20 3144 #define wqe_pu_MASK 0x00000003 3145 #define wqe_pu_WORD word7 3146 #define wqe_erp_SHIFT 22 3147 #define wqe_erp_MASK 0x00000001 3148 #define wqe_erp_WORD word7 3149 #define wqe_conf_SHIFT wqe_erp_SHIFT 3150 #define wqe_conf_MASK wqe_erp_MASK 3151 #define wqe_conf_WORD wqe_erp_WORD 3152 #define wqe_lnk_SHIFT 23 3153 #define wqe_lnk_MASK 0x00000001 3154 #define wqe_lnk_WORD word7 3155 #define wqe_tmo_SHIFT 24 3156 #define wqe_tmo_MASK 0x000000ff 3157 #define wqe_tmo_WORD word7 3158 uint32_t abort_tag; /* word 8 in WQE */ 3159 uint32_t word9; 3160 #define wqe_reqtag_SHIFT 0 3161 #define wqe_reqtag_MASK 0x0000FFFF 3162 #define wqe_reqtag_WORD word9 3163 #define wqe_temp_rpi_SHIFT 16 3164 #define wqe_temp_rpi_MASK 0x0000FFFF 3165 #define wqe_temp_rpi_WORD word9 3166 #define wqe_rcvoxid_SHIFT 16 3167 #define wqe_rcvoxid_MASK 0x0000FFFF 3168 #define wqe_rcvoxid_WORD word9 3169 uint32_t word10; 3170 #define wqe_ebde_cnt_SHIFT 0 3171 #define wqe_ebde_cnt_MASK 0x0000000f 3172 #define wqe_ebde_cnt_WORD word10 3173 #define wqe_lenloc_SHIFT 7 3174 #define wqe_lenloc_MASK 0x00000003 3175 #define wqe_lenloc_WORD word10 3176 #define LPFC_WQE_LENLOC_NONE 0 3177 #define LPFC_WQE_LENLOC_WORD3 1 3178 #define LPFC_WQE_LENLOC_WORD12 2 3179 #define LPFC_WQE_LENLOC_WORD4 3 3180 #define wqe_qosd_SHIFT 9 3181 #define wqe_qosd_MASK 0x00000001 3182 #define wqe_qosd_WORD word10 3183 #define wqe_xbl_SHIFT 11 3184 #define wqe_xbl_MASK 0x00000001 3185 #define wqe_xbl_WORD word10 3186 #define wqe_iod_SHIFT 13 3187 #define wqe_iod_MASK 0x00000001 3188 #define wqe_iod_WORD word10 3189 #define LPFC_WQE_IOD_WRITE 0 3190 #define LPFC_WQE_IOD_READ 1 3191 #define wqe_dbde_SHIFT 14 3192 #define wqe_dbde_MASK 0x00000001 3193 #define wqe_dbde_WORD word10 3194 #define wqe_wqes_SHIFT 15 3195 #define wqe_wqes_MASK 0x00000001 3196 #define wqe_wqes_WORD word10 3197 /* Note that this field overlaps above fields */ 3198 #define wqe_wqid_SHIFT 1 3199 #define wqe_wqid_MASK 0x00007fff 3200 #define wqe_wqid_WORD word10 3201 #define wqe_pri_SHIFT 16 3202 #define wqe_pri_MASK 0x00000007 3203 #define wqe_pri_WORD word10 3204 #define wqe_pv_SHIFT 19 3205 #define wqe_pv_MASK 0x00000001 3206 #define wqe_pv_WORD word10 3207 #define wqe_xc_SHIFT 21 3208 #define wqe_xc_MASK 0x00000001 3209 #define wqe_xc_WORD word10 3210 #define wqe_sr_SHIFT 22 3211 #define wqe_sr_MASK 0x00000001 3212 #define wqe_sr_WORD word10 3213 #define wqe_ccpe_SHIFT 23 3214 #define wqe_ccpe_MASK 0x00000001 3215 #define wqe_ccpe_WORD word10 3216 #define wqe_ccp_SHIFT 24 3217 #define wqe_ccp_MASK 0x000000ff 3218 #define wqe_ccp_WORD word10 3219 uint32_t word11; 3220 #define wqe_cmd_type_SHIFT 0 3221 #define wqe_cmd_type_MASK 0x0000000f 3222 #define wqe_cmd_type_WORD word11 3223 #define wqe_els_id_SHIFT 4 3224 #define wqe_els_id_MASK 0x00000003 3225 #define wqe_els_id_WORD word11 3226 #define LPFC_ELS_ID_FLOGI 3 3227 #define LPFC_ELS_ID_FDISC 2 3228 #define LPFC_ELS_ID_LOGO 1 3229 #define LPFC_ELS_ID_DEFAULT 0 3230 #define wqe_wqec_SHIFT 7 3231 #define wqe_wqec_MASK 0x00000001 3232 #define wqe_wqec_WORD word11 3233 #define wqe_cqid_SHIFT 16 3234 #define wqe_cqid_MASK 0x0000ffff 3235 #define wqe_cqid_WORD word11 3236 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3237 }; 3238 3239 struct wqe_did { 3240 uint32_t word5; 3241 #define wqe_els_did_SHIFT 0 3242 #define wqe_els_did_MASK 0x00FFFFFF 3243 #define wqe_els_did_WORD word5 3244 #define wqe_xmit_bls_pt_SHIFT 28 3245 #define wqe_xmit_bls_pt_MASK 0x00000003 3246 #define wqe_xmit_bls_pt_WORD word5 3247 #define wqe_xmit_bls_ar_SHIFT 30 3248 #define wqe_xmit_bls_ar_MASK 0x00000001 3249 #define wqe_xmit_bls_ar_WORD word5 3250 #define wqe_xmit_bls_xo_SHIFT 31 3251 #define wqe_xmit_bls_xo_MASK 0x00000001 3252 #define wqe_xmit_bls_xo_WORD word5 3253 }; 3254 3255 struct lpfc_wqe_generic{ 3256 struct ulp_bde64 bde; 3257 uint32_t word3; 3258 uint32_t word4; 3259 uint32_t word5; 3260 struct wqe_common wqe_com; 3261 uint32_t payload[4]; 3262 }; 3263 3264 struct els_request64_wqe { 3265 struct ulp_bde64 bde; 3266 uint32_t payload_len; 3267 uint32_t word4; 3268 #define els_req64_sid_SHIFT 0 3269 #define els_req64_sid_MASK 0x00FFFFFF 3270 #define els_req64_sid_WORD word4 3271 #define els_req64_sp_SHIFT 24 3272 #define els_req64_sp_MASK 0x00000001 3273 #define els_req64_sp_WORD word4 3274 #define els_req64_vf_SHIFT 25 3275 #define els_req64_vf_MASK 0x00000001 3276 #define els_req64_vf_WORD word4 3277 struct wqe_did wqe_dest; 3278 struct wqe_common wqe_com; /* words 6-11 */ 3279 uint32_t word12; 3280 #define els_req64_vfid_SHIFT 1 3281 #define els_req64_vfid_MASK 0x00000FFF 3282 #define els_req64_vfid_WORD word12 3283 #define els_req64_pri_SHIFT 13 3284 #define els_req64_pri_MASK 0x00000007 3285 #define els_req64_pri_WORD word12 3286 uint32_t word13; 3287 #define els_req64_hopcnt_SHIFT 24 3288 #define els_req64_hopcnt_MASK 0x000000ff 3289 #define els_req64_hopcnt_WORD word13 3290 uint32_t reserved[2]; 3291 }; 3292 3293 struct xmit_els_rsp64_wqe { 3294 struct ulp_bde64 bde; 3295 uint32_t response_payload_len; 3296 uint32_t rsvd4; 3297 struct wqe_did wqe_dest; 3298 struct wqe_common wqe_com; /* words 6-11 */ 3299 uint32_t word12; 3300 #define wqe_rsp_temp_rpi_SHIFT 0 3301 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3302 #define wqe_rsp_temp_rpi_WORD word12 3303 uint32_t rsvd_13_15[3]; 3304 }; 3305 3306 struct xmit_bls_rsp64_wqe { 3307 uint32_t payload0; 3308 /* Payload0 for BA_ACC */ 3309 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3310 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3311 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3312 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3313 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3314 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3315 /* Payload0 for BA_RJT */ 3316 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3317 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3318 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3319 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3320 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3321 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3322 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3323 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3324 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3325 uint32_t word1; 3326 #define xmit_bls_rsp64_rxid_SHIFT 0 3327 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3328 #define xmit_bls_rsp64_rxid_WORD word1 3329 #define xmit_bls_rsp64_oxid_SHIFT 16 3330 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3331 #define xmit_bls_rsp64_oxid_WORD word1 3332 uint32_t word2; 3333 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3334 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3335 #define xmit_bls_rsp64_seqcnthi_WORD word2 3336 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3337 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3338 #define xmit_bls_rsp64_seqcntlo_WORD word2 3339 uint32_t rsrvd3; 3340 uint32_t rsrvd4; 3341 struct wqe_did wqe_dest; 3342 struct wqe_common wqe_com; /* words 6-11 */ 3343 uint32_t word12; 3344 #define xmit_bls_rsp64_temprpi_SHIFT 0 3345 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3346 #define xmit_bls_rsp64_temprpi_WORD word12 3347 uint32_t rsvd_13_15[3]; 3348 }; 3349 3350 struct wqe_rctl_dfctl { 3351 uint32_t word5; 3352 #define wqe_si_SHIFT 2 3353 #define wqe_si_MASK 0x000000001 3354 #define wqe_si_WORD word5 3355 #define wqe_la_SHIFT 3 3356 #define wqe_la_MASK 0x000000001 3357 #define wqe_la_WORD word5 3358 #define wqe_xo_SHIFT 6 3359 #define wqe_xo_MASK 0x000000001 3360 #define wqe_xo_WORD word5 3361 #define wqe_ls_SHIFT 7 3362 #define wqe_ls_MASK 0x000000001 3363 #define wqe_ls_WORD word5 3364 #define wqe_dfctl_SHIFT 8 3365 #define wqe_dfctl_MASK 0x0000000ff 3366 #define wqe_dfctl_WORD word5 3367 #define wqe_type_SHIFT 16 3368 #define wqe_type_MASK 0x0000000ff 3369 #define wqe_type_WORD word5 3370 #define wqe_rctl_SHIFT 24 3371 #define wqe_rctl_MASK 0x0000000ff 3372 #define wqe_rctl_WORD word5 3373 }; 3374 3375 struct xmit_seq64_wqe { 3376 struct ulp_bde64 bde; 3377 uint32_t rsvd3; 3378 uint32_t relative_offset; 3379 struct wqe_rctl_dfctl wge_ctl; 3380 struct wqe_common wqe_com; /* words 6-11 */ 3381 uint32_t xmit_len; 3382 uint32_t rsvd_12_15[3]; 3383 }; 3384 struct xmit_bcast64_wqe { 3385 struct ulp_bde64 bde; 3386 uint32_t seq_payload_len; 3387 uint32_t rsvd4; 3388 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3389 struct wqe_common wqe_com; /* words 6-11 */ 3390 uint32_t rsvd_12_15[4]; 3391 }; 3392 3393 struct gen_req64_wqe { 3394 struct ulp_bde64 bde; 3395 uint32_t request_payload_len; 3396 uint32_t relative_offset; 3397 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3398 struct wqe_common wqe_com; /* words 6-11 */ 3399 uint32_t rsvd_12_15[4]; 3400 }; 3401 3402 struct create_xri_wqe { 3403 uint32_t rsrvd[5]; /* words 0-4 */ 3404 struct wqe_did wqe_dest; /* word 5 */ 3405 struct wqe_common wqe_com; /* words 6-11 */ 3406 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3407 }; 3408 3409 #define T_REQUEST_TAG 3 3410 #define T_XRI_TAG 1 3411 3412 struct abort_cmd_wqe { 3413 uint32_t rsrvd[3]; 3414 uint32_t word3; 3415 #define abort_cmd_ia_SHIFT 0 3416 #define abort_cmd_ia_MASK 0x000000001 3417 #define abort_cmd_ia_WORD word3 3418 #define abort_cmd_criteria_SHIFT 8 3419 #define abort_cmd_criteria_MASK 0x0000000ff 3420 #define abort_cmd_criteria_WORD word3 3421 uint32_t rsrvd4; 3422 uint32_t rsrvd5; 3423 struct wqe_common wqe_com; /* words 6-11 */ 3424 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3425 }; 3426 3427 struct fcp_iwrite64_wqe { 3428 struct ulp_bde64 bde; 3429 uint32_t payload_offset_len; 3430 uint32_t total_xfer_len; 3431 uint32_t initial_xfer_len; 3432 struct wqe_common wqe_com; /* words 6-11 */ 3433 uint32_t rsrvd12; 3434 struct ulp_bde64 ph_bde; /* words 13-15 */ 3435 }; 3436 3437 struct fcp_iread64_wqe { 3438 struct ulp_bde64 bde; 3439 uint32_t payload_offset_len; /* word 3 */ 3440 uint32_t total_xfer_len; /* word 4 */ 3441 uint32_t rsrvd5; /* word 5 */ 3442 struct wqe_common wqe_com; /* words 6-11 */ 3443 uint32_t rsrvd12; 3444 struct ulp_bde64 ph_bde; /* words 13-15 */ 3445 }; 3446 3447 struct fcp_icmnd64_wqe { 3448 struct ulp_bde64 bde; /* words 0-2 */ 3449 uint32_t rsrvd3; /* word 3 */ 3450 uint32_t rsrvd4; /* word 4 */ 3451 uint32_t rsrvd5; /* word 5 */ 3452 struct wqe_common wqe_com; /* words 6-11 */ 3453 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3454 }; 3455 3456 3457 union lpfc_wqe { 3458 uint32_t words[16]; 3459 struct lpfc_wqe_generic generic; 3460 struct fcp_icmnd64_wqe fcp_icmd; 3461 struct fcp_iread64_wqe fcp_iread; 3462 struct fcp_iwrite64_wqe fcp_iwrite; 3463 struct abort_cmd_wqe abort_cmd; 3464 struct create_xri_wqe create_xri; 3465 struct xmit_bcast64_wqe xmit_bcast64; 3466 struct xmit_seq64_wqe xmit_sequence; 3467 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3468 struct xmit_els_rsp64_wqe xmit_els_rsp; 3469 struct els_request64_wqe els_req; 3470 struct gen_req64_wqe gen_req; 3471 }; 3472 3473 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3474 #define LPFC_FILE_TYPE_GROUP 0xf7 3475 #define LPFC_FILE_ID_GROUP 0xa2 3476 struct lpfc_grp_hdr { 3477 uint32_t size; 3478 uint32_t magic_number; 3479 uint32_t word2; 3480 #define lpfc_grp_hdr_file_type_SHIFT 24 3481 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3482 #define lpfc_grp_hdr_file_type_WORD word2 3483 #define lpfc_grp_hdr_id_SHIFT 16 3484 #define lpfc_grp_hdr_id_MASK 0x000000FF 3485 #define lpfc_grp_hdr_id_WORD word2 3486 uint8_t rev_name[128]; 3487 uint8_t date[12]; 3488 uint8_t revision[32]; 3489 }; 3490 3491 #define FCP_COMMAND 0x0 3492 #define FCP_COMMAND_DATA_OUT 0x1 3493 #define ELS_COMMAND_NON_FIP 0xC 3494 #define ELS_COMMAND_FIP 0xD 3495 #define OTHER_COMMAND 0x8 3496 3497 #define LPFC_FW_DUMP 1 3498 #define LPFC_FW_RESET 2 3499 #define LPFC_DV_RESET 3 3500