1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009-2013 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE_V0 4 110 #define LPFC_MAX_WQ_PAGE 8 111 #define LPFC_MAX_CQ_PAGE 4 112 #define LPFC_MAX_EQ_PAGE 8 113 114 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 115 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 116 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 117 118 /* Define SLI4 Alignment requirements. */ 119 #define LPFC_ALIGN_16_BYTE 16 120 #define LPFC_ALIGN_64_BYTE 64 121 122 /* Define SLI4 specific definitions. */ 123 #define LPFC_MQ_CQE_BYTE_OFFSET 256 124 #define LPFC_MBX_CMD_HDR_LENGTH 16 125 #define LPFC_MBX_ERROR_RANGE 0x4000 126 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 127 #define LPFC_BMBX_BIT1_ADDR_LO 0 128 #define LPFC_RPI_HDR_COUNT 64 129 #define LPFC_HDR_TEMPLATE_SIZE 4096 130 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 131 #define LPFC_FCF_RECORD_WD_CNT 132 132 #define LPFC_ENTIRE_FCF_DATABASE 0 133 #define LPFC_DFLT_FCF_INDEX 0 134 135 /* Virtual function numbers */ 136 #define LPFC_VF0 0 137 #define LPFC_VF1 1 138 #define LPFC_VF2 2 139 #define LPFC_VF3 3 140 #define LPFC_VF4 4 141 #define LPFC_VF5 5 142 #define LPFC_VF6 6 143 #define LPFC_VF7 7 144 #define LPFC_VF8 8 145 #define LPFC_VF9 9 146 #define LPFC_VF10 10 147 #define LPFC_VF11 11 148 #define LPFC_VF12 12 149 #define LPFC_VF13 13 150 #define LPFC_VF14 14 151 #define LPFC_VF15 15 152 #define LPFC_VF16 16 153 #define LPFC_VF17 17 154 #define LPFC_VF18 18 155 #define LPFC_VF19 19 156 #define LPFC_VF20 20 157 #define LPFC_VF21 21 158 #define LPFC_VF22 22 159 #define LPFC_VF23 23 160 #define LPFC_VF24 24 161 #define LPFC_VF25 25 162 #define LPFC_VF26 26 163 #define LPFC_VF27 27 164 #define LPFC_VF28 28 165 #define LPFC_VF29 29 166 #define LPFC_VF30 30 167 #define LPFC_VF31 31 168 169 /* PCI function numbers */ 170 #define LPFC_PCI_FUNC0 0 171 #define LPFC_PCI_FUNC1 1 172 #define LPFC_PCI_FUNC2 2 173 #define LPFC_PCI_FUNC3 3 174 #define LPFC_PCI_FUNC4 4 175 176 /* SLI4 interface type-2 PDEV_CTL register */ 177 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 178 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 179 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 180 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 181 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 182 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 183 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 184 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 185 186 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 187 188 /* Active interrupt test count */ 189 #define LPFC_ACT_INTR_CNT 4 190 191 /* Algrithmns for scheduling FCP commands to WQs */ 192 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 193 #define LPFC_FCP_SCHED_BY_CPU 1 194 195 /* Delay Multiplier constant */ 196 #define LPFC_DMULT_CONST 651042 197 198 /* Configuration of Interrupts / sec for entire HBA port */ 199 #define LPFC_MIN_IMAX 5000 200 #define LPFC_MAX_IMAX 5000000 201 #define LPFC_DEF_IMAX 50000 202 203 #define LPFC_MIN_CPU_MAP 0 204 #define LPFC_MAX_CPU_MAP 2 205 #define LPFC_HBA_CPU_MAP 1 206 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 207 208 /* PORT_CAPABILITIES constants. */ 209 #define LPFC_MAX_SUPPORTED_PAGES 8 210 211 struct ulp_bde64 { 212 union ULP_BDE_TUS { 213 uint32_t w; 214 struct { 215 #ifdef __BIG_ENDIAN_BITFIELD 216 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 217 VALUE !! */ 218 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 219 #else /* __LITTLE_ENDIAN_BITFIELD */ 220 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 222 VALUE !! */ 223 #endif 224 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 225 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 226 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 227 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 228 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 229 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 230 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 231 } f; 232 } tus; 233 uint32_t addrLow; 234 uint32_t addrHigh; 235 }; 236 237 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 238 #define LPFC_MAX_BDE_IMM_SIZE 64 239 240 struct lpfc_sli4_flags { 241 uint32_t word0; 242 #define lpfc_idx_rsrc_rdy_SHIFT 0 243 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 244 #define lpfc_idx_rsrc_rdy_WORD word0 245 #define LPFC_IDX_RSRC_RDY 1 246 #define lpfc_rpi_rsrc_rdy_SHIFT 1 247 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 248 #define lpfc_rpi_rsrc_rdy_WORD word0 249 #define LPFC_RPI_RSRC_RDY 1 250 #define lpfc_vpi_rsrc_rdy_SHIFT 2 251 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 252 #define lpfc_vpi_rsrc_rdy_WORD word0 253 #define LPFC_VPI_RSRC_RDY 1 254 #define lpfc_vfi_rsrc_rdy_SHIFT 3 255 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 256 #define lpfc_vfi_rsrc_rdy_WORD word0 257 #define LPFC_VFI_RSRC_RDY 1 258 }; 259 260 struct sli4_bls_rsp { 261 uint32_t word0_rsvd; /* Word0 must be reserved */ 262 uint32_t word1; 263 #define lpfc_abts_orig_SHIFT 0 264 #define lpfc_abts_orig_MASK 0x00000001 265 #define lpfc_abts_orig_WORD word1 266 #define LPFC_ABTS_UNSOL_RSP 1 267 #define LPFC_ABTS_UNSOL_INT 0 268 uint32_t word2; 269 #define lpfc_abts_rxid_SHIFT 0 270 #define lpfc_abts_rxid_MASK 0x0000FFFF 271 #define lpfc_abts_rxid_WORD word2 272 #define lpfc_abts_oxid_SHIFT 16 273 #define lpfc_abts_oxid_MASK 0x0000FFFF 274 #define lpfc_abts_oxid_WORD word2 275 uint32_t word3; 276 #define lpfc_vndr_code_SHIFT 0 277 #define lpfc_vndr_code_MASK 0x000000FF 278 #define lpfc_vndr_code_WORD word3 279 #define lpfc_rsn_expln_SHIFT 8 280 #define lpfc_rsn_expln_MASK 0x000000FF 281 #define lpfc_rsn_expln_WORD word3 282 #define lpfc_rsn_code_SHIFT 16 283 #define lpfc_rsn_code_MASK 0x000000FF 284 #define lpfc_rsn_code_WORD word3 285 286 uint32_t word4; 287 uint32_t word5_rsvd; /* Word5 must be reserved */ 288 }; 289 290 /* event queue entry structure */ 291 struct lpfc_eqe { 292 uint32_t word0; 293 #define lpfc_eqe_resource_id_SHIFT 16 294 #define lpfc_eqe_resource_id_MASK 0x000000FF 295 #define lpfc_eqe_resource_id_WORD word0 296 #define lpfc_eqe_minor_code_SHIFT 4 297 #define lpfc_eqe_minor_code_MASK 0x00000FFF 298 #define lpfc_eqe_minor_code_WORD word0 299 #define lpfc_eqe_major_code_SHIFT 1 300 #define lpfc_eqe_major_code_MASK 0x00000007 301 #define lpfc_eqe_major_code_WORD word0 302 #define lpfc_eqe_valid_SHIFT 0 303 #define lpfc_eqe_valid_MASK 0x00000001 304 #define lpfc_eqe_valid_WORD word0 305 }; 306 307 /* completion queue entry structure (common fields for all cqe types) */ 308 struct lpfc_cqe { 309 uint32_t reserved0; 310 uint32_t reserved1; 311 uint32_t reserved2; 312 uint32_t word3; 313 #define lpfc_cqe_valid_SHIFT 31 314 #define lpfc_cqe_valid_MASK 0x00000001 315 #define lpfc_cqe_valid_WORD word3 316 #define lpfc_cqe_code_SHIFT 16 317 #define lpfc_cqe_code_MASK 0x000000FF 318 #define lpfc_cqe_code_WORD word3 319 }; 320 321 /* Completion Queue Entry Status Codes */ 322 #define CQE_STATUS_SUCCESS 0x0 323 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 324 #define CQE_STATUS_REMOTE_STOP 0x2 325 #define CQE_STATUS_LOCAL_REJECT 0x3 326 #define CQE_STATUS_NPORT_RJT 0x4 327 #define CQE_STATUS_FABRIC_RJT 0x5 328 #define CQE_STATUS_NPORT_BSY 0x6 329 #define CQE_STATUS_FABRIC_BSY 0x7 330 #define CQE_STATUS_INTERMED_RSP 0x8 331 #define CQE_STATUS_LS_RJT 0x9 332 #define CQE_STATUS_CMD_REJECT 0xb 333 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 334 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 335 #define CQE_STATUS_DI_ERROR 0x16 336 337 /* Used when mapping CQE status to IOCB */ 338 #define LPFC_IOCB_STATUS_MASK 0xf 339 340 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 341 #define CQE_HW_STATUS_NO_ERR 0x0 342 #define CQE_HW_STATUS_UNDERRUN 0x1 343 #define CQE_HW_STATUS_OVERRUN 0x2 344 345 /* Completion Queue Entry Codes */ 346 #define CQE_CODE_COMPL_WQE 0x1 347 #define CQE_CODE_RELEASE_WQE 0x2 348 #define CQE_CODE_RECEIVE 0x4 349 #define CQE_CODE_XRI_ABORTED 0x5 350 #define CQE_CODE_RECEIVE_V1 0x9 351 352 /* 353 * Define mask value for xri_aborted and wcqe completed CQE extended status. 354 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 355 */ 356 #define WCQE_PARAM_MASK 0x1FF 357 358 /* completion queue entry for wqe completions */ 359 struct lpfc_wcqe_complete { 360 uint32_t word0; 361 #define lpfc_wcqe_c_request_tag_SHIFT 16 362 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 363 #define lpfc_wcqe_c_request_tag_WORD word0 364 #define lpfc_wcqe_c_status_SHIFT 8 365 #define lpfc_wcqe_c_status_MASK 0x000000FF 366 #define lpfc_wcqe_c_status_WORD word0 367 #define lpfc_wcqe_c_hw_status_SHIFT 0 368 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 369 #define lpfc_wcqe_c_hw_status_WORD word0 370 uint32_t total_data_placed; 371 uint32_t parameter; 372 #define lpfc_wcqe_c_bg_edir_SHIFT 5 373 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 374 #define lpfc_wcqe_c_bg_edir_WORD parameter 375 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 376 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 377 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 378 #define lpfc_wcqe_c_bg_re_SHIFT 2 379 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 380 #define lpfc_wcqe_c_bg_re_WORD parameter 381 #define lpfc_wcqe_c_bg_ae_SHIFT 1 382 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 383 #define lpfc_wcqe_c_bg_ae_WORD parameter 384 #define lpfc_wcqe_c_bg_ge_SHIFT 0 385 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 386 #define lpfc_wcqe_c_bg_ge_WORD parameter 387 uint32_t word3; 388 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 389 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 390 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 391 #define lpfc_wcqe_c_xb_SHIFT 28 392 #define lpfc_wcqe_c_xb_MASK 0x00000001 393 #define lpfc_wcqe_c_xb_WORD word3 394 #define lpfc_wcqe_c_pv_SHIFT 27 395 #define lpfc_wcqe_c_pv_MASK 0x00000001 396 #define lpfc_wcqe_c_pv_WORD word3 397 #define lpfc_wcqe_c_priority_SHIFT 24 398 #define lpfc_wcqe_c_priority_MASK 0x00000007 399 #define lpfc_wcqe_c_priority_WORD word3 400 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 401 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 402 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 403 }; 404 405 /* completion queue entry for wqe release */ 406 struct lpfc_wcqe_release { 407 uint32_t reserved0; 408 uint32_t reserved1; 409 uint32_t word2; 410 #define lpfc_wcqe_r_wq_id_SHIFT 16 411 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 412 #define lpfc_wcqe_r_wq_id_WORD word2 413 #define lpfc_wcqe_r_wqe_index_SHIFT 0 414 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 415 #define lpfc_wcqe_r_wqe_index_WORD word2 416 uint32_t word3; 417 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 418 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 419 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 420 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 421 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 422 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 423 }; 424 425 struct sli4_wcqe_xri_aborted { 426 uint32_t word0; 427 #define lpfc_wcqe_xa_status_SHIFT 8 428 #define lpfc_wcqe_xa_status_MASK 0x000000FF 429 #define lpfc_wcqe_xa_status_WORD word0 430 uint32_t parameter; 431 uint32_t word2; 432 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 433 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 434 #define lpfc_wcqe_xa_remote_xid_WORD word2 435 #define lpfc_wcqe_xa_xri_SHIFT 0 436 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 437 #define lpfc_wcqe_xa_xri_WORD word2 438 uint32_t word3; 439 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 440 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 441 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 442 #define lpfc_wcqe_xa_ia_SHIFT 30 443 #define lpfc_wcqe_xa_ia_MASK 0x00000001 444 #define lpfc_wcqe_xa_ia_WORD word3 445 #define CQE_XRI_ABORTED_IA_REMOTE 0 446 #define CQE_XRI_ABORTED_IA_LOCAL 1 447 #define lpfc_wcqe_xa_br_SHIFT 29 448 #define lpfc_wcqe_xa_br_MASK 0x00000001 449 #define lpfc_wcqe_xa_br_WORD word3 450 #define CQE_XRI_ABORTED_BR_BA_ACC 0 451 #define CQE_XRI_ABORTED_BR_BA_RJT 1 452 #define lpfc_wcqe_xa_eo_SHIFT 28 453 #define lpfc_wcqe_xa_eo_MASK 0x00000001 454 #define lpfc_wcqe_xa_eo_WORD word3 455 #define CQE_XRI_ABORTED_EO_REMOTE 0 456 #define CQE_XRI_ABORTED_EO_LOCAL 1 457 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 458 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 459 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 460 }; 461 462 /* completion queue entry structure for rqe completion */ 463 struct lpfc_rcqe { 464 uint32_t word0; 465 #define lpfc_rcqe_bindex_SHIFT 16 466 #define lpfc_rcqe_bindex_MASK 0x0000FFF 467 #define lpfc_rcqe_bindex_WORD word0 468 #define lpfc_rcqe_status_SHIFT 8 469 #define lpfc_rcqe_status_MASK 0x000000FF 470 #define lpfc_rcqe_status_WORD word0 471 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 472 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 473 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 474 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 475 uint32_t word1; 476 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 477 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 478 #define lpfc_rcqe_fcf_id_v1_WORD word1 479 uint32_t word2; 480 #define lpfc_rcqe_length_SHIFT 16 481 #define lpfc_rcqe_length_MASK 0x0000FFFF 482 #define lpfc_rcqe_length_WORD word2 483 #define lpfc_rcqe_rq_id_SHIFT 6 484 #define lpfc_rcqe_rq_id_MASK 0x000003FF 485 #define lpfc_rcqe_rq_id_WORD word2 486 #define lpfc_rcqe_fcf_id_SHIFT 0 487 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 488 #define lpfc_rcqe_fcf_id_WORD word2 489 #define lpfc_rcqe_rq_id_v1_SHIFT 0 490 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 491 #define lpfc_rcqe_rq_id_v1_WORD word2 492 uint32_t word3; 493 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 494 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 495 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 496 #define lpfc_rcqe_port_SHIFT 30 497 #define lpfc_rcqe_port_MASK 0x00000001 498 #define lpfc_rcqe_port_WORD word3 499 #define lpfc_rcqe_hdr_length_SHIFT 24 500 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 501 #define lpfc_rcqe_hdr_length_WORD word3 502 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 503 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 504 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 505 #define lpfc_rcqe_eof_SHIFT 8 506 #define lpfc_rcqe_eof_MASK 0x000000FF 507 #define lpfc_rcqe_eof_WORD word3 508 #define FCOE_EOFn 0x41 509 #define FCOE_EOFt 0x42 510 #define FCOE_EOFni 0x49 511 #define FCOE_EOFa 0x50 512 #define lpfc_rcqe_sof_SHIFT 0 513 #define lpfc_rcqe_sof_MASK 0x000000FF 514 #define lpfc_rcqe_sof_WORD word3 515 #define FCOE_SOFi2 0x2d 516 #define FCOE_SOFi3 0x2e 517 #define FCOE_SOFn2 0x35 518 #define FCOE_SOFn3 0x36 519 }; 520 521 struct lpfc_rqe { 522 uint32_t address_hi; 523 uint32_t address_lo; 524 }; 525 526 /* buffer descriptors */ 527 struct lpfc_bde4 { 528 uint32_t addr_hi; 529 uint32_t addr_lo; 530 uint32_t word2; 531 #define lpfc_bde4_last_SHIFT 31 532 #define lpfc_bde4_last_MASK 0x00000001 533 #define lpfc_bde4_last_WORD word2 534 #define lpfc_bde4_sge_offset_SHIFT 0 535 #define lpfc_bde4_sge_offset_MASK 0x000003FF 536 #define lpfc_bde4_sge_offset_WORD word2 537 uint32_t word3; 538 #define lpfc_bde4_length_SHIFT 0 539 #define lpfc_bde4_length_MASK 0x000000FF 540 #define lpfc_bde4_length_WORD word3 541 }; 542 543 struct lpfc_register { 544 uint32_t word0; 545 }; 546 547 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 548 #define LPFC_UERR_STATUS_HI 0x00A4 549 #define LPFC_UERR_STATUS_LO 0x00A0 550 #define LPFC_UE_MASK_HI 0x00AC 551 #define LPFC_UE_MASK_LO 0x00A8 552 553 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 554 #define LPFC_SLI_INTF 0x0058 555 556 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 557 #define lpfc_port_smphr_perr_SHIFT 31 558 #define lpfc_port_smphr_perr_MASK 0x1 559 #define lpfc_port_smphr_perr_WORD word0 560 #define lpfc_port_smphr_sfi_SHIFT 30 561 #define lpfc_port_smphr_sfi_MASK 0x1 562 #define lpfc_port_smphr_sfi_WORD word0 563 #define lpfc_port_smphr_nip_SHIFT 29 564 #define lpfc_port_smphr_nip_MASK 0x1 565 #define lpfc_port_smphr_nip_WORD word0 566 #define lpfc_port_smphr_ipc_SHIFT 28 567 #define lpfc_port_smphr_ipc_MASK 0x1 568 #define lpfc_port_smphr_ipc_WORD word0 569 #define lpfc_port_smphr_scr1_SHIFT 27 570 #define lpfc_port_smphr_scr1_MASK 0x1 571 #define lpfc_port_smphr_scr1_WORD word0 572 #define lpfc_port_smphr_scr2_SHIFT 26 573 #define lpfc_port_smphr_scr2_MASK 0x1 574 #define lpfc_port_smphr_scr2_WORD word0 575 #define lpfc_port_smphr_host_scratch_SHIFT 16 576 #define lpfc_port_smphr_host_scratch_MASK 0xFF 577 #define lpfc_port_smphr_host_scratch_WORD word0 578 #define lpfc_port_smphr_port_status_SHIFT 0 579 #define lpfc_port_smphr_port_status_MASK 0xFFFF 580 #define lpfc_port_smphr_port_status_WORD word0 581 582 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 583 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 584 #define LPFC_POST_STAGE_HOST_RDY 0x0002 585 #define LPFC_POST_STAGE_BE_RESET 0x0003 586 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 587 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 588 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 589 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 590 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 591 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 592 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 593 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 594 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 595 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 596 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 597 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 598 #define LPFC_POST_STAGE_ARMFW_START 0x0800 599 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 600 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 601 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 602 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 603 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 604 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 605 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 606 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 607 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 608 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 609 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 610 #define LPFC_POST_STAGE_RC_DONE 0x0B07 611 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 612 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 613 #define LPFC_POST_STAGE_PORT_READY 0xC000 614 #define LPFC_POST_STAGE_PORT_UE 0xF000 615 616 #define LPFC_CTL_PORT_STA_OFFSET 0x404 617 #define lpfc_sliport_status_err_SHIFT 31 618 #define lpfc_sliport_status_err_MASK 0x1 619 #define lpfc_sliport_status_err_WORD word0 620 #define lpfc_sliport_status_end_SHIFT 30 621 #define lpfc_sliport_status_end_MASK 0x1 622 #define lpfc_sliport_status_end_WORD word0 623 #define lpfc_sliport_status_oti_SHIFT 29 624 #define lpfc_sliport_status_oti_MASK 0x1 625 #define lpfc_sliport_status_oti_WORD word0 626 #define lpfc_sliport_status_rn_SHIFT 24 627 #define lpfc_sliport_status_rn_MASK 0x1 628 #define lpfc_sliport_status_rn_WORD word0 629 #define lpfc_sliport_status_rdy_SHIFT 23 630 #define lpfc_sliport_status_rdy_MASK 0x1 631 #define lpfc_sliport_status_rdy_WORD word0 632 #define MAX_IF_TYPE_2_RESETS 6 633 634 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 635 #define lpfc_sliport_ctrl_end_SHIFT 30 636 #define lpfc_sliport_ctrl_end_MASK 0x1 637 #define lpfc_sliport_ctrl_end_WORD word0 638 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 639 #define LPFC_SLIPORT_BIG_ENDIAN 1 640 #define lpfc_sliport_ctrl_ip_SHIFT 27 641 #define lpfc_sliport_ctrl_ip_MASK 0x1 642 #define lpfc_sliport_ctrl_ip_WORD word0 643 #define LPFC_SLIPORT_INIT_PORT 1 644 645 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 646 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 647 648 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 649 * reside in BAR 2. 650 */ 651 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 652 653 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 654 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 655 656 #define LPFC_HST_ISR0 0x0C18 657 #define LPFC_HST_ISR1 0x0C1C 658 #define LPFC_HST_ISR2 0x0C20 659 #define LPFC_HST_ISR3 0x0C24 660 #define LPFC_HST_ISR4 0x0C28 661 662 #define LPFC_HST_IMR0 0x0C48 663 #define LPFC_HST_IMR1 0x0C4C 664 #define LPFC_HST_IMR2 0x0C50 665 #define LPFC_HST_IMR3 0x0C54 666 #define LPFC_HST_IMR4 0x0C58 667 668 #define LPFC_HST_ISCR0 0x0C78 669 #define LPFC_HST_ISCR1 0x0C7C 670 #define LPFC_HST_ISCR2 0x0C80 671 #define LPFC_HST_ISCR3 0x0C84 672 #define LPFC_HST_ISCR4 0x0C88 673 674 #define LPFC_SLI4_INTR0 BIT0 675 #define LPFC_SLI4_INTR1 BIT1 676 #define LPFC_SLI4_INTR2 BIT2 677 #define LPFC_SLI4_INTR3 BIT3 678 #define LPFC_SLI4_INTR4 BIT4 679 #define LPFC_SLI4_INTR5 BIT5 680 #define LPFC_SLI4_INTR6 BIT6 681 #define LPFC_SLI4_INTR7 BIT7 682 #define LPFC_SLI4_INTR8 BIT8 683 #define LPFC_SLI4_INTR9 BIT9 684 #define LPFC_SLI4_INTR10 BIT10 685 #define LPFC_SLI4_INTR11 BIT11 686 #define LPFC_SLI4_INTR12 BIT12 687 #define LPFC_SLI4_INTR13 BIT13 688 #define LPFC_SLI4_INTR14 BIT14 689 #define LPFC_SLI4_INTR15 BIT15 690 #define LPFC_SLI4_INTR16 BIT16 691 #define LPFC_SLI4_INTR17 BIT17 692 #define LPFC_SLI4_INTR18 BIT18 693 #define LPFC_SLI4_INTR19 BIT19 694 #define LPFC_SLI4_INTR20 BIT20 695 #define LPFC_SLI4_INTR21 BIT21 696 #define LPFC_SLI4_INTR22 BIT22 697 #define LPFC_SLI4_INTR23 BIT23 698 #define LPFC_SLI4_INTR24 BIT24 699 #define LPFC_SLI4_INTR25 BIT25 700 #define LPFC_SLI4_INTR26 BIT26 701 #define LPFC_SLI4_INTR27 BIT27 702 #define LPFC_SLI4_INTR28 BIT28 703 #define LPFC_SLI4_INTR29 BIT29 704 #define LPFC_SLI4_INTR30 BIT30 705 #define LPFC_SLI4_INTR31 BIT31 706 707 /* 708 * The Doorbell registers defined here exist in different BAR 709 * register sets depending on the UCNA Port's reported if_type 710 * value. For UCNA ports running SLI4 and if_type 0, they reside in 711 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 712 * BAR0. The offsets are the same so the driver must account for 713 * any base address difference. 714 */ 715 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 716 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 717 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 718 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 719 #define lpfc_rq_db_list_fm_num_posted_WORD word0 720 #define lpfc_rq_db_list_fm_index_SHIFT 16 721 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 722 #define lpfc_rq_db_list_fm_index_WORD word0 723 #define lpfc_rq_db_list_fm_id_SHIFT 0 724 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 725 #define lpfc_rq_db_list_fm_id_WORD word0 726 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 727 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 728 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 729 #define lpfc_rq_db_ring_fm_id_SHIFT 0 730 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 731 #define lpfc_rq_db_ring_fm_id_WORD word0 732 733 #define LPFC_ULP0_WQ_DOORBELL 0x0040 734 #define LPFC_ULP1_WQ_DOORBELL 0x0060 735 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 736 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 737 #define lpfc_wq_db_list_fm_num_posted_WORD word0 738 #define lpfc_wq_db_list_fm_index_SHIFT 16 739 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 740 #define lpfc_wq_db_list_fm_index_WORD word0 741 #define lpfc_wq_db_list_fm_id_SHIFT 0 742 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 743 #define lpfc_wq_db_list_fm_id_WORD word0 744 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 745 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 746 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 747 #define lpfc_wq_db_ring_fm_id_SHIFT 0 748 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 749 #define lpfc_wq_db_ring_fm_id_WORD word0 750 751 #define LPFC_EQCQ_DOORBELL 0x0120 752 #define lpfc_eqcq_doorbell_se_SHIFT 31 753 #define lpfc_eqcq_doorbell_se_MASK 0x0001 754 #define lpfc_eqcq_doorbell_se_WORD word0 755 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 756 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 757 #define lpfc_eqcq_doorbell_arm_SHIFT 29 758 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 759 #define lpfc_eqcq_doorbell_arm_WORD word0 760 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 761 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 762 #define lpfc_eqcq_doorbell_num_released_WORD word0 763 #define lpfc_eqcq_doorbell_qt_SHIFT 10 764 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 765 #define lpfc_eqcq_doorbell_qt_WORD word0 766 #define LPFC_QUEUE_TYPE_COMPLETION 0 767 #define LPFC_QUEUE_TYPE_EVENT 1 768 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 769 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 770 #define lpfc_eqcq_doorbell_eqci_WORD word0 771 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 772 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 773 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 774 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 775 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 776 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 777 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 778 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 779 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 780 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 781 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 782 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 783 #define LPFC_CQID_HI_FIELD_SHIFT 10 784 #define LPFC_EQID_HI_FIELD_SHIFT 9 785 786 #define LPFC_BMBX 0x0160 787 #define lpfc_bmbx_addr_SHIFT 2 788 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 789 #define lpfc_bmbx_addr_WORD word0 790 #define lpfc_bmbx_hi_SHIFT 1 791 #define lpfc_bmbx_hi_MASK 0x0001 792 #define lpfc_bmbx_hi_WORD word0 793 #define lpfc_bmbx_rdy_SHIFT 0 794 #define lpfc_bmbx_rdy_MASK 0x0001 795 #define lpfc_bmbx_rdy_WORD word0 796 797 #define LPFC_MQ_DOORBELL 0x0140 798 #define lpfc_mq_doorbell_num_posted_SHIFT 16 799 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 800 #define lpfc_mq_doorbell_num_posted_WORD word0 801 #define lpfc_mq_doorbell_id_SHIFT 0 802 #define lpfc_mq_doorbell_id_MASK 0xFFFF 803 #define lpfc_mq_doorbell_id_WORD word0 804 805 struct lpfc_sli4_cfg_mhdr { 806 uint32_t word1; 807 #define lpfc_mbox_hdr_emb_SHIFT 0 808 #define lpfc_mbox_hdr_emb_MASK 0x00000001 809 #define lpfc_mbox_hdr_emb_WORD word1 810 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 811 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 812 #define lpfc_mbox_hdr_sge_cnt_WORD word1 813 uint32_t payload_length; 814 uint32_t tag_lo; 815 uint32_t tag_hi; 816 uint32_t reserved5; 817 }; 818 819 union lpfc_sli4_cfg_shdr { 820 struct { 821 uint32_t word6; 822 #define lpfc_mbox_hdr_opcode_SHIFT 0 823 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 824 #define lpfc_mbox_hdr_opcode_WORD word6 825 #define lpfc_mbox_hdr_subsystem_SHIFT 8 826 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 827 #define lpfc_mbox_hdr_subsystem_WORD word6 828 #define lpfc_mbox_hdr_port_number_SHIFT 16 829 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 830 #define lpfc_mbox_hdr_port_number_WORD word6 831 #define lpfc_mbox_hdr_domain_SHIFT 24 832 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 833 #define lpfc_mbox_hdr_domain_WORD word6 834 uint32_t timeout; 835 uint32_t request_length; 836 uint32_t word9; 837 #define lpfc_mbox_hdr_version_SHIFT 0 838 #define lpfc_mbox_hdr_version_MASK 0x000000FF 839 #define lpfc_mbox_hdr_version_WORD word9 840 #define lpfc_mbox_hdr_pf_num_SHIFT 16 841 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 842 #define lpfc_mbox_hdr_pf_num_WORD word9 843 #define lpfc_mbox_hdr_vh_num_SHIFT 24 844 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 845 #define lpfc_mbox_hdr_vh_num_WORD word9 846 #define LPFC_Q_CREATE_VERSION_2 2 847 #define LPFC_Q_CREATE_VERSION_1 1 848 #define LPFC_Q_CREATE_VERSION_0 0 849 #define LPFC_OPCODE_VERSION_0 0 850 #define LPFC_OPCODE_VERSION_1 1 851 } request; 852 struct { 853 uint32_t word6; 854 #define lpfc_mbox_hdr_opcode_SHIFT 0 855 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 856 #define lpfc_mbox_hdr_opcode_WORD word6 857 #define lpfc_mbox_hdr_subsystem_SHIFT 8 858 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 859 #define lpfc_mbox_hdr_subsystem_WORD word6 860 #define lpfc_mbox_hdr_domain_SHIFT 24 861 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 862 #define lpfc_mbox_hdr_domain_WORD word6 863 uint32_t word7; 864 #define lpfc_mbox_hdr_status_SHIFT 0 865 #define lpfc_mbox_hdr_status_MASK 0x000000FF 866 #define lpfc_mbox_hdr_status_WORD word7 867 #define lpfc_mbox_hdr_add_status_SHIFT 8 868 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 869 #define lpfc_mbox_hdr_add_status_WORD word7 870 uint32_t response_length; 871 uint32_t actual_response_length; 872 } response; 873 }; 874 875 /* Mailbox Header structures. 876 * struct mbox_header is defined for first generation SLI4_CFG mailbox 877 * calls deployed for BE-based ports. 878 * 879 * struct sli4_mbox_header is defined for second generation SLI4 880 * ports that don't deploy the SLI4_CFG mechanism. 881 */ 882 struct mbox_header { 883 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 884 union lpfc_sli4_cfg_shdr cfg_shdr; 885 }; 886 887 #define LPFC_EXTENT_LOCAL 0 888 #define LPFC_TIMEOUT_DEFAULT 0 889 #define LPFC_EXTENT_VERSION_DEFAULT 0 890 891 /* Subsystem Definitions */ 892 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 893 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 894 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 895 896 /* Device Specific Definitions */ 897 898 /* The HOST ENDIAN defines are in Big Endian format. */ 899 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 900 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 901 902 /* Common Opcodes */ 903 #define LPFC_MBOX_OPCODE_NA 0x00 904 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 905 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 906 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 907 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 908 #define LPFC_MBOX_OPCODE_NOP 0x21 909 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 910 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 911 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 912 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 913 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 914 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 915 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 916 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 917 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 918 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 919 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 920 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 921 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 922 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 923 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 924 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 925 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 926 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 927 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 928 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 929 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 930 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 931 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 932 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 933 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 934 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 935 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 936 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 937 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 938 939 /* FCoE Opcodes */ 940 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 941 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 942 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 943 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 944 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 945 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 946 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 947 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 948 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 949 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 950 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 951 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 952 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 953 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 954 955 /* Mailbox command structures */ 956 struct eq_context { 957 uint32_t word0; 958 #define lpfc_eq_context_size_SHIFT 31 959 #define lpfc_eq_context_size_MASK 0x00000001 960 #define lpfc_eq_context_size_WORD word0 961 #define LPFC_EQE_SIZE_4 0x0 962 #define LPFC_EQE_SIZE_16 0x1 963 #define lpfc_eq_context_valid_SHIFT 29 964 #define lpfc_eq_context_valid_MASK 0x00000001 965 #define lpfc_eq_context_valid_WORD word0 966 uint32_t word1; 967 #define lpfc_eq_context_count_SHIFT 26 968 #define lpfc_eq_context_count_MASK 0x00000003 969 #define lpfc_eq_context_count_WORD word1 970 #define LPFC_EQ_CNT_256 0x0 971 #define LPFC_EQ_CNT_512 0x1 972 #define LPFC_EQ_CNT_1024 0x2 973 #define LPFC_EQ_CNT_2048 0x3 974 #define LPFC_EQ_CNT_4096 0x4 975 uint32_t word2; 976 #define lpfc_eq_context_delay_multi_SHIFT 13 977 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 978 #define lpfc_eq_context_delay_multi_WORD word2 979 uint32_t reserved3; 980 }; 981 982 struct eq_delay_info { 983 uint32_t eq_id; 984 uint32_t phase; 985 uint32_t delay_multi; 986 }; 987 #define LPFC_MAX_EQ_DELAY 8 988 989 struct sgl_page_pairs { 990 uint32_t sgl_pg0_addr_lo; 991 uint32_t sgl_pg0_addr_hi; 992 uint32_t sgl_pg1_addr_lo; 993 uint32_t sgl_pg1_addr_hi; 994 }; 995 996 struct lpfc_mbx_post_sgl_pages { 997 struct mbox_header header; 998 uint32_t word0; 999 #define lpfc_post_sgl_pages_xri_SHIFT 0 1000 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1001 #define lpfc_post_sgl_pages_xri_WORD word0 1002 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1003 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1004 #define lpfc_post_sgl_pages_xricnt_WORD word0 1005 struct sgl_page_pairs sgl_pg_pairs[1]; 1006 }; 1007 1008 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1009 struct lpfc_mbx_post_uembed_sgl_page1 { 1010 union lpfc_sli4_cfg_shdr cfg_shdr; 1011 uint32_t word0; 1012 struct sgl_page_pairs sgl_pg_pairs; 1013 }; 1014 1015 struct lpfc_mbx_sge { 1016 uint32_t pa_lo; 1017 uint32_t pa_hi; 1018 uint32_t length; 1019 }; 1020 1021 struct lpfc_mbx_nembed_cmd { 1022 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1023 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1024 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1025 }; 1026 1027 struct lpfc_mbx_nembed_sge_virt { 1028 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1029 }; 1030 1031 struct lpfc_mbx_eq_create { 1032 struct mbox_header header; 1033 union { 1034 struct { 1035 uint32_t word0; 1036 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1037 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1038 #define lpfc_mbx_eq_create_num_pages_WORD word0 1039 struct eq_context context; 1040 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1041 } request; 1042 struct { 1043 uint32_t word0; 1044 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1045 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1046 #define lpfc_mbx_eq_create_q_id_WORD word0 1047 } response; 1048 } u; 1049 }; 1050 1051 struct lpfc_mbx_modify_eq_delay { 1052 struct mbox_header header; 1053 union { 1054 struct { 1055 uint32_t num_eq; 1056 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY]; 1057 } request; 1058 struct { 1059 uint32_t word0; 1060 } response; 1061 } u; 1062 }; 1063 1064 struct lpfc_mbx_eq_destroy { 1065 struct mbox_header header; 1066 union { 1067 struct { 1068 uint32_t word0; 1069 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1070 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1071 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1072 } request; 1073 struct { 1074 uint32_t word0; 1075 } response; 1076 } u; 1077 }; 1078 1079 struct lpfc_mbx_nop { 1080 struct mbox_header header; 1081 uint32_t context[2]; 1082 }; 1083 1084 struct cq_context { 1085 uint32_t word0; 1086 #define lpfc_cq_context_event_SHIFT 31 1087 #define lpfc_cq_context_event_MASK 0x00000001 1088 #define lpfc_cq_context_event_WORD word0 1089 #define lpfc_cq_context_valid_SHIFT 29 1090 #define lpfc_cq_context_valid_MASK 0x00000001 1091 #define lpfc_cq_context_valid_WORD word0 1092 #define lpfc_cq_context_count_SHIFT 27 1093 #define lpfc_cq_context_count_MASK 0x00000003 1094 #define lpfc_cq_context_count_WORD word0 1095 #define LPFC_CQ_CNT_256 0x0 1096 #define LPFC_CQ_CNT_512 0x1 1097 #define LPFC_CQ_CNT_1024 0x2 1098 uint32_t word1; 1099 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1100 #define lpfc_cq_eq_id_MASK 0x000000FF 1101 #define lpfc_cq_eq_id_WORD word1 1102 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1103 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1104 #define lpfc_cq_eq_id_2_WORD word1 1105 uint32_t reserved0; 1106 uint32_t reserved1; 1107 }; 1108 1109 struct lpfc_mbx_cq_create { 1110 struct mbox_header header; 1111 union { 1112 struct { 1113 uint32_t word0; 1114 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1115 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1116 #define lpfc_mbx_cq_create_page_size_WORD word0 1117 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1118 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1119 #define lpfc_mbx_cq_create_num_pages_WORD word0 1120 struct cq_context context; 1121 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1122 } request; 1123 struct { 1124 uint32_t word0; 1125 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1126 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1127 #define lpfc_mbx_cq_create_q_id_WORD word0 1128 } response; 1129 } u; 1130 }; 1131 1132 struct lpfc_mbx_cq_destroy { 1133 struct mbox_header header; 1134 union { 1135 struct { 1136 uint32_t word0; 1137 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1138 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1139 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1140 } request; 1141 struct { 1142 uint32_t word0; 1143 } response; 1144 } u; 1145 }; 1146 1147 struct wq_context { 1148 uint32_t reserved0; 1149 uint32_t reserved1; 1150 uint32_t reserved2; 1151 uint32_t reserved3; 1152 }; 1153 1154 struct lpfc_mbx_wq_create { 1155 struct mbox_header header; 1156 union { 1157 struct { /* Version 0 Request */ 1158 uint32_t word0; 1159 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1160 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1161 #define lpfc_mbx_wq_create_num_pages_WORD word0 1162 #define lpfc_mbx_wq_create_dua_SHIFT 8 1163 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1164 #define lpfc_mbx_wq_create_dua_WORD word0 1165 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1166 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1167 #define lpfc_mbx_wq_create_cq_id_WORD word0 1168 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1169 uint32_t word9; 1170 #define lpfc_mbx_wq_create_bua_SHIFT 0 1171 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1172 #define lpfc_mbx_wq_create_bua_WORD word9 1173 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1174 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1175 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1176 } request; 1177 struct { /* Version 1 Request */ 1178 uint32_t word0; /* Word 0 is the same as in v0 */ 1179 uint32_t word1; 1180 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1181 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1182 #define lpfc_mbx_wq_create_page_size_WORD word1 1183 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1184 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1185 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1186 #define LPFC_WQ_WQE_SIZE_64 0x5 1187 #define LPFC_WQ_WQE_SIZE_128 0x6 1188 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1189 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1190 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1191 uint32_t word2; 1192 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1193 } request_1; 1194 struct { 1195 uint32_t word0; 1196 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1197 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1198 #define lpfc_mbx_wq_create_q_id_WORD word0 1199 uint32_t doorbell_offset; 1200 uint32_t word2; 1201 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1202 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1203 #define lpfc_mbx_wq_create_bar_set_WORD word2 1204 #define WQ_PCI_BAR_0_AND_1 0x00 1205 #define WQ_PCI_BAR_2_AND_3 0x01 1206 #define WQ_PCI_BAR_4_AND_5 0x02 1207 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1208 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1209 #define lpfc_mbx_wq_create_db_format_WORD word2 1210 } response; 1211 } u; 1212 }; 1213 1214 struct lpfc_mbx_wq_destroy { 1215 struct mbox_header header; 1216 union { 1217 struct { 1218 uint32_t word0; 1219 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1220 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1221 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1222 } request; 1223 struct { 1224 uint32_t word0; 1225 } response; 1226 } u; 1227 }; 1228 1229 #define LPFC_HDR_BUF_SIZE 128 1230 #define LPFC_DATA_BUF_SIZE 2048 1231 struct rq_context { 1232 uint32_t word0; 1233 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1234 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1235 #define lpfc_rq_context_rqe_count_WORD word0 1236 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1237 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1238 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1239 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1240 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1241 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1242 #define lpfc_rq_context_rqe_count_1_WORD word0 1243 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1244 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1245 #define lpfc_rq_context_rqe_size_WORD word0 1246 #define LPFC_RQE_SIZE_8 2 1247 #define LPFC_RQE_SIZE_16 3 1248 #define LPFC_RQE_SIZE_32 4 1249 #define LPFC_RQE_SIZE_64 5 1250 #define LPFC_RQE_SIZE_128 6 1251 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1252 #define lpfc_rq_context_page_size_MASK 0x000000FF 1253 #define lpfc_rq_context_page_size_WORD word0 1254 uint32_t reserved1; 1255 uint32_t word2; 1256 #define lpfc_rq_context_cq_id_SHIFT 16 1257 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1258 #define lpfc_rq_context_cq_id_WORD word2 1259 #define lpfc_rq_context_buf_size_SHIFT 0 1260 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1261 #define lpfc_rq_context_buf_size_WORD word2 1262 uint32_t buffer_size; /* Version 1 Only */ 1263 }; 1264 1265 struct lpfc_mbx_rq_create { 1266 struct mbox_header header; 1267 union { 1268 struct { 1269 uint32_t word0; 1270 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1271 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1272 #define lpfc_mbx_rq_create_num_pages_WORD word0 1273 #define lpfc_mbx_rq_create_dua_SHIFT 16 1274 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1275 #define lpfc_mbx_rq_create_dua_WORD word0 1276 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1277 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1278 #define lpfc_mbx_rq_create_bqu_WORD word0 1279 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1280 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1281 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1282 struct rq_context context; 1283 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1284 } request; 1285 struct { 1286 uint32_t word0; 1287 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1288 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1289 #define lpfc_mbx_rq_create_q_id_WORD word0 1290 uint32_t doorbell_offset; 1291 uint32_t word2; 1292 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1293 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1294 #define lpfc_mbx_rq_create_bar_set_WORD word2 1295 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1296 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1297 #define lpfc_mbx_rq_create_db_format_WORD word2 1298 } response; 1299 } u; 1300 }; 1301 1302 struct lpfc_mbx_rq_destroy { 1303 struct mbox_header header; 1304 union { 1305 struct { 1306 uint32_t word0; 1307 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1308 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1309 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1310 } request; 1311 struct { 1312 uint32_t word0; 1313 } response; 1314 } u; 1315 }; 1316 1317 struct mq_context { 1318 uint32_t word0; 1319 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1320 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1321 #define lpfc_mq_context_cq_id_WORD word0 1322 #define lpfc_mq_context_ring_size_SHIFT 16 1323 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1324 #define lpfc_mq_context_ring_size_WORD word0 1325 #define LPFC_MQ_RING_SIZE_16 0x5 1326 #define LPFC_MQ_RING_SIZE_32 0x6 1327 #define LPFC_MQ_RING_SIZE_64 0x7 1328 #define LPFC_MQ_RING_SIZE_128 0x8 1329 uint32_t word1; 1330 #define lpfc_mq_context_valid_SHIFT 31 1331 #define lpfc_mq_context_valid_MASK 0x00000001 1332 #define lpfc_mq_context_valid_WORD word1 1333 uint32_t reserved2; 1334 uint32_t reserved3; 1335 }; 1336 1337 struct lpfc_mbx_mq_create { 1338 struct mbox_header header; 1339 union { 1340 struct { 1341 uint32_t word0; 1342 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1343 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1344 #define lpfc_mbx_mq_create_num_pages_WORD word0 1345 struct mq_context context; 1346 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1347 } request; 1348 struct { 1349 uint32_t word0; 1350 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1351 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1352 #define lpfc_mbx_mq_create_q_id_WORD word0 1353 } response; 1354 } u; 1355 }; 1356 1357 struct lpfc_mbx_mq_create_ext { 1358 struct mbox_header header; 1359 union { 1360 struct { 1361 uint32_t word0; 1362 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1363 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1364 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1365 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1366 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1367 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1368 uint32_t async_evt_bmap; 1369 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1370 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1371 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1372 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1373 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1374 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1375 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1376 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1377 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1378 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1379 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1380 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1381 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1382 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1383 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1384 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1385 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1386 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1387 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1388 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1389 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1390 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1391 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1392 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1393 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1394 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1395 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1396 struct mq_context context; 1397 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1398 } request; 1399 struct { 1400 uint32_t word0; 1401 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1402 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1403 #define lpfc_mbx_mq_create_q_id_WORD word0 1404 } response; 1405 } u; 1406 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1407 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1408 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1409 }; 1410 1411 struct lpfc_mbx_mq_destroy { 1412 struct mbox_header header; 1413 union { 1414 struct { 1415 uint32_t word0; 1416 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1417 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1418 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1419 } request; 1420 struct { 1421 uint32_t word0; 1422 } response; 1423 } u; 1424 }; 1425 1426 /* Start Gen 2 SLI4 Mailbox definitions: */ 1427 1428 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1429 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1430 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1431 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1432 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1433 1434 struct lpfc_mbx_get_rsrc_extent_info { 1435 struct mbox_header header; 1436 union { 1437 struct { 1438 uint32_t word4; 1439 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1440 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1441 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1442 } req; 1443 struct { 1444 uint32_t word4; 1445 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1446 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1447 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1448 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1449 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1450 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1451 } rsp; 1452 } u; 1453 }; 1454 1455 struct lpfc_mbx_query_fw_config { 1456 struct mbox_header header; 1457 struct { 1458 uint32_t config_number; 1459 #define LPFC_FC_FCOE 0x00000007 1460 uint32_t asic_revision; 1461 uint32_t physical_port; 1462 uint32_t function_mode; 1463 #define LPFC_FCOE_INI_MODE 0x00000040 1464 #define LPFC_FCOE_TGT_MODE 0x00000080 1465 #define LPFC_DUA_MODE 0x00000800 1466 uint32_t ulp0_mode; 1467 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1468 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1469 uint32_t ulp0_nap_words[12]; 1470 uint32_t ulp1_mode; 1471 uint32_t ulp1_nap_words[12]; 1472 uint32_t function_capabilities; 1473 uint32_t cqid_base; 1474 uint32_t cqid_tot; 1475 uint32_t eqid_base; 1476 uint32_t eqid_tot; 1477 uint32_t ulp0_nap2_words[2]; 1478 uint32_t ulp1_nap2_words[2]; 1479 } rsp; 1480 }; 1481 1482 struct lpfc_id_range { 1483 uint32_t word5; 1484 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1485 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1486 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1487 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1488 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1489 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1490 }; 1491 1492 struct lpfc_mbx_set_link_diag_state { 1493 struct mbox_header header; 1494 union { 1495 struct { 1496 uint32_t word0; 1497 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1498 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1499 #define lpfc_mbx_set_diag_state_diag_WORD word0 1500 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1501 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1502 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1503 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1504 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1505 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1506 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1507 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1508 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1509 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1510 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1511 } req; 1512 struct { 1513 uint32_t word0; 1514 } rsp; 1515 } u; 1516 }; 1517 1518 struct lpfc_mbx_set_link_diag_loopback { 1519 struct mbox_header header; 1520 union { 1521 struct { 1522 uint32_t word0; 1523 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1524 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1525 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1526 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1527 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1528 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1529 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1530 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1531 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1532 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1533 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1534 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1535 } req; 1536 struct { 1537 uint32_t word0; 1538 } rsp; 1539 } u; 1540 }; 1541 1542 struct lpfc_mbx_run_link_diag_test { 1543 struct mbox_header header; 1544 union { 1545 struct { 1546 uint32_t word0; 1547 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1548 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1549 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1550 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1551 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1552 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1553 uint32_t word1; 1554 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1555 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1556 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1557 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1558 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1559 #define lpfc_mbx_run_diag_test_loops_WORD word1 1560 uint32_t word2; 1561 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1562 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1563 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1564 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1565 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1566 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1567 } req; 1568 struct { 1569 uint32_t word0; 1570 } rsp; 1571 } u; 1572 }; 1573 1574 /* 1575 * struct lpfc_mbx_alloc_rsrc_extents: 1576 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1577 * 6 words of header + 4 words of shared subcommand header + 1578 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1579 * 1580 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1581 * for extents payload. 1582 * 1583 * 212/2 (bytes per extent) = 106 extents. 1584 * 106/2 (extents per word) = 53 words. 1585 * lpfc_id_range id is statically size to 53. 1586 * 1587 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1588 * extent ranges. For ALLOC, the type and cnt are required. 1589 * For GET_ALLOCATED, only the type is required. 1590 */ 1591 struct lpfc_mbx_alloc_rsrc_extents { 1592 struct mbox_header header; 1593 union { 1594 struct { 1595 uint32_t word4; 1596 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1597 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1598 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1599 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1600 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1601 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1602 } req; 1603 struct { 1604 uint32_t word4; 1605 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1606 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1607 #define lpfc_mbx_rsrc_cnt_WORD word4 1608 struct lpfc_id_range id[53]; 1609 } rsp; 1610 } u; 1611 }; 1612 1613 /* 1614 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1615 * structure shares the same SHIFT/MASK/WORD defines provided in the 1616 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1617 * the structures defined above. This non-embedded structure provides for the 1618 * maximum number of extents supported by the port. 1619 */ 1620 struct lpfc_mbx_nembed_rsrc_extent { 1621 union lpfc_sli4_cfg_shdr cfg_shdr; 1622 uint32_t word4; 1623 struct lpfc_id_range id; 1624 }; 1625 1626 struct lpfc_mbx_dealloc_rsrc_extents { 1627 struct mbox_header header; 1628 struct { 1629 uint32_t word4; 1630 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1631 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1632 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1633 } req; 1634 1635 }; 1636 1637 /* Start SLI4 FCoE specific mbox structures. */ 1638 1639 struct lpfc_mbx_post_hdr_tmpl { 1640 struct mbox_header header; 1641 uint32_t word10; 1642 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1643 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1644 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1645 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1646 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1647 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1648 uint32_t rpi_paddr_lo; 1649 uint32_t rpi_paddr_hi; 1650 }; 1651 1652 struct sli4_sge { /* SLI-4 */ 1653 uint32_t addr_hi; 1654 uint32_t addr_lo; 1655 1656 uint32_t word2; 1657 #define lpfc_sli4_sge_offset_SHIFT 0 1658 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1659 #define lpfc_sli4_sge_offset_WORD word2 1660 #define lpfc_sli4_sge_type_SHIFT 27 1661 #define lpfc_sli4_sge_type_MASK 0x0000000F 1662 #define lpfc_sli4_sge_type_WORD word2 1663 #define LPFC_SGE_TYPE_DATA 0x0 1664 #define LPFC_SGE_TYPE_DIF 0x4 1665 #define LPFC_SGE_TYPE_LSP 0x5 1666 #define LPFC_SGE_TYPE_PEDIF 0x6 1667 #define LPFC_SGE_TYPE_PESEED 0x7 1668 #define LPFC_SGE_TYPE_DISEED 0x8 1669 #define LPFC_SGE_TYPE_ENC 0x9 1670 #define LPFC_SGE_TYPE_ATM 0xA 1671 #define LPFC_SGE_TYPE_SKIP 0xC 1672 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1673 #define lpfc_sli4_sge_last_MASK 0x00000001 1674 #define lpfc_sli4_sge_last_WORD word2 1675 uint32_t sge_len; 1676 }; 1677 1678 struct sli4_sge_diseed { /* SLI-4 */ 1679 uint32_t ref_tag; 1680 uint32_t ref_tag_tran; 1681 1682 uint32_t word2; 1683 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1684 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1685 #define lpfc_sli4_sge_dif_apptran_WORD word2 1686 #define lpfc_sli4_sge_dif_af_SHIFT 24 1687 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1688 #define lpfc_sli4_sge_dif_af_WORD word2 1689 #define lpfc_sli4_sge_dif_na_SHIFT 25 1690 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1691 #define lpfc_sli4_sge_dif_na_WORD word2 1692 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1693 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1694 #define lpfc_sli4_sge_dif_hi_WORD word2 1695 #define lpfc_sli4_sge_dif_type_SHIFT 27 1696 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1697 #define lpfc_sli4_sge_dif_type_WORD word2 1698 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1699 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1700 #define lpfc_sli4_sge_dif_last_WORD word2 1701 uint32_t word3; 1702 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1703 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1704 #define lpfc_sli4_sge_dif_apptag_WORD word3 1705 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1706 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1707 #define lpfc_sli4_sge_dif_bs_WORD word3 1708 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1709 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1710 #define lpfc_sli4_sge_dif_ai_WORD word3 1711 #define lpfc_sli4_sge_dif_me_SHIFT 20 1712 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1713 #define lpfc_sli4_sge_dif_me_WORD word3 1714 #define lpfc_sli4_sge_dif_re_SHIFT 21 1715 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1716 #define lpfc_sli4_sge_dif_re_WORD word3 1717 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1718 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1719 #define lpfc_sli4_sge_dif_ce_WORD word3 1720 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1721 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1722 #define lpfc_sli4_sge_dif_nr_WORD word3 1723 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1724 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1725 #define lpfc_sli4_sge_dif_oprx_WORD word3 1726 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1727 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1728 #define lpfc_sli4_sge_dif_optx_WORD word3 1729 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1730 }; 1731 1732 struct fcf_record { 1733 uint32_t max_rcv_size; 1734 uint32_t fka_adv_period; 1735 uint32_t fip_priority; 1736 uint32_t word3; 1737 #define lpfc_fcf_record_mac_0_SHIFT 0 1738 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1739 #define lpfc_fcf_record_mac_0_WORD word3 1740 #define lpfc_fcf_record_mac_1_SHIFT 8 1741 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1742 #define lpfc_fcf_record_mac_1_WORD word3 1743 #define lpfc_fcf_record_mac_2_SHIFT 16 1744 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1745 #define lpfc_fcf_record_mac_2_WORD word3 1746 #define lpfc_fcf_record_mac_3_SHIFT 24 1747 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1748 #define lpfc_fcf_record_mac_3_WORD word3 1749 uint32_t word4; 1750 #define lpfc_fcf_record_mac_4_SHIFT 0 1751 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1752 #define lpfc_fcf_record_mac_4_WORD word4 1753 #define lpfc_fcf_record_mac_5_SHIFT 8 1754 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1755 #define lpfc_fcf_record_mac_5_WORD word4 1756 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1757 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1758 #define lpfc_fcf_record_fcf_avail_WORD word4 1759 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1760 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1761 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1762 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1763 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1764 uint32_t word5; 1765 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1766 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1767 #define lpfc_fcf_record_fab_name_0_WORD word5 1768 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1769 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1770 #define lpfc_fcf_record_fab_name_1_WORD word5 1771 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1772 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1773 #define lpfc_fcf_record_fab_name_2_WORD word5 1774 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1775 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1776 #define lpfc_fcf_record_fab_name_3_WORD word5 1777 uint32_t word6; 1778 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1779 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1780 #define lpfc_fcf_record_fab_name_4_WORD word6 1781 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1782 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1783 #define lpfc_fcf_record_fab_name_5_WORD word6 1784 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1785 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1786 #define lpfc_fcf_record_fab_name_6_WORD word6 1787 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1788 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1789 #define lpfc_fcf_record_fab_name_7_WORD word6 1790 uint32_t word7; 1791 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1792 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1793 #define lpfc_fcf_record_fc_map_0_WORD word7 1794 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1795 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1796 #define lpfc_fcf_record_fc_map_1_WORD word7 1797 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1798 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1799 #define lpfc_fcf_record_fc_map_2_WORD word7 1800 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1801 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 1802 #define lpfc_fcf_record_fcf_valid_WORD word7 1803 #define lpfc_fcf_record_fcf_fc_SHIFT 25 1804 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 1805 #define lpfc_fcf_record_fcf_fc_WORD word7 1806 #define lpfc_fcf_record_fcf_sol_SHIFT 31 1807 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 1808 #define lpfc_fcf_record_fcf_sol_WORD word7 1809 uint32_t word8; 1810 #define lpfc_fcf_record_fcf_index_SHIFT 0 1811 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1812 #define lpfc_fcf_record_fcf_index_WORD word8 1813 #define lpfc_fcf_record_fcf_state_SHIFT 16 1814 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1815 #define lpfc_fcf_record_fcf_state_WORD word8 1816 uint8_t vlan_bitmap[512]; 1817 uint32_t word137; 1818 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1819 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1820 #define lpfc_fcf_record_switch_name_0_WORD word137 1821 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1822 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1823 #define lpfc_fcf_record_switch_name_1_WORD word137 1824 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1825 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1826 #define lpfc_fcf_record_switch_name_2_WORD word137 1827 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1828 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1829 #define lpfc_fcf_record_switch_name_3_WORD word137 1830 uint32_t word138; 1831 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1832 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1833 #define lpfc_fcf_record_switch_name_4_WORD word138 1834 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1835 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1836 #define lpfc_fcf_record_switch_name_5_WORD word138 1837 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1838 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1839 #define lpfc_fcf_record_switch_name_6_WORD word138 1840 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1841 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1842 #define lpfc_fcf_record_switch_name_7_WORD word138 1843 }; 1844 1845 struct lpfc_mbx_read_fcf_tbl { 1846 union lpfc_sli4_cfg_shdr cfg_shdr; 1847 union { 1848 struct { 1849 uint32_t word10; 1850 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1851 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1852 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1853 } request; 1854 struct { 1855 uint32_t eventag; 1856 } response; 1857 } u; 1858 uint32_t word11; 1859 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1860 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1861 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1862 }; 1863 1864 struct lpfc_mbx_add_fcf_tbl_entry { 1865 union lpfc_sli4_cfg_shdr cfg_shdr; 1866 uint32_t word10; 1867 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1868 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1869 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1870 struct lpfc_mbx_sge fcf_sge; 1871 }; 1872 1873 struct lpfc_mbx_del_fcf_tbl_entry { 1874 struct mbox_header header; 1875 uint32_t word10; 1876 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1877 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1878 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1879 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1880 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1881 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1882 }; 1883 1884 struct lpfc_mbx_redisc_fcf_tbl { 1885 struct mbox_header header; 1886 uint32_t word10; 1887 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1888 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1889 #define lpfc_mbx_redisc_fcf_count_WORD word10 1890 uint32_t resvd; 1891 uint32_t word12; 1892 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1893 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1894 #define lpfc_mbx_redisc_fcf_index_WORD word12 1895 }; 1896 1897 /* Status field for embedded SLI_CONFIG mailbox command */ 1898 #define STATUS_SUCCESS 0x0 1899 #define STATUS_FAILED 0x1 1900 #define STATUS_ILLEGAL_REQUEST 0x2 1901 #define STATUS_ILLEGAL_FIELD 0x3 1902 #define STATUS_INSUFFICIENT_BUFFER 0x4 1903 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1904 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1905 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1906 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1907 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1908 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1909 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1910 #define STATUS_ASSERT_FAILED 0x1e 1911 #define STATUS_INVALID_SESSION 0x1f 1912 #define STATUS_INVALID_CONNECTION 0x20 1913 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1914 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1915 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1916 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1917 #define STATUS_FLASHROM_READ_FAILED 0x27 1918 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1919 #define STATUS_ERROR_ACITMAIN 0x2a 1920 #define STATUS_REBOOT_REQUIRED 0x2c 1921 #define STATUS_FCF_IN_USE 0x3a 1922 #define STATUS_FCF_TABLE_EMPTY 0x43 1923 1924 struct lpfc_mbx_sli4_config { 1925 struct mbox_header header; 1926 }; 1927 1928 struct lpfc_mbx_init_vfi { 1929 uint32_t word1; 1930 #define lpfc_init_vfi_vr_SHIFT 31 1931 #define lpfc_init_vfi_vr_MASK 0x00000001 1932 #define lpfc_init_vfi_vr_WORD word1 1933 #define lpfc_init_vfi_vt_SHIFT 30 1934 #define lpfc_init_vfi_vt_MASK 0x00000001 1935 #define lpfc_init_vfi_vt_WORD word1 1936 #define lpfc_init_vfi_vf_SHIFT 29 1937 #define lpfc_init_vfi_vf_MASK 0x00000001 1938 #define lpfc_init_vfi_vf_WORD word1 1939 #define lpfc_init_vfi_vp_SHIFT 28 1940 #define lpfc_init_vfi_vp_MASK 0x00000001 1941 #define lpfc_init_vfi_vp_WORD word1 1942 #define lpfc_init_vfi_vfi_SHIFT 0 1943 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1944 #define lpfc_init_vfi_vfi_WORD word1 1945 uint32_t word2; 1946 #define lpfc_init_vfi_vpi_SHIFT 16 1947 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1948 #define lpfc_init_vfi_vpi_WORD word2 1949 #define lpfc_init_vfi_fcfi_SHIFT 0 1950 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1951 #define lpfc_init_vfi_fcfi_WORD word2 1952 uint32_t word3; 1953 #define lpfc_init_vfi_pri_SHIFT 13 1954 #define lpfc_init_vfi_pri_MASK 0x00000007 1955 #define lpfc_init_vfi_pri_WORD word3 1956 #define lpfc_init_vfi_vf_id_SHIFT 1 1957 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1958 #define lpfc_init_vfi_vf_id_WORD word3 1959 uint32_t word4; 1960 #define lpfc_init_vfi_hop_count_SHIFT 24 1961 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1962 #define lpfc_init_vfi_hop_count_WORD word4 1963 }; 1964 #define MBX_VFI_IN_USE 0x9F02 1965 1966 1967 struct lpfc_mbx_reg_vfi { 1968 uint32_t word1; 1969 #define lpfc_reg_vfi_upd_SHIFT 29 1970 #define lpfc_reg_vfi_upd_MASK 0x00000001 1971 #define lpfc_reg_vfi_upd_WORD word1 1972 #define lpfc_reg_vfi_vp_SHIFT 28 1973 #define lpfc_reg_vfi_vp_MASK 0x00000001 1974 #define lpfc_reg_vfi_vp_WORD word1 1975 #define lpfc_reg_vfi_vfi_SHIFT 0 1976 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 1977 #define lpfc_reg_vfi_vfi_WORD word1 1978 uint32_t word2; 1979 #define lpfc_reg_vfi_vpi_SHIFT 16 1980 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 1981 #define lpfc_reg_vfi_vpi_WORD word2 1982 #define lpfc_reg_vfi_fcfi_SHIFT 0 1983 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 1984 #define lpfc_reg_vfi_fcfi_WORD word2 1985 uint32_t wwn[2]; 1986 struct ulp_bde64 bde; 1987 uint32_t e_d_tov; 1988 uint32_t r_a_tov; 1989 uint32_t word10; 1990 #define lpfc_reg_vfi_nport_id_SHIFT 0 1991 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 1992 #define lpfc_reg_vfi_nport_id_WORD word10 1993 }; 1994 1995 struct lpfc_mbx_init_vpi { 1996 uint32_t word1; 1997 #define lpfc_init_vpi_vfi_SHIFT 16 1998 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 1999 #define lpfc_init_vpi_vfi_WORD word1 2000 #define lpfc_init_vpi_vpi_SHIFT 0 2001 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2002 #define lpfc_init_vpi_vpi_WORD word1 2003 }; 2004 2005 struct lpfc_mbx_read_vpi { 2006 uint32_t word1_rsvd; 2007 uint32_t word2; 2008 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2009 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2010 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2011 uint32_t word3_rsvd; 2012 uint32_t word4; 2013 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2014 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2015 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2016 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2017 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2018 #define lpfc_mbx_read_vpi_pb_WORD word4 2019 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2020 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2021 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2022 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2023 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2024 #define lpfc_mbx_read_vpi_ns_WORD word4 2025 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2026 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2027 #define lpfc_mbx_read_vpi_hl_WORD word4 2028 uint32_t word5_rsvd; 2029 uint32_t word6; 2030 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2031 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2032 #define lpfc_mbx_read_vpi_vpi_WORD word6 2033 uint32_t word7; 2034 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2035 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2036 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2037 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2038 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2039 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2040 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2041 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2042 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2043 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2044 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2045 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2046 uint32_t word8; 2047 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2048 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2049 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2050 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2051 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2052 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2053 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2054 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2055 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2056 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2057 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2058 #define lpfc_mbx_read_vpi_vv_WORD word8 2059 }; 2060 2061 struct lpfc_mbx_unreg_vfi { 2062 uint32_t word1_rsvd; 2063 uint32_t word2; 2064 #define lpfc_unreg_vfi_vfi_SHIFT 0 2065 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2066 #define lpfc_unreg_vfi_vfi_WORD word2 2067 }; 2068 2069 struct lpfc_mbx_resume_rpi { 2070 uint32_t word1; 2071 #define lpfc_resume_rpi_index_SHIFT 0 2072 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2073 #define lpfc_resume_rpi_index_WORD word1 2074 #define lpfc_resume_rpi_ii_SHIFT 30 2075 #define lpfc_resume_rpi_ii_MASK 0x00000003 2076 #define lpfc_resume_rpi_ii_WORD word1 2077 #define RESUME_INDEX_RPI 0 2078 #define RESUME_INDEX_VPI 1 2079 #define RESUME_INDEX_VFI 2 2080 #define RESUME_INDEX_FCFI 3 2081 uint32_t event_tag; 2082 }; 2083 2084 #define REG_FCF_INVALID_QID 0xFFFF 2085 struct lpfc_mbx_reg_fcfi { 2086 uint32_t word1; 2087 #define lpfc_reg_fcfi_info_index_SHIFT 0 2088 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2089 #define lpfc_reg_fcfi_info_index_WORD word1 2090 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2091 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2092 #define lpfc_reg_fcfi_fcfi_WORD word1 2093 uint32_t word2; 2094 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2095 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2096 #define lpfc_reg_fcfi_rq_id1_WORD word2 2097 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2098 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2099 #define lpfc_reg_fcfi_rq_id0_WORD word2 2100 uint32_t word3; 2101 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2102 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2103 #define lpfc_reg_fcfi_rq_id3_WORD word3 2104 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2105 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2106 #define lpfc_reg_fcfi_rq_id2_WORD word3 2107 uint32_t word4; 2108 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2109 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2110 #define lpfc_reg_fcfi_type_match0_WORD word4 2111 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2112 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2113 #define lpfc_reg_fcfi_type_mask0_WORD word4 2114 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2115 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2116 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2117 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2118 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2119 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2120 uint32_t word5; 2121 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2122 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2123 #define lpfc_reg_fcfi_type_match1_WORD word5 2124 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2125 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2126 #define lpfc_reg_fcfi_type_mask1_WORD word5 2127 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2128 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2129 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2130 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2131 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2132 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2133 uint32_t word6; 2134 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2135 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2136 #define lpfc_reg_fcfi_type_match2_WORD word6 2137 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2138 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2139 #define lpfc_reg_fcfi_type_mask2_WORD word6 2140 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2141 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2142 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2143 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2144 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2145 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2146 uint32_t word7; 2147 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2148 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2149 #define lpfc_reg_fcfi_type_match3_WORD word7 2150 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2151 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2152 #define lpfc_reg_fcfi_type_mask3_WORD word7 2153 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2154 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2155 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2156 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2157 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2158 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2159 uint32_t word8; 2160 #define lpfc_reg_fcfi_mam_SHIFT 13 2161 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2162 #define lpfc_reg_fcfi_mam_WORD word8 2163 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2164 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2165 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2166 #define lpfc_reg_fcfi_vv_SHIFT 12 2167 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2168 #define lpfc_reg_fcfi_vv_WORD word8 2169 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2170 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2171 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2172 }; 2173 2174 struct lpfc_mbx_unreg_fcfi { 2175 uint32_t word1_rsv; 2176 uint32_t word2; 2177 #define lpfc_unreg_fcfi_SHIFT 0 2178 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2179 #define lpfc_unreg_fcfi_WORD word2 2180 }; 2181 2182 struct lpfc_mbx_read_rev { 2183 uint32_t word1; 2184 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2185 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2186 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2187 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2188 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2189 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2190 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2191 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2192 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2193 #define LPFC_PREDCBX_CEE_MODE 0 2194 #define LPFC_DCBX_CEE_MODE 1 2195 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2196 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2197 #define lpfc_mbx_rd_rev_vpd_WORD word1 2198 uint32_t first_hw_rev; 2199 uint32_t second_hw_rev; 2200 uint32_t word4_rsvd; 2201 uint32_t third_hw_rev; 2202 uint32_t word6; 2203 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2204 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2205 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2206 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2207 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2208 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2209 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2210 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2211 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2212 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2213 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2214 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2215 uint32_t word7_rsvd; 2216 uint32_t fw_id_rev; 2217 uint8_t fw_name[16]; 2218 uint32_t ulp_fw_id_rev; 2219 uint8_t ulp_fw_name[16]; 2220 uint32_t word18_47_rsvd[30]; 2221 uint32_t word48; 2222 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2223 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2224 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2225 uint32_t vpd_paddr_low; 2226 uint32_t vpd_paddr_high; 2227 uint32_t avail_vpd_len; 2228 uint32_t rsvd_52_63[12]; 2229 }; 2230 2231 struct lpfc_mbx_read_config { 2232 uint32_t word1; 2233 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2234 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2235 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2236 uint32_t word2; 2237 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2238 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2239 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2240 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2241 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2242 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2243 #define LPFC_LNK_TYPE_GE 0 2244 #define LPFC_LNK_TYPE_FC 1 2245 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2246 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2247 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2248 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2249 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2250 #define lpfc_mbx_rd_conf_topology_WORD word2 2251 uint32_t rsvd_3; 2252 uint32_t word4; 2253 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2254 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2255 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2256 uint32_t rsvd_5; 2257 uint32_t word6; 2258 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2259 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2260 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2261 uint32_t rsvd_7; 2262 uint32_t rsvd_8; 2263 uint32_t word9; 2264 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2265 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2266 #define lpfc_mbx_rd_conf_lmt_WORD word9 2267 uint32_t rsvd_10; 2268 uint32_t rsvd_11; 2269 uint32_t word12; 2270 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2271 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2272 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2273 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2274 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2275 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2276 uint32_t word13; 2277 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2278 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2279 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2280 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2281 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2282 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2283 uint32_t word14; 2284 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2285 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2286 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2287 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2288 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2289 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2290 uint32_t word15; 2291 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2292 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2293 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2294 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2295 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2296 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2297 uint32_t word16; 2298 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2299 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2300 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2301 uint32_t word17; 2302 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2303 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2304 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2305 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2306 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2307 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2308 uint32_t word18; 2309 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2310 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2311 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2312 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2313 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2314 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2315 }; 2316 2317 struct lpfc_mbx_request_features { 2318 uint32_t word1; 2319 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2320 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2321 #define lpfc_mbx_rq_ftr_qry_WORD word1 2322 uint32_t word2; 2323 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2324 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2325 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2326 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2327 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2328 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2329 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2330 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2331 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2332 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2333 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2334 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2335 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2336 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2337 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2338 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2339 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2340 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2341 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2342 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2343 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2344 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2345 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2346 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2347 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2348 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2349 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2350 uint32_t word3; 2351 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2352 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2353 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2354 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2355 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2356 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2357 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2358 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2359 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2360 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2361 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2362 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2363 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2364 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2365 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2366 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2367 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2368 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2369 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2370 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2371 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2372 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2373 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2374 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2375 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2376 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2377 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2378 }; 2379 2380 struct lpfc_mbx_supp_pages { 2381 uint32_t word1; 2382 #define qs_SHIFT 0 2383 #define qs_MASK 0x00000001 2384 #define qs_WORD word1 2385 #define wr_SHIFT 1 2386 #define wr_MASK 0x00000001 2387 #define wr_WORD word1 2388 #define pf_SHIFT 8 2389 #define pf_MASK 0x000000ff 2390 #define pf_WORD word1 2391 #define cpn_SHIFT 16 2392 #define cpn_MASK 0x000000ff 2393 #define cpn_WORD word1 2394 uint32_t word2; 2395 #define list_offset_SHIFT 0 2396 #define list_offset_MASK 0x000000ff 2397 #define list_offset_WORD word2 2398 #define next_offset_SHIFT 8 2399 #define next_offset_MASK 0x000000ff 2400 #define next_offset_WORD word2 2401 #define elem_cnt_SHIFT 16 2402 #define elem_cnt_MASK 0x000000ff 2403 #define elem_cnt_WORD word2 2404 uint32_t word3; 2405 #define pn_0_SHIFT 24 2406 #define pn_0_MASK 0x000000ff 2407 #define pn_0_WORD word3 2408 #define pn_1_SHIFT 16 2409 #define pn_1_MASK 0x000000ff 2410 #define pn_1_WORD word3 2411 #define pn_2_SHIFT 8 2412 #define pn_2_MASK 0x000000ff 2413 #define pn_2_WORD word3 2414 #define pn_3_SHIFT 0 2415 #define pn_3_MASK 0x000000ff 2416 #define pn_3_WORD word3 2417 uint32_t word4; 2418 #define pn_4_SHIFT 24 2419 #define pn_4_MASK 0x000000ff 2420 #define pn_4_WORD word4 2421 #define pn_5_SHIFT 16 2422 #define pn_5_MASK 0x000000ff 2423 #define pn_5_WORD word4 2424 #define pn_6_SHIFT 8 2425 #define pn_6_MASK 0x000000ff 2426 #define pn_6_WORD word4 2427 #define pn_7_SHIFT 0 2428 #define pn_7_MASK 0x000000ff 2429 #define pn_7_WORD word4 2430 uint32_t rsvd[27]; 2431 #define LPFC_SUPP_PAGES 0 2432 #define LPFC_BLOCK_GUARD_PROFILES 1 2433 #define LPFC_SLI4_PARAMETERS 2 2434 }; 2435 2436 struct lpfc_mbx_pc_sli4_params { 2437 uint32_t word1; 2438 #define qs_SHIFT 0 2439 #define qs_MASK 0x00000001 2440 #define qs_WORD word1 2441 #define wr_SHIFT 1 2442 #define wr_MASK 0x00000001 2443 #define wr_WORD word1 2444 #define pf_SHIFT 8 2445 #define pf_MASK 0x000000ff 2446 #define pf_WORD word1 2447 #define cpn_SHIFT 16 2448 #define cpn_MASK 0x000000ff 2449 #define cpn_WORD word1 2450 uint32_t word2; 2451 #define if_type_SHIFT 0 2452 #define if_type_MASK 0x00000007 2453 #define if_type_WORD word2 2454 #define sli_rev_SHIFT 4 2455 #define sli_rev_MASK 0x0000000f 2456 #define sli_rev_WORD word2 2457 #define sli_family_SHIFT 8 2458 #define sli_family_MASK 0x000000ff 2459 #define sli_family_WORD word2 2460 #define featurelevel_1_SHIFT 16 2461 #define featurelevel_1_MASK 0x000000ff 2462 #define featurelevel_1_WORD word2 2463 #define featurelevel_2_SHIFT 24 2464 #define featurelevel_2_MASK 0x0000001f 2465 #define featurelevel_2_WORD word2 2466 uint32_t word3; 2467 #define fcoe_SHIFT 0 2468 #define fcoe_MASK 0x00000001 2469 #define fcoe_WORD word3 2470 #define fc_SHIFT 1 2471 #define fc_MASK 0x00000001 2472 #define fc_WORD word3 2473 #define nic_SHIFT 2 2474 #define nic_MASK 0x00000001 2475 #define nic_WORD word3 2476 #define iscsi_SHIFT 3 2477 #define iscsi_MASK 0x00000001 2478 #define iscsi_WORD word3 2479 #define rdma_SHIFT 4 2480 #define rdma_MASK 0x00000001 2481 #define rdma_WORD word3 2482 uint32_t sge_supp_len; 2483 #define SLI4_PAGE_SIZE 4096 2484 uint32_t word5; 2485 #define if_page_sz_SHIFT 0 2486 #define if_page_sz_MASK 0x0000ffff 2487 #define if_page_sz_WORD word5 2488 #define loopbk_scope_SHIFT 24 2489 #define loopbk_scope_MASK 0x0000000f 2490 #define loopbk_scope_WORD word5 2491 #define rq_db_window_SHIFT 28 2492 #define rq_db_window_MASK 0x0000000f 2493 #define rq_db_window_WORD word5 2494 uint32_t word6; 2495 #define eq_pages_SHIFT 0 2496 #define eq_pages_MASK 0x0000000f 2497 #define eq_pages_WORD word6 2498 #define eqe_size_SHIFT 8 2499 #define eqe_size_MASK 0x000000ff 2500 #define eqe_size_WORD word6 2501 uint32_t word7; 2502 #define cq_pages_SHIFT 0 2503 #define cq_pages_MASK 0x0000000f 2504 #define cq_pages_WORD word7 2505 #define cqe_size_SHIFT 8 2506 #define cqe_size_MASK 0x000000ff 2507 #define cqe_size_WORD word7 2508 uint32_t word8; 2509 #define mq_pages_SHIFT 0 2510 #define mq_pages_MASK 0x0000000f 2511 #define mq_pages_WORD word8 2512 #define mqe_size_SHIFT 8 2513 #define mqe_size_MASK 0x000000ff 2514 #define mqe_size_WORD word8 2515 #define mq_elem_cnt_SHIFT 16 2516 #define mq_elem_cnt_MASK 0x000000ff 2517 #define mq_elem_cnt_WORD word8 2518 uint32_t word9; 2519 #define wq_pages_SHIFT 0 2520 #define wq_pages_MASK 0x0000ffff 2521 #define wq_pages_WORD word9 2522 #define wqe_size_SHIFT 8 2523 #define wqe_size_MASK 0x000000ff 2524 #define wqe_size_WORD word9 2525 uint32_t word10; 2526 #define rq_pages_SHIFT 0 2527 #define rq_pages_MASK 0x0000ffff 2528 #define rq_pages_WORD word10 2529 #define rqe_size_SHIFT 8 2530 #define rqe_size_MASK 0x000000ff 2531 #define rqe_size_WORD word10 2532 uint32_t word11; 2533 #define hdr_pages_SHIFT 0 2534 #define hdr_pages_MASK 0x0000000f 2535 #define hdr_pages_WORD word11 2536 #define hdr_size_SHIFT 8 2537 #define hdr_size_MASK 0x0000000f 2538 #define hdr_size_WORD word11 2539 #define hdr_pp_align_SHIFT 16 2540 #define hdr_pp_align_MASK 0x0000ffff 2541 #define hdr_pp_align_WORD word11 2542 uint32_t word12; 2543 #define sgl_pages_SHIFT 0 2544 #define sgl_pages_MASK 0x0000000f 2545 #define sgl_pages_WORD word12 2546 #define sgl_pp_align_SHIFT 16 2547 #define sgl_pp_align_MASK 0x0000ffff 2548 #define sgl_pp_align_WORD word12 2549 uint32_t rsvd_13_63[51]; 2550 }; 2551 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2552 &(~((SLI4_PAGE_SIZE)-1))) 2553 2554 struct lpfc_sli4_parameters { 2555 uint32_t word0; 2556 #define cfg_prot_type_SHIFT 0 2557 #define cfg_prot_type_MASK 0x000000FF 2558 #define cfg_prot_type_WORD word0 2559 uint32_t word1; 2560 #define cfg_ft_SHIFT 0 2561 #define cfg_ft_MASK 0x00000001 2562 #define cfg_ft_WORD word1 2563 #define cfg_sli_rev_SHIFT 4 2564 #define cfg_sli_rev_MASK 0x0000000f 2565 #define cfg_sli_rev_WORD word1 2566 #define cfg_sli_family_SHIFT 8 2567 #define cfg_sli_family_MASK 0x0000000f 2568 #define cfg_sli_family_WORD word1 2569 #define cfg_if_type_SHIFT 12 2570 #define cfg_if_type_MASK 0x0000000f 2571 #define cfg_if_type_WORD word1 2572 #define cfg_sli_hint_1_SHIFT 16 2573 #define cfg_sli_hint_1_MASK 0x000000ff 2574 #define cfg_sli_hint_1_WORD word1 2575 #define cfg_sli_hint_2_SHIFT 24 2576 #define cfg_sli_hint_2_MASK 0x0000001f 2577 #define cfg_sli_hint_2_WORD word1 2578 uint32_t word2; 2579 uint32_t word3; 2580 uint32_t word4; 2581 #define cfg_cqv_SHIFT 14 2582 #define cfg_cqv_MASK 0x00000003 2583 #define cfg_cqv_WORD word4 2584 uint32_t word5; 2585 uint32_t word6; 2586 #define cfg_mqv_SHIFT 14 2587 #define cfg_mqv_MASK 0x00000003 2588 #define cfg_mqv_WORD word6 2589 uint32_t word7; 2590 uint32_t word8; 2591 #define cfg_wqsize_SHIFT 8 2592 #define cfg_wqsize_MASK 0x0000000f 2593 #define cfg_wqsize_WORD word8 2594 #define cfg_wqv_SHIFT 14 2595 #define cfg_wqv_MASK 0x00000003 2596 #define cfg_wqv_WORD word8 2597 uint32_t word9; 2598 uint32_t word10; 2599 #define cfg_rqv_SHIFT 14 2600 #define cfg_rqv_MASK 0x00000003 2601 #define cfg_rqv_WORD word10 2602 uint32_t word11; 2603 #define cfg_rq_db_window_SHIFT 28 2604 #define cfg_rq_db_window_MASK 0x0000000f 2605 #define cfg_rq_db_window_WORD word11 2606 uint32_t word12; 2607 #define cfg_fcoe_SHIFT 0 2608 #define cfg_fcoe_MASK 0x00000001 2609 #define cfg_fcoe_WORD word12 2610 #define cfg_ext_SHIFT 1 2611 #define cfg_ext_MASK 0x00000001 2612 #define cfg_ext_WORD word12 2613 #define cfg_hdrr_SHIFT 2 2614 #define cfg_hdrr_MASK 0x00000001 2615 #define cfg_hdrr_WORD word12 2616 #define cfg_phwq_SHIFT 15 2617 #define cfg_phwq_MASK 0x00000001 2618 #define cfg_phwq_WORD word12 2619 #define cfg_loopbk_scope_SHIFT 28 2620 #define cfg_loopbk_scope_MASK 0x0000000f 2621 #define cfg_loopbk_scope_WORD word12 2622 uint32_t sge_supp_len; 2623 uint32_t word14; 2624 #define cfg_sgl_page_cnt_SHIFT 0 2625 #define cfg_sgl_page_cnt_MASK 0x0000000f 2626 #define cfg_sgl_page_cnt_WORD word14 2627 #define cfg_sgl_page_size_SHIFT 8 2628 #define cfg_sgl_page_size_MASK 0x000000ff 2629 #define cfg_sgl_page_size_WORD word14 2630 #define cfg_sgl_pp_align_SHIFT 16 2631 #define cfg_sgl_pp_align_MASK 0x000000ff 2632 #define cfg_sgl_pp_align_WORD word14 2633 uint32_t word15; 2634 uint32_t word16; 2635 uint32_t word17; 2636 uint32_t word18; 2637 uint32_t word19; 2638 }; 2639 2640 struct lpfc_mbx_get_sli4_parameters { 2641 struct mbox_header header; 2642 struct lpfc_sli4_parameters sli4_parameters; 2643 }; 2644 2645 struct lpfc_rscr_desc_generic { 2646 #define LPFC_RSRC_DESC_WSIZE 22 2647 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2648 }; 2649 2650 struct lpfc_rsrc_desc_pcie { 2651 uint32_t word0; 2652 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2653 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2654 #define lpfc_rsrc_desc_pcie_type_WORD word0 2655 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2656 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 2657 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 2658 #define lpfc_rsrc_desc_pcie_length_WORD word0 2659 uint32_t word1; 2660 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2661 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2662 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2663 uint32_t reserved; 2664 uint32_t word3; 2665 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2666 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2667 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2668 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2669 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2670 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2671 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2672 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2673 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2674 uint32_t word4; 2675 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2676 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2677 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2678 }; 2679 2680 struct lpfc_rsrc_desc_fcfcoe { 2681 uint32_t word0; 2682 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2683 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2684 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2685 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2686 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 2687 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 2688 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 2689 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 2690 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 2691 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 2692 uint32_t word1; 2693 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2694 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2695 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2696 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2697 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2698 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2699 uint32_t word2; 2700 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2701 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2702 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2703 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2704 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2705 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2706 uint32_t word3; 2707 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2708 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2709 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2710 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2711 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2712 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2713 uint32_t word4; 2714 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2715 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2716 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2717 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2718 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2719 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2720 uint32_t word5; 2721 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2722 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2723 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2724 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2725 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2726 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2727 uint32_t word6; 2728 uint32_t word7; 2729 uint32_t word8; 2730 uint32_t word9; 2731 uint32_t word10; 2732 uint32_t word11; 2733 uint32_t word12; 2734 uint32_t word13; 2735 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2736 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2737 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2738 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2739 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2740 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2741 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2742 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2743 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2744 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2745 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2746 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2747 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 2748 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 2749 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 2750 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 2751 uint32_t bw_min; 2752 uint32_t bw_max; 2753 uint32_t iops_min; 2754 uint32_t iops_max; 2755 uint32_t reserved[4]; 2756 }; 2757 2758 struct lpfc_func_cfg { 2759 #define LPFC_RSRC_DESC_MAX_NUM 2 2760 uint32_t rsrc_desc_count; 2761 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2762 }; 2763 2764 struct lpfc_mbx_get_func_cfg { 2765 struct mbox_header header; 2766 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2767 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2768 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2769 struct lpfc_func_cfg func_cfg; 2770 }; 2771 2772 struct lpfc_prof_cfg { 2773 #define LPFC_RSRC_DESC_MAX_NUM 2 2774 uint32_t rsrc_desc_count; 2775 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 2776 }; 2777 2778 struct lpfc_mbx_get_prof_cfg { 2779 struct mbox_header header; 2780 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 2781 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 2782 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 2783 union { 2784 struct { 2785 uint32_t word10; 2786 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 2787 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 2788 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 2789 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 2790 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 2791 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 2792 } request; 2793 struct { 2794 struct lpfc_prof_cfg prof_cfg; 2795 } response; 2796 } u; 2797 }; 2798 2799 struct lpfc_controller_attribute { 2800 uint32_t version_string[8]; 2801 uint32_t manufacturer_name[8]; 2802 uint32_t supported_modes; 2803 uint32_t word17; 2804 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 2805 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 2806 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 2807 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 2808 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 2809 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 2810 uint32_t mbx_da_struct_ver; 2811 uint32_t ep_fw_da_struct_ver; 2812 uint32_t ncsi_ver_str[3]; 2813 uint32_t dflt_ext_timeout; 2814 uint32_t model_number[8]; 2815 uint32_t description[16]; 2816 uint32_t serial_number[8]; 2817 uint32_t ip_ver_str[8]; 2818 uint32_t fw_ver_str[8]; 2819 uint32_t bios_ver_str[8]; 2820 uint32_t redboot_ver_str[8]; 2821 uint32_t driver_ver_str[8]; 2822 uint32_t flash_fw_ver_str[8]; 2823 uint32_t functionality; 2824 uint32_t word105; 2825 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 2826 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 2827 #define lpfc_cntl_attr_max_cbd_len_WORD word105 2828 #define lpfc_cntl_attr_asic_rev_SHIFT 16 2829 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 2830 #define lpfc_cntl_attr_asic_rev_WORD word105 2831 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 2832 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 2833 #define lpfc_cntl_attr_gen_guid0_WORD word105 2834 uint32_t gen_guid1_12[3]; 2835 uint32_t word109; 2836 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 2837 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 2838 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 2839 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 2840 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 2841 #define lpfc_cntl_attr_gen_guid15_WORD word109 2842 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 2843 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 2844 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 2845 uint32_t word110; 2846 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 2847 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 2848 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 2849 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 2850 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 2851 #define lpfc_cntl_attr_multi_func_dev_WORD word110 2852 uint32_t word111; 2853 #define lpfc_cntl_attr_cache_valid_SHIFT 0 2854 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 2855 #define lpfc_cntl_attr_cache_valid_WORD word111 2856 #define lpfc_cntl_attr_hba_status_SHIFT 8 2857 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 2858 #define lpfc_cntl_attr_hba_status_WORD word111 2859 #define lpfc_cntl_attr_max_domain_SHIFT 16 2860 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 2861 #define lpfc_cntl_attr_max_domain_WORD word111 2862 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 2863 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 2864 #define lpfc_cntl_attr_lnk_numb_WORD word111 2865 #define lpfc_cntl_attr_lnk_type_SHIFT 30 2866 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 2867 #define lpfc_cntl_attr_lnk_type_WORD word111 2868 uint32_t fw_post_status; 2869 uint32_t hba_mtu[8]; 2870 uint32_t word121; 2871 uint32_t reserved1[3]; 2872 uint32_t word125; 2873 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 2874 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 2875 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 2876 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 2877 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 2878 #define lpfc_cntl_attr_pci_device_id_WORD word125 2879 uint32_t word126; 2880 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 2881 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 2882 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 2883 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 2884 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 2885 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 2886 uint32_t word127; 2887 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 2888 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 2889 #define lpfc_cntl_attr_pci_bus_num_WORD word127 2890 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 2891 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 2892 #define lpfc_cntl_attr_pci_dev_num_WORD word127 2893 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 2894 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 2895 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 2896 #define lpfc_cntl_attr_inf_type_SHIFT 24 2897 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 2898 #define lpfc_cntl_attr_inf_type_WORD word127 2899 uint32_t unique_id[2]; 2900 uint32_t word130; 2901 #define lpfc_cntl_attr_num_netfil_SHIFT 0 2902 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 2903 #define lpfc_cntl_attr_num_netfil_WORD word130 2904 uint32_t reserved2[4]; 2905 }; 2906 2907 struct lpfc_mbx_get_cntl_attributes { 2908 union lpfc_sli4_cfg_shdr cfg_shdr; 2909 struct lpfc_controller_attribute cntl_attr; 2910 }; 2911 2912 struct lpfc_mbx_get_port_name { 2913 struct mbox_header header; 2914 union { 2915 struct { 2916 uint32_t word4; 2917 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 2918 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 2919 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 2920 } request; 2921 struct { 2922 uint32_t word4; 2923 #define lpfc_mbx_get_port_name_name0_SHIFT 0 2924 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 2925 #define lpfc_mbx_get_port_name_name0_WORD word4 2926 #define lpfc_mbx_get_port_name_name1_SHIFT 8 2927 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 2928 #define lpfc_mbx_get_port_name_name1_WORD word4 2929 #define lpfc_mbx_get_port_name_name2_SHIFT 16 2930 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 2931 #define lpfc_mbx_get_port_name_name2_WORD word4 2932 #define lpfc_mbx_get_port_name_name3_SHIFT 24 2933 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 2934 #define lpfc_mbx_get_port_name_name3_WORD word4 2935 #define LPFC_LINK_NUMBER_0 0 2936 #define LPFC_LINK_NUMBER_1 1 2937 #define LPFC_LINK_NUMBER_2 2 2938 #define LPFC_LINK_NUMBER_3 3 2939 } response; 2940 } u; 2941 }; 2942 2943 /* Mailbox Completion Queue Error Messages */ 2944 #define MB_CQE_STATUS_SUCCESS 0x0 2945 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 2946 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 2947 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 2948 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 2949 #define MB_CQE_STATUS_DMA_FAILED 0x5 2950 2951 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 2952 struct lpfc_mbx_wr_object { 2953 struct mbox_header header; 2954 union { 2955 struct { 2956 uint32_t word4; 2957 #define lpfc_wr_object_eof_SHIFT 31 2958 #define lpfc_wr_object_eof_MASK 0x00000001 2959 #define lpfc_wr_object_eof_WORD word4 2960 #define lpfc_wr_object_write_length_SHIFT 0 2961 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 2962 #define lpfc_wr_object_write_length_WORD word4 2963 uint32_t write_offset; 2964 uint32_t object_name[26]; 2965 uint32_t bde_count; 2966 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 2967 } request; 2968 struct { 2969 uint32_t actual_write_length; 2970 } response; 2971 } u; 2972 }; 2973 2974 /* mailbox queue entry structure */ 2975 struct lpfc_mqe { 2976 uint32_t word0; 2977 #define lpfc_mqe_status_SHIFT 16 2978 #define lpfc_mqe_status_MASK 0x0000FFFF 2979 #define lpfc_mqe_status_WORD word0 2980 #define lpfc_mqe_command_SHIFT 8 2981 #define lpfc_mqe_command_MASK 0x000000FF 2982 #define lpfc_mqe_command_WORD word0 2983 union { 2984 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 2985 /* sli4 mailbox commands */ 2986 struct lpfc_mbx_sli4_config sli4_config; 2987 struct lpfc_mbx_init_vfi init_vfi; 2988 struct lpfc_mbx_reg_vfi reg_vfi; 2989 struct lpfc_mbx_reg_vfi unreg_vfi; 2990 struct lpfc_mbx_init_vpi init_vpi; 2991 struct lpfc_mbx_resume_rpi resume_rpi; 2992 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 2993 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 2994 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 2995 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 2996 struct lpfc_mbx_reg_fcfi reg_fcfi; 2997 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 2998 struct lpfc_mbx_mq_create mq_create; 2999 struct lpfc_mbx_mq_create_ext mq_create_ext; 3000 struct lpfc_mbx_eq_create eq_create; 3001 struct lpfc_mbx_modify_eq_delay eq_delay; 3002 struct lpfc_mbx_cq_create cq_create; 3003 struct lpfc_mbx_wq_create wq_create; 3004 struct lpfc_mbx_rq_create rq_create; 3005 struct lpfc_mbx_mq_destroy mq_destroy; 3006 struct lpfc_mbx_eq_destroy eq_destroy; 3007 struct lpfc_mbx_cq_destroy cq_destroy; 3008 struct lpfc_mbx_wq_destroy wq_destroy; 3009 struct lpfc_mbx_rq_destroy rq_destroy; 3010 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3011 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3012 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3013 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3014 struct lpfc_mbx_nembed_cmd nembed_cmd; 3015 struct lpfc_mbx_read_rev read_rev; 3016 struct lpfc_mbx_read_vpi read_vpi; 3017 struct lpfc_mbx_read_config rd_config; 3018 struct lpfc_mbx_request_features req_ftrs; 3019 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3020 struct lpfc_mbx_query_fw_config query_fw_cfg; 3021 struct lpfc_mbx_supp_pages supp_pages; 3022 struct lpfc_mbx_pc_sli4_params sli4_params; 3023 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3024 struct lpfc_mbx_set_link_diag_state link_diag_state; 3025 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3026 struct lpfc_mbx_run_link_diag_test link_diag_test; 3027 struct lpfc_mbx_get_func_cfg get_func_cfg; 3028 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3029 struct lpfc_mbx_wr_object wr_object; 3030 struct lpfc_mbx_get_port_name get_port_name; 3031 struct lpfc_mbx_nop nop; 3032 } un; 3033 }; 3034 3035 struct lpfc_mcqe { 3036 uint32_t word0; 3037 #define lpfc_mcqe_status_SHIFT 0 3038 #define lpfc_mcqe_status_MASK 0x0000FFFF 3039 #define lpfc_mcqe_status_WORD word0 3040 #define lpfc_mcqe_ext_status_SHIFT 16 3041 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3042 #define lpfc_mcqe_ext_status_WORD word0 3043 uint32_t mcqe_tag0; 3044 uint32_t mcqe_tag1; 3045 uint32_t trailer; 3046 #define lpfc_trailer_valid_SHIFT 31 3047 #define lpfc_trailer_valid_MASK 0x00000001 3048 #define lpfc_trailer_valid_WORD trailer 3049 #define lpfc_trailer_async_SHIFT 30 3050 #define lpfc_trailer_async_MASK 0x00000001 3051 #define lpfc_trailer_async_WORD trailer 3052 #define lpfc_trailer_hpi_SHIFT 29 3053 #define lpfc_trailer_hpi_MASK 0x00000001 3054 #define lpfc_trailer_hpi_WORD trailer 3055 #define lpfc_trailer_completed_SHIFT 28 3056 #define lpfc_trailer_completed_MASK 0x00000001 3057 #define lpfc_trailer_completed_WORD trailer 3058 #define lpfc_trailer_consumed_SHIFT 27 3059 #define lpfc_trailer_consumed_MASK 0x00000001 3060 #define lpfc_trailer_consumed_WORD trailer 3061 #define lpfc_trailer_type_SHIFT 16 3062 #define lpfc_trailer_type_MASK 0x000000FF 3063 #define lpfc_trailer_type_WORD trailer 3064 #define lpfc_trailer_code_SHIFT 8 3065 #define lpfc_trailer_code_MASK 0x000000FF 3066 #define lpfc_trailer_code_WORD trailer 3067 #define LPFC_TRAILER_CODE_LINK 0x1 3068 #define LPFC_TRAILER_CODE_FCOE 0x2 3069 #define LPFC_TRAILER_CODE_DCBX 0x3 3070 #define LPFC_TRAILER_CODE_GRP5 0x5 3071 #define LPFC_TRAILER_CODE_FC 0x10 3072 #define LPFC_TRAILER_CODE_SLI 0x11 3073 }; 3074 3075 struct lpfc_acqe_link { 3076 uint32_t word0; 3077 #define lpfc_acqe_link_speed_SHIFT 24 3078 #define lpfc_acqe_link_speed_MASK 0x000000FF 3079 #define lpfc_acqe_link_speed_WORD word0 3080 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3081 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3082 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3083 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3084 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3085 #define lpfc_acqe_link_duplex_SHIFT 16 3086 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3087 #define lpfc_acqe_link_duplex_WORD word0 3088 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3089 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3090 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3091 #define lpfc_acqe_link_status_SHIFT 8 3092 #define lpfc_acqe_link_status_MASK 0x000000FF 3093 #define lpfc_acqe_link_status_WORD word0 3094 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3095 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3096 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3097 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3098 #define lpfc_acqe_link_type_SHIFT 6 3099 #define lpfc_acqe_link_type_MASK 0x00000003 3100 #define lpfc_acqe_link_type_WORD word0 3101 #define lpfc_acqe_link_number_SHIFT 0 3102 #define lpfc_acqe_link_number_MASK 0x0000003F 3103 #define lpfc_acqe_link_number_WORD word0 3104 uint32_t word1; 3105 #define lpfc_acqe_link_fault_SHIFT 0 3106 #define lpfc_acqe_link_fault_MASK 0x000000FF 3107 #define lpfc_acqe_link_fault_WORD word1 3108 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3109 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3110 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3111 #define lpfc_acqe_logical_link_speed_SHIFT 16 3112 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3113 #define lpfc_acqe_logical_link_speed_WORD word1 3114 uint32_t event_tag; 3115 uint32_t trailer; 3116 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3117 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3118 }; 3119 3120 struct lpfc_acqe_fip { 3121 uint32_t index; 3122 uint32_t word1; 3123 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3124 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3125 #define lpfc_acqe_fip_fcf_count_WORD word1 3126 #define lpfc_acqe_fip_event_type_SHIFT 16 3127 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3128 #define lpfc_acqe_fip_event_type_WORD word1 3129 uint32_t event_tag; 3130 uint32_t trailer; 3131 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3132 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3133 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3134 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3135 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3136 }; 3137 3138 struct lpfc_acqe_dcbx { 3139 uint32_t tlv_ttl; 3140 uint32_t reserved; 3141 uint32_t event_tag; 3142 uint32_t trailer; 3143 }; 3144 3145 struct lpfc_acqe_grp5 { 3146 uint32_t word0; 3147 #define lpfc_acqe_grp5_type_SHIFT 6 3148 #define lpfc_acqe_grp5_type_MASK 0x00000003 3149 #define lpfc_acqe_grp5_type_WORD word0 3150 #define lpfc_acqe_grp5_number_SHIFT 0 3151 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3152 #define lpfc_acqe_grp5_number_WORD word0 3153 uint32_t word1; 3154 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3155 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3156 #define lpfc_acqe_grp5_llink_spd_WORD word1 3157 uint32_t event_tag; 3158 uint32_t trailer; 3159 }; 3160 3161 struct lpfc_acqe_fc_la { 3162 uint32_t word0; 3163 #define lpfc_acqe_fc_la_speed_SHIFT 24 3164 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3165 #define lpfc_acqe_fc_la_speed_WORD word0 3166 #define LPFC_FC_LA_SPEED_UNKOWN 0x0 3167 #define LPFC_FC_LA_SPEED_1G 0x1 3168 #define LPFC_FC_LA_SPEED_2G 0x2 3169 #define LPFC_FC_LA_SPEED_4G 0x4 3170 #define LPFC_FC_LA_SPEED_8G 0x8 3171 #define LPFC_FC_LA_SPEED_10G 0xA 3172 #define LPFC_FC_LA_SPEED_16G 0x10 3173 #define lpfc_acqe_fc_la_topology_SHIFT 16 3174 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3175 #define lpfc_acqe_fc_la_topology_WORD word0 3176 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3177 #define LPFC_FC_LA_TOP_P2P 0x1 3178 #define LPFC_FC_LA_TOP_FCAL 0x2 3179 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3180 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3181 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3182 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3183 #define lpfc_acqe_fc_la_att_type_WORD word0 3184 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3185 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3186 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3187 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3188 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3189 #define lpfc_acqe_fc_la_port_type_WORD word0 3190 #define LPFC_LINK_TYPE_ETHERNET 0x0 3191 #define LPFC_LINK_TYPE_FC 0x1 3192 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3193 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3194 #define lpfc_acqe_fc_la_port_number_WORD word0 3195 uint32_t word1; 3196 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3197 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3198 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3199 #define lpfc_acqe_fc_la_fault_SHIFT 0 3200 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3201 #define lpfc_acqe_fc_la_fault_WORD word1 3202 #define LPFC_FC_LA_FAULT_NONE 0x0 3203 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3204 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3205 uint32_t event_tag; 3206 uint32_t trailer; 3207 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3208 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3209 }; 3210 3211 struct lpfc_acqe_misconfigured_event { 3212 struct { 3213 uint32_t word0; 3214 #define lpfc_sli_misconfigured_port0_SHIFT 0 3215 #define lpfc_sli_misconfigured_port0_MASK 0x000000FF 3216 #define lpfc_sli_misconfigured_port0_WORD word0 3217 #define lpfc_sli_misconfigured_port1_SHIFT 8 3218 #define lpfc_sli_misconfigured_port1_MASK 0x000000FF 3219 #define lpfc_sli_misconfigured_port1_WORD word0 3220 #define lpfc_sli_misconfigured_port2_SHIFT 16 3221 #define lpfc_sli_misconfigured_port2_MASK 0x000000FF 3222 #define lpfc_sli_misconfigured_port2_WORD word0 3223 #define lpfc_sli_misconfigured_port3_SHIFT 24 3224 #define lpfc_sli_misconfigured_port3_MASK 0x000000FF 3225 #define lpfc_sli_misconfigured_port3_WORD word0 3226 } theEvent; 3227 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 3228 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 3229 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 3230 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 3231 }; 3232 3233 struct lpfc_acqe_sli { 3234 uint32_t event_data1; 3235 uint32_t event_data2; 3236 uint32_t reserved; 3237 uint32_t trailer; 3238 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3239 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3240 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3241 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3242 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3243 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 3244 }; 3245 3246 /* 3247 * Define the bootstrap mailbox (bmbx) region used to communicate 3248 * mailbox command between the host and port. The mailbox consists 3249 * of a payload area of 256 bytes and a completion queue of length 3250 * 16 bytes. 3251 */ 3252 struct lpfc_bmbx_create { 3253 struct lpfc_mqe mqe; 3254 struct lpfc_mcqe mcqe; 3255 }; 3256 3257 #define SGL_ALIGN_SZ 64 3258 #define SGL_PAGE_SIZE 4096 3259 /* align SGL addr on a size boundary - adjust address up */ 3260 #define NO_XRI 0xffff 3261 3262 struct wqe_common { 3263 uint32_t word6; 3264 #define wqe_xri_tag_SHIFT 0 3265 #define wqe_xri_tag_MASK 0x0000FFFF 3266 #define wqe_xri_tag_WORD word6 3267 #define wqe_ctxt_tag_SHIFT 16 3268 #define wqe_ctxt_tag_MASK 0x0000FFFF 3269 #define wqe_ctxt_tag_WORD word6 3270 uint32_t word7; 3271 #define wqe_dif_SHIFT 0 3272 #define wqe_dif_MASK 0x00000003 3273 #define wqe_dif_WORD word7 3274 #define LPFC_WQE_DIF_PASSTHRU 1 3275 #define LPFC_WQE_DIF_STRIP 2 3276 #define LPFC_WQE_DIF_INSERT 3 3277 #define wqe_ct_SHIFT 2 3278 #define wqe_ct_MASK 0x00000003 3279 #define wqe_ct_WORD word7 3280 #define wqe_status_SHIFT 4 3281 #define wqe_status_MASK 0x0000000f 3282 #define wqe_status_WORD word7 3283 #define wqe_cmnd_SHIFT 8 3284 #define wqe_cmnd_MASK 0x000000ff 3285 #define wqe_cmnd_WORD word7 3286 #define wqe_class_SHIFT 16 3287 #define wqe_class_MASK 0x00000007 3288 #define wqe_class_WORD word7 3289 #define wqe_ar_SHIFT 19 3290 #define wqe_ar_MASK 0x00000001 3291 #define wqe_ar_WORD word7 3292 #define wqe_ag_SHIFT wqe_ar_SHIFT 3293 #define wqe_ag_MASK wqe_ar_MASK 3294 #define wqe_ag_WORD wqe_ar_WORD 3295 #define wqe_pu_SHIFT 20 3296 #define wqe_pu_MASK 0x00000003 3297 #define wqe_pu_WORD word7 3298 #define wqe_erp_SHIFT 22 3299 #define wqe_erp_MASK 0x00000001 3300 #define wqe_erp_WORD word7 3301 #define wqe_conf_SHIFT wqe_erp_SHIFT 3302 #define wqe_conf_MASK wqe_erp_MASK 3303 #define wqe_conf_WORD wqe_erp_WORD 3304 #define wqe_lnk_SHIFT 23 3305 #define wqe_lnk_MASK 0x00000001 3306 #define wqe_lnk_WORD word7 3307 #define wqe_tmo_SHIFT 24 3308 #define wqe_tmo_MASK 0x000000ff 3309 #define wqe_tmo_WORD word7 3310 uint32_t abort_tag; /* word 8 in WQE */ 3311 uint32_t word9; 3312 #define wqe_reqtag_SHIFT 0 3313 #define wqe_reqtag_MASK 0x0000FFFF 3314 #define wqe_reqtag_WORD word9 3315 #define wqe_temp_rpi_SHIFT 16 3316 #define wqe_temp_rpi_MASK 0x0000FFFF 3317 #define wqe_temp_rpi_WORD word9 3318 #define wqe_rcvoxid_SHIFT 16 3319 #define wqe_rcvoxid_MASK 0x0000FFFF 3320 #define wqe_rcvoxid_WORD word9 3321 uint32_t word10; 3322 #define wqe_ebde_cnt_SHIFT 0 3323 #define wqe_ebde_cnt_MASK 0x0000000f 3324 #define wqe_ebde_cnt_WORD word10 3325 #define wqe_lenloc_SHIFT 7 3326 #define wqe_lenloc_MASK 0x00000003 3327 #define wqe_lenloc_WORD word10 3328 #define LPFC_WQE_LENLOC_NONE 0 3329 #define LPFC_WQE_LENLOC_WORD3 1 3330 #define LPFC_WQE_LENLOC_WORD12 2 3331 #define LPFC_WQE_LENLOC_WORD4 3 3332 #define wqe_qosd_SHIFT 9 3333 #define wqe_qosd_MASK 0x00000001 3334 #define wqe_qosd_WORD word10 3335 #define wqe_xbl_SHIFT 11 3336 #define wqe_xbl_MASK 0x00000001 3337 #define wqe_xbl_WORD word10 3338 #define wqe_iod_SHIFT 13 3339 #define wqe_iod_MASK 0x00000001 3340 #define wqe_iod_WORD word10 3341 #define LPFC_WQE_IOD_WRITE 0 3342 #define LPFC_WQE_IOD_READ 1 3343 #define wqe_dbde_SHIFT 14 3344 #define wqe_dbde_MASK 0x00000001 3345 #define wqe_dbde_WORD word10 3346 #define wqe_wqes_SHIFT 15 3347 #define wqe_wqes_MASK 0x00000001 3348 #define wqe_wqes_WORD word10 3349 /* Note that this field overlaps above fields */ 3350 #define wqe_wqid_SHIFT 1 3351 #define wqe_wqid_MASK 0x00007fff 3352 #define wqe_wqid_WORD word10 3353 #define wqe_pri_SHIFT 16 3354 #define wqe_pri_MASK 0x00000007 3355 #define wqe_pri_WORD word10 3356 #define wqe_pv_SHIFT 19 3357 #define wqe_pv_MASK 0x00000001 3358 #define wqe_pv_WORD word10 3359 #define wqe_xc_SHIFT 21 3360 #define wqe_xc_MASK 0x00000001 3361 #define wqe_xc_WORD word10 3362 #define wqe_sr_SHIFT 22 3363 #define wqe_sr_MASK 0x00000001 3364 #define wqe_sr_WORD word10 3365 #define wqe_ccpe_SHIFT 23 3366 #define wqe_ccpe_MASK 0x00000001 3367 #define wqe_ccpe_WORD word10 3368 #define wqe_ccp_SHIFT 24 3369 #define wqe_ccp_MASK 0x000000ff 3370 #define wqe_ccp_WORD word10 3371 uint32_t word11; 3372 #define wqe_cmd_type_SHIFT 0 3373 #define wqe_cmd_type_MASK 0x0000000f 3374 #define wqe_cmd_type_WORD word11 3375 #define wqe_els_id_SHIFT 4 3376 #define wqe_els_id_MASK 0x00000003 3377 #define wqe_els_id_WORD word11 3378 #define LPFC_ELS_ID_FLOGI 3 3379 #define LPFC_ELS_ID_FDISC 2 3380 #define LPFC_ELS_ID_LOGO 1 3381 #define LPFC_ELS_ID_DEFAULT 0 3382 #define wqe_wqec_SHIFT 7 3383 #define wqe_wqec_MASK 0x00000001 3384 #define wqe_wqec_WORD word11 3385 #define wqe_cqid_SHIFT 16 3386 #define wqe_cqid_MASK 0x0000ffff 3387 #define wqe_cqid_WORD word11 3388 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3389 }; 3390 3391 struct wqe_did { 3392 uint32_t word5; 3393 #define wqe_els_did_SHIFT 0 3394 #define wqe_els_did_MASK 0x00FFFFFF 3395 #define wqe_els_did_WORD word5 3396 #define wqe_xmit_bls_pt_SHIFT 28 3397 #define wqe_xmit_bls_pt_MASK 0x00000003 3398 #define wqe_xmit_bls_pt_WORD word5 3399 #define wqe_xmit_bls_ar_SHIFT 30 3400 #define wqe_xmit_bls_ar_MASK 0x00000001 3401 #define wqe_xmit_bls_ar_WORD word5 3402 #define wqe_xmit_bls_xo_SHIFT 31 3403 #define wqe_xmit_bls_xo_MASK 0x00000001 3404 #define wqe_xmit_bls_xo_WORD word5 3405 }; 3406 3407 struct lpfc_wqe_generic{ 3408 struct ulp_bde64 bde; 3409 uint32_t word3; 3410 uint32_t word4; 3411 uint32_t word5; 3412 struct wqe_common wqe_com; 3413 uint32_t payload[4]; 3414 }; 3415 3416 struct els_request64_wqe { 3417 struct ulp_bde64 bde; 3418 uint32_t payload_len; 3419 uint32_t word4; 3420 #define els_req64_sid_SHIFT 0 3421 #define els_req64_sid_MASK 0x00FFFFFF 3422 #define els_req64_sid_WORD word4 3423 #define els_req64_sp_SHIFT 24 3424 #define els_req64_sp_MASK 0x00000001 3425 #define els_req64_sp_WORD word4 3426 #define els_req64_vf_SHIFT 25 3427 #define els_req64_vf_MASK 0x00000001 3428 #define els_req64_vf_WORD word4 3429 struct wqe_did wqe_dest; 3430 struct wqe_common wqe_com; /* words 6-11 */ 3431 uint32_t word12; 3432 #define els_req64_vfid_SHIFT 1 3433 #define els_req64_vfid_MASK 0x00000FFF 3434 #define els_req64_vfid_WORD word12 3435 #define els_req64_pri_SHIFT 13 3436 #define els_req64_pri_MASK 0x00000007 3437 #define els_req64_pri_WORD word12 3438 uint32_t word13; 3439 #define els_req64_hopcnt_SHIFT 24 3440 #define els_req64_hopcnt_MASK 0x000000ff 3441 #define els_req64_hopcnt_WORD word13 3442 uint32_t word14; 3443 uint32_t max_response_payload_len; 3444 }; 3445 3446 struct xmit_els_rsp64_wqe { 3447 struct ulp_bde64 bde; 3448 uint32_t response_payload_len; 3449 uint32_t word4; 3450 #define els_rsp64_sid_SHIFT 0 3451 #define els_rsp64_sid_MASK 0x00FFFFFF 3452 #define els_rsp64_sid_WORD word4 3453 #define els_rsp64_sp_SHIFT 24 3454 #define els_rsp64_sp_MASK 0x00000001 3455 #define els_rsp64_sp_WORD word4 3456 struct wqe_did wqe_dest; 3457 struct wqe_common wqe_com; /* words 6-11 */ 3458 uint32_t word12; 3459 #define wqe_rsp_temp_rpi_SHIFT 0 3460 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3461 #define wqe_rsp_temp_rpi_WORD word12 3462 uint32_t rsvd_13_15[3]; 3463 }; 3464 3465 struct xmit_bls_rsp64_wqe { 3466 uint32_t payload0; 3467 /* Payload0 for BA_ACC */ 3468 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3469 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3470 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3471 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3472 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3473 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3474 /* Payload0 for BA_RJT */ 3475 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3476 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3477 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3478 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3479 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3480 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3481 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3482 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3483 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3484 uint32_t word1; 3485 #define xmit_bls_rsp64_rxid_SHIFT 0 3486 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3487 #define xmit_bls_rsp64_rxid_WORD word1 3488 #define xmit_bls_rsp64_oxid_SHIFT 16 3489 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3490 #define xmit_bls_rsp64_oxid_WORD word1 3491 uint32_t word2; 3492 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3493 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3494 #define xmit_bls_rsp64_seqcnthi_WORD word2 3495 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3496 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3497 #define xmit_bls_rsp64_seqcntlo_WORD word2 3498 uint32_t rsrvd3; 3499 uint32_t rsrvd4; 3500 struct wqe_did wqe_dest; 3501 struct wqe_common wqe_com; /* words 6-11 */ 3502 uint32_t word12; 3503 #define xmit_bls_rsp64_temprpi_SHIFT 0 3504 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3505 #define xmit_bls_rsp64_temprpi_WORD word12 3506 uint32_t rsvd_13_15[3]; 3507 }; 3508 3509 struct wqe_rctl_dfctl { 3510 uint32_t word5; 3511 #define wqe_si_SHIFT 2 3512 #define wqe_si_MASK 0x000000001 3513 #define wqe_si_WORD word5 3514 #define wqe_la_SHIFT 3 3515 #define wqe_la_MASK 0x000000001 3516 #define wqe_la_WORD word5 3517 #define wqe_xo_SHIFT 6 3518 #define wqe_xo_MASK 0x000000001 3519 #define wqe_xo_WORD word5 3520 #define wqe_ls_SHIFT 7 3521 #define wqe_ls_MASK 0x000000001 3522 #define wqe_ls_WORD word5 3523 #define wqe_dfctl_SHIFT 8 3524 #define wqe_dfctl_MASK 0x0000000ff 3525 #define wqe_dfctl_WORD word5 3526 #define wqe_type_SHIFT 16 3527 #define wqe_type_MASK 0x0000000ff 3528 #define wqe_type_WORD word5 3529 #define wqe_rctl_SHIFT 24 3530 #define wqe_rctl_MASK 0x0000000ff 3531 #define wqe_rctl_WORD word5 3532 }; 3533 3534 struct xmit_seq64_wqe { 3535 struct ulp_bde64 bde; 3536 uint32_t rsvd3; 3537 uint32_t relative_offset; 3538 struct wqe_rctl_dfctl wge_ctl; 3539 struct wqe_common wqe_com; /* words 6-11 */ 3540 uint32_t xmit_len; 3541 uint32_t rsvd_12_15[3]; 3542 }; 3543 struct xmit_bcast64_wqe { 3544 struct ulp_bde64 bde; 3545 uint32_t seq_payload_len; 3546 uint32_t rsvd4; 3547 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3548 struct wqe_common wqe_com; /* words 6-11 */ 3549 uint32_t rsvd_12_15[4]; 3550 }; 3551 3552 struct gen_req64_wqe { 3553 struct ulp_bde64 bde; 3554 uint32_t request_payload_len; 3555 uint32_t relative_offset; 3556 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3557 struct wqe_common wqe_com; /* words 6-11 */ 3558 uint32_t rsvd_12_14[3]; 3559 uint32_t max_response_payload_len; 3560 }; 3561 3562 struct create_xri_wqe { 3563 uint32_t rsrvd[5]; /* words 0-4 */ 3564 struct wqe_did wqe_dest; /* word 5 */ 3565 struct wqe_common wqe_com; /* words 6-11 */ 3566 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3567 }; 3568 3569 #define T_REQUEST_TAG 3 3570 #define T_XRI_TAG 1 3571 3572 struct abort_cmd_wqe { 3573 uint32_t rsrvd[3]; 3574 uint32_t word3; 3575 #define abort_cmd_ia_SHIFT 0 3576 #define abort_cmd_ia_MASK 0x000000001 3577 #define abort_cmd_ia_WORD word3 3578 #define abort_cmd_criteria_SHIFT 8 3579 #define abort_cmd_criteria_MASK 0x0000000ff 3580 #define abort_cmd_criteria_WORD word3 3581 uint32_t rsrvd4; 3582 uint32_t rsrvd5; 3583 struct wqe_common wqe_com; /* words 6-11 */ 3584 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3585 }; 3586 3587 struct fcp_iwrite64_wqe { 3588 struct ulp_bde64 bde; 3589 uint32_t word3; 3590 #define cmd_buff_len_SHIFT 16 3591 #define cmd_buff_len_MASK 0x00000ffff 3592 #define cmd_buff_len_WORD word3 3593 #define payload_offset_len_SHIFT 0 3594 #define payload_offset_len_MASK 0x0000ffff 3595 #define payload_offset_len_WORD word3 3596 uint32_t total_xfer_len; 3597 uint32_t initial_xfer_len; 3598 struct wqe_common wqe_com; /* words 6-11 */ 3599 uint32_t rsrvd12; 3600 struct ulp_bde64 ph_bde; /* words 13-15 */ 3601 }; 3602 3603 struct fcp_iread64_wqe { 3604 struct ulp_bde64 bde; 3605 uint32_t word3; 3606 #define cmd_buff_len_SHIFT 16 3607 #define cmd_buff_len_MASK 0x00000ffff 3608 #define cmd_buff_len_WORD word3 3609 #define payload_offset_len_SHIFT 0 3610 #define payload_offset_len_MASK 0x0000ffff 3611 #define payload_offset_len_WORD word3 3612 uint32_t total_xfer_len; /* word 4 */ 3613 uint32_t rsrvd5; /* word 5 */ 3614 struct wqe_common wqe_com; /* words 6-11 */ 3615 uint32_t rsrvd12; 3616 struct ulp_bde64 ph_bde; /* words 13-15 */ 3617 }; 3618 3619 struct fcp_icmnd64_wqe { 3620 struct ulp_bde64 bde; /* words 0-2 */ 3621 uint32_t word3; 3622 #define cmd_buff_len_SHIFT 16 3623 #define cmd_buff_len_MASK 0x00000ffff 3624 #define cmd_buff_len_WORD word3 3625 #define payload_offset_len_SHIFT 0 3626 #define payload_offset_len_MASK 0x0000ffff 3627 #define payload_offset_len_WORD word3 3628 uint32_t rsrvd4; /* word 4 */ 3629 uint32_t rsrvd5; /* word 5 */ 3630 struct wqe_common wqe_com; /* words 6-11 */ 3631 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3632 }; 3633 3634 3635 union lpfc_wqe { 3636 uint32_t words[16]; 3637 struct lpfc_wqe_generic generic; 3638 struct fcp_icmnd64_wqe fcp_icmd; 3639 struct fcp_iread64_wqe fcp_iread; 3640 struct fcp_iwrite64_wqe fcp_iwrite; 3641 struct abort_cmd_wqe abort_cmd; 3642 struct create_xri_wqe create_xri; 3643 struct xmit_bcast64_wqe xmit_bcast64; 3644 struct xmit_seq64_wqe xmit_sequence; 3645 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3646 struct xmit_els_rsp64_wqe xmit_els_rsp; 3647 struct els_request64_wqe els_req; 3648 struct gen_req64_wqe gen_req; 3649 }; 3650 3651 union lpfc_wqe128 { 3652 uint32_t words[32]; 3653 struct lpfc_wqe_generic generic; 3654 struct xmit_seq64_wqe xmit_sequence; 3655 struct gen_req64_wqe gen_req; 3656 }; 3657 3658 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3659 #define LPFC_FILE_TYPE_GROUP 0xf7 3660 #define LPFC_FILE_ID_GROUP 0xa2 3661 struct lpfc_grp_hdr { 3662 uint32_t size; 3663 uint32_t magic_number; 3664 uint32_t word2; 3665 #define lpfc_grp_hdr_file_type_SHIFT 24 3666 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3667 #define lpfc_grp_hdr_file_type_WORD word2 3668 #define lpfc_grp_hdr_id_SHIFT 16 3669 #define lpfc_grp_hdr_id_MASK 0x000000FF 3670 #define lpfc_grp_hdr_id_WORD word2 3671 uint8_t rev_name[128]; 3672 uint8_t date[12]; 3673 uint8_t revision[32]; 3674 }; 3675 3676 #define FCP_COMMAND 0x0 3677 #define FCP_COMMAND_DATA_OUT 0x1 3678 #define ELS_COMMAND_NON_FIP 0xC 3679 #define ELS_COMMAND_FIP 0xD 3680 #define OTHER_COMMAND 0x8 3681 3682 #define LPFC_FW_DUMP 1 3683 #define LPFC_FW_RESET 2 3684 #define LPFC_DV_RESET 3 3685