1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE_V0 4 110 #define LPFC_MAX_WQ_PAGE 8 111 #define LPFC_MAX_CQ_PAGE 4 112 #define LPFC_MAX_EQ_PAGE 8 113 114 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 115 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 116 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 117 118 /* Define SLI4 Alignment requirements. */ 119 #define LPFC_ALIGN_16_BYTE 16 120 #define LPFC_ALIGN_64_BYTE 64 121 122 /* Define SLI4 specific definitions. */ 123 #define LPFC_MQ_CQE_BYTE_OFFSET 256 124 #define LPFC_MBX_CMD_HDR_LENGTH 16 125 #define LPFC_MBX_ERROR_RANGE 0x4000 126 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 127 #define LPFC_BMBX_BIT1_ADDR_LO 0 128 #define LPFC_RPI_HDR_COUNT 64 129 #define LPFC_HDR_TEMPLATE_SIZE 4096 130 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 131 #define LPFC_FCF_RECORD_WD_CNT 132 132 #define LPFC_ENTIRE_FCF_DATABASE 0 133 #define LPFC_DFLT_FCF_INDEX 0 134 135 /* Virtual function numbers */ 136 #define LPFC_VF0 0 137 #define LPFC_VF1 1 138 #define LPFC_VF2 2 139 #define LPFC_VF3 3 140 #define LPFC_VF4 4 141 #define LPFC_VF5 5 142 #define LPFC_VF6 6 143 #define LPFC_VF7 7 144 #define LPFC_VF8 8 145 #define LPFC_VF9 9 146 #define LPFC_VF10 10 147 #define LPFC_VF11 11 148 #define LPFC_VF12 12 149 #define LPFC_VF13 13 150 #define LPFC_VF14 14 151 #define LPFC_VF15 15 152 #define LPFC_VF16 16 153 #define LPFC_VF17 17 154 #define LPFC_VF18 18 155 #define LPFC_VF19 19 156 #define LPFC_VF20 20 157 #define LPFC_VF21 21 158 #define LPFC_VF22 22 159 #define LPFC_VF23 23 160 #define LPFC_VF24 24 161 #define LPFC_VF25 25 162 #define LPFC_VF26 26 163 #define LPFC_VF27 27 164 #define LPFC_VF28 28 165 #define LPFC_VF29 29 166 #define LPFC_VF30 30 167 #define LPFC_VF31 31 168 169 /* PCI function numbers */ 170 #define LPFC_PCI_FUNC0 0 171 #define LPFC_PCI_FUNC1 1 172 #define LPFC_PCI_FUNC2 2 173 #define LPFC_PCI_FUNC3 3 174 #define LPFC_PCI_FUNC4 4 175 176 /* SLI4 interface type-2 PDEV_CTL register */ 177 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 178 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 179 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 180 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 181 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 182 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 183 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 184 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 185 186 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 187 188 /* Active interrupt test count */ 189 #define LPFC_ACT_INTR_CNT 4 190 191 /* Algrithmns for scheduling FCP commands to WQs */ 192 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 193 #define LPFC_FCP_SCHED_BY_CPU 1 194 195 /* Delay Multiplier constant */ 196 #define LPFC_DMULT_CONST 651042 197 198 /* Configuration of Interrupts / sec for entire HBA port */ 199 #define LPFC_MIN_IMAX 5000 200 #define LPFC_MAX_IMAX 5000000 201 #define LPFC_DEF_IMAX 50000 202 203 #define LPFC_MIN_CPU_MAP 0 204 #define LPFC_MAX_CPU_MAP 2 205 #define LPFC_HBA_CPU_MAP 1 206 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 207 208 /* PORT_CAPABILITIES constants. */ 209 #define LPFC_MAX_SUPPORTED_PAGES 8 210 211 struct ulp_bde64 { 212 union ULP_BDE_TUS { 213 uint32_t w; 214 struct { 215 #ifdef __BIG_ENDIAN_BITFIELD 216 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 217 VALUE !! */ 218 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 219 #else /* __LITTLE_ENDIAN_BITFIELD */ 220 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 222 VALUE !! */ 223 #endif 224 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 225 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 226 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 227 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 228 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 229 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 230 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 231 } f; 232 } tus; 233 uint32_t addrLow; 234 uint32_t addrHigh; 235 }; 236 237 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 238 #define LPFC_MAX_BDE_IMM_SIZE 64 239 240 struct lpfc_sli4_flags { 241 uint32_t word0; 242 #define lpfc_idx_rsrc_rdy_SHIFT 0 243 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 244 #define lpfc_idx_rsrc_rdy_WORD word0 245 #define LPFC_IDX_RSRC_RDY 1 246 #define lpfc_rpi_rsrc_rdy_SHIFT 1 247 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 248 #define lpfc_rpi_rsrc_rdy_WORD word0 249 #define LPFC_RPI_RSRC_RDY 1 250 #define lpfc_vpi_rsrc_rdy_SHIFT 2 251 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 252 #define lpfc_vpi_rsrc_rdy_WORD word0 253 #define LPFC_VPI_RSRC_RDY 1 254 #define lpfc_vfi_rsrc_rdy_SHIFT 3 255 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 256 #define lpfc_vfi_rsrc_rdy_WORD word0 257 #define LPFC_VFI_RSRC_RDY 1 258 }; 259 260 struct sli4_bls_rsp { 261 uint32_t word0_rsvd; /* Word0 must be reserved */ 262 uint32_t word1; 263 #define lpfc_abts_orig_SHIFT 0 264 #define lpfc_abts_orig_MASK 0x00000001 265 #define lpfc_abts_orig_WORD word1 266 #define LPFC_ABTS_UNSOL_RSP 1 267 #define LPFC_ABTS_UNSOL_INT 0 268 uint32_t word2; 269 #define lpfc_abts_rxid_SHIFT 0 270 #define lpfc_abts_rxid_MASK 0x0000FFFF 271 #define lpfc_abts_rxid_WORD word2 272 #define lpfc_abts_oxid_SHIFT 16 273 #define lpfc_abts_oxid_MASK 0x0000FFFF 274 #define lpfc_abts_oxid_WORD word2 275 uint32_t word3; 276 #define lpfc_vndr_code_SHIFT 0 277 #define lpfc_vndr_code_MASK 0x000000FF 278 #define lpfc_vndr_code_WORD word3 279 #define lpfc_rsn_expln_SHIFT 8 280 #define lpfc_rsn_expln_MASK 0x000000FF 281 #define lpfc_rsn_expln_WORD word3 282 #define lpfc_rsn_code_SHIFT 16 283 #define lpfc_rsn_code_MASK 0x000000FF 284 #define lpfc_rsn_code_WORD word3 285 286 uint32_t word4; 287 uint32_t word5_rsvd; /* Word5 must be reserved */ 288 }; 289 290 /* event queue entry structure */ 291 struct lpfc_eqe { 292 uint32_t word0; 293 #define lpfc_eqe_resource_id_SHIFT 16 294 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 295 #define lpfc_eqe_resource_id_WORD word0 296 #define lpfc_eqe_minor_code_SHIFT 4 297 #define lpfc_eqe_minor_code_MASK 0x00000FFF 298 #define lpfc_eqe_minor_code_WORD word0 299 #define lpfc_eqe_major_code_SHIFT 1 300 #define lpfc_eqe_major_code_MASK 0x00000007 301 #define lpfc_eqe_major_code_WORD word0 302 #define lpfc_eqe_valid_SHIFT 0 303 #define lpfc_eqe_valid_MASK 0x00000001 304 #define lpfc_eqe_valid_WORD word0 305 }; 306 307 /* completion queue entry structure (common fields for all cqe types) */ 308 struct lpfc_cqe { 309 uint32_t reserved0; 310 uint32_t reserved1; 311 uint32_t reserved2; 312 uint32_t word3; 313 #define lpfc_cqe_valid_SHIFT 31 314 #define lpfc_cqe_valid_MASK 0x00000001 315 #define lpfc_cqe_valid_WORD word3 316 #define lpfc_cqe_code_SHIFT 16 317 #define lpfc_cqe_code_MASK 0x000000FF 318 #define lpfc_cqe_code_WORD word3 319 }; 320 321 /* Completion Queue Entry Status Codes */ 322 #define CQE_STATUS_SUCCESS 0x0 323 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 324 #define CQE_STATUS_REMOTE_STOP 0x2 325 #define CQE_STATUS_LOCAL_REJECT 0x3 326 #define CQE_STATUS_NPORT_RJT 0x4 327 #define CQE_STATUS_FABRIC_RJT 0x5 328 #define CQE_STATUS_NPORT_BSY 0x6 329 #define CQE_STATUS_FABRIC_BSY 0x7 330 #define CQE_STATUS_INTERMED_RSP 0x8 331 #define CQE_STATUS_LS_RJT 0x9 332 #define CQE_STATUS_CMD_REJECT 0xb 333 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 334 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 335 #define CQE_STATUS_DI_ERROR 0x16 336 337 /* Used when mapping CQE status to IOCB */ 338 #define LPFC_IOCB_STATUS_MASK 0xf 339 340 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 341 #define CQE_HW_STATUS_NO_ERR 0x0 342 #define CQE_HW_STATUS_UNDERRUN 0x1 343 #define CQE_HW_STATUS_OVERRUN 0x2 344 345 /* Completion Queue Entry Codes */ 346 #define CQE_CODE_COMPL_WQE 0x1 347 #define CQE_CODE_RELEASE_WQE 0x2 348 #define CQE_CODE_RECEIVE 0x4 349 #define CQE_CODE_XRI_ABORTED 0x5 350 #define CQE_CODE_RECEIVE_V1 0x9 351 352 /* 353 * Define mask value for xri_aborted and wcqe completed CQE extended status. 354 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 355 */ 356 #define WCQE_PARAM_MASK 0x1FF 357 358 /* completion queue entry for wqe completions */ 359 struct lpfc_wcqe_complete { 360 uint32_t word0; 361 #define lpfc_wcqe_c_request_tag_SHIFT 16 362 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 363 #define lpfc_wcqe_c_request_tag_WORD word0 364 #define lpfc_wcqe_c_status_SHIFT 8 365 #define lpfc_wcqe_c_status_MASK 0x000000FF 366 #define lpfc_wcqe_c_status_WORD word0 367 #define lpfc_wcqe_c_hw_status_SHIFT 0 368 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 369 #define lpfc_wcqe_c_hw_status_WORD word0 370 uint32_t total_data_placed; 371 uint32_t parameter; 372 #define lpfc_wcqe_c_bg_edir_SHIFT 5 373 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 374 #define lpfc_wcqe_c_bg_edir_WORD parameter 375 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 376 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 377 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 378 #define lpfc_wcqe_c_bg_re_SHIFT 2 379 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 380 #define lpfc_wcqe_c_bg_re_WORD parameter 381 #define lpfc_wcqe_c_bg_ae_SHIFT 1 382 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 383 #define lpfc_wcqe_c_bg_ae_WORD parameter 384 #define lpfc_wcqe_c_bg_ge_SHIFT 0 385 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 386 #define lpfc_wcqe_c_bg_ge_WORD parameter 387 uint32_t word3; 388 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 389 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 390 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 391 #define lpfc_wcqe_c_xb_SHIFT 28 392 #define lpfc_wcqe_c_xb_MASK 0x00000001 393 #define lpfc_wcqe_c_xb_WORD word3 394 #define lpfc_wcqe_c_pv_SHIFT 27 395 #define lpfc_wcqe_c_pv_MASK 0x00000001 396 #define lpfc_wcqe_c_pv_WORD word3 397 #define lpfc_wcqe_c_priority_SHIFT 24 398 #define lpfc_wcqe_c_priority_MASK 0x00000007 399 #define lpfc_wcqe_c_priority_WORD word3 400 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 401 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 402 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 403 }; 404 405 /* completion queue entry for wqe release */ 406 struct lpfc_wcqe_release { 407 uint32_t reserved0; 408 uint32_t reserved1; 409 uint32_t word2; 410 #define lpfc_wcqe_r_wq_id_SHIFT 16 411 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 412 #define lpfc_wcqe_r_wq_id_WORD word2 413 #define lpfc_wcqe_r_wqe_index_SHIFT 0 414 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 415 #define lpfc_wcqe_r_wqe_index_WORD word2 416 uint32_t word3; 417 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 418 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 419 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 420 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 421 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 422 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 423 }; 424 425 struct sli4_wcqe_xri_aborted { 426 uint32_t word0; 427 #define lpfc_wcqe_xa_status_SHIFT 8 428 #define lpfc_wcqe_xa_status_MASK 0x000000FF 429 #define lpfc_wcqe_xa_status_WORD word0 430 uint32_t parameter; 431 uint32_t word2; 432 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 433 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 434 #define lpfc_wcqe_xa_remote_xid_WORD word2 435 #define lpfc_wcqe_xa_xri_SHIFT 0 436 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 437 #define lpfc_wcqe_xa_xri_WORD word2 438 uint32_t word3; 439 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 440 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 441 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 442 #define lpfc_wcqe_xa_ia_SHIFT 30 443 #define lpfc_wcqe_xa_ia_MASK 0x00000001 444 #define lpfc_wcqe_xa_ia_WORD word3 445 #define CQE_XRI_ABORTED_IA_REMOTE 0 446 #define CQE_XRI_ABORTED_IA_LOCAL 1 447 #define lpfc_wcqe_xa_br_SHIFT 29 448 #define lpfc_wcqe_xa_br_MASK 0x00000001 449 #define lpfc_wcqe_xa_br_WORD word3 450 #define CQE_XRI_ABORTED_BR_BA_ACC 0 451 #define CQE_XRI_ABORTED_BR_BA_RJT 1 452 #define lpfc_wcqe_xa_eo_SHIFT 28 453 #define lpfc_wcqe_xa_eo_MASK 0x00000001 454 #define lpfc_wcqe_xa_eo_WORD word3 455 #define CQE_XRI_ABORTED_EO_REMOTE 0 456 #define CQE_XRI_ABORTED_EO_LOCAL 1 457 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 458 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 459 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 460 }; 461 462 /* completion queue entry structure for rqe completion */ 463 struct lpfc_rcqe { 464 uint32_t word0; 465 #define lpfc_rcqe_bindex_SHIFT 16 466 #define lpfc_rcqe_bindex_MASK 0x0000FFF 467 #define lpfc_rcqe_bindex_WORD word0 468 #define lpfc_rcqe_status_SHIFT 8 469 #define lpfc_rcqe_status_MASK 0x000000FF 470 #define lpfc_rcqe_status_WORD word0 471 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 472 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 473 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 474 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 475 uint32_t word1; 476 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 477 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 478 #define lpfc_rcqe_fcf_id_v1_WORD word1 479 uint32_t word2; 480 #define lpfc_rcqe_length_SHIFT 16 481 #define lpfc_rcqe_length_MASK 0x0000FFFF 482 #define lpfc_rcqe_length_WORD word2 483 #define lpfc_rcqe_rq_id_SHIFT 6 484 #define lpfc_rcqe_rq_id_MASK 0x000003FF 485 #define lpfc_rcqe_rq_id_WORD word2 486 #define lpfc_rcqe_fcf_id_SHIFT 0 487 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 488 #define lpfc_rcqe_fcf_id_WORD word2 489 #define lpfc_rcqe_rq_id_v1_SHIFT 0 490 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 491 #define lpfc_rcqe_rq_id_v1_WORD word2 492 uint32_t word3; 493 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 494 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 495 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 496 #define lpfc_rcqe_port_SHIFT 30 497 #define lpfc_rcqe_port_MASK 0x00000001 498 #define lpfc_rcqe_port_WORD word3 499 #define lpfc_rcqe_hdr_length_SHIFT 24 500 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 501 #define lpfc_rcqe_hdr_length_WORD word3 502 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 503 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 504 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 505 #define lpfc_rcqe_eof_SHIFT 8 506 #define lpfc_rcqe_eof_MASK 0x000000FF 507 #define lpfc_rcqe_eof_WORD word3 508 #define FCOE_EOFn 0x41 509 #define FCOE_EOFt 0x42 510 #define FCOE_EOFni 0x49 511 #define FCOE_EOFa 0x50 512 #define lpfc_rcqe_sof_SHIFT 0 513 #define lpfc_rcqe_sof_MASK 0x000000FF 514 #define lpfc_rcqe_sof_WORD word3 515 #define FCOE_SOFi2 0x2d 516 #define FCOE_SOFi3 0x2e 517 #define FCOE_SOFn2 0x35 518 #define FCOE_SOFn3 0x36 519 }; 520 521 struct lpfc_rqe { 522 uint32_t address_hi; 523 uint32_t address_lo; 524 }; 525 526 /* buffer descriptors */ 527 struct lpfc_bde4 { 528 uint32_t addr_hi; 529 uint32_t addr_lo; 530 uint32_t word2; 531 #define lpfc_bde4_last_SHIFT 31 532 #define lpfc_bde4_last_MASK 0x00000001 533 #define lpfc_bde4_last_WORD word2 534 #define lpfc_bde4_sge_offset_SHIFT 0 535 #define lpfc_bde4_sge_offset_MASK 0x000003FF 536 #define lpfc_bde4_sge_offset_WORD word2 537 uint32_t word3; 538 #define lpfc_bde4_length_SHIFT 0 539 #define lpfc_bde4_length_MASK 0x000000FF 540 #define lpfc_bde4_length_WORD word3 541 }; 542 543 struct lpfc_register { 544 uint32_t word0; 545 }; 546 547 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 548 #define LPFC_PORT_SEM_MASK 0xF000 549 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 550 #define LPFC_UERR_STATUS_HI 0x00A4 551 #define LPFC_UERR_STATUS_LO 0x00A0 552 #define LPFC_UE_MASK_HI 0x00AC 553 #define LPFC_UE_MASK_LO 0x00A8 554 555 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 556 #define LPFC_SLI_INTF 0x0058 557 558 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 559 #define lpfc_port_smphr_perr_SHIFT 31 560 #define lpfc_port_smphr_perr_MASK 0x1 561 #define lpfc_port_smphr_perr_WORD word0 562 #define lpfc_port_smphr_sfi_SHIFT 30 563 #define lpfc_port_smphr_sfi_MASK 0x1 564 #define lpfc_port_smphr_sfi_WORD word0 565 #define lpfc_port_smphr_nip_SHIFT 29 566 #define lpfc_port_smphr_nip_MASK 0x1 567 #define lpfc_port_smphr_nip_WORD word0 568 #define lpfc_port_smphr_ipc_SHIFT 28 569 #define lpfc_port_smphr_ipc_MASK 0x1 570 #define lpfc_port_smphr_ipc_WORD word0 571 #define lpfc_port_smphr_scr1_SHIFT 27 572 #define lpfc_port_smphr_scr1_MASK 0x1 573 #define lpfc_port_smphr_scr1_WORD word0 574 #define lpfc_port_smphr_scr2_SHIFT 26 575 #define lpfc_port_smphr_scr2_MASK 0x1 576 #define lpfc_port_smphr_scr2_WORD word0 577 #define lpfc_port_smphr_host_scratch_SHIFT 16 578 #define lpfc_port_smphr_host_scratch_MASK 0xFF 579 #define lpfc_port_smphr_host_scratch_WORD word0 580 #define lpfc_port_smphr_port_status_SHIFT 0 581 #define lpfc_port_smphr_port_status_MASK 0xFFFF 582 #define lpfc_port_smphr_port_status_WORD word0 583 584 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 585 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 586 #define LPFC_POST_STAGE_HOST_RDY 0x0002 587 #define LPFC_POST_STAGE_BE_RESET 0x0003 588 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 589 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 590 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 591 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 592 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 593 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 594 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 595 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 596 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 597 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 598 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 599 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 600 #define LPFC_POST_STAGE_ARMFW_START 0x0800 601 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 602 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 603 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 604 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 605 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 606 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 607 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 608 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 609 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 610 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 611 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 612 #define LPFC_POST_STAGE_RC_DONE 0x0B07 613 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 614 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 615 #define LPFC_POST_STAGE_PORT_READY 0xC000 616 #define LPFC_POST_STAGE_PORT_UE 0xF000 617 618 #define LPFC_CTL_PORT_STA_OFFSET 0x404 619 #define lpfc_sliport_status_err_SHIFT 31 620 #define lpfc_sliport_status_err_MASK 0x1 621 #define lpfc_sliport_status_err_WORD word0 622 #define lpfc_sliport_status_end_SHIFT 30 623 #define lpfc_sliport_status_end_MASK 0x1 624 #define lpfc_sliport_status_end_WORD word0 625 #define lpfc_sliport_status_oti_SHIFT 29 626 #define lpfc_sliport_status_oti_MASK 0x1 627 #define lpfc_sliport_status_oti_WORD word0 628 #define lpfc_sliport_status_rn_SHIFT 24 629 #define lpfc_sliport_status_rn_MASK 0x1 630 #define lpfc_sliport_status_rn_WORD word0 631 #define lpfc_sliport_status_rdy_SHIFT 23 632 #define lpfc_sliport_status_rdy_MASK 0x1 633 #define lpfc_sliport_status_rdy_WORD word0 634 #define MAX_IF_TYPE_2_RESETS 6 635 636 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 637 #define lpfc_sliport_ctrl_end_SHIFT 30 638 #define lpfc_sliport_ctrl_end_MASK 0x1 639 #define lpfc_sliport_ctrl_end_WORD word0 640 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 641 #define LPFC_SLIPORT_BIG_ENDIAN 1 642 #define lpfc_sliport_ctrl_ip_SHIFT 27 643 #define lpfc_sliport_ctrl_ip_MASK 0x1 644 #define lpfc_sliport_ctrl_ip_WORD word0 645 #define LPFC_SLIPORT_INIT_PORT 1 646 647 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 648 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 649 650 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 651 * reside in BAR 2. 652 */ 653 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 654 655 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 656 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 657 658 #define LPFC_HST_ISR0 0x0C18 659 #define LPFC_HST_ISR1 0x0C1C 660 #define LPFC_HST_ISR2 0x0C20 661 #define LPFC_HST_ISR3 0x0C24 662 #define LPFC_HST_ISR4 0x0C28 663 664 #define LPFC_HST_IMR0 0x0C48 665 #define LPFC_HST_IMR1 0x0C4C 666 #define LPFC_HST_IMR2 0x0C50 667 #define LPFC_HST_IMR3 0x0C54 668 #define LPFC_HST_IMR4 0x0C58 669 670 #define LPFC_HST_ISCR0 0x0C78 671 #define LPFC_HST_ISCR1 0x0C7C 672 #define LPFC_HST_ISCR2 0x0C80 673 #define LPFC_HST_ISCR3 0x0C84 674 #define LPFC_HST_ISCR4 0x0C88 675 676 #define LPFC_SLI4_INTR0 BIT0 677 #define LPFC_SLI4_INTR1 BIT1 678 #define LPFC_SLI4_INTR2 BIT2 679 #define LPFC_SLI4_INTR3 BIT3 680 #define LPFC_SLI4_INTR4 BIT4 681 #define LPFC_SLI4_INTR5 BIT5 682 #define LPFC_SLI4_INTR6 BIT6 683 #define LPFC_SLI4_INTR7 BIT7 684 #define LPFC_SLI4_INTR8 BIT8 685 #define LPFC_SLI4_INTR9 BIT9 686 #define LPFC_SLI4_INTR10 BIT10 687 #define LPFC_SLI4_INTR11 BIT11 688 #define LPFC_SLI4_INTR12 BIT12 689 #define LPFC_SLI4_INTR13 BIT13 690 #define LPFC_SLI4_INTR14 BIT14 691 #define LPFC_SLI4_INTR15 BIT15 692 #define LPFC_SLI4_INTR16 BIT16 693 #define LPFC_SLI4_INTR17 BIT17 694 #define LPFC_SLI4_INTR18 BIT18 695 #define LPFC_SLI4_INTR19 BIT19 696 #define LPFC_SLI4_INTR20 BIT20 697 #define LPFC_SLI4_INTR21 BIT21 698 #define LPFC_SLI4_INTR22 BIT22 699 #define LPFC_SLI4_INTR23 BIT23 700 #define LPFC_SLI4_INTR24 BIT24 701 #define LPFC_SLI4_INTR25 BIT25 702 #define LPFC_SLI4_INTR26 BIT26 703 #define LPFC_SLI4_INTR27 BIT27 704 #define LPFC_SLI4_INTR28 BIT28 705 #define LPFC_SLI4_INTR29 BIT29 706 #define LPFC_SLI4_INTR30 BIT30 707 #define LPFC_SLI4_INTR31 BIT31 708 709 /* 710 * The Doorbell registers defined here exist in different BAR 711 * register sets depending on the UCNA Port's reported if_type 712 * value. For UCNA ports running SLI4 and if_type 0, they reside in 713 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 714 * BAR0. The offsets are the same so the driver must account for 715 * any base address difference. 716 */ 717 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 718 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 719 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 720 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 721 #define lpfc_rq_db_list_fm_num_posted_WORD word0 722 #define lpfc_rq_db_list_fm_index_SHIFT 16 723 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 724 #define lpfc_rq_db_list_fm_index_WORD word0 725 #define lpfc_rq_db_list_fm_id_SHIFT 0 726 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 727 #define lpfc_rq_db_list_fm_id_WORD word0 728 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 729 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 730 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 731 #define lpfc_rq_db_ring_fm_id_SHIFT 0 732 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 733 #define lpfc_rq_db_ring_fm_id_WORD word0 734 735 #define LPFC_ULP0_WQ_DOORBELL 0x0040 736 #define LPFC_ULP1_WQ_DOORBELL 0x0060 737 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 738 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 739 #define lpfc_wq_db_list_fm_num_posted_WORD word0 740 #define lpfc_wq_db_list_fm_index_SHIFT 16 741 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 742 #define lpfc_wq_db_list_fm_index_WORD word0 743 #define lpfc_wq_db_list_fm_id_SHIFT 0 744 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 745 #define lpfc_wq_db_list_fm_id_WORD word0 746 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 747 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 748 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 749 #define lpfc_wq_db_ring_fm_id_SHIFT 0 750 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 751 #define lpfc_wq_db_ring_fm_id_WORD word0 752 753 #define LPFC_EQCQ_DOORBELL 0x0120 754 #define lpfc_eqcq_doorbell_se_SHIFT 31 755 #define lpfc_eqcq_doorbell_se_MASK 0x0001 756 #define lpfc_eqcq_doorbell_se_WORD word0 757 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 758 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 759 #define lpfc_eqcq_doorbell_arm_SHIFT 29 760 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 761 #define lpfc_eqcq_doorbell_arm_WORD word0 762 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 763 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 764 #define lpfc_eqcq_doorbell_num_released_WORD word0 765 #define lpfc_eqcq_doorbell_qt_SHIFT 10 766 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 767 #define lpfc_eqcq_doorbell_qt_WORD word0 768 #define LPFC_QUEUE_TYPE_COMPLETION 0 769 #define LPFC_QUEUE_TYPE_EVENT 1 770 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 771 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 772 #define lpfc_eqcq_doorbell_eqci_WORD word0 773 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 774 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 775 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 776 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 777 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 778 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 779 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 780 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 781 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 782 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 783 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 784 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 785 #define LPFC_CQID_HI_FIELD_SHIFT 10 786 #define LPFC_EQID_HI_FIELD_SHIFT 9 787 788 #define LPFC_BMBX 0x0160 789 #define lpfc_bmbx_addr_SHIFT 2 790 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 791 #define lpfc_bmbx_addr_WORD word0 792 #define lpfc_bmbx_hi_SHIFT 1 793 #define lpfc_bmbx_hi_MASK 0x0001 794 #define lpfc_bmbx_hi_WORD word0 795 #define lpfc_bmbx_rdy_SHIFT 0 796 #define lpfc_bmbx_rdy_MASK 0x0001 797 #define lpfc_bmbx_rdy_WORD word0 798 799 #define LPFC_MQ_DOORBELL 0x0140 800 #define lpfc_mq_doorbell_num_posted_SHIFT 16 801 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 802 #define lpfc_mq_doorbell_num_posted_WORD word0 803 #define lpfc_mq_doorbell_id_SHIFT 0 804 #define lpfc_mq_doorbell_id_MASK 0xFFFF 805 #define lpfc_mq_doorbell_id_WORD word0 806 807 struct lpfc_sli4_cfg_mhdr { 808 uint32_t word1; 809 #define lpfc_mbox_hdr_emb_SHIFT 0 810 #define lpfc_mbox_hdr_emb_MASK 0x00000001 811 #define lpfc_mbox_hdr_emb_WORD word1 812 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 813 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 814 #define lpfc_mbox_hdr_sge_cnt_WORD word1 815 uint32_t payload_length; 816 uint32_t tag_lo; 817 uint32_t tag_hi; 818 uint32_t reserved5; 819 }; 820 821 union lpfc_sli4_cfg_shdr { 822 struct { 823 uint32_t word6; 824 #define lpfc_mbox_hdr_opcode_SHIFT 0 825 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 826 #define lpfc_mbox_hdr_opcode_WORD word6 827 #define lpfc_mbox_hdr_subsystem_SHIFT 8 828 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 829 #define lpfc_mbox_hdr_subsystem_WORD word6 830 #define lpfc_mbox_hdr_port_number_SHIFT 16 831 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 832 #define lpfc_mbox_hdr_port_number_WORD word6 833 #define lpfc_mbox_hdr_domain_SHIFT 24 834 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 835 #define lpfc_mbox_hdr_domain_WORD word6 836 uint32_t timeout; 837 uint32_t request_length; 838 uint32_t word9; 839 #define lpfc_mbox_hdr_version_SHIFT 0 840 #define lpfc_mbox_hdr_version_MASK 0x000000FF 841 #define lpfc_mbox_hdr_version_WORD word9 842 #define lpfc_mbox_hdr_pf_num_SHIFT 16 843 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 844 #define lpfc_mbox_hdr_pf_num_WORD word9 845 #define lpfc_mbox_hdr_vh_num_SHIFT 24 846 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 847 #define lpfc_mbox_hdr_vh_num_WORD word9 848 #define LPFC_Q_CREATE_VERSION_2 2 849 #define LPFC_Q_CREATE_VERSION_1 1 850 #define LPFC_Q_CREATE_VERSION_0 0 851 #define LPFC_OPCODE_VERSION_0 0 852 #define LPFC_OPCODE_VERSION_1 1 853 } request; 854 struct { 855 uint32_t word6; 856 #define lpfc_mbox_hdr_opcode_SHIFT 0 857 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 858 #define lpfc_mbox_hdr_opcode_WORD word6 859 #define lpfc_mbox_hdr_subsystem_SHIFT 8 860 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 861 #define lpfc_mbox_hdr_subsystem_WORD word6 862 #define lpfc_mbox_hdr_domain_SHIFT 24 863 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 864 #define lpfc_mbox_hdr_domain_WORD word6 865 uint32_t word7; 866 #define lpfc_mbox_hdr_status_SHIFT 0 867 #define lpfc_mbox_hdr_status_MASK 0x000000FF 868 #define lpfc_mbox_hdr_status_WORD word7 869 #define lpfc_mbox_hdr_add_status_SHIFT 8 870 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 871 #define lpfc_mbox_hdr_add_status_WORD word7 872 uint32_t response_length; 873 uint32_t actual_response_length; 874 } response; 875 }; 876 877 /* Mailbox Header structures. 878 * struct mbox_header is defined for first generation SLI4_CFG mailbox 879 * calls deployed for BE-based ports. 880 * 881 * struct sli4_mbox_header is defined for second generation SLI4 882 * ports that don't deploy the SLI4_CFG mechanism. 883 */ 884 struct mbox_header { 885 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 886 union lpfc_sli4_cfg_shdr cfg_shdr; 887 }; 888 889 #define LPFC_EXTENT_LOCAL 0 890 #define LPFC_TIMEOUT_DEFAULT 0 891 #define LPFC_EXTENT_VERSION_DEFAULT 0 892 893 /* Subsystem Definitions */ 894 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 895 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 896 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 897 898 /* Device Specific Definitions */ 899 900 /* The HOST ENDIAN defines are in Big Endian format. */ 901 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 902 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 903 904 /* Common Opcodes */ 905 #define LPFC_MBOX_OPCODE_NA 0x00 906 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 907 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 908 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 909 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 910 #define LPFC_MBOX_OPCODE_NOP 0x21 911 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 912 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 913 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 914 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 915 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 916 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 917 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 918 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 919 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 920 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 921 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 922 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 923 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 924 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 925 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 926 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 927 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 928 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 929 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 930 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 931 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 932 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 933 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 934 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 935 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 936 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 937 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 938 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 939 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 940 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 941 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 942 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 943 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 944 945 /* FCoE Opcodes */ 946 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 947 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 948 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 949 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 950 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 951 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 952 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 953 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 954 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 955 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 956 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 957 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 958 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 959 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 960 961 /* Mailbox command structures */ 962 struct eq_context { 963 uint32_t word0; 964 #define lpfc_eq_context_size_SHIFT 31 965 #define lpfc_eq_context_size_MASK 0x00000001 966 #define lpfc_eq_context_size_WORD word0 967 #define LPFC_EQE_SIZE_4 0x0 968 #define LPFC_EQE_SIZE_16 0x1 969 #define lpfc_eq_context_valid_SHIFT 29 970 #define lpfc_eq_context_valid_MASK 0x00000001 971 #define lpfc_eq_context_valid_WORD word0 972 uint32_t word1; 973 #define lpfc_eq_context_count_SHIFT 26 974 #define lpfc_eq_context_count_MASK 0x00000003 975 #define lpfc_eq_context_count_WORD word1 976 #define LPFC_EQ_CNT_256 0x0 977 #define LPFC_EQ_CNT_512 0x1 978 #define LPFC_EQ_CNT_1024 0x2 979 #define LPFC_EQ_CNT_2048 0x3 980 #define LPFC_EQ_CNT_4096 0x4 981 uint32_t word2; 982 #define lpfc_eq_context_delay_multi_SHIFT 13 983 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 984 #define lpfc_eq_context_delay_multi_WORD word2 985 uint32_t reserved3; 986 }; 987 988 struct eq_delay_info { 989 uint32_t eq_id; 990 uint32_t phase; 991 uint32_t delay_multi; 992 }; 993 #define LPFC_MAX_EQ_DELAY 8 994 995 struct sgl_page_pairs { 996 uint32_t sgl_pg0_addr_lo; 997 uint32_t sgl_pg0_addr_hi; 998 uint32_t sgl_pg1_addr_lo; 999 uint32_t sgl_pg1_addr_hi; 1000 }; 1001 1002 struct lpfc_mbx_post_sgl_pages { 1003 struct mbox_header header; 1004 uint32_t word0; 1005 #define lpfc_post_sgl_pages_xri_SHIFT 0 1006 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1007 #define lpfc_post_sgl_pages_xri_WORD word0 1008 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1009 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1010 #define lpfc_post_sgl_pages_xricnt_WORD word0 1011 struct sgl_page_pairs sgl_pg_pairs[1]; 1012 }; 1013 1014 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1015 struct lpfc_mbx_post_uembed_sgl_page1 { 1016 union lpfc_sli4_cfg_shdr cfg_shdr; 1017 uint32_t word0; 1018 struct sgl_page_pairs sgl_pg_pairs; 1019 }; 1020 1021 struct lpfc_mbx_sge { 1022 uint32_t pa_lo; 1023 uint32_t pa_hi; 1024 uint32_t length; 1025 }; 1026 1027 struct lpfc_mbx_nembed_cmd { 1028 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1029 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1030 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1031 }; 1032 1033 struct lpfc_mbx_nembed_sge_virt { 1034 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1035 }; 1036 1037 struct lpfc_mbx_eq_create { 1038 struct mbox_header header; 1039 union { 1040 struct { 1041 uint32_t word0; 1042 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1043 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1044 #define lpfc_mbx_eq_create_num_pages_WORD word0 1045 struct eq_context context; 1046 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1047 } request; 1048 struct { 1049 uint32_t word0; 1050 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1051 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1052 #define lpfc_mbx_eq_create_q_id_WORD word0 1053 } response; 1054 } u; 1055 }; 1056 1057 struct lpfc_mbx_modify_eq_delay { 1058 struct mbox_header header; 1059 union { 1060 struct { 1061 uint32_t num_eq; 1062 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY]; 1063 } request; 1064 struct { 1065 uint32_t word0; 1066 } response; 1067 } u; 1068 }; 1069 1070 struct lpfc_mbx_eq_destroy { 1071 struct mbox_header header; 1072 union { 1073 struct { 1074 uint32_t word0; 1075 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1076 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1077 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1078 } request; 1079 struct { 1080 uint32_t word0; 1081 } response; 1082 } u; 1083 }; 1084 1085 struct lpfc_mbx_nop { 1086 struct mbox_header header; 1087 uint32_t context[2]; 1088 }; 1089 1090 struct cq_context { 1091 uint32_t word0; 1092 #define lpfc_cq_context_event_SHIFT 31 1093 #define lpfc_cq_context_event_MASK 0x00000001 1094 #define lpfc_cq_context_event_WORD word0 1095 #define lpfc_cq_context_valid_SHIFT 29 1096 #define lpfc_cq_context_valid_MASK 0x00000001 1097 #define lpfc_cq_context_valid_WORD word0 1098 #define lpfc_cq_context_count_SHIFT 27 1099 #define lpfc_cq_context_count_MASK 0x00000003 1100 #define lpfc_cq_context_count_WORD word0 1101 #define LPFC_CQ_CNT_256 0x0 1102 #define LPFC_CQ_CNT_512 0x1 1103 #define LPFC_CQ_CNT_1024 0x2 1104 uint32_t word1; 1105 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1106 #define lpfc_cq_eq_id_MASK 0x000000FF 1107 #define lpfc_cq_eq_id_WORD word1 1108 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1109 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1110 #define lpfc_cq_eq_id_2_WORD word1 1111 uint32_t reserved0; 1112 uint32_t reserved1; 1113 }; 1114 1115 struct lpfc_mbx_cq_create { 1116 struct mbox_header header; 1117 union { 1118 struct { 1119 uint32_t word0; 1120 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1121 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1122 #define lpfc_mbx_cq_create_page_size_WORD word0 1123 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1124 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1125 #define lpfc_mbx_cq_create_num_pages_WORD word0 1126 struct cq_context context; 1127 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1128 } request; 1129 struct { 1130 uint32_t word0; 1131 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1132 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1133 #define lpfc_mbx_cq_create_q_id_WORD word0 1134 } response; 1135 } u; 1136 }; 1137 1138 struct lpfc_mbx_cq_destroy { 1139 struct mbox_header header; 1140 union { 1141 struct { 1142 uint32_t word0; 1143 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1144 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1145 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1146 } request; 1147 struct { 1148 uint32_t word0; 1149 } response; 1150 } u; 1151 }; 1152 1153 struct wq_context { 1154 uint32_t reserved0; 1155 uint32_t reserved1; 1156 uint32_t reserved2; 1157 uint32_t reserved3; 1158 }; 1159 1160 struct lpfc_mbx_wq_create { 1161 struct mbox_header header; 1162 union { 1163 struct { /* Version 0 Request */ 1164 uint32_t word0; 1165 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1166 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1167 #define lpfc_mbx_wq_create_num_pages_WORD word0 1168 #define lpfc_mbx_wq_create_dua_SHIFT 8 1169 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1170 #define lpfc_mbx_wq_create_dua_WORD word0 1171 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1172 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1173 #define lpfc_mbx_wq_create_cq_id_WORD word0 1174 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1175 uint32_t word9; 1176 #define lpfc_mbx_wq_create_bua_SHIFT 0 1177 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1178 #define lpfc_mbx_wq_create_bua_WORD word9 1179 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1180 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1181 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1182 } request; 1183 struct { /* Version 1 Request */ 1184 uint32_t word0; /* Word 0 is the same as in v0 */ 1185 uint32_t word1; 1186 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1187 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1188 #define lpfc_mbx_wq_create_page_size_WORD word1 1189 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1190 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1191 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1192 #define LPFC_WQ_WQE_SIZE_64 0x5 1193 #define LPFC_WQ_WQE_SIZE_128 0x6 1194 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1195 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1196 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1197 uint32_t word2; 1198 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1199 } request_1; 1200 struct { 1201 uint32_t word0; 1202 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1203 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1204 #define lpfc_mbx_wq_create_q_id_WORD word0 1205 uint32_t doorbell_offset; 1206 uint32_t word2; 1207 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1208 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1209 #define lpfc_mbx_wq_create_bar_set_WORD word2 1210 #define WQ_PCI_BAR_0_AND_1 0x00 1211 #define WQ_PCI_BAR_2_AND_3 0x01 1212 #define WQ_PCI_BAR_4_AND_5 0x02 1213 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1214 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1215 #define lpfc_mbx_wq_create_db_format_WORD word2 1216 } response; 1217 } u; 1218 }; 1219 1220 struct lpfc_mbx_wq_destroy { 1221 struct mbox_header header; 1222 union { 1223 struct { 1224 uint32_t word0; 1225 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1226 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1227 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1228 } request; 1229 struct { 1230 uint32_t word0; 1231 } response; 1232 } u; 1233 }; 1234 1235 #define LPFC_HDR_BUF_SIZE 128 1236 #define LPFC_DATA_BUF_SIZE 2048 1237 struct rq_context { 1238 uint32_t word0; 1239 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1240 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1241 #define lpfc_rq_context_rqe_count_WORD word0 1242 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1243 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1244 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1245 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1246 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1247 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1248 #define lpfc_rq_context_rqe_count_1_WORD word0 1249 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1250 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1251 #define lpfc_rq_context_rqe_size_WORD word0 1252 #define LPFC_RQE_SIZE_8 2 1253 #define LPFC_RQE_SIZE_16 3 1254 #define LPFC_RQE_SIZE_32 4 1255 #define LPFC_RQE_SIZE_64 5 1256 #define LPFC_RQE_SIZE_128 6 1257 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1258 #define lpfc_rq_context_page_size_MASK 0x000000FF 1259 #define lpfc_rq_context_page_size_WORD word0 1260 uint32_t reserved1; 1261 uint32_t word2; 1262 #define lpfc_rq_context_cq_id_SHIFT 16 1263 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1264 #define lpfc_rq_context_cq_id_WORD word2 1265 #define lpfc_rq_context_buf_size_SHIFT 0 1266 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1267 #define lpfc_rq_context_buf_size_WORD word2 1268 uint32_t buffer_size; /* Version 1 Only */ 1269 }; 1270 1271 struct lpfc_mbx_rq_create { 1272 struct mbox_header header; 1273 union { 1274 struct { 1275 uint32_t word0; 1276 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1277 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1278 #define lpfc_mbx_rq_create_num_pages_WORD word0 1279 #define lpfc_mbx_rq_create_dua_SHIFT 16 1280 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1281 #define lpfc_mbx_rq_create_dua_WORD word0 1282 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1283 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1284 #define lpfc_mbx_rq_create_bqu_WORD word0 1285 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1286 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1287 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1288 struct rq_context context; 1289 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1290 } request; 1291 struct { 1292 uint32_t word0; 1293 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1294 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1295 #define lpfc_mbx_rq_create_q_id_WORD word0 1296 uint32_t doorbell_offset; 1297 uint32_t word2; 1298 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1299 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1300 #define lpfc_mbx_rq_create_bar_set_WORD word2 1301 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1302 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1303 #define lpfc_mbx_rq_create_db_format_WORD word2 1304 } response; 1305 } u; 1306 }; 1307 1308 struct lpfc_mbx_rq_destroy { 1309 struct mbox_header header; 1310 union { 1311 struct { 1312 uint32_t word0; 1313 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1314 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1315 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1316 } request; 1317 struct { 1318 uint32_t word0; 1319 } response; 1320 } u; 1321 }; 1322 1323 struct mq_context { 1324 uint32_t word0; 1325 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1326 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1327 #define lpfc_mq_context_cq_id_WORD word0 1328 #define lpfc_mq_context_ring_size_SHIFT 16 1329 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1330 #define lpfc_mq_context_ring_size_WORD word0 1331 #define LPFC_MQ_RING_SIZE_16 0x5 1332 #define LPFC_MQ_RING_SIZE_32 0x6 1333 #define LPFC_MQ_RING_SIZE_64 0x7 1334 #define LPFC_MQ_RING_SIZE_128 0x8 1335 uint32_t word1; 1336 #define lpfc_mq_context_valid_SHIFT 31 1337 #define lpfc_mq_context_valid_MASK 0x00000001 1338 #define lpfc_mq_context_valid_WORD word1 1339 uint32_t reserved2; 1340 uint32_t reserved3; 1341 }; 1342 1343 struct lpfc_mbx_mq_create { 1344 struct mbox_header header; 1345 union { 1346 struct { 1347 uint32_t word0; 1348 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1349 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1350 #define lpfc_mbx_mq_create_num_pages_WORD word0 1351 struct mq_context context; 1352 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1353 } request; 1354 struct { 1355 uint32_t word0; 1356 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1357 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1358 #define lpfc_mbx_mq_create_q_id_WORD word0 1359 } response; 1360 } u; 1361 }; 1362 1363 struct lpfc_mbx_mq_create_ext { 1364 struct mbox_header header; 1365 union { 1366 struct { 1367 uint32_t word0; 1368 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1369 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1370 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1371 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1372 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1373 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1374 uint32_t async_evt_bmap; 1375 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1376 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1377 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1378 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1379 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1380 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1381 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1382 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1383 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1384 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1385 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1386 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1387 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1388 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1389 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1390 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1391 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1392 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1393 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1394 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1395 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1396 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1397 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1398 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1399 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1400 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1401 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1402 struct mq_context context; 1403 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1404 } request; 1405 struct { 1406 uint32_t word0; 1407 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1408 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1409 #define lpfc_mbx_mq_create_q_id_WORD word0 1410 } response; 1411 } u; 1412 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1413 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1414 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1415 }; 1416 1417 struct lpfc_mbx_mq_destroy { 1418 struct mbox_header header; 1419 union { 1420 struct { 1421 uint32_t word0; 1422 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1423 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1424 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1425 } request; 1426 struct { 1427 uint32_t word0; 1428 } response; 1429 } u; 1430 }; 1431 1432 /* Start Gen 2 SLI4 Mailbox definitions: */ 1433 1434 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1435 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1436 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1437 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1438 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1439 1440 struct lpfc_mbx_get_rsrc_extent_info { 1441 struct mbox_header header; 1442 union { 1443 struct { 1444 uint32_t word4; 1445 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1446 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1447 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1448 } req; 1449 struct { 1450 uint32_t word4; 1451 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1452 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1453 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1454 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1455 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1456 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1457 } rsp; 1458 } u; 1459 }; 1460 1461 struct lpfc_mbx_query_fw_config { 1462 struct mbox_header header; 1463 struct { 1464 uint32_t config_number; 1465 #define LPFC_FC_FCOE 0x00000007 1466 uint32_t asic_revision; 1467 uint32_t physical_port; 1468 uint32_t function_mode; 1469 #define LPFC_FCOE_INI_MODE 0x00000040 1470 #define LPFC_FCOE_TGT_MODE 0x00000080 1471 #define LPFC_DUA_MODE 0x00000800 1472 uint32_t ulp0_mode; 1473 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1474 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1475 uint32_t ulp0_nap_words[12]; 1476 uint32_t ulp1_mode; 1477 uint32_t ulp1_nap_words[12]; 1478 uint32_t function_capabilities; 1479 uint32_t cqid_base; 1480 uint32_t cqid_tot; 1481 uint32_t eqid_base; 1482 uint32_t eqid_tot; 1483 uint32_t ulp0_nap2_words[2]; 1484 uint32_t ulp1_nap2_words[2]; 1485 } rsp; 1486 }; 1487 1488 struct lpfc_mbx_set_beacon_config { 1489 struct mbox_header header; 1490 uint32_t word4; 1491 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1492 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1493 #define lpfc_mbx_set_beacon_port_num_WORD word4 1494 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1495 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1496 #define lpfc_mbx_set_beacon_port_type_WORD word4 1497 #define lpfc_mbx_set_beacon_state_SHIFT 8 1498 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1499 #define lpfc_mbx_set_beacon_state_WORD word4 1500 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1501 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1502 #define lpfc_mbx_set_beacon_duration_WORD word4 1503 #define lpfc_mbx_set_beacon_status_duration_SHIFT 24 1504 #define lpfc_mbx_set_beacon_status_duration_MASK 0x000000FF 1505 #define lpfc_mbx_set_beacon_status_duration_WORD word4 1506 }; 1507 1508 struct lpfc_id_range { 1509 uint32_t word5; 1510 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1511 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1512 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1513 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1514 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1515 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1516 }; 1517 1518 struct lpfc_mbx_set_link_diag_state { 1519 struct mbox_header header; 1520 union { 1521 struct { 1522 uint32_t word0; 1523 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1524 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1525 #define lpfc_mbx_set_diag_state_diag_WORD word0 1526 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1527 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1528 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1529 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1530 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1531 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1532 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1533 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1534 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1535 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1536 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1537 } req; 1538 struct { 1539 uint32_t word0; 1540 } rsp; 1541 } u; 1542 }; 1543 1544 struct lpfc_mbx_set_link_diag_loopback { 1545 struct mbox_header header; 1546 union { 1547 struct { 1548 uint32_t word0; 1549 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1550 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1551 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1552 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1553 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1554 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1555 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1556 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1557 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1558 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1559 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1560 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1561 } req; 1562 struct { 1563 uint32_t word0; 1564 } rsp; 1565 } u; 1566 }; 1567 1568 struct lpfc_mbx_run_link_diag_test { 1569 struct mbox_header header; 1570 union { 1571 struct { 1572 uint32_t word0; 1573 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1574 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1575 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1576 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1577 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1578 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1579 uint32_t word1; 1580 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1581 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1582 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1583 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1584 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1585 #define lpfc_mbx_run_diag_test_loops_WORD word1 1586 uint32_t word2; 1587 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1588 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1589 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1590 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1591 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1592 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1593 } req; 1594 struct { 1595 uint32_t word0; 1596 } rsp; 1597 } u; 1598 }; 1599 1600 /* 1601 * struct lpfc_mbx_alloc_rsrc_extents: 1602 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1603 * 6 words of header + 4 words of shared subcommand header + 1604 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1605 * 1606 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1607 * for extents payload. 1608 * 1609 * 212/2 (bytes per extent) = 106 extents. 1610 * 106/2 (extents per word) = 53 words. 1611 * lpfc_id_range id is statically size to 53. 1612 * 1613 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1614 * extent ranges. For ALLOC, the type and cnt are required. 1615 * For GET_ALLOCATED, only the type is required. 1616 */ 1617 struct lpfc_mbx_alloc_rsrc_extents { 1618 struct mbox_header header; 1619 union { 1620 struct { 1621 uint32_t word4; 1622 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1623 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1624 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1625 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1626 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1627 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1628 } req; 1629 struct { 1630 uint32_t word4; 1631 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1632 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1633 #define lpfc_mbx_rsrc_cnt_WORD word4 1634 struct lpfc_id_range id[53]; 1635 } rsp; 1636 } u; 1637 }; 1638 1639 /* 1640 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1641 * structure shares the same SHIFT/MASK/WORD defines provided in the 1642 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1643 * the structures defined above. This non-embedded structure provides for the 1644 * maximum number of extents supported by the port. 1645 */ 1646 struct lpfc_mbx_nembed_rsrc_extent { 1647 union lpfc_sli4_cfg_shdr cfg_shdr; 1648 uint32_t word4; 1649 struct lpfc_id_range id; 1650 }; 1651 1652 struct lpfc_mbx_dealloc_rsrc_extents { 1653 struct mbox_header header; 1654 struct { 1655 uint32_t word4; 1656 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1657 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1658 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1659 } req; 1660 1661 }; 1662 1663 /* Start SLI4 FCoE specific mbox structures. */ 1664 1665 struct lpfc_mbx_post_hdr_tmpl { 1666 struct mbox_header header; 1667 uint32_t word10; 1668 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1669 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1670 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1671 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1672 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1673 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1674 uint32_t rpi_paddr_lo; 1675 uint32_t rpi_paddr_hi; 1676 }; 1677 1678 struct sli4_sge { /* SLI-4 */ 1679 uint32_t addr_hi; 1680 uint32_t addr_lo; 1681 1682 uint32_t word2; 1683 #define lpfc_sli4_sge_offset_SHIFT 0 1684 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1685 #define lpfc_sli4_sge_offset_WORD word2 1686 #define lpfc_sli4_sge_type_SHIFT 27 1687 #define lpfc_sli4_sge_type_MASK 0x0000000F 1688 #define lpfc_sli4_sge_type_WORD word2 1689 #define LPFC_SGE_TYPE_DATA 0x0 1690 #define LPFC_SGE_TYPE_DIF 0x4 1691 #define LPFC_SGE_TYPE_LSP 0x5 1692 #define LPFC_SGE_TYPE_PEDIF 0x6 1693 #define LPFC_SGE_TYPE_PESEED 0x7 1694 #define LPFC_SGE_TYPE_DISEED 0x8 1695 #define LPFC_SGE_TYPE_ENC 0x9 1696 #define LPFC_SGE_TYPE_ATM 0xA 1697 #define LPFC_SGE_TYPE_SKIP 0xC 1698 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1699 #define lpfc_sli4_sge_last_MASK 0x00000001 1700 #define lpfc_sli4_sge_last_WORD word2 1701 uint32_t sge_len; 1702 }; 1703 1704 struct sli4_sge_diseed { /* SLI-4 */ 1705 uint32_t ref_tag; 1706 uint32_t ref_tag_tran; 1707 1708 uint32_t word2; 1709 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1710 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1711 #define lpfc_sli4_sge_dif_apptran_WORD word2 1712 #define lpfc_sli4_sge_dif_af_SHIFT 24 1713 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1714 #define lpfc_sli4_sge_dif_af_WORD word2 1715 #define lpfc_sli4_sge_dif_na_SHIFT 25 1716 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1717 #define lpfc_sli4_sge_dif_na_WORD word2 1718 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1719 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1720 #define lpfc_sli4_sge_dif_hi_WORD word2 1721 #define lpfc_sli4_sge_dif_type_SHIFT 27 1722 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1723 #define lpfc_sli4_sge_dif_type_WORD word2 1724 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1725 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1726 #define lpfc_sli4_sge_dif_last_WORD word2 1727 uint32_t word3; 1728 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1729 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1730 #define lpfc_sli4_sge_dif_apptag_WORD word3 1731 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1732 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1733 #define lpfc_sli4_sge_dif_bs_WORD word3 1734 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1735 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1736 #define lpfc_sli4_sge_dif_ai_WORD word3 1737 #define lpfc_sli4_sge_dif_me_SHIFT 20 1738 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1739 #define lpfc_sli4_sge_dif_me_WORD word3 1740 #define lpfc_sli4_sge_dif_re_SHIFT 21 1741 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1742 #define lpfc_sli4_sge_dif_re_WORD word3 1743 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1744 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1745 #define lpfc_sli4_sge_dif_ce_WORD word3 1746 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1747 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1748 #define lpfc_sli4_sge_dif_nr_WORD word3 1749 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1750 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1751 #define lpfc_sli4_sge_dif_oprx_WORD word3 1752 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1753 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1754 #define lpfc_sli4_sge_dif_optx_WORD word3 1755 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1756 }; 1757 1758 struct fcf_record { 1759 uint32_t max_rcv_size; 1760 uint32_t fka_adv_period; 1761 uint32_t fip_priority; 1762 uint32_t word3; 1763 #define lpfc_fcf_record_mac_0_SHIFT 0 1764 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1765 #define lpfc_fcf_record_mac_0_WORD word3 1766 #define lpfc_fcf_record_mac_1_SHIFT 8 1767 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1768 #define lpfc_fcf_record_mac_1_WORD word3 1769 #define lpfc_fcf_record_mac_2_SHIFT 16 1770 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1771 #define lpfc_fcf_record_mac_2_WORD word3 1772 #define lpfc_fcf_record_mac_3_SHIFT 24 1773 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1774 #define lpfc_fcf_record_mac_3_WORD word3 1775 uint32_t word4; 1776 #define lpfc_fcf_record_mac_4_SHIFT 0 1777 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1778 #define lpfc_fcf_record_mac_4_WORD word4 1779 #define lpfc_fcf_record_mac_5_SHIFT 8 1780 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1781 #define lpfc_fcf_record_mac_5_WORD word4 1782 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1783 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1784 #define lpfc_fcf_record_fcf_avail_WORD word4 1785 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1786 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1787 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1788 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1789 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1790 uint32_t word5; 1791 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1792 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1793 #define lpfc_fcf_record_fab_name_0_WORD word5 1794 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1795 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1796 #define lpfc_fcf_record_fab_name_1_WORD word5 1797 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1798 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1799 #define lpfc_fcf_record_fab_name_2_WORD word5 1800 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1801 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1802 #define lpfc_fcf_record_fab_name_3_WORD word5 1803 uint32_t word6; 1804 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1805 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1806 #define lpfc_fcf_record_fab_name_4_WORD word6 1807 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1808 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1809 #define lpfc_fcf_record_fab_name_5_WORD word6 1810 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1811 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1812 #define lpfc_fcf_record_fab_name_6_WORD word6 1813 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1814 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1815 #define lpfc_fcf_record_fab_name_7_WORD word6 1816 uint32_t word7; 1817 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1818 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1819 #define lpfc_fcf_record_fc_map_0_WORD word7 1820 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1821 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1822 #define lpfc_fcf_record_fc_map_1_WORD word7 1823 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1824 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1825 #define lpfc_fcf_record_fc_map_2_WORD word7 1826 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1827 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 1828 #define lpfc_fcf_record_fcf_valid_WORD word7 1829 #define lpfc_fcf_record_fcf_fc_SHIFT 25 1830 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 1831 #define lpfc_fcf_record_fcf_fc_WORD word7 1832 #define lpfc_fcf_record_fcf_sol_SHIFT 31 1833 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 1834 #define lpfc_fcf_record_fcf_sol_WORD word7 1835 uint32_t word8; 1836 #define lpfc_fcf_record_fcf_index_SHIFT 0 1837 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1838 #define lpfc_fcf_record_fcf_index_WORD word8 1839 #define lpfc_fcf_record_fcf_state_SHIFT 16 1840 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1841 #define lpfc_fcf_record_fcf_state_WORD word8 1842 uint8_t vlan_bitmap[512]; 1843 uint32_t word137; 1844 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1845 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1846 #define lpfc_fcf_record_switch_name_0_WORD word137 1847 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1848 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1849 #define lpfc_fcf_record_switch_name_1_WORD word137 1850 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1851 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1852 #define lpfc_fcf_record_switch_name_2_WORD word137 1853 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1854 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1855 #define lpfc_fcf_record_switch_name_3_WORD word137 1856 uint32_t word138; 1857 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1858 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1859 #define lpfc_fcf_record_switch_name_4_WORD word138 1860 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1861 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1862 #define lpfc_fcf_record_switch_name_5_WORD word138 1863 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1864 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1865 #define lpfc_fcf_record_switch_name_6_WORD word138 1866 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1867 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1868 #define lpfc_fcf_record_switch_name_7_WORD word138 1869 }; 1870 1871 struct lpfc_mbx_read_fcf_tbl { 1872 union lpfc_sli4_cfg_shdr cfg_shdr; 1873 union { 1874 struct { 1875 uint32_t word10; 1876 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1877 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1878 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1879 } request; 1880 struct { 1881 uint32_t eventag; 1882 } response; 1883 } u; 1884 uint32_t word11; 1885 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1886 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1887 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1888 }; 1889 1890 struct lpfc_mbx_add_fcf_tbl_entry { 1891 union lpfc_sli4_cfg_shdr cfg_shdr; 1892 uint32_t word10; 1893 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1894 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1895 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1896 struct lpfc_mbx_sge fcf_sge; 1897 }; 1898 1899 struct lpfc_mbx_del_fcf_tbl_entry { 1900 struct mbox_header header; 1901 uint32_t word10; 1902 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1903 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1904 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1905 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1906 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1907 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1908 }; 1909 1910 struct lpfc_mbx_redisc_fcf_tbl { 1911 struct mbox_header header; 1912 uint32_t word10; 1913 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1914 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1915 #define lpfc_mbx_redisc_fcf_count_WORD word10 1916 uint32_t resvd; 1917 uint32_t word12; 1918 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1919 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1920 #define lpfc_mbx_redisc_fcf_index_WORD word12 1921 }; 1922 1923 /* Status field for embedded SLI_CONFIG mailbox command */ 1924 #define STATUS_SUCCESS 0x0 1925 #define STATUS_FAILED 0x1 1926 #define STATUS_ILLEGAL_REQUEST 0x2 1927 #define STATUS_ILLEGAL_FIELD 0x3 1928 #define STATUS_INSUFFICIENT_BUFFER 0x4 1929 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1930 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1931 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1932 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1933 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1934 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1935 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1936 #define STATUS_ASSERT_FAILED 0x1e 1937 #define STATUS_INVALID_SESSION 0x1f 1938 #define STATUS_INVALID_CONNECTION 0x20 1939 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1940 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1941 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1942 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1943 #define STATUS_FLASHROM_READ_FAILED 0x27 1944 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1945 #define STATUS_ERROR_ACITMAIN 0x2a 1946 #define STATUS_REBOOT_REQUIRED 0x2c 1947 #define STATUS_FCF_IN_USE 0x3a 1948 #define STATUS_FCF_TABLE_EMPTY 0x43 1949 1950 /* 1951 * Additional status field for embedded SLI_CONFIG mailbox 1952 * command. 1953 */ 1954 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 1955 1956 struct lpfc_mbx_sli4_config { 1957 struct mbox_header header; 1958 }; 1959 1960 struct lpfc_mbx_init_vfi { 1961 uint32_t word1; 1962 #define lpfc_init_vfi_vr_SHIFT 31 1963 #define lpfc_init_vfi_vr_MASK 0x00000001 1964 #define lpfc_init_vfi_vr_WORD word1 1965 #define lpfc_init_vfi_vt_SHIFT 30 1966 #define lpfc_init_vfi_vt_MASK 0x00000001 1967 #define lpfc_init_vfi_vt_WORD word1 1968 #define lpfc_init_vfi_vf_SHIFT 29 1969 #define lpfc_init_vfi_vf_MASK 0x00000001 1970 #define lpfc_init_vfi_vf_WORD word1 1971 #define lpfc_init_vfi_vp_SHIFT 28 1972 #define lpfc_init_vfi_vp_MASK 0x00000001 1973 #define lpfc_init_vfi_vp_WORD word1 1974 #define lpfc_init_vfi_vfi_SHIFT 0 1975 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1976 #define lpfc_init_vfi_vfi_WORD word1 1977 uint32_t word2; 1978 #define lpfc_init_vfi_vpi_SHIFT 16 1979 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1980 #define lpfc_init_vfi_vpi_WORD word2 1981 #define lpfc_init_vfi_fcfi_SHIFT 0 1982 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1983 #define lpfc_init_vfi_fcfi_WORD word2 1984 uint32_t word3; 1985 #define lpfc_init_vfi_pri_SHIFT 13 1986 #define lpfc_init_vfi_pri_MASK 0x00000007 1987 #define lpfc_init_vfi_pri_WORD word3 1988 #define lpfc_init_vfi_vf_id_SHIFT 1 1989 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1990 #define lpfc_init_vfi_vf_id_WORD word3 1991 uint32_t word4; 1992 #define lpfc_init_vfi_hop_count_SHIFT 24 1993 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1994 #define lpfc_init_vfi_hop_count_WORD word4 1995 }; 1996 #define MBX_VFI_IN_USE 0x9F02 1997 1998 1999 struct lpfc_mbx_reg_vfi { 2000 uint32_t word1; 2001 #define lpfc_reg_vfi_upd_SHIFT 29 2002 #define lpfc_reg_vfi_upd_MASK 0x00000001 2003 #define lpfc_reg_vfi_upd_WORD word1 2004 #define lpfc_reg_vfi_vp_SHIFT 28 2005 #define lpfc_reg_vfi_vp_MASK 0x00000001 2006 #define lpfc_reg_vfi_vp_WORD word1 2007 #define lpfc_reg_vfi_vfi_SHIFT 0 2008 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2009 #define lpfc_reg_vfi_vfi_WORD word1 2010 uint32_t word2; 2011 #define lpfc_reg_vfi_vpi_SHIFT 16 2012 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2013 #define lpfc_reg_vfi_vpi_WORD word2 2014 #define lpfc_reg_vfi_fcfi_SHIFT 0 2015 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2016 #define lpfc_reg_vfi_fcfi_WORD word2 2017 uint32_t wwn[2]; 2018 struct ulp_bde64 bde; 2019 uint32_t e_d_tov; 2020 uint32_t r_a_tov; 2021 uint32_t word10; 2022 #define lpfc_reg_vfi_nport_id_SHIFT 0 2023 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2024 #define lpfc_reg_vfi_nport_id_WORD word10 2025 }; 2026 2027 struct lpfc_mbx_init_vpi { 2028 uint32_t word1; 2029 #define lpfc_init_vpi_vfi_SHIFT 16 2030 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2031 #define lpfc_init_vpi_vfi_WORD word1 2032 #define lpfc_init_vpi_vpi_SHIFT 0 2033 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2034 #define lpfc_init_vpi_vpi_WORD word1 2035 }; 2036 2037 struct lpfc_mbx_read_vpi { 2038 uint32_t word1_rsvd; 2039 uint32_t word2; 2040 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2041 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2042 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2043 uint32_t word3_rsvd; 2044 uint32_t word4; 2045 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2046 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2047 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2048 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2049 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2050 #define lpfc_mbx_read_vpi_pb_WORD word4 2051 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2052 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2053 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2054 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2055 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2056 #define lpfc_mbx_read_vpi_ns_WORD word4 2057 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2058 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2059 #define lpfc_mbx_read_vpi_hl_WORD word4 2060 uint32_t word5_rsvd; 2061 uint32_t word6; 2062 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2063 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2064 #define lpfc_mbx_read_vpi_vpi_WORD word6 2065 uint32_t word7; 2066 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2067 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2068 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2069 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2070 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2071 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2072 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2073 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2074 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2075 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2076 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2077 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2078 uint32_t word8; 2079 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2080 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2081 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2082 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2083 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2084 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2085 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2086 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2087 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2088 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2089 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2090 #define lpfc_mbx_read_vpi_vv_WORD word8 2091 }; 2092 2093 struct lpfc_mbx_unreg_vfi { 2094 uint32_t word1_rsvd; 2095 uint32_t word2; 2096 #define lpfc_unreg_vfi_vfi_SHIFT 0 2097 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2098 #define lpfc_unreg_vfi_vfi_WORD word2 2099 }; 2100 2101 struct lpfc_mbx_resume_rpi { 2102 uint32_t word1; 2103 #define lpfc_resume_rpi_index_SHIFT 0 2104 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2105 #define lpfc_resume_rpi_index_WORD word1 2106 #define lpfc_resume_rpi_ii_SHIFT 30 2107 #define lpfc_resume_rpi_ii_MASK 0x00000003 2108 #define lpfc_resume_rpi_ii_WORD word1 2109 #define RESUME_INDEX_RPI 0 2110 #define RESUME_INDEX_VPI 1 2111 #define RESUME_INDEX_VFI 2 2112 #define RESUME_INDEX_FCFI 3 2113 uint32_t event_tag; 2114 }; 2115 2116 #define REG_FCF_INVALID_QID 0xFFFF 2117 struct lpfc_mbx_reg_fcfi { 2118 uint32_t word1; 2119 #define lpfc_reg_fcfi_info_index_SHIFT 0 2120 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2121 #define lpfc_reg_fcfi_info_index_WORD word1 2122 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2123 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2124 #define lpfc_reg_fcfi_fcfi_WORD word1 2125 uint32_t word2; 2126 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2127 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2128 #define lpfc_reg_fcfi_rq_id1_WORD word2 2129 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2130 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2131 #define lpfc_reg_fcfi_rq_id0_WORD word2 2132 uint32_t word3; 2133 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2134 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2135 #define lpfc_reg_fcfi_rq_id3_WORD word3 2136 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2137 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2138 #define lpfc_reg_fcfi_rq_id2_WORD word3 2139 uint32_t word4; 2140 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2141 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2142 #define lpfc_reg_fcfi_type_match0_WORD word4 2143 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2144 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2145 #define lpfc_reg_fcfi_type_mask0_WORD word4 2146 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2147 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2148 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2149 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2150 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2151 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2152 uint32_t word5; 2153 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2154 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2155 #define lpfc_reg_fcfi_type_match1_WORD word5 2156 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2157 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2158 #define lpfc_reg_fcfi_type_mask1_WORD word5 2159 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2160 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2161 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2162 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2163 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2164 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2165 uint32_t word6; 2166 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2167 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2168 #define lpfc_reg_fcfi_type_match2_WORD word6 2169 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2170 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2171 #define lpfc_reg_fcfi_type_mask2_WORD word6 2172 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2173 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2174 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2175 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2176 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2177 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2178 uint32_t word7; 2179 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2180 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2181 #define lpfc_reg_fcfi_type_match3_WORD word7 2182 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2183 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2184 #define lpfc_reg_fcfi_type_mask3_WORD word7 2185 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2186 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2187 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2188 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2189 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2190 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2191 uint32_t word8; 2192 #define lpfc_reg_fcfi_mam_SHIFT 13 2193 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2194 #define lpfc_reg_fcfi_mam_WORD word8 2195 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2196 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2197 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2198 #define lpfc_reg_fcfi_vv_SHIFT 12 2199 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2200 #define lpfc_reg_fcfi_vv_WORD word8 2201 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2202 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2203 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2204 }; 2205 2206 struct lpfc_mbx_unreg_fcfi { 2207 uint32_t word1_rsv; 2208 uint32_t word2; 2209 #define lpfc_unreg_fcfi_SHIFT 0 2210 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2211 #define lpfc_unreg_fcfi_WORD word2 2212 }; 2213 2214 struct lpfc_mbx_read_rev { 2215 uint32_t word1; 2216 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2217 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2218 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2219 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2220 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2221 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2222 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2223 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2224 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2225 #define LPFC_PREDCBX_CEE_MODE 0 2226 #define LPFC_DCBX_CEE_MODE 1 2227 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2228 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2229 #define lpfc_mbx_rd_rev_vpd_WORD word1 2230 uint32_t first_hw_rev; 2231 uint32_t second_hw_rev; 2232 uint32_t word4_rsvd; 2233 uint32_t third_hw_rev; 2234 uint32_t word6; 2235 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2236 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2237 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2238 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2239 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2240 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2241 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2242 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2243 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2244 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2245 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2246 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2247 uint32_t word7_rsvd; 2248 uint32_t fw_id_rev; 2249 uint8_t fw_name[16]; 2250 uint32_t ulp_fw_id_rev; 2251 uint8_t ulp_fw_name[16]; 2252 uint32_t word18_47_rsvd[30]; 2253 uint32_t word48; 2254 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2255 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2256 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2257 uint32_t vpd_paddr_low; 2258 uint32_t vpd_paddr_high; 2259 uint32_t avail_vpd_len; 2260 uint32_t rsvd_52_63[12]; 2261 }; 2262 2263 struct lpfc_mbx_read_config { 2264 uint32_t word1; 2265 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2266 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2267 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2268 uint32_t word2; 2269 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2270 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2271 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2272 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2273 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2274 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2275 #define LPFC_LNK_TYPE_GE 0 2276 #define LPFC_LNK_TYPE_FC 1 2277 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2278 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2279 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2280 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2281 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2282 #define lpfc_mbx_rd_conf_topology_WORD word2 2283 uint32_t rsvd_3; 2284 uint32_t word4; 2285 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2286 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2287 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2288 uint32_t rsvd_5; 2289 uint32_t word6; 2290 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2291 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2292 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2293 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2294 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2295 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2296 uint32_t rsvd_7; 2297 uint32_t rsvd_8; 2298 uint32_t word9; 2299 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2300 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2301 #define lpfc_mbx_rd_conf_lmt_WORD word9 2302 uint32_t rsvd_10; 2303 uint32_t rsvd_11; 2304 uint32_t word12; 2305 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2306 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2307 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2308 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2309 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2310 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2311 uint32_t word13; 2312 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2313 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2314 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2315 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2316 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2317 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2318 uint32_t word14; 2319 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2320 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2321 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2322 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2323 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2324 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2325 uint32_t word15; 2326 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2327 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2328 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2329 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2330 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2331 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2332 uint32_t word16; 2333 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2334 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2335 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2336 uint32_t word17; 2337 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2338 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2339 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2340 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2341 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2342 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2343 uint32_t word18; 2344 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2345 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2346 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2347 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2348 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2349 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2350 }; 2351 2352 struct lpfc_mbx_request_features { 2353 uint32_t word1; 2354 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2355 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2356 #define lpfc_mbx_rq_ftr_qry_WORD word1 2357 uint32_t word2; 2358 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2359 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2360 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2361 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2362 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2363 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2364 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2365 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2366 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2367 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2368 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2369 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2370 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2371 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2372 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2373 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2374 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2375 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2376 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2377 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2378 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2379 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2380 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2381 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2382 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2383 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2384 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2385 uint32_t word3; 2386 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2387 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2388 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2389 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2390 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2391 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2392 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2393 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2394 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2395 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2396 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2397 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2398 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2399 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2400 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2401 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2402 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2403 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2404 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2405 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2406 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2407 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2408 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2409 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2410 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2411 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2412 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2413 }; 2414 2415 struct lpfc_mbx_supp_pages { 2416 uint32_t word1; 2417 #define qs_SHIFT 0 2418 #define qs_MASK 0x00000001 2419 #define qs_WORD word1 2420 #define wr_SHIFT 1 2421 #define wr_MASK 0x00000001 2422 #define wr_WORD word1 2423 #define pf_SHIFT 8 2424 #define pf_MASK 0x000000ff 2425 #define pf_WORD word1 2426 #define cpn_SHIFT 16 2427 #define cpn_MASK 0x000000ff 2428 #define cpn_WORD word1 2429 uint32_t word2; 2430 #define list_offset_SHIFT 0 2431 #define list_offset_MASK 0x000000ff 2432 #define list_offset_WORD word2 2433 #define next_offset_SHIFT 8 2434 #define next_offset_MASK 0x000000ff 2435 #define next_offset_WORD word2 2436 #define elem_cnt_SHIFT 16 2437 #define elem_cnt_MASK 0x000000ff 2438 #define elem_cnt_WORD word2 2439 uint32_t word3; 2440 #define pn_0_SHIFT 24 2441 #define pn_0_MASK 0x000000ff 2442 #define pn_0_WORD word3 2443 #define pn_1_SHIFT 16 2444 #define pn_1_MASK 0x000000ff 2445 #define pn_1_WORD word3 2446 #define pn_2_SHIFT 8 2447 #define pn_2_MASK 0x000000ff 2448 #define pn_2_WORD word3 2449 #define pn_3_SHIFT 0 2450 #define pn_3_MASK 0x000000ff 2451 #define pn_3_WORD word3 2452 uint32_t word4; 2453 #define pn_4_SHIFT 24 2454 #define pn_4_MASK 0x000000ff 2455 #define pn_4_WORD word4 2456 #define pn_5_SHIFT 16 2457 #define pn_5_MASK 0x000000ff 2458 #define pn_5_WORD word4 2459 #define pn_6_SHIFT 8 2460 #define pn_6_MASK 0x000000ff 2461 #define pn_6_WORD word4 2462 #define pn_7_SHIFT 0 2463 #define pn_7_MASK 0x000000ff 2464 #define pn_7_WORD word4 2465 uint32_t rsvd[27]; 2466 #define LPFC_SUPP_PAGES 0 2467 #define LPFC_BLOCK_GUARD_PROFILES 1 2468 #define LPFC_SLI4_PARAMETERS 2 2469 }; 2470 2471 struct lpfc_mbx_memory_dump_type3 { 2472 uint32_t word1; 2473 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2474 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2475 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2476 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2477 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2478 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2479 uint32_t word2; 2480 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2481 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 2482 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 2483 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 2484 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 2485 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 2486 uint32_t word3; 2487 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 2488 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 2489 #define lpfc_mbx_memory_dump_type3_length_WORD word3 2490 uint32_t addr_lo; 2491 uint32_t addr_hi; 2492 uint32_t return_len; 2493 }; 2494 2495 #define DMP_PAGE_A0 0xa0 2496 #define DMP_PAGE_A2 0xa2 2497 #define DMP_SFF_PAGE_A0_SIZE 256 2498 #define DMP_SFF_PAGE_A2_SIZE 256 2499 2500 #define SFP_WAVELENGTH_LC1310 1310 2501 #define SFP_WAVELENGTH_LL1550 1550 2502 2503 2504 /* 2505 * * SFF-8472 TABLE 3.4 2506 * */ 2507 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 2508 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 2509 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 2510 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 2511 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 2512 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 2513 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 2514 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 2515 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 2516 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 2517 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 2518 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 2519 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 2520 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 2521 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 2522 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 2523 2524 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 2525 2526 #define SSF_IDENTIFIER 0 2527 #define SSF_EXT_IDENTIFIER 1 2528 #define SSF_CONNECTOR 2 2529 #define SSF_TRANSCEIVER_CODE_B0 3 2530 #define SSF_TRANSCEIVER_CODE_B1 4 2531 #define SSF_TRANSCEIVER_CODE_B2 5 2532 #define SSF_TRANSCEIVER_CODE_B3 6 2533 #define SSF_TRANSCEIVER_CODE_B4 7 2534 #define SSF_TRANSCEIVER_CODE_B5 8 2535 #define SSF_TRANSCEIVER_CODE_B6 9 2536 #define SSF_TRANSCEIVER_CODE_B7 10 2537 #define SSF_ENCODING 11 2538 #define SSF_BR_NOMINAL 12 2539 #define SSF_RATE_IDENTIFIER 13 2540 #define SSF_LENGTH_9UM_KM 14 2541 #define SSF_LENGTH_9UM 15 2542 #define SSF_LENGTH_50UM_OM2 16 2543 #define SSF_LENGTH_62UM_OM1 17 2544 #define SFF_LENGTH_COPPER 18 2545 #define SSF_LENGTH_50UM_OM3 19 2546 #define SSF_VENDOR_NAME 20 2547 #define SSF_VENDOR_OUI 36 2548 #define SSF_VENDOR_PN 40 2549 #define SSF_VENDOR_REV 56 2550 #define SSF_WAVELENGTH_B1 60 2551 #define SSF_WAVELENGTH_B0 61 2552 #define SSF_CC_BASE 63 2553 #define SSF_OPTIONS_B1 64 2554 #define SSF_OPTIONS_B0 65 2555 #define SSF_BR_MAX 66 2556 #define SSF_BR_MIN 67 2557 #define SSF_VENDOR_SN 68 2558 #define SSF_DATE_CODE 84 2559 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 2560 #define SSF_ENHANCED_OPTIONS 93 2561 #define SFF_8472_COMPLIANCE 94 2562 #define SSF_CC_EXT 95 2563 #define SSF_A0_VENDOR_SPECIFIC 96 2564 2565 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 2566 2567 #define SSF_TEMP_HIGH_ALARM 0 2568 #define SSF_TEMP_LOW_ALARM 2 2569 #define SSF_TEMP_HIGH_WARNING 4 2570 #define SSF_TEMP_LOW_WARNING 6 2571 #define SSF_VOLTAGE_HIGH_ALARM 8 2572 #define SSF_VOLTAGE_LOW_ALARM 10 2573 #define SSF_VOLTAGE_HIGH_WARNING 12 2574 #define SSF_VOLTAGE_LOW_WARNING 14 2575 #define SSF_BIAS_HIGH_ALARM 16 2576 #define SSF_BIAS_LOW_ALARM 18 2577 #define SSF_BIAS_HIGH_WARNING 20 2578 #define SSF_BIAS_LOW_WARNING 22 2579 #define SSF_TXPOWER_HIGH_ALARM 24 2580 #define SSF_TXPOWER_LOW_ALARM 26 2581 #define SSF_TXPOWER_HIGH_WARNING 28 2582 #define SSF_TXPOWER_LOW_WARNING 30 2583 #define SSF_RXPOWER_HIGH_ALARM 32 2584 #define SSF_RXPOWER_LOW_ALARM 34 2585 #define SSF_RXPOWER_HIGH_WARNING 36 2586 #define SSF_RXPOWER_LOW_WARNING 38 2587 #define SSF_EXT_CAL_CONSTANTS 56 2588 #define SSF_CC_DMI 95 2589 #define SFF_TEMPERATURE_B1 96 2590 #define SFF_TEMPERATURE_B0 97 2591 #define SFF_VCC_B1 98 2592 #define SFF_VCC_B0 99 2593 #define SFF_TX_BIAS_CURRENT_B1 100 2594 #define SFF_TX_BIAS_CURRENT_B0 101 2595 #define SFF_TXPOWER_B1 102 2596 #define SFF_TXPOWER_B0 103 2597 #define SFF_RXPOWER_B1 104 2598 #define SFF_RXPOWER_B0 105 2599 #define SSF_STATUS_CONTROL 110 2600 #define SSF_ALARM_FLAGS 112 2601 #define SSF_WARNING_FLAGS 116 2602 #define SSF_EXT_TATUS_CONTROL_B1 118 2603 #define SSF_EXT_TATUS_CONTROL_B0 119 2604 #define SSF_A2_VENDOR_SPECIFIC 120 2605 #define SSF_USER_EEPROM 128 2606 #define SSF_VENDOR_CONTROL 148 2607 2608 2609 /* 2610 * Tranceiver codes Fibre Channel SFF-8472 2611 * Table 3.5. 2612 */ 2613 2614 struct sff_trasnceiver_codes_byte0 { 2615 uint8_t inifiband:4; 2616 uint8_t teng_ethernet:4; 2617 }; 2618 2619 struct sff_trasnceiver_codes_byte1 { 2620 uint8_t sonet:6; 2621 uint8_t escon:2; 2622 }; 2623 2624 struct sff_trasnceiver_codes_byte2 { 2625 uint8_t soNet:8; 2626 }; 2627 2628 struct sff_trasnceiver_codes_byte3 { 2629 uint8_t ethernet:8; 2630 }; 2631 2632 struct sff_trasnceiver_codes_byte4 { 2633 uint8_t fc_el_lo:1; 2634 uint8_t fc_lw_laser:1; 2635 uint8_t fc_sw_laser:1; 2636 uint8_t fc_md_distance:1; 2637 uint8_t fc_lg_distance:1; 2638 uint8_t fc_int_distance:1; 2639 uint8_t fc_short_distance:1; 2640 uint8_t fc_vld_distance:1; 2641 }; 2642 2643 struct sff_trasnceiver_codes_byte5 { 2644 uint8_t reserved1:1; 2645 uint8_t reserved2:1; 2646 uint8_t fc_sfp_active:1; /* Active cable */ 2647 uint8_t fc_sfp_passive:1; /* Passive cable */ 2648 uint8_t fc_lw_laser:1; /* Longwave laser */ 2649 uint8_t fc_sw_laser_sl:1; 2650 uint8_t fc_sw_laser_sn:1; 2651 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 2652 }; 2653 2654 struct sff_trasnceiver_codes_byte6 { 2655 uint8_t fc_tm_sm:1; /* Single Mode */ 2656 uint8_t reserved:1; 2657 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 2658 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 2659 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 2660 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 2661 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 2662 }; 2663 2664 struct sff_trasnceiver_codes_byte7 { 2665 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 2666 uint8_t reserve:1; 2667 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 2668 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 2669 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 2670 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 2671 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 2672 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 2673 }; 2674 2675 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 2676 struct user_eeprom { 2677 uint8_t vendor_name[16]; 2678 uint8_t vendor_oui[3]; 2679 uint8_t vendor_pn[816]; 2680 uint8_t vendor_rev[4]; 2681 uint8_t vendor_sn[16]; 2682 uint8_t datecode[6]; 2683 uint8_t lot_code[2]; 2684 uint8_t reserved191[57]; 2685 }; 2686 2687 struct lpfc_mbx_pc_sli4_params { 2688 uint32_t word1; 2689 #define qs_SHIFT 0 2690 #define qs_MASK 0x00000001 2691 #define qs_WORD word1 2692 #define wr_SHIFT 1 2693 #define wr_MASK 0x00000001 2694 #define wr_WORD word1 2695 #define pf_SHIFT 8 2696 #define pf_MASK 0x000000ff 2697 #define pf_WORD word1 2698 #define cpn_SHIFT 16 2699 #define cpn_MASK 0x000000ff 2700 #define cpn_WORD word1 2701 uint32_t word2; 2702 #define if_type_SHIFT 0 2703 #define if_type_MASK 0x00000007 2704 #define if_type_WORD word2 2705 #define sli_rev_SHIFT 4 2706 #define sli_rev_MASK 0x0000000f 2707 #define sli_rev_WORD word2 2708 #define sli_family_SHIFT 8 2709 #define sli_family_MASK 0x000000ff 2710 #define sli_family_WORD word2 2711 #define featurelevel_1_SHIFT 16 2712 #define featurelevel_1_MASK 0x000000ff 2713 #define featurelevel_1_WORD word2 2714 #define featurelevel_2_SHIFT 24 2715 #define featurelevel_2_MASK 0x0000001f 2716 #define featurelevel_2_WORD word2 2717 uint32_t word3; 2718 #define fcoe_SHIFT 0 2719 #define fcoe_MASK 0x00000001 2720 #define fcoe_WORD word3 2721 #define fc_SHIFT 1 2722 #define fc_MASK 0x00000001 2723 #define fc_WORD word3 2724 #define nic_SHIFT 2 2725 #define nic_MASK 0x00000001 2726 #define nic_WORD word3 2727 #define iscsi_SHIFT 3 2728 #define iscsi_MASK 0x00000001 2729 #define iscsi_WORD word3 2730 #define rdma_SHIFT 4 2731 #define rdma_MASK 0x00000001 2732 #define rdma_WORD word3 2733 uint32_t sge_supp_len; 2734 #define SLI4_PAGE_SIZE 4096 2735 uint32_t word5; 2736 #define if_page_sz_SHIFT 0 2737 #define if_page_sz_MASK 0x0000ffff 2738 #define if_page_sz_WORD word5 2739 #define loopbk_scope_SHIFT 24 2740 #define loopbk_scope_MASK 0x0000000f 2741 #define loopbk_scope_WORD word5 2742 #define rq_db_window_SHIFT 28 2743 #define rq_db_window_MASK 0x0000000f 2744 #define rq_db_window_WORD word5 2745 uint32_t word6; 2746 #define eq_pages_SHIFT 0 2747 #define eq_pages_MASK 0x0000000f 2748 #define eq_pages_WORD word6 2749 #define eqe_size_SHIFT 8 2750 #define eqe_size_MASK 0x000000ff 2751 #define eqe_size_WORD word6 2752 uint32_t word7; 2753 #define cq_pages_SHIFT 0 2754 #define cq_pages_MASK 0x0000000f 2755 #define cq_pages_WORD word7 2756 #define cqe_size_SHIFT 8 2757 #define cqe_size_MASK 0x000000ff 2758 #define cqe_size_WORD word7 2759 uint32_t word8; 2760 #define mq_pages_SHIFT 0 2761 #define mq_pages_MASK 0x0000000f 2762 #define mq_pages_WORD word8 2763 #define mqe_size_SHIFT 8 2764 #define mqe_size_MASK 0x000000ff 2765 #define mqe_size_WORD word8 2766 #define mq_elem_cnt_SHIFT 16 2767 #define mq_elem_cnt_MASK 0x000000ff 2768 #define mq_elem_cnt_WORD word8 2769 uint32_t word9; 2770 #define wq_pages_SHIFT 0 2771 #define wq_pages_MASK 0x0000ffff 2772 #define wq_pages_WORD word9 2773 #define wqe_size_SHIFT 8 2774 #define wqe_size_MASK 0x000000ff 2775 #define wqe_size_WORD word9 2776 uint32_t word10; 2777 #define rq_pages_SHIFT 0 2778 #define rq_pages_MASK 0x0000ffff 2779 #define rq_pages_WORD word10 2780 #define rqe_size_SHIFT 8 2781 #define rqe_size_MASK 0x000000ff 2782 #define rqe_size_WORD word10 2783 uint32_t word11; 2784 #define hdr_pages_SHIFT 0 2785 #define hdr_pages_MASK 0x0000000f 2786 #define hdr_pages_WORD word11 2787 #define hdr_size_SHIFT 8 2788 #define hdr_size_MASK 0x0000000f 2789 #define hdr_size_WORD word11 2790 #define hdr_pp_align_SHIFT 16 2791 #define hdr_pp_align_MASK 0x0000ffff 2792 #define hdr_pp_align_WORD word11 2793 uint32_t word12; 2794 #define sgl_pages_SHIFT 0 2795 #define sgl_pages_MASK 0x0000000f 2796 #define sgl_pages_WORD word12 2797 #define sgl_pp_align_SHIFT 16 2798 #define sgl_pp_align_MASK 0x0000ffff 2799 #define sgl_pp_align_WORD word12 2800 uint32_t rsvd_13_63[51]; 2801 }; 2802 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2803 &(~((SLI4_PAGE_SIZE)-1))) 2804 2805 struct lpfc_sli4_parameters { 2806 uint32_t word0; 2807 #define cfg_prot_type_SHIFT 0 2808 #define cfg_prot_type_MASK 0x000000FF 2809 #define cfg_prot_type_WORD word0 2810 uint32_t word1; 2811 #define cfg_ft_SHIFT 0 2812 #define cfg_ft_MASK 0x00000001 2813 #define cfg_ft_WORD word1 2814 #define cfg_sli_rev_SHIFT 4 2815 #define cfg_sli_rev_MASK 0x0000000f 2816 #define cfg_sli_rev_WORD word1 2817 #define cfg_sli_family_SHIFT 8 2818 #define cfg_sli_family_MASK 0x0000000f 2819 #define cfg_sli_family_WORD word1 2820 #define cfg_if_type_SHIFT 12 2821 #define cfg_if_type_MASK 0x0000000f 2822 #define cfg_if_type_WORD word1 2823 #define cfg_sli_hint_1_SHIFT 16 2824 #define cfg_sli_hint_1_MASK 0x000000ff 2825 #define cfg_sli_hint_1_WORD word1 2826 #define cfg_sli_hint_2_SHIFT 24 2827 #define cfg_sli_hint_2_MASK 0x0000001f 2828 #define cfg_sli_hint_2_WORD word1 2829 uint32_t word2; 2830 uint32_t word3; 2831 uint32_t word4; 2832 #define cfg_cqv_SHIFT 14 2833 #define cfg_cqv_MASK 0x00000003 2834 #define cfg_cqv_WORD word4 2835 uint32_t word5; 2836 uint32_t word6; 2837 #define cfg_mqv_SHIFT 14 2838 #define cfg_mqv_MASK 0x00000003 2839 #define cfg_mqv_WORD word6 2840 uint32_t word7; 2841 uint32_t word8; 2842 #define cfg_wqsize_SHIFT 8 2843 #define cfg_wqsize_MASK 0x0000000f 2844 #define cfg_wqsize_WORD word8 2845 #define cfg_wqv_SHIFT 14 2846 #define cfg_wqv_MASK 0x00000003 2847 #define cfg_wqv_WORD word8 2848 uint32_t word9; 2849 uint32_t word10; 2850 #define cfg_rqv_SHIFT 14 2851 #define cfg_rqv_MASK 0x00000003 2852 #define cfg_rqv_WORD word10 2853 uint32_t word11; 2854 #define cfg_rq_db_window_SHIFT 28 2855 #define cfg_rq_db_window_MASK 0x0000000f 2856 #define cfg_rq_db_window_WORD word11 2857 uint32_t word12; 2858 #define cfg_fcoe_SHIFT 0 2859 #define cfg_fcoe_MASK 0x00000001 2860 #define cfg_fcoe_WORD word12 2861 #define cfg_ext_SHIFT 1 2862 #define cfg_ext_MASK 0x00000001 2863 #define cfg_ext_WORD word12 2864 #define cfg_hdrr_SHIFT 2 2865 #define cfg_hdrr_MASK 0x00000001 2866 #define cfg_hdrr_WORD word12 2867 #define cfg_phwq_SHIFT 15 2868 #define cfg_phwq_MASK 0x00000001 2869 #define cfg_phwq_WORD word12 2870 #define cfg_oas_SHIFT 25 2871 #define cfg_oas_MASK 0x00000001 2872 #define cfg_oas_WORD word12 2873 #define cfg_loopbk_scope_SHIFT 28 2874 #define cfg_loopbk_scope_MASK 0x0000000f 2875 #define cfg_loopbk_scope_WORD word12 2876 uint32_t sge_supp_len; 2877 uint32_t word14; 2878 #define cfg_sgl_page_cnt_SHIFT 0 2879 #define cfg_sgl_page_cnt_MASK 0x0000000f 2880 #define cfg_sgl_page_cnt_WORD word14 2881 #define cfg_sgl_page_size_SHIFT 8 2882 #define cfg_sgl_page_size_MASK 0x000000ff 2883 #define cfg_sgl_page_size_WORD word14 2884 #define cfg_sgl_pp_align_SHIFT 16 2885 #define cfg_sgl_pp_align_MASK 0x000000ff 2886 #define cfg_sgl_pp_align_WORD word14 2887 uint32_t word15; 2888 uint32_t word16; 2889 uint32_t word17; 2890 uint32_t word18; 2891 uint32_t word19; 2892 #define cfg_ext_embed_cb_SHIFT 0 2893 #define cfg_ext_embed_cb_MASK 0x00000001 2894 #define cfg_ext_embed_cb_WORD word19 2895 #define cfg_mds_diags_SHIFT 1 2896 #define cfg_mds_diags_MASK 0x00000001 2897 #define cfg_mds_diags_WORD word19 2898 }; 2899 2900 #define LPFC_SET_UE_RECOVERY 0x10 2901 #define LPFC_SET_MDS_DIAGS 0x11 2902 struct lpfc_mbx_set_feature { 2903 struct mbox_header header; 2904 uint32_t feature; 2905 uint32_t param_len; 2906 uint32_t word6; 2907 #define lpfc_mbx_set_feature_UER_SHIFT 0 2908 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 2909 #define lpfc_mbx_set_feature_UER_WORD word6 2910 #define lpfc_mbx_set_feature_mds_SHIFT 0 2911 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 2912 #define lpfc_mbx_set_feature_mds_WORD word6 2913 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 2914 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 2915 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 2916 uint32_t word7; 2917 #define lpfc_mbx_set_feature_UERP_SHIFT 0 2918 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 2919 #define lpfc_mbx_set_feature_UERP_WORD word7 2920 #define lpfc_mbx_set_feature_UESR_SHIFT 16 2921 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 2922 #define lpfc_mbx_set_feature_UESR_WORD word7 2923 }; 2924 2925 2926 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 2927 struct lpfc_mbx_set_host_data { 2928 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 2929 struct mbox_header header; 2930 uint32_t param_id; 2931 uint32_t param_len; 2932 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 2933 }; 2934 2935 2936 struct lpfc_mbx_get_sli4_parameters { 2937 struct mbox_header header; 2938 struct lpfc_sli4_parameters sli4_parameters; 2939 }; 2940 2941 struct lpfc_rscr_desc_generic { 2942 #define LPFC_RSRC_DESC_WSIZE 22 2943 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2944 }; 2945 2946 struct lpfc_rsrc_desc_pcie { 2947 uint32_t word0; 2948 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2949 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2950 #define lpfc_rsrc_desc_pcie_type_WORD word0 2951 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2952 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 2953 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 2954 #define lpfc_rsrc_desc_pcie_length_WORD word0 2955 uint32_t word1; 2956 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2957 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2958 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2959 uint32_t reserved; 2960 uint32_t word3; 2961 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2962 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2963 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2964 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2965 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2966 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2967 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2968 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2969 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2970 uint32_t word4; 2971 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2972 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2973 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2974 }; 2975 2976 struct lpfc_rsrc_desc_fcfcoe { 2977 uint32_t word0; 2978 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2979 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2980 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2981 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2982 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 2983 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 2984 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 2985 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 2986 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 2987 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 2988 uint32_t word1; 2989 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2990 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2991 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2992 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2993 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2994 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2995 uint32_t word2; 2996 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2997 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2998 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2999 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3000 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3001 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3002 uint32_t word3; 3003 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3004 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3005 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3006 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3007 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3008 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3009 uint32_t word4; 3010 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3011 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3012 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3013 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3014 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3015 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3016 uint32_t word5; 3017 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3018 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3019 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3020 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3021 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3022 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3023 uint32_t word6; 3024 uint32_t word7; 3025 uint32_t word8; 3026 uint32_t word9; 3027 uint32_t word10; 3028 uint32_t word11; 3029 uint32_t word12; 3030 uint32_t word13; 3031 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3032 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3033 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3034 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3035 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3036 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3037 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3038 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3039 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3040 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3041 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3042 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3043 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3044 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3045 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3046 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3047 uint32_t bw_min; 3048 uint32_t bw_max; 3049 uint32_t iops_min; 3050 uint32_t iops_max; 3051 uint32_t reserved[4]; 3052 }; 3053 3054 struct lpfc_func_cfg { 3055 #define LPFC_RSRC_DESC_MAX_NUM 2 3056 uint32_t rsrc_desc_count; 3057 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3058 }; 3059 3060 struct lpfc_mbx_get_func_cfg { 3061 struct mbox_header header; 3062 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3063 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3064 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3065 struct lpfc_func_cfg func_cfg; 3066 }; 3067 3068 struct lpfc_prof_cfg { 3069 #define LPFC_RSRC_DESC_MAX_NUM 2 3070 uint32_t rsrc_desc_count; 3071 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3072 }; 3073 3074 struct lpfc_mbx_get_prof_cfg { 3075 struct mbox_header header; 3076 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3077 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3078 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3079 union { 3080 struct { 3081 uint32_t word10; 3082 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3083 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3084 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3085 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3086 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3087 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3088 } request; 3089 struct { 3090 struct lpfc_prof_cfg prof_cfg; 3091 } response; 3092 } u; 3093 }; 3094 3095 struct lpfc_controller_attribute { 3096 uint32_t version_string[8]; 3097 uint32_t manufacturer_name[8]; 3098 uint32_t supported_modes; 3099 uint32_t word17; 3100 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3101 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3102 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3103 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3104 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3105 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3106 uint32_t mbx_da_struct_ver; 3107 uint32_t ep_fw_da_struct_ver; 3108 uint32_t ncsi_ver_str[3]; 3109 uint32_t dflt_ext_timeout; 3110 uint32_t model_number[8]; 3111 uint32_t description[16]; 3112 uint32_t serial_number[8]; 3113 uint32_t ip_ver_str[8]; 3114 uint32_t fw_ver_str[8]; 3115 uint32_t bios_ver_str[8]; 3116 uint32_t redboot_ver_str[8]; 3117 uint32_t driver_ver_str[8]; 3118 uint32_t flash_fw_ver_str[8]; 3119 uint32_t functionality; 3120 uint32_t word105; 3121 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3122 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3123 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3124 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3125 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3126 #define lpfc_cntl_attr_asic_rev_WORD word105 3127 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3128 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3129 #define lpfc_cntl_attr_gen_guid0_WORD word105 3130 uint32_t gen_guid1_12[3]; 3131 uint32_t word109; 3132 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3133 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3134 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3135 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3136 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3137 #define lpfc_cntl_attr_gen_guid15_WORD word109 3138 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3139 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3140 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3141 uint32_t word110; 3142 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3143 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3144 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3145 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3146 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3147 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3148 uint32_t word111; 3149 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3150 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3151 #define lpfc_cntl_attr_cache_valid_WORD word111 3152 #define lpfc_cntl_attr_hba_status_SHIFT 8 3153 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3154 #define lpfc_cntl_attr_hba_status_WORD word111 3155 #define lpfc_cntl_attr_max_domain_SHIFT 16 3156 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3157 #define lpfc_cntl_attr_max_domain_WORD word111 3158 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3159 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3160 #define lpfc_cntl_attr_lnk_numb_WORD word111 3161 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3162 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3163 #define lpfc_cntl_attr_lnk_type_WORD word111 3164 uint32_t fw_post_status; 3165 uint32_t hba_mtu[8]; 3166 uint32_t word121; 3167 uint32_t reserved1[3]; 3168 uint32_t word125; 3169 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3170 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3171 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3172 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3173 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3174 #define lpfc_cntl_attr_pci_device_id_WORD word125 3175 uint32_t word126; 3176 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3177 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3178 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3179 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3180 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3181 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3182 uint32_t word127; 3183 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3184 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3185 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3186 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3187 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3188 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3189 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3190 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3191 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3192 #define lpfc_cntl_attr_inf_type_SHIFT 24 3193 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3194 #define lpfc_cntl_attr_inf_type_WORD word127 3195 uint32_t unique_id[2]; 3196 uint32_t word130; 3197 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3198 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3199 #define lpfc_cntl_attr_num_netfil_WORD word130 3200 uint32_t reserved2[4]; 3201 }; 3202 3203 struct lpfc_mbx_get_cntl_attributes { 3204 union lpfc_sli4_cfg_shdr cfg_shdr; 3205 struct lpfc_controller_attribute cntl_attr; 3206 }; 3207 3208 struct lpfc_mbx_get_port_name { 3209 struct mbox_header header; 3210 union { 3211 struct { 3212 uint32_t word4; 3213 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3214 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3215 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3216 } request; 3217 struct { 3218 uint32_t word4; 3219 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3220 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3221 #define lpfc_mbx_get_port_name_name0_WORD word4 3222 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3223 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3224 #define lpfc_mbx_get_port_name_name1_WORD word4 3225 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3226 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3227 #define lpfc_mbx_get_port_name_name2_WORD word4 3228 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3229 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3230 #define lpfc_mbx_get_port_name_name3_WORD word4 3231 #define LPFC_LINK_NUMBER_0 0 3232 #define LPFC_LINK_NUMBER_1 1 3233 #define LPFC_LINK_NUMBER_2 2 3234 #define LPFC_LINK_NUMBER_3 3 3235 } response; 3236 } u; 3237 }; 3238 3239 /* Mailbox Completion Queue Error Messages */ 3240 #define MB_CQE_STATUS_SUCCESS 0x0 3241 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3242 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3243 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3244 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3245 #define MB_CQE_STATUS_DMA_FAILED 0x5 3246 3247 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 3248 struct lpfc_mbx_wr_object { 3249 struct mbox_header header; 3250 union { 3251 struct { 3252 uint32_t word4; 3253 #define lpfc_wr_object_eof_SHIFT 31 3254 #define lpfc_wr_object_eof_MASK 0x00000001 3255 #define lpfc_wr_object_eof_WORD word4 3256 #define lpfc_wr_object_write_length_SHIFT 0 3257 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3258 #define lpfc_wr_object_write_length_WORD word4 3259 uint32_t write_offset; 3260 uint32_t object_name[26]; 3261 uint32_t bde_count; 3262 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3263 } request; 3264 struct { 3265 uint32_t actual_write_length; 3266 } response; 3267 } u; 3268 }; 3269 3270 /* mailbox queue entry structure */ 3271 struct lpfc_mqe { 3272 uint32_t word0; 3273 #define lpfc_mqe_status_SHIFT 16 3274 #define lpfc_mqe_status_MASK 0x0000FFFF 3275 #define lpfc_mqe_status_WORD word0 3276 #define lpfc_mqe_command_SHIFT 8 3277 #define lpfc_mqe_command_MASK 0x000000FF 3278 #define lpfc_mqe_command_WORD word0 3279 union { 3280 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3281 /* sli4 mailbox commands */ 3282 struct lpfc_mbx_sli4_config sli4_config; 3283 struct lpfc_mbx_init_vfi init_vfi; 3284 struct lpfc_mbx_reg_vfi reg_vfi; 3285 struct lpfc_mbx_reg_vfi unreg_vfi; 3286 struct lpfc_mbx_init_vpi init_vpi; 3287 struct lpfc_mbx_resume_rpi resume_rpi; 3288 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3289 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3290 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3291 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3292 struct lpfc_mbx_reg_fcfi reg_fcfi; 3293 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3294 struct lpfc_mbx_mq_create mq_create; 3295 struct lpfc_mbx_mq_create_ext mq_create_ext; 3296 struct lpfc_mbx_eq_create eq_create; 3297 struct lpfc_mbx_modify_eq_delay eq_delay; 3298 struct lpfc_mbx_cq_create cq_create; 3299 struct lpfc_mbx_wq_create wq_create; 3300 struct lpfc_mbx_rq_create rq_create; 3301 struct lpfc_mbx_mq_destroy mq_destroy; 3302 struct lpfc_mbx_eq_destroy eq_destroy; 3303 struct lpfc_mbx_cq_destroy cq_destroy; 3304 struct lpfc_mbx_wq_destroy wq_destroy; 3305 struct lpfc_mbx_rq_destroy rq_destroy; 3306 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3307 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3308 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3309 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3310 struct lpfc_mbx_nembed_cmd nembed_cmd; 3311 struct lpfc_mbx_read_rev read_rev; 3312 struct lpfc_mbx_read_vpi read_vpi; 3313 struct lpfc_mbx_read_config rd_config; 3314 struct lpfc_mbx_request_features req_ftrs; 3315 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3316 struct lpfc_mbx_query_fw_config query_fw_cfg; 3317 struct lpfc_mbx_set_beacon_config beacon_config; 3318 struct lpfc_mbx_supp_pages supp_pages; 3319 struct lpfc_mbx_pc_sli4_params sli4_params; 3320 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3321 struct lpfc_mbx_set_link_diag_state link_diag_state; 3322 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3323 struct lpfc_mbx_run_link_diag_test link_diag_test; 3324 struct lpfc_mbx_get_func_cfg get_func_cfg; 3325 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3326 struct lpfc_mbx_wr_object wr_object; 3327 struct lpfc_mbx_get_port_name get_port_name; 3328 struct lpfc_mbx_set_feature set_feature; 3329 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3330 struct lpfc_mbx_set_host_data set_host_data; 3331 struct lpfc_mbx_nop nop; 3332 } un; 3333 }; 3334 3335 struct lpfc_mcqe { 3336 uint32_t word0; 3337 #define lpfc_mcqe_status_SHIFT 0 3338 #define lpfc_mcqe_status_MASK 0x0000FFFF 3339 #define lpfc_mcqe_status_WORD word0 3340 #define lpfc_mcqe_ext_status_SHIFT 16 3341 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3342 #define lpfc_mcqe_ext_status_WORD word0 3343 uint32_t mcqe_tag0; 3344 uint32_t mcqe_tag1; 3345 uint32_t trailer; 3346 #define lpfc_trailer_valid_SHIFT 31 3347 #define lpfc_trailer_valid_MASK 0x00000001 3348 #define lpfc_trailer_valid_WORD trailer 3349 #define lpfc_trailer_async_SHIFT 30 3350 #define lpfc_trailer_async_MASK 0x00000001 3351 #define lpfc_trailer_async_WORD trailer 3352 #define lpfc_trailer_hpi_SHIFT 29 3353 #define lpfc_trailer_hpi_MASK 0x00000001 3354 #define lpfc_trailer_hpi_WORD trailer 3355 #define lpfc_trailer_completed_SHIFT 28 3356 #define lpfc_trailer_completed_MASK 0x00000001 3357 #define lpfc_trailer_completed_WORD trailer 3358 #define lpfc_trailer_consumed_SHIFT 27 3359 #define lpfc_trailer_consumed_MASK 0x00000001 3360 #define lpfc_trailer_consumed_WORD trailer 3361 #define lpfc_trailer_type_SHIFT 16 3362 #define lpfc_trailer_type_MASK 0x000000FF 3363 #define lpfc_trailer_type_WORD trailer 3364 #define lpfc_trailer_code_SHIFT 8 3365 #define lpfc_trailer_code_MASK 0x000000FF 3366 #define lpfc_trailer_code_WORD trailer 3367 #define LPFC_TRAILER_CODE_LINK 0x1 3368 #define LPFC_TRAILER_CODE_FCOE 0x2 3369 #define LPFC_TRAILER_CODE_DCBX 0x3 3370 #define LPFC_TRAILER_CODE_GRP5 0x5 3371 #define LPFC_TRAILER_CODE_FC 0x10 3372 #define LPFC_TRAILER_CODE_SLI 0x11 3373 }; 3374 3375 struct lpfc_acqe_link { 3376 uint32_t word0; 3377 #define lpfc_acqe_link_speed_SHIFT 24 3378 #define lpfc_acqe_link_speed_MASK 0x000000FF 3379 #define lpfc_acqe_link_speed_WORD word0 3380 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3381 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3382 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3383 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3384 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3385 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3386 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3387 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3388 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3389 #define lpfc_acqe_link_duplex_SHIFT 16 3390 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3391 #define lpfc_acqe_link_duplex_WORD word0 3392 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3393 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3394 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3395 #define lpfc_acqe_link_status_SHIFT 8 3396 #define lpfc_acqe_link_status_MASK 0x000000FF 3397 #define lpfc_acqe_link_status_WORD word0 3398 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3399 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3400 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3401 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3402 #define lpfc_acqe_link_type_SHIFT 6 3403 #define lpfc_acqe_link_type_MASK 0x00000003 3404 #define lpfc_acqe_link_type_WORD word0 3405 #define lpfc_acqe_link_number_SHIFT 0 3406 #define lpfc_acqe_link_number_MASK 0x0000003F 3407 #define lpfc_acqe_link_number_WORD word0 3408 uint32_t word1; 3409 #define lpfc_acqe_link_fault_SHIFT 0 3410 #define lpfc_acqe_link_fault_MASK 0x000000FF 3411 #define lpfc_acqe_link_fault_WORD word1 3412 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3413 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3414 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3415 #define lpfc_acqe_logical_link_speed_SHIFT 16 3416 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3417 #define lpfc_acqe_logical_link_speed_WORD word1 3418 uint32_t event_tag; 3419 uint32_t trailer; 3420 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3421 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3422 }; 3423 3424 struct lpfc_acqe_fip { 3425 uint32_t index; 3426 uint32_t word1; 3427 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3428 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3429 #define lpfc_acqe_fip_fcf_count_WORD word1 3430 #define lpfc_acqe_fip_event_type_SHIFT 16 3431 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3432 #define lpfc_acqe_fip_event_type_WORD word1 3433 uint32_t event_tag; 3434 uint32_t trailer; 3435 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3436 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3437 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3438 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3439 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3440 }; 3441 3442 struct lpfc_acqe_dcbx { 3443 uint32_t tlv_ttl; 3444 uint32_t reserved; 3445 uint32_t event_tag; 3446 uint32_t trailer; 3447 }; 3448 3449 struct lpfc_acqe_grp5 { 3450 uint32_t word0; 3451 #define lpfc_acqe_grp5_type_SHIFT 6 3452 #define lpfc_acqe_grp5_type_MASK 0x00000003 3453 #define lpfc_acqe_grp5_type_WORD word0 3454 #define lpfc_acqe_grp5_number_SHIFT 0 3455 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3456 #define lpfc_acqe_grp5_number_WORD word0 3457 uint32_t word1; 3458 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3459 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3460 #define lpfc_acqe_grp5_llink_spd_WORD word1 3461 uint32_t event_tag; 3462 uint32_t trailer; 3463 }; 3464 3465 struct lpfc_acqe_fc_la { 3466 uint32_t word0; 3467 #define lpfc_acqe_fc_la_speed_SHIFT 24 3468 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3469 #define lpfc_acqe_fc_la_speed_WORD word0 3470 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 3471 #define LPFC_FC_LA_SPEED_1G 0x1 3472 #define LPFC_FC_LA_SPEED_2G 0x2 3473 #define LPFC_FC_LA_SPEED_4G 0x4 3474 #define LPFC_FC_LA_SPEED_8G 0x8 3475 #define LPFC_FC_LA_SPEED_10G 0xA 3476 #define LPFC_FC_LA_SPEED_16G 0x10 3477 #define LPFC_FC_LA_SPEED_32G 0x20 3478 #define lpfc_acqe_fc_la_topology_SHIFT 16 3479 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3480 #define lpfc_acqe_fc_la_topology_WORD word0 3481 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3482 #define LPFC_FC_LA_TOP_P2P 0x1 3483 #define LPFC_FC_LA_TOP_FCAL 0x2 3484 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3485 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3486 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3487 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3488 #define lpfc_acqe_fc_la_att_type_WORD word0 3489 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3490 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3491 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3492 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 3493 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 3494 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3495 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3496 #define lpfc_acqe_fc_la_port_type_WORD word0 3497 #define LPFC_LINK_TYPE_ETHERNET 0x0 3498 #define LPFC_LINK_TYPE_FC 0x1 3499 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3500 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3501 #define lpfc_acqe_fc_la_port_number_WORD word0 3502 uint32_t word1; 3503 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3504 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3505 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3506 #define lpfc_acqe_fc_la_fault_SHIFT 0 3507 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3508 #define lpfc_acqe_fc_la_fault_WORD word1 3509 #define LPFC_FC_LA_FAULT_NONE 0x0 3510 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3511 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3512 uint32_t event_tag; 3513 uint32_t trailer; 3514 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3515 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3516 }; 3517 3518 struct lpfc_acqe_misconfigured_event { 3519 struct { 3520 uint32_t word0; 3521 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 3522 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 3523 #define lpfc_sli_misconfigured_port0_state_WORD word0 3524 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 3525 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 3526 #define lpfc_sli_misconfigured_port1_state_WORD word0 3527 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 3528 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 3529 #define lpfc_sli_misconfigured_port2_state_WORD word0 3530 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 3531 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 3532 #define lpfc_sli_misconfigured_port3_state_WORD word0 3533 uint32_t word1; 3534 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 3535 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 3536 #define lpfc_sli_misconfigured_port0_op_WORD word1 3537 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 3538 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 3539 #define lpfc_sli_misconfigured_port0_severity_WORD word1 3540 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 3541 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 3542 #define lpfc_sli_misconfigured_port1_op_WORD word1 3543 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 3544 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 3545 #define lpfc_sli_misconfigured_port1_severity_WORD word1 3546 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 3547 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 3548 #define lpfc_sli_misconfigured_port2_op_WORD word1 3549 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 3550 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 3551 #define lpfc_sli_misconfigured_port2_severity_WORD word1 3552 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 3553 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 3554 #define lpfc_sli_misconfigured_port3_op_WORD word1 3555 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 3556 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 3557 #define lpfc_sli_misconfigured_port3_severity_WORD word1 3558 } theEvent; 3559 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 3560 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 3561 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 3562 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 3563 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 3564 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 3565 }; 3566 3567 struct lpfc_acqe_sli { 3568 uint32_t event_data1; 3569 uint32_t event_data2; 3570 uint32_t reserved; 3571 uint32_t trailer; 3572 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3573 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3574 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3575 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3576 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3577 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 3578 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 3579 }; 3580 3581 /* 3582 * Define the bootstrap mailbox (bmbx) region used to communicate 3583 * mailbox command between the host and port. The mailbox consists 3584 * of a payload area of 256 bytes and a completion queue of length 3585 * 16 bytes. 3586 */ 3587 struct lpfc_bmbx_create { 3588 struct lpfc_mqe mqe; 3589 struct lpfc_mcqe mcqe; 3590 }; 3591 3592 #define SGL_ALIGN_SZ 64 3593 #define SGL_PAGE_SIZE 4096 3594 /* align SGL addr on a size boundary - adjust address up */ 3595 #define NO_XRI 0xffff 3596 3597 struct wqe_common { 3598 uint32_t word6; 3599 #define wqe_xri_tag_SHIFT 0 3600 #define wqe_xri_tag_MASK 0x0000FFFF 3601 #define wqe_xri_tag_WORD word6 3602 #define wqe_ctxt_tag_SHIFT 16 3603 #define wqe_ctxt_tag_MASK 0x0000FFFF 3604 #define wqe_ctxt_tag_WORD word6 3605 uint32_t word7; 3606 #define wqe_dif_SHIFT 0 3607 #define wqe_dif_MASK 0x00000003 3608 #define wqe_dif_WORD word7 3609 #define LPFC_WQE_DIF_PASSTHRU 1 3610 #define LPFC_WQE_DIF_STRIP 2 3611 #define LPFC_WQE_DIF_INSERT 3 3612 #define wqe_ct_SHIFT 2 3613 #define wqe_ct_MASK 0x00000003 3614 #define wqe_ct_WORD word7 3615 #define wqe_status_SHIFT 4 3616 #define wqe_status_MASK 0x0000000f 3617 #define wqe_status_WORD word7 3618 #define wqe_cmnd_SHIFT 8 3619 #define wqe_cmnd_MASK 0x000000ff 3620 #define wqe_cmnd_WORD word7 3621 #define wqe_class_SHIFT 16 3622 #define wqe_class_MASK 0x00000007 3623 #define wqe_class_WORD word7 3624 #define wqe_ar_SHIFT 19 3625 #define wqe_ar_MASK 0x00000001 3626 #define wqe_ar_WORD word7 3627 #define wqe_ag_SHIFT wqe_ar_SHIFT 3628 #define wqe_ag_MASK wqe_ar_MASK 3629 #define wqe_ag_WORD wqe_ar_WORD 3630 #define wqe_pu_SHIFT 20 3631 #define wqe_pu_MASK 0x00000003 3632 #define wqe_pu_WORD word7 3633 #define wqe_erp_SHIFT 22 3634 #define wqe_erp_MASK 0x00000001 3635 #define wqe_erp_WORD word7 3636 #define wqe_conf_SHIFT wqe_erp_SHIFT 3637 #define wqe_conf_MASK wqe_erp_MASK 3638 #define wqe_conf_WORD wqe_erp_WORD 3639 #define wqe_lnk_SHIFT 23 3640 #define wqe_lnk_MASK 0x00000001 3641 #define wqe_lnk_WORD word7 3642 #define wqe_tmo_SHIFT 24 3643 #define wqe_tmo_MASK 0x000000ff 3644 #define wqe_tmo_WORD word7 3645 uint32_t abort_tag; /* word 8 in WQE */ 3646 uint32_t word9; 3647 #define wqe_reqtag_SHIFT 0 3648 #define wqe_reqtag_MASK 0x0000FFFF 3649 #define wqe_reqtag_WORD word9 3650 #define wqe_temp_rpi_SHIFT 16 3651 #define wqe_temp_rpi_MASK 0x0000FFFF 3652 #define wqe_temp_rpi_WORD word9 3653 #define wqe_rcvoxid_SHIFT 16 3654 #define wqe_rcvoxid_MASK 0x0000FFFF 3655 #define wqe_rcvoxid_WORD word9 3656 uint32_t word10; 3657 #define wqe_ebde_cnt_SHIFT 0 3658 #define wqe_ebde_cnt_MASK 0x0000000f 3659 #define wqe_ebde_cnt_WORD word10 3660 #define wqe_oas_SHIFT 6 3661 #define wqe_oas_MASK 0x00000001 3662 #define wqe_oas_WORD word10 3663 #define wqe_lenloc_SHIFT 7 3664 #define wqe_lenloc_MASK 0x00000003 3665 #define wqe_lenloc_WORD word10 3666 #define LPFC_WQE_LENLOC_NONE 0 3667 #define LPFC_WQE_LENLOC_WORD3 1 3668 #define LPFC_WQE_LENLOC_WORD12 2 3669 #define LPFC_WQE_LENLOC_WORD4 3 3670 #define wqe_qosd_SHIFT 9 3671 #define wqe_qosd_MASK 0x00000001 3672 #define wqe_qosd_WORD word10 3673 #define wqe_xbl_SHIFT 11 3674 #define wqe_xbl_MASK 0x00000001 3675 #define wqe_xbl_WORD word10 3676 #define wqe_iod_SHIFT 13 3677 #define wqe_iod_MASK 0x00000001 3678 #define wqe_iod_WORD word10 3679 #define LPFC_WQE_IOD_WRITE 0 3680 #define LPFC_WQE_IOD_READ 1 3681 #define wqe_dbde_SHIFT 14 3682 #define wqe_dbde_MASK 0x00000001 3683 #define wqe_dbde_WORD word10 3684 #define wqe_wqes_SHIFT 15 3685 #define wqe_wqes_MASK 0x00000001 3686 #define wqe_wqes_WORD word10 3687 /* Note that this field overlaps above fields */ 3688 #define wqe_wqid_SHIFT 1 3689 #define wqe_wqid_MASK 0x00007fff 3690 #define wqe_wqid_WORD word10 3691 #define wqe_pri_SHIFT 16 3692 #define wqe_pri_MASK 0x00000007 3693 #define wqe_pri_WORD word10 3694 #define wqe_pv_SHIFT 19 3695 #define wqe_pv_MASK 0x00000001 3696 #define wqe_pv_WORD word10 3697 #define wqe_xc_SHIFT 21 3698 #define wqe_xc_MASK 0x00000001 3699 #define wqe_xc_WORD word10 3700 #define wqe_sr_SHIFT 22 3701 #define wqe_sr_MASK 0x00000001 3702 #define wqe_sr_WORD word10 3703 #define wqe_ccpe_SHIFT 23 3704 #define wqe_ccpe_MASK 0x00000001 3705 #define wqe_ccpe_WORD word10 3706 #define wqe_ccp_SHIFT 24 3707 #define wqe_ccp_MASK 0x000000ff 3708 #define wqe_ccp_WORD word10 3709 uint32_t word11; 3710 #define wqe_cmd_type_SHIFT 0 3711 #define wqe_cmd_type_MASK 0x0000000f 3712 #define wqe_cmd_type_WORD word11 3713 #define wqe_els_id_SHIFT 4 3714 #define wqe_els_id_MASK 0x00000003 3715 #define wqe_els_id_WORD word11 3716 #define LPFC_ELS_ID_FLOGI 3 3717 #define LPFC_ELS_ID_FDISC 2 3718 #define LPFC_ELS_ID_LOGO 1 3719 #define LPFC_ELS_ID_DEFAULT 0 3720 #define wqe_wqec_SHIFT 7 3721 #define wqe_wqec_MASK 0x00000001 3722 #define wqe_wqec_WORD word11 3723 #define wqe_cqid_SHIFT 16 3724 #define wqe_cqid_MASK 0x0000ffff 3725 #define wqe_cqid_WORD word11 3726 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3727 }; 3728 3729 struct wqe_did { 3730 uint32_t word5; 3731 #define wqe_els_did_SHIFT 0 3732 #define wqe_els_did_MASK 0x00FFFFFF 3733 #define wqe_els_did_WORD word5 3734 #define wqe_xmit_bls_pt_SHIFT 28 3735 #define wqe_xmit_bls_pt_MASK 0x00000003 3736 #define wqe_xmit_bls_pt_WORD word5 3737 #define wqe_xmit_bls_ar_SHIFT 30 3738 #define wqe_xmit_bls_ar_MASK 0x00000001 3739 #define wqe_xmit_bls_ar_WORD word5 3740 #define wqe_xmit_bls_xo_SHIFT 31 3741 #define wqe_xmit_bls_xo_MASK 0x00000001 3742 #define wqe_xmit_bls_xo_WORD word5 3743 }; 3744 3745 struct lpfc_wqe_generic{ 3746 struct ulp_bde64 bde; 3747 uint32_t word3; 3748 uint32_t word4; 3749 uint32_t word5; 3750 struct wqe_common wqe_com; 3751 uint32_t payload[4]; 3752 }; 3753 3754 struct els_request64_wqe { 3755 struct ulp_bde64 bde; 3756 uint32_t payload_len; 3757 uint32_t word4; 3758 #define els_req64_sid_SHIFT 0 3759 #define els_req64_sid_MASK 0x00FFFFFF 3760 #define els_req64_sid_WORD word4 3761 #define els_req64_sp_SHIFT 24 3762 #define els_req64_sp_MASK 0x00000001 3763 #define els_req64_sp_WORD word4 3764 #define els_req64_vf_SHIFT 25 3765 #define els_req64_vf_MASK 0x00000001 3766 #define els_req64_vf_WORD word4 3767 struct wqe_did wqe_dest; 3768 struct wqe_common wqe_com; /* words 6-11 */ 3769 uint32_t word12; 3770 #define els_req64_vfid_SHIFT 1 3771 #define els_req64_vfid_MASK 0x00000FFF 3772 #define els_req64_vfid_WORD word12 3773 #define els_req64_pri_SHIFT 13 3774 #define els_req64_pri_MASK 0x00000007 3775 #define els_req64_pri_WORD word12 3776 uint32_t word13; 3777 #define els_req64_hopcnt_SHIFT 24 3778 #define els_req64_hopcnt_MASK 0x000000ff 3779 #define els_req64_hopcnt_WORD word13 3780 uint32_t word14; 3781 uint32_t max_response_payload_len; 3782 }; 3783 3784 struct xmit_els_rsp64_wqe { 3785 struct ulp_bde64 bde; 3786 uint32_t response_payload_len; 3787 uint32_t word4; 3788 #define els_rsp64_sid_SHIFT 0 3789 #define els_rsp64_sid_MASK 0x00FFFFFF 3790 #define els_rsp64_sid_WORD word4 3791 #define els_rsp64_sp_SHIFT 24 3792 #define els_rsp64_sp_MASK 0x00000001 3793 #define els_rsp64_sp_WORD word4 3794 struct wqe_did wqe_dest; 3795 struct wqe_common wqe_com; /* words 6-11 */ 3796 uint32_t word12; 3797 #define wqe_rsp_temp_rpi_SHIFT 0 3798 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3799 #define wqe_rsp_temp_rpi_WORD word12 3800 uint32_t rsvd_13_15[3]; 3801 }; 3802 3803 struct xmit_bls_rsp64_wqe { 3804 uint32_t payload0; 3805 /* Payload0 for BA_ACC */ 3806 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3807 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3808 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3809 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3810 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3811 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3812 /* Payload0 for BA_RJT */ 3813 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3814 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3815 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3816 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3817 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3818 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3819 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3820 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3821 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3822 uint32_t word1; 3823 #define xmit_bls_rsp64_rxid_SHIFT 0 3824 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3825 #define xmit_bls_rsp64_rxid_WORD word1 3826 #define xmit_bls_rsp64_oxid_SHIFT 16 3827 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3828 #define xmit_bls_rsp64_oxid_WORD word1 3829 uint32_t word2; 3830 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3831 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3832 #define xmit_bls_rsp64_seqcnthi_WORD word2 3833 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3834 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3835 #define xmit_bls_rsp64_seqcntlo_WORD word2 3836 uint32_t rsrvd3; 3837 uint32_t rsrvd4; 3838 struct wqe_did wqe_dest; 3839 struct wqe_common wqe_com; /* words 6-11 */ 3840 uint32_t word12; 3841 #define xmit_bls_rsp64_temprpi_SHIFT 0 3842 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3843 #define xmit_bls_rsp64_temprpi_WORD word12 3844 uint32_t rsvd_13_15[3]; 3845 }; 3846 3847 struct wqe_rctl_dfctl { 3848 uint32_t word5; 3849 #define wqe_si_SHIFT 2 3850 #define wqe_si_MASK 0x000000001 3851 #define wqe_si_WORD word5 3852 #define wqe_la_SHIFT 3 3853 #define wqe_la_MASK 0x000000001 3854 #define wqe_la_WORD word5 3855 #define wqe_xo_SHIFT 6 3856 #define wqe_xo_MASK 0x000000001 3857 #define wqe_xo_WORD word5 3858 #define wqe_ls_SHIFT 7 3859 #define wqe_ls_MASK 0x000000001 3860 #define wqe_ls_WORD word5 3861 #define wqe_dfctl_SHIFT 8 3862 #define wqe_dfctl_MASK 0x0000000ff 3863 #define wqe_dfctl_WORD word5 3864 #define wqe_type_SHIFT 16 3865 #define wqe_type_MASK 0x0000000ff 3866 #define wqe_type_WORD word5 3867 #define wqe_rctl_SHIFT 24 3868 #define wqe_rctl_MASK 0x0000000ff 3869 #define wqe_rctl_WORD word5 3870 }; 3871 3872 struct xmit_seq64_wqe { 3873 struct ulp_bde64 bde; 3874 uint32_t rsvd3; 3875 uint32_t relative_offset; 3876 struct wqe_rctl_dfctl wge_ctl; 3877 struct wqe_common wqe_com; /* words 6-11 */ 3878 uint32_t xmit_len; 3879 uint32_t rsvd_12_15[3]; 3880 }; 3881 struct xmit_bcast64_wqe { 3882 struct ulp_bde64 bde; 3883 uint32_t seq_payload_len; 3884 uint32_t rsvd4; 3885 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3886 struct wqe_common wqe_com; /* words 6-11 */ 3887 uint32_t rsvd_12_15[4]; 3888 }; 3889 3890 struct gen_req64_wqe { 3891 struct ulp_bde64 bde; 3892 uint32_t request_payload_len; 3893 uint32_t relative_offset; 3894 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3895 struct wqe_common wqe_com; /* words 6-11 */ 3896 uint32_t rsvd_12_14[3]; 3897 uint32_t max_response_payload_len; 3898 }; 3899 3900 struct create_xri_wqe { 3901 uint32_t rsrvd[5]; /* words 0-4 */ 3902 struct wqe_did wqe_dest; /* word 5 */ 3903 struct wqe_common wqe_com; /* words 6-11 */ 3904 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3905 }; 3906 3907 #define T_REQUEST_TAG 3 3908 #define T_XRI_TAG 1 3909 3910 struct abort_cmd_wqe { 3911 uint32_t rsrvd[3]; 3912 uint32_t word3; 3913 #define abort_cmd_ia_SHIFT 0 3914 #define abort_cmd_ia_MASK 0x000000001 3915 #define abort_cmd_ia_WORD word3 3916 #define abort_cmd_criteria_SHIFT 8 3917 #define abort_cmd_criteria_MASK 0x0000000ff 3918 #define abort_cmd_criteria_WORD word3 3919 uint32_t rsrvd4; 3920 uint32_t rsrvd5; 3921 struct wqe_common wqe_com; /* words 6-11 */ 3922 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3923 }; 3924 3925 struct fcp_iwrite64_wqe { 3926 struct ulp_bde64 bde; 3927 uint32_t word3; 3928 #define cmd_buff_len_SHIFT 16 3929 #define cmd_buff_len_MASK 0x00000ffff 3930 #define cmd_buff_len_WORD word3 3931 #define payload_offset_len_SHIFT 0 3932 #define payload_offset_len_MASK 0x0000ffff 3933 #define payload_offset_len_WORD word3 3934 uint32_t total_xfer_len; 3935 uint32_t initial_xfer_len; 3936 struct wqe_common wqe_com; /* words 6-11 */ 3937 uint32_t rsrvd12; 3938 struct ulp_bde64 ph_bde; /* words 13-15 */ 3939 }; 3940 3941 struct fcp_iread64_wqe { 3942 struct ulp_bde64 bde; 3943 uint32_t word3; 3944 #define cmd_buff_len_SHIFT 16 3945 #define cmd_buff_len_MASK 0x00000ffff 3946 #define cmd_buff_len_WORD word3 3947 #define payload_offset_len_SHIFT 0 3948 #define payload_offset_len_MASK 0x0000ffff 3949 #define payload_offset_len_WORD word3 3950 uint32_t total_xfer_len; /* word 4 */ 3951 uint32_t rsrvd5; /* word 5 */ 3952 struct wqe_common wqe_com; /* words 6-11 */ 3953 uint32_t rsrvd12; 3954 struct ulp_bde64 ph_bde; /* words 13-15 */ 3955 }; 3956 3957 struct fcp_icmnd64_wqe { 3958 struct ulp_bde64 bde; /* words 0-2 */ 3959 uint32_t word3; 3960 #define cmd_buff_len_SHIFT 16 3961 #define cmd_buff_len_MASK 0x00000ffff 3962 #define cmd_buff_len_WORD word3 3963 #define payload_offset_len_SHIFT 0 3964 #define payload_offset_len_MASK 0x0000ffff 3965 #define payload_offset_len_WORD word3 3966 uint32_t rsrvd4; /* word 4 */ 3967 uint32_t rsrvd5; /* word 5 */ 3968 struct wqe_common wqe_com; /* words 6-11 */ 3969 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3970 }; 3971 3972 3973 union lpfc_wqe { 3974 uint32_t words[16]; 3975 struct lpfc_wqe_generic generic; 3976 struct fcp_icmnd64_wqe fcp_icmd; 3977 struct fcp_iread64_wqe fcp_iread; 3978 struct fcp_iwrite64_wqe fcp_iwrite; 3979 struct abort_cmd_wqe abort_cmd; 3980 struct create_xri_wqe create_xri; 3981 struct xmit_bcast64_wqe xmit_bcast64; 3982 struct xmit_seq64_wqe xmit_sequence; 3983 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3984 struct xmit_els_rsp64_wqe xmit_els_rsp; 3985 struct els_request64_wqe els_req; 3986 struct gen_req64_wqe gen_req; 3987 }; 3988 3989 union lpfc_wqe128 { 3990 uint32_t words[32]; 3991 struct lpfc_wqe_generic generic; 3992 struct fcp_icmnd64_wqe fcp_icmd; 3993 struct fcp_iread64_wqe fcp_iread; 3994 struct fcp_iwrite64_wqe fcp_iwrite; 3995 struct xmit_seq64_wqe xmit_sequence; 3996 struct gen_req64_wqe gen_req; 3997 }; 3998 3999 #define LPFC_GROUP_OJECT_MAGIC_G5 0xfeaa0001 4000 #define LPFC_GROUP_OJECT_MAGIC_G6 0xfeaa0003 4001 #define LPFC_FILE_TYPE_GROUP 0xf7 4002 #define LPFC_FILE_ID_GROUP 0xa2 4003 struct lpfc_grp_hdr { 4004 uint32_t size; 4005 uint32_t magic_number; 4006 uint32_t word2; 4007 #define lpfc_grp_hdr_file_type_SHIFT 24 4008 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4009 #define lpfc_grp_hdr_file_type_WORD word2 4010 #define lpfc_grp_hdr_id_SHIFT 16 4011 #define lpfc_grp_hdr_id_MASK 0x000000FF 4012 #define lpfc_grp_hdr_id_WORD word2 4013 uint8_t rev_name[128]; 4014 uint8_t date[12]; 4015 uint8_t revision[32]; 4016 }; 4017 4018 #define FCP_COMMAND 0x0 4019 #define FCP_COMMAND_DATA_OUT 0x1 4020 #define ELS_COMMAND_NON_FIP 0xC 4021 #define ELS_COMMAND_FIP 0xD 4022 #define OTHER_COMMAND 0x8 4023 4024 #define LPFC_FW_DUMP 1 4025 #define LPFC_FW_RESET 2 4026 #define LPFC_DV_RESET 3 4027