1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2018 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 /* Macros to deal with bit fields. Each bit field must have 3 #defines 24 * associated with it (_SHIFT, _MASK, and _WORD). 25 * EG. For a bit field that is in the 7th bit of the "field4" field of a 26 * structure and is 2 bits in size the following #defines must exist: 27 * struct temp { 28 * uint32_t field1; 29 * uint32_t field2; 30 * uint32_t field3; 31 * uint32_t field4; 32 * #define example_bit_field_SHIFT 7 33 * #define example_bit_field_MASK 0x03 34 * #define example_bit_field_WORD field4 35 * uint32_t field5; 36 * }; 37 * Then the macros below may be used to get or set the value of that field. 38 * EG. To get the value of the bit field from the above example: 39 * struct temp t1; 40 * value = bf_get(example_bit_field, &t1); 41 * And then to set that bit field: 42 * bf_set(example_bit_field, &t1, 2); 43 * Or clear that bit field: 44 * bf_set(example_bit_field, &t1, 0); 45 */ 46 #define bf_get_be32(name, ptr) \ 47 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get_le32(name, ptr) \ 49 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get(name, ptr) \ 51 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 52 #define bf_set_le32(name, ptr, value) \ 53 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 54 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 55 ~(name##_MASK << name##_SHIFT))))) 56 #define bf_set(name, ptr, value) \ 57 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 58 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 59 60 struct dma_address { 61 uint32_t addr_lo; 62 uint32_t addr_hi; 63 }; 64 65 struct lpfc_sli_intf { 66 uint32_t word0; 67 #define lpfc_sli_intf_valid_SHIFT 29 68 #define lpfc_sli_intf_valid_MASK 0x00000007 69 #define lpfc_sli_intf_valid_WORD word0 70 #define LPFC_SLI_INTF_VALID 6 71 #define lpfc_sli_intf_sli_hint2_SHIFT 24 72 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 73 #define lpfc_sli_intf_sli_hint2_WORD word0 74 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 75 #define lpfc_sli_intf_sli_hint1_SHIFT 16 76 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 77 #define lpfc_sli_intf_sli_hint1_WORD word0 78 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 79 #define LPFC_SLI_INTF_SLI_HINT1_1 1 80 #define LPFC_SLI_INTF_SLI_HINT1_2 2 81 #define lpfc_sli_intf_if_type_SHIFT 12 82 #define lpfc_sli_intf_if_type_MASK 0x0000000F 83 #define lpfc_sli_intf_if_type_WORD word0 84 #define LPFC_SLI_INTF_IF_TYPE_0 0 85 #define LPFC_SLI_INTF_IF_TYPE_1 1 86 #define LPFC_SLI_INTF_IF_TYPE_2 2 87 #define LPFC_SLI_INTF_IF_TYPE_6 6 88 #define lpfc_sli_intf_sli_family_SHIFT 8 89 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 90 #define lpfc_sli_intf_sli_family_WORD word0 91 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 92 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 93 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 94 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 95 #define lpfc_sli_intf_slirev_SHIFT 4 96 #define lpfc_sli_intf_slirev_MASK 0x0000000F 97 #define lpfc_sli_intf_slirev_WORD word0 98 #define LPFC_SLI_INTF_REV_SLI3 3 99 #define LPFC_SLI_INTF_REV_SLI4 4 100 #define lpfc_sli_intf_func_type_SHIFT 0 101 #define lpfc_sli_intf_func_type_MASK 0x00000001 102 #define lpfc_sli_intf_func_type_WORD word0 103 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 104 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 105 }; 106 107 #define LPFC_SLI4_MBX_EMBED true 108 #define LPFC_SLI4_MBX_NEMBED false 109 110 #define LPFC_SLI4_MB_WORD_COUNT 64 111 #define LPFC_MAX_MQ_PAGE 8 112 #define LPFC_MAX_WQ_PAGE_V0 4 113 #define LPFC_MAX_WQ_PAGE 8 114 #define LPFC_MAX_RQ_PAGE 8 115 #define LPFC_MAX_CQ_PAGE 4 116 #define LPFC_MAX_EQ_PAGE 8 117 118 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 119 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 120 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 121 122 /* Define SLI4 Alignment requirements. */ 123 #define LPFC_ALIGN_16_BYTE 16 124 #define LPFC_ALIGN_64_BYTE 64 125 126 /* Define SLI4 specific definitions. */ 127 #define LPFC_MQ_CQE_BYTE_OFFSET 256 128 #define LPFC_MBX_CMD_HDR_LENGTH 16 129 #define LPFC_MBX_ERROR_RANGE 0x4000 130 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 131 #define LPFC_BMBX_BIT1_ADDR_LO 0 132 #define LPFC_RPI_HDR_COUNT 64 133 #define LPFC_HDR_TEMPLATE_SIZE 4096 134 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 135 #define LPFC_FCF_RECORD_WD_CNT 132 136 #define LPFC_ENTIRE_FCF_DATABASE 0 137 #define LPFC_DFLT_FCF_INDEX 0 138 139 /* Virtual function numbers */ 140 #define LPFC_VF0 0 141 #define LPFC_VF1 1 142 #define LPFC_VF2 2 143 #define LPFC_VF3 3 144 #define LPFC_VF4 4 145 #define LPFC_VF5 5 146 #define LPFC_VF6 6 147 #define LPFC_VF7 7 148 #define LPFC_VF8 8 149 #define LPFC_VF9 9 150 #define LPFC_VF10 10 151 #define LPFC_VF11 11 152 #define LPFC_VF12 12 153 #define LPFC_VF13 13 154 #define LPFC_VF14 14 155 #define LPFC_VF15 15 156 #define LPFC_VF16 16 157 #define LPFC_VF17 17 158 #define LPFC_VF18 18 159 #define LPFC_VF19 19 160 #define LPFC_VF20 20 161 #define LPFC_VF21 21 162 #define LPFC_VF22 22 163 #define LPFC_VF23 23 164 #define LPFC_VF24 24 165 #define LPFC_VF25 25 166 #define LPFC_VF26 26 167 #define LPFC_VF27 27 168 #define LPFC_VF28 28 169 #define LPFC_VF29 29 170 #define LPFC_VF30 30 171 #define LPFC_VF31 31 172 173 /* PCI function numbers */ 174 #define LPFC_PCI_FUNC0 0 175 #define LPFC_PCI_FUNC1 1 176 #define LPFC_PCI_FUNC2 2 177 #define LPFC_PCI_FUNC3 3 178 #define LPFC_PCI_FUNC4 4 179 180 /* SLI4 interface type-2 PDEV_CTL register */ 181 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 182 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 183 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 184 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 185 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 186 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 187 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 188 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 189 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 190 191 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 192 193 /* Active interrupt test count */ 194 #define LPFC_ACT_INTR_CNT 4 195 196 /* Algrithmns for scheduling FCP commands to WQs */ 197 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 198 #define LPFC_FCP_SCHED_BY_CPU 1 199 200 /* Delay Multiplier constant */ 201 #define LPFC_DMULT_CONST 651042 202 #define LPFC_DMULT_MAX 1023 203 204 /* Configuration of Interrupts / sec for entire HBA port */ 205 #define LPFC_MIN_IMAX 5000 206 #define LPFC_MAX_IMAX 5000000 207 #define LPFC_DEF_IMAX 150000 208 209 #define LPFC_MIN_CPU_MAP 0 210 #define LPFC_MAX_CPU_MAP 2 211 #define LPFC_HBA_CPU_MAP 1 212 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 213 214 /* PORT_CAPABILITIES constants. */ 215 #define LPFC_MAX_SUPPORTED_PAGES 8 216 217 struct ulp_bde64 { 218 union ULP_BDE_TUS { 219 uint32_t w; 220 struct { 221 #ifdef __BIG_ENDIAN_BITFIELD 222 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 223 VALUE !! */ 224 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 225 #else /* __LITTLE_ENDIAN_BITFIELD */ 226 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 227 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 228 VALUE !! */ 229 #endif 230 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 231 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 232 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 233 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 234 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 235 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 236 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 237 } f; 238 } tus; 239 uint32_t addrLow; 240 uint32_t addrHigh; 241 }; 242 243 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 244 #define LPFC_MAX_BDE_IMM_SIZE 64 245 246 struct lpfc_sli4_flags { 247 uint32_t word0; 248 #define lpfc_idx_rsrc_rdy_SHIFT 0 249 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 250 #define lpfc_idx_rsrc_rdy_WORD word0 251 #define LPFC_IDX_RSRC_RDY 1 252 #define lpfc_rpi_rsrc_rdy_SHIFT 1 253 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 254 #define lpfc_rpi_rsrc_rdy_WORD word0 255 #define LPFC_RPI_RSRC_RDY 1 256 #define lpfc_vpi_rsrc_rdy_SHIFT 2 257 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 258 #define lpfc_vpi_rsrc_rdy_WORD word0 259 #define LPFC_VPI_RSRC_RDY 1 260 #define lpfc_vfi_rsrc_rdy_SHIFT 3 261 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 262 #define lpfc_vfi_rsrc_rdy_WORD word0 263 #define LPFC_VFI_RSRC_RDY 1 264 }; 265 266 struct sli4_bls_rsp { 267 uint32_t word0_rsvd; /* Word0 must be reserved */ 268 uint32_t word1; 269 #define lpfc_abts_orig_SHIFT 0 270 #define lpfc_abts_orig_MASK 0x00000001 271 #define lpfc_abts_orig_WORD word1 272 #define LPFC_ABTS_UNSOL_RSP 1 273 #define LPFC_ABTS_UNSOL_INT 0 274 uint32_t word2; 275 #define lpfc_abts_rxid_SHIFT 0 276 #define lpfc_abts_rxid_MASK 0x0000FFFF 277 #define lpfc_abts_rxid_WORD word2 278 #define lpfc_abts_oxid_SHIFT 16 279 #define lpfc_abts_oxid_MASK 0x0000FFFF 280 #define lpfc_abts_oxid_WORD word2 281 uint32_t word3; 282 #define lpfc_vndr_code_SHIFT 0 283 #define lpfc_vndr_code_MASK 0x000000FF 284 #define lpfc_vndr_code_WORD word3 285 #define lpfc_rsn_expln_SHIFT 8 286 #define lpfc_rsn_expln_MASK 0x000000FF 287 #define lpfc_rsn_expln_WORD word3 288 #define lpfc_rsn_code_SHIFT 16 289 #define lpfc_rsn_code_MASK 0x000000FF 290 #define lpfc_rsn_code_WORD word3 291 292 uint32_t word4; 293 uint32_t word5_rsvd; /* Word5 must be reserved */ 294 }; 295 296 /* event queue entry structure */ 297 struct lpfc_eqe { 298 uint32_t word0; 299 #define lpfc_eqe_resource_id_SHIFT 16 300 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 301 #define lpfc_eqe_resource_id_WORD word0 302 #define lpfc_eqe_minor_code_SHIFT 4 303 #define lpfc_eqe_minor_code_MASK 0x00000FFF 304 #define lpfc_eqe_minor_code_WORD word0 305 #define lpfc_eqe_major_code_SHIFT 1 306 #define lpfc_eqe_major_code_MASK 0x00000007 307 #define lpfc_eqe_major_code_WORD word0 308 #define lpfc_eqe_valid_SHIFT 0 309 #define lpfc_eqe_valid_MASK 0x00000001 310 #define lpfc_eqe_valid_WORD word0 311 }; 312 313 /* completion queue entry structure (common fields for all cqe types) */ 314 struct lpfc_cqe { 315 uint32_t reserved0; 316 uint32_t reserved1; 317 uint32_t reserved2; 318 uint32_t word3; 319 #define lpfc_cqe_valid_SHIFT 31 320 #define lpfc_cqe_valid_MASK 0x00000001 321 #define lpfc_cqe_valid_WORD word3 322 #define lpfc_cqe_code_SHIFT 16 323 #define lpfc_cqe_code_MASK 0x000000FF 324 #define lpfc_cqe_code_WORD word3 325 }; 326 327 /* Completion Queue Entry Status Codes */ 328 #define CQE_STATUS_SUCCESS 0x0 329 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 330 #define CQE_STATUS_REMOTE_STOP 0x2 331 #define CQE_STATUS_LOCAL_REJECT 0x3 332 #define CQE_STATUS_NPORT_RJT 0x4 333 #define CQE_STATUS_FABRIC_RJT 0x5 334 #define CQE_STATUS_NPORT_BSY 0x6 335 #define CQE_STATUS_FABRIC_BSY 0x7 336 #define CQE_STATUS_INTERMED_RSP 0x8 337 #define CQE_STATUS_LS_RJT 0x9 338 #define CQE_STATUS_CMD_REJECT 0xb 339 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 340 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 341 #define CQE_STATUS_DI_ERROR 0x16 342 343 /* Used when mapping CQE status to IOCB */ 344 #define LPFC_IOCB_STATUS_MASK 0xf 345 346 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 347 #define CQE_HW_STATUS_NO_ERR 0x0 348 #define CQE_HW_STATUS_UNDERRUN 0x1 349 #define CQE_HW_STATUS_OVERRUN 0x2 350 351 /* Completion Queue Entry Codes */ 352 #define CQE_CODE_COMPL_WQE 0x1 353 #define CQE_CODE_RELEASE_WQE 0x2 354 #define CQE_CODE_RECEIVE 0x4 355 #define CQE_CODE_XRI_ABORTED 0x5 356 #define CQE_CODE_RECEIVE_V1 0x9 357 #define CQE_CODE_NVME_ERSP 0xd 358 359 /* 360 * Define mask value for xri_aborted and wcqe completed CQE extended status. 361 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 362 */ 363 #define WCQE_PARAM_MASK 0x1FF 364 365 /* completion queue entry for wqe completions */ 366 struct lpfc_wcqe_complete { 367 uint32_t word0; 368 #define lpfc_wcqe_c_request_tag_SHIFT 16 369 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 370 #define lpfc_wcqe_c_request_tag_WORD word0 371 #define lpfc_wcqe_c_status_SHIFT 8 372 #define lpfc_wcqe_c_status_MASK 0x000000FF 373 #define lpfc_wcqe_c_status_WORD word0 374 #define lpfc_wcqe_c_hw_status_SHIFT 0 375 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 376 #define lpfc_wcqe_c_hw_status_WORD word0 377 #define lpfc_wcqe_c_ersp0_SHIFT 0 378 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 379 #define lpfc_wcqe_c_ersp0_WORD word0 380 uint32_t total_data_placed; 381 uint32_t parameter; 382 #define lpfc_wcqe_c_bg_edir_SHIFT 5 383 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 384 #define lpfc_wcqe_c_bg_edir_WORD parameter 385 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 386 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 387 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 388 #define lpfc_wcqe_c_bg_re_SHIFT 2 389 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 390 #define lpfc_wcqe_c_bg_re_WORD parameter 391 #define lpfc_wcqe_c_bg_ae_SHIFT 1 392 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 393 #define lpfc_wcqe_c_bg_ae_WORD parameter 394 #define lpfc_wcqe_c_bg_ge_SHIFT 0 395 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 396 #define lpfc_wcqe_c_bg_ge_WORD parameter 397 uint32_t word3; 398 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 399 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 400 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 401 #define lpfc_wcqe_c_xb_SHIFT 28 402 #define lpfc_wcqe_c_xb_MASK 0x00000001 403 #define lpfc_wcqe_c_xb_WORD word3 404 #define lpfc_wcqe_c_pv_SHIFT 27 405 #define lpfc_wcqe_c_pv_MASK 0x00000001 406 #define lpfc_wcqe_c_pv_WORD word3 407 #define lpfc_wcqe_c_priority_SHIFT 24 408 #define lpfc_wcqe_c_priority_MASK 0x00000007 409 #define lpfc_wcqe_c_priority_WORD word3 410 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 411 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 412 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 413 #define lpfc_wcqe_c_sqhead_SHIFT 0 414 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 415 #define lpfc_wcqe_c_sqhead_WORD word3 416 }; 417 418 /* completion queue entry for wqe release */ 419 struct lpfc_wcqe_release { 420 uint32_t reserved0; 421 uint32_t reserved1; 422 uint32_t word2; 423 #define lpfc_wcqe_r_wq_id_SHIFT 16 424 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 425 #define lpfc_wcqe_r_wq_id_WORD word2 426 #define lpfc_wcqe_r_wqe_index_SHIFT 0 427 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 428 #define lpfc_wcqe_r_wqe_index_WORD word2 429 uint32_t word3; 430 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 431 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 432 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 433 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 434 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 435 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 436 }; 437 438 struct sli4_wcqe_xri_aborted { 439 uint32_t word0; 440 #define lpfc_wcqe_xa_status_SHIFT 8 441 #define lpfc_wcqe_xa_status_MASK 0x000000FF 442 #define lpfc_wcqe_xa_status_WORD word0 443 uint32_t parameter; 444 uint32_t word2; 445 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 446 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 447 #define lpfc_wcqe_xa_remote_xid_WORD word2 448 #define lpfc_wcqe_xa_xri_SHIFT 0 449 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 450 #define lpfc_wcqe_xa_xri_WORD word2 451 uint32_t word3; 452 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 453 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 454 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 455 #define lpfc_wcqe_xa_ia_SHIFT 30 456 #define lpfc_wcqe_xa_ia_MASK 0x00000001 457 #define lpfc_wcqe_xa_ia_WORD word3 458 #define CQE_XRI_ABORTED_IA_REMOTE 0 459 #define CQE_XRI_ABORTED_IA_LOCAL 1 460 #define lpfc_wcqe_xa_br_SHIFT 29 461 #define lpfc_wcqe_xa_br_MASK 0x00000001 462 #define lpfc_wcqe_xa_br_WORD word3 463 #define CQE_XRI_ABORTED_BR_BA_ACC 0 464 #define CQE_XRI_ABORTED_BR_BA_RJT 1 465 #define lpfc_wcqe_xa_eo_SHIFT 28 466 #define lpfc_wcqe_xa_eo_MASK 0x00000001 467 #define lpfc_wcqe_xa_eo_WORD word3 468 #define CQE_XRI_ABORTED_EO_REMOTE 0 469 #define CQE_XRI_ABORTED_EO_LOCAL 1 470 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 471 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 472 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 473 }; 474 475 /* completion queue entry structure for rqe completion */ 476 struct lpfc_rcqe { 477 uint32_t word0; 478 #define lpfc_rcqe_bindex_SHIFT 16 479 #define lpfc_rcqe_bindex_MASK 0x0000FFF 480 #define lpfc_rcqe_bindex_WORD word0 481 #define lpfc_rcqe_status_SHIFT 8 482 #define lpfc_rcqe_status_MASK 0x000000FF 483 #define lpfc_rcqe_status_WORD word0 484 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 485 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 486 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 487 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 488 uint32_t word1; 489 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 490 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 491 #define lpfc_rcqe_fcf_id_v1_WORD word1 492 uint32_t word2; 493 #define lpfc_rcqe_length_SHIFT 16 494 #define lpfc_rcqe_length_MASK 0x0000FFFF 495 #define lpfc_rcqe_length_WORD word2 496 #define lpfc_rcqe_rq_id_SHIFT 6 497 #define lpfc_rcqe_rq_id_MASK 0x000003FF 498 #define lpfc_rcqe_rq_id_WORD word2 499 #define lpfc_rcqe_fcf_id_SHIFT 0 500 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 501 #define lpfc_rcqe_fcf_id_WORD word2 502 #define lpfc_rcqe_rq_id_v1_SHIFT 0 503 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 504 #define lpfc_rcqe_rq_id_v1_WORD word2 505 uint32_t word3; 506 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 507 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 508 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 509 #define lpfc_rcqe_port_SHIFT 30 510 #define lpfc_rcqe_port_MASK 0x00000001 511 #define lpfc_rcqe_port_WORD word3 512 #define lpfc_rcqe_hdr_length_SHIFT 24 513 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 514 #define lpfc_rcqe_hdr_length_WORD word3 515 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 516 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 517 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 518 #define lpfc_rcqe_eof_SHIFT 8 519 #define lpfc_rcqe_eof_MASK 0x000000FF 520 #define lpfc_rcqe_eof_WORD word3 521 #define FCOE_EOFn 0x41 522 #define FCOE_EOFt 0x42 523 #define FCOE_EOFni 0x49 524 #define FCOE_EOFa 0x50 525 #define lpfc_rcqe_sof_SHIFT 0 526 #define lpfc_rcqe_sof_MASK 0x000000FF 527 #define lpfc_rcqe_sof_WORD word3 528 #define FCOE_SOFi2 0x2d 529 #define FCOE_SOFi3 0x2e 530 #define FCOE_SOFn2 0x35 531 #define FCOE_SOFn3 0x36 532 }; 533 534 struct lpfc_rqe { 535 uint32_t address_hi; 536 uint32_t address_lo; 537 }; 538 539 /* buffer descriptors */ 540 struct lpfc_bde4 { 541 uint32_t addr_hi; 542 uint32_t addr_lo; 543 uint32_t word2; 544 #define lpfc_bde4_last_SHIFT 31 545 #define lpfc_bde4_last_MASK 0x00000001 546 #define lpfc_bde4_last_WORD word2 547 #define lpfc_bde4_sge_offset_SHIFT 0 548 #define lpfc_bde4_sge_offset_MASK 0x000003FF 549 #define lpfc_bde4_sge_offset_WORD word2 550 uint32_t word3; 551 #define lpfc_bde4_length_SHIFT 0 552 #define lpfc_bde4_length_MASK 0x000000FF 553 #define lpfc_bde4_length_WORD word3 554 }; 555 556 struct lpfc_register { 557 uint32_t word0; 558 }; 559 560 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 561 #define LPFC_PORT_SEM_MASK 0xF000 562 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 563 #define LPFC_UERR_STATUS_HI 0x00A4 564 #define LPFC_UERR_STATUS_LO 0x00A0 565 #define LPFC_UE_MASK_HI 0x00AC 566 #define LPFC_UE_MASK_LO 0x00A8 567 568 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 569 #define LPFC_SLI_INTF 0x0058 570 #define LPFC_SLI_ASIC_VER 0x009C 571 572 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 573 #define lpfc_port_smphr_perr_SHIFT 31 574 #define lpfc_port_smphr_perr_MASK 0x1 575 #define lpfc_port_smphr_perr_WORD word0 576 #define lpfc_port_smphr_sfi_SHIFT 30 577 #define lpfc_port_smphr_sfi_MASK 0x1 578 #define lpfc_port_smphr_sfi_WORD word0 579 #define lpfc_port_smphr_nip_SHIFT 29 580 #define lpfc_port_smphr_nip_MASK 0x1 581 #define lpfc_port_smphr_nip_WORD word0 582 #define lpfc_port_smphr_ipc_SHIFT 28 583 #define lpfc_port_smphr_ipc_MASK 0x1 584 #define lpfc_port_smphr_ipc_WORD word0 585 #define lpfc_port_smphr_scr1_SHIFT 27 586 #define lpfc_port_smphr_scr1_MASK 0x1 587 #define lpfc_port_smphr_scr1_WORD word0 588 #define lpfc_port_smphr_scr2_SHIFT 26 589 #define lpfc_port_smphr_scr2_MASK 0x1 590 #define lpfc_port_smphr_scr2_WORD word0 591 #define lpfc_port_smphr_host_scratch_SHIFT 16 592 #define lpfc_port_smphr_host_scratch_MASK 0xFF 593 #define lpfc_port_smphr_host_scratch_WORD word0 594 #define lpfc_port_smphr_port_status_SHIFT 0 595 #define lpfc_port_smphr_port_status_MASK 0xFFFF 596 #define lpfc_port_smphr_port_status_WORD word0 597 598 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 599 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 600 #define LPFC_POST_STAGE_HOST_RDY 0x0002 601 #define LPFC_POST_STAGE_BE_RESET 0x0003 602 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 603 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 604 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 605 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 606 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 607 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 608 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 609 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 610 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 611 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 612 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 613 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 614 #define LPFC_POST_STAGE_ARMFW_START 0x0800 615 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 616 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 617 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 618 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 619 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 620 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 621 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 622 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 623 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 624 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 625 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 626 #define LPFC_POST_STAGE_RC_DONE 0x0B07 627 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 628 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 629 #define LPFC_POST_STAGE_PORT_READY 0xC000 630 #define LPFC_POST_STAGE_PORT_UE 0xF000 631 632 #define LPFC_CTL_PORT_STA_OFFSET 0x404 633 #define lpfc_sliport_status_err_SHIFT 31 634 #define lpfc_sliport_status_err_MASK 0x1 635 #define lpfc_sliport_status_err_WORD word0 636 #define lpfc_sliport_status_end_SHIFT 30 637 #define lpfc_sliport_status_end_MASK 0x1 638 #define lpfc_sliport_status_end_WORD word0 639 #define lpfc_sliport_status_oti_SHIFT 29 640 #define lpfc_sliport_status_oti_MASK 0x1 641 #define lpfc_sliport_status_oti_WORD word0 642 #define lpfc_sliport_status_rn_SHIFT 24 643 #define lpfc_sliport_status_rn_MASK 0x1 644 #define lpfc_sliport_status_rn_WORD word0 645 #define lpfc_sliport_status_rdy_SHIFT 23 646 #define lpfc_sliport_status_rdy_MASK 0x1 647 #define lpfc_sliport_status_rdy_WORD word0 648 #define MAX_IF_TYPE_2_RESETS 6 649 650 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 651 #define lpfc_sliport_ctrl_end_SHIFT 30 652 #define lpfc_sliport_ctrl_end_MASK 0x1 653 #define lpfc_sliport_ctrl_end_WORD word0 654 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 655 #define LPFC_SLIPORT_BIG_ENDIAN 1 656 #define lpfc_sliport_ctrl_ip_SHIFT 27 657 #define lpfc_sliport_ctrl_ip_MASK 0x1 658 #define lpfc_sliport_ctrl_ip_WORD word0 659 #define LPFC_SLIPORT_INIT_PORT 1 660 661 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 662 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 663 664 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 665 #define lpfc_sliport_eqdelay_delay_SHIFT 16 666 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 667 #define lpfc_sliport_eqdelay_delay_WORD word0 668 #define lpfc_sliport_eqdelay_id_SHIFT 0 669 #define lpfc_sliport_eqdelay_id_MASK 0xfff 670 #define lpfc_sliport_eqdelay_id_WORD word0 671 #define LPFC_SEC_TO_USEC 1000000 672 673 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 674 * reside in BAR 2. 675 */ 676 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 677 678 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 679 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 680 681 #define LPFC_HST_ISR0 0x0C18 682 #define LPFC_HST_ISR1 0x0C1C 683 #define LPFC_HST_ISR2 0x0C20 684 #define LPFC_HST_ISR3 0x0C24 685 #define LPFC_HST_ISR4 0x0C28 686 687 #define LPFC_HST_IMR0 0x0C48 688 #define LPFC_HST_IMR1 0x0C4C 689 #define LPFC_HST_IMR2 0x0C50 690 #define LPFC_HST_IMR3 0x0C54 691 #define LPFC_HST_IMR4 0x0C58 692 693 #define LPFC_HST_ISCR0 0x0C78 694 #define LPFC_HST_ISCR1 0x0C7C 695 #define LPFC_HST_ISCR2 0x0C80 696 #define LPFC_HST_ISCR3 0x0C84 697 #define LPFC_HST_ISCR4 0x0C88 698 699 #define LPFC_SLI4_INTR0 BIT0 700 #define LPFC_SLI4_INTR1 BIT1 701 #define LPFC_SLI4_INTR2 BIT2 702 #define LPFC_SLI4_INTR3 BIT3 703 #define LPFC_SLI4_INTR4 BIT4 704 #define LPFC_SLI4_INTR5 BIT5 705 #define LPFC_SLI4_INTR6 BIT6 706 #define LPFC_SLI4_INTR7 BIT7 707 #define LPFC_SLI4_INTR8 BIT8 708 #define LPFC_SLI4_INTR9 BIT9 709 #define LPFC_SLI4_INTR10 BIT10 710 #define LPFC_SLI4_INTR11 BIT11 711 #define LPFC_SLI4_INTR12 BIT12 712 #define LPFC_SLI4_INTR13 BIT13 713 #define LPFC_SLI4_INTR14 BIT14 714 #define LPFC_SLI4_INTR15 BIT15 715 #define LPFC_SLI4_INTR16 BIT16 716 #define LPFC_SLI4_INTR17 BIT17 717 #define LPFC_SLI4_INTR18 BIT18 718 #define LPFC_SLI4_INTR19 BIT19 719 #define LPFC_SLI4_INTR20 BIT20 720 #define LPFC_SLI4_INTR21 BIT21 721 #define LPFC_SLI4_INTR22 BIT22 722 #define LPFC_SLI4_INTR23 BIT23 723 #define LPFC_SLI4_INTR24 BIT24 724 #define LPFC_SLI4_INTR25 BIT25 725 #define LPFC_SLI4_INTR26 BIT26 726 #define LPFC_SLI4_INTR27 BIT27 727 #define LPFC_SLI4_INTR28 BIT28 728 #define LPFC_SLI4_INTR29 BIT29 729 #define LPFC_SLI4_INTR30 BIT30 730 #define LPFC_SLI4_INTR31 BIT31 731 732 /* 733 * The Doorbell registers defined here exist in different BAR 734 * register sets depending on the UCNA Port's reported if_type 735 * value. For UCNA ports running SLI4 and if_type 0, they reside in 736 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 737 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 738 * BAR2. The offsets and base address are different, so the driver 739 * has to compute the register addresses accordingly 740 */ 741 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 742 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 743 #define LPFC_IF6_RQ_DOORBELL 0x0080 744 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 745 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 746 #define lpfc_rq_db_list_fm_num_posted_WORD word0 747 #define lpfc_rq_db_list_fm_index_SHIFT 16 748 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 749 #define lpfc_rq_db_list_fm_index_WORD word0 750 #define lpfc_rq_db_list_fm_id_SHIFT 0 751 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 752 #define lpfc_rq_db_list_fm_id_WORD word0 753 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 754 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 755 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 756 #define lpfc_rq_db_ring_fm_id_SHIFT 0 757 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 758 #define lpfc_rq_db_ring_fm_id_WORD word0 759 760 #define LPFC_ULP0_WQ_DOORBELL 0x0040 761 #define LPFC_ULP1_WQ_DOORBELL 0x0060 762 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 763 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 764 #define lpfc_wq_db_list_fm_num_posted_WORD word0 765 #define lpfc_wq_db_list_fm_index_SHIFT 16 766 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 767 #define lpfc_wq_db_list_fm_index_WORD word0 768 #define lpfc_wq_db_list_fm_id_SHIFT 0 769 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 770 #define lpfc_wq_db_list_fm_id_WORD word0 771 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 772 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 773 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 774 #define lpfc_wq_db_ring_fm_id_SHIFT 0 775 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 776 #define lpfc_wq_db_ring_fm_id_WORD word0 777 778 #define LPFC_IF6_WQ_DOORBELL 0x0040 779 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 780 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 781 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 782 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 783 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 784 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 785 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 786 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 787 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 788 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 789 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 790 #define lpfc_if6_wq_db_list_fm_id_WORD word0 791 792 #define LPFC_EQCQ_DOORBELL 0x0120 793 #define lpfc_eqcq_doorbell_se_SHIFT 31 794 #define lpfc_eqcq_doorbell_se_MASK 0x0001 795 #define lpfc_eqcq_doorbell_se_WORD word0 796 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 797 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 798 #define lpfc_eqcq_doorbell_arm_SHIFT 29 799 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 800 #define lpfc_eqcq_doorbell_arm_WORD word0 801 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 802 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 803 #define lpfc_eqcq_doorbell_num_released_WORD word0 804 #define lpfc_eqcq_doorbell_qt_SHIFT 10 805 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 806 #define lpfc_eqcq_doorbell_qt_WORD word0 807 #define LPFC_QUEUE_TYPE_COMPLETION 0 808 #define LPFC_QUEUE_TYPE_EVENT 1 809 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 810 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 811 #define lpfc_eqcq_doorbell_eqci_WORD word0 812 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 813 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 814 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 815 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 816 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 817 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 818 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 819 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 820 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 821 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 822 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 823 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 824 #define LPFC_CQID_HI_FIELD_SHIFT 10 825 #define LPFC_EQID_HI_FIELD_SHIFT 9 826 827 #define LPFC_IF6_CQ_DOORBELL 0x00C0 828 #define lpfc_if6_cq_doorbell_se_SHIFT 31 829 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 830 #define lpfc_if6_cq_doorbell_se_WORD word0 831 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 832 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 833 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 834 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 835 #define lpfc_if6_cq_doorbell_arm_WORD word0 836 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 837 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 838 #define lpfc_if6_cq_doorbell_num_released_WORD word0 839 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 840 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 841 #define lpfc_if6_cq_doorbell_cqid_WORD word0 842 843 #define LPFC_IF6_EQ_DOORBELL 0x0120 844 #define lpfc_if6_eq_doorbell_io_SHIFT 31 845 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 846 #define lpfc_if6_eq_doorbell_io_WORD word0 847 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 848 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 849 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 850 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 851 #define lpfc_if6_eq_doorbell_arm_WORD word0 852 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 853 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 854 #define lpfc_if6_eq_doorbell_num_released_WORD word0 855 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 856 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 857 #define lpfc_if6_eq_doorbell_eqid_WORD word0 858 859 #define LPFC_BMBX 0x0160 860 #define lpfc_bmbx_addr_SHIFT 2 861 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 862 #define lpfc_bmbx_addr_WORD word0 863 #define lpfc_bmbx_hi_SHIFT 1 864 #define lpfc_bmbx_hi_MASK 0x0001 865 #define lpfc_bmbx_hi_WORD word0 866 #define lpfc_bmbx_rdy_SHIFT 0 867 #define lpfc_bmbx_rdy_MASK 0x0001 868 #define lpfc_bmbx_rdy_WORD word0 869 870 #define LPFC_MQ_DOORBELL 0x0140 871 #define LPFC_IF6_MQ_DOORBELL 0x0160 872 #define lpfc_mq_doorbell_num_posted_SHIFT 16 873 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 874 #define lpfc_mq_doorbell_num_posted_WORD word0 875 #define lpfc_mq_doorbell_id_SHIFT 0 876 #define lpfc_mq_doorbell_id_MASK 0xFFFF 877 #define lpfc_mq_doorbell_id_WORD word0 878 879 struct lpfc_sli4_cfg_mhdr { 880 uint32_t word1; 881 #define lpfc_mbox_hdr_emb_SHIFT 0 882 #define lpfc_mbox_hdr_emb_MASK 0x00000001 883 #define lpfc_mbox_hdr_emb_WORD word1 884 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 885 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 886 #define lpfc_mbox_hdr_sge_cnt_WORD word1 887 uint32_t payload_length; 888 uint32_t tag_lo; 889 uint32_t tag_hi; 890 uint32_t reserved5; 891 }; 892 893 union lpfc_sli4_cfg_shdr { 894 struct { 895 uint32_t word6; 896 #define lpfc_mbox_hdr_opcode_SHIFT 0 897 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 898 #define lpfc_mbox_hdr_opcode_WORD word6 899 #define lpfc_mbox_hdr_subsystem_SHIFT 8 900 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 901 #define lpfc_mbox_hdr_subsystem_WORD word6 902 #define lpfc_mbox_hdr_port_number_SHIFT 16 903 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 904 #define lpfc_mbox_hdr_port_number_WORD word6 905 #define lpfc_mbox_hdr_domain_SHIFT 24 906 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 907 #define lpfc_mbox_hdr_domain_WORD word6 908 uint32_t timeout; 909 uint32_t request_length; 910 uint32_t word9; 911 #define lpfc_mbox_hdr_version_SHIFT 0 912 #define lpfc_mbox_hdr_version_MASK 0x000000FF 913 #define lpfc_mbox_hdr_version_WORD word9 914 #define lpfc_mbox_hdr_pf_num_SHIFT 16 915 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 916 #define lpfc_mbox_hdr_pf_num_WORD word9 917 #define lpfc_mbox_hdr_vh_num_SHIFT 24 918 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 919 #define lpfc_mbox_hdr_vh_num_WORD word9 920 #define LPFC_Q_CREATE_VERSION_2 2 921 #define LPFC_Q_CREATE_VERSION_1 1 922 #define LPFC_Q_CREATE_VERSION_0 0 923 #define LPFC_OPCODE_VERSION_0 0 924 #define LPFC_OPCODE_VERSION_1 1 925 } request; 926 struct { 927 uint32_t word6; 928 #define lpfc_mbox_hdr_opcode_SHIFT 0 929 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 930 #define lpfc_mbox_hdr_opcode_WORD word6 931 #define lpfc_mbox_hdr_subsystem_SHIFT 8 932 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 933 #define lpfc_mbox_hdr_subsystem_WORD word6 934 #define lpfc_mbox_hdr_domain_SHIFT 24 935 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 936 #define lpfc_mbox_hdr_domain_WORD word6 937 uint32_t word7; 938 #define lpfc_mbox_hdr_status_SHIFT 0 939 #define lpfc_mbox_hdr_status_MASK 0x000000FF 940 #define lpfc_mbox_hdr_status_WORD word7 941 #define lpfc_mbox_hdr_add_status_SHIFT 8 942 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 943 #define lpfc_mbox_hdr_add_status_WORD word7 944 uint32_t response_length; 945 uint32_t actual_response_length; 946 } response; 947 }; 948 949 /* Mailbox Header structures. 950 * struct mbox_header is defined for first generation SLI4_CFG mailbox 951 * calls deployed for BE-based ports. 952 * 953 * struct sli4_mbox_header is defined for second generation SLI4 954 * ports that don't deploy the SLI4_CFG mechanism. 955 */ 956 struct mbox_header { 957 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 958 union lpfc_sli4_cfg_shdr cfg_shdr; 959 }; 960 961 #define LPFC_EXTENT_LOCAL 0 962 #define LPFC_TIMEOUT_DEFAULT 0 963 #define LPFC_EXTENT_VERSION_DEFAULT 0 964 965 /* Subsystem Definitions */ 966 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 967 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 968 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 969 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 970 971 /* Device Specific Definitions */ 972 973 /* The HOST ENDIAN defines are in Big Endian format. */ 974 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 975 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 976 977 /* Common Opcodes */ 978 #define LPFC_MBOX_OPCODE_NA 0x00 979 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 980 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 981 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 982 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 983 #define LPFC_MBOX_OPCODE_NOP 0x21 984 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 985 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 986 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 987 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 988 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 989 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 990 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 991 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 992 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 993 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 994 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 995 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 996 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 997 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 998 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 999 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1000 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1001 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1002 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1003 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1004 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1005 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1006 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1007 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1008 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1009 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1010 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1011 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1012 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1013 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1014 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1015 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1016 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1017 1018 /* FCoE Opcodes */ 1019 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1020 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1021 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1022 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1023 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1024 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1025 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1026 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1027 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1028 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1029 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1030 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1031 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1032 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1033 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1034 1035 /* Low level Opcodes */ 1036 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1037 1038 /* Mailbox command structures */ 1039 struct eq_context { 1040 uint32_t word0; 1041 #define lpfc_eq_context_size_SHIFT 31 1042 #define lpfc_eq_context_size_MASK 0x00000001 1043 #define lpfc_eq_context_size_WORD word0 1044 #define LPFC_EQE_SIZE_4 0x0 1045 #define LPFC_EQE_SIZE_16 0x1 1046 #define lpfc_eq_context_valid_SHIFT 29 1047 #define lpfc_eq_context_valid_MASK 0x00000001 1048 #define lpfc_eq_context_valid_WORD word0 1049 #define lpfc_eq_context_autovalid_SHIFT 28 1050 #define lpfc_eq_context_autovalid_MASK 0x00000001 1051 #define lpfc_eq_context_autovalid_WORD word0 1052 uint32_t word1; 1053 #define lpfc_eq_context_count_SHIFT 26 1054 #define lpfc_eq_context_count_MASK 0x00000003 1055 #define lpfc_eq_context_count_WORD word1 1056 #define LPFC_EQ_CNT_256 0x0 1057 #define LPFC_EQ_CNT_512 0x1 1058 #define LPFC_EQ_CNT_1024 0x2 1059 #define LPFC_EQ_CNT_2048 0x3 1060 #define LPFC_EQ_CNT_4096 0x4 1061 uint32_t word2; 1062 #define lpfc_eq_context_delay_multi_SHIFT 13 1063 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1064 #define lpfc_eq_context_delay_multi_WORD word2 1065 uint32_t reserved3; 1066 }; 1067 1068 struct eq_delay_info { 1069 uint32_t eq_id; 1070 uint32_t phase; 1071 uint32_t delay_multi; 1072 }; 1073 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1074 1075 struct sgl_page_pairs { 1076 uint32_t sgl_pg0_addr_lo; 1077 uint32_t sgl_pg0_addr_hi; 1078 uint32_t sgl_pg1_addr_lo; 1079 uint32_t sgl_pg1_addr_hi; 1080 }; 1081 1082 struct lpfc_mbx_post_sgl_pages { 1083 struct mbox_header header; 1084 uint32_t word0; 1085 #define lpfc_post_sgl_pages_xri_SHIFT 0 1086 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1087 #define lpfc_post_sgl_pages_xri_WORD word0 1088 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1089 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1090 #define lpfc_post_sgl_pages_xricnt_WORD word0 1091 struct sgl_page_pairs sgl_pg_pairs[1]; 1092 }; 1093 1094 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1095 struct lpfc_mbx_post_uembed_sgl_page1 { 1096 union lpfc_sli4_cfg_shdr cfg_shdr; 1097 uint32_t word0; 1098 struct sgl_page_pairs sgl_pg_pairs; 1099 }; 1100 1101 struct lpfc_mbx_sge { 1102 uint32_t pa_lo; 1103 uint32_t pa_hi; 1104 uint32_t length; 1105 }; 1106 1107 struct lpfc_mbx_nembed_cmd { 1108 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1109 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1110 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1111 }; 1112 1113 struct lpfc_mbx_nembed_sge_virt { 1114 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1115 }; 1116 1117 struct lpfc_mbx_eq_create { 1118 struct mbox_header header; 1119 union { 1120 struct { 1121 uint32_t word0; 1122 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1123 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1124 #define lpfc_mbx_eq_create_num_pages_WORD word0 1125 struct eq_context context; 1126 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1127 } request; 1128 struct { 1129 uint32_t word0; 1130 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1131 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1132 #define lpfc_mbx_eq_create_q_id_WORD word0 1133 } response; 1134 } u; 1135 }; 1136 1137 struct lpfc_mbx_modify_eq_delay { 1138 struct mbox_header header; 1139 union { 1140 struct { 1141 uint32_t num_eq; 1142 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1143 } request; 1144 struct { 1145 uint32_t word0; 1146 } response; 1147 } u; 1148 }; 1149 1150 struct lpfc_mbx_eq_destroy { 1151 struct mbox_header header; 1152 union { 1153 struct { 1154 uint32_t word0; 1155 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1156 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1157 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1158 } request; 1159 struct { 1160 uint32_t word0; 1161 } response; 1162 } u; 1163 }; 1164 1165 struct lpfc_mbx_nop { 1166 struct mbox_header header; 1167 uint32_t context[2]; 1168 }; 1169 1170 1171 1172 struct lpfc_mbx_set_ras_fwlog { 1173 struct mbox_header header; 1174 union { 1175 struct { 1176 uint32_t word4; 1177 #define lpfc_fwlog_enable_SHIFT 0 1178 #define lpfc_fwlog_enable_MASK 0x00000001 1179 #define lpfc_fwlog_enable_WORD word4 1180 #define lpfc_fwlog_loglvl_SHIFT 8 1181 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1182 #define lpfc_fwlog_loglvl_WORD word4 1183 #define lpfc_fwlog_ra_SHIFT 15 1184 #define lpfc_fwlog_ra_WORD 0x00000008 1185 #define lpfc_fwlog_buffcnt_SHIFT 16 1186 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1187 #define lpfc_fwlog_buffcnt_WORD word4 1188 #define lpfc_fwlog_buffsz_SHIFT 24 1189 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1190 #define lpfc_fwlog_buffsz_WORD word4 1191 uint32_t word5; 1192 #define lpfc_fwlog_acqe_SHIFT 0 1193 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1194 #define lpfc_fwlog_acqe_WORD word5 1195 #define lpfc_fwlog_cqid_SHIFT 16 1196 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1197 #define lpfc_fwlog_cqid_WORD word5 1198 #define LPFC_MAX_FWLOG_PAGE 16 1199 struct dma_address lwpd; 1200 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1201 } request; 1202 struct { 1203 uint32_t word0; 1204 } response; 1205 } u; 1206 }; 1207 1208 1209 struct cq_context { 1210 uint32_t word0; 1211 #define lpfc_cq_context_event_SHIFT 31 1212 #define lpfc_cq_context_event_MASK 0x00000001 1213 #define lpfc_cq_context_event_WORD word0 1214 #define lpfc_cq_context_valid_SHIFT 29 1215 #define lpfc_cq_context_valid_MASK 0x00000001 1216 #define lpfc_cq_context_valid_WORD word0 1217 #define lpfc_cq_context_count_SHIFT 27 1218 #define lpfc_cq_context_count_MASK 0x00000003 1219 #define lpfc_cq_context_count_WORD word0 1220 #define LPFC_CQ_CNT_256 0x0 1221 #define LPFC_CQ_CNT_512 0x1 1222 #define LPFC_CQ_CNT_1024 0x2 1223 #define LPFC_CQ_CNT_WORD7 0x3 1224 #define lpfc_cq_context_autovalid_SHIFT 15 1225 #define lpfc_cq_context_autovalid_MASK 0x00000001 1226 #define lpfc_cq_context_autovalid_WORD word0 1227 uint32_t word1; 1228 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1229 #define lpfc_cq_eq_id_MASK 0x000000FF 1230 #define lpfc_cq_eq_id_WORD word1 1231 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1232 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1233 #define lpfc_cq_eq_id_2_WORD word1 1234 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1235 uint32_t reserved1; 1236 }; 1237 1238 struct lpfc_mbx_cq_create { 1239 struct mbox_header header; 1240 union { 1241 struct { 1242 uint32_t word0; 1243 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1244 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1245 #define lpfc_mbx_cq_create_page_size_WORD word0 1246 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1247 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1248 #define lpfc_mbx_cq_create_num_pages_WORD word0 1249 struct cq_context context; 1250 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1251 } request; 1252 struct { 1253 uint32_t word0; 1254 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1255 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1256 #define lpfc_mbx_cq_create_q_id_WORD word0 1257 } response; 1258 } u; 1259 }; 1260 1261 struct lpfc_mbx_cq_create_set { 1262 union lpfc_sli4_cfg_shdr cfg_shdr; 1263 union { 1264 struct { 1265 uint32_t word0; 1266 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1267 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1268 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1269 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1270 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1271 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1272 uint32_t word1; 1273 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1274 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1275 #define lpfc_mbx_cq_create_set_evt_WORD word1 1276 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1277 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1278 #define lpfc_mbx_cq_create_set_valid_WORD word1 1279 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1280 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1281 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1282 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1283 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1284 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1285 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1286 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1287 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1288 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1289 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1290 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1291 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1292 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1293 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1294 uint32_t word2; 1295 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1296 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1297 #define lpfc_mbx_cq_create_set_arm_WORD word2 1298 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1299 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1300 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1301 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1302 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1303 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1304 uint32_t word3; 1305 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1306 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1307 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1308 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1309 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1310 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1311 uint32_t word4; 1312 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1313 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1314 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1315 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1316 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1317 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1318 uint32_t word5; 1319 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1320 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1321 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1322 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1323 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1324 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1325 uint32_t word6; 1326 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1327 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1328 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1329 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1330 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1331 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1332 uint32_t word7; 1333 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1334 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1335 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1336 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1337 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1338 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1339 uint32_t word8; 1340 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1341 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1342 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1343 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1344 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1345 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1346 uint32_t word9; 1347 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1348 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1349 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1350 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1351 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1352 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1353 uint32_t word10; 1354 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1355 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1356 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1357 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1358 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1359 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1360 struct dma_address page[1]; 1361 } request; 1362 struct { 1363 uint32_t word0; 1364 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1365 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1366 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1367 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1368 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1369 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1370 } response; 1371 } u; 1372 }; 1373 1374 struct lpfc_mbx_cq_destroy { 1375 struct mbox_header header; 1376 union { 1377 struct { 1378 uint32_t word0; 1379 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1380 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1381 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1382 } request; 1383 struct { 1384 uint32_t word0; 1385 } response; 1386 } u; 1387 }; 1388 1389 struct wq_context { 1390 uint32_t reserved0; 1391 uint32_t reserved1; 1392 uint32_t reserved2; 1393 uint32_t reserved3; 1394 }; 1395 1396 struct lpfc_mbx_wq_create { 1397 struct mbox_header header; 1398 union { 1399 struct { /* Version 0 Request */ 1400 uint32_t word0; 1401 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1402 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1403 #define lpfc_mbx_wq_create_num_pages_WORD word0 1404 #define lpfc_mbx_wq_create_dua_SHIFT 8 1405 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1406 #define lpfc_mbx_wq_create_dua_WORD word0 1407 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1408 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1409 #define lpfc_mbx_wq_create_cq_id_WORD word0 1410 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1411 uint32_t word9; 1412 #define lpfc_mbx_wq_create_bua_SHIFT 0 1413 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1414 #define lpfc_mbx_wq_create_bua_WORD word9 1415 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1416 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1417 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1418 } request; 1419 struct { /* Version 1 Request */ 1420 uint32_t word0; /* Word 0 is the same as in v0 */ 1421 uint32_t word1; 1422 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1423 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1424 #define lpfc_mbx_wq_create_page_size_WORD word1 1425 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1426 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1427 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1428 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1429 #define lpfc_mbx_wq_create_doe_SHIFT 14 1430 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1431 #define lpfc_mbx_wq_create_doe_WORD word1 1432 #define lpfc_mbx_wq_create_toe_SHIFT 13 1433 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1434 #define lpfc_mbx_wq_create_toe_WORD word1 1435 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1436 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1437 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1438 #define LPFC_WQ_WQE_SIZE_64 0x5 1439 #define LPFC_WQ_WQE_SIZE_128 0x6 1440 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1441 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1442 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1443 uint32_t word2; 1444 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1445 } request_1; 1446 struct { 1447 uint32_t word0; 1448 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1449 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1450 #define lpfc_mbx_wq_create_q_id_WORD word0 1451 uint32_t doorbell_offset; 1452 uint32_t word2; 1453 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1454 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1455 #define lpfc_mbx_wq_create_bar_set_WORD word2 1456 #define WQ_PCI_BAR_0_AND_1 0x00 1457 #define WQ_PCI_BAR_2_AND_3 0x01 1458 #define WQ_PCI_BAR_4_AND_5 0x02 1459 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1460 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1461 #define lpfc_mbx_wq_create_db_format_WORD word2 1462 } response; 1463 struct { 1464 uint32_t word0; 1465 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1466 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1467 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1468 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1469 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1470 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1471 uint32_t word1; 1472 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1473 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1474 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1475 uint32_t doorbell_offset; 1476 uint32_t word3; 1477 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1478 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1479 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1480 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1481 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1482 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1483 uint32_t dpp_offset; 1484 } response_1; 1485 } u; 1486 }; 1487 1488 struct lpfc_mbx_wq_destroy { 1489 struct mbox_header header; 1490 union { 1491 struct { 1492 uint32_t word0; 1493 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1494 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1495 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1496 } request; 1497 struct { 1498 uint32_t word0; 1499 } response; 1500 } u; 1501 }; 1502 1503 #define LPFC_HDR_BUF_SIZE 128 1504 #define LPFC_DATA_BUF_SIZE 2048 1505 #define LPFC_NVMET_DATA_BUF_SIZE 128 1506 struct rq_context { 1507 uint32_t word0; 1508 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1509 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1510 #define lpfc_rq_context_rqe_count_WORD word0 1511 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1512 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1513 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1514 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1515 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1516 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1517 #define lpfc_rq_context_rqe_count_1_WORD word0 1518 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1519 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1520 #define lpfc_rq_context_rqe_size_WORD word0 1521 #define LPFC_RQE_SIZE_8 2 1522 #define LPFC_RQE_SIZE_16 3 1523 #define LPFC_RQE_SIZE_32 4 1524 #define LPFC_RQE_SIZE_64 5 1525 #define LPFC_RQE_SIZE_128 6 1526 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1527 #define lpfc_rq_context_page_size_MASK 0x000000FF 1528 #define lpfc_rq_context_page_size_WORD word0 1529 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1530 uint32_t word1; 1531 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1532 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1533 #define lpfc_rq_context_data_size_WORD word1 1534 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1535 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1536 #define lpfc_rq_context_hdr_size_WORD word1 1537 uint32_t word2; 1538 #define lpfc_rq_context_cq_id_SHIFT 16 1539 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1540 #define lpfc_rq_context_cq_id_WORD word2 1541 #define lpfc_rq_context_buf_size_SHIFT 0 1542 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1543 #define lpfc_rq_context_buf_size_WORD word2 1544 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1545 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1546 #define lpfc_rq_context_base_cq_WORD word2 1547 uint32_t buffer_size; /* Version 1 Only */ 1548 }; 1549 1550 struct lpfc_mbx_rq_create { 1551 struct mbox_header header; 1552 union { 1553 struct { 1554 uint32_t word0; 1555 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1556 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1557 #define lpfc_mbx_rq_create_num_pages_WORD word0 1558 #define lpfc_mbx_rq_create_dua_SHIFT 16 1559 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1560 #define lpfc_mbx_rq_create_dua_WORD word0 1561 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1562 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1563 #define lpfc_mbx_rq_create_bqu_WORD word0 1564 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1565 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1566 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1567 struct rq_context context; 1568 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1569 } request; 1570 struct { 1571 uint32_t word0; 1572 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1573 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1574 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1575 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1576 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1577 #define lpfc_mbx_rq_create_q_id_WORD word0 1578 uint32_t doorbell_offset; 1579 uint32_t word2; 1580 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1581 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1582 #define lpfc_mbx_rq_create_bar_set_WORD word2 1583 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1584 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1585 #define lpfc_mbx_rq_create_db_format_WORD word2 1586 } response; 1587 } u; 1588 }; 1589 1590 struct lpfc_mbx_rq_create_v2 { 1591 union lpfc_sli4_cfg_shdr cfg_shdr; 1592 union { 1593 struct { 1594 uint32_t word0; 1595 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1596 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1597 #define lpfc_mbx_rq_create_num_pages_WORD word0 1598 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1599 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1600 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1601 #define lpfc_mbx_rq_create_dua_SHIFT 16 1602 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1603 #define lpfc_mbx_rq_create_dua_WORD word0 1604 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1605 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1606 #define lpfc_mbx_rq_create_bqu_WORD word0 1607 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1608 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1609 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1610 #define lpfc_mbx_rq_create_dim_SHIFT 29 1611 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1612 #define lpfc_mbx_rq_create_dim_WORD word0 1613 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1614 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1615 #define lpfc_mbx_rq_create_dfd_WORD word0 1616 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1617 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1618 #define lpfc_mbx_rq_create_dnb_WORD word0 1619 struct rq_context context; 1620 struct dma_address page[1]; 1621 } request; 1622 struct { 1623 uint32_t word0; 1624 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1625 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1626 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1627 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1628 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1629 #define lpfc_mbx_rq_create_q_id_WORD word0 1630 uint32_t doorbell_offset; 1631 uint32_t word2; 1632 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1633 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1634 #define lpfc_mbx_rq_create_bar_set_WORD word2 1635 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1636 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1637 #define lpfc_mbx_rq_create_db_format_WORD word2 1638 } response; 1639 } u; 1640 }; 1641 1642 struct lpfc_mbx_rq_destroy { 1643 struct mbox_header header; 1644 union { 1645 struct { 1646 uint32_t word0; 1647 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1648 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1649 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1650 } request; 1651 struct { 1652 uint32_t word0; 1653 } response; 1654 } u; 1655 }; 1656 1657 struct mq_context { 1658 uint32_t word0; 1659 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1660 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1661 #define lpfc_mq_context_cq_id_WORD word0 1662 #define lpfc_mq_context_ring_size_SHIFT 16 1663 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1664 #define lpfc_mq_context_ring_size_WORD word0 1665 #define LPFC_MQ_RING_SIZE_16 0x5 1666 #define LPFC_MQ_RING_SIZE_32 0x6 1667 #define LPFC_MQ_RING_SIZE_64 0x7 1668 #define LPFC_MQ_RING_SIZE_128 0x8 1669 uint32_t word1; 1670 #define lpfc_mq_context_valid_SHIFT 31 1671 #define lpfc_mq_context_valid_MASK 0x00000001 1672 #define lpfc_mq_context_valid_WORD word1 1673 uint32_t reserved2; 1674 uint32_t reserved3; 1675 }; 1676 1677 struct lpfc_mbx_mq_create { 1678 struct mbox_header header; 1679 union { 1680 struct { 1681 uint32_t word0; 1682 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1683 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1684 #define lpfc_mbx_mq_create_num_pages_WORD word0 1685 struct mq_context context; 1686 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1687 } request; 1688 struct { 1689 uint32_t word0; 1690 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1691 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1692 #define lpfc_mbx_mq_create_q_id_WORD word0 1693 } response; 1694 } u; 1695 }; 1696 1697 struct lpfc_mbx_mq_create_ext { 1698 struct mbox_header header; 1699 union { 1700 struct { 1701 uint32_t word0; 1702 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1703 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1704 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1705 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1706 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1707 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1708 uint32_t async_evt_bmap; 1709 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1710 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1711 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1712 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1713 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1714 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1715 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1716 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1717 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1718 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1719 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1720 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1721 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1722 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1723 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1724 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1725 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1726 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1727 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1728 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1729 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1730 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1731 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1732 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1733 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1734 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1735 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1736 struct mq_context context; 1737 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1738 } request; 1739 struct { 1740 uint32_t word0; 1741 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1742 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1743 #define lpfc_mbx_mq_create_q_id_WORD word0 1744 } response; 1745 } u; 1746 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1747 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1748 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1749 }; 1750 1751 struct lpfc_mbx_mq_destroy { 1752 struct mbox_header header; 1753 union { 1754 struct { 1755 uint32_t word0; 1756 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1757 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1758 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1759 } request; 1760 struct { 1761 uint32_t word0; 1762 } response; 1763 } u; 1764 }; 1765 1766 /* Start Gen 2 SLI4 Mailbox definitions: */ 1767 1768 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1769 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1770 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1771 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1772 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1773 1774 struct lpfc_mbx_get_rsrc_extent_info { 1775 struct mbox_header header; 1776 union { 1777 struct { 1778 uint32_t word4; 1779 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1780 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1781 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1782 } req; 1783 struct { 1784 uint32_t word4; 1785 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1786 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1787 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1788 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1789 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1790 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1791 } rsp; 1792 } u; 1793 }; 1794 1795 struct lpfc_mbx_query_fw_config { 1796 struct mbox_header header; 1797 struct { 1798 uint32_t config_number; 1799 #define LPFC_FC_FCOE 0x00000007 1800 uint32_t asic_revision; 1801 uint32_t physical_port; 1802 uint32_t function_mode; 1803 #define LPFC_FCOE_INI_MODE 0x00000040 1804 #define LPFC_FCOE_TGT_MODE 0x00000080 1805 #define LPFC_DUA_MODE 0x00000800 1806 uint32_t ulp0_mode; 1807 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1808 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1809 uint32_t ulp0_nap_words[12]; 1810 uint32_t ulp1_mode; 1811 uint32_t ulp1_nap_words[12]; 1812 uint32_t function_capabilities; 1813 uint32_t cqid_base; 1814 uint32_t cqid_tot; 1815 uint32_t eqid_base; 1816 uint32_t eqid_tot; 1817 uint32_t ulp0_nap2_words[2]; 1818 uint32_t ulp1_nap2_words[2]; 1819 } rsp; 1820 }; 1821 1822 struct lpfc_mbx_set_beacon_config { 1823 struct mbox_header header; 1824 uint32_t word4; 1825 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1826 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1827 #define lpfc_mbx_set_beacon_port_num_WORD word4 1828 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1829 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1830 #define lpfc_mbx_set_beacon_port_type_WORD word4 1831 #define lpfc_mbx_set_beacon_state_SHIFT 8 1832 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1833 #define lpfc_mbx_set_beacon_state_WORD word4 1834 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1835 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1836 #define lpfc_mbx_set_beacon_duration_WORD word4 1837 1838 /* COMMON_SET_BEACON_CONFIG_V1 */ 1839 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1840 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1841 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1842 uint32_t word5; /* RESERVED */ 1843 }; 1844 1845 struct lpfc_id_range { 1846 uint32_t word5; 1847 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1848 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1849 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1850 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1851 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1852 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1853 }; 1854 1855 struct lpfc_mbx_set_link_diag_state { 1856 struct mbox_header header; 1857 union { 1858 struct { 1859 uint32_t word0; 1860 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1861 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1862 #define lpfc_mbx_set_diag_state_diag_WORD word0 1863 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1864 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1865 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1866 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1867 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1868 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1869 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1870 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1871 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1872 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1873 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1874 } req; 1875 struct { 1876 uint32_t word0; 1877 } rsp; 1878 } u; 1879 }; 1880 1881 struct lpfc_mbx_set_link_diag_loopback { 1882 struct mbox_header header; 1883 union { 1884 struct { 1885 uint32_t word0; 1886 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1887 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1888 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1889 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1890 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1891 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1892 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1893 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1894 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1895 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1896 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1897 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1898 } req; 1899 struct { 1900 uint32_t word0; 1901 } rsp; 1902 } u; 1903 }; 1904 1905 struct lpfc_mbx_run_link_diag_test { 1906 struct mbox_header header; 1907 union { 1908 struct { 1909 uint32_t word0; 1910 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1911 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1912 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1913 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1914 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1915 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1916 uint32_t word1; 1917 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1918 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1919 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1920 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1921 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1922 #define lpfc_mbx_run_diag_test_loops_WORD word1 1923 uint32_t word2; 1924 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1925 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1926 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1927 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1928 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1929 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1930 } req; 1931 struct { 1932 uint32_t word0; 1933 } rsp; 1934 } u; 1935 }; 1936 1937 /* 1938 * struct lpfc_mbx_alloc_rsrc_extents: 1939 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1940 * 6 words of header + 4 words of shared subcommand header + 1941 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1942 * 1943 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1944 * for extents payload. 1945 * 1946 * 212/2 (bytes per extent) = 106 extents. 1947 * 106/2 (extents per word) = 53 words. 1948 * lpfc_id_range id is statically size to 53. 1949 * 1950 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1951 * extent ranges. For ALLOC, the type and cnt are required. 1952 * For GET_ALLOCATED, only the type is required. 1953 */ 1954 struct lpfc_mbx_alloc_rsrc_extents { 1955 struct mbox_header header; 1956 union { 1957 struct { 1958 uint32_t word4; 1959 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1960 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1961 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1962 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1963 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1964 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1965 } req; 1966 struct { 1967 uint32_t word4; 1968 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1969 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1970 #define lpfc_mbx_rsrc_cnt_WORD word4 1971 struct lpfc_id_range id[53]; 1972 } rsp; 1973 } u; 1974 }; 1975 1976 /* 1977 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1978 * structure shares the same SHIFT/MASK/WORD defines provided in the 1979 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1980 * the structures defined above. This non-embedded structure provides for the 1981 * maximum number of extents supported by the port. 1982 */ 1983 struct lpfc_mbx_nembed_rsrc_extent { 1984 union lpfc_sli4_cfg_shdr cfg_shdr; 1985 uint32_t word4; 1986 struct lpfc_id_range id; 1987 }; 1988 1989 struct lpfc_mbx_dealloc_rsrc_extents { 1990 struct mbox_header header; 1991 struct { 1992 uint32_t word4; 1993 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1994 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1995 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1996 } req; 1997 1998 }; 1999 2000 /* Start SLI4 FCoE specific mbox structures. */ 2001 2002 struct lpfc_mbx_post_hdr_tmpl { 2003 struct mbox_header header; 2004 uint32_t word10; 2005 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2006 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2007 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2008 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2009 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2010 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2011 uint32_t rpi_paddr_lo; 2012 uint32_t rpi_paddr_hi; 2013 }; 2014 2015 struct sli4_sge { /* SLI-4 */ 2016 uint32_t addr_hi; 2017 uint32_t addr_lo; 2018 2019 uint32_t word2; 2020 #define lpfc_sli4_sge_offset_SHIFT 0 2021 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2022 #define lpfc_sli4_sge_offset_WORD word2 2023 #define lpfc_sli4_sge_type_SHIFT 27 2024 #define lpfc_sli4_sge_type_MASK 0x0000000F 2025 #define lpfc_sli4_sge_type_WORD word2 2026 #define LPFC_SGE_TYPE_DATA 0x0 2027 #define LPFC_SGE_TYPE_DIF 0x4 2028 #define LPFC_SGE_TYPE_LSP 0x5 2029 #define LPFC_SGE_TYPE_PEDIF 0x6 2030 #define LPFC_SGE_TYPE_PESEED 0x7 2031 #define LPFC_SGE_TYPE_DISEED 0x8 2032 #define LPFC_SGE_TYPE_ENC 0x9 2033 #define LPFC_SGE_TYPE_ATM 0xA 2034 #define LPFC_SGE_TYPE_SKIP 0xC 2035 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2036 #define lpfc_sli4_sge_last_MASK 0x00000001 2037 #define lpfc_sli4_sge_last_WORD word2 2038 uint32_t sge_len; 2039 }; 2040 2041 struct sli4_sge_diseed { /* SLI-4 */ 2042 uint32_t ref_tag; 2043 uint32_t ref_tag_tran; 2044 2045 uint32_t word2; 2046 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2047 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2048 #define lpfc_sli4_sge_dif_apptran_WORD word2 2049 #define lpfc_sli4_sge_dif_af_SHIFT 24 2050 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2051 #define lpfc_sli4_sge_dif_af_WORD word2 2052 #define lpfc_sli4_sge_dif_na_SHIFT 25 2053 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2054 #define lpfc_sli4_sge_dif_na_WORD word2 2055 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2056 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2057 #define lpfc_sli4_sge_dif_hi_WORD word2 2058 #define lpfc_sli4_sge_dif_type_SHIFT 27 2059 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2060 #define lpfc_sli4_sge_dif_type_WORD word2 2061 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2062 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2063 #define lpfc_sli4_sge_dif_last_WORD word2 2064 uint32_t word3; 2065 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2066 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2067 #define lpfc_sli4_sge_dif_apptag_WORD word3 2068 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2069 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2070 #define lpfc_sli4_sge_dif_bs_WORD word3 2071 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2072 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2073 #define lpfc_sli4_sge_dif_ai_WORD word3 2074 #define lpfc_sli4_sge_dif_me_SHIFT 20 2075 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2076 #define lpfc_sli4_sge_dif_me_WORD word3 2077 #define lpfc_sli4_sge_dif_re_SHIFT 21 2078 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2079 #define lpfc_sli4_sge_dif_re_WORD word3 2080 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2081 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2082 #define lpfc_sli4_sge_dif_ce_WORD word3 2083 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2084 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2085 #define lpfc_sli4_sge_dif_nr_WORD word3 2086 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2087 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2088 #define lpfc_sli4_sge_dif_oprx_WORD word3 2089 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2090 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2091 #define lpfc_sli4_sge_dif_optx_WORD word3 2092 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2093 }; 2094 2095 struct fcf_record { 2096 uint32_t max_rcv_size; 2097 uint32_t fka_adv_period; 2098 uint32_t fip_priority; 2099 uint32_t word3; 2100 #define lpfc_fcf_record_mac_0_SHIFT 0 2101 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2102 #define lpfc_fcf_record_mac_0_WORD word3 2103 #define lpfc_fcf_record_mac_1_SHIFT 8 2104 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2105 #define lpfc_fcf_record_mac_1_WORD word3 2106 #define lpfc_fcf_record_mac_2_SHIFT 16 2107 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2108 #define lpfc_fcf_record_mac_2_WORD word3 2109 #define lpfc_fcf_record_mac_3_SHIFT 24 2110 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2111 #define lpfc_fcf_record_mac_3_WORD word3 2112 uint32_t word4; 2113 #define lpfc_fcf_record_mac_4_SHIFT 0 2114 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2115 #define lpfc_fcf_record_mac_4_WORD word4 2116 #define lpfc_fcf_record_mac_5_SHIFT 8 2117 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2118 #define lpfc_fcf_record_mac_5_WORD word4 2119 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2120 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2121 #define lpfc_fcf_record_fcf_avail_WORD word4 2122 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2123 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2124 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2125 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2126 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2127 uint32_t word5; 2128 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2129 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2130 #define lpfc_fcf_record_fab_name_0_WORD word5 2131 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2132 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2133 #define lpfc_fcf_record_fab_name_1_WORD word5 2134 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2135 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2136 #define lpfc_fcf_record_fab_name_2_WORD word5 2137 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2138 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2139 #define lpfc_fcf_record_fab_name_3_WORD word5 2140 uint32_t word6; 2141 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2142 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2143 #define lpfc_fcf_record_fab_name_4_WORD word6 2144 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2145 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2146 #define lpfc_fcf_record_fab_name_5_WORD word6 2147 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2148 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2149 #define lpfc_fcf_record_fab_name_6_WORD word6 2150 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2151 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2152 #define lpfc_fcf_record_fab_name_7_WORD word6 2153 uint32_t word7; 2154 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2155 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2156 #define lpfc_fcf_record_fc_map_0_WORD word7 2157 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2158 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2159 #define lpfc_fcf_record_fc_map_1_WORD word7 2160 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2161 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2162 #define lpfc_fcf_record_fc_map_2_WORD word7 2163 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2164 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2165 #define lpfc_fcf_record_fcf_valid_WORD word7 2166 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2167 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2168 #define lpfc_fcf_record_fcf_fc_WORD word7 2169 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2170 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2171 #define lpfc_fcf_record_fcf_sol_WORD word7 2172 uint32_t word8; 2173 #define lpfc_fcf_record_fcf_index_SHIFT 0 2174 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2175 #define lpfc_fcf_record_fcf_index_WORD word8 2176 #define lpfc_fcf_record_fcf_state_SHIFT 16 2177 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2178 #define lpfc_fcf_record_fcf_state_WORD word8 2179 uint8_t vlan_bitmap[512]; 2180 uint32_t word137; 2181 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2182 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2183 #define lpfc_fcf_record_switch_name_0_WORD word137 2184 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2185 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2186 #define lpfc_fcf_record_switch_name_1_WORD word137 2187 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2188 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2189 #define lpfc_fcf_record_switch_name_2_WORD word137 2190 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2191 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2192 #define lpfc_fcf_record_switch_name_3_WORD word137 2193 uint32_t word138; 2194 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2195 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2196 #define lpfc_fcf_record_switch_name_4_WORD word138 2197 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2198 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2199 #define lpfc_fcf_record_switch_name_5_WORD word138 2200 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2201 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2202 #define lpfc_fcf_record_switch_name_6_WORD word138 2203 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2204 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2205 #define lpfc_fcf_record_switch_name_7_WORD word138 2206 }; 2207 2208 struct lpfc_mbx_read_fcf_tbl { 2209 union lpfc_sli4_cfg_shdr cfg_shdr; 2210 union { 2211 struct { 2212 uint32_t word10; 2213 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2214 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2215 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2216 } request; 2217 struct { 2218 uint32_t eventag; 2219 } response; 2220 } u; 2221 uint32_t word11; 2222 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2223 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2224 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2225 }; 2226 2227 struct lpfc_mbx_add_fcf_tbl_entry { 2228 union lpfc_sli4_cfg_shdr cfg_shdr; 2229 uint32_t word10; 2230 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2231 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2232 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2233 struct lpfc_mbx_sge fcf_sge; 2234 }; 2235 2236 struct lpfc_mbx_del_fcf_tbl_entry { 2237 struct mbox_header header; 2238 uint32_t word10; 2239 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2240 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2241 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2242 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2243 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2244 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2245 }; 2246 2247 struct lpfc_mbx_redisc_fcf_tbl { 2248 struct mbox_header header; 2249 uint32_t word10; 2250 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2251 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2252 #define lpfc_mbx_redisc_fcf_count_WORD word10 2253 uint32_t resvd; 2254 uint32_t word12; 2255 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2256 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2257 #define lpfc_mbx_redisc_fcf_index_WORD word12 2258 }; 2259 2260 /* Status field for embedded SLI_CONFIG mailbox command */ 2261 #define STATUS_SUCCESS 0x0 2262 #define STATUS_FAILED 0x1 2263 #define STATUS_ILLEGAL_REQUEST 0x2 2264 #define STATUS_ILLEGAL_FIELD 0x3 2265 #define STATUS_INSUFFICIENT_BUFFER 0x4 2266 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2267 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2268 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2269 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2270 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2271 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2272 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2273 #define STATUS_ASSERT_FAILED 0x1e 2274 #define STATUS_INVALID_SESSION 0x1f 2275 #define STATUS_INVALID_CONNECTION 0x20 2276 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2277 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2278 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2279 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2280 #define STATUS_FLASHROM_READ_FAILED 0x27 2281 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2282 #define STATUS_ERROR_ACITMAIN 0x2a 2283 #define STATUS_REBOOT_REQUIRED 0x2c 2284 #define STATUS_FCF_IN_USE 0x3a 2285 #define STATUS_FCF_TABLE_EMPTY 0x43 2286 2287 /* 2288 * Additional status field for embedded SLI_CONFIG mailbox 2289 * command. 2290 */ 2291 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2292 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2293 #define ADD_STATUS_INVALID_REQUEST 0x4B 2294 2295 struct lpfc_mbx_sli4_config { 2296 struct mbox_header header; 2297 }; 2298 2299 struct lpfc_mbx_init_vfi { 2300 uint32_t word1; 2301 #define lpfc_init_vfi_vr_SHIFT 31 2302 #define lpfc_init_vfi_vr_MASK 0x00000001 2303 #define lpfc_init_vfi_vr_WORD word1 2304 #define lpfc_init_vfi_vt_SHIFT 30 2305 #define lpfc_init_vfi_vt_MASK 0x00000001 2306 #define lpfc_init_vfi_vt_WORD word1 2307 #define lpfc_init_vfi_vf_SHIFT 29 2308 #define lpfc_init_vfi_vf_MASK 0x00000001 2309 #define lpfc_init_vfi_vf_WORD word1 2310 #define lpfc_init_vfi_vp_SHIFT 28 2311 #define lpfc_init_vfi_vp_MASK 0x00000001 2312 #define lpfc_init_vfi_vp_WORD word1 2313 #define lpfc_init_vfi_vfi_SHIFT 0 2314 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2315 #define lpfc_init_vfi_vfi_WORD word1 2316 uint32_t word2; 2317 #define lpfc_init_vfi_vpi_SHIFT 16 2318 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2319 #define lpfc_init_vfi_vpi_WORD word2 2320 #define lpfc_init_vfi_fcfi_SHIFT 0 2321 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2322 #define lpfc_init_vfi_fcfi_WORD word2 2323 uint32_t word3; 2324 #define lpfc_init_vfi_pri_SHIFT 13 2325 #define lpfc_init_vfi_pri_MASK 0x00000007 2326 #define lpfc_init_vfi_pri_WORD word3 2327 #define lpfc_init_vfi_vf_id_SHIFT 1 2328 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2329 #define lpfc_init_vfi_vf_id_WORD word3 2330 uint32_t word4; 2331 #define lpfc_init_vfi_hop_count_SHIFT 24 2332 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2333 #define lpfc_init_vfi_hop_count_WORD word4 2334 }; 2335 #define MBX_VFI_IN_USE 0x9F02 2336 2337 2338 struct lpfc_mbx_reg_vfi { 2339 uint32_t word1; 2340 #define lpfc_reg_vfi_upd_SHIFT 29 2341 #define lpfc_reg_vfi_upd_MASK 0x00000001 2342 #define lpfc_reg_vfi_upd_WORD word1 2343 #define lpfc_reg_vfi_vp_SHIFT 28 2344 #define lpfc_reg_vfi_vp_MASK 0x00000001 2345 #define lpfc_reg_vfi_vp_WORD word1 2346 #define lpfc_reg_vfi_vfi_SHIFT 0 2347 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2348 #define lpfc_reg_vfi_vfi_WORD word1 2349 uint32_t word2; 2350 #define lpfc_reg_vfi_vpi_SHIFT 16 2351 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2352 #define lpfc_reg_vfi_vpi_WORD word2 2353 #define lpfc_reg_vfi_fcfi_SHIFT 0 2354 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2355 #define lpfc_reg_vfi_fcfi_WORD word2 2356 uint32_t wwn[2]; 2357 struct ulp_bde64 bde; 2358 uint32_t e_d_tov; 2359 uint32_t r_a_tov; 2360 uint32_t word10; 2361 #define lpfc_reg_vfi_nport_id_SHIFT 0 2362 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2363 #define lpfc_reg_vfi_nport_id_WORD word10 2364 #define lpfc_reg_vfi_bbcr_SHIFT 27 2365 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2366 #define lpfc_reg_vfi_bbcr_WORD word10 2367 #define lpfc_reg_vfi_bbscn_SHIFT 28 2368 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2369 #define lpfc_reg_vfi_bbscn_WORD word10 2370 }; 2371 2372 struct lpfc_mbx_init_vpi { 2373 uint32_t word1; 2374 #define lpfc_init_vpi_vfi_SHIFT 16 2375 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2376 #define lpfc_init_vpi_vfi_WORD word1 2377 #define lpfc_init_vpi_vpi_SHIFT 0 2378 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2379 #define lpfc_init_vpi_vpi_WORD word1 2380 }; 2381 2382 struct lpfc_mbx_read_vpi { 2383 uint32_t word1_rsvd; 2384 uint32_t word2; 2385 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2386 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2387 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2388 uint32_t word3_rsvd; 2389 uint32_t word4; 2390 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2391 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2392 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2393 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2394 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2395 #define lpfc_mbx_read_vpi_pb_WORD word4 2396 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2397 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2398 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2399 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2400 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2401 #define lpfc_mbx_read_vpi_ns_WORD word4 2402 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2403 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2404 #define lpfc_mbx_read_vpi_hl_WORD word4 2405 uint32_t word5_rsvd; 2406 uint32_t word6; 2407 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2408 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2409 #define lpfc_mbx_read_vpi_vpi_WORD word6 2410 uint32_t word7; 2411 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2412 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2413 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2414 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2415 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2416 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2417 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2418 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2419 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2420 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2421 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2422 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2423 uint32_t word8; 2424 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2425 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2426 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2427 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2428 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2429 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2430 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2431 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2432 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2433 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2434 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2435 #define lpfc_mbx_read_vpi_vv_WORD word8 2436 }; 2437 2438 struct lpfc_mbx_unreg_vfi { 2439 uint32_t word1_rsvd; 2440 uint32_t word2; 2441 #define lpfc_unreg_vfi_vfi_SHIFT 0 2442 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2443 #define lpfc_unreg_vfi_vfi_WORD word2 2444 }; 2445 2446 struct lpfc_mbx_resume_rpi { 2447 uint32_t word1; 2448 #define lpfc_resume_rpi_index_SHIFT 0 2449 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2450 #define lpfc_resume_rpi_index_WORD word1 2451 #define lpfc_resume_rpi_ii_SHIFT 30 2452 #define lpfc_resume_rpi_ii_MASK 0x00000003 2453 #define lpfc_resume_rpi_ii_WORD word1 2454 #define RESUME_INDEX_RPI 0 2455 #define RESUME_INDEX_VPI 1 2456 #define RESUME_INDEX_VFI 2 2457 #define RESUME_INDEX_FCFI 3 2458 uint32_t event_tag; 2459 }; 2460 2461 #define REG_FCF_INVALID_QID 0xFFFF 2462 struct lpfc_mbx_reg_fcfi { 2463 uint32_t word1; 2464 #define lpfc_reg_fcfi_info_index_SHIFT 0 2465 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2466 #define lpfc_reg_fcfi_info_index_WORD word1 2467 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2468 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2469 #define lpfc_reg_fcfi_fcfi_WORD word1 2470 uint32_t word2; 2471 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2472 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2473 #define lpfc_reg_fcfi_rq_id1_WORD word2 2474 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2475 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2476 #define lpfc_reg_fcfi_rq_id0_WORD word2 2477 uint32_t word3; 2478 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2479 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2480 #define lpfc_reg_fcfi_rq_id3_WORD word3 2481 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2482 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2483 #define lpfc_reg_fcfi_rq_id2_WORD word3 2484 uint32_t word4; 2485 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2486 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2487 #define lpfc_reg_fcfi_type_match0_WORD word4 2488 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2489 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2490 #define lpfc_reg_fcfi_type_mask0_WORD word4 2491 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2492 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2493 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2494 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2495 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2496 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2497 uint32_t word5; 2498 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2499 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2500 #define lpfc_reg_fcfi_type_match1_WORD word5 2501 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2502 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2503 #define lpfc_reg_fcfi_type_mask1_WORD word5 2504 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2505 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2506 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2507 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2508 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2509 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2510 uint32_t word6; 2511 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2512 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2513 #define lpfc_reg_fcfi_type_match2_WORD word6 2514 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2515 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2516 #define lpfc_reg_fcfi_type_mask2_WORD word6 2517 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2518 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2519 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2520 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2521 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2522 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2523 uint32_t word7; 2524 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2525 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2526 #define lpfc_reg_fcfi_type_match3_WORD word7 2527 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2528 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2529 #define lpfc_reg_fcfi_type_mask3_WORD word7 2530 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2531 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2532 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2533 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2534 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2535 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2536 uint32_t word8; 2537 #define lpfc_reg_fcfi_mam_SHIFT 13 2538 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2539 #define lpfc_reg_fcfi_mam_WORD word8 2540 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2541 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2542 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2543 #define lpfc_reg_fcfi_vv_SHIFT 12 2544 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2545 #define lpfc_reg_fcfi_vv_WORD word8 2546 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2547 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2548 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2549 }; 2550 2551 struct lpfc_mbx_reg_fcfi_mrq { 2552 uint32_t word1; 2553 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2554 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2555 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2556 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2557 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2558 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2559 uint32_t word2; 2560 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2561 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2562 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2563 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2564 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2565 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2566 uint32_t word3; 2567 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2568 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2569 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2570 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2571 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2572 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2573 uint32_t word4; 2574 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2575 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2576 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2577 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2578 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2579 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2580 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2581 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2582 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2583 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2584 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2585 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2586 uint32_t word5; 2587 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2588 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2589 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2590 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2591 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2592 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2593 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2594 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2595 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2596 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2597 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2598 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2599 uint32_t word6; 2600 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2601 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2602 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2603 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2604 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2605 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2606 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2607 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2608 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2609 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2610 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2611 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2612 uint32_t word7; 2613 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2614 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2615 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2616 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2617 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2618 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2619 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2620 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2621 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2622 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2623 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2624 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2625 uint32_t word8; 2626 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2627 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2628 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2629 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2630 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2631 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2632 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2633 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2634 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2635 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2636 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2637 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2638 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2639 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2640 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2641 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2642 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2643 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2644 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2645 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2646 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2647 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2648 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2649 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2650 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2651 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2652 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2653 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2654 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2655 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2656 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2657 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2658 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2659 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2660 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2661 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2662 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2663 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2664 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2665 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2666 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2667 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2668 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2669 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2670 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2671 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2672 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2673 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2674 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2675 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2676 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2677 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2678 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2679 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2680 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2681 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2682 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2683 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2684 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2685 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2686 uint32_t word9; 2687 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2688 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2689 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2690 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2691 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2692 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2693 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2694 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2695 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2696 uint32_t word10; 2697 uint32_t word11; 2698 uint32_t word12; 2699 uint32_t word13; 2700 uint32_t word14; 2701 uint32_t word15; 2702 uint32_t word16; 2703 }; 2704 2705 struct lpfc_mbx_unreg_fcfi { 2706 uint32_t word1_rsv; 2707 uint32_t word2; 2708 #define lpfc_unreg_fcfi_SHIFT 0 2709 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2710 #define lpfc_unreg_fcfi_WORD word2 2711 }; 2712 2713 struct lpfc_mbx_read_rev { 2714 uint32_t word1; 2715 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2716 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2717 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2718 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2719 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2720 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2721 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2722 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2723 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2724 #define LPFC_PREDCBX_CEE_MODE 0 2725 #define LPFC_DCBX_CEE_MODE 1 2726 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2727 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2728 #define lpfc_mbx_rd_rev_vpd_WORD word1 2729 uint32_t first_hw_rev; 2730 #define LPFC_G7_ASIC_1 0xd 2731 uint32_t second_hw_rev; 2732 uint32_t word4_rsvd; 2733 uint32_t third_hw_rev; 2734 uint32_t word6; 2735 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2736 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2737 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2738 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2739 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2740 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2741 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2742 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2743 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2744 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2745 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2746 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2747 uint32_t word7_rsvd; 2748 uint32_t fw_id_rev; 2749 uint8_t fw_name[16]; 2750 uint32_t ulp_fw_id_rev; 2751 uint8_t ulp_fw_name[16]; 2752 uint32_t word18_47_rsvd[30]; 2753 uint32_t word48; 2754 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2755 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2756 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2757 uint32_t vpd_paddr_low; 2758 uint32_t vpd_paddr_high; 2759 uint32_t avail_vpd_len; 2760 uint32_t rsvd_52_63[12]; 2761 }; 2762 2763 struct lpfc_mbx_read_config { 2764 uint32_t word1; 2765 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2766 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2767 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2768 uint32_t word2; 2769 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2770 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2771 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2772 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2773 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2774 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2775 #define LPFC_LNK_TYPE_GE 0 2776 #define LPFC_LNK_TYPE_FC 1 2777 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2778 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2779 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2780 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2781 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2782 #define lpfc_mbx_rd_conf_topology_WORD word2 2783 uint32_t rsvd_3; 2784 uint32_t word4; 2785 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2786 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2787 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2788 uint32_t rsvd_5; 2789 uint32_t word6; 2790 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2791 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2792 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2793 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2794 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2795 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2796 uint32_t rsvd_7; 2797 uint32_t word8; 2798 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2799 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2800 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2801 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2802 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2803 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2804 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2805 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2806 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2807 uint32_t word9; 2808 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2809 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2810 #define lpfc_mbx_rd_conf_lmt_WORD word9 2811 uint32_t rsvd_10; 2812 uint32_t rsvd_11; 2813 uint32_t word12; 2814 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2815 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2816 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2817 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2818 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2819 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2820 uint32_t word13; 2821 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2822 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2823 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2824 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2825 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2826 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2827 uint32_t word14; 2828 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2829 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2830 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2831 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2832 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2833 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2834 uint32_t word15; 2835 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2836 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2837 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2838 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2839 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2840 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2841 uint32_t word16; 2842 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2843 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2844 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2845 uint32_t word17; 2846 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2847 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2848 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2849 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2850 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2851 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2852 uint32_t word18; 2853 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2854 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2855 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2856 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2857 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2858 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2859 }; 2860 2861 struct lpfc_mbx_request_features { 2862 uint32_t word1; 2863 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2864 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2865 #define lpfc_mbx_rq_ftr_qry_WORD word1 2866 uint32_t word2; 2867 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2868 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2869 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2870 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2871 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2872 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2873 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2874 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2875 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2876 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2877 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2878 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2879 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2880 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2881 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2882 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2883 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2884 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2885 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2886 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2887 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2888 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2889 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2890 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2891 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2892 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2893 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2894 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2895 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2896 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2897 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2898 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2899 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2900 uint32_t word3; 2901 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2902 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2903 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2904 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2905 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2906 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2907 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2908 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2909 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2910 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2911 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2912 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2913 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2914 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2915 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2916 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2917 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2918 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2919 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2920 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2921 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2922 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2923 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2924 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2925 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2926 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2927 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2928 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2929 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2930 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2931 }; 2932 2933 struct lpfc_mbx_supp_pages { 2934 uint32_t word1; 2935 #define qs_SHIFT 0 2936 #define qs_MASK 0x00000001 2937 #define qs_WORD word1 2938 #define wr_SHIFT 1 2939 #define wr_MASK 0x00000001 2940 #define wr_WORD word1 2941 #define pf_SHIFT 8 2942 #define pf_MASK 0x000000ff 2943 #define pf_WORD word1 2944 #define cpn_SHIFT 16 2945 #define cpn_MASK 0x000000ff 2946 #define cpn_WORD word1 2947 uint32_t word2; 2948 #define list_offset_SHIFT 0 2949 #define list_offset_MASK 0x000000ff 2950 #define list_offset_WORD word2 2951 #define next_offset_SHIFT 8 2952 #define next_offset_MASK 0x000000ff 2953 #define next_offset_WORD word2 2954 #define elem_cnt_SHIFT 16 2955 #define elem_cnt_MASK 0x000000ff 2956 #define elem_cnt_WORD word2 2957 uint32_t word3; 2958 #define pn_0_SHIFT 24 2959 #define pn_0_MASK 0x000000ff 2960 #define pn_0_WORD word3 2961 #define pn_1_SHIFT 16 2962 #define pn_1_MASK 0x000000ff 2963 #define pn_1_WORD word3 2964 #define pn_2_SHIFT 8 2965 #define pn_2_MASK 0x000000ff 2966 #define pn_2_WORD word3 2967 #define pn_3_SHIFT 0 2968 #define pn_3_MASK 0x000000ff 2969 #define pn_3_WORD word3 2970 uint32_t word4; 2971 #define pn_4_SHIFT 24 2972 #define pn_4_MASK 0x000000ff 2973 #define pn_4_WORD word4 2974 #define pn_5_SHIFT 16 2975 #define pn_5_MASK 0x000000ff 2976 #define pn_5_WORD word4 2977 #define pn_6_SHIFT 8 2978 #define pn_6_MASK 0x000000ff 2979 #define pn_6_WORD word4 2980 #define pn_7_SHIFT 0 2981 #define pn_7_MASK 0x000000ff 2982 #define pn_7_WORD word4 2983 uint32_t rsvd[27]; 2984 #define LPFC_SUPP_PAGES 0 2985 #define LPFC_BLOCK_GUARD_PROFILES 1 2986 #define LPFC_SLI4_PARAMETERS 2 2987 }; 2988 2989 struct lpfc_mbx_memory_dump_type3 { 2990 uint32_t word1; 2991 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2992 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2993 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2994 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2995 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2996 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2997 uint32_t word2; 2998 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2999 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3000 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3001 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3002 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3003 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3004 uint32_t word3; 3005 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3006 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3007 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3008 uint32_t addr_lo; 3009 uint32_t addr_hi; 3010 uint32_t return_len; 3011 }; 3012 3013 #define DMP_PAGE_A0 0xa0 3014 #define DMP_PAGE_A2 0xa2 3015 #define DMP_SFF_PAGE_A0_SIZE 256 3016 #define DMP_SFF_PAGE_A2_SIZE 256 3017 3018 #define SFP_WAVELENGTH_LC1310 1310 3019 #define SFP_WAVELENGTH_LL1550 1550 3020 3021 3022 /* 3023 * * SFF-8472 TABLE 3.4 3024 * */ 3025 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3026 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3027 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3028 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3029 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3030 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3031 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3032 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3033 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3034 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3035 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3036 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3037 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3038 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3039 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3040 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3041 3042 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3043 3044 #define SSF_IDENTIFIER 0 3045 #define SSF_EXT_IDENTIFIER 1 3046 #define SSF_CONNECTOR 2 3047 #define SSF_TRANSCEIVER_CODE_B0 3 3048 #define SSF_TRANSCEIVER_CODE_B1 4 3049 #define SSF_TRANSCEIVER_CODE_B2 5 3050 #define SSF_TRANSCEIVER_CODE_B3 6 3051 #define SSF_TRANSCEIVER_CODE_B4 7 3052 #define SSF_TRANSCEIVER_CODE_B5 8 3053 #define SSF_TRANSCEIVER_CODE_B6 9 3054 #define SSF_TRANSCEIVER_CODE_B7 10 3055 #define SSF_ENCODING 11 3056 #define SSF_BR_NOMINAL 12 3057 #define SSF_RATE_IDENTIFIER 13 3058 #define SSF_LENGTH_9UM_KM 14 3059 #define SSF_LENGTH_9UM 15 3060 #define SSF_LENGTH_50UM_OM2 16 3061 #define SSF_LENGTH_62UM_OM1 17 3062 #define SFF_LENGTH_COPPER 18 3063 #define SSF_LENGTH_50UM_OM3 19 3064 #define SSF_VENDOR_NAME 20 3065 #define SSF_VENDOR_OUI 36 3066 #define SSF_VENDOR_PN 40 3067 #define SSF_VENDOR_REV 56 3068 #define SSF_WAVELENGTH_B1 60 3069 #define SSF_WAVELENGTH_B0 61 3070 #define SSF_CC_BASE 63 3071 #define SSF_OPTIONS_B1 64 3072 #define SSF_OPTIONS_B0 65 3073 #define SSF_BR_MAX 66 3074 #define SSF_BR_MIN 67 3075 #define SSF_VENDOR_SN 68 3076 #define SSF_DATE_CODE 84 3077 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3078 #define SSF_ENHANCED_OPTIONS 93 3079 #define SFF_8472_COMPLIANCE 94 3080 #define SSF_CC_EXT 95 3081 #define SSF_A0_VENDOR_SPECIFIC 96 3082 3083 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3084 3085 #define SSF_TEMP_HIGH_ALARM 0 3086 #define SSF_TEMP_LOW_ALARM 2 3087 #define SSF_TEMP_HIGH_WARNING 4 3088 #define SSF_TEMP_LOW_WARNING 6 3089 #define SSF_VOLTAGE_HIGH_ALARM 8 3090 #define SSF_VOLTAGE_LOW_ALARM 10 3091 #define SSF_VOLTAGE_HIGH_WARNING 12 3092 #define SSF_VOLTAGE_LOW_WARNING 14 3093 #define SSF_BIAS_HIGH_ALARM 16 3094 #define SSF_BIAS_LOW_ALARM 18 3095 #define SSF_BIAS_HIGH_WARNING 20 3096 #define SSF_BIAS_LOW_WARNING 22 3097 #define SSF_TXPOWER_HIGH_ALARM 24 3098 #define SSF_TXPOWER_LOW_ALARM 26 3099 #define SSF_TXPOWER_HIGH_WARNING 28 3100 #define SSF_TXPOWER_LOW_WARNING 30 3101 #define SSF_RXPOWER_HIGH_ALARM 32 3102 #define SSF_RXPOWER_LOW_ALARM 34 3103 #define SSF_RXPOWER_HIGH_WARNING 36 3104 #define SSF_RXPOWER_LOW_WARNING 38 3105 #define SSF_EXT_CAL_CONSTANTS 56 3106 #define SSF_CC_DMI 95 3107 #define SFF_TEMPERATURE_B1 96 3108 #define SFF_TEMPERATURE_B0 97 3109 #define SFF_VCC_B1 98 3110 #define SFF_VCC_B0 99 3111 #define SFF_TX_BIAS_CURRENT_B1 100 3112 #define SFF_TX_BIAS_CURRENT_B0 101 3113 #define SFF_TXPOWER_B1 102 3114 #define SFF_TXPOWER_B0 103 3115 #define SFF_RXPOWER_B1 104 3116 #define SFF_RXPOWER_B0 105 3117 #define SSF_STATUS_CONTROL 110 3118 #define SSF_ALARM_FLAGS 112 3119 #define SSF_WARNING_FLAGS 116 3120 #define SSF_EXT_TATUS_CONTROL_B1 118 3121 #define SSF_EXT_TATUS_CONTROL_B0 119 3122 #define SSF_A2_VENDOR_SPECIFIC 120 3123 #define SSF_USER_EEPROM 128 3124 #define SSF_VENDOR_CONTROL 148 3125 3126 3127 /* 3128 * Tranceiver codes Fibre Channel SFF-8472 3129 * Table 3.5. 3130 */ 3131 3132 struct sff_trasnceiver_codes_byte0 { 3133 uint8_t inifiband:4; 3134 uint8_t teng_ethernet:4; 3135 }; 3136 3137 struct sff_trasnceiver_codes_byte1 { 3138 uint8_t sonet:6; 3139 uint8_t escon:2; 3140 }; 3141 3142 struct sff_trasnceiver_codes_byte2 { 3143 uint8_t soNet:8; 3144 }; 3145 3146 struct sff_trasnceiver_codes_byte3 { 3147 uint8_t ethernet:8; 3148 }; 3149 3150 struct sff_trasnceiver_codes_byte4 { 3151 uint8_t fc_el_lo:1; 3152 uint8_t fc_lw_laser:1; 3153 uint8_t fc_sw_laser:1; 3154 uint8_t fc_md_distance:1; 3155 uint8_t fc_lg_distance:1; 3156 uint8_t fc_int_distance:1; 3157 uint8_t fc_short_distance:1; 3158 uint8_t fc_vld_distance:1; 3159 }; 3160 3161 struct sff_trasnceiver_codes_byte5 { 3162 uint8_t reserved1:1; 3163 uint8_t reserved2:1; 3164 uint8_t fc_sfp_active:1; /* Active cable */ 3165 uint8_t fc_sfp_passive:1; /* Passive cable */ 3166 uint8_t fc_lw_laser:1; /* Longwave laser */ 3167 uint8_t fc_sw_laser_sl:1; 3168 uint8_t fc_sw_laser_sn:1; 3169 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3170 }; 3171 3172 struct sff_trasnceiver_codes_byte6 { 3173 uint8_t fc_tm_sm:1; /* Single Mode */ 3174 uint8_t reserved:1; 3175 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3176 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3177 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3178 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3179 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3180 }; 3181 3182 struct sff_trasnceiver_codes_byte7 { 3183 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3184 uint8_t reserve:1; 3185 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3186 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3187 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3188 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3189 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3190 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3191 }; 3192 3193 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3194 struct user_eeprom { 3195 uint8_t vendor_name[16]; 3196 uint8_t vendor_oui[3]; 3197 uint8_t vendor_pn[816]; 3198 uint8_t vendor_rev[4]; 3199 uint8_t vendor_sn[16]; 3200 uint8_t datecode[6]; 3201 uint8_t lot_code[2]; 3202 uint8_t reserved191[57]; 3203 }; 3204 3205 struct lpfc_mbx_pc_sli4_params { 3206 uint32_t word1; 3207 #define qs_SHIFT 0 3208 #define qs_MASK 0x00000001 3209 #define qs_WORD word1 3210 #define wr_SHIFT 1 3211 #define wr_MASK 0x00000001 3212 #define wr_WORD word1 3213 #define pf_SHIFT 8 3214 #define pf_MASK 0x000000ff 3215 #define pf_WORD word1 3216 #define cpn_SHIFT 16 3217 #define cpn_MASK 0x000000ff 3218 #define cpn_WORD word1 3219 uint32_t word2; 3220 #define if_type_SHIFT 0 3221 #define if_type_MASK 0x00000007 3222 #define if_type_WORD word2 3223 #define sli_rev_SHIFT 4 3224 #define sli_rev_MASK 0x0000000f 3225 #define sli_rev_WORD word2 3226 #define sli_family_SHIFT 8 3227 #define sli_family_MASK 0x000000ff 3228 #define sli_family_WORD word2 3229 #define featurelevel_1_SHIFT 16 3230 #define featurelevel_1_MASK 0x000000ff 3231 #define featurelevel_1_WORD word2 3232 #define featurelevel_2_SHIFT 24 3233 #define featurelevel_2_MASK 0x0000001f 3234 #define featurelevel_2_WORD word2 3235 uint32_t word3; 3236 #define fcoe_SHIFT 0 3237 #define fcoe_MASK 0x00000001 3238 #define fcoe_WORD word3 3239 #define fc_SHIFT 1 3240 #define fc_MASK 0x00000001 3241 #define fc_WORD word3 3242 #define nic_SHIFT 2 3243 #define nic_MASK 0x00000001 3244 #define nic_WORD word3 3245 #define iscsi_SHIFT 3 3246 #define iscsi_MASK 0x00000001 3247 #define iscsi_WORD word3 3248 #define rdma_SHIFT 4 3249 #define rdma_MASK 0x00000001 3250 #define rdma_WORD word3 3251 uint32_t sge_supp_len; 3252 #define SLI4_PAGE_SIZE 4096 3253 uint32_t word5; 3254 #define if_page_sz_SHIFT 0 3255 #define if_page_sz_MASK 0x0000ffff 3256 #define if_page_sz_WORD word5 3257 #define loopbk_scope_SHIFT 24 3258 #define loopbk_scope_MASK 0x0000000f 3259 #define loopbk_scope_WORD word5 3260 #define rq_db_window_SHIFT 28 3261 #define rq_db_window_MASK 0x0000000f 3262 #define rq_db_window_WORD word5 3263 uint32_t word6; 3264 #define eq_pages_SHIFT 0 3265 #define eq_pages_MASK 0x0000000f 3266 #define eq_pages_WORD word6 3267 #define eqe_size_SHIFT 8 3268 #define eqe_size_MASK 0x000000ff 3269 #define eqe_size_WORD word6 3270 uint32_t word7; 3271 #define cq_pages_SHIFT 0 3272 #define cq_pages_MASK 0x0000000f 3273 #define cq_pages_WORD word7 3274 #define cqe_size_SHIFT 8 3275 #define cqe_size_MASK 0x000000ff 3276 #define cqe_size_WORD word7 3277 uint32_t word8; 3278 #define mq_pages_SHIFT 0 3279 #define mq_pages_MASK 0x0000000f 3280 #define mq_pages_WORD word8 3281 #define mqe_size_SHIFT 8 3282 #define mqe_size_MASK 0x000000ff 3283 #define mqe_size_WORD word8 3284 #define mq_elem_cnt_SHIFT 16 3285 #define mq_elem_cnt_MASK 0x000000ff 3286 #define mq_elem_cnt_WORD word8 3287 uint32_t word9; 3288 #define wq_pages_SHIFT 0 3289 #define wq_pages_MASK 0x0000ffff 3290 #define wq_pages_WORD word9 3291 #define wqe_size_SHIFT 8 3292 #define wqe_size_MASK 0x000000ff 3293 #define wqe_size_WORD word9 3294 uint32_t word10; 3295 #define rq_pages_SHIFT 0 3296 #define rq_pages_MASK 0x0000ffff 3297 #define rq_pages_WORD word10 3298 #define rqe_size_SHIFT 8 3299 #define rqe_size_MASK 0x000000ff 3300 #define rqe_size_WORD word10 3301 uint32_t word11; 3302 #define hdr_pages_SHIFT 0 3303 #define hdr_pages_MASK 0x0000000f 3304 #define hdr_pages_WORD word11 3305 #define hdr_size_SHIFT 8 3306 #define hdr_size_MASK 0x0000000f 3307 #define hdr_size_WORD word11 3308 #define hdr_pp_align_SHIFT 16 3309 #define hdr_pp_align_MASK 0x0000ffff 3310 #define hdr_pp_align_WORD word11 3311 uint32_t word12; 3312 #define sgl_pages_SHIFT 0 3313 #define sgl_pages_MASK 0x0000000f 3314 #define sgl_pages_WORD word12 3315 #define sgl_pp_align_SHIFT 16 3316 #define sgl_pp_align_MASK 0x0000ffff 3317 #define sgl_pp_align_WORD word12 3318 uint32_t rsvd_13_63[51]; 3319 }; 3320 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3321 &(~((SLI4_PAGE_SIZE)-1))) 3322 3323 struct lpfc_sli4_parameters { 3324 uint32_t word0; 3325 #define cfg_prot_type_SHIFT 0 3326 #define cfg_prot_type_MASK 0x000000FF 3327 #define cfg_prot_type_WORD word0 3328 uint32_t word1; 3329 #define cfg_ft_SHIFT 0 3330 #define cfg_ft_MASK 0x00000001 3331 #define cfg_ft_WORD word1 3332 #define cfg_sli_rev_SHIFT 4 3333 #define cfg_sli_rev_MASK 0x0000000f 3334 #define cfg_sli_rev_WORD word1 3335 #define cfg_sli_family_SHIFT 8 3336 #define cfg_sli_family_MASK 0x0000000f 3337 #define cfg_sli_family_WORD word1 3338 #define cfg_if_type_SHIFT 12 3339 #define cfg_if_type_MASK 0x0000000f 3340 #define cfg_if_type_WORD word1 3341 #define cfg_sli_hint_1_SHIFT 16 3342 #define cfg_sli_hint_1_MASK 0x000000ff 3343 #define cfg_sli_hint_1_WORD word1 3344 #define cfg_sli_hint_2_SHIFT 24 3345 #define cfg_sli_hint_2_MASK 0x0000001f 3346 #define cfg_sli_hint_2_WORD word1 3347 uint32_t word2; 3348 #define cfg_eqav_SHIFT 31 3349 #define cfg_eqav_MASK 0x00000001 3350 #define cfg_eqav_WORD word2 3351 uint32_t word3; 3352 uint32_t word4; 3353 #define cfg_cqv_SHIFT 14 3354 #define cfg_cqv_MASK 0x00000003 3355 #define cfg_cqv_WORD word4 3356 #define cfg_cqpsize_SHIFT 16 3357 #define cfg_cqpsize_MASK 0x000000ff 3358 #define cfg_cqpsize_WORD word4 3359 #define cfg_cqav_SHIFT 31 3360 #define cfg_cqav_MASK 0x00000001 3361 #define cfg_cqav_WORD word4 3362 uint32_t word5; 3363 uint32_t word6; 3364 #define cfg_mqv_SHIFT 14 3365 #define cfg_mqv_MASK 0x00000003 3366 #define cfg_mqv_WORD word6 3367 uint32_t word7; 3368 uint32_t word8; 3369 #define cfg_wqpcnt_SHIFT 0 3370 #define cfg_wqpcnt_MASK 0x0000000f 3371 #define cfg_wqpcnt_WORD word8 3372 #define cfg_wqsize_SHIFT 8 3373 #define cfg_wqsize_MASK 0x0000000f 3374 #define cfg_wqsize_WORD word8 3375 #define cfg_wqv_SHIFT 14 3376 #define cfg_wqv_MASK 0x00000003 3377 #define cfg_wqv_WORD word8 3378 #define cfg_wqpsize_SHIFT 16 3379 #define cfg_wqpsize_MASK 0x000000ff 3380 #define cfg_wqpsize_WORD word8 3381 uint32_t word9; 3382 uint32_t word10; 3383 #define cfg_rqv_SHIFT 14 3384 #define cfg_rqv_MASK 0x00000003 3385 #define cfg_rqv_WORD word10 3386 uint32_t word11; 3387 #define cfg_rq_db_window_SHIFT 28 3388 #define cfg_rq_db_window_MASK 0x0000000f 3389 #define cfg_rq_db_window_WORD word11 3390 uint32_t word12; 3391 #define cfg_fcoe_SHIFT 0 3392 #define cfg_fcoe_MASK 0x00000001 3393 #define cfg_fcoe_WORD word12 3394 #define cfg_ext_SHIFT 1 3395 #define cfg_ext_MASK 0x00000001 3396 #define cfg_ext_WORD word12 3397 #define cfg_hdrr_SHIFT 2 3398 #define cfg_hdrr_MASK 0x00000001 3399 #define cfg_hdrr_WORD word12 3400 #define cfg_phwq_SHIFT 15 3401 #define cfg_phwq_MASK 0x00000001 3402 #define cfg_phwq_WORD word12 3403 #define cfg_oas_SHIFT 25 3404 #define cfg_oas_MASK 0x00000001 3405 #define cfg_oas_WORD word12 3406 #define cfg_loopbk_scope_SHIFT 28 3407 #define cfg_loopbk_scope_MASK 0x0000000f 3408 #define cfg_loopbk_scope_WORD word12 3409 uint32_t sge_supp_len; 3410 uint32_t word14; 3411 #define cfg_sgl_page_cnt_SHIFT 0 3412 #define cfg_sgl_page_cnt_MASK 0x0000000f 3413 #define cfg_sgl_page_cnt_WORD word14 3414 #define cfg_sgl_page_size_SHIFT 8 3415 #define cfg_sgl_page_size_MASK 0x000000ff 3416 #define cfg_sgl_page_size_WORD word14 3417 #define cfg_sgl_pp_align_SHIFT 16 3418 #define cfg_sgl_pp_align_MASK 0x000000ff 3419 #define cfg_sgl_pp_align_WORD word14 3420 uint32_t word15; 3421 uint32_t word16; 3422 uint32_t word17; 3423 uint32_t word18; 3424 uint32_t word19; 3425 #define cfg_ext_embed_cb_SHIFT 0 3426 #define cfg_ext_embed_cb_MASK 0x00000001 3427 #define cfg_ext_embed_cb_WORD word19 3428 #define cfg_mds_diags_SHIFT 1 3429 #define cfg_mds_diags_MASK 0x00000001 3430 #define cfg_mds_diags_WORD word19 3431 #define cfg_nvme_SHIFT 3 3432 #define cfg_nvme_MASK 0x00000001 3433 #define cfg_nvme_WORD word19 3434 #define cfg_xib_SHIFT 4 3435 #define cfg_xib_MASK 0x00000001 3436 #define cfg_xib_WORD word19 3437 #define cfg_eqdr_SHIFT 8 3438 #define cfg_eqdr_MASK 0x00000001 3439 #define cfg_eqdr_WORD word19 3440 #define cfg_nosr_SHIFT 9 3441 #define cfg_nosr_MASK 0x00000001 3442 #define cfg_nosr_WORD word19 3443 3444 #define cfg_bv1s_SHIFT 10 3445 #define cfg_bv1s_MASK 0x00000001 3446 #define cfg_bv1s_WORD word19 3447 3448 uint32_t word20; 3449 #define cfg_max_tow_xri_SHIFT 0 3450 #define cfg_max_tow_xri_MASK 0x0000ffff 3451 #define cfg_max_tow_xri_WORD word20 3452 3453 uint32_t word21; /* RESERVED */ 3454 uint32_t word22; /* RESERVED */ 3455 uint32_t word23; /* RESERVED */ 3456 3457 uint32_t word24; 3458 #define cfg_frag_field_offset_SHIFT 0 3459 #define cfg_frag_field_offset_MASK 0x0000ffff 3460 #define cfg_frag_field_offset_WORD word24 3461 3462 #define cfg_frag_field_size_SHIFT 16 3463 #define cfg_frag_field_size_MASK 0x0000ffff 3464 #define cfg_frag_field_size_WORD word24 3465 3466 uint32_t word25; 3467 #define cfg_sgl_field_offset_SHIFT 0 3468 #define cfg_sgl_field_offset_MASK 0x0000ffff 3469 #define cfg_sgl_field_offset_WORD word25 3470 3471 #define cfg_sgl_field_size_SHIFT 16 3472 #define cfg_sgl_field_size_MASK 0x0000ffff 3473 #define cfg_sgl_field_size_WORD word25 3474 3475 uint32_t word26; /* Chain SGE initial value LOW */ 3476 uint32_t word27; /* Chain SGE initial value HIGH */ 3477 #define LPFC_NODELAY_MAX_IO 32 3478 }; 3479 3480 #define LPFC_SET_UE_RECOVERY 0x10 3481 #define LPFC_SET_MDS_DIAGS 0x11 3482 struct lpfc_mbx_set_feature { 3483 struct mbox_header header; 3484 uint32_t feature; 3485 uint32_t param_len; 3486 uint32_t word6; 3487 #define lpfc_mbx_set_feature_UER_SHIFT 0 3488 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3489 #define lpfc_mbx_set_feature_UER_WORD word6 3490 #define lpfc_mbx_set_feature_mds_SHIFT 0 3491 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3492 #define lpfc_mbx_set_feature_mds_WORD word6 3493 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3494 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3495 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3496 uint32_t word7; 3497 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3498 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3499 #define lpfc_mbx_set_feature_UERP_WORD word7 3500 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3501 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3502 #define lpfc_mbx_set_feature_UESR_WORD word7 3503 }; 3504 3505 3506 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3507 struct lpfc_mbx_set_host_data { 3508 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3509 struct mbox_header header; 3510 uint32_t param_id; 3511 uint32_t param_len; 3512 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3513 }; 3514 3515 3516 struct lpfc_mbx_get_sli4_parameters { 3517 struct mbox_header header; 3518 struct lpfc_sli4_parameters sli4_parameters; 3519 }; 3520 3521 struct lpfc_rscr_desc_generic { 3522 #define LPFC_RSRC_DESC_WSIZE 22 3523 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3524 }; 3525 3526 struct lpfc_rsrc_desc_pcie { 3527 uint32_t word0; 3528 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3529 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3530 #define lpfc_rsrc_desc_pcie_type_WORD word0 3531 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3532 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3533 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3534 #define lpfc_rsrc_desc_pcie_length_WORD word0 3535 uint32_t word1; 3536 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3537 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3538 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3539 uint32_t reserved; 3540 uint32_t word3; 3541 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3542 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3543 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3544 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3545 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3546 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3547 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3548 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3549 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3550 uint32_t word4; 3551 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3552 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3553 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3554 }; 3555 3556 struct lpfc_rsrc_desc_fcfcoe { 3557 uint32_t word0; 3558 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3559 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3560 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3561 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3562 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3563 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3564 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3565 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3566 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3567 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3568 uint32_t word1; 3569 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3570 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3571 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3572 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3573 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3574 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3575 uint32_t word2; 3576 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3577 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3578 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3579 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3580 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3581 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3582 uint32_t word3; 3583 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3584 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3585 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3586 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3587 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3588 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3589 uint32_t word4; 3590 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3591 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3592 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3593 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3594 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3595 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3596 uint32_t word5; 3597 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3598 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3599 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3600 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3601 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3602 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3603 uint32_t word6; 3604 uint32_t word7; 3605 uint32_t word8; 3606 uint32_t word9; 3607 uint32_t word10; 3608 uint32_t word11; 3609 uint32_t word12; 3610 uint32_t word13; 3611 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3612 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3613 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3614 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3615 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3616 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3617 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3618 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3619 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3620 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3621 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3622 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3623 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3624 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3625 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3626 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3627 uint32_t bw_min; 3628 uint32_t bw_max; 3629 uint32_t iops_min; 3630 uint32_t iops_max; 3631 uint32_t reserved[4]; 3632 }; 3633 3634 struct lpfc_func_cfg { 3635 #define LPFC_RSRC_DESC_MAX_NUM 2 3636 uint32_t rsrc_desc_count; 3637 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3638 }; 3639 3640 struct lpfc_mbx_get_func_cfg { 3641 struct mbox_header header; 3642 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3643 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3644 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3645 struct lpfc_func_cfg func_cfg; 3646 }; 3647 3648 struct lpfc_prof_cfg { 3649 #define LPFC_RSRC_DESC_MAX_NUM 2 3650 uint32_t rsrc_desc_count; 3651 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3652 }; 3653 3654 struct lpfc_mbx_get_prof_cfg { 3655 struct mbox_header header; 3656 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3657 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3658 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3659 union { 3660 struct { 3661 uint32_t word10; 3662 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3663 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3664 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3665 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3666 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3667 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3668 } request; 3669 struct { 3670 struct lpfc_prof_cfg prof_cfg; 3671 } response; 3672 } u; 3673 }; 3674 3675 struct lpfc_controller_attribute { 3676 uint32_t version_string[8]; 3677 uint32_t manufacturer_name[8]; 3678 uint32_t supported_modes; 3679 uint32_t word17; 3680 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3681 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3682 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3683 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3684 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3685 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3686 uint32_t mbx_da_struct_ver; 3687 uint32_t ep_fw_da_struct_ver; 3688 uint32_t ncsi_ver_str[3]; 3689 uint32_t dflt_ext_timeout; 3690 uint32_t model_number[8]; 3691 uint32_t description[16]; 3692 uint32_t serial_number[8]; 3693 uint32_t ip_ver_str[8]; 3694 uint32_t fw_ver_str[8]; 3695 uint32_t bios_ver_str[8]; 3696 uint32_t redboot_ver_str[8]; 3697 uint32_t driver_ver_str[8]; 3698 uint32_t flash_fw_ver_str[8]; 3699 uint32_t functionality; 3700 uint32_t word105; 3701 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3702 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3703 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3704 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3705 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3706 #define lpfc_cntl_attr_asic_rev_WORD word105 3707 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3708 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3709 #define lpfc_cntl_attr_gen_guid0_WORD word105 3710 uint32_t gen_guid1_12[3]; 3711 uint32_t word109; 3712 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3713 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3714 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3715 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3716 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3717 #define lpfc_cntl_attr_gen_guid15_WORD word109 3718 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3719 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3720 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3721 uint32_t word110; 3722 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3723 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3724 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3725 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3726 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3727 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3728 uint32_t word111; 3729 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3730 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3731 #define lpfc_cntl_attr_cache_valid_WORD word111 3732 #define lpfc_cntl_attr_hba_status_SHIFT 8 3733 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3734 #define lpfc_cntl_attr_hba_status_WORD word111 3735 #define lpfc_cntl_attr_max_domain_SHIFT 16 3736 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3737 #define lpfc_cntl_attr_max_domain_WORD word111 3738 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3739 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3740 #define lpfc_cntl_attr_lnk_numb_WORD word111 3741 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3742 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3743 #define lpfc_cntl_attr_lnk_type_WORD word111 3744 uint32_t fw_post_status; 3745 uint32_t hba_mtu[8]; 3746 uint32_t word121; 3747 uint32_t reserved1[3]; 3748 uint32_t word125; 3749 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3750 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3751 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3752 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3753 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3754 #define lpfc_cntl_attr_pci_device_id_WORD word125 3755 uint32_t word126; 3756 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3757 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3758 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3759 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3760 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3761 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3762 uint32_t word127; 3763 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3764 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3765 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3766 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3767 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3768 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3769 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3770 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3771 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3772 #define lpfc_cntl_attr_inf_type_SHIFT 24 3773 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3774 #define lpfc_cntl_attr_inf_type_WORD word127 3775 uint32_t unique_id[2]; 3776 uint32_t word130; 3777 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3778 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3779 #define lpfc_cntl_attr_num_netfil_WORD word130 3780 uint32_t reserved2[4]; 3781 }; 3782 3783 struct lpfc_mbx_get_cntl_attributes { 3784 union lpfc_sli4_cfg_shdr cfg_shdr; 3785 struct lpfc_controller_attribute cntl_attr; 3786 }; 3787 3788 struct lpfc_mbx_get_port_name { 3789 struct mbox_header header; 3790 union { 3791 struct { 3792 uint32_t word4; 3793 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3794 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3795 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3796 } request; 3797 struct { 3798 uint32_t word4; 3799 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3800 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3801 #define lpfc_mbx_get_port_name_name0_WORD word4 3802 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3803 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3804 #define lpfc_mbx_get_port_name_name1_WORD word4 3805 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3806 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3807 #define lpfc_mbx_get_port_name_name2_WORD word4 3808 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3809 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3810 #define lpfc_mbx_get_port_name_name3_WORD word4 3811 #define LPFC_LINK_NUMBER_0 0 3812 #define LPFC_LINK_NUMBER_1 1 3813 #define LPFC_LINK_NUMBER_2 2 3814 #define LPFC_LINK_NUMBER_3 3 3815 } response; 3816 } u; 3817 }; 3818 3819 /* Mailbox Completion Queue Error Messages */ 3820 #define MB_CQE_STATUS_SUCCESS 0x0 3821 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3822 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3823 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3824 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3825 #define MB_CQE_STATUS_DMA_FAILED 0x5 3826 3827 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3828 struct lpfc_mbx_wr_object { 3829 struct mbox_header header; 3830 union { 3831 struct { 3832 uint32_t word4; 3833 #define lpfc_wr_object_eof_SHIFT 31 3834 #define lpfc_wr_object_eof_MASK 0x00000001 3835 #define lpfc_wr_object_eof_WORD word4 3836 #define lpfc_wr_object_write_length_SHIFT 0 3837 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3838 #define lpfc_wr_object_write_length_WORD word4 3839 uint32_t write_offset; 3840 uint32_t object_name[26]; 3841 uint32_t bde_count; 3842 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3843 } request; 3844 struct { 3845 uint32_t actual_write_length; 3846 } response; 3847 } u; 3848 }; 3849 3850 /* mailbox queue entry structure */ 3851 struct lpfc_mqe { 3852 uint32_t word0; 3853 #define lpfc_mqe_status_SHIFT 16 3854 #define lpfc_mqe_status_MASK 0x0000FFFF 3855 #define lpfc_mqe_status_WORD word0 3856 #define lpfc_mqe_command_SHIFT 8 3857 #define lpfc_mqe_command_MASK 0x000000FF 3858 #define lpfc_mqe_command_WORD word0 3859 union { 3860 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3861 /* sli4 mailbox commands */ 3862 struct lpfc_mbx_sli4_config sli4_config; 3863 struct lpfc_mbx_init_vfi init_vfi; 3864 struct lpfc_mbx_reg_vfi reg_vfi; 3865 struct lpfc_mbx_reg_vfi unreg_vfi; 3866 struct lpfc_mbx_init_vpi init_vpi; 3867 struct lpfc_mbx_resume_rpi resume_rpi; 3868 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3869 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3870 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3871 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3872 struct lpfc_mbx_reg_fcfi reg_fcfi; 3873 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3874 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3875 struct lpfc_mbx_mq_create mq_create; 3876 struct lpfc_mbx_mq_create_ext mq_create_ext; 3877 struct lpfc_mbx_eq_create eq_create; 3878 struct lpfc_mbx_modify_eq_delay eq_delay; 3879 struct lpfc_mbx_cq_create cq_create; 3880 struct lpfc_mbx_cq_create_set cq_create_set; 3881 struct lpfc_mbx_wq_create wq_create; 3882 struct lpfc_mbx_rq_create rq_create; 3883 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3884 struct lpfc_mbx_mq_destroy mq_destroy; 3885 struct lpfc_mbx_eq_destroy eq_destroy; 3886 struct lpfc_mbx_cq_destroy cq_destroy; 3887 struct lpfc_mbx_wq_destroy wq_destroy; 3888 struct lpfc_mbx_rq_destroy rq_destroy; 3889 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3890 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3891 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3892 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3893 struct lpfc_mbx_nembed_cmd nembed_cmd; 3894 struct lpfc_mbx_read_rev read_rev; 3895 struct lpfc_mbx_read_vpi read_vpi; 3896 struct lpfc_mbx_read_config rd_config; 3897 struct lpfc_mbx_request_features req_ftrs; 3898 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3899 struct lpfc_mbx_query_fw_config query_fw_cfg; 3900 struct lpfc_mbx_set_beacon_config beacon_config; 3901 struct lpfc_mbx_supp_pages supp_pages; 3902 struct lpfc_mbx_pc_sli4_params sli4_params; 3903 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3904 struct lpfc_mbx_set_link_diag_state link_diag_state; 3905 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3906 struct lpfc_mbx_run_link_diag_test link_diag_test; 3907 struct lpfc_mbx_get_func_cfg get_func_cfg; 3908 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3909 struct lpfc_mbx_wr_object wr_object; 3910 struct lpfc_mbx_get_port_name get_port_name; 3911 struct lpfc_mbx_set_feature set_feature; 3912 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3913 struct lpfc_mbx_set_host_data set_host_data; 3914 struct lpfc_mbx_nop nop; 3915 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 3916 } un; 3917 }; 3918 3919 struct lpfc_mcqe { 3920 uint32_t word0; 3921 #define lpfc_mcqe_status_SHIFT 0 3922 #define lpfc_mcqe_status_MASK 0x0000FFFF 3923 #define lpfc_mcqe_status_WORD word0 3924 #define lpfc_mcqe_ext_status_SHIFT 16 3925 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3926 #define lpfc_mcqe_ext_status_WORD word0 3927 uint32_t mcqe_tag0; 3928 uint32_t mcqe_tag1; 3929 uint32_t trailer; 3930 #define lpfc_trailer_valid_SHIFT 31 3931 #define lpfc_trailer_valid_MASK 0x00000001 3932 #define lpfc_trailer_valid_WORD trailer 3933 #define lpfc_trailer_async_SHIFT 30 3934 #define lpfc_trailer_async_MASK 0x00000001 3935 #define lpfc_trailer_async_WORD trailer 3936 #define lpfc_trailer_hpi_SHIFT 29 3937 #define lpfc_trailer_hpi_MASK 0x00000001 3938 #define lpfc_trailer_hpi_WORD trailer 3939 #define lpfc_trailer_completed_SHIFT 28 3940 #define lpfc_trailer_completed_MASK 0x00000001 3941 #define lpfc_trailer_completed_WORD trailer 3942 #define lpfc_trailer_consumed_SHIFT 27 3943 #define lpfc_trailer_consumed_MASK 0x00000001 3944 #define lpfc_trailer_consumed_WORD trailer 3945 #define lpfc_trailer_type_SHIFT 16 3946 #define lpfc_trailer_type_MASK 0x000000FF 3947 #define lpfc_trailer_type_WORD trailer 3948 #define lpfc_trailer_code_SHIFT 8 3949 #define lpfc_trailer_code_MASK 0x000000FF 3950 #define lpfc_trailer_code_WORD trailer 3951 #define LPFC_TRAILER_CODE_LINK 0x1 3952 #define LPFC_TRAILER_CODE_FCOE 0x2 3953 #define LPFC_TRAILER_CODE_DCBX 0x3 3954 #define LPFC_TRAILER_CODE_GRP5 0x5 3955 #define LPFC_TRAILER_CODE_FC 0x10 3956 #define LPFC_TRAILER_CODE_SLI 0x11 3957 }; 3958 3959 struct lpfc_acqe_link { 3960 uint32_t word0; 3961 #define lpfc_acqe_link_speed_SHIFT 24 3962 #define lpfc_acqe_link_speed_MASK 0x000000FF 3963 #define lpfc_acqe_link_speed_WORD word0 3964 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3965 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3966 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3967 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3968 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3969 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3970 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3971 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3972 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3973 #define lpfc_acqe_link_duplex_SHIFT 16 3974 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3975 #define lpfc_acqe_link_duplex_WORD word0 3976 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3977 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3978 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3979 #define lpfc_acqe_link_status_SHIFT 8 3980 #define lpfc_acqe_link_status_MASK 0x000000FF 3981 #define lpfc_acqe_link_status_WORD word0 3982 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3983 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3984 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3985 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3986 #define lpfc_acqe_link_type_SHIFT 6 3987 #define lpfc_acqe_link_type_MASK 0x00000003 3988 #define lpfc_acqe_link_type_WORD word0 3989 #define lpfc_acqe_link_number_SHIFT 0 3990 #define lpfc_acqe_link_number_MASK 0x0000003F 3991 #define lpfc_acqe_link_number_WORD word0 3992 uint32_t word1; 3993 #define lpfc_acqe_link_fault_SHIFT 0 3994 #define lpfc_acqe_link_fault_MASK 0x000000FF 3995 #define lpfc_acqe_link_fault_WORD word1 3996 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3997 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3998 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3999 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 4000 #define lpfc_acqe_logical_link_speed_SHIFT 16 4001 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 4002 #define lpfc_acqe_logical_link_speed_WORD word1 4003 uint32_t event_tag; 4004 uint32_t trailer; 4005 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 4006 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 4007 }; 4008 4009 struct lpfc_acqe_fip { 4010 uint32_t index; 4011 uint32_t word1; 4012 #define lpfc_acqe_fip_fcf_count_SHIFT 0 4013 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 4014 #define lpfc_acqe_fip_fcf_count_WORD word1 4015 #define lpfc_acqe_fip_event_type_SHIFT 16 4016 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 4017 #define lpfc_acqe_fip_event_type_WORD word1 4018 uint32_t event_tag; 4019 uint32_t trailer; 4020 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 4021 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 4022 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 4023 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 4024 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 4025 }; 4026 4027 struct lpfc_acqe_dcbx { 4028 uint32_t tlv_ttl; 4029 uint32_t reserved; 4030 uint32_t event_tag; 4031 uint32_t trailer; 4032 }; 4033 4034 struct lpfc_acqe_grp5 { 4035 uint32_t word0; 4036 #define lpfc_acqe_grp5_type_SHIFT 6 4037 #define lpfc_acqe_grp5_type_MASK 0x00000003 4038 #define lpfc_acqe_grp5_type_WORD word0 4039 #define lpfc_acqe_grp5_number_SHIFT 0 4040 #define lpfc_acqe_grp5_number_MASK 0x0000003F 4041 #define lpfc_acqe_grp5_number_WORD word0 4042 uint32_t word1; 4043 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 4044 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 4045 #define lpfc_acqe_grp5_llink_spd_WORD word1 4046 uint32_t event_tag; 4047 uint32_t trailer; 4048 }; 4049 4050 struct lpfc_acqe_fc_la { 4051 uint32_t word0; 4052 #define lpfc_acqe_fc_la_speed_SHIFT 24 4053 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4054 #define lpfc_acqe_fc_la_speed_WORD word0 4055 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4056 #define LPFC_FC_LA_SPEED_1G 0x1 4057 #define LPFC_FC_LA_SPEED_2G 0x2 4058 #define LPFC_FC_LA_SPEED_4G 0x4 4059 #define LPFC_FC_LA_SPEED_8G 0x8 4060 #define LPFC_FC_LA_SPEED_10G 0xA 4061 #define LPFC_FC_LA_SPEED_16G 0x10 4062 #define LPFC_FC_LA_SPEED_32G 0x20 4063 #define LPFC_FC_LA_SPEED_64G 0x21 4064 #define LPFC_FC_LA_SPEED_128G 0x22 4065 #define LPFC_FC_LA_SPEED_256G 0x23 4066 #define lpfc_acqe_fc_la_topology_SHIFT 16 4067 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4068 #define lpfc_acqe_fc_la_topology_WORD word0 4069 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4070 #define LPFC_FC_LA_TOP_P2P 0x1 4071 #define LPFC_FC_LA_TOP_FCAL 0x2 4072 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4073 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4074 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4075 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4076 #define lpfc_acqe_fc_la_att_type_WORD word0 4077 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4078 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4079 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4080 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4081 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4082 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4083 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4084 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4085 #define lpfc_acqe_fc_la_port_type_WORD word0 4086 #define LPFC_LINK_TYPE_ETHERNET 0x0 4087 #define LPFC_LINK_TYPE_FC 0x1 4088 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4089 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4090 #define lpfc_acqe_fc_la_port_number_WORD word0 4091 uint32_t word1; 4092 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4093 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4094 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4095 #define lpfc_acqe_fc_la_fault_SHIFT 0 4096 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4097 #define lpfc_acqe_fc_la_fault_WORD word1 4098 #define LPFC_FC_LA_FAULT_NONE 0x0 4099 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4100 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4101 uint32_t event_tag; 4102 uint32_t trailer; 4103 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4104 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4105 }; 4106 4107 struct lpfc_acqe_misconfigured_event { 4108 struct { 4109 uint32_t word0; 4110 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4111 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4112 #define lpfc_sli_misconfigured_port0_state_WORD word0 4113 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4114 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4115 #define lpfc_sli_misconfigured_port1_state_WORD word0 4116 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4117 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4118 #define lpfc_sli_misconfigured_port2_state_WORD word0 4119 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4120 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4121 #define lpfc_sli_misconfigured_port3_state_WORD word0 4122 uint32_t word1; 4123 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4124 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4125 #define lpfc_sli_misconfigured_port0_op_WORD word1 4126 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4127 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4128 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4129 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4130 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4131 #define lpfc_sli_misconfigured_port1_op_WORD word1 4132 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4133 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4134 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4135 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4136 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4137 #define lpfc_sli_misconfigured_port2_op_WORD word1 4138 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4139 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4140 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4141 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4142 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4143 #define lpfc_sli_misconfigured_port3_op_WORD word1 4144 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4145 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4146 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4147 } theEvent; 4148 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4149 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4150 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4151 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4152 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4153 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4154 }; 4155 4156 struct lpfc_acqe_sli { 4157 uint32_t event_data1; 4158 uint32_t event_data2; 4159 uint32_t reserved; 4160 uint32_t trailer; 4161 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4162 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4163 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4164 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4165 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4166 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4167 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4168 }; 4169 4170 /* 4171 * Define the bootstrap mailbox (bmbx) region used to communicate 4172 * mailbox command between the host and port. The mailbox consists 4173 * of a payload area of 256 bytes and a completion queue of length 4174 * 16 bytes. 4175 */ 4176 struct lpfc_bmbx_create { 4177 struct lpfc_mqe mqe; 4178 struct lpfc_mcqe mcqe; 4179 }; 4180 4181 #define SGL_ALIGN_SZ 64 4182 #define SGL_PAGE_SIZE 4096 4183 /* align SGL addr on a size boundary - adjust address up */ 4184 #define NO_XRI 0xffff 4185 4186 struct wqe_common { 4187 uint32_t word6; 4188 #define wqe_xri_tag_SHIFT 0 4189 #define wqe_xri_tag_MASK 0x0000FFFF 4190 #define wqe_xri_tag_WORD word6 4191 #define wqe_ctxt_tag_SHIFT 16 4192 #define wqe_ctxt_tag_MASK 0x0000FFFF 4193 #define wqe_ctxt_tag_WORD word6 4194 uint32_t word7; 4195 #define wqe_dif_SHIFT 0 4196 #define wqe_dif_MASK 0x00000003 4197 #define wqe_dif_WORD word7 4198 #define LPFC_WQE_DIF_PASSTHRU 1 4199 #define LPFC_WQE_DIF_STRIP 2 4200 #define LPFC_WQE_DIF_INSERT 3 4201 #define wqe_ct_SHIFT 2 4202 #define wqe_ct_MASK 0x00000003 4203 #define wqe_ct_WORD word7 4204 #define wqe_status_SHIFT 4 4205 #define wqe_status_MASK 0x0000000f 4206 #define wqe_status_WORD word7 4207 #define wqe_cmnd_SHIFT 8 4208 #define wqe_cmnd_MASK 0x000000ff 4209 #define wqe_cmnd_WORD word7 4210 #define wqe_class_SHIFT 16 4211 #define wqe_class_MASK 0x00000007 4212 #define wqe_class_WORD word7 4213 #define wqe_ar_SHIFT 19 4214 #define wqe_ar_MASK 0x00000001 4215 #define wqe_ar_WORD word7 4216 #define wqe_ag_SHIFT wqe_ar_SHIFT 4217 #define wqe_ag_MASK wqe_ar_MASK 4218 #define wqe_ag_WORD wqe_ar_WORD 4219 #define wqe_pu_SHIFT 20 4220 #define wqe_pu_MASK 0x00000003 4221 #define wqe_pu_WORD word7 4222 #define wqe_erp_SHIFT 22 4223 #define wqe_erp_MASK 0x00000001 4224 #define wqe_erp_WORD word7 4225 #define wqe_conf_SHIFT wqe_erp_SHIFT 4226 #define wqe_conf_MASK wqe_erp_MASK 4227 #define wqe_conf_WORD wqe_erp_WORD 4228 #define wqe_lnk_SHIFT 23 4229 #define wqe_lnk_MASK 0x00000001 4230 #define wqe_lnk_WORD word7 4231 #define wqe_tmo_SHIFT 24 4232 #define wqe_tmo_MASK 0x000000ff 4233 #define wqe_tmo_WORD word7 4234 uint32_t abort_tag; /* word 8 in WQE */ 4235 uint32_t word9; 4236 #define wqe_reqtag_SHIFT 0 4237 #define wqe_reqtag_MASK 0x0000FFFF 4238 #define wqe_reqtag_WORD word9 4239 #define wqe_temp_rpi_SHIFT 16 4240 #define wqe_temp_rpi_MASK 0x0000FFFF 4241 #define wqe_temp_rpi_WORD word9 4242 #define wqe_rcvoxid_SHIFT 16 4243 #define wqe_rcvoxid_MASK 0x0000FFFF 4244 #define wqe_rcvoxid_WORD word9 4245 uint32_t word10; 4246 #define wqe_ebde_cnt_SHIFT 0 4247 #define wqe_ebde_cnt_MASK 0x0000000f 4248 #define wqe_ebde_cnt_WORD word10 4249 #define wqe_nvme_SHIFT 4 4250 #define wqe_nvme_MASK 0x00000001 4251 #define wqe_nvme_WORD word10 4252 #define wqe_oas_SHIFT 6 4253 #define wqe_oas_MASK 0x00000001 4254 #define wqe_oas_WORD word10 4255 #define wqe_lenloc_SHIFT 7 4256 #define wqe_lenloc_MASK 0x00000003 4257 #define wqe_lenloc_WORD word10 4258 #define LPFC_WQE_LENLOC_NONE 0 4259 #define LPFC_WQE_LENLOC_WORD3 1 4260 #define LPFC_WQE_LENLOC_WORD12 2 4261 #define LPFC_WQE_LENLOC_WORD4 3 4262 #define wqe_qosd_SHIFT 9 4263 #define wqe_qosd_MASK 0x00000001 4264 #define wqe_qosd_WORD word10 4265 #define wqe_xbl_SHIFT 11 4266 #define wqe_xbl_MASK 0x00000001 4267 #define wqe_xbl_WORD word10 4268 #define wqe_iod_SHIFT 13 4269 #define wqe_iod_MASK 0x00000001 4270 #define wqe_iod_WORD word10 4271 #define LPFC_WQE_IOD_NONE 0 4272 #define LPFC_WQE_IOD_WRITE 0 4273 #define LPFC_WQE_IOD_READ 1 4274 #define wqe_dbde_SHIFT 14 4275 #define wqe_dbde_MASK 0x00000001 4276 #define wqe_dbde_WORD word10 4277 #define wqe_wqes_SHIFT 15 4278 #define wqe_wqes_MASK 0x00000001 4279 #define wqe_wqes_WORD word10 4280 /* Note that this field overlaps above fields */ 4281 #define wqe_wqid_SHIFT 1 4282 #define wqe_wqid_MASK 0x00007fff 4283 #define wqe_wqid_WORD word10 4284 #define wqe_pri_SHIFT 16 4285 #define wqe_pri_MASK 0x00000007 4286 #define wqe_pri_WORD word10 4287 #define wqe_pv_SHIFT 19 4288 #define wqe_pv_MASK 0x00000001 4289 #define wqe_pv_WORD word10 4290 #define wqe_xc_SHIFT 21 4291 #define wqe_xc_MASK 0x00000001 4292 #define wqe_xc_WORD word10 4293 #define wqe_sr_SHIFT 22 4294 #define wqe_sr_MASK 0x00000001 4295 #define wqe_sr_WORD word10 4296 #define wqe_ccpe_SHIFT 23 4297 #define wqe_ccpe_MASK 0x00000001 4298 #define wqe_ccpe_WORD word10 4299 #define wqe_ccp_SHIFT 24 4300 #define wqe_ccp_MASK 0x000000ff 4301 #define wqe_ccp_WORD word10 4302 uint32_t word11; 4303 #define wqe_cmd_type_SHIFT 0 4304 #define wqe_cmd_type_MASK 0x0000000f 4305 #define wqe_cmd_type_WORD word11 4306 #define wqe_els_id_SHIFT 4 4307 #define wqe_els_id_MASK 0x00000003 4308 #define wqe_els_id_WORD word11 4309 #define LPFC_ELS_ID_FLOGI 3 4310 #define LPFC_ELS_ID_FDISC 2 4311 #define LPFC_ELS_ID_LOGO 1 4312 #define LPFC_ELS_ID_DEFAULT 0 4313 #define wqe_irsp_SHIFT 4 4314 #define wqe_irsp_MASK 0x00000001 4315 #define wqe_irsp_WORD word11 4316 #define wqe_pbde_SHIFT 5 4317 #define wqe_pbde_MASK 0x00000001 4318 #define wqe_pbde_WORD word11 4319 #define wqe_sup_SHIFT 6 4320 #define wqe_sup_MASK 0x00000001 4321 #define wqe_sup_WORD word11 4322 #define wqe_wqec_SHIFT 7 4323 #define wqe_wqec_MASK 0x00000001 4324 #define wqe_wqec_WORD word11 4325 #define wqe_irsplen_SHIFT 8 4326 #define wqe_irsplen_MASK 0x0000000f 4327 #define wqe_irsplen_WORD word11 4328 #define wqe_cqid_SHIFT 16 4329 #define wqe_cqid_MASK 0x0000ffff 4330 #define wqe_cqid_WORD word11 4331 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4332 }; 4333 4334 struct wqe_did { 4335 uint32_t word5; 4336 #define wqe_els_did_SHIFT 0 4337 #define wqe_els_did_MASK 0x00FFFFFF 4338 #define wqe_els_did_WORD word5 4339 #define wqe_xmit_bls_pt_SHIFT 28 4340 #define wqe_xmit_bls_pt_MASK 0x00000003 4341 #define wqe_xmit_bls_pt_WORD word5 4342 #define wqe_xmit_bls_ar_SHIFT 30 4343 #define wqe_xmit_bls_ar_MASK 0x00000001 4344 #define wqe_xmit_bls_ar_WORD word5 4345 #define wqe_xmit_bls_xo_SHIFT 31 4346 #define wqe_xmit_bls_xo_MASK 0x00000001 4347 #define wqe_xmit_bls_xo_WORD word5 4348 }; 4349 4350 struct lpfc_wqe_generic{ 4351 struct ulp_bde64 bde; 4352 uint32_t word3; 4353 uint32_t word4; 4354 uint32_t word5; 4355 struct wqe_common wqe_com; 4356 uint32_t payload[4]; 4357 }; 4358 4359 struct els_request64_wqe { 4360 struct ulp_bde64 bde; 4361 uint32_t payload_len; 4362 uint32_t word4; 4363 #define els_req64_sid_SHIFT 0 4364 #define els_req64_sid_MASK 0x00FFFFFF 4365 #define els_req64_sid_WORD word4 4366 #define els_req64_sp_SHIFT 24 4367 #define els_req64_sp_MASK 0x00000001 4368 #define els_req64_sp_WORD word4 4369 #define els_req64_vf_SHIFT 25 4370 #define els_req64_vf_MASK 0x00000001 4371 #define els_req64_vf_WORD word4 4372 struct wqe_did wqe_dest; 4373 struct wqe_common wqe_com; /* words 6-11 */ 4374 uint32_t word12; 4375 #define els_req64_vfid_SHIFT 1 4376 #define els_req64_vfid_MASK 0x00000FFF 4377 #define els_req64_vfid_WORD word12 4378 #define els_req64_pri_SHIFT 13 4379 #define els_req64_pri_MASK 0x00000007 4380 #define els_req64_pri_WORD word12 4381 uint32_t word13; 4382 #define els_req64_hopcnt_SHIFT 24 4383 #define els_req64_hopcnt_MASK 0x000000ff 4384 #define els_req64_hopcnt_WORD word13 4385 uint32_t word14; 4386 uint32_t max_response_payload_len; 4387 }; 4388 4389 struct xmit_els_rsp64_wqe { 4390 struct ulp_bde64 bde; 4391 uint32_t response_payload_len; 4392 uint32_t word4; 4393 #define els_rsp64_sid_SHIFT 0 4394 #define els_rsp64_sid_MASK 0x00FFFFFF 4395 #define els_rsp64_sid_WORD word4 4396 #define els_rsp64_sp_SHIFT 24 4397 #define els_rsp64_sp_MASK 0x00000001 4398 #define els_rsp64_sp_WORD word4 4399 struct wqe_did wqe_dest; 4400 struct wqe_common wqe_com; /* words 6-11 */ 4401 uint32_t word12; 4402 #define wqe_rsp_temp_rpi_SHIFT 0 4403 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4404 #define wqe_rsp_temp_rpi_WORD word12 4405 uint32_t rsvd_13_15[3]; 4406 }; 4407 4408 struct xmit_bls_rsp64_wqe { 4409 uint32_t payload0; 4410 /* Payload0 for BA_ACC */ 4411 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4412 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4413 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4414 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4415 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4416 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4417 /* Payload0 for BA_RJT */ 4418 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4419 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4420 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4421 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4422 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4423 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4424 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4425 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4426 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4427 uint32_t word1; 4428 #define xmit_bls_rsp64_rxid_SHIFT 0 4429 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4430 #define xmit_bls_rsp64_rxid_WORD word1 4431 #define xmit_bls_rsp64_oxid_SHIFT 16 4432 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4433 #define xmit_bls_rsp64_oxid_WORD word1 4434 uint32_t word2; 4435 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4436 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4437 #define xmit_bls_rsp64_seqcnthi_WORD word2 4438 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4439 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4440 #define xmit_bls_rsp64_seqcntlo_WORD word2 4441 uint32_t rsrvd3; 4442 uint32_t rsrvd4; 4443 struct wqe_did wqe_dest; 4444 struct wqe_common wqe_com; /* words 6-11 */ 4445 uint32_t word12; 4446 #define xmit_bls_rsp64_temprpi_SHIFT 0 4447 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4448 #define xmit_bls_rsp64_temprpi_WORD word12 4449 uint32_t rsvd_13_15[3]; 4450 }; 4451 4452 struct wqe_rctl_dfctl { 4453 uint32_t word5; 4454 #define wqe_si_SHIFT 2 4455 #define wqe_si_MASK 0x000000001 4456 #define wqe_si_WORD word5 4457 #define wqe_la_SHIFT 3 4458 #define wqe_la_MASK 0x000000001 4459 #define wqe_la_WORD word5 4460 #define wqe_xo_SHIFT 6 4461 #define wqe_xo_MASK 0x000000001 4462 #define wqe_xo_WORD word5 4463 #define wqe_ls_SHIFT 7 4464 #define wqe_ls_MASK 0x000000001 4465 #define wqe_ls_WORD word5 4466 #define wqe_dfctl_SHIFT 8 4467 #define wqe_dfctl_MASK 0x0000000ff 4468 #define wqe_dfctl_WORD word5 4469 #define wqe_type_SHIFT 16 4470 #define wqe_type_MASK 0x0000000ff 4471 #define wqe_type_WORD word5 4472 #define wqe_rctl_SHIFT 24 4473 #define wqe_rctl_MASK 0x0000000ff 4474 #define wqe_rctl_WORD word5 4475 }; 4476 4477 struct xmit_seq64_wqe { 4478 struct ulp_bde64 bde; 4479 uint32_t rsvd3; 4480 uint32_t relative_offset; 4481 struct wqe_rctl_dfctl wge_ctl; 4482 struct wqe_common wqe_com; /* words 6-11 */ 4483 uint32_t xmit_len; 4484 uint32_t rsvd_12_15[3]; 4485 }; 4486 struct xmit_bcast64_wqe { 4487 struct ulp_bde64 bde; 4488 uint32_t seq_payload_len; 4489 uint32_t rsvd4; 4490 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4491 struct wqe_common wqe_com; /* words 6-11 */ 4492 uint32_t rsvd_12_15[4]; 4493 }; 4494 4495 struct gen_req64_wqe { 4496 struct ulp_bde64 bde; 4497 uint32_t request_payload_len; 4498 uint32_t relative_offset; 4499 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4500 struct wqe_common wqe_com; /* words 6-11 */ 4501 uint32_t rsvd_12_14[3]; 4502 uint32_t max_response_payload_len; 4503 }; 4504 4505 /* Define NVME PRLI request to fabric. NVME is a 4506 * fabric-only protocol. 4507 * Updated to red-lined v1.08 on Sept 16, 2016 4508 */ 4509 struct lpfc_nvme_prli { 4510 uint32_t word1; 4511 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4512 #define prli_acc_rsp_code_SHIFT 8 4513 #define prli_acc_rsp_code_MASK 0x0000000f 4514 #define prli_acc_rsp_code_WORD word1 4515 #define prli_estabImagePair_SHIFT 13 4516 #define prli_estabImagePair_MASK 0x00000001 4517 #define prli_estabImagePair_WORD word1 4518 #define prli_type_code_ext_SHIFT 16 4519 #define prli_type_code_ext_MASK 0x000000ff 4520 #define prli_type_code_ext_WORD word1 4521 #define prli_type_code_SHIFT 24 4522 #define prli_type_code_MASK 0x000000ff 4523 #define prli_type_code_WORD word1 4524 uint32_t word_rsvd2; 4525 uint32_t word_rsvd3; 4526 uint32_t word4; 4527 #define prli_fba_SHIFT 0 4528 #define prli_fba_MASK 0x00000001 4529 #define prli_fba_WORD word4 4530 #define prli_disc_SHIFT 3 4531 #define prli_disc_MASK 0x00000001 4532 #define prli_disc_WORD word4 4533 #define prli_tgt_SHIFT 4 4534 #define prli_tgt_MASK 0x00000001 4535 #define prli_tgt_WORD word4 4536 #define prli_init_SHIFT 5 4537 #define prli_init_MASK 0x00000001 4538 #define prli_init_WORD word4 4539 #define prli_conf_SHIFT 7 4540 #define prli_conf_MASK 0x00000001 4541 #define prli_conf_WORD word4 4542 uint32_t word5; 4543 #define prli_fb_sz_SHIFT 0 4544 #define prli_fb_sz_MASK 0x0000ffff 4545 #define prli_fb_sz_WORD word5 4546 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4547 }; 4548 4549 struct create_xri_wqe { 4550 uint32_t rsrvd[5]; /* words 0-4 */ 4551 struct wqe_did wqe_dest; /* word 5 */ 4552 struct wqe_common wqe_com; /* words 6-11 */ 4553 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4554 }; 4555 4556 #define T_REQUEST_TAG 3 4557 #define T_XRI_TAG 1 4558 4559 struct abort_cmd_wqe { 4560 uint32_t rsrvd[3]; 4561 uint32_t word3; 4562 #define abort_cmd_ia_SHIFT 0 4563 #define abort_cmd_ia_MASK 0x000000001 4564 #define abort_cmd_ia_WORD word3 4565 #define abort_cmd_criteria_SHIFT 8 4566 #define abort_cmd_criteria_MASK 0x0000000ff 4567 #define abort_cmd_criteria_WORD word3 4568 uint32_t rsrvd4; 4569 uint32_t rsrvd5; 4570 struct wqe_common wqe_com; /* words 6-11 */ 4571 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4572 }; 4573 4574 struct fcp_iwrite64_wqe { 4575 struct ulp_bde64 bde; 4576 uint32_t word3; 4577 #define cmd_buff_len_SHIFT 16 4578 #define cmd_buff_len_MASK 0x00000ffff 4579 #define cmd_buff_len_WORD word3 4580 #define payload_offset_len_SHIFT 0 4581 #define payload_offset_len_MASK 0x0000ffff 4582 #define payload_offset_len_WORD word3 4583 uint32_t total_xfer_len; 4584 uint32_t initial_xfer_len; 4585 struct wqe_common wqe_com; /* words 6-11 */ 4586 uint32_t rsrvd12; 4587 struct ulp_bde64 ph_bde; /* words 13-15 */ 4588 }; 4589 4590 struct fcp_iread64_wqe { 4591 struct ulp_bde64 bde; 4592 uint32_t word3; 4593 #define cmd_buff_len_SHIFT 16 4594 #define cmd_buff_len_MASK 0x00000ffff 4595 #define cmd_buff_len_WORD word3 4596 #define payload_offset_len_SHIFT 0 4597 #define payload_offset_len_MASK 0x0000ffff 4598 #define payload_offset_len_WORD word3 4599 uint32_t total_xfer_len; /* word 4 */ 4600 uint32_t rsrvd5; /* word 5 */ 4601 struct wqe_common wqe_com; /* words 6-11 */ 4602 uint32_t rsrvd12; 4603 struct ulp_bde64 ph_bde; /* words 13-15 */ 4604 }; 4605 4606 struct fcp_icmnd64_wqe { 4607 struct ulp_bde64 bde; /* words 0-2 */ 4608 uint32_t word3; 4609 #define cmd_buff_len_SHIFT 16 4610 #define cmd_buff_len_MASK 0x00000ffff 4611 #define cmd_buff_len_WORD word3 4612 #define payload_offset_len_SHIFT 0 4613 #define payload_offset_len_MASK 0x0000ffff 4614 #define payload_offset_len_WORD word3 4615 uint32_t rsrvd4; /* word 4 */ 4616 uint32_t rsrvd5; /* word 5 */ 4617 struct wqe_common wqe_com; /* words 6-11 */ 4618 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4619 }; 4620 4621 struct fcp_trsp64_wqe { 4622 struct ulp_bde64 bde; 4623 uint32_t response_len; 4624 uint32_t rsvd_4_5[2]; 4625 struct wqe_common wqe_com; /* words 6-11 */ 4626 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4627 }; 4628 4629 struct fcp_tsend64_wqe { 4630 struct ulp_bde64 bde; 4631 uint32_t payload_offset_len; 4632 uint32_t relative_offset; 4633 uint32_t reserved; 4634 struct wqe_common wqe_com; /* words 6-11 */ 4635 uint32_t fcp_data_len; /* word 12 */ 4636 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4637 }; 4638 4639 struct fcp_treceive64_wqe { 4640 struct ulp_bde64 bde; 4641 uint32_t payload_offset_len; 4642 uint32_t relative_offset; 4643 uint32_t reserved; 4644 struct wqe_common wqe_com; /* words 6-11 */ 4645 uint32_t fcp_data_len; /* word 12 */ 4646 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4647 }; 4648 #define TXRDY_PAYLOAD_LEN 12 4649 4650 #define CMD_SEND_FRAME 0xE1 4651 4652 struct send_frame_wqe { 4653 struct ulp_bde64 bde; /* words 0-2 */ 4654 uint32_t frame_len; /* word 3 */ 4655 uint32_t fc_hdr_wd0; /* word 4 */ 4656 uint32_t fc_hdr_wd1; /* word 5 */ 4657 struct wqe_common wqe_com; /* words 6-11 */ 4658 uint32_t fc_hdr_wd2; /* word 12 */ 4659 uint32_t fc_hdr_wd3; /* word 13 */ 4660 uint32_t fc_hdr_wd4; /* word 14 */ 4661 uint32_t fc_hdr_wd5; /* word 15 */ 4662 }; 4663 4664 union lpfc_wqe { 4665 uint32_t words[16]; 4666 struct lpfc_wqe_generic generic; 4667 struct fcp_icmnd64_wqe fcp_icmd; 4668 struct fcp_iread64_wqe fcp_iread; 4669 struct fcp_iwrite64_wqe fcp_iwrite; 4670 struct abort_cmd_wqe abort_cmd; 4671 struct create_xri_wqe create_xri; 4672 struct xmit_bcast64_wqe xmit_bcast64; 4673 struct xmit_seq64_wqe xmit_sequence; 4674 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4675 struct xmit_els_rsp64_wqe xmit_els_rsp; 4676 struct els_request64_wqe els_req; 4677 struct gen_req64_wqe gen_req; 4678 struct fcp_trsp64_wqe fcp_trsp; 4679 struct fcp_tsend64_wqe fcp_tsend; 4680 struct fcp_treceive64_wqe fcp_treceive; 4681 struct send_frame_wqe send_frame; 4682 }; 4683 4684 union lpfc_wqe128 { 4685 uint32_t words[32]; 4686 struct lpfc_wqe_generic generic; 4687 struct fcp_icmnd64_wqe fcp_icmd; 4688 struct fcp_iread64_wqe fcp_iread; 4689 struct fcp_iwrite64_wqe fcp_iwrite; 4690 struct abort_cmd_wqe abort_cmd; 4691 struct create_xri_wqe create_xri; 4692 struct xmit_bcast64_wqe xmit_bcast64; 4693 struct xmit_seq64_wqe xmit_sequence; 4694 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4695 struct xmit_els_rsp64_wqe xmit_els_rsp; 4696 struct els_request64_wqe els_req; 4697 struct gen_req64_wqe gen_req; 4698 struct fcp_trsp64_wqe fcp_trsp; 4699 struct fcp_tsend64_wqe fcp_tsend; 4700 struct fcp_treceive64_wqe fcp_treceive; 4701 struct send_frame_wqe send_frame; 4702 }; 4703 4704 #define MAGIC_NUMER_G6 0xFEAA0003 4705 #define MAGIC_NUMER_G7 0xFEAA0005 4706 4707 struct lpfc_grp_hdr { 4708 uint32_t size; 4709 uint32_t magic_number; 4710 uint32_t word2; 4711 #define lpfc_grp_hdr_file_type_SHIFT 24 4712 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4713 #define lpfc_grp_hdr_file_type_WORD word2 4714 #define lpfc_grp_hdr_id_SHIFT 16 4715 #define lpfc_grp_hdr_id_MASK 0x000000FF 4716 #define lpfc_grp_hdr_id_WORD word2 4717 uint8_t rev_name[128]; 4718 uint8_t date[12]; 4719 uint8_t revision[32]; 4720 }; 4721 4722 /* Defines for WQE command type */ 4723 #define FCP_COMMAND 0x0 4724 #define NVME_READ_CMD 0x0 4725 #define FCP_COMMAND_DATA_OUT 0x1 4726 #define NVME_WRITE_CMD 0x1 4727 #define FCP_COMMAND_TRECEIVE 0x2 4728 #define FCP_COMMAND_TRSP 0x3 4729 #define FCP_COMMAND_TSEND 0x7 4730 #define OTHER_COMMAND 0x8 4731 #define ELS_COMMAND_NON_FIP 0xC 4732 #define ELS_COMMAND_FIP 0xD 4733 4734 #define LPFC_NVME_EMBED_CMD 0x0 4735 #define LPFC_NVME_EMBED_WRITE 0x1 4736 #define LPFC_NVME_EMBED_READ 0x2 4737 4738 /* WQE Commands */ 4739 #define CMD_ABORT_XRI_WQE 0x0F 4740 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4741 #define CMD_XMIT_BCAST64_WQE 0x84 4742 #define CMD_ELS_REQUEST64_WQE 0x8A 4743 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4744 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4745 #define CMD_FCP_IWRITE64_WQE 0x98 4746 #define CMD_FCP_IREAD64_WQE 0x9A 4747 #define CMD_FCP_ICMND64_WQE 0x9C 4748 #define CMD_FCP_TSEND64_WQE 0x9F 4749 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4750 #define CMD_FCP_TRSP64_WQE 0xA3 4751 #define CMD_GEN_REQUEST64_WQE 0xC2 4752 4753 #define CMD_WQE_MASK 0xff 4754 4755 4756 #define LPFC_FW_DUMP 1 4757 #define LPFC_FW_RESET 2 4758 #define LPFC_DV_RESET 3 4759