1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2021 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #include <uapi/scsi/fc/fc_els.h> 24 25 /* Macros to deal with bit fields. Each bit field must have 3 #defines 26 * associated with it (_SHIFT, _MASK, and _WORD). 27 * EG. For a bit field that is in the 7th bit of the "field4" field of a 28 * structure and is 2 bits in size the following #defines must exist: 29 * struct temp { 30 * uint32_t field1; 31 * uint32_t field2; 32 * uint32_t field3; 33 * uint32_t field4; 34 * #define example_bit_field_SHIFT 7 35 * #define example_bit_field_MASK 0x03 36 * #define example_bit_field_WORD field4 37 * uint32_t field5; 38 * }; 39 * Then the macros below may be used to get or set the value of that field. 40 * EG. To get the value of the bit field from the above example: 41 * struct temp t1; 42 * value = bf_get(example_bit_field, &t1); 43 * And then to set that bit field: 44 * bf_set(example_bit_field, &t1, 2); 45 * Or clear that bit field: 46 * bf_set(example_bit_field, &t1, 0); 47 */ 48 #define bf_get_be32(name, ptr) \ 49 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 50 #define bf_get_le32(name, ptr) \ 51 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 52 #define bf_get(name, ptr) \ 53 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 54 #define bf_set_le32(name, ptr, value) \ 55 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 56 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 57 ~(name##_MASK << name##_SHIFT))))) 58 #define bf_set(name, ptr, value) \ 59 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 60 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 61 62 struct dma_address { 63 uint32_t addr_lo; 64 uint32_t addr_hi; 65 }; 66 67 struct lpfc_sli_intf { 68 uint32_t word0; 69 #define lpfc_sli_intf_valid_SHIFT 29 70 #define lpfc_sli_intf_valid_MASK 0x00000007 71 #define lpfc_sli_intf_valid_WORD word0 72 #define LPFC_SLI_INTF_VALID 6 73 #define lpfc_sli_intf_sli_hint2_SHIFT 24 74 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 75 #define lpfc_sli_intf_sli_hint2_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 77 #define lpfc_sli_intf_sli_hint1_SHIFT 16 78 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 79 #define lpfc_sli_intf_sli_hint1_WORD word0 80 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 81 #define LPFC_SLI_INTF_SLI_HINT1_1 1 82 #define LPFC_SLI_INTF_SLI_HINT1_2 2 83 #define lpfc_sli_intf_if_type_SHIFT 12 84 #define lpfc_sli_intf_if_type_MASK 0x0000000F 85 #define lpfc_sli_intf_if_type_WORD word0 86 #define LPFC_SLI_INTF_IF_TYPE_0 0 87 #define LPFC_SLI_INTF_IF_TYPE_1 1 88 #define LPFC_SLI_INTF_IF_TYPE_2 2 89 #define LPFC_SLI_INTF_IF_TYPE_6 6 90 #define lpfc_sli_intf_sli_family_SHIFT 8 91 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 92 #define lpfc_sli_intf_sli_family_WORD word0 93 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 94 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 95 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 96 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 97 #define LPFC_SLI_INTF_FAMILY_G6 0xc 98 #define LPFC_SLI_INTF_FAMILY_G7 0xd 99 #define LPFC_SLI_INTF_FAMILY_G7P 0xe 100 #define lpfc_sli_intf_slirev_SHIFT 4 101 #define lpfc_sli_intf_slirev_MASK 0x0000000F 102 #define lpfc_sli_intf_slirev_WORD word0 103 #define LPFC_SLI_INTF_REV_SLI3 3 104 #define LPFC_SLI_INTF_REV_SLI4 4 105 #define lpfc_sli_intf_func_type_SHIFT 0 106 #define lpfc_sli_intf_func_type_MASK 0x00000001 107 #define lpfc_sli_intf_func_type_WORD word0 108 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 109 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 110 }; 111 112 #define LPFC_SLI4_MBX_EMBED true 113 #define LPFC_SLI4_MBX_NEMBED false 114 115 #define LPFC_SLI4_MB_WORD_COUNT 64 116 #define LPFC_MAX_MQ_PAGE 8 117 #define LPFC_MAX_WQ_PAGE_V0 4 118 #define LPFC_MAX_WQ_PAGE 8 119 #define LPFC_MAX_RQ_PAGE 8 120 #define LPFC_MAX_CQ_PAGE 4 121 #define LPFC_MAX_EQ_PAGE 8 122 123 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 124 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 125 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 126 127 /* Define SLI4 Alignment requirements. */ 128 #define LPFC_ALIGN_16_BYTE 16 129 #define LPFC_ALIGN_64_BYTE 64 130 #define SLI4_PAGE_SIZE 4096 131 132 /* Define SLI4 specific definitions. */ 133 #define LPFC_MQ_CQE_BYTE_OFFSET 256 134 #define LPFC_MBX_CMD_HDR_LENGTH 16 135 #define LPFC_MBX_ERROR_RANGE 0x4000 136 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 137 #define LPFC_BMBX_BIT1_ADDR_LO 0 138 #define LPFC_RPI_HDR_COUNT 64 139 #define LPFC_HDR_TEMPLATE_SIZE 4096 140 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 141 #define LPFC_FCF_RECORD_WD_CNT 132 142 #define LPFC_ENTIRE_FCF_DATABASE 0 143 #define LPFC_DFLT_FCF_INDEX 0 144 145 /* Virtual function numbers */ 146 #define LPFC_VF0 0 147 #define LPFC_VF1 1 148 #define LPFC_VF2 2 149 #define LPFC_VF3 3 150 #define LPFC_VF4 4 151 #define LPFC_VF5 5 152 #define LPFC_VF6 6 153 #define LPFC_VF7 7 154 #define LPFC_VF8 8 155 #define LPFC_VF9 9 156 #define LPFC_VF10 10 157 #define LPFC_VF11 11 158 #define LPFC_VF12 12 159 #define LPFC_VF13 13 160 #define LPFC_VF14 14 161 #define LPFC_VF15 15 162 #define LPFC_VF16 16 163 #define LPFC_VF17 17 164 #define LPFC_VF18 18 165 #define LPFC_VF19 19 166 #define LPFC_VF20 20 167 #define LPFC_VF21 21 168 #define LPFC_VF22 22 169 #define LPFC_VF23 23 170 #define LPFC_VF24 24 171 #define LPFC_VF25 25 172 #define LPFC_VF26 26 173 #define LPFC_VF27 27 174 #define LPFC_VF28 28 175 #define LPFC_VF29 29 176 #define LPFC_VF30 30 177 #define LPFC_VF31 31 178 179 /* PCI function numbers */ 180 #define LPFC_PCI_FUNC0 0 181 #define LPFC_PCI_FUNC1 1 182 #define LPFC_PCI_FUNC2 2 183 #define LPFC_PCI_FUNC3 3 184 #define LPFC_PCI_FUNC4 4 185 186 /* SLI4 interface type-2 PDEV_CTL register */ 187 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 188 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 189 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 190 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 191 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 192 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 193 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 194 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 195 #define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000 196 197 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 198 199 /* Active interrupt test count */ 200 #define LPFC_ACT_INTR_CNT 4 201 202 /* Algrithmns for scheduling FCP commands to WQs */ 203 #define LPFC_FCP_SCHED_BY_HDWQ 0 204 #define LPFC_FCP_SCHED_BY_CPU 1 205 206 /* Algrithmns for NameServer Query after RSCN */ 207 #define LPFC_NS_QUERY_GID_FT 0 208 #define LPFC_NS_QUERY_GID_PT 1 209 210 /* Delay Multiplier constant */ 211 #define LPFC_DMULT_CONST 651042 212 #define LPFC_DMULT_MAX 1023 213 214 /* Configuration of Interrupts / sec for entire HBA port */ 215 #define LPFC_MIN_IMAX 5000 216 #define LPFC_MAX_IMAX 5000000 217 #define LPFC_DEF_IMAX 0 218 219 #define LPFC_MAX_AUTO_EQ_DELAY 120 220 #define LPFC_EQ_DELAY_STEP 15 221 #define LPFC_EQD_ISR_TRIGGER 20000 222 /* 1s intervals */ 223 #define LPFC_EQ_DELAY_MSECS 1000 224 225 #define LPFC_MIN_CPU_MAP 0 226 #define LPFC_MAX_CPU_MAP 1 227 #define LPFC_HBA_CPU_MAP 1 228 229 /* PORT_CAPABILITIES constants. */ 230 #define LPFC_MAX_SUPPORTED_PAGES 8 231 232 struct ulp_bde64 { 233 union ULP_BDE_TUS { 234 uint32_t w; 235 struct { 236 #ifdef __BIG_ENDIAN_BITFIELD 237 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 238 VALUE !! */ 239 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 240 #else /* __LITTLE_ENDIAN_BITFIELD */ 241 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 242 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 243 VALUE !! */ 244 #endif 245 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 246 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 247 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 248 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 249 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 250 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 251 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 252 } f; 253 } tus; 254 uint32_t addrLow; 255 uint32_t addrHigh; 256 }; 257 258 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 259 #define LPFC_MAX_BDE_IMM_SIZE 64 260 261 struct lpfc_sli4_flags { 262 uint32_t word0; 263 #define lpfc_idx_rsrc_rdy_SHIFT 0 264 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 265 #define lpfc_idx_rsrc_rdy_WORD word0 266 #define LPFC_IDX_RSRC_RDY 1 267 #define lpfc_rpi_rsrc_rdy_SHIFT 1 268 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 269 #define lpfc_rpi_rsrc_rdy_WORD word0 270 #define LPFC_RPI_RSRC_RDY 1 271 #define lpfc_vpi_rsrc_rdy_SHIFT 2 272 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 273 #define lpfc_vpi_rsrc_rdy_WORD word0 274 #define LPFC_VPI_RSRC_RDY 1 275 #define lpfc_vfi_rsrc_rdy_SHIFT 3 276 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 277 #define lpfc_vfi_rsrc_rdy_WORD word0 278 #define LPFC_VFI_RSRC_RDY 1 279 #define lpfc_ftr_ashdr_SHIFT 4 280 #define lpfc_ftr_ashdr_MASK 0x00000001 281 #define lpfc_ftr_ashdr_WORD word0 282 }; 283 284 struct sli4_bls_rsp { 285 uint32_t word0_rsvd; /* Word0 must be reserved */ 286 uint32_t word1; 287 #define lpfc_abts_orig_SHIFT 0 288 #define lpfc_abts_orig_MASK 0x00000001 289 #define lpfc_abts_orig_WORD word1 290 #define LPFC_ABTS_UNSOL_RSP 1 291 #define LPFC_ABTS_UNSOL_INT 0 292 uint32_t word2; 293 #define lpfc_abts_rxid_SHIFT 0 294 #define lpfc_abts_rxid_MASK 0x0000FFFF 295 #define lpfc_abts_rxid_WORD word2 296 #define lpfc_abts_oxid_SHIFT 16 297 #define lpfc_abts_oxid_MASK 0x0000FFFF 298 #define lpfc_abts_oxid_WORD word2 299 uint32_t word3; 300 #define lpfc_vndr_code_SHIFT 0 301 #define lpfc_vndr_code_MASK 0x000000FF 302 #define lpfc_vndr_code_WORD word3 303 #define lpfc_rsn_expln_SHIFT 8 304 #define lpfc_rsn_expln_MASK 0x000000FF 305 #define lpfc_rsn_expln_WORD word3 306 #define lpfc_rsn_code_SHIFT 16 307 #define lpfc_rsn_code_MASK 0x000000FF 308 #define lpfc_rsn_code_WORD word3 309 310 uint32_t word4; 311 uint32_t word5_rsvd; /* Word5 must be reserved */ 312 }; 313 314 /* event queue entry structure */ 315 struct lpfc_eqe { 316 uint32_t word0; 317 #define lpfc_eqe_resource_id_SHIFT 16 318 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 319 #define lpfc_eqe_resource_id_WORD word0 320 #define lpfc_eqe_minor_code_SHIFT 4 321 #define lpfc_eqe_minor_code_MASK 0x00000FFF 322 #define lpfc_eqe_minor_code_WORD word0 323 #define lpfc_eqe_major_code_SHIFT 1 324 #define lpfc_eqe_major_code_MASK 0x00000007 325 #define lpfc_eqe_major_code_WORD word0 326 #define lpfc_eqe_valid_SHIFT 0 327 #define lpfc_eqe_valid_MASK 0x00000001 328 #define lpfc_eqe_valid_WORD word0 329 }; 330 331 /* completion queue entry structure (common fields for all cqe types) */ 332 struct lpfc_cqe { 333 uint32_t reserved0; 334 uint32_t reserved1; 335 uint32_t reserved2; 336 uint32_t word3; 337 #define lpfc_cqe_valid_SHIFT 31 338 #define lpfc_cqe_valid_MASK 0x00000001 339 #define lpfc_cqe_valid_WORD word3 340 #define lpfc_cqe_code_SHIFT 16 341 #define lpfc_cqe_code_MASK 0x000000FF 342 #define lpfc_cqe_code_WORD word3 343 }; 344 345 /* Completion Queue Entry Status Codes */ 346 #define CQE_STATUS_SUCCESS 0x0 347 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 348 #define CQE_STATUS_REMOTE_STOP 0x2 349 #define CQE_STATUS_LOCAL_REJECT 0x3 350 #define CQE_STATUS_NPORT_RJT 0x4 351 #define CQE_STATUS_FABRIC_RJT 0x5 352 #define CQE_STATUS_NPORT_BSY 0x6 353 #define CQE_STATUS_FABRIC_BSY 0x7 354 #define CQE_STATUS_INTERMED_RSP 0x8 355 #define CQE_STATUS_LS_RJT 0x9 356 #define CQE_STATUS_CMD_REJECT 0xb 357 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 358 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 359 #define CQE_STATUS_DI_ERROR 0x16 360 361 /* Used when mapping CQE status to IOCB */ 362 #define LPFC_IOCB_STATUS_MASK 0xf 363 364 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 365 #define CQE_HW_STATUS_NO_ERR 0x0 366 #define CQE_HW_STATUS_UNDERRUN 0x1 367 #define CQE_HW_STATUS_OVERRUN 0x2 368 369 /* Completion Queue Entry Codes */ 370 #define CQE_CODE_COMPL_WQE 0x1 371 #define CQE_CODE_RELEASE_WQE 0x2 372 #define CQE_CODE_RECEIVE 0x4 373 #define CQE_CODE_XRI_ABORTED 0x5 374 #define CQE_CODE_RECEIVE_V1 0x9 375 #define CQE_CODE_NVME_ERSP 0xd 376 377 /* 378 * Define mask value for xri_aborted and wcqe completed CQE extended status. 379 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 380 */ 381 #define WCQE_PARAM_MASK 0x1FF 382 383 /* completion queue entry for wqe completions */ 384 struct lpfc_wcqe_complete { 385 uint32_t word0; 386 #define lpfc_wcqe_c_request_tag_SHIFT 16 387 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 388 #define lpfc_wcqe_c_request_tag_WORD word0 389 #define lpfc_wcqe_c_status_SHIFT 8 390 #define lpfc_wcqe_c_status_MASK 0x000000FF 391 #define lpfc_wcqe_c_status_WORD word0 392 #define lpfc_wcqe_c_hw_status_SHIFT 0 393 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 394 #define lpfc_wcqe_c_hw_status_WORD word0 395 #define lpfc_wcqe_c_ersp0_SHIFT 0 396 #define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF 397 #define lpfc_wcqe_c_ersp0_WORD word0 398 uint32_t total_data_placed; 399 uint32_t parameter; 400 #define lpfc_wcqe_c_bg_edir_SHIFT 5 401 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 402 #define lpfc_wcqe_c_bg_edir_WORD parameter 403 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 404 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 405 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 406 #define lpfc_wcqe_c_bg_re_SHIFT 2 407 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 408 #define lpfc_wcqe_c_bg_re_WORD parameter 409 #define lpfc_wcqe_c_bg_ae_SHIFT 1 410 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 411 #define lpfc_wcqe_c_bg_ae_WORD parameter 412 #define lpfc_wcqe_c_bg_ge_SHIFT 0 413 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 414 #define lpfc_wcqe_c_bg_ge_WORD parameter 415 uint32_t word3; 416 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 417 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 418 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 419 #define lpfc_wcqe_c_xb_SHIFT 28 420 #define lpfc_wcqe_c_xb_MASK 0x00000001 421 #define lpfc_wcqe_c_xb_WORD word3 422 #define lpfc_wcqe_c_pv_SHIFT 27 423 #define lpfc_wcqe_c_pv_MASK 0x00000001 424 #define lpfc_wcqe_c_pv_WORD word3 425 #define lpfc_wcqe_c_priority_SHIFT 24 426 #define lpfc_wcqe_c_priority_MASK 0x00000007 427 #define lpfc_wcqe_c_priority_WORD word3 428 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 429 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 430 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 431 #define lpfc_wcqe_c_sqhead_SHIFT 0 432 #define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF 433 #define lpfc_wcqe_c_sqhead_WORD word3 434 }; 435 436 /* completion queue entry for wqe release */ 437 struct lpfc_wcqe_release { 438 uint32_t reserved0; 439 uint32_t reserved1; 440 uint32_t word2; 441 #define lpfc_wcqe_r_wq_id_SHIFT 16 442 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 443 #define lpfc_wcqe_r_wq_id_WORD word2 444 #define lpfc_wcqe_r_wqe_index_SHIFT 0 445 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 446 #define lpfc_wcqe_r_wqe_index_WORD word2 447 uint32_t word3; 448 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 449 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 450 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 451 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 452 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 453 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 454 }; 455 456 struct sli4_wcqe_xri_aborted { 457 uint32_t word0; 458 #define lpfc_wcqe_xa_status_SHIFT 8 459 #define lpfc_wcqe_xa_status_MASK 0x000000FF 460 #define lpfc_wcqe_xa_status_WORD word0 461 uint32_t parameter; 462 uint32_t word2; 463 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 464 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 465 #define lpfc_wcqe_xa_remote_xid_WORD word2 466 #define lpfc_wcqe_xa_xri_SHIFT 0 467 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 468 #define lpfc_wcqe_xa_xri_WORD word2 469 uint32_t word3; 470 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 471 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 472 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 473 #define lpfc_wcqe_xa_ia_SHIFT 30 474 #define lpfc_wcqe_xa_ia_MASK 0x00000001 475 #define lpfc_wcqe_xa_ia_WORD word3 476 #define CQE_XRI_ABORTED_IA_REMOTE 0 477 #define CQE_XRI_ABORTED_IA_LOCAL 1 478 #define lpfc_wcqe_xa_br_SHIFT 29 479 #define lpfc_wcqe_xa_br_MASK 0x00000001 480 #define lpfc_wcqe_xa_br_WORD word3 481 #define CQE_XRI_ABORTED_BR_BA_ACC 0 482 #define CQE_XRI_ABORTED_BR_BA_RJT 1 483 #define lpfc_wcqe_xa_eo_SHIFT 28 484 #define lpfc_wcqe_xa_eo_MASK 0x00000001 485 #define lpfc_wcqe_xa_eo_WORD word3 486 #define CQE_XRI_ABORTED_EO_REMOTE 0 487 #define CQE_XRI_ABORTED_EO_LOCAL 1 488 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 489 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 490 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 491 }; 492 493 /* completion queue entry structure for rqe completion */ 494 struct lpfc_rcqe { 495 uint32_t word0; 496 #define lpfc_rcqe_bindex_SHIFT 16 497 #define lpfc_rcqe_bindex_MASK 0x0000FFF 498 #define lpfc_rcqe_bindex_WORD word0 499 #define lpfc_rcqe_status_SHIFT 8 500 #define lpfc_rcqe_status_MASK 0x000000FF 501 #define lpfc_rcqe_status_WORD word0 502 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 503 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 504 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 505 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 506 uint32_t word1; 507 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 508 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 509 #define lpfc_rcqe_fcf_id_v1_WORD word1 510 uint32_t word2; 511 #define lpfc_rcqe_length_SHIFT 16 512 #define lpfc_rcqe_length_MASK 0x0000FFFF 513 #define lpfc_rcqe_length_WORD word2 514 #define lpfc_rcqe_rq_id_SHIFT 6 515 #define lpfc_rcqe_rq_id_MASK 0x000003FF 516 #define lpfc_rcqe_rq_id_WORD word2 517 #define lpfc_rcqe_fcf_id_SHIFT 0 518 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 519 #define lpfc_rcqe_fcf_id_WORD word2 520 #define lpfc_rcqe_rq_id_v1_SHIFT 0 521 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 522 #define lpfc_rcqe_rq_id_v1_WORD word2 523 uint32_t word3; 524 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 525 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 526 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 527 #define lpfc_rcqe_port_SHIFT 30 528 #define lpfc_rcqe_port_MASK 0x00000001 529 #define lpfc_rcqe_port_WORD word3 530 #define lpfc_rcqe_hdr_length_SHIFT 24 531 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 532 #define lpfc_rcqe_hdr_length_WORD word3 533 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 534 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 535 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 536 #define lpfc_rcqe_eof_SHIFT 8 537 #define lpfc_rcqe_eof_MASK 0x000000FF 538 #define lpfc_rcqe_eof_WORD word3 539 #define FCOE_EOFn 0x41 540 #define FCOE_EOFt 0x42 541 #define FCOE_EOFni 0x49 542 #define FCOE_EOFa 0x50 543 #define lpfc_rcqe_sof_SHIFT 0 544 #define lpfc_rcqe_sof_MASK 0x000000FF 545 #define lpfc_rcqe_sof_WORD word3 546 #define FCOE_SOFi2 0x2d 547 #define FCOE_SOFi3 0x2e 548 #define FCOE_SOFn2 0x35 549 #define FCOE_SOFn3 0x36 550 }; 551 552 struct lpfc_rqe { 553 uint32_t address_hi; 554 uint32_t address_lo; 555 }; 556 557 /* buffer descriptors */ 558 struct lpfc_bde4 { 559 uint32_t addr_hi; 560 uint32_t addr_lo; 561 uint32_t word2; 562 #define lpfc_bde4_last_SHIFT 31 563 #define lpfc_bde4_last_MASK 0x00000001 564 #define lpfc_bde4_last_WORD word2 565 #define lpfc_bde4_sge_offset_SHIFT 0 566 #define lpfc_bde4_sge_offset_MASK 0x000003FF 567 #define lpfc_bde4_sge_offset_WORD word2 568 uint32_t word3; 569 #define lpfc_bde4_length_SHIFT 0 570 #define lpfc_bde4_length_MASK 0x000000FF 571 #define lpfc_bde4_length_WORD word3 572 }; 573 574 struct lpfc_register { 575 uint32_t word0; 576 }; 577 578 #define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000 579 #define LPFC_PORT_SEM_MASK 0xF000 580 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 581 #define LPFC_UERR_STATUS_HI 0x00A4 582 #define LPFC_UERR_STATUS_LO 0x00A0 583 #define LPFC_UE_MASK_HI 0x00AC 584 #define LPFC_UE_MASK_LO 0x00A8 585 586 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 587 #define LPFC_SLI_INTF 0x0058 588 #define LPFC_SLI_ASIC_VER 0x009C 589 590 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 591 #define lpfc_port_smphr_perr_SHIFT 31 592 #define lpfc_port_smphr_perr_MASK 0x1 593 #define lpfc_port_smphr_perr_WORD word0 594 #define lpfc_port_smphr_sfi_SHIFT 30 595 #define lpfc_port_smphr_sfi_MASK 0x1 596 #define lpfc_port_smphr_sfi_WORD word0 597 #define lpfc_port_smphr_nip_SHIFT 29 598 #define lpfc_port_smphr_nip_MASK 0x1 599 #define lpfc_port_smphr_nip_WORD word0 600 #define lpfc_port_smphr_ipc_SHIFT 28 601 #define lpfc_port_smphr_ipc_MASK 0x1 602 #define lpfc_port_smphr_ipc_WORD word0 603 #define lpfc_port_smphr_scr1_SHIFT 27 604 #define lpfc_port_smphr_scr1_MASK 0x1 605 #define lpfc_port_smphr_scr1_WORD word0 606 #define lpfc_port_smphr_scr2_SHIFT 26 607 #define lpfc_port_smphr_scr2_MASK 0x1 608 #define lpfc_port_smphr_scr2_WORD word0 609 #define lpfc_port_smphr_host_scratch_SHIFT 16 610 #define lpfc_port_smphr_host_scratch_MASK 0xFF 611 #define lpfc_port_smphr_host_scratch_WORD word0 612 #define lpfc_port_smphr_port_status_SHIFT 0 613 #define lpfc_port_smphr_port_status_MASK 0xFFFF 614 #define lpfc_port_smphr_port_status_WORD word0 615 616 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 617 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 618 #define LPFC_POST_STAGE_HOST_RDY 0x0002 619 #define LPFC_POST_STAGE_BE_RESET 0x0003 620 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 621 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 622 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 623 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 624 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 625 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 626 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 627 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 628 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 629 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 630 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 631 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 632 #define LPFC_POST_STAGE_ARMFW_START 0x0800 633 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 634 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 635 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 636 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 637 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 638 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 639 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 640 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 641 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 642 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 643 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 644 #define LPFC_POST_STAGE_RC_DONE 0x0B07 645 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 646 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 647 #define LPFC_POST_STAGE_PORT_READY 0xC000 648 #define LPFC_POST_STAGE_PORT_UE 0xF000 649 650 #define LPFC_CTL_PORT_STA_OFFSET 0x404 651 #define lpfc_sliport_status_err_SHIFT 31 652 #define lpfc_sliport_status_err_MASK 0x1 653 #define lpfc_sliport_status_err_WORD word0 654 #define lpfc_sliport_status_end_SHIFT 30 655 #define lpfc_sliport_status_end_MASK 0x1 656 #define lpfc_sliport_status_end_WORD word0 657 #define lpfc_sliport_status_oti_SHIFT 29 658 #define lpfc_sliport_status_oti_MASK 0x1 659 #define lpfc_sliport_status_oti_WORD word0 660 #define lpfc_sliport_status_dip_SHIFT 25 661 #define lpfc_sliport_status_dip_MASK 0x1 662 #define lpfc_sliport_status_dip_WORD word0 663 #define lpfc_sliport_status_rn_SHIFT 24 664 #define lpfc_sliport_status_rn_MASK 0x1 665 #define lpfc_sliport_status_rn_WORD word0 666 #define lpfc_sliport_status_rdy_SHIFT 23 667 #define lpfc_sliport_status_rdy_MASK 0x1 668 #define lpfc_sliport_status_rdy_WORD word0 669 #define MAX_IF_TYPE_2_RESETS 6 670 671 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 672 #define lpfc_sliport_ctrl_end_SHIFT 30 673 #define lpfc_sliport_ctrl_end_MASK 0x1 674 #define lpfc_sliport_ctrl_end_WORD word0 675 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 676 #define LPFC_SLIPORT_BIG_ENDIAN 1 677 #define lpfc_sliport_ctrl_ip_SHIFT 27 678 #define lpfc_sliport_ctrl_ip_MASK 0x1 679 #define lpfc_sliport_ctrl_ip_WORD word0 680 #define LPFC_SLIPORT_INIT_PORT 1 681 682 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 683 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 684 685 #define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418 686 #define lpfc_sliport_eqdelay_delay_SHIFT 16 687 #define lpfc_sliport_eqdelay_delay_MASK 0xffff 688 #define lpfc_sliport_eqdelay_delay_WORD word0 689 #define lpfc_sliport_eqdelay_id_SHIFT 0 690 #define lpfc_sliport_eqdelay_id_MASK 0xfff 691 #define lpfc_sliport_eqdelay_id_WORD word0 692 #define LPFC_SEC_TO_USEC 1000000 693 694 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 695 * reside in BAR 2. 696 */ 697 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 698 699 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 700 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 701 702 #define LPFC_HST_ISR0 0x0C18 703 #define LPFC_HST_ISR1 0x0C1C 704 #define LPFC_HST_ISR2 0x0C20 705 #define LPFC_HST_ISR3 0x0C24 706 #define LPFC_HST_ISR4 0x0C28 707 708 #define LPFC_HST_IMR0 0x0C48 709 #define LPFC_HST_IMR1 0x0C4C 710 #define LPFC_HST_IMR2 0x0C50 711 #define LPFC_HST_IMR3 0x0C54 712 #define LPFC_HST_IMR4 0x0C58 713 714 #define LPFC_HST_ISCR0 0x0C78 715 #define LPFC_HST_ISCR1 0x0C7C 716 #define LPFC_HST_ISCR2 0x0C80 717 #define LPFC_HST_ISCR3 0x0C84 718 #define LPFC_HST_ISCR4 0x0C88 719 720 #define LPFC_SLI4_INTR0 BIT0 721 #define LPFC_SLI4_INTR1 BIT1 722 #define LPFC_SLI4_INTR2 BIT2 723 #define LPFC_SLI4_INTR3 BIT3 724 #define LPFC_SLI4_INTR4 BIT4 725 #define LPFC_SLI4_INTR5 BIT5 726 #define LPFC_SLI4_INTR6 BIT6 727 #define LPFC_SLI4_INTR7 BIT7 728 #define LPFC_SLI4_INTR8 BIT8 729 #define LPFC_SLI4_INTR9 BIT9 730 #define LPFC_SLI4_INTR10 BIT10 731 #define LPFC_SLI4_INTR11 BIT11 732 #define LPFC_SLI4_INTR12 BIT12 733 #define LPFC_SLI4_INTR13 BIT13 734 #define LPFC_SLI4_INTR14 BIT14 735 #define LPFC_SLI4_INTR15 BIT15 736 #define LPFC_SLI4_INTR16 BIT16 737 #define LPFC_SLI4_INTR17 BIT17 738 #define LPFC_SLI4_INTR18 BIT18 739 #define LPFC_SLI4_INTR19 BIT19 740 #define LPFC_SLI4_INTR20 BIT20 741 #define LPFC_SLI4_INTR21 BIT21 742 #define LPFC_SLI4_INTR22 BIT22 743 #define LPFC_SLI4_INTR23 BIT23 744 #define LPFC_SLI4_INTR24 BIT24 745 #define LPFC_SLI4_INTR25 BIT25 746 #define LPFC_SLI4_INTR26 BIT26 747 #define LPFC_SLI4_INTR27 BIT27 748 #define LPFC_SLI4_INTR28 BIT28 749 #define LPFC_SLI4_INTR29 BIT29 750 #define LPFC_SLI4_INTR30 BIT30 751 #define LPFC_SLI4_INTR31 BIT31 752 753 /* 754 * The Doorbell registers defined here exist in different BAR 755 * register sets depending on the UCNA Port's reported if_type 756 * value. For UCNA ports running SLI4 and if_type 0, they reside in 757 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 758 * BAR0. For FC ports running SLI4 and if_type 6, they reside in 759 * BAR2. The offsets and base address are different, so the driver 760 * has to compute the register addresses accordingly 761 */ 762 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 763 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 764 #define LPFC_IF6_RQ_DOORBELL 0x0080 765 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 766 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 767 #define lpfc_rq_db_list_fm_num_posted_WORD word0 768 #define lpfc_rq_db_list_fm_index_SHIFT 16 769 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 770 #define lpfc_rq_db_list_fm_index_WORD word0 771 #define lpfc_rq_db_list_fm_id_SHIFT 0 772 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 773 #define lpfc_rq_db_list_fm_id_WORD word0 774 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 775 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 776 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 777 #define lpfc_rq_db_ring_fm_id_SHIFT 0 778 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 779 #define lpfc_rq_db_ring_fm_id_WORD word0 780 781 #define LPFC_ULP0_WQ_DOORBELL 0x0040 782 #define LPFC_ULP1_WQ_DOORBELL 0x0060 783 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 784 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 785 #define lpfc_wq_db_list_fm_num_posted_WORD word0 786 #define lpfc_wq_db_list_fm_index_SHIFT 16 787 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 788 #define lpfc_wq_db_list_fm_index_WORD word0 789 #define lpfc_wq_db_list_fm_id_SHIFT 0 790 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 791 #define lpfc_wq_db_list_fm_id_WORD word0 792 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 793 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 794 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 795 #define lpfc_wq_db_ring_fm_id_SHIFT 0 796 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 797 #define lpfc_wq_db_ring_fm_id_WORD word0 798 799 #define LPFC_IF6_WQ_DOORBELL 0x0040 800 #define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24 801 #define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF 802 #define lpfc_if6_wq_db_list_fm_num_posted_WORD word0 803 #define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23 804 #define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001 805 #define lpfc_if6_wq_db_list_fm_dpp_WORD word0 806 #define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16 807 #define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F 808 #define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0 809 #define lpfc_if6_wq_db_list_fm_id_SHIFT 0 810 #define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF 811 #define lpfc_if6_wq_db_list_fm_id_WORD word0 812 813 #define LPFC_EQCQ_DOORBELL 0x0120 814 #define lpfc_eqcq_doorbell_se_SHIFT 31 815 #define lpfc_eqcq_doorbell_se_MASK 0x0001 816 #define lpfc_eqcq_doorbell_se_WORD word0 817 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 818 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 819 #define lpfc_eqcq_doorbell_arm_SHIFT 29 820 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 821 #define lpfc_eqcq_doorbell_arm_WORD word0 822 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 823 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 824 #define lpfc_eqcq_doorbell_num_released_WORD word0 825 #define lpfc_eqcq_doorbell_qt_SHIFT 10 826 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 827 #define lpfc_eqcq_doorbell_qt_WORD word0 828 #define LPFC_QUEUE_TYPE_COMPLETION 0 829 #define LPFC_QUEUE_TYPE_EVENT 1 830 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 831 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 832 #define lpfc_eqcq_doorbell_eqci_WORD word0 833 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 834 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 835 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 836 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 837 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 838 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 839 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 840 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 841 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 842 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 843 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 844 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 845 #define LPFC_CQID_HI_FIELD_SHIFT 10 846 #define LPFC_EQID_HI_FIELD_SHIFT 9 847 848 #define LPFC_IF6_CQ_DOORBELL 0x00C0 849 #define lpfc_if6_cq_doorbell_se_SHIFT 31 850 #define lpfc_if6_cq_doorbell_se_MASK 0x0001 851 #define lpfc_if6_cq_doorbell_se_WORD word0 852 #define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0 853 #define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1 854 #define lpfc_if6_cq_doorbell_arm_SHIFT 29 855 #define lpfc_if6_cq_doorbell_arm_MASK 0x0001 856 #define lpfc_if6_cq_doorbell_arm_WORD word0 857 #define lpfc_if6_cq_doorbell_num_released_SHIFT 16 858 #define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF 859 #define lpfc_if6_cq_doorbell_num_released_WORD word0 860 #define lpfc_if6_cq_doorbell_cqid_SHIFT 0 861 #define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF 862 #define lpfc_if6_cq_doorbell_cqid_WORD word0 863 864 #define LPFC_IF6_EQ_DOORBELL 0x0120 865 #define lpfc_if6_eq_doorbell_io_SHIFT 31 866 #define lpfc_if6_eq_doorbell_io_MASK 0x0001 867 #define lpfc_if6_eq_doorbell_io_WORD word0 868 #define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0 869 #define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1 870 #define lpfc_if6_eq_doorbell_arm_SHIFT 29 871 #define lpfc_if6_eq_doorbell_arm_MASK 0x0001 872 #define lpfc_if6_eq_doorbell_arm_WORD word0 873 #define lpfc_if6_eq_doorbell_num_released_SHIFT 16 874 #define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF 875 #define lpfc_if6_eq_doorbell_num_released_WORD word0 876 #define lpfc_if6_eq_doorbell_eqid_SHIFT 0 877 #define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF 878 #define lpfc_if6_eq_doorbell_eqid_WORD word0 879 880 #define LPFC_BMBX 0x0160 881 #define lpfc_bmbx_addr_SHIFT 2 882 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 883 #define lpfc_bmbx_addr_WORD word0 884 #define lpfc_bmbx_hi_SHIFT 1 885 #define lpfc_bmbx_hi_MASK 0x0001 886 #define lpfc_bmbx_hi_WORD word0 887 #define lpfc_bmbx_rdy_SHIFT 0 888 #define lpfc_bmbx_rdy_MASK 0x0001 889 #define lpfc_bmbx_rdy_WORD word0 890 891 #define LPFC_MQ_DOORBELL 0x0140 892 #define LPFC_IF6_MQ_DOORBELL 0x0160 893 #define lpfc_mq_doorbell_num_posted_SHIFT 16 894 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 895 #define lpfc_mq_doorbell_num_posted_WORD word0 896 #define lpfc_mq_doorbell_id_SHIFT 0 897 #define lpfc_mq_doorbell_id_MASK 0xFFFF 898 #define lpfc_mq_doorbell_id_WORD word0 899 900 struct lpfc_sli4_cfg_mhdr { 901 uint32_t word1; 902 #define lpfc_mbox_hdr_emb_SHIFT 0 903 #define lpfc_mbox_hdr_emb_MASK 0x00000001 904 #define lpfc_mbox_hdr_emb_WORD word1 905 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 906 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 907 #define lpfc_mbox_hdr_sge_cnt_WORD word1 908 uint32_t payload_length; 909 uint32_t tag_lo; 910 uint32_t tag_hi; 911 uint32_t reserved5; 912 }; 913 914 union lpfc_sli4_cfg_shdr { 915 struct { 916 uint32_t word6; 917 #define lpfc_mbox_hdr_opcode_SHIFT 0 918 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 919 #define lpfc_mbox_hdr_opcode_WORD word6 920 #define lpfc_mbox_hdr_subsystem_SHIFT 8 921 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 922 #define lpfc_mbox_hdr_subsystem_WORD word6 923 #define lpfc_mbox_hdr_port_number_SHIFT 16 924 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 925 #define lpfc_mbox_hdr_port_number_WORD word6 926 #define lpfc_mbox_hdr_domain_SHIFT 24 927 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 928 #define lpfc_mbox_hdr_domain_WORD word6 929 uint32_t timeout; 930 uint32_t request_length; 931 uint32_t word9; 932 #define lpfc_mbox_hdr_version_SHIFT 0 933 #define lpfc_mbox_hdr_version_MASK 0x000000FF 934 #define lpfc_mbox_hdr_version_WORD word9 935 #define lpfc_mbox_hdr_pf_num_SHIFT 16 936 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 937 #define lpfc_mbox_hdr_pf_num_WORD word9 938 #define lpfc_mbox_hdr_vh_num_SHIFT 24 939 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 940 #define lpfc_mbox_hdr_vh_num_WORD word9 941 #define LPFC_Q_CREATE_VERSION_2 2 942 #define LPFC_Q_CREATE_VERSION_1 1 943 #define LPFC_Q_CREATE_VERSION_0 0 944 #define LPFC_OPCODE_VERSION_0 0 945 #define LPFC_OPCODE_VERSION_1 1 946 } request; 947 struct { 948 uint32_t word6; 949 #define lpfc_mbox_hdr_opcode_SHIFT 0 950 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 951 #define lpfc_mbox_hdr_opcode_WORD word6 952 #define lpfc_mbox_hdr_subsystem_SHIFT 8 953 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 954 #define lpfc_mbox_hdr_subsystem_WORD word6 955 #define lpfc_mbox_hdr_domain_SHIFT 24 956 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 957 #define lpfc_mbox_hdr_domain_WORD word6 958 uint32_t word7; 959 #define lpfc_mbox_hdr_status_SHIFT 0 960 #define lpfc_mbox_hdr_status_MASK 0x000000FF 961 #define lpfc_mbox_hdr_status_WORD word7 962 #define lpfc_mbox_hdr_add_status_SHIFT 8 963 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 964 #define lpfc_mbox_hdr_add_status_WORD word7 965 #define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2 966 #define lpfc_mbox_hdr_add_status_2_SHIFT 16 967 #define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF 968 #define lpfc_mbox_hdr_add_status_2_WORD word7 969 #define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01 970 #define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02 971 uint32_t response_length; 972 uint32_t actual_response_length; 973 } response; 974 }; 975 976 /* Mailbox Header structures. 977 * struct mbox_header is defined for first generation SLI4_CFG mailbox 978 * calls deployed for BE-based ports. 979 * 980 * struct sli4_mbox_header is defined for second generation SLI4 981 * ports that don't deploy the SLI4_CFG mechanism. 982 */ 983 struct mbox_header { 984 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 985 union lpfc_sli4_cfg_shdr cfg_shdr; 986 }; 987 988 #define LPFC_EXTENT_LOCAL 0 989 #define LPFC_TIMEOUT_DEFAULT 0 990 #define LPFC_EXTENT_VERSION_DEFAULT 0 991 992 /* Subsystem Definitions */ 993 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 994 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 995 #define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB 996 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 997 998 /* Device Specific Definitions */ 999 1000 /* The HOST ENDIAN defines are in Big Endian format. */ 1001 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 1002 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 1003 1004 /* Common Opcodes */ 1005 #define LPFC_MBOX_OPCODE_NA 0x00 1006 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 1007 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 1008 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 1009 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 1010 #define LPFC_MBOX_OPCODE_NOP 0x21 1011 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 1012 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 1013 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 1014 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 1015 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 1016 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 1017 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 1018 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 1019 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 1020 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 1021 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 1022 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 1023 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 1024 #define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D 1025 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 1026 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 1027 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 1028 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 1029 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 1030 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 1031 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 1032 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 1033 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 1034 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 1035 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 1036 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 1037 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 1038 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 1039 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 1040 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 1041 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 1042 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 1043 #define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF 1044 1045 /* FCoE Opcodes */ 1046 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 1047 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 1048 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 1049 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 1050 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 1051 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 1052 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 1053 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 1054 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 1055 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 1056 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 1057 #define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D 1058 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 1059 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 1060 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 1061 #define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42 1062 1063 /* Low level Opcodes */ 1064 #define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37 1065 1066 /* Mailbox command structures */ 1067 struct eq_context { 1068 uint32_t word0; 1069 #define lpfc_eq_context_size_SHIFT 31 1070 #define lpfc_eq_context_size_MASK 0x00000001 1071 #define lpfc_eq_context_size_WORD word0 1072 #define LPFC_EQE_SIZE_4 0x0 1073 #define LPFC_EQE_SIZE_16 0x1 1074 #define lpfc_eq_context_valid_SHIFT 29 1075 #define lpfc_eq_context_valid_MASK 0x00000001 1076 #define lpfc_eq_context_valid_WORD word0 1077 #define lpfc_eq_context_autovalid_SHIFT 28 1078 #define lpfc_eq_context_autovalid_MASK 0x00000001 1079 #define lpfc_eq_context_autovalid_WORD word0 1080 uint32_t word1; 1081 #define lpfc_eq_context_count_SHIFT 26 1082 #define lpfc_eq_context_count_MASK 0x00000003 1083 #define lpfc_eq_context_count_WORD word1 1084 #define LPFC_EQ_CNT_256 0x0 1085 #define LPFC_EQ_CNT_512 0x1 1086 #define LPFC_EQ_CNT_1024 0x2 1087 #define LPFC_EQ_CNT_2048 0x3 1088 #define LPFC_EQ_CNT_4096 0x4 1089 uint32_t word2; 1090 #define lpfc_eq_context_delay_multi_SHIFT 13 1091 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 1092 #define lpfc_eq_context_delay_multi_WORD word2 1093 uint32_t reserved3; 1094 }; 1095 1096 struct eq_delay_info { 1097 uint32_t eq_id; 1098 uint32_t phase; 1099 uint32_t delay_multi; 1100 }; 1101 #define LPFC_MAX_EQ_DELAY_EQID_CNT 8 1102 1103 struct sgl_page_pairs { 1104 uint32_t sgl_pg0_addr_lo; 1105 uint32_t sgl_pg0_addr_hi; 1106 uint32_t sgl_pg1_addr_lo; 1107 uint32_t sgl_pg1_addr_hi; 1108 }; 1109 1110 struct lpfc_mbx_post_sgl_pages { 1111 struct mbox_header header; 1112 uint32_t word0; 1113 #define lpfc_post_sgl_pages_xri_SHIFT 0 1114 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1115 #define lpfc_post_sgl_pages_xri_WORD word0 1116 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1117 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1118 #define lpfc_post_sgl_pages_xricnt_WORD word0 1119 struct sgl_page_pairs sgl_pg_pairs[1]; 1120 }; 1121 1122 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1123 struct lpfc_mbx_post_uembed_sgl_page1 { 1124 union lpfc_sli4_cfg_shdr cfg_shdr; 1125 uint32_t word0; 1126 struct sgl_page_pairs sgl_pg_pairs; 1127 }; 1128 1129 struct lpfc_mbx_sge { 1130 uint32_t pa_lo; 1131 uint32_t pa_hi; 1132 uint32_t length; 1133 }; 1134 1135 struct lpfc_mbx_nembed_cmd { 1136 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1137 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1138 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1139 }; 1140 1141 struct lpfc_mbx_nembed_sge_virt { 1142 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1143 }; 1144 1145 struct lpfc_mbx_eq_create { 1146 struct mbox_header header; 1147 union { 1148 struct { 1149 uint32_t word0; 1150 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1151 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1152 #define lpfc_mbx_eq_create_num_pages_WORD word0 1153 struct eq_context context; 1154 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1155 } request; 1156 struct { 1157 uint32_t word0; 1158 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1159 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1160 #define lpfc_mbx_eq_create_q_id_WORD word0 1161 } response; 1162 } u; 1163 }; 1164 1165 struct lpfc_mbx_modify_eq_delay { 1166 struct mbox_header header; 1167 union { 1168 struct { 1169 uint32_t num_eq; 1170 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT]; 1171 } request; 1172 struct { 1173 uint32_t word0; 1174 } response; 1175 } u; 1176 }; 1177 1178 struct lpfc_mbx_eq_destroy { 1179 struct mbox_header header; 1180 union { 1181 struct { 1182 uint32_t word0; 1183 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1184 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1185 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1186 } request; 1187 struct { 1188 uint32_t word0; 1189 } response; 1190 } u; 1191 }; 1192 1193 struct lpfc_mbx_nop { 1194 struct mbox_header header; 1195 uint32_t context[2]; 1196 }; 1197 1198 1199 1200 struct lpfc_mbx_set_ras_fwlog { 1201 struct mbox_header header; 1202 union { 1203 struct { 1204 uint32_t word4; 1205 #define lpfc_fwlog_enable_SHIFT 0 1206 #define lpfc_fwlog_enable_MASK 0x00000001 1207 #define lpfc_fwlog_enable_WORD word4 1208 #define lpfc_fwlog_loglvl_SHIFT 8 1209 #define lpfc_fwlog_loglvl_MASK 0x0000000F 1210 #define lpfc_fwlog_loglvl_WORD word4 1211 #define lpfc_fwlog_ra_SHIFT 15 1212 #define lpfc_fwlog_ra_WORD 0x00000008 1213 #define lpfc_fwlog_buffcnt_SHIFT 16 1214 #define lpfc_fwlog_buffcnt_MASK 0x000000FF 1215 #define lpfc_fwlog_buffcnt_WORD word4 1216 #define lpfc_fwlog_buffsz_SHIFT 24 1217 #define lpfc_fwlog_buffsz_MASK 0x000000FF 1218 #define lpfc_fwlog_buffsz_WORD word4 1219 uint32_t word5; 1220 #define lpfc_fwlog_acqe_SHIFT 0 1221 #define lpfc_fwlog_acqe_MASK 0x0000FFFF 1222 #define lpfc_fwlog_acqe_WORD word5 1223 #define lpfc_fwlog_cqid_SHIFT 16 1224 #define lpfc_fwlog_cqid_MASK 0x0000FFFF 1225 #define lpfc_fwlog_cqid_WORD word5 1226 #define LPFC_MAX_FWLOG_PAGE 16 1227 struct dma_address lwpd; 1228 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE]; 1229 } request; 1230 struct { 1231 uint32_t word0; 1232 } response; 1233 } u; 1234 }; 1235 1236 1237 struct cq_context { 1238 uint32_t word0; 1239 #define lpfc_cq_context_event_SHIFT 31 1240 #define lpfc_cq_context_event_MASK 0x00000001 1241 #define lpfc_cq_context_event_WORD word0 1242 #define lpfc_cq_context_valid_SHIFT 29 1243 #define lpfc_cq_context_valid_MASK 0x00000001 1244 #define lpfc_cq_context_valid_WORD word0 1245 #define lpfc_cq_context_count_SHIFT 27 1246 #define lpfc_cq_context_count_MASK 0x00000003 1247 #define lpfc_cq_context_count_WORD word0 1248 #define LPFC_CQ_CNT_256 0x0 1249 #define LPFC_CQ_CNT_512 0x1 1250 #define LPFC_CQ_CNT_1024 0x2 1251 #define LPFC_CQ_CNT_WORD7 0x3 1252 #define lpfc_cq_context_autovalid_SHIFT 15 1253 #define lpfc_cq_context_autovalid_MASK 0x00000001 1254 #define lpfc_cq_context_autovalid_WORD word0 1255 uint32_t word1; 1256 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1257 #define lpfc_cq_eq_id_MASK 0x000000FF 1258 #define lpfc_cq_eq_id_WORD word1 1259 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1260 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1261 #define lpfc_cq_eq_id_2_WORD word1 1262 uint32_t lpfc_cq_context_count; /* Version 2 Only */ 1263 uint32_t reserved1; 1264 }; 1265 1266 struct lpfc_mbx_cq_create { 1267 struct mbox_header header; 1268 union { 1269 struct { 1270 uint32_t word0; 1271 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1272 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1273 #define lpfc_mbx_cq_create_page_size_WORD word0 1274 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1275 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1276 #define lpfc_mbx_cq_create_num_pages_WORD word0 1277 struct cq_context context; 1278 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1279 } request; 1280 struct { 1281 uint32_t word0; 1282 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1283 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1284 #define lpfc_mbx_cq_create_q_id_WORD word0 1285 } response; 1286 } u; 1287 }; 1288 1289 struct lpfc_mbx_cq_create_set { 1290 union lpfc_sli4_cfg_shdr cfg_shdr; 1291 union { 1292 struct { 1293 uint32_t word0; 1294 #define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */ 1295 #define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF 1296 #define lpfc_mbx_cq_create_set_page_size_WORD word0 1297 #define lpfc_mbx_cq_create_set_num_pages_SHIFT 0 1298 #define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF 1299 #define lpfc_mbx_cq_create_set_num_pages_WORD word0 1300 uint32_t word1; 1301 #define lpfc_mbx_cq_create_set_evt_SHIFT 31 1302 #define lpfc_mbx_cq_create_set_evt_MASK 0x00000001 1303 #define lpfc_mbx_cq_create_set_evt_WORD word1 1304 #define lpfc_mbx_cq_create_set_valid_SHIFT 29 1305 #define lpfc_mbx_cq_create_set_valid_MASK 0x00000001 1306 #define lpfc_mbx_cq_create_set_valid_WORD word1 1307 #define lpfc_mbx_cq_create_set_cqe_cnt_SHIFT 27 1308 #define lpfc_mbx_cq_create_set_cqe_cnt_MASK 0x00000003 1309 #define lpfc_mbx_cq_create_set_cqe_cnt_WORD word1 1310 #define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25 1311 #define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003 1312 #define lpfc_mbx_cq_create_set_cqe_size_WORD word1 1313 #define lpfc_mbx_cq_create_set_autovalid_SHIFT 15 1314 #define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001 1315 #define lpfc_mbx_cq_create_set_autovalid_WORD word1 1316 #define lpfc_mbx_cq_create_set_nodelay_SHIFT 14 1317 #define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001 1318 #define lpfc_mbx_cq_create_set_nodelay_WORD word1 1319 #define lpfc_mbx_cq_create_set_clswm_SHIFT 12 1320 #define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003 1321 #define lpfc_mbx_cq_create_set_clswm_WORD word1 1322 uint32_t word2; 1323 #define lpfc_mbx_cq_create_set_arm_SHIFT 31 1324 #define lpfc_mbx_cq_create_set_arm_MASK 0x00000001 1325 #define lpfc_mbx_cq_create_set_arm_WORD word2 1326 #define lpfc_mbx_cq_create_set_cq_cnt_SHIFT 16 1327 #define lpfc_mbx_cq_create_set_cq_cnt_MASK 0x00007FFF 1328 #define lpfc_mbx_cq_create_set_cq_cnt_WORD word2 1329 #define lpfc_mbx_cq_create_set_num_cq_SHIFT 0 1330 #define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF 1331 #define lpfc_mbx_cq_create_set_num_cq_WORD word2 1332 uint32_t word3; 1333 #define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16 1334 #define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF 1335 #define lpfc_mbx_cq_create_set_eq_id1_WORD word3 1336 #define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0 1337 #define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF 1338 #define lpfc_mbx_cq_create_set_eq_id0_WORD word3 1339 uint32_t word4; 1340 #define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16 1341 #define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF 1342 #define lpfc_mbx_cq_create_set_eq_id3_WORD word4 1343 #define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0 1344 #define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF 1345 #define lpfc_mbx_cq_create_set_eq_id2_WORD word4 1346 uint32_t word5; 1347 #define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16 1348 #define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF 1349 #define lpfc_mbx_cq_create_set_eq_id5_WORD word5 1350 #define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0 1351 #define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF 1352 #define lpfc_mbx_cq_create_set_eq_id4_WORD word5 1353 uint32_t word6; 1354 #define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16 1355 #define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF 1356 #define lpfc_mbx_cq_create_set_eq_id7_WORD word6 1357 #define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0 1358 #define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF 1359 #define lpfc_mbx_cq_create_set_eq_id6_WORD word6 1360 uint32_t word7; 1361 #define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16 1362 #define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF 1363 #define lpfc_mbx_cq_create_set_eq_id9_WORD word7 1364 #define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0 1365 #define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF 1366 #define lpfc_mbx_cq_create_set_eq_id8_WORD word7 1367 uint32_t word8; 1368 #define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16 1369 #define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF 1370 #define lpfc_mbx_cq_create_set_eq_id11_WORD word8 1371 #define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0 1372 #define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF 1373 #define lpfc_mbx_cq_create_set_eq_id10_WORD word8 1374 uint32_t word9; 1375 #define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16 1376 #define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF 1377 #define lpfc_mbx_cq_create_set_eq_id13_WORD word9 1378 #define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0 1379 #define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF 1380 #define lpfc_mbx_cq_create_set_eq_id12_WORD word9 1381 uint32_t word10; 1382 #define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16 1383 #define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF 1384 #define lpfc_mbx_cq_create_set_eq_id15_WORD word10 1385 #define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0 1386 #define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF 1387 #define lpfc_mbx_cq_create_set_eq_id14_WORD word10 1388 struct dma_address page[1]; 1389 } request; 1390 struct { 1391 uint32_t word0; 1392 #define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16 1393 #define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF 1394 #define lpfc_mbx_cq_create_set_num_alloc_WORD word0 1395 #define lpfc_mbx_cq_create_set_base_id_SHIFT 0 1396 #define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF 1397 #define lpfc_mbx_cq_create_set_base_id_WORD word0 1398 } response; 1399 } u; 1400 }; 1401 1402 struct lpfc_mbx_cq_destroy { 1403 struct mbox_header header; 1404 union { 1405 struct { 1406 uint32_t word0; 1407 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1408 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1409 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1410 } request; 1411 struct { 1412 uint32_t word0; 1413 } response; 1414 } u; 1415 }; 1416 1417 struct wq_context { 1418 uint32_t reserved0; 1419 uint32_t reserved1; 1420 uint32_t reserved2; 1421 uint32_t reserved3; 1422 }; 1423 1424 struct lpfc_mbx_wq_create { 1425 struct mbox_header header; 1426 union { 1427 struct { /* Version 0 Request */ 1428 uint32_t word0; 1429 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1430 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1431 #define lpfc_mbx_wq_create_num_pages_WORD word0 1432 #define lpfc_mbx_wq_create_dua_SHIFT 8 1433 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1434 #define lpfc_mbx_wq_create_dua_WORD word0 1435 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1436 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1437 #define lpfc_mbx_wq_create_cq_id_WORD word0 1438 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1439 uint32_t word9; 1440 #define lpfc_mbx_wq_create_bua_SHIFT 0 1441 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1442 #define lpfc_mbx_wq_create_bua_WORD word9 1443 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1444 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1445 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1446 } request; 1447 struct { /* Version 1 Request */ 1448 uint32_t word0; /* Word 0 is the same as in v0 */ 1449 uint32_t word1; 1450 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1451 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1452 #define lpfc_mbx_wq_create_page_size_WORD word1 1453 #define LPFC_WQ_PAGE_SIZE_4096 0x1 1454 #define lpfc_mbx_wq_create_dpp_req_SHIFT 15 1455 #define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001 1456 #define lpfc_mbx_wq_create_dpp_req_WORD word1 1457 #define lpfc_mbx_wq_create_doe_SHIFT 14 1458 #define lpfc_mbx_wq_create_doe_MASK 0x00000001 1459 #define lpfc_mbx_wq_create_doe_WORD word1 1460 #define lpfc_mbx_wq_create_toe_SHIFT 13 1461 #define lpfc_mbx_wq_create_toe_MASK 0x00000001 1462 #define lpfc_mbx_wq_create_toe_WORD word1 1463 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1464 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1465 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1466 #define LPFC_WQ_WQE_SIZE_64 0x5 1467 #define LPFC_WQ_WQE_SIZE_128 0x6 1468 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1469 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1470 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1471 uint32_t word2; 1472 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1473 } request_1; 1474 struct { 1475 uint32_t word0; 1476 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1477 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1478 #define lpfc_mbx_wq_create_q_id_WORD word0 1479 uint32_t doorbell_offset; 1480 uint32_t word2; 1481 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1482 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1483 #define lpfc_mbx_wq_create_bar_set_WORD word2 1484 #define WQ_PCI_BAR_0_AND_1 0x00 1485 #define WQ_PCI_BAR_2_AND_3 0x01 1486 #define WQ_PCI_BAR_4_AND_5 0x02 1487 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1488 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1489 #define lpfc_mbx_wq_create_db_format_WORD word2 1490 } response; 1491 struct { 1492 uint32_t word0; 1493 #define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31 1494 #define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001 1495 #define lpfc_mbx_wq_create_dpp_rsp_WORD word0 1496 #define lpfc_mbx_wq_create_v1_q_id_SHIFT 0 1497 #define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF 1498 #define lpfc_mbx_wq_create_v1_q_id_WORD word0 1499 uint32_t word1; 1500 #define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0 1501 #define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F 1502 #define lpfc_mbx_wq_create_v1_bar_set_WORD word1 1503 uint32_t doorbell_offset; 1504 uint32_t word3; 1505 #define lpfc_mbx_wq_create_dpp_id_SHIFT 16 1506 #define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F 1507 #define lpfc_mbx_wq_create_dpp_id_WORD word3 1508 #define lpfc_mbx_wq_create_dpp_bar_SHIFT 0 1509 #define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F 1510 #define lpfc_mbx_wq_create_dpp_bar_WORD word3 1511 uint32_t dpp_offset; 1512 } response_1; 1513 } u; 1514 }; 1515 1516 struct lpfc_mbx_wq_destroy { 1517 struct mbox_header header; 1518 union { 1519 struct { 1520 uint32_t word0; 1521 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1522 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1523 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1524 } request; 1525 struct { 1526 uint32_t word0; 1527 } response; 1528 } u; 1529 }; 1530 1531 #define LPFC_HDR_BUF_SIZE 128 1532 #define LPFC_DATA_BUF_SIZE 2048 1533 #define LPFC_NVMET_DATA_BUF_SIZE 128 1534 struct rq_context { 1535 uint32_t word0; 1536 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1537 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1538 #define lpfc_rq_context_rqe_count_WORD word0 1539 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1540 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1541 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1542 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1543 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */ 1544 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1545 #define lpfc_rq_context_rqe_count_1_WORD word0 1546 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */ 1547 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1548 #define lpfc_rq_context_rqe_size_WORD word0 1549 #define LPFC_RQE_SIZE_8 2 1550 #define LPFC_RQE_SIZE_16 3 1551 #define LPFC_RQE_SIZE_32 4 1552 #define LPFC_RQE_SIZE_64 5 1553 #define LPFC_RQE_SIZE_128 6 1554 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1555 #define lpfc_rq_context_page_size_MASK 0x000000FF 1556 #define lpfc_rq_context_page_size_WORD word0 1557 #define LPFC_RQ_PAGE_SIZE_4096 0x1 1558 uint32_t word1; 1559 #define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */ 1560 #define lpfc_rq_context_data_size_MASK 0x0000FFFF 1561 #define lpfc_rq_context_data_size_WORD word1 1562 #define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */ 1563 #define lpfc_rq_context_hdr_size_MASK 0x0000FFFF 1564 #define lpfc_rq_context_hdr_size_WORD word1 1565 uint32_t word2; 1566 #define lpfc_rq_context_cq_id_SHIFT 16 1567 #define lpfc_rq_context_cq_id_MASK 0x0000FFFF 1568 #define lpfc_rq_context_cq_id_WORD word2 1569 #define lpfc_rq_context_buf_size_SHIFT 0 1570 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1571 #define lpfc_rq_context_buf_size_WORD word2 1572 #define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */ 1573 #define lpfc_rq_context_base_cq_MASK 0x0000FFFF 1574 #define lpfc_rq_context_base_cq_WORD word2 1575 uint32_t buffer_size; /* Version 1 Only */ 1576 }; 1577 1578 struct lpfc_mbx_rq_create { 1579 struct mbox_header header; 1580 union { 1581 struct { 1582 uint32_t word0; 1583 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1584 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1585 #define lpfc_mbx_rq_create_num_pages_WORD word0 1586 #define lpfc_mbx_rq_create_dua_SHIFT 16 1587 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1588 #define lpfc_mbx_rq_create_dua_WORD word0 1589 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1590 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1591 #define lpfc_mbx_rq_create_bqu_WORD word0 1592 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1593 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1594 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1595 struct rq_context context; 1596 struct dma_address page[LPFC_MAX_RQ_PAGE]; 1597 } request; 1598 struct { 1599 uint32_t word0; 1600 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1601 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1602 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1603 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1604 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1605 #define lpfc_mbx_rq_create_q_id_WORD word0 1606 uint32_t doorbell_offset; 1607 uint32_t word2; 1608 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1609 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1610 #define lpfc_mbx_rq_create_bar_set_WORD word2 1611 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1612 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1613 #define lpfc_mbx_rq_create_db_format_WORD word2 1614 } response; 1615 } u; 1616 }; 1617 1618 struct lpfc_mbx_rq_create_v2 { 1619 union lpfc_sli4_cfg_shdr cfg_shdr; 1620 union { 1621 struct { 1622 uint32_t word0; 1623 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1624 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1625 #define lpfc_mbx_rq_create_num_pages_WORD word0 1626 #define lpfc_mbx_rq_create_rq_cnt_SHIFT 16 1627 #define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF 1628 #define lpfc_mbx_rq_create_rq_cnt_WORD word0 1629 #define lpfc_mbx_rq_create_dua_SHIFT 16 1630 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1631 #define lpfc_mbx_rq_create_dua_WORD word0 1632 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1633 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1634 #define lpfc_mbx_rq_create_bqu_WORD word0 1635 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1636 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1637 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1638 #define lpfc_mbx_rq_create_dim_SHIFT 29 1639 #define lpfc_mbx_rq_create_dim_MASK 0x00000001 1640 #define lpfc_mbx_rq_create_dim_WORD word0 1641 #define lpfc_mbx_rq_create_dfd_SHIFT 30 1642 #define lpfc_mbx_rq_create_dfd_MASK 0x00000001 1643 #define lpfc_mbx_rq_create_dfd_WORD word0 1644 #define lpfc_mbx_rq_create_dnb_SHIFT 31 1645 #define lpfc_mbx_rq_create_dnb_MASK 0x00000001 1646 #define lpfc_mbx_rq_create_dnb_WORD word0 1647 struct rq_context context; 1648 struct dma_address page[1]; 1649 } request; 1650 struct { 1651 uint32_t word0; 1652 #define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16 1653 #define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF 1654 #define lpfc_mbx_rq_create_q_cnt_v2_WORD word0 1655 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1656 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1657 #define lpfc_mbx_rq_create_q_id_WORD word0 1658 uint32_t doorbell_offset; 1659 uint32_t word2; 1660 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1661 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1662 #define lpfc_mbx_rq_create_bar_set_WORD word2 1663 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1664 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1665 #define lpfc_mbx_rq_create_db_format_WORD word2 1666 } response; 1667 } u; 1668 }; 1669 1670 struct lpfc_mbx_rq_destroy { 1671 struct mbox_header header; 1672 union { 1673 struct { 1674 uint32_t word0; 1675 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1676 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1677 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1678 } request; 1679 struct { 1680 uint32_t word0; 1681 } response; 1682 } u; 1683 }; 1684 1685 struct mq_context { 1686 uint32_t word0; 1687 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1688 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1689 #define lpfc_mq_context_cq_id_WORD word0 1690 #define lpfc_mq_context_ring_size_SHIFT 16 1691 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1692 #define lpfc_mq_context_ring_size_WORD word0 1693 #define LPFC_MQ_RING_SIZE_16 0x5 1694 #define LPFC_MQ_RING_SIZE_32 0x6 1695 #define LPFC_MQ_RING_SIZE_64 0x7 1696 #define LPFC_MQ_RING_SIZE_128 0x8 1697 uint32_t word1; 1698 #define lpfc_mq_context_valid_SHIFT 31 1699 #define lpfc_mq_context_valid_MASK 0x00000001 1700 #define lpfc_mq_context_valid_WORD word1 1701 uint32_t reserved2; 1702 uint32_t reserved3; 1703 }; 1704 1705 struct lpfc_mbx_mq_create { 1706 struct mbox_header header; 1707 union { 1708 struct { 1709 uint32_t word0; 1710 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1711 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1712 #define lpfc_mbx_mq_create_num_pages_WORD word0 1713 struct mq_context context; 1714 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1715 } request; 1716 struct { 1717 uint32_t word0; 1718 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1719 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1720 #define lpfc_mbx_mq_create_q_id_WORD word0 1721 } response; 1722 } u; 1723 }; 1724 1725 struct lpfc_mbx_mq_create_ext { 1726 struct mbox_header header; 1727 union { 1728 struct { 1729 uint32_t word0; 1730 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1731 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1732 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1733 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1734 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1735 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1736 uint32_t async_evt_bmap; 1737 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1738 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1739 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1740 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1741 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1742 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1743 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1744 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1745 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1746 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1747 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1748 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1749 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1750 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1751 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1752 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1753 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1754 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1755 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1756 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1757 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1758 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1759 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1760 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1761 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1762 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1763 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1764 struct mq_context context; 1765 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1766 } request; 1767 struct { 1768 uint32_t word0; 1769 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1770 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1771 #define lpfc_mbx_mq_create_q_id_WORD word0 1772 } response; 1773 } u; 1774 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1775 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1776 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1777 }; 1778 1779 struct lpfc_mbx_mq_destroy { 1780 struct mbox_header header; 1781 union { 1782 struct { 1783 uint32_t word0; 1784 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1785 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1786 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1787 } request; 1788 struct { 1789 uint32_t word0; 1790 } response; 1791 } u; 1792 }; 1793 1794 /* Start Gen 2 SLI4 Mailbox definitions: */ 1795 1796 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1797 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1798 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1799 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1800 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1801 1802 struct lpfc_mbx_get_rsrc_extent_info { 1803 struct mbox_header header; 1804 union { 1805 struct { 1806 uint32_t word4; 1807 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1808 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1809 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1810 } req; 1811 struct { 1812 uint32_t word4; 1813 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1814 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1815 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1816 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1817 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1818 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1819 } rsp; 1820 } u; 1821 }; 1822 1823 struct lpfc_mbx_query_fw_config { 1824 struct mbox_header header; 1825 struct { 1826 uint32_t config_number; 1827 #define LPFC_FC_FCOE 0x00000007 1828 uint32_t asic_revision; 1829 uint32_t physical_port; 1830 uint32_t function_mode; 1831 #define LPFC_FCOE_INI_MODE 0x00000040 1832 #define LPFC_FCOE_TGT_MODE 0x00000080 1833 #define LPFC_DUA_MODE 0x00000800 1834 uint32_t ulp0_mode; 1835 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1836 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1837 uint32_t ulp0_nap_words[12]; 1838 uint32_t ulp1_mode; 1839 uint32_t ulp1_nap_words[12]; 1840 uint32_t function_capabilities; 1841 uint32_t cqid_base; 1842 uint32_t cqid_tot; 1843 uint32_t eqid_base; 1844 uint32_t eqid_tot; 1845 uint32_t ulp0_nap2_words[2]; 1846 uint32_t ulp1_nap2_words[2]; 1847 } rsp; 1848 }; 1849 1850 struct lpfc_mbx_set_beacon_config { 1851 struct mbox_header header; 1852 uint32_t word4; 1853 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1854 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1855 #define lpfc_mbx_set_beacon_port_num_WORD word4 1856 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1857 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1858 #define lpfc_mbx_set_beacon_port_type_WORD word4 1859 #define lpfc_mbx_set_beacon_state_SHIFT 8 1860 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1861 #define lpfc_mbx_set_beacon_state_WORD word4 1862 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1863 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1864 #define lpfc_mbx_set_beacon_duration_WORD word4 1865 1866 /* COMMON_SET_BEACON_CONFIG_V1 */ 1867 #define lpfc_mbx_set_beacon_duration_v1_SHIFT 16 1868 #define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF 1869 #define lpfc_mbx_set_beacon_duration_v1_WORD word4 1870 uint32_t word5; /* RESERVED */ 1871 }; 1872 1873 struct lpfc_id_range { 1874 uint32_t word5; 1875 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1876 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1877 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1878 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1879 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1880 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1881 }; 1882 1883 struct lpfc_mbx_set_link_diag_state { 1884 struct mbox_header header; 1885 union { 1886 struct { 1887 uint32_t word0; 1888 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1889 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1890 #define lpfc_mbx_set_diag_state_diag_WORD word0 1891 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1892 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1893 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1894 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1895 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1896 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1897 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1898 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1899 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1900 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1901 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1902 } req; 1903 struct { 1904 uint32_t word0; 1905 } rsp; 1906 } u; 1907 }; 1908 1909 struct lpfc_mbx_set_link_diag_loopback { 1910 struct mbox_header header; 1911 union { 1912 struct { 1913 uint32_t word0; 1914 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1915 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1916 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1917 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1918 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1919 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1920 #define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3 1921 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1922 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1923 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1924 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1925 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1926 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1927 } req; 1928 struct { 1929 uint32_t word0; 1930 } rsp; 1931 } u; 1932 }; 1933 1934 struct lpfc_mbx_run_link_diag_test { 1935 struct mbox_header header; 1936 union { 1937 struct { 1938 uint32_t word0; 1939 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1940 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1941 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1942 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1943 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1944 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1945 uint32_t word1; 1946 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1947 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1948 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1949 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1950 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1951 #define lpfc_mbx_run_diag_test_loops_WORD word1 1952 uint32_t word2; 1953 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1954 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1955 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1956 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1957 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1958 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1959 } req; 1960 struct { 1961 uint32_t word0; 1962 } rsp; 1963 } u; 1964 }; 1965 1966 /* 1967 * struct lpfc_mbx_alloc_rsrc_extents: 1968 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1969 * 6 words of header + 4 words of shared subcommand header + 1970 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1971 * 1972 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1973 * for extents payload. 1974 * 1975 * 212/2 (bytes per extent) = 106 extents. 1976 * 106/2 (extents per word) = 53 words. 1977 * lpfc_id_range id is statically size to 53. 1978 * 1979 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1980 * extent ranges. For ALLOC, the type and cnt are required. 1981 * For GET_ALLOCATED, only the type is required. 1982 */ 1983 struct lpfc_mbx_alloc_rsrc_extents { 1984 struct mbox_header header; 1985 union { 1986 struct { 1987 uint32_t word4; 1988 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1989 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1990 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1991 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1992 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1993 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1994 } req; 1995 struct { 1996 uint32_t word4; 1997 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1998 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1999 #define lpfc_mbx_rsrc_cnt_WORD word4 2000 struct lpfc_id_range id[53]; 2001 } rsp; 2002 } u; 2003 }; 2004 2005 /* 2006 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 2007 * structure shares the same SHIFT/MASK/WORD defines provided in the 2008 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 2009 * the structures defined above. This non-embedded structure provides for the 2010 * maximum number of extents supported by the port. 2011 */ 2012 struct lpfc_mbx_nembed_rsrc_extent { 2013 union lpfc_sli4_cfg_shdr cfg_shdr; 2014 uint32_t word4; 2015 struct lpfc_id_range id; 2016 }; 2017 2018 struct lpfc_mbx_dealloc_rsrc_extents { 2019 struct mbox_header header; 2020 struct { 2021 uint32_t word4; 2022 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 2023 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 2024 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 2025 } req; 2026 2027 }; 2028 2029 /* Start SLI4 FCoE specific mbox structures. */ 2030 2031 struct lpfc_mbx_post_hdr_tmpl { 2032 struct mbox_header header; 2033 uint32_t word10; 2034 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 2035 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 2036 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 2037 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 2038 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 2039 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 2040 uint32_t rpi_paddr_lo; 2041 uint32_t rpi_paddr_hi; 2042 }; 2043 2044 struct sli4_sge { /* SLI-4 */ 2045 uint32_t addr_hi; 2046 uint32_t addr_lo; 2047 2048 uint32_t word2; 2049 #define lpfc_sli4_sge_offset_SHIFT 0 2050 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 2051 #define lpfc_sli4_sge_offset_WORD word2 2052 #define lpfc_sli4_sge_type_SHIFT 27 2053 #define lpfc_sli4_sge_type_MASK 0x0000000F 2054 #define lpfc_sli4_sge_type_WORD word2 2055 #define LPFC_SGE_TYPE_DATA 0x0 2056 #define LPFC_SGE_TYPE_DIF 0x4 2057 #define LPFC_SGE_TYPE_LSP 0x5 2058 #define LPFC_SGE_TYPE_PEDIF 0x6 2059 #define LPFC_SGE_TYPE_PESEED 0x7 2060 #define LPFC_SGE_TYPE_DISEED 0x8 2061 #define LPFC_SGE_TYPE_ENC 0x9 2062 #define LPFC_SGE_TYPE_ATM 0xA 2063 #define LPFC_SGE_TYPE_SKIP 0xC 2064 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2065 #define lpfc_sli4_sge_last_MASK 0x00000001 2066 #define lpfc_sli4_sge_last_WORD word2 2067 uint32_t sge_len; 2068 }; 2069 2070 struct sli4_hybrid_sgl { 2071 struct list_head list_node; 2072 struct sli4_sge *dma_sgl; 2073 dma_addr_t dma_phys_sgl; 2074 }; 2075 2076 struct fcp_cmd_rsp_buf { 2077 struct list_head list_node; 2078 2079 /* for storing cmd/rsp dma alloc'ed virt_addr */ 2080 struct fcp_cmnd *fcp_cmnd; 2081 struct fcp_rsp *fcp_rsp; 2082 2083 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */ 2084 dma_addr_t fcp_cmd_rsp_dma_handle; 2085 }; 2086 2087 struct sli4_sge_diseed { /* SLI-4 */ 2088 uint32_t ref_tag; 2089 uint32_t ref_tag_tran; 2090 2091 uint32_t word2; 2092 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 2093 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 2094 #define lpfc_sli4_sge_dif_apptran_WORD word2 2095 #define lpfc_sli4_sge_dif_af_SHIFT 24 2096 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 2097 #define lpfc_sli4_sge_dif_af_WORD word2 2098 #define lpfc_sli4_sge_dif_na_SHIFT 25 2099 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 2100 #define lpfc_sli4_sge_dif_na_WORD word2 2101 #define lpfc_sli4_sge_dif_hi_SHIFT 26 2102 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 2103 #define lpfc_sli4_sge_dif_hi_WORD word2 2104 #define lpfc_sli4_sge_dif_type_SHIFT 27 2105 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 2106 #define lpfc_sli4_sge_dif_type_WORD word2 2107 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 2108 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 2109 #define lpfc_sli4_sge_dif_last_WORD word2 2110 uint32_t word3; 2111 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 2112 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 2113 #define lpfc_sli4_sge_dif_apptag_WORD word3 2114 #define lpfc_sli4_sge_dif_bs_SHIFT 16 2115 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 2116 #define lpfc_sli4_sge_dif_bs_WORD word3 2117 #define lpfc_sli4_sge_dif_ai_SHIFT 19 2118 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 2119 #define lpfc_sli4_sge_dif_ai_WORD word3 2120 #define lpfc_sli4_sge_dif_me_SHIFT 20 2121 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 2122 #define lpfc_sli4_sge_dif_me_WORD word3 2123 #define lpfc_sli4_sge_dif_re_SHIFT 21 2124 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 2125 #define lpfc_sli4_sge_dif_re_WORD word3 2126 #define lpfc_sli4_sge_dif_ce_SHIFT 22 2127 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 2128 #define lpfc_sli4_sge_dif_ce_WORD word3 2129 #define lpfc_sli4_sge_dif_nr_SHIFT 23 2130 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 2131 #define lpfc_sli4_sge_dif_nr_WORD word3 2132 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 2133 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 2134 #define lpfc_sli4_sge_dif_oprx_WORD word3 2135 #define lpfc_sli4_sge_dif_optx_SHIFT 28 2136 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 2137 #define lpfc_sli4_sge_dif_optx_WORD word3 2138 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 2139 }; 2140 2141 struct fcf_record { 2142 uint32_t max_rcv_size; 2143 uint32_t fka_adv_period; 2144 uint32_t fip_priority; 2145 uint32_t word3; 2146 #define lpfc_fcf_record_mac_0_SHIFT 0 2147 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 2148 #define lpfc_fcf_record_mac_0_WORD word3 2149 #define lpfc_fcf_record_mac_1_SHIFT 8 2150 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 2151 #define lpfc_fcf_record_mac_1_WORD word3 2152 #define lpfc_fcf_record_mac_2_SHIFT 16 2153 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 2154 #define lpfc_fcf_record_mac_2_WORD word3 2155 #define lpfc_fcf_record_mac_3_SHIFT 24 2156 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 2157 #define lpfc_fcf_record_mac_3_WORD word3 2158 uint32_t word4; 2159 #define lpfc_fcf_record_mac_4_SHIFT 0 2160 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 2161 #define lpfc_fcf_record_mac_4_WORD word4 2162 #define lpfc_fcf_record_mac_5_SHIFT 8 2163 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 2164 #define lpfc_fcf_record_mac_5_WORD word4 2165 #define lpfc_fcf_record_fcf_avail_SHIFT 16 2166 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 2167 #define lpfc_fcf_record_fcf_avail_WORD word4 2168 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 2169 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 2170 #define lpfc_fcf_record_mac_addr_prov_WORD word4 2171 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 2172 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 2173 uint32_t word5; 2174 #define lpfc_fcf_record_fab_name_0_SHIFT 0 2175 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 2176 #define lpfc_fcf_record_fab_name_0_WORD word5 2177 #define lpfc_fcf_record_fab_name_1_SHIFT 8 2178 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 2179 #define lpfc_fcf_record_fab_name_1_WORD word5 2180 #define lpfc_fcf_record_fab_name_2_SHIFT 16 2181 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 2182 #define lpfc_fcf_record_fab_name_2_WORD word5 2183 #define lpfc_fcf_record_fab_name_3_SHIFT 24 2184 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 2185 #define lpfc_fcf_record_fab_name_3_WORD word5 2186 uint32_t word6; 2187 #define lpfc_fcf_record_fab_name_4_SHIFT 0 2188 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 2189 #define lpfc_fcf_record_fab_name_4_WORD word6 2190 #define lpfc_fcf_record_fab_name_5_SHIFT 8 2191 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 2192 #define lpfc_fcf_record_fab_name_5_WORD word6 2193 #define lpfc_fcf_record_fab_name_6_SHIFT 16 2194 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 2195 #define lpfc_fcf_record_fab_name_6_WORD word6 2196 #define lpfc_fcf_record_fab_name_7_SHIFT 24 2197 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 2198 #define lpfc_fcf_record_fab_name_7_WORD word6 2199 uint32_t word7; 2200 #define lpfc_fcf_record_fc_map_0_SHIFT 0 2201 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 2202 #define lpfc_fcf_record_fc_map_0_WORD word7 2203 #define lpfc_fcf_record_fc_map_1_SHIFT 8 2204 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 2205 #define lpfc_fcf_record_fc_map_1_WORD word7 2206 #define lpfc_fcf_record_fc_map_2_SHIFT 16 2207 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 2208 #define lpfc_fcf_record_fc_map_2_WORD word7 2209 #define lpfc_fcf_record_fcf_valid_SHIFT 24 2210 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 2211 #define lpfc_fcf_record_fcf_valid_WORD word7 2212 #define lpfc_fcf_record_fcf_fc_SHIFT 25 2213 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 2214 #define lpfc_fcf_record_fcf_fc_WORD word7 2215 #define lpfc_fcf_record_fcf_sol_SHIFT 31 2216 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 2217 #define lpfc_fcf_record_fcf_sol_WORD word7 2218 uint32_t word8; 2219 #define lpfc_fcf_record_fcf_index_SHIFT 0 2220 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 2221 #define lpfc_fcf_record_fcf_index_WORD word8 2222 #define lpfc_fcf_record_fcf_state_SHIFT 16 2223 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 2224 #define lpfc_fcf_record_fcf_state_WORD word8 2225 uint8_t vlan_bitmap[512]; 2226 uint32_t word137; 2227 #define lpfc_fcf_record_switch_name_0_SHIFT 0 2228 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 2229 #define lpfc_fcf_record_switch_name_0_WORD word137 2230 #define lpfc_fcf_record_switch_name_1_SHIFT 8 2231 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 2232 #define lpfc_fcf_record_switch_name_1_WORD word137 2233 #define lpfc_fcf_record_switch_name_2_SHIFT 16 2234 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 2235 #define lpfc_fcf_record_switch_name_2_WORD word137 2236 #define lpfc_fcf_record_switch_name_3_SHIFT 24 2237 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 2238 #define lpfc_fcf_record_switch_name_3_WORD word137 2239 uint32_t word138; 2240 #define lpfc_fcf_record_switch_name_4_SHIFT 0 2241 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 2242 #define lpfc_fcf_record_switch_name_4_WORD word138 2243 #define lpfc_fcf_record_switch_name_5_SHIFT 8 2244 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 2245 #define lpfc_fcf_record_switch_name_5_WORD word138 2246 #define lpfc_fcf_record_switch_name_6_SHIFT 16 2247 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 2248 #define lpfc_fcf_record_switch_name_6_WORD word138 2249 #define lpfc_fcf_record_switch_name_7_SHIFT 24 2250 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 2251 #define lpfc_fcf_record_switch_name_7_WORD word138 2252 }; 2253 2254 struct lpfc_mbx_read_fcf_tbl { 2255 union lpfc_sli4_cfg_shdr cfg_shdr; 2256 union { 2257 struct { 2258 uint32_t word10; 2259 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 2260 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 2261 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 2262 } request; 2263 struct { 2264 uint32_t eventag; 2265 } response; 2266 } u; 2267 uint32_t word11; 2268 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 2269 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 2270 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 2271 }; 2272 2273 struct lpfc_mbx_add_fcf_tbl_entry { 2274 union lpfc_sli4_cfg_shdr cfg_shdr; 2275 uint32_t word10; 2276 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 2277 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 2278 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 2279 struct lpfc_mbx_sge fcf_sge; 2280 }; 2281 2282 struct lpfc_mbx_del_fcf_tbl_entry { 2283 struct mbox_header header; 2284 uint32_t word10; 2285 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 2286 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 2287 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 2288 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 2289 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 2290 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 2291 }; 2292 2293 struct lpfc_mbx_redisc_fcf_tbl { 2294 struct mbox_header header; 2295 uint32_t word10; 2296 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 2297 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 2298 #define lpfc_mbx_redisc_fcf_count_WORD word10 2299 uint32_t resvd; 2300 uint32_t word12; 2301 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 2302 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 2303 #define lpfc_mbx_redisc_fcf_index_WORD word12 2304 }; 2305 2306 /* Status field for embedded SLI_CONFIG mailbox command */ 2307 #define STATUS_SUCCESS 0x0 2308 #define STATUS_FAILED 0x1 2309 #define STATUS_ILLEGAL_REQUEST 0x2 2310 #define STATUS_ILLEGAL_FIELD 0x3 2311 #define STATUS_INSUFFICIENT_BUFFER 0x4 2312 #define STATUS_UNAUTHORIZED_REQUEST 0x5 2313 #define STATUS_FLASHROM_SAVE_FAILED 0x17 2314 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 2315 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 2316 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 2317 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 2318 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 2319 #define STATUS_ASSERT_FAILED 0x1e 2320 #define STATUS_INVALID_SESSION 0x1f 2321 #define STATUS_INVALID_CONNECTION 0x20 2322 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 2323 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 2324 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 2325 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 2326 #define STATUS_FLASHROM_READ_FAILED 0x27 2327 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 2328 #define STATUS_ERROR_ACITMAIN 0x2a 2329 #define STATUS_REBOOT_REQUIRED 0x2c 2330 #define STATUS_FCF_IN_USE 0x3a 2331 #define STATUS_FCF_TABLE_EMPTY 0x43 2332 2333 /* 2334 * Additional status field for embedded SLI_CONFIG mailbox 2335 * command. 2336 */ 2337 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 2338 #define ADD_STATUS_FW_NOT_SUPPORTED 0xEB 2339 #define ADD_STATUS_INVALID_REQUEST 0x4B 2340 #define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58 2341 2342 struct lpfc_mbx_sli4_config { 2343 struct mbox_header header; 2344 }; 2345 2346 struct lpfc_mbx_init_vfi { 2347 uint32_t word1; 2348 #define lpfc_init_vfi_vr_SHIFT 31 2349 #define lpfc_init_vfi_vr_MASK 0x00000001 2350 #define lpfc_init_vfi_vr_WORD word1 2351 #define lpfc_init_vfi_vt_SHIFT 30 2352 #define lpfc_init_vfi_vt_MASK 0x00000001 2353 #define lpfc_init_vfi_vt_WORD word1 2354 #define lpfc_init_vfi_vf_SHIFT 29 2355 #define lpfc_init_vfi_vf_MASK 0x00000001 2356 #define lpfc_init_vfi_vf_WORD word1 2357 #define lpfc_init_vfi_vp_SHIFT 28 2358 #define lpfc_init_vfi_vp_MASK 0x00000001 2359 #define lpfc_init_vfi_vp_WORD word1 2360 #define lpfc_init_vfi_vfi_SHIFT 0 2361 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 2362 #define lpfc_init_vfi_vfi_WORD word1 2363 uint32_t word2; 2364 #define lpfc_init_vfi_vpi_SHIFT 16 2365 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 2366 #define lpfc_init_vfi_vpi_WORD word2 2367 #define lpfc_init_vfi_fcfi_SHIFT 0 2368 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 2369 #define lpfc_init_vfi_fcfi_WORD word2 2370 uint32_t word3; 2371 #define lpfc_init_vfi_pri_SHIFT 13 2372 #define lpfc_init_vfi_pri_MASK 0x00000007 2373 #define lpfc_init_vfi_pri_WORD word3 2374 #define lpfc_init_vfi_vf_id_SHIFT 1 2375 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 2376 #define lpfc_init_vfi_vf_id_WORD word3 2377 uint32_t word4; 2378 #define lpfc_init_vfi_hop_count_SHIFT 24 2379 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 2380 #define lpfc_init_vfi_hop_count_WORD word4 2381 }; 2382 #define MBX_VFI_IN_USE 0x9F02 2383 2384 2385 struct lpfc_mbx_reg_vfi { 2386 uint32_t word1; 2387 #define lpfc_reg_vfi_upd_SHIFT 29 2388 #define lpfc_reg_vfi_upd_MASK 0x00000001 2389 #define lpfc_reg_vfi_upd_WORD word1 2390 #define lpfc_reg_vfi_vp_SHIFT 28 2391 #define lpfc_reg_vfi_vp_MASK 0x00000001 2392 #define lpfc_reg_vfi_vp_WORD word1 2393 #define lpfc_reg_vfi_vfi_SHIFT 0 2394 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2395 #define lpfc_reg_vfi_vfi_WORD word1 2396 uint32_t word2; 2397 #define lpfc_reg_vfi_vpi_SHIFT 16 2398 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2399 #define lpfc_reg_vfi_vpi_WORD word2 2400 #define lpfc_reg_vfi_fcfi_SHIFT 0 2401 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2402 #define lpfc_reg_vfi_fcfi_WORD word2 2403 uint32_t wwn[2]; 2404 struct ulp_bde64 bde; 2405 uint32_t e_d_tov; 2406 uint32_t r_a_tov; 2407 uint32_t word10; 2408 #define lpfc_reg_vfi_nport_id_SHIFT 0 2409 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2410 #define lpfc_reg_vfi_nport_id_WORD word10 2411 #define lpfc_reg_vfi_bbcr_SHIFT 27 2412 #define lpfc_reg_vfi_bbcr_MASK 0x00000001 2413 #define lpfc_reg_vfi_bbcr_WORD word10 2414 #define lpfc_reg_vfi_bbscn_SHIFT 28 2415 #define lpfc_reg_vfi_bbscn_MASK 0x0000000F 2416 #define lpfc_reg_vfi_bbscn_WORD word10 2417 }; 2418 2419 struct lpfc_mbx_init_vpi { 2420 uint32_t word1; 2421 #define lpfc_init_vpi_vfi_SHIFT 16 2422 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2423 #define lpfc_init_vpi_vfi_WORD word1 2424 #define lpfc_init_vpi_vpi_SHIFT 0 2425 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2426 #define lpfc_init_vpi_vpi_WORD word1 2427 }; 2428 2429 struct lpfc_mbx_read_vpi { 2430 uint32_t word1_rsvd; 2431 uint32_t word2; 2432 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2433 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2434 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2435 uint32_t word3_rsvd; 2436 uint32_t word4; 2437 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2438 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2439 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2440 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2441 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2442 #define lpfc_mbx_read_vpi_pb_WORD word4 2443 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2444 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2445 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2446 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2447 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2448 #define lpfc_mbx_read_vpi_ns_WORD word4 2449 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2450 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2451 #define lpfc_mbx_read_vpi_hl_WORD word4 2452 uint32_t word5_rsvd; 2453 uint32_t word6; 2454 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2455 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2456 #define lpfc_mbx_read_vpi_vpi_WORD word6 2457 uint32_t word7; 2458 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2459 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2460 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2461 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2462 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2463 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2464 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2465 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2466 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2467 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2468 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2469 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2470 uint32_t word8; 2471 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2472 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2473 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2474 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2475 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2476 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2477 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2478 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2479 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2480 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2481 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2482 #define lpfc_mbx_read_vpi_vv_WORD word8 2483 }; 2484 2485 struct lpfc_mbx_unreg_vfi { 2486 uint32_t word1_rsvd; 2487 uint32_t word2; 2488 #define lpfc_unreg_vfi_vfi_SHIFT 0 2489 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2490 #define lpfc_unreg_vfi_vfi_WORD word2 2491 }; 2492 2493 struct lpfc_mbx_resume_rpi { 2494 uint32_t word1; 2495 #define lpfc_resume_rpi_index_SHIFT 0 2496 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2497 #define lpfc_resume_rpi_index_WORD word1 2498 #define lpfc_resume_rpi_ii_SHIFT 30 2499 #define lpfc_resume_rpi_ii_MASK 0x00000003 2500 #define lpfc_resume_rpi_ii_WORD word1 2501 #define RESUME_INDEX_RPI 0 2502 #define RESUME_INDEX_VPI 1 2503 #define RESUME_INDEX_VFI 2 2504 #define RESUME_INDEX_FCFI 3 2505 uint32_t event_tag; 2506 }; 2507 2508 #define REG_FCF_INVALID_QID 0xFFFF 2509 struct lpfc_mbx_reg_fcfi { 2510 uint32_t word1; 2511 #define lpfc_reg_fcfi_info_index_SHIFT 0 2512 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2513 #define lpfc_reg_fcfi_info_index_WORD word1 2514 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2515 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2516 #define lpfc_reg_fcfi_fcfi_WORD word1 2517 uint32_t word2; 2518 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2519 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2520 #define lpfc_reg_fcfi_rq_id1_WORD word2 2521 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2522 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2523 #define lpfc_reg_fcfi_rq_id0_WORD word2 2524 uint32_t word3; 2525 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2526 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2527 #define lpfc_reg_fcfi_rq_id3_WORD word3 2528 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2529 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2530 #define lpfc_reg_fcfi_rq_id2_WORD word3 2531 uint32_t word4; 2532 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2533 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2534 #define lpfc_reg_fcfi_type_match0_WORD word4 2535 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2536 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2537 #define lpfc_reg_fcfi_type_mask0_WORD word4 2538 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2539 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2540 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2541 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2542 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2543 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2544 uint32_t word5; 2545 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2546 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2547 #define lpfc_reg_fcfi_type_match1_WORD word5 2548 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2549 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2550 #define lpfc_reg_fcfi_type_mask1_WORD word5 2551 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2552 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2553 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2554 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2555 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2556 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2557 uint32_t word6; 2558 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2559 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2560 #define lpfc_reg_fcfi_type_match2_WORD word6 2561 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2562 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2563 #define lpfc_reg_fcfi_type_mask2_WORD word6 2564 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2565 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2566 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2567 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2568 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2569 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2570 uint32_t word7; 2571 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2572 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2573 #define lpfc_reg_fcfi_type_match3_WORD word7 2574 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2575 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2576 #define lpfc_reg_fcfi_type_mask3_WORD word7 2577 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2578 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2579 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2580 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2581 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2582 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2583 uint32_t word8; 2584 #define lpfc_reg_fcfi_mam_SHIFT 13 2585 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2586 #define lpfc_reg_fcfi_mam_WORD word8 2587 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2588 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2589 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2590 #define lpfc_reg_fcfi_vv_SHIFT 12 2591 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2592 #define lpfc_reg_fcfi_vv_WORD word8 2593 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2594 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2595 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2596 }; 2597 2598 struct lpfc_mbx_reg_fcfi_mrq { 2599 uint32_t word1; 2600 #define lpfc_reg_fcfi_mrq_info_index_SHIFT 0 2601 #define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF 2602 #define lpfc_reg_fcfi_mrq_info_index_WORD word1 2603 #define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16 2604 #define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF 2605 #define lpfc_reg_fcfi_mrq_fcfi_WORD word1 2606 uint32_t word2; 2607 #define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0 2608 #define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF 2609 #define lpfc_reg_fcfi_mrq_rq_id1_WORD word2 2610 #define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16 2611 #define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF 2612 #define lpfc_reg_fcfi_mrq_rq_id0_WORD word2 2613 uint32_t word3; 2614 #define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0 2615 #define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF 2616 #define lpfc_reg_fcfi_mrq_rq_id3_WORD word3 2617 #define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16 2618 #define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF 2619 #define lpfc_reg_fcfi_mrq_rq_id2_WORD word3 2620 uint32_t word4; 2621 #define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24 2622 #define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF 2623 #define lpfc_reg_fcfi_mrq_type_match0_WORD word4 2624 #define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16 2625 #define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF 2626 #define lpfc_reg_fcfi_mrq_type_mask0_WORD word4 2627 #define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8 2628 #define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF 2629 #define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4 2630 #define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0 2631 #define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF 2632 #define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4 2633 uint32_t word5; 2634 #define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24 2635 #define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF 2636 #define lpfc_reg_fcfi_mrq_type_match1_WORD word5 2637 #define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16 2638 #define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF 2639 #define lpfc_reg_fcfi_mrq_type_mask1_WORD word5 2640 #define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8 2641 #define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF 2642 #define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5 2643 #define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0 2644 #define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF 2645 #define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5 2646 uint32_t word6; 2647 #define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24 2648 #define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF 2649 #define lpfc_reg_fcfi_mrq_type_match2_WORD word6 2650 #define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16 2651 #define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF 2652 #define lpfc_reg_fcfi_mrq_type_mask2_WORD word6 2653 #define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8 2654 #define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF 2655 #define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6 2656 #define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0 2657 #define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF 2658 #define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6 2659 uint32_t word7; 2660 #define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24 2661 #define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF 2662 #define lpfc_reg_fcfi_mrq_type_match3_WORD word7 2663 #define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16 2664 #define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF 2665 #define lpfc_reg_fcfi_mrq_type_mask3_WORD word7 2666 #define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8 2667 #define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF 2668 #define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7 2669 #define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0 2670 #define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF 2671 #define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7 2672 uint32_t word8; 2673 #define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31 2674 #define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001 2675 #define lpfc_reg_fcfi_mrq_ptc7_WORD word8 2676 #define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30 2677 #define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001 2678 #define lpfc_reg_fcfi_mrq_ptc6_WORD word8 2679 #define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29 2680 #define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001 2681 #define lpfc_reg_fcfi_mrq_ptc5_WORD word8 2682 #define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28 2683 #define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001 2684 #define lpfc_reg_fcfi_mrq_ptc4_WORD word8 2685 #define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27 2686 #define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001 2687 #define lpfc_reg_fcfi_mrq_ptc3_WORD word8 2688 #define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26 2689 #define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001 2690 #define lpfc_reg_fcfi_mrq_ptc2_WORD word8 2691 #define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25 2692 #define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001 2693 #define lpfc_reg_fcfi_mrq_ptc1_WORD word8 2694 #define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24 2695 #define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001 2696 #define lpfc_reg_fcfi_mrq_ptc0_WORD word8 2697 #define lpfc_reg_fcfi_mrq_pt7_SHIFT 23 2698 #define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001 2699 #define lpfc_reg_fcfi_mrq_pt7_WORD word8 2700 #define lpfc_reg_fcfi_mrq_pt6_SHIFT 22 2701 #define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001 2702 #define lpfc_reg_fcfi_mrq_pt6_WORD word8 2703 #define lpfc_reg_fcfi_mrq_pt5_SHIFT 21 2704 #define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001 2705 #define lpfc_reg_fcfi_mrq_pt5_WORD word8 2706 #define lpfc_reg_fcfi_mrq_pt4_SHIFT 20 2707 #define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001 2708 #define lpfc_reg_fcfi_mrq_pt4_WORD word8 2709 #define lpfc_reg_fcfi_mrq_pt3_SHIFT 19 2710 #define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001 2711 #define lpfc_reg_fcfi_mrq_pt3_WORD word8 2712 #define lpfc_reg_fcfi_mrq_pt2_SHIFT 18 2713 #define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001 2714 #define lpfc_reg_fcfi_mrq_pt2_WORD word8 2715 #define lpfc_reg_fcfi_mrq_pt1_SHIFT 17 2716 #define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001 2717 #define lpfc_reg_fcfi_mrq_pt1_WORD word8 2718 #define lpfc_reg_fcfi_mrq_pt0_SHIFT 16 2719 #define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001 2720 #define lpfc_reg_fcfi_mrq_pt0_WORD word8 2721 #define lpfc_reg_fcfi_mrq_xmv_SHIFT 15 2722 #define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001 2723 #define lpfc_reg_fcfi_mrq_xmv_WORD word8 2724 #define lpfc_reg_fcfi_mrq_mode_SHIFT 13 2725 #define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001 2726 #define lpfc_reg_fcfi_mrq_mode_WORD word8 2727 #define lpfc_reg_fcfi_mrq_vv_SHIFT 12 2728 #define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001 2729 #define lpfc_reg_fcfi_mrq_vv_WORD word8 2730 #define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0 2731 #define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF 2732 #define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8 2733 uint32_t word9; 2734 #define lpfc_reg_fcfi_mrq_policy_SHIFT 12 2735 #define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F 2736 #define lpfc_reg_fcfi_mrq_policy_WORD word9 2737 #define lpfc_reg_fcfi_mrq_filter_SHIFT 8 2738 #define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F 2739 #define lpfc_reg_fcfi_mrq_filter_WORD word9 2740 #define lpfc_reg_fcfi_mrq_npairs_SHIFT 0 2741 #define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF 2742 #define lpfc_reg_fcfi_mrq_npairs_WORD word9 2743 uint32_t word10; 2744 uint32_t word11; 2745 uint32_t word12; 2746 uint32_t word13; 2747 uint32_t word14; 2748 uint32_t word15; 2749 uint32_t word16; 2750 }; 2751 2752 struct lpfc_mbx_unreg_fcfi { 2753 uint32_t word1_rsv; 2754 uint32_t word2; 2755 #define lpfc_unreg_fcfi_SHIFT 0 2756 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2757 #define lpfc_unreg_fcfi_WORD word2 2758 }; 2759 2760 struct lpfc_mbx_read_rev { 2761 uint32_t word1; 2762 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2763 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2764 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2765 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2766 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2767 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2768 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2769 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2770 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2771 #define LPFC_PREDCBX_CEE_MODE 0 2772 #define LPFC_DCBX_CEE_MODE 1 2773 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2774 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2775 #define lpfc_mbx_rd_rev_vpd_WORD word1 2776 uint32_t first_hw_rev; 2777 #define LPFC_G7_ASIC_1 0xd 2778 uint32_t second_hw_rev; 2779 uint32_t word4_rsvd; 2780 uint32_t third_hw_rev; 2781 uint32_t word6; 2782 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2783 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2784 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2785 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2786 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2787 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2788 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2789 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2790 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2791 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2792 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2793 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2794 uint32_t word7_rsvd; 2795 uint32_t fw_id_rev; 2796 uint8_t fw_name[16]; 2797 uint32_t ulp_fw_id_rev; 2798 uint8_t ulp_fw_name[16]; 2799 uint32_t word18_47_rsvd[30]; 2800 uint32_t word48; 2801 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2802 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2803 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2804 uint32_t vpd_paddr_low; 2805 uint32_t vpd_paddr_high; 2806 uint32_t avail_vpd_len; 2807 uint32_t rsvd_52_63[12]; 2808 }; 2809 2810 struct lpfc_mbx_read_config { 2811 uint32_t word1; 2812 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2813 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2814 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2815 uint32_t word2; 2816 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2817 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2818 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2819 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2820 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2821 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2822 #define LPFC_LNK_TYPE_GE 0 2823 #define LPFC_LNK_TYPE_FC 1 2824 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2825 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2826 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2827 #define lpfc_mbx_rd_conf_trunk_SHIFT 12 2828 #define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F 2829 #define lpfc_mbx_rd_conf_trunk_WORD word2 2830 #define lpfc_mbx_rd_conf_pt_SHIFT 20 2831 #define lpfc_mbx_rd_conf_pt_MASK 0x00000003 2832 #define lpfc_mbx_rd_conf_pt_WORD word2 2833 #define lpfc_mbx_rd_conf_tf_SHIFT 22 2834 #define lpfc_mbx_rd_conf_tf_MASK 0x00000001 2835 #define lpfc_mbx_rd_conf_tf_WORD word2 2836 #define lpfc_mbx_rd_conf_ptv_SHIFT 23 2837 #define lpfc_mbx_rd_conf_ptv_MASK 0x00000001 2838 #define lpfc_mbx_rd_conf_ptv_WORD word2 2839 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2840 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2841 #define lpfc_mbx_rd_conf_topology_WORD word2 2842 uint32_t rsvd_3; 2843 uint32_t word4; 2844 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2845 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2846 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2847 uint32_t rsvd_5; 2848 uint32_t word6; 2849 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2850 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2851 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2852 #define lpfc_mbx_rd_conf_link_speed_SHIFT 16 2853 #define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF 2854 #define lpfc_mbx_rd_conf_link_speed_WORD word6 2855 uint32_t rsvd_7; 2856 uint32_t word8; 2857 #define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0 2858 #define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F 2859 #define lpfc_mbx_rd_conf_bbscn_min_WORD word8 2860 #define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4 2861 #define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F 2862 #define lpfc_mbx_rd_conf_bbscn_max_WORD word8 2863 #define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8 2864 #define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F 2865 #define lpfc_mbx_rd_conf_bbscn_def_WORD word8 2866 uint32_t word9; 2867 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2868 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2869 #define lpfc_mbx_rd_conf_lmt_WORD word9 2870 uint32_t rsvd_10; 2871 uint32_t rsvd_11; 2872 uint32_t word12; 2873 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2874 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2875 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2876 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2877 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2878 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2879 uint32_t word13; 2880 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2881 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2882 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2883 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2884 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2885 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2886 uint32_t word14; 2887 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2888 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2889 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2890 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2891 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2892 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2893 uint32_t word15; 2894 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2895 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2896 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2897 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2898 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2899 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2900 uint32_t word16; 2901 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2902 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2903 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2904 uint32_t word17; 2905 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2906 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2907 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2908 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2909 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2910 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2911 uint32_t word18; 2912 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2913 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2914 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2915 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2916 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2917 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2918 }; 2919 2920 struct lpfc_mbx_request_features { 2921 uint32_t word1; 2922 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2923 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2924 #define lpfc_mbx_rq_ftr_qry_WORD word1 2925 uint32_t word2; 2926 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2927 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2928 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2929 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2930 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2931 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2932 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2933 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2934 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2935 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2936 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2937 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2938 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2939 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2940 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2941 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2942 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2943 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2944 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2945 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2946 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2947 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2948 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2949 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2950 #define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9 2951 #define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001 2952 #define lpfc_mbx_rq_ftr_rq_iaar_WORD word2 2953 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2954 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2955 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2956 #define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16 2957 #define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001 2958 #define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2 2959 #define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17 2960 #define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001 2961 #define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2 2962 uint32_t word3; 2963 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2964 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2965 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2966 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2967 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2968 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2969 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2970 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2971 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2972 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2973 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2974 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2975 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2976 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2977 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2978 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2979 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2980 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2981 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2982 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2983 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2984 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2985 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2986 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2987 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2988 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2989 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2990 #define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16 2991 #define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001 2992 #define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3 2993 #define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17 2994 #define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001 2995 #define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3 2996 }; 2997 2998 struct lpfc_mbx_memory_dump_type3 { 2999 uint32_t word1; 3000 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 3001 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 3002 #define lpfc_mbx_memory_dump_type3_type_WORD word1 3003 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 3004 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 3005 #define lpfc_mbx_memory_dump_type3_link_WORD word1 3006 uint32_t word2; 3007 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 3008 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 3009 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 3010 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 3011 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 3012 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 3013 uint32_t word3; 3014 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 3015 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 3016 #define lpfc_mbx_memory_dump_type3_length_WORD word3 3017 uint32_t addr_lo; 3018 uint32_t addr_hi; 3019 uint32_t return_len; 3020 }; 3021 3022 #define DMP_PAGE_A0 0xa0 3023 #define DMP_PAGE_A2 0xa2 3024 #define DMP_SFF_PAGE_A0_SIZE 256 3025 #define DMP_SFF_PAGE_A2_SIZE 256 3026 3027 #define SFP_WAVELENGTH_LC1310 1310 3028 #define SFP_WAVELENGTH_LL1550 1550 3029 3030 3031 /* 3032 * * SFF-8472 TABLE 3.4 3033 * */ 3034 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 3035 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 3036 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 3037 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 3038 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 3039 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 3040 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 3041 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 3042 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 3043 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 3044 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 3045 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 3046 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 3047 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 3048 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 3049 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 3050 3051 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 3052 3053 #define SSF_IDENTIFIER 0 3054 #define SSF_EXT_IDENTIFIER 1 3055 #define SSF_CONNECTOR 2 3056 #define SSF_TRANSCEIVER_CODE_B0 3 3057 #define SSF_TRANSCEIVER_CODE_B1 4 3058 #define SSF_TRANSCEIVER_CODE_B2 5 3059 #define SSF_TRANSCEIVER_CODE_B3 6 3060 #define SSF_TRANSCEIVER_CODE_B4 7 3061 #define SSF_TRANSCEIVER_CODE_B5 8 3062 #define SSF_TRANSCEIVER_CODE_B6 9 3063 #define SSF_TRANSCEIVER_CODE_B7 10 3064 #define SSF_ENCODING 11 3065 #define SSF_BR_NOMINAL 12 3066 #define SSF_RATE_IDENTIFIER 13 3067 #define SSF_LENGTH_9UM_KM 14 3068 #define SSF_LENGTH_9UM 15 3069 #define SSF_LENGTH_50UM_OM2 16 3070 #define SSF_LENGTH_62UM_OM1 17 3071 #define SFF_LENGTH_COPPER 18 3072 #define SSF_LENGTH_50UM_OM3 19 3073 #define SSF_VENDOR_NAME 20 3074 #define SSF_VENDOR_OUI 36 3075 #define SSF_VENDOR_PN 40 3076 #define SSF_VENDOR_REV 56 3077 #define SSF_WAVELENGTH_B1 60 3078 #define SSF_WAVELENGTH_B0 61 3079 #define SSF_CC_BASE 63 3080 #define SSF_OPTIONS_B1 64 3081 #define SSF_OPTIONS_B0 65 3082 #define SSF_BR_MAX 66 3083 #define SSF_BR_MIN 67 3084 #define SSF_VENDOR_SN 68 3085 #define SSF_DATE_CODE 84 3086 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 3087 #define SSF_ENHANCED_OPTIONS 93 3088 #define SFF_8472_COMPLIANCE 94 3089 #define SSF_CC_EXT 95 3090 #define SSF_A0_VENDOR_SPECIFIC 96 3091 3092 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 3093 3094 #define SSF_TEMP_HIGH_ALARM 0 3095 #define SSF_TEMP_LOW_ALARM 2 3096 #define SSF_TEMP_HIGH_WARNING 4 3097 #define SSF_TEMP_LOW_WARNING 6 3098 #define SSF_VOLTAGE_HIGH_ALARM 8 3099 #define SSF_VOLTAGE_LOW_ALARM 10 3100 #define SSF_VOLTAGE_HIGH_WARNING 12 3101 #define SSF_VOLTAGE_LOW_WARNING 14 3102 #define SSF_BIAS_HIGH_ALARM 16 3103 #define SSF_BIAS_LOW_ALARM 18 3104 #define SSF_BIAS_HIGH_WARNING 20 3105 #define SSF_BIAS_LOW_WARNING 22 3106 #define SSF_TXPOWER_HIGH_ALARM 24 3107 #define SSF_TXPOWER_LOW_ALARM 26 3108 #define SSF_TXPOWER_HIGH_WARNING 28 3109 #define SSF_TXPOWER_LOW_WARNING 30 3110 #define SSF_RXPOWER_HIGH_ALARM 32 3111 #define SSF_RXPOWER_LOW_ALARM 34 3112 #define SSF_RXPOWER_HIGH_WARNING 36 3113 #define SSF_RXPOWER_LOW_WARNING 38 3114 #define SSF_EXT_CAL_CONSTANTS 56 3115 #define SSF_CC_DMI 95 3116 #define SFF_TEMPERATURE_B1 96 3117 #define SFF_TEMPERATURE_B0 97 3118 #define SFF_VCC_B1 98 3119 #define SFF_VCC_B0 99 3120 #define SFF_TX_BIAS_CURRENT_B1 100 3121 #define SFF_TX_BIAS_CURRENT_B0 101 3122 #define SFF_TXPOWER_B1 102 3123 #define SFF_TXPOWER_B0 103 3124 #define SFF_RXPOWER_B1 104 3125 #define SFF_RXPOWER_B0 105 3126 #define SSF_STATUS_CONTROL 110 3127 #define SSF_ALARM_FLAGS 112 3128 #define SSF_WARNING_FLAGS 116 3129 #define SSF_EXT_TATUS_CONTROL_B1 118 3130 #define SSF_EXT_TATUS_CONTROL_B0 119 3131 #define SSF_A2_VENDOR_SPECIFIC 120 3132 #define SSF_USER_EEPROM 128 3133 #define SSF_VENDOR_CONTROL 148 3134 3135 3136 /* 3137 * Tranceiver codes Fibre Channel SFF-8472 3138 * Table 3.5. 3139 */ 3140 3141 struct sff_trasnceiver_codes_byte0 { 3142 uint8_t inifiband:4; 3143 uint8_t teng_ethernet:4; 3144 }; 3145 3146 struct sff_trasnceiver_codes_byte1 { 3147 uint8_t sonet:6; 3148 uint8_t escon:2; 3149 }; 3150 3151 struct sff_trasnceiver_codes_byte2 { 3152 uint8_t soNet:8; 3153 }; 3154 3155 struct sff_trasnceiver_codes_byte3 { 3156 uint8_t ethernet:8; 3157 }; 3158 3159 struct sff_trasnceiver_codes_byte4 { 3160 uint8_t fc_el_lo:1; 3161 uint8_t fc_lw_laser:1; 3162 uint8_t fc_sw_laser:1; 3163 uint8_t fc_md_distance:1; 3164 uint8_t fc_lg_distance:1; 3165 uint8_t fc_int_distance:1; 3166 uint8_t fc_short_distance:1; 3167 uint8_t fc_vld_distance:1; 3168 }; 3169 3170 struct sff_trasnceiver_codes_byte5 { 3171 uint8_t reserved1:1; 3172 uint8_t reserved2:1; 3173 uint8_t fc_sfp_active:1; /* Active cable */ 3174 uint8_t fc_sfp_passive:1; /* Passive cable */ 3175 uint8_t fc_lw_laser:1; /* Longwave laser */ 3176 uint8_t fc_sw_laser_sl:1; 3177 uint8_t fc_sw_laser_sn:1; 3178 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 3179 }; 3180 3181 struct sff_trasnceiver_codes_byte6 { 3182 uint8_t fc_tm_sm:1; /* Single Mode */ 3183 uint8_t reserved:1; 3184 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 3185 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 3186 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 3187 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 3188 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 3189 }; 3190 3191 struct sff_trasnceiver_codes_byte7 { 3192 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 3193 uint8_t reserve:1; 3194 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 3195 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 3196 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 3197 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 3198 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 3199 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 3200 }; 3201 3202 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 3203 struct user_eeprom { 3204 uint8_t vendor_name[16]; 3205 uint8_t vendor_oui[3]; 3206 uint8_t vendor_pn[816]; 3207 uint8_t vendor_rev[4]; 3208 uint8_t vendor_sn[16]; 3209 uint8_t datecode[6]; 3210 uint8_t lot_code[2]; 3211 uint8_t reserved191[57]; 3212 }; 3213 3214 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 3215 &(~((SLI4_PAGE_SIZE)-1))) 3216 3217 struct lpfc_sli4_parameters { 3218 uint32_t word0; 3219 #define cfg_prot_type_SHIFT 0 3220 #define cfg_prot_type_MASK 0x000000FF 3221 #define cfg_prot_type_WORD word0 3222 uint32_t word1; 3223 #define cfg_ft_SHIFT 0 3224 #define cfg_ft_MASK 0x00000001 3225 #define cfg_ft_WORD word1 3226 #define cfg_sli_rev_SHIFT 4 3227 #define cfg_sli_rev_MASK 0x0000000f 3228 #define cfg_sli_rev_WORD word1 3229 #define cfg_sli_family_SHIFT 8 3230 #define cfg_sli_family_MASK 0x0000000f 3231 #define cfg_sli_family_WORD word1 3232 #define cfg_if_type_SHIFT 12 3233 #define cfg_if_type_MASK 0x0000000f 3234 #define cfg_if_type_WORD word1 3235 #define cfg_sli_hint_1_SHIFT 16 3236 #define cfg_sli_hint_1_MASK 0x000000ff 3237 #define cfg_sli_hint_1_WORD word1 3238 #define cfg_sli_hint_2_SHIFT 24 3239 #define cfg_sli_hint_2_MASK 0x0000001f 3240 #define cfg_sli_hint_2_WORD word1 3241 uint32_t word2; 3242 #define cfg_eqav_SHIFT 31 3243 #define cfg_eqav_MASK 0x00000001 3244 #define cfg_eqav_WORD word2 3245 uint32_t word3; 3246 uint32_t word4; 3247 #define cfg_cqv_SHIFT 14 3248 #define cfg_cqv_MASK 0x00000003 3249 #define cfg_cqv_WORD word4 3250 #define cfg_cqpsize_SHIFT 16 3251 #define cfg_cqpsize_MASK 0x000000ff 3252 #define cfg_cqpsize_WORD word4 3253 #define cfg_cqav_SHIFT 31 3254 #define cfg_cqav_MASK 0x00000001 3255 #define cfg_cqav_WORD word4 3256 uint32_t word5; 3257 uint32_t word6; 3258 #define cfg_mqv_SHIFT 14 3259 #define cfg_mqv_MASK 0x00000003 3260 #define cfg_mqv_WORD word6 3261 uint32_t word7; 3262 uint32_t word8; 3263 #define cfg_wqpcnt_SHIFT 0 3264 #define cfg_wqpcnt_MASK 0x0000000f 3265 #define cfg_wqpcnt_WORD word8 3266 #define cfg_wqsize_SHIFT 8 3267 #define cfg_wqsize_MASK 0x0000000f 3268 #define cfg_wqsize_WORD word8 3269 #define cfg_wqv_SHIFT 14 3270 #define cfg_wqv_MASK 0x00000003 3271 #define cfg_wqv_WORD word8 3272 #define cfg_wqpsize_SHIFT 16 3273 #define cfg_wqpsize_MASK 0x000000ff 3274 #define cfg_wqpsize_WORD word8 3275 uint32_t word9; 3276 uint32_t word10; 3277 #define cfg_rqv_SHIFT 14 3278 #define cfg_rqv_MASK 0x00000003 3279 #define cfg_rqv_WORD word10 3280 uint32_t word11; 3281 #define cfg_rq_db_window_SHIFT 28 3282 #define cfg_rq_db_window_MASK 0x0000000f 3283 #define cfg_rq_db_window_WORD word11 3284 uint32_t word12; 3285 #define cfg_fcoe_SHIFT 0 3286 #define cfg_fcoe_MASK 0x00000001 3287 #define cfg_fcoe_WORD word12 3288 #define cfg_ext_SHIFT 1 3289 #define cfg_ext_MASK 0x00000001 3290 #define cfg_ext_WORD word12 3291 #define cfg_hdrr_SHIFT 2 3292 #define cfg_hdrr_MASK 0x00000001 3293 #define cfg_hdrr_WORD word12 3294 #define cfg_phwq_SHIFT 15 3295 #define cfg_phwq_MASK 0x00000001 3296 #define cfg_phwq_WORD word12 3297 #define cfg_oas_SHIFT 25 3298 #define cfg_oas_MASK 0x00000001 3299 #define cfg_oas_WORD word12 3300 #define cfg_loopbk_scope_SHIFT 28 3301 #define cfg_loopbk_scope_MASK 0x0000000f 3302 #define cfg_loopbk_scope_WORD word12 3303 uint32_t sge_supp_len; 3304 uint32_t word14; 3305 #define cfg_sgl_page_cnt_SHIFT 0 3306 #define cfg_sgl_page_cnt_MASK 0x0000000f 3307 #define cfg_sgl_page_cnt_WORD word14 3308 #define cfg_sgl_page_size_SHIFT 8 3309 #define cfg_sgl_page_size_MASK 0x000000ff 3310 #define cfg_sgl_page_size_WORD word14 3311 #define cfg_sgl_pp_align_SHIFT 16 3312 #define cfg_sgl_pp_align_MASK 0x000000ff 3313 #define cfg_sgl_pp_align_WORD word14 3314 uint32_t word15; 3315 uint32_t word16; 3316 uint32_t word17; 3317 uint32_t word18; 3318 uint32_t word19; 3319 #define cfg_ext_embed_cb_SHIFT 0 3320 #define cfg_ext_embed_cb_MASK 0x00000001 3321 #define cfg_ext_embed_cb_WORD word19 3322 #define cfg_mds_diags_SHIFT 1 3323 #define cfg_mds_diags_MASK 0x00000001 3324 #define cfg_mds_diags_WORD word19 3325 #define cfg_nvme_SHIFT 3 3326 #define cfg_nvme_MASK 0x00000001 3327 #define cfg_nvme_WORD word19 3328 #define cfg_xib_SHIFT 4 3329 #define cfg_xib_MASK 0x00000001 3330 #define cfg_xib_WORD word19 3331 #define cfg_xpsgl_SHIFT 6 3332 #define cfg_xpsgl_MASK 0x00000001 3333 #define cfg_xpsgl_WORD word19 3334 #define cfg_eqdr_SHIFT 8 3335 #define cfg_eqdr_MASK 0x00000001 3336 #define cfg_eqdr_WORD word19 3337 #define cfg_nosr_SHIFT 9 3338 #define cfg_nosr_MASK 0x00000001 3339 #define cfg_nosr_WORD word19 3340 #define cfg_bv1s_SHIFT 10 3341 #define cfg_bv1s_MASK 0x00000001 3342 #define cfg_bv1s_WORD word19 3343 3344 #define cfg_nsler_SHIFT 12 3345 #define cfg_nsler_MASK 0x00000001 3346 #define cfg_nsler_WORD word19 3347 #define cfg_pvl_SHIFT 13 3348 #define cfg_pvl_MASK 0x00000001 3349 #define cfg_pvl_WORD word19 3350 3351 #define cfg_pbde_SHIFT 20 3352 #define cfg_pbde_MASK 0x00000001 3353 #define cfg_pbde_WORD word19 3354 3355 uint32_t word20; 3356 #define cfg_max_tow_xri_SHIFT 0 3357 #define cfg_max_tow_xri_MASK 0x0000ffff 3358 #define cfg_max_tow_xri_WORD word20 3359 3360 uint32_t word21; 3361 #define cfg_mib_bde_cnt_SHIFT 16 3362 #define cfg_mib_bde_cnt_MASK 0x000000ff 3363 #define cfg_mib_bde_cnt_WORD word21 3364 #define cfg_mi_ver_SHIFT 0 3365 #define cfg_mi_ver_MASK 0x0000ffff 3366 #define cfg_mi_ver_WORD word21 3367 uint32_t mib_size; 3368 uint32_t word23; /* RESERVED */ 3369 3370 uint32_t word24; 3371 #define cfg_frag_field_offset_SHIFT 0 3372 #define cfg_frag_field_offset_MASK 0x0000ffff 3373 #define cfg_frag_field_offset_WORD word24 3374 3375 #define cfg_frag_field_size_SHIFT 16 3376 #define cfg_frag_field_size_MASK 0x0000ffff 3377 #define cfg_frag_field_size_WORD word24 3378 3379 uint32_t word25; 3380 #define cfg_sgl_field_offset_SHIFT 0 3381 #define cfg_sgl_field_offset_MASK 0x0000ffff 3382 #define cfg_sgl_field_offset_WORD word25 3383 3384 #define cfg_sgl_field_size_SHIFT 16 3385 #define cfg_sgl_field_size_MASK 0x0000ffff 3386 #define cfg_sgl_field_size_WORD word25 3387 3388 uint32_t word26; /* Chain SGE initial value LOW */ 3389 uint32_t word27; /* Chain SGE initial value HIGH */ 3390 #define LPFC_NODELAY_MAX_IO 32 3391 }; 3392 3393 #define LPFC_SET_UE_RECOVERY 0x10 3394 #define LPFC_SET_MDS_DIAGS 0x12 3395 #define LPFC_SET_DUAL_DUMP 0x1e 3396 struct lpfc_mbx_set_feature { 3397 struct mbox_header header; 3398 uint32_t feature; 3399 uint32_t param_len; 3400 uint32_t word6; 3401 #define lpfc_mbx_set_feature_UER_SHIFT 0 3402 #define lpfc_mbx_set_feature_UER_MASK 0x00000001 3403 #define lpfc_mbx_set_feature_UER_WORD word6 3404 #define lpfc_mbx_set_feature_mds_SHIFT 2 3405 #define lpfc_mbx_set_feature_mds_MASK 0x00000001 3406 #define lpfc_mbx_set_feature_mds_WORD word6 3407 #define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1 3408 #define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001 3409 #define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6 3410 #define lpfc_mbx_set_feature_dd_SHIFT 0 3411 #define lpfc_mbx_set_feature_dd_MASK 0x00000001 3412 #define lpfc_mbx_set_feature_dd_WORD word6 3413 #define lpfc_mbx_set_feature_ddquery_SHIFT 1 3414 #define lpfc_mbx_set_feature_ddquery_MASK 0x00000001 3415 #define lpfc_mbx_set_feature_ddquery_WORD word6 3416 #define LPFC_DISABLE_DUAL_DUMP 0 3417 #define LPFC_ENABLE_DUAL_DUMP 1 3418 #define LPFC_QUERY_OP_DUAL_DUMP 2 3419 uint32_t word7; 3420 #define lpfc_mbx_set_feature_UERP_SHIFT 0 3421 #define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff 3422 #define lpfc_mbx_set_feature_UERP_WORD word7 3423 #define lpfc_mbx_set_feature_UESR_SHIFT 16 3424 #define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff 3425 #define lpfc_mbx_set_feature_UESR_WORD word7 3426 }; 3427 3428 3429 #define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2 3430 struct lpfc_mbx_set_host_data { 3431 #define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48 3432 struct mbox_header header; 3433 uint32_t param_id; 3434 uint32_t param_len; 3435 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE]; 3436 }; 3437 3438 struct lpfc_mbx_set_trunk_mode { 3439 struct mbox_header header; 3440 uint32_t word0; 3441 #define lpfc_mbx_set_trunk_mode_WORD word0 3442 #define lpfc_mbx_set_trunk_mode_SHIFT 0 3443 #define lpfc_mbx_set_trunk_mode_MASK 0xFF 3444 uint32_t word1; 3445 uint32_t word2; 3446 }; 3447 3448 struct lpfc_mbx_get_sli4_parameters { 3449 struct mbox_header header; 3450 struct lpfc_sli4_parameters sli4_parameters; 3451 }; 3452 3453 struct lpfc_rscr_desc_generic { 3454 #define LPFC_RSRC_DESC_WSIZE 22 3455 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 3456 }; 3457 3458 struct lpfc_rsrc_desc_pcie { 3459 uint32_t word0; 3460 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 3461 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 3462 #define lpfc_rsrc_desc_pcie_type_WORD word0 3463 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 3464 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 3465 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 3466 #define lpfc_rsrc_desc_pcie_length_WORD word0 3467 uint32_t word1; 3468 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 3469 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 3470 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 3471 uint32_t reserved; 3472 uint32_t word3; 3473 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 3474 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 3475 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 3476 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 3477 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 3478 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 3479 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 3480 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 3481 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 3482 uint32_t word4; 3483 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 3484 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 3485 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 3486 }; 3487 3488 struct lpfc_rsrc_desc_fcfcoe { 3489 uint32_t word0; 3490 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 3491 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 3492 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 3493 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 3494 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 3495 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 3496 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 3497 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 3498 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 3499 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 3500 uint32_t word1; 3501 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 3502 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 3503 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 3504 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 3505 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 3506 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 3507 uint32_t word2; 3508 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 3509 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 3510 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 3511 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 3512 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 3513 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 3514 uint32_t word3; 3515 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 3516 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 3517 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 3518 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 3519 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 3520 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 3521 uint32_t word4; 3522 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 3523 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 3524 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 3525 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 3526 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 3527 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 3528 uint32_t word5; 3529 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 3530 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 3531 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 3532 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 3533 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 3534 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 3535 uint32_t word6; 3536 uint32_t word7; 3537 uint32_t word8; 3538 uint32_t word9; 3539 uint32_t word10; 3540 uint32_t word11; 3541 uint32_t word12; 3542 uint32_t word13; 3543 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 3544 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 3545 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 3546 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 3547 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 3548 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 3549 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 3550 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 3551 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 3552 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 3553 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 3554 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 3555 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3556 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3557 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3558 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3559 uint32_t bw_min; 3560 uint32_t bw_max; 3561 uint32_t iops_min; 3562 uint32_t iops_max; 3563 uint32_t reserved[4]; 3564 }; 3565 3566 struct lpfc_func_cfg { 3567 #define LPFC_RSRC_DESC_MAX_NUM 2 3568 uint32_t rsrc_desc_count; 3569 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3570 }; 3571 3572 struct lpfc_mbx_get_func_cfg { 3573 struct mbox_header header; 3574 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3575 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3576 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3577 struct lpfc_func_cfg func_cfg; 3578 }; 3579 3580 struct lpfc_prof_cfg { 3581 #define LPFC_RSRC_DESC_MAX_NUM 2 3582 uint32_t rsrc_desc_count; 3583 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3584 }; 3585 3586 struct lpfc_mbx_get_prof_cfg { 3587 struct mbox_header header; 3588 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3589 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3590 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3591 union { 3592 struct { 3593 uint32_t word10; 3594 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3595 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3596 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3597 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3598 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3599 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3600 } request; 3601 struct { 3602 struct lpfc_prof_cfg prof_cfg; 3603 } response; 3604 } u; 3605 }; 3606 3607 struct lpfc_controller_attribute { 3608 uint32_t version_string[8]; 3609 uint32_t manufacturer_name[8]; 3610 uint32_t supported_modes; 3611 uint32_t word17; 3612 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3613 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3614 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3615 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3616 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3617 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3618 #define lpfc_cntl_attr_flash_id_SHIFT 16 3619 #define lpfc_cntl_attr_flash_id_MASK 0x000000ff 3620 #define lpfc_cntl_attr_flash_id_WORD word17 3621 uint32_t mbx_da_struct_ver; 3622 uint32_t ep_fw_da_struct_ver; 3623 uint32_t ncsi_ver_str[3]; 3624 uint32_t dflt_ext_timeout; 3625 uint32_t model_number[8]; 3626 uint32_t description[16]; 3627 uint32_t serial_number[8]; 3628 uint32_t ip_ver_str[8]; 3629 uint32_t fw_ver_str[8]; 3630 uint32_t bios_ver_str[8]; 3631 uint32_t redboot_ver_str[8]; 3632 uint32_t driver_ver_str[8]; 3633 uint32_t flash_fw_ver_str[8]; 3634 uint32_t functionality; 3635 uint32_t word105; 3636 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3637 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3638 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3639 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3640 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3641 #define lpfc_cntl_attr_asic_rev_WORD word105 3642 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3643 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3644 #define lpfc_cntl_attr_gen_guid0_WORD word105 3645 uint32_t gen_guid1_12[3]; 3646 uint32_t word109; 3647 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3648 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3649 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3650 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3651 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3652 #define lpfc_cntl_attr_gen_guid15_WORD word109 3653 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3654 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3655 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3656 uint32_t word110; 3657 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3658 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3659 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3660 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3661 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3662 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3663 uint32_t word111; 3664 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3665 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3666 #define lpfc_cntl_attr_cache_valid_WORD word111 3667 #define lpfc_cntl_attr_hba_status_SHIFT 8 3668 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3669 #define lpfc_cntl_attr_hba_status_WORD word111 3670 #define lpfc_cntl_attr_max_domain_SHIFT 16 3671 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3672 #define lpfc_cntl_attr_max_domain_WORD word111 3673 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3674 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3675 #define lpfc_cntl_attr_lnk_numb_WORD word111 3676 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3677 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3678 #define lpfc_cntl_attr_lnk_type_WORD word111 3679 uint32_t fw_post_status; 3680 uint32_t hba_mtu[8]; 3681 uint32_t word121; 3682 uint32_t reserved1[3]; 3683 uint32_t word125; 3684 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3685 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3686 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3687 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3688 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3689 #define lpfc_cntl_attr_pci_device_id_WORD word125 3690 uint32_t word126; 3691 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3692 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3693 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3694 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3695 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3696 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3697 uint32_t word127; 3698 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3699 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3700 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3701 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3702 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3703 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3704 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3705 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3706 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3707 #define lpfc_cntl_attr_inf_type_SHIFT 24 3708 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3709 #define lpfc_cntl_attr_inf_type_WORD word127 3710 uint32_t unique_id[2]; 3711 uint32_t word130; 3712 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3713 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3714 #define lpfc_cntl_attr_num_netfil_WORD word130 3715 uint32_t reserved2[4]; 3716 }; 3717 3718 struct lpfc_mbx_get_cntl_attributes { 3719 union lpfc_sli4_cfg_shdr cfg_shdr; 3720 struct lpfc_controller_attribute cntl_attr; 3721 }; 3722 3723 struct lpfc_mbx_get_port_name { 3724 struct mbox_header header; 3725 union { 3726 struct { 3727 uint32_t word4; 3728 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3729 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3730 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3731 } request; 3732 struct { 3733 uint32_t word4; 3734 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3735 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3736 #define lpfc_mbx_get_port_name_name0_WORD word4 3737 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3738 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3739 #define lpfc_mbx_get_port_name_name1_WORD word4 3740 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3741 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3742 #define lpfc_mbx_get_port_name_name2_WORD word4 3743 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3744 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3745 #define lpfc_mbx_get_port_name_name3_WORD word4 3746 #define LPFC_LINK_NUMBER_0 0 3747 #define LPFC_LINK_NUMBER_1 1 3748 #define LPFC_LINK_NUMBER_2 2 3749 #define LPFC_LINK_NUMBER_3 3 3750 } response; 3751 } u; 3752 }; 3753 3754 /* Mailbox Completion Queue Error Messages */ 3755 #define MB_CQE_STATUS_SUCCESS 0x0 3756 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3757 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3758 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3759 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3760 #define MB_CQE_STATUS_DMA_FAILED 0x5 3761 3762 #define LPFC_MBX_WR_CONFIG_MAX_BDE 1 3763 struct lpfc_mbx_wr_object { 3764 struct mbox_header header; 3765 union { 3766 struct { 3767 uint32_t word4; 3768 #define lpfc_wr_object_eof_SHIFT 31 3769 #define lpfc_wr_object_eof_MASK 0x00000001 3770 #define lpfc_wr_object_eof_WORD word4 3771 #define lpfc_wr_object_eas_SHIFT 29 3772 #define lpfc_wr_object_eas_MASK 0x00000001 3773 #define lpfc_wr_object_eas_WORD word4 3774 #define lpfc_wr_object_write_length_SHIFT 0 3775 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3776 #define lpfc_wr_object_write_length_WORD word4 3777 uint32_t write_offset; 3778 uint32_t object_name[26]; 3779 uint32_t bde_count; 3780 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3781 } request; 3782 struct { 3783 uint32_t actual_write_length; 3784 uint32_t word5; 3785 #define lpfc_wr_object_change_status_SHIFT 0 3786 #define lpfc_wr_object_change_status_MASK 0x000000FF 3787 #define lpfc_wr_object_change_status_WORD word5 3788 #define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00 3789 #define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01 3790 #define LPFC_CHANGE_STATUS_FW_RESET 0x02 3791 #define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04 3792 #define LPFC_CHANGE_STATUS_PCI_RESET 0x05 3793 #define lpfc_wr_object_csf_SHIFT 8 3794 #define lpfc_wr_object_csf_MASK 0x00000001 3795 #define lpfc_wr_object_csf_WORD word5 3796 } response; 3797 } u; 3798 }; 3799 3800 /* mailbox queue entry structure */ 3801 struct lpfc_mqe { 3802 uint32_t word0; 3803 #define lpfc_mqe_status_SHIFT 16 3804 #define lpfc_mqe_status_MASK 0x0000FFFF 3805 #define lpfc_mqe_status_WORD word0 3806 #define lpfc_mqe_command_SHIFT 8 3807 #define lpfc_mqe_command_MASK 0x000000FF 3808 #define lpfc_mqe_command_WORD word0 3809 union { 3810 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3811 /* sli4 mailbox commands */ 3812 struct lpfc_mbx_sli4_config sli4_config; 3813 struct lpfc_mbx_init_vfi init_vfi; 3814 struct lpfc_mbx_reg_vfi reg_vfi; 3815 struct lpfc_mbx_reg_vfi unreg_vfi; 3816 struct lpfc_mbx_init_vpi init_vpi; 3817 struct lpfc_mbx_resume_rpi resume_rpi; 3818 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3819 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3820 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3821 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3822 struct lpfc_mbx_reg_fcfi reg_fcfi; 3823 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq; 3824 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3825 struct lpfc_mbx_mq_create mq_create; 3826 struct lpfc_mbx_mq_create_ext mq_create_ext; 3827 struct lpfc_mbx_eq_create eq_create; 3828 struct lpfc_mbx_modify_eq_delay eq_delay; 3829 struct lpfc_mbx_cq_create cq_create; 3830 struct lpfc_mbx_cq_create_set cq_create_set; 3831 struct lpfc_mbx_wq_create wq_create; 3832 struct lpfc_mbx_rq_create rq_create; 3833 struct lpfc_mbx_rq_create_v2 rq_create_v2; 3834 struct lpfc_mbx_mq_destroy mq_destroy; 3835 struct lpfc_mbx_eq_destroy eq_destroy; 3836 struct lpfc_mbx_cq_destroy cq_destroy; 3837 struct lpfc_mbx_wq_destroy wq_destroy; 3838 struct lpfc_mbx_rq_destroy rq_destroy; 3839 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3840 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3841 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3842 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3843 struct lpfc_mbx_nembed_cmd nembed_cmd; 3844 struct lpfc_mbx_read_rev read_rev; 3845 struct lpfc_mbx_read_vpi read_vpi; 3846 struct lpfc_mbx_read_config rd_config; 3847 struct lpfc_mbx_request_features req_ftrs; 3848 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3849 struct lpfc_mbx_query_fw_config query_fw_cfg; 3850 struct lpfc_mbx_set_beacon_config beacon_config; 3851 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3852 struct lpfc_mbx_set_link_diag_state link_diag_state; 3853 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3854 struct lpfc_mbx_run_link_diag_test link_diag_test; 3855 struct lpfc_mbx_get_func_cfg get_func_cfg; 3856 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3857 struct lpfc_mbx_wr_object wr_object; 3858 struct lpfc_mbx_get_port_name get_port_name; 3859 struct lpfc_mbx_set_feature set_feature; 3860 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3861 struct lpfc_mbx_set_host_data set_host_data; 3862 struct lpfc_mbx_set_trunk_mode set_trunk_mode; 3863 struct lpfc_mbx_nop nop; 3864 struct lpfc_mbx_set_ras_fwlog ras_fwlog; 3865 } un; 3866 }; 3867 3868 struct lpfc_mcqe { 3869 uint32_t word0; 3870 #define lpfc_mcqe_status_SHIFT 0 3871 #define lpfc_mcqe_status_MASK 0x0000FFFF 3872 #define lpfc_mcqe_status_WORD word0 3873 #define lpfc_mcqe_ext_status_SHIFT 16 3874 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3875 #define lpfc_mcqe_ext_status_WORD word0 3876 uint32_t mcqe_tag0; 3877 uint32_t mcqe_tag1; 3878 uint32_t trailer; 3879 #define lpfc_trailer_valid_SHIFT 31 3880 #define lpfc_trailer_valid_MASK 0x00000001 3881 #define lpfc_trailer_valid_WORD trailer 3882 #define lpfc_trailer_async_SHIFT 30 3883 #define lpfc_trailer_async_MASK 0x00000001 3884 #define lpfc_trailer_async_WORD trailer 3885 #define lpfc_trailer_hpi_SHIFT 29 3886 #define lpfc_trailer_hpi_MASK 0x00000001 3887 #define lpfc_trailer_hpi_WORD trailer 3888 #define lpfc_trailer_completed_SHIFT 28 3889 #define lpfc_trailer_completed_MASK 0x00000001 3890 #define lpfc_trailer_completed_WORD trailer 3891 #define lpfc_trailer_consumed_SHIFT 27 3892 #define lpfc_trailer_consumed_MASK 0x00000001 3893 #define lpfc_trailer_consumed_WORD trailer 3894 #define lpfc_trailer_type_SHIFT 16 3895 #define lpfc_trailer_type_MASK 0x000000FF 3896 #define lpfc_trailer_type_WORD trailer 3897 #define lpfc_trailer_code_SHIFT 8 3898 #define lpfc_trailer_code_MASK 0x000000FF 3899 #define lpfc_trailer_code_WORD trailer 3900 #define LPFC_TRAILER_CODE_LINK 0x1 3901 #define LPFC_TRAILER_CODE_FCOE 0x2 3902 #define LPFC_TRAILER_CODE_DCBX 0x3 3903 #define LPFC_TRAILER_CODE_GRP5 0x5 3904 #define LPFC_TRAILER_CODE_FC 0x10 3905 #define LPFC_TRAILER_CODE_SLI 0x11 3906 }; 3907 3908 struct lpfc_acqe_link { 3909 uint32_t word0; 3910 #define lpfc_acqe_link_speed_SHIFT 24 3911 #define lpfc_acqe_link_speed_MASK 0x000000FF 3912 #define lpfc_acqe_link_speed_WORD word0 3913 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3914 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3915 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3916 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3917 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3918 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3919 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3920 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3921 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3922 #define lpfc_acqe_link_duplex_SHIFT 16 3923 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3924 #define lpfc_acqe_link_duplex_WORD word0 3925 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3926 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3927 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3928 #define lpfc_acqe_link_status_SHIFT 8 3929 #define lpfc_acqe_link_status_MASK 0x000000FF 3930 #define lpfc_acqe_link_status_WORD word0 3931 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3932 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3933 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3934 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3935 #define lpfc_acqe_link_type_SHIFT 6 3936 #define lpfc_acqe_link_type_MASK 0x00000003 3937 #define lpfc_acqe_link_type_WORD word0 3938 #define lpfc_acqe_link_number_SHIFT 0 3939 #define lpfc_acqe_link_number_MASK 0x0000003F 3940 #define lpfc_acqe_link_number_WORD word0 3941 uint32_t word1; 3942 #define lpfc_acqe_link_fault_SHIFT 0 3943 #define lpfc_acqe_link_fault_MASK 0x000000FF 3944 #define lpfc_acqe_link_fault_WORD word1 3945 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3946 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3947 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3948 #define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3 3949 #define lpfc_acqe_logical_link_speed_SHIFT 16 3950 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3951 #define lpfc_acqe_logical_link_speed_WORD word1 3952 uint32_t event_tag; 3953 uint32_t trailer; 3954 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3955 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3956 }; 3957 3958 struct lpfc_acqe_fip { 3959 uint32_t index; 3960 uint32_t word1; 3961 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3962 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3963 #define lpfc_acqe_fip_fcf_count_WORD word1 3964 #define lpfc_acqe_fip_event_type_SHIFT 16 3965 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3966 #define lpfc_acqe_fip_event_type_WORD word1 3967 uint32_t event_tag; 3968 uint32_t trailer; 3969 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3970 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3971 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3972 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3973 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3974 }; 3975 3976 struct lpfc_acqe_dcbx { 3977 uint32_t tlv_ttl; 3978 uint32_t reserved; 3979 uint32_t event_tag; 3980 uint32_t trailer; 3981 }; 3982 3983 struct lpfc_acqe_grp5 { 3984 uint32_t word0; 3985 #define lpfc_acqe_grp5_type_SHIFT 6 3986 #define lpfc_acqe_grp5_type_MASK 0x00000003 3987 #define lpfc_acqe_grp5_type_WORD word0 3988 #define lpfc_acqe_grp5_number_SHIFT 0 3989 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3990 #define lpfc_acqe_grp5_number_WORD word0 3991 uint32_t word1; 3992 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3993 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3994 #define lpfc_acqe_grp5_llink_spd_WORD word1 3995 uint32_t event_tag; 3996 uint32_t trailer; 3997 }; 3998 3999 extern const char *const trunk_errmsg[]; 4000 4001 struct lpfc_acqe_fc_la { 4002 uint32_t word0; 4003 #define lpfc_acqe_fc_la_speed_SHIFT 24 4004 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 4005 #define lpfc_acqe_fc_la_speed_WORD word0 4006 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 4007 #define LPFC_FC_LA_SPEED_1G 0x1 4008 #define LPFC_FC_LA_SPEED_2G 0x2 4009 #define LPFC_FC_LA_SPEED_4G 0x4 4010 #define LPFC_FC_LA_SPEED_8G 0x8 4011 #define LPFC_FC_LA_SPEED_10G 0xA 4012 #define LPFC_FC_LA_SPEED_16G 0x10 4013 #define LPFC_FC_LA_SPEED_32G 0x20 4014 #define LPFC_FC_LA_SPEED_64G 0x21 4015 #define LPFC_FC_LA_SPEED_128G 0x22 4016 #define LPFC_FC_LA_SPEED_256G 0x23 4017 #define lpfc_acqe_fc_la_topology_SHIFT 16 4018 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 4019 #define lpfc_acqe_fc_la_topology_WORD word0 4020 #define LPFC_FC_LA_TOP_UNKOWN 0x0 4021 #define LPFC_FC_LA_TOP_P2P 0x1 4022 #define LPFC_FC_LA_TOP_FCAL 0x2 4023 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 4024 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 4025 #define lpfc_acqe_fc_la_att_type_SHIFT 8 4026 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 4027 #define lpfc_acqe_fc_la_att_type_WORD word0 4028 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 4029 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 4030 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 4031 #define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4 4032 #define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5 4033 #define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6 4034 #define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7 4035 #define lpfc_acqe_fc_la_port_type_SHIFT 6 4036 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 4037 #define lpfc_acqe_fc_la_port_type_WORD word0 4038 #define LPFC_LINK_TYPE_ETHERNET 0x0 4039 #define LPFC_LINK_TYPE_FC 0x1 4040 #define lpfc_acqe_fc_la_port_number_SHIFT 0 4041 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 4042 #define lpfc_acqe_fc_la_port_number_WORD word0 4043 4044 /* Attention Type is 0x07 (Trunking Event) word0 */ 4045 #define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16 4046 #define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001 4047 #define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0 4048 #define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17 4049 #define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001 4050 #define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0 4051 #define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18 4052 #define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001 4053 #define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0 4054 #define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19 4055 #define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001 4056 #define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0 4057 #define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20 4058 #define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001 4059 #define lpfc_acqe_fc_la_trunk_config_port0_WORD word0 4060 #define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21 4061 #define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001 4062 #define lpfc_acqe_fc_la_trunk_config_port1_WORD word0 4063 #define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22 4064 #define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001 4065 #define lpfc_acqe_fc_la_trunk_config_port2_WORD word0 4066 #define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23 4067 #define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001 4068 #define lpfc_acqe_fc_la_trunk_config_port3_WORD word0 4069 uint32_t word1; 4070 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 4071 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 4072 #define lpfc_acqe_fc_la_llink_spd_WORD word1 4073 #define lpfc_acqe_fc_la_fault_SHIFT 0 4074 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 4075 #define lpfc_acqe_fc_la_fault_WORD word1 4076 #define lpfc_acqe_fc_la_trunk_fault_SHIFT 0 4077 #define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F 4078 #define lpfc_acqe_fc_la_trunk_fault_WORD word1 4079 #define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4 4080 #define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F 4081 #define lpfc_acqe_fc_la_trunk_linkmask_WORD word1 4082 #define LPFC_FC_LA_FAULT_NONE 0x0 4083 #define LPFC_FC_LA_FAULT_LOCAL 0x1 4084 #define LPFC_FC_LA_FAULT_REMOTE 0x2 4085 uint32_t event_tag; 4086 uint32_t trailer; 4087 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 4088 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 4089 }; 4090 4091 struct lpfc_acqe_misconfigured_event { 4092 struct { 4093 uint32_t word0; 4094 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 4095 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 4096 #define lpfc_sli_misconfigured_port0_state_WORD word0 4097 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 4098 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 4099 #define lpfc_sli_misconfigured_port1_state_WORD word0 4100 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 4101 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 4102 #define lpfc_sli_misconfigured_port2_state_WORD word0 4103 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 4104 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 4105 #define lpfc_sli_misconfigured_port3_state_WORD word0 4106 uint32_t word1; 4107 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 4108 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 4109 #define lpfc_sli_misconfigured_port0_op_WORD word1 4110 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 4111 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 4112 #define lpfc_sli_misconfigured_port0_severity_WORD word1 4113 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 4114 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 4115 #define lpfc_sli_misconfigured_port1_op_WORD word1 4116 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 4117 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 4118 #define lpfc_sli_misconfigured_port1_severity_WORD word1 4119 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 4120 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 4121 #define lpfc_sli_misconfigured_port2_op_WORD word1 4122 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 4123 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 4124 #define lpfc_sli_misconfigured_port2_severity_WORD word1 4125 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 4126 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 4127 #define lpfc_sli_misconfigured_port3_op_WORD word1 4128 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 4129 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 4130 #define lpfc_sli_misconfigured_port3_severity_WORD word1 4131 } theEvent; 4132 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 4133 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 4134 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 4135 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 4136 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 4137 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 4138 }; 4139 4140 struct lpfc_acqe_sli { 4141 uint32_t event_data1; 4142 uint32_t event_data2; 4143 uint32_t reserved; 4144 uint32_t trailer; 4145 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 4146 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 4147 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 4148 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 4149 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 4150 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 4151 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 4152 #define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF 4153 #define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10 4154 }; 4155 4156 /* 4157 * Define the bootstrap mailbox (bmbx) region used to communicate 4158 * mailbox command between the host and port. The mailbox consists 4159 * of a payload area of 256 bytes and a completion queue of length 4160 * 16 bytes. 4161 */ 4162 struct lpfc_bmbx_create { 4163 struct lpfc_mqe mqe; 4164 struct lpfc_mcqe mcqe; 4165 }; 4166 4167 #define SGL_ALIGN_SZ 64 4168 #define SGL_PAGE_SIZE 4096 4169 /* align SGL addr on a size boundary - adjust address up */ 4170 #define NO_XRI 0xffff 4171 4172 struct wqe_common { 4173 uint32_t word6; 4174 #define wqe_xri_tag_SHIFT 0 4175 #define wqe_xri_tag_MASK 0x0000FFFF 4176 #define wqe_xri_tag_WORD word6 4177 #define wqe_ctxt_tag_SHIFT 16 4178 #define wqe_ctxt_tag_MASK 0x0000FFFF 4179 #define wqe_ctxt_tag_WORD word6 4180 uint32_t word7; 4181 #define wqe_dif_SHIFT 0 4182 #define wqe_dif_MASK 0x00000003 4183 #define wqe_dif_WORD word7 4184 #define LPFC_WQE_DIF_PASSTHRU 1 4185 #define LPFC_WQE_DIF_STRIP 2 4186 #define LPFC_WQE_DIF_INSERT 3 4187 #define wqe_ct_SHIFT 2 4188 #define wqe_ct_MASK 0x00000003 4189 #define wqe_ct_WORD word7 4190 #define wqe_status_SHIFT 4 4191 #define wqe_status_MASK 0x0000000f 4192 #define wqe_status_WORD word7 4193 #define wqe_cmnd_SHIFT 8 4194 #define wqe_cmnd_MASK 0x000000ff 4195 #define wqe_cmnd_WORD word7 4196 #define wqe_class_SHIFT 16 4197 #define wqe_class_MASK 0x00000007 4198 #define wqe_class_WORD word7 4199 #define wqe_ar_SHIFT 19 4200 #define wqe_ar_MASK 0x00000001 4201 #define wqe_ar_WORD word7 4202 #define wqe_ag_SHIFT wqe_ar_SHIFT 4203 #define wqe_ag_MASK wqe_ar_MASK 4204 #define wqe_ag_WORD wqe_ar_WORD 4205 #define wqe_pu_SHIFT 20 4206 #define wqe_pu_MASK 0x00000003 4207 #define wqe_pu_WORD word7 4208 #define wqe_erp_SHIFT 22 4209 #define wqe_erp_MASK 0x00000001 4210 #define wqe_erp_WORD word7 4211 #define wqe_conf_SHIFT wqe_erp_SHIFT 4212 #define wqe_conf_MASK wqe_erp_MASK 4213 #define wqe_conf_WORD wqe_erp_WORD 4214 #define wqe_lnk_SHIFT 23 4215 #define wqe_lnk_MASK 0x00000001 4216 #define wqe_lnk_WORD word7 4217 #define wqe_tmo_SHIFT 24 4218 #define wqe_tmo_MASK 0x000000ff 4219 #define wqe_tmo_WORD word7 4220 uint32_t abort_tag; /* word 8 in WQE */ 4221 uint32_t word9; 4222 #define wqe_reqtag_SHIFT 0 4223 #define wqe_reqtag_MASK 0x0000FFFF 4224 #define wqe_reqtag_WORD word9 4225 #define wqe_temp_rpi_SHIFT 16 4226 #define wqe_temp_rpi_MASK 0x0000FFFF 4227 #define wqe_temp_rpi_WORD word9 4228 #define wqe_rcvoxid_SHIFT 16 4229 #define wqe_rcvoxid_MASK 0x0000FFFF 4230 #define wqe_rcvoxid_WORD word9 4231 #define wqe_sof_SHIFT 24 4232 #define wqe_sof_MASK 0x000000FF 4233 #define wqe_sof_WORD word9 4234 #define wqe_eof_SHIFT 16 4235 #define wqe_eof_MASK 0x000000FF 4236 #define wqe_eof_WORD word9 4237 uint32_t word10; 4238 #define wqe_ebde_cnt_SHIFT 0 4239 #define wqe_ebde_cnt_MASK 0x0000000f 4240 #define wqe_ebde_cnt_WORD word10 4241 #define wqe_xchg_SHIFT 4 4242 #define wqe_xchg_MASK 0x00000001 4243 #define wqe_xchg_WORD word10 4244 #define LPFC_SCSI_XCHG 0x0 4245 #define LPFC_NVME_XCHG 0x1 4246 #define wqe_appid_SHIFT 5 4247 #define wqe_appid_MASK 0x00000001 4248 #define wqe_appid_WORD word10 4249 #define wqe_oas_SHIFT 6 4250 #define wqe_oas_MASK 0x00000001 4251 #define wqe_oas_WORD word10 4252 #define wqe_lenloc_SHIFT 7 4253 #define wqe_lenloc_MASK 0x00000003 4254 #define wqe_lenloc_WORD word10 4255 #define LPFC_WQE_LENLOC_NONE 0 4256 #define LPFC_WQE_LENLOC_WORD3 1 4257 #define LPFC_WQE_LENLOC_WORD12 2 4258 #define LPFC_WQE_LENLOC_WORD4 3 4259 #define wqe_qosd_SHIFT 9 4260 #define wqe_qosd_MASK 0x00000001 4261 #define wqe_qosd_WORD word10 4262 #define wqe_xbl_SHIFT 11 4263 #define wqe_xbl_MASK 0x00000001 4264 #define wqe_xbl_WORD word10 4265 #define wqe_iod_SHIFT 13 4266 #define wqe_iod_MASK 0x00000001 4267 #define wqe_iod_WORD word10 4268 #define LPFC_WQE_IOD_NONE 0 4269 #define LPFC_WQE_IOD_WRITE 0 4270 #define LPFC_WQE_IOD_READ 1 4271 #define wqe_dbde_SHIFT 14 4272 #define wqe_dbde_MASK 0x00000001 4273 #define wqe_dbde_WORD word10 4274 #define wqe_wqes_SHIFT 15 4275 #define wqe_wqes_MASK 0x00000001 4276 #define wqe_wqes_WORD word10 4277 /* Note that this field overlaps above fields */ 4278 #define wqe_wqid_SHIFT 1 4279 #define wqe_wqid_MASK 0x00007fff 4280 #define wqe_wqid_WORD word10 4281 #define wqe_pri_SHIFT 16 4282 #define wqe_pri_MASK 0x00000007 4283 #define wqe_pri_WORD word10 4284 #define wqe_pv_SHIFT 19 4285 #define wqe_pv_MASK 0x00000001 4286 #define wqe_pv_WORD word10 4287 #define wqe_xc_SHIFT 21 4288 #define wqe_xc_MASK 0x00000001 4289 #define wqe_xc_WORD word10 4290 #define wqe_sr_SHIFT 22 4291 #define wqe_sr_MASK 0x00000001 4292 #define wqe_sr_WORD word10 4293 #define wqe_ccpe_SHIFT 23 4294 #define wqe_ccpe_MASK 0x00000001 4295 #define wqe_ccpe_WORD word10 4296 #define wqe_ccp_SHIFT 24 4297 #define wqe_ccp_MASK 0x000000ff 4298 #define wqe_ccp_WORD word10 4299 uint32_t word11; 4300 #define wqe_cmd_type_SHIFT 0 4301 #define wqe_cmd_type_MASK 0x0000000f 4302 #define wqe_cmd_type_WORD word11 4303 #define wqe_els_id_SHIFT 4 4304 #define wqe_els_id_MASK 0x00000003 4305 #define wqe_els_id_WORD word11 4306 #define LPFC_ELS_ID_FLOGI 3 4307 #define LPFC_ELS_ID_FDISC 2 4308 #define LPFC_ELS_ID_LOGO 1 4309 #define LPFC_ELS_ID_DEFAULT 0 4310 #define wqe_irsp_SHIFT 4 4311 #define wqe_irsp_MASK 0x00000001 4312 #define wqe_irsp_WORD word11 4313 #define wqe_pbde_SHIFT 5 4314 #define wqe_pbde_MASK 0x00000001 4315 #define wqe_pbde_WORD word11 4316 #define wqe_sup_SHIFT 6 4317 #define wqe_sup_MASK 0x00000001 4318 #define wqe_sup_WORD word11 4319 #define wqe_wqec_SHIFT 7 4320 #define wqe_wqec_MASK 0x00000001 4321 #define wqe_wqec_WORD word11 4322 #define wqe_irsplen_SHIFT 8 4323 #define wqe_irsplen_MASK 0x0000000f 4324 #define wqe_irsplen_WORD word11 4325 #define wqe_cqid_SHIFT 16 4326 #define wqe_cqid_MASK 0x0000ffff 4327 #define wqe_cqid_WORD word11 4328 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 4329 }; 4330 4331 struct wqe_did { 4332 uint32_t word5; 4333 #define wqe_els_did_SHIFT 0 4334 #define wqe_els_did_MASK 0x00FFFFFF 4335 #define wqe_els_did_WORD word5 4336 #define wqe_xmit_bls_pt_SHIFT 28 4337 #define wqe_xmit_bls_pt_MASK 0x00000003 4338 #define wqe_xmit_bls_pt_WORD word5 4339 #define wqe_xmit_bls_ar_SHIFT 30 4340 #define wqe_xmit_bls_ar_MASK 0x00000001 4341 #define wqe_xmit_bls_ar_WORD word5 4342 #define wqe_xmit_bls_xo_SHIFT 31 4343 #define wqe_xmit_bls_xo_MASK 0x00000001 4344 #define wqe_xmit_bls_xo_WORD word5 4345 }; 4346 4347 struct lpfc_wqe_generic{ 4348 struct ulp_bde64 bde; 4349 uint32_t word3; 4350 uint32_t word4; 4351 uint32_t word5; 4352 struct wqe_common wqe_com; 4353 uint32_t payload[4]; 4354 }; 4355 4356 struct els_request64_wqe { 4357 struct ulp_bde64 bde; 4358 uint32_t payload_len; 4359 uint32_t word4; 4360 #define els_req64_sid_SHIFT 0 4361 #define els_req64_sid_MASK 0x00FFFFFF 4362 #define els_req64_sid_WORD word4 4363 #define els_req64_sp_SHIFT 24 4364 #define els_req64_sp_MASK 0x00000001 4365 #define els_req64_sp_WORD word4 4366 #define els_req64_vf_SHIFT 25 4367 #define els_req64_vf_MASK 0x00000001 4368 #define els_req64_vf_WORD word4 4369 struct wqe_did wqe_dest; 4370 struct wqe_common wqe_com; /* words 6-11 */ 4371 uint32_t word12; 4372 #define els_req64_vfid_SHIFT 1 4373 #define els_req64_vfid_MASK 0x00000FFF 4374 #define els_req64_vfid_WORD word12 4375 #define els_req64_pri_SHIFT 13 4376 #define els_req64_pri_MASK 0x00000007 4377 #define els_req64_pri_WORD word12 4378 uint32_t word13; 4379 #define els_req64_hopcnt_SHIFT 24 4380 #define els_req64_hopcnt_MASK 0x000000ff 4381 #define els_req64_hopcnt_WORD word13 4382 uint32_t word14; 4383 uint32_t max_response_payload_len; 4384 }; 4385 4386 struct xmit_els_rsp64_wqe { 4387 struct ulp_bde64 bde; 4388 uint32_t response_payload_len; 4389 uint32_t word4; 4390 #define els_rsp64_sid_SHIFT 0 4391 #define els_rsp64_sid_MASK 0x00FFFFFF 4392 #define els_rsp64_sid_WORD word4 4393 #define els_rsp64_sp_SHIFT 24 4394 #define els_rsp64_sp_MASK 0x00000001 4395 #define els_rsp64_sp_WORD word4 4396 struct wqe_did wqe_dest; 4397 struct wqe_common wqe_com; /* words 6-11 */ 4398 uint32_t word12; 4399 #define wqe_rsp_temp_rpi_SHIFT 0 4400 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 4401 #define wqe_rsp_temp_rpi_WORD word12 4402 uint32_t rsvd_13_15[3]; 4403 }; 4404 4405 struct xmit_bls_rsp64_wqe { 4406 uint32_t payload0; 4407 /* Payload0 for BA_ACC */ 4408 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 4409 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 4410 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 4411 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 4412 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 4413 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 4414 /* Payload0 for BA_RJT */ 4415 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 4416 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 4417 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 4418 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 4419 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 4420 #define xmit_bls_rsp64_rjt_expc_WORD payload0 4421 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 4422 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 4423 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 4424 uint32_t word1; 4425 #define xmit_bls_rsp64_rxid_SHIFT 0 4426 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 4427 #define xmit_bls_rsp64_rxid_WORD word1 4428 #define xmit_bls_rsp64_oxid_SHIFT 16 4429 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 4430 #define xmit_bls_rsp64_oxid_WORD word1 4431 uint32_t word2; 4432 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 4433 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 4434 #define xmit_bls_rsp64_seqcnthi_WORD word2 4435 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 4436 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 4437 #define xmit_bls_rsp64_seqcntlo_WORD word2 4438 uint32_t rsrvd3; 4439 uint32_t rsrvd4; 4440 struct wqe_did wqe_dest; 4441 struct wqe_common wqe_com; /* words 6-11 */ 4442 uint32_t word12; 4443 #define xmit_bls_rsp64_temprpi_SHIFT 0 4444 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 4445 #define xmit_bls_rsp64_temprpi_WORD word12 4446 uint32_t rsvd_13_15[3]; 4447 }; 4448 4449 struct wqe_rctl_dfctl { 4450 uint32_t word5; 4451 #define wqe_si_SHIFT 2 4452 #define wqe_si_MASK 0x000000001 4453 #define wqe_si_WORD word5 4454 #define wqe_la_SHIFT 3 4455 #define wqe_la_MASK 0x000000001 4456 #define wqe_la_WORD word5 4457 #define wqe_xo_SHIFT 6 4458 #define wqe_xo_MASK 0x000000001 4459 #define wqe_xo_WORD word5 4460 #define wqe_ls_SHIFT 7 4461 #define wqe_ls_MASK 0x000000001 4462 #define wqe_ls_WORD word5 4463 #define wqe_dfctl_SHIFT 8 4464 #define wqe_dfctl_MASK 0x0000000ff 4465 #define wqe_dfctl_WORD word5 4466 #define wqe_type_SHIFT 16 4467 #define wqe_type_MASK 0x0000000ff 4468 #define wqe_type_WORD word5 4469 #define wqe_rctl_SHIFT 24 4470 #define wqe_rctl_MASK 0x0000000ff 4471 #define wqe_rctl_WORD word5 4472 }; 4473 4474 struct xmit_seq64_wqe { 4475 struct ulp_bde64 bde; 4476 uint32_t rsvd3; 4477 uint32_t relative_offset; 4478 struct wqe_rctl_dfctl wge_ctl; 4479 struct wqe_common wqe_com; /* words 6-11 */ 4480 uint32_t xmit_len; 4481 uint32_t rsvd_12_15[3]; 4482 }; 4483 struct xmit_bcast64_wqe { 4484 struct ulp_bde64 bde; 4485 uint32_t seq_payload_len; 4486 uint32_t rsvd4; 4487 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4488 struct wqe_common wqe_com; /* words 6-11 */ 4489 uint32_t rsvd_12_15[4]; 4490 }; 4491 4492 struct gen_req64_wqe { 4493 struct ulp_bde64 bde; 4494 uint32_t request_payload_len; 4495 uint32_t relative_offset; 4496 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 4497 struct wqe_common wqe_com; /* words 6-11 */ 4498 uint32_t rsvd_12_14[3]; 4499 uint32_t max_response_payload_len; 4500 }; 4501 4502 /* Define NVME PRLI request to fabric. NVME is a 4503 * fabric-only protocol. 4504 * Updated to red-lined v1.08 on Sept 16, 2016 4505 */ 4506 struct lpfc_nvme_prli { 4507 uint32_t word1; 4508 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */ 4509 #define prli_acc_rsp_code_SHIFT 8 4510 #define prli_acc_rsp_code_MASK 0x0000000f 4511 #define prli_acc_rsp_code_WORD word1 4512 #define prli_estabImagePair_SHIFT 13 4513 #define prli_estabImagePair_MASK 0x00000001 4514 #define prli_estabImagePair_WORD word1 4515 #define prli_type_code_ext_SHIFT 16 4516 #define prli_type_code_ext_MASK 0x000000ff 4517 #define prli_type_code_ext_WORD word1 4518 #define prli_type_code_SHIFT 24 4519 #define prli_type_code_MASK 0x000000ff 4520 #define prli_type_code_WORD word1 4521 uint32_t word_rsvd2; 4522 uint32_t word_rsvd3; 4523 4524 uint32_t word4; 4525 #define prli_fba_SHIFT 0 4526 #define prli_fba_MASK 0x00000001 4527 #define prli_fba_WORD word4 4528 #define prli_disc_SHIFT 3 4529 #define prli_disc_MASK 0x00000001 4530 #define prli_disc_WORD word4 4531 #define prli_tgt_SHIFT 4 4532 #define prli_tgt_MASK 0x00000001 4533 #define prli_tgt_WORD word4 4534 #define prli_init_SHIFT 5 4535 #define prli_init_MASK 0x00000001 4536 #define prli_init_WORD word4 4537 #define prli_conf_SHIFT 7 4538 #define prli_conf_MASK 0x00000001 4539 #define prli_conf_WORD word4 4540 #define prli_nsler_SHIFT 8 4541 #define prli_nsler_MASK 0x00000001 4542 #define prli_nsler_WORD word4 4543 uint32_t word5; 4544 #define prli_fb_sz_SHIFT 0 4545 #define prli_fb_sz_MASK 0x0000ffff 4546 #define prli_fb_sz_WORD word5 4547 #define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */ 4548 }; 4549 4550 struct create_xri_wqe { 4551 uint32_t rsrvd[5]; /* words 0-4 */ 4552 struct wqe_did wqe_dest; /* word 5 */ 4553 struct wqe_common wqe_com; /* words 6-11 */ 4554 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4555 }; 4556 4557 #define INHIBIT_ABORT 1 4558 #define T_REQUEST_TAG 3 4559 #define T_XRI_TAG 1 4560 4561 struct abort_cmd_wqe { 4562 uint32_t rsrvd[3]; 4563 uint32_t word3; 4564 #define abort_cmd_ia_SHIFT 0 4565 #define abort_cmd_ia_MASK 0x000000001 4566 #define abort_cmd_ia_WORD word3 4567 #define abort_cmd_criteria_SHIFT 8 4568 #define abort_cmd_criteria_MASK 0x0000000ff 4569 #define abort_cmd_criteria_WORD word3 4570 uint32_t rsrvd4; 4571 uint32_t rsrvd5; 4572 struct wqe_common wqe_com; /* words 6-11 */ 4573 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4574 }; 4575 4576 struct fcp_iwrite64_wqe { 4577 struct ulp_bde64 bde; 4578 uint32_t word3; 4579 #define cmd_buff_len_SHIFT 16 4580 #define cmd_buff_len_MASK 0x00000ffff 4581 #define cmd_buff_len_WORD word3 4582 #define payload_offset_len_SHIFT 0 4583 #define payload_offset_len_MASK 0x0000ffff 4584 #define payload_offset_len_WORD word3 4585 uint32_t total_xfer_len; 4586 uint32_t initial_xfer_len; 4587 struct wqe_common wqe_com; /* words 6-11 */ 4588 uint32_t rsrvd12; 4589 struct ulp_bde64 ph_bde; /* words 13-15 */ 4590 }; 4591 4592 struct fcp_iread64_wqe { 4593 struct ulp_bde64 bde; 4594 uint32_t word3; 4595 #define cmd_buff_len_SHIFT 16 4596 #define cmd_buff_len_MASK 0x00000ffff 4597 #define cmd_buff_len_WORD word3 4598 #define payload_offset_len_SHIFT 0 4599 #define payload_offset_len_MASK 0x0000ffff 4600 #define payload_offset_len_WORD word3 4601 uint32_t total_xfer_len; /* word 4 */ 4602 uint32_t rsrvd5; /* word 5 */ 4603 struct wqe_common wqe_com; /* words 6-11 */ 4604 uint32_t rsrvd12; 4605 struct ulp_bde64 ph_bde; /* words 13-15 */ 4606 }; 4607 4608 struct fcp_icmnd64_wqe { 4609 struct ulp_bde64 bde; /* words 0-2 */ 4610 uint32_t word3; 4611 #define cmd_buff_len_SHIFT 16 4612 #define cmd_buff_len_MASK 0x00000ffff 4613 #define cmd_buff_len_WORD word3 4614 #define payload_offset_len_SHIFT 0 4615 #define payload_offset_len_MASK 0x0000ffff 4616 #define payload_offset_len_WORD word3 4617 uint32_t rsrvd4; /* word 4 */ 4618 uint32_t rsrvd5; /* word 5 */ 4619 struct wqe_common wqe_com; /* words 6-11 */ 4620 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4621 }; 4622 4623 struct fcp_trsp64_wqe { 4624 struct ulp_bde64 bde; 4625 uint32_t response_len; 4626 uint32_t rsvd_4_5[2]; 4627 struct wqe_common wqe_com; /* words 6-11 */ 4628 uint32_t rsvd_12_15[4]; /* word 12-15 */ 4629 }; 4630 4631 struct fcp_tsend64_wqe { 4632 struct ulp_bde64 bde; 4633 uint32_t payload_offset_len; 4634 uint32_t relative_offset; 4635 uint32_t reserved; 4636 struct wqe_common wqe_com; /* words 6-11 */ 4637 uint32_t fcp_data_len; /* word 12 */ 4638 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4639 }; 4640 4641 struct fcp_treceive64_wqe { 4642 struct ulp_bde64 bde; 4643 uint32_t payload_offset_len; 4644 uint32_t relative_offset; 4645 uint32_t reserved; 4646 struct wqe_common wqe_com; /* words 6-11 */ 4647 uint32_t fcp_data_len; /* word 12 */ 4648 uint32_t rsvd_13_15[3]; /* word 13-15 */ 4649 }; 4650 #define TXRDY_PAYLOAD_LEN 12 4651 4652 #define CMD_SEND_FRAME 0xE1 4653 4654 struct send_frame_wqe { 4655 struct ulp_bde64 bde; /* words 0-2 */ 4656 uint32_t frame_len; /* word 3 */ 4657 uint32_t fc_hdr_wd0; /* word 4 */ 4658 uint32_t fc_hdr_wd1; /* word 5 */ 4659 struct wqe_common wqe_com; /* words 6-11 */ 4660 uint32_t fc_hdr_wd2; /* word 12 */ 4661 uint32_t fc_hdr_wd3; /* word 13 */ 4662 uint32_t fc_hdr_wd4; /* word 14 */ 4663 uint32_t fc_hdr_wd5; /* word 15 */ 4664 }; 4665 4666 #define ELS_RDF_REG_TAG_CNT 4 4667 struct lpfc_els_rdf_reg_desc { 4668 struct fc_df_desc_fpin_reg reg_desc; /* descriptor header */ 4669 __be32 desc_tags[ELS_RDF_REG_TAG_CNT]; 4670 /* tags in reg_desc */ 4671 }; 4672 4673 struct lpfc_els_rdf_req { 4674 struct fc_els_rdf rdf; /* hdr up to descriptors */ 4675 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4676 }; 4677 4678 struct lpfc_els_rdf_rsp { 4679 struct fc_els_rdf_resp rdf_resp; /* hdr up to descriptors */ 4680 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */ 4681 }; 4682 4683 union lpfc_wqe { 4684 uint32_t words[16]; 4685 struct lpfc_wqe_generic generic; 4686 struct fcp_icmnd64_wqe fcp_icmd; 4687 struct fcp_iread64_wqe fcp_iread; 4688 struct fcp_iwrite64_wqe fcp_iwrite; 4689 struct abort_cmd_wqe abort_cmd; 4690 struct create_xri_wqe create_xri; 4691 struct xmit_bcast64_wqe xmit_bcast64; 4692 struct xmit_seq64_wqe xmit_sequence; 4693 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4694 struct xmit_els_rsp64_wqe xmit_els_rsp; 4695 struct els_request64_wqe els_req; 4696 struct gen_req64_wqe gen_req; 4697 struct fcp_trsp64_wqe fcp_trsp; 4698 struct fcp_tsend64_wqe fcp_tsend; 4699 struct fcp_treceive64_wqe fcp_treceive; 4700 struct send_frame_wqe send_frame; 4701 }; 4702 4703 union lpfc_wqe128 { 4704 uint32_t words[32]; 4705 struct lpfc_wqe_generic generic; 4706 struct fcp_icmnd64_wqe fcp_icmd; 4707 struct fcp_iread64_wqe fcp_iread; 4708 struct fcp_iwrite64_wqe fcp_iwrite; 4709 struct abort_cmd_wqe abort_cmd; 4710 struct create_xri_wqe create_xri; 4711 struct xmit_bcast64_wqe xmit_bcast64; 4712 struct xmit_seq64_wqe xmit_sequence; 4713 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 4714 struct xmit_els_rsp64_wqe xmit_els_rsp; 4715 struct els_request64_wqe els_req; 4716 struct gen_req64_wqe gen_req; 4717 struct fcp_trsp64_wqe fcp_trsp; 4718 struct fcp_tsend64_wqe fcp_tsend; 4719 struct fcp_treceive64_wqe fcp_treceive; 4720 struct send_frame_wqe send_frame; 4721 }; 4722 4723 #define MAGIC_NUMBER_G6 0xFEAA0003 4724 #define MAGIC_NUMBER_G7 0xFEAA0005 4725 #define MAGIC_NUMBER_G7P 0xFEAA0020 4726 4727 struct lpfc_grp_hdr { 4728 uint32_t size; 4729 uint32_t magic_number; 4730 uint32_t word2; 4731 #define lpfc_grp_hdr_file_type_SHIFT 24 4732 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 4733 #define lpfc_grp_hdr_file_type_WORD word2 4734 #define lpfc_grp_hdr_id_SHIFT 16 4735 #define lpfc_grp_hdr_id_MASK 0x000000FF 4736 #define lpfc_grp_hdr_id_WORD word2 4737 uint8_t rev_name[128]; 4738 uint8_t date[12]; 4739 uint8_t revision[32]; 4740 }; 4741 4742 /* Defines for WQE command type */ 4743 #define FCP_COMMAND 0x0 4744 #define NVME_READ_CMD 0x0 4745 #define FCP_COMMAND_DATA_OUT 0x1 4746 #define NVME_WRITE_CMD 0x1 4747 #define COMMAND_DATA_IN 0x0 4748 #define COMMAND_DATA_OUT 0x1 4749 #define FCP_COMMAND_TRECEIVE 0x2 4750 #define FCP_COMMAND_TRSP 0x3 4751 #define FCP_COMMAND_TSEND 0x7 4752 #define OTHER_COMMAND 0x8 4753 #define ELS_COMMAND_NON_FIP 0xC 4754 #define ELS_COMMAND_FIP 0xD 4755 4756 #define LPFC_NVME_EMBED_CMD 0x0 4757 #define LPFC_NVME_EMBED_WRITE 0x1 4758 #define LPFC_NVME_EMBED_READ 0x2 4759 4760 /* WQE Commands */ 4761 #define CMD_ABORT_XRI_WQE 0x0F 4762 #define CMD_XMIT_SEQUENCE64_WQE 0x82 4763 #define CMD_XMIT_BCAST64_WQE 0x84 4764 #define CMD_ELS_REQUEST64_WQE 0x8A 4765 #define CMD_XMIT_ELS_RSP64_WQE 0x95 4766 #define CMD_XMIT_BLS_RSP64_WQE 0x97 4767 #define CMD_FCP_IWRITE64_WQE 0x98 4768 #define CMD_FCP_IREAD64_WQE 0x9A 4769 #define CMD_FCP_ICMND64_WQE 0x9C 4770 #define CMD_FCP_TSEND64_WQE 0x9F 4771 #define CMD_FCP_TRECEIVE64_WQE 0xA1 4772 #define CMD_FCP_TRSP64_WQE 0xA3 4773 #define CMD_GEN_REQUEST64_WQE 0xC2 4774 4775 #define CMD_WQE_MASK 0xff 4776 4777 4778 #define LPFC_FW_DUMP 1 4779 #define LPFC_FW_RESET 2 4780 #define LPFC_DV_RESET 3 4781