1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2009-2016 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 /* Macros to deal with bit fields. Each bit field must have 3 #defines 22 * associated with it (_SHIFT, _MASK, and _WORD). 23 * EG. For a bit field that is in the 7th bit of the "field4" field of a 24 * structure and is 2 bits in size the following #defines must exist: 25 * struct temp { 26 * uint32_t field1; 27 * uint32_t field2; 28 * uint32_t field3; 29 * uint32_t field4; 30 * #define example_bit_field_SHIFT 7 31 * #define example_bit_field_MASK 0x03 32 * #define example_bit_field_WORD field4 33 * uint32_t field5; 34 * }; 35 * Then the macros below may be used to get or set the value of that field. 36 * EG. To get the value of the bit field from the above example: 37 * struct temp t1; 38 * value = bf_get(example_bit_field, &t1); 39 * And then to set that bit field: 40 * bf_set(example_bit_field, &t1, 2); 41 * Or clear that bit field: 42 * bf_set(example_bit_field, &t1, 0); 43 */ 44 #define bf_get_be32(name, ptr) \ 45 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 46 #define bf_get_le32(name, ptr) \ 47 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) 48 #define bf_get(name, ptr) \ 49 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) 50 #define bf_set_le32(name, ptr, value) \ 51 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \ 52 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ 53 ~(name##_MASK << name##_SHIFT))))) 54 #define bf_set(name, ptr, value) \ 55 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ 56 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) 57 58 struct dma_address { 59 uint32_t addr_lo; 60 uint32_t addr_hi; 61 }; 62 63 struct lpfc_sli_intf { 64 uint32_t word0; 65 #define lpfc_sli_intf_valid_SHIFT 29 66 #define lpfc_sli_intf_valid_MASK 0x00000007 67 #define lpfc_sli_intf_valid_WORD word0 68 #define LPFC_SLI_INTF_VALID 6 69 #define lpfc_sli_intf_sli_hint2_SHIFT 24 70 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F 71 #define lpfc_sli_intf_sli_hint2_WORD word0 72 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0 73 #define lpfc_sli_intf_sli_hint1_SHIFT 16 74 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF 75 #define lpfc_sli_intf_sli_hint1_WORD word0 76 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0 77 #define LPFC_SLI_INTF_SLI_HINT1_1 1 78 #define LPFC_SLI_INTF_SLI_HINT1_2 2 79 #define lpfc_sli_intf_if_type_SHIFT 12 80 #define lpfc_sli_intf_if_type_MASK 0x0000000F 81 #define lpfc_sli_intf_if_type_WORD word0 82 #define LPFC_SLI_INTF_IF_TYPE_0 0 83 #define LPFC_SLI_INTF_IF_TYPE_1 1 84 #define LPFC_SLI_INTF_IF_TYPE_2 2 85 #define lpfc_sli_intf_sli_family_SHIFT 8 86 #define lpfc_sli_intf_sli_family_MASK 0x0000000F 87 #define lpfc_sli_intf_sli_family_WORD word0 88 #define LPFC_SLI_INTF_FAMILY_BE2 0x0 89 #define LPFC_SLI_INTF_FAMILY_BE3 0x1 90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa 91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb 92 #define lpfc_sli_intf_slirev_SHIFT 4 93 #define lpfc_sli_intf_slirev_MASK 0x0000000F 94 #define lpfc_sli_intf_slirev_WORD word0 95 #define LPFC_SLI_INTF_REV_SLI3 3 96 #define LPFC_SLI_INTF_REV_SLI4 4 97 #define lpfc_sli_intf_func_type_SHIFT 0 98 #define lpfc_sli_intf_func_type_MASK 0x00000001 99 #define lpfc_sli_intf_func_type_WORD word0 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS 0 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT 1 102 }; 103 104 #define LPFC_SLI4_MBX_EMBED true 105 #define LPFC_SLI4_MBX_NEMBED false 106 107 #define LPFC_SLI4_MB_WORD_COUNT 64 108 #define LPFC_MAX_MQ_PAGE 8 109 #define LPFC_MAX_WQ_PAGE_V0 4 110 #define LPFC_MAX_WQ_PAGE 8 111 #define LPFC_MAX_CQ_PAGE 4 112 #define LPFC_MAX_EQ_PAGE 8 113 114 #define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */ 115 #define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */ 116 #define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */ 117 118 /* Define SLI4 Alignment requirements. */ 119 #define LPFC_ALIGN_16_BYTE 16 120 #define LPFC_ALIGN_64_BYTE 64 121 122 /* Define SLI4 specific definitions. */ 123 #define LPFC_MQ_CQE_BYTE_OFFSET 256 124 #define LPFC_MBX_CMD_HDR_LENGTH 16 125 #define LPFC_MBX_ERROR_RANGE 0x4000 126 #define LPFC_BMBX_BIT1_ADDR_HI 0x2 127 #define LPFC_BMBX_BIT1_ADDR_LO 0 128 #define LPFC_RPI_HDR_COUNT 64 129 #define LPFC_HDR_TEMPLATE_SIZE 4096 130 #define LPFC_RPI_ALLOC_ERROR 0xFFFF 131 #define LPFC_FCF_RECORD_WD_CNT 132 132 #define LPFC_ENTIRE_FCF_DATABASE 0 133 #define LPFC_DFLT_FCF_INDEX 0 134 135 /* Virtual function numbers */ 136 #define LPFC_VF0 0 137 #define LPFC_VF1 1 138 #define LPFC_VF2 2 139 #define LPFC_VF3 3 140 #define LPFC_VF4 4 141 #define LPFC_VF5 5 142 #define LPFC_VF6 6 143 #define LPFC_VF7 7 144 #define LPFC_VF8 8 145 #define LPFC_VF9 9 146 #define LPFC_VF10 10 147 #define LPFC_VF11 11 148 #define LPFC_VF12 12 149 #define LPFC_VF13 13 150 #define LPFC_VF14 14 151 #define LPFC_VF15 15 152 #define LPFC_VF16 16 153 #define LPFC_VF17 17 154 #define LPFC_VF18 18 155 #define LPFC_VF19 19 156 #define LPFC_VF20 20 157 #define LPFC_VF21 21 158 #define LPFC_VF22 22 159 #define LPFC_VF23 23 160 #define LPFC_VF24 24 161 #define LPFC_VF25 25 162 #define LPFC_VF26 26 163 #define LPFC_VF27 27 164 #define LPFC_VF28 28 165 #define LPFC_VF29 29 166 #define LPFC_VF30 30 167 #define LPFC_VF31 31 168 169 /* PCI function numbers */ 170 #define LPFC_PCI_FUNC0 0 171 #define LPFC_PCI_FUNC1 1 172 #define LPFC_PCI_FUNC2 2 173 #define LPFC_PCI_FUNC3 3 174 #define LPFC_PCI_FUNC4 4 175 176 /* SLI4 interface type-2 PDEV_CTL register */ 177 #define LPFC_CTL_PDEV_CTL_OFFSET 0x414 178 #define LPFC_CTL_PDEV_CTL_DRST 0x00000001 179 #define LPFC_CTL_PDEV_CTL_FRST 0x00000002 180 #define LPFC_CTL_PDEV_CTL_DD 0x00000004 181 #define LPFC_CTL_PDEV_CTL_LC 0x00000008 182 #define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00 183 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10 184 #define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20 185 186 #define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST) 187 188 /* Active interrupt test count */ 189 #define LPFC_ACT_INTR_CNT 4 190 191 /* Algrithmns for scheduling FCP commands to WQs */ 192 #define LPFC_FCP_SCHED_ROUND_ROBIN 0 193 #define LPFC_FCP_SCHED_BY_CPU 1 194 195 /* Delay Multiplier constant */ 196 #define LPFC_DMULT_CONST 651042 197 198 /* Configuration of Interrupts / sec for entire HBA port */ 199 #define LPFC_MIN_IMAX 5000 200 #define LPFC_MAX_IMAX 5000000 201 #define LPFC_DEF_IMAX 50000 202 203 #define LPFC_MIN_CPU_MAP 0 204 #define LPFC_MAX_CPU_MAP 2 205 #define LPFC_HBA_CPU_MAP 1 206 #define LPFC_DRIVER_CPU_MAP 2 /* Default */ 207 208 /* PORT_CAPABILITIES constants. */ 209 #define LPFC_MAX_SUPPORTED_PAGES 8 210 211 struct ulp_bde64 { 212 union ULP_BDE_TUS { 213 uint32_t w; 214 struct { 215 #ifdef __BIG_ENDIAN_BITFIELD 216 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 217 VALUE !! */ 218 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 219 #else /* __LITTLE_ENDIAN_BITFIELD */ 220 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 221 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 222 VALUE !! */ 223 #endif 224 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 225 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 226 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 227 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 228 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 229 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 230 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 231 } f; 232 } tus; 233 uint32_t addrLow; 234 uint32_t addrHigh; 235 }; 236 237 /* Maximun size of immediate data that can fit into a 128 byte WQE */ 238 #define LPFC_MAX_BDE_IMM_SIZE 64 239 240 struct lpfc_sli4_flags { 241 uint32_t word0; 242 #define lpfc_idx_rsrc_rdy_SHIFT 0 243 #define lpfc_idx_rsrc_rdy_MASK 0x00000001 244 #define lpfc_idx_rsrc_rdy_WORD word0 245 #define LPFC_IDX_RSRC_RDY 1 246 #define lpfc_rpi_rsrc_rdy_SHIFT 1 247 #define lpfc_rpi_rsrc_rdy_MASK 0x00000001 248 #define lpfc_rpi_rsrc_rdy_WORD word0 249 #define LPFC_RPI_RSRC_RDY 1 250 #define lpfc_vpi_rsrc_rdy_SHIFT 2 251 #define lpfc_vpi_rsrc_rdy_MASK 0x00000001 252 #define lpfc_vpi_rsrc_rdy_WORD word0 253 #define LPFC_VPI_RSRC_RDY 1 254 #define lpfc_vfi_rsrc_rdy_SHIFT 3 255 #define lpfc_vfi_rsrc_rdy_MASK 0x00000001 256 #define lpfc_vfi_rsrc_rdy_WORD word0 257 #define LPFC_VFI_RSRC_RDY 1 258 }; 259 260 struct sli4_bls_rsp { 261 uint32_t word0_rsvd; /* Word0 must be reserved */ 262 uint32_t word1; 263 #define lpfc_abts_orig_SHIFT 0 264 #define lpfc_abts_orig_MASK 0x00000001 265 #define lpfc_abts_orig_WORD word1 266 #define LPFC_ABTS_UNSOL_RSP 1 267 #define LPFC_ABTS_UNSOL_INT 0 268 uint32_t word2; 269 #define lpfc_abts_rxid_SHIFT 0 270 #define lpfc_abts_rxid_MASK 0x0000FFFF 271 #define lpfc_abts_rxid_WORD word2 272 #define lpfc_abts_oxid_SHIFT 16 273 #define lpfc_abts_oxid_MASK 0x0000FFFF 274 #define lpfc_abts_oxid_WORD word2 275 uint32_t word3; 276 #define lpfc_vndr_code_SHIFT 0 277 #define lpfc_vndr_code_MASK 0x000000FF 278 #define lpfc_vndr_code_WORD word3 279 #define lpfc_rsn_expln_SHIFT 8 280 #define lpfc_rsn_expln_MASK 0x000000FF 281 #define lpfc_rsn_expln_WORD word3 282 #define lpfc_rsn_code_SHIFT 16 283 #define lpfc_rsn_code_MASK 0x000000FF 284 #define lpfc_rsn_code_WORD word3 285 286 uint32_t word4; 287 uint32_t word5_rsvd; /* Word5 must be reserved */ 288 }; 289 290 /* event queue entry structure */ 291 struct lpfc_eqe { 292 uint32_t word0; 293 #define lpfc_eqe_resource_id_SHIFT 16 294 #define lpfc_eqe_resource_id_MASK 0x0000FFFF 295 #define lpfc_eqe_resource_id_WORD word0 296 #define lpfc_eqe_minor_code_SHIFT 4 297 #define lpfc_eqe_minor_code_MASK 0x00000FFF 298 #define lpfc_eqe_minor_code_WORD word0 299 #define lpfc_eqe_major_code_SHIFT 1 300 #define lpfc_eqe_major_code_MASK 0x00000007 301 #define lpfc_eqe_major_code_WORD word0 302 #define lpfc_eqe_valid_SHIFT 0 303 #define lpfc_eqe_valid_MASK 0x00000001 304 #define lpfc_eqe_valid_WORD word0 305 }; 306 307 /* completion queue entry structure (common fields for all cqe types) */ 308 struct lpfc_cqe { 309 uint32_t reserved0; 310 uint32_t reserved1; 311 uint32_t reserved2; 312 uint32_t word3; 313 #define lpfc_cqe_valid_SHIFT 31 314 #define lpfc_cqe_valid_MASK 0x00000001 315 #define lpfc_cqe_valid_WORD word3 316 #define lpfc_cqe_code_SHIFT 16 317 #define lpfc_cqe_code_MASK 0x000000FF 318 #define lpfc_cqe_code_WORD word3 319 }; 320 321 /* Completion Queue Entry Status Codes */ 322 #define CQE_STATUS_SUCCESS 0x0 323 #define CQE_STATUS_FCP_RSP_FAILURE 0x1 324 #define CQE_STATUS_REMOTE_STOP 0x2 325 #define CQE_STATUS_LOCAL_REJECT 0x3 326 #define CQE_STATUS_NPORT_RJT 0x4 327 #define CQE_STATUS_FABRIC_RJT 0x5 328 #define CQE_STATUS_NPORT_BSY 0x6 329 #define CQE_STATUS_FABRIC_BSY 0x7 330 #define CQE_STATUS_INTERMED_RSP 0x8 331 #define CQE_STATUS_LS_RJT 0x9 332 #define CQE_STATUS_CMD_REJECT 0xb 333 #define CQE_STATUS_FCP_TGT_LENCHECK 0xc 334 #define CQE_STATUS_NEED_BUFF_ENTRY 0xf 335 #define CQE_STATUS_DI_ERROR 0x16 336 337 /* Used when mapping CQE status to IOCB */ 338 #define LPFC_IOCB_STATUS_MASK 0xf 339 340 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */ 341 #define CQE_HW_STATUS_NO_ERR 0x0 342 #define CQE_HW_STATUS_UNDERRUN 0x1 343 #define CQE_HW_STATUS_OVERRUN 0x2 344 345 /* Completion Queue Entry Codes */ 346 #define CQE_CODE_COMPL_WQE 0x1 347 #define CQE_CODE_RELEASE_WQE 0x2 348 #define CQE_CODE_RECEIVE 0x4 349 #define CQE_CODE_XRI_ABORTED 0x5 350 #define CQE_CODE_RECEIVE_V1 0x9 351 352 /* 353 * Define mask value for xri_aborted and wcqe completed CQE extended status. 354 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) . 355 */ 356 #define WCQE_PARAM_MASK 0x1FF 357 358 /* completion queue entry for wqe completions */ 359 struct lpfc_wcqe_complete { 360 uint32_t word0; 361 #define lpfc_wcqe_c_request_tag_SHIFT 16 362 #define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF 363 #define lpfc_wcqe_c_request_tag_WORD word0 364 #define lpfc_wcqe_c_status_SHIFT 8 365 #define lpfc_wcqe_c_status_MASK 0x000000FF 366 #define lpfc_wcqe_c_status_WORD word0 367 #define lpfc_wcqe_c_hw_status_SHIFT 0 368 #define lpfc_wcqe_c_hw_status_MASK 0x000000FF 369 #define lpfc_wcqe_c_hw_status_WORD word0 370 uint32_t total_data_placed; 371 uint32_t parameter; 372 #define lpfc_wcqe_c_bg_edir_SHIFT 5 373 #define lpfc_wcqe_c_bg_edir_MASK 0x00000001 374 #define lpfc_wcqe_c_bg_edir_WORD parameter 375 #define lpfc_wcqe_c_bg_tdpv_SHIFT 3 376 #define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001 377 #define lpfc_wcqe_c_bg_tdpv_WORD parameter 378 #define lpfc_wcqe_c_bg_re_SHIFT 2 379 #define lpfc_wcqe_c_bg_re_MASK 0x00000001 380 #define lpfc_wcqe_c_bg_re_WORD parameter 381 #define lpfc_wcqe_c_bg_ae_SHIFT 1 382 #define lpfc_wcqe_c_bg_ae_MASK 0x00000001 383 #define lpfc_wcqe_c_bg_ae_WORD parameter 384 #define lpfc_wcqe_c_bg_ge_SHIFT 0 385 #define lpfc_wcqe_c_bg_ge_MASK 0x00000001 386 #define lpfc_wcqe_c_bg_ge_WORD parameter 387 uint32_t word3; 388 #define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT 389 #define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK 390 #define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD 391 #define lpfc_wcqe_c_xb_SHIFT 28 392 #define lpfc_wcqe_c_xb_MASK 0x00000001 393 #define lpfc_wcqe_c_xb_WORD word3 394 #define lpfc_wcqe_c_pv_SHIFT 27 395 #define lpfc_wcqe_c_pv_MASK 0x00000001 396 #define lpfc_wcqe_c_pv_WORD word3 397 #define lpfc_wcqe_c_priority_SHIFT 24 398 #define lpfc_wcqe_c_priority_MASK 0x00000007 399 #define lpfc_wcqe_c_priority_WORD word3 400 #define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT 401 #define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK 402 #define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD 403 }; 404 405 /* completion queue entry for wqe release */ 406 struct lpfc_wcqe_release { 407 uint32_t reserved0; 408 uint32_t reserved1; 409 uint32_t word2; 410 #define lpfc_wcqe_r_wq_id_SHIFT 16 411 #define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF 412 #define lpfc_wcqe_r_wq_id_WORD word2 413 #define lpfc_wcqe_r_wqe_index_SHIFT 0 414 #define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF 415 #define lpfc_wcqe_r_wqe_index_WORD word2 416 uint32_t word3; 417 #define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT 418 #define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK 419 #define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD 420 #define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT 421 #define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK 422 #define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD 423 }; 424 425 struct sli4_wcqe_xri_aborted { 426 uint32_t word0; 427 #define lpfc_wcqe_xa_status_SHIFT 8 428 #define lpfc_wcqe_xa_status_MASK 0x000000FF 429 #define lpfc_wcqe_xa_status_WORD word0 430 uint32_t parameter; 431 uint32_t word2; 432 #define lpfc_wcqe_xa_remote_xid_SHIFT 16 433 #define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF 434 #define lpfc_wcqe_xa_remote_xid_WORD word2 435 #define lpfc_wcqe_xa_xri_SHIFT 0 436 #define lpfc_wcqe_xa_xri_MASK 0x0000FFFF 437 #define lpfc_wcqe_xa_xri_WORD word2 438 uint32_t word3; 439 #define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT 440 #define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK 441 #define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD 442 #define lpfc_wcqe_xa_ia_SHIFT 30 443 #define lpfc_wcqe_xa_ia_MASK 0x00000001 444 #define lpfc_wcqe_xa_ia_WORD word3 445 #define CQE_XRI_ABORTED_IA_REMOTE 0 446 #define CQE_XRI_ABORTED_IA_LOCAL 1 447 #define lpfc_wcqe_xa_br_SHIFT 29 448 #define lpfc_wcqe_xa_br_MASK 0x00000001 449 #define lpfc_wcqe_xa_br_WORD word3 450 #define CQE_XRI_ABORTED_BR_BA_ACC 0 451 #define CQE_XRI_ABORTED_BR_BA_RJT 1 452 #define lpfc_wcqe_xa_eo_SHIFT 28 453 #define lpfc_wcqe_xa_eo_MASK 0x00000001 454 #define lpfc_wcqe_xa_eo_WORD word3 455 #define CQE_XRI_ABORTED_EO_REMOTE 0 456 #define CQE_XRI_ABORTED_EO_LOCAL 1 457 #define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT 458 #define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK 459 #define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD 460 }; 461 462 /* completion queue entry structure for rqe completion */ 463 struct lpfc_rcqe { 464 uint32_t word0; 465 #define lpfc_rcqe_bindex_SHIFT 16 466 #define lpfc_rcqe_bindex_MASK 0x0000FFF 467 #define lpfc_rcqe_bindex_WORD word0 468 #define lpfc_rcqe_status_SHIFT 8 469 #define lpfc_rcqe_status_MASK 0x000000FF 470 #define lpfc_rcqe_status_WORD word0 471 #define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */ 472 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */ 473 #define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */ 474 #define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */ 475 uint32_t word1; 476 #define lpfc_rcqe_fcf_id_v1_SHIFT 0 477 #define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F 478 #define lpfc_rcqe_fcf_id_v1_WORD word1 479 uint32_t word2; 480 #define lpfc_rcqe_length_SHIFT 16 481 #define lpfc_rcqe_length_MASK 0x0000FFFF 482 #define lpfc_rcqe_length_WORD word2 483 #define lpfc_rcqe_rq_id_SHIFT 6 484 #define lpfc_rcqe_rq_id_MASK 0x000003FF 485 #define lpfc_rcqe_rq_id_WORD word2 486 #define lpfc_rcqe_fcf_id_SHIFT 0 487 #define lpfc_rcqe_fcf_id_MASK 0x0000003F 488 #define lpfc_rcqe_fcf_id_WORD word2 489 #define lpfc_rcqe_rq_id_v1_SHIFT 0 490 #define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF 491 #define lpfc_rcqe_rq_id_v1_WORD word2 492 uint32_t word3; 493 #define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT 494 #define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK 495 #define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD 496 #define lpfc_rcqe_port_SHIFT 30 497 #define lpfc_rcqe_port_MASK 0x00000001 498 #define lpfc_rcqe_port_WORD word3 499 #define lpfc_rcqe_hdr_length_SHIFT 24 500 #define lpfc_rcqe_hdr_length_MASK 0x0000001F 501 #define lpfc_rcqe_hdr_length_WORD word3 502 #define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT 503 #define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK 504 #define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD 505 #define lpfc_rcqe_eof_SHIFT 8 506 #define lpfc_rcqe_eof_MASK 0x000000FF 507 #define lpfc_rcqe_eof_WORD word3 508 #define FCOE_EOFn 0x41 509 #define FCOE_EOFt 0x42 510 #define FCOE_EOFni 0x49 511 #define FCOE_EOFa 0x50 512 #define lpfc_rcqe_sof_SHIFT 0 513 #define lpfc_rcqe_sof_MASK 0x000000FF 514 #define lpfc_rcqe_sof_WORD word3 515 #define FCOE_SOFi2 0x2d 516 #define FCOE_SOFi3 0x2e 517 #define FCOE_SOFn2 0x35 518 #define FCOE_SOFn3 0x36 519 }; 520 521 struct lpfc_rqe { 522 uint32_t address_hi; 523 uint32_t address_lo; 524 }; 525 526 /* buffer descriptors */ 527 struct lpfc_bde4 { 528 uint32_t addr_hi; 529 uint32_t addr_lo; 530 uint32_t word2; 531 #define lpfc_bde4_last_SHIFT 31 532 #define lpfc_bde4_last_MASK 0x00000001 533 #define lpfc_bde4_last_WORD word2 534 #define lpfc_bde4_sge_offset_SHIFT 0 535 #define lpfc_bde4_sge_offset_MASK 0x000003FF 536 #define lpfc_bde4_sge_offset_WORD word2 537 uint32_t word3; 538 #define lpfc_bde4_length_SHIFT 0 539 #define lpfc_bde4_length_MASK 0x000000FF 540 #define lpfc_bde4_length_WORD word3 541 }; 542 543 struct lpfc_register { 544 uint32_t word0; 545 }; 546 547 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */ 548 #define LPFC_UERR_STATUS_HI 0x00A4 549 #define LPFC_UERR_STATUS_LO 0x00A0 550 #define LPFC_UE_MASK_HI 0x00AC 551 #define LPFC_UE_MASK_LO 0x00A8 552 553 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */ 554 #define LPFC_SLI_INTF 0x0058 555 556 #define LPFC_CTL_PORT_SEM_OFFSET 0x400 557 #define lpfc_port_smphr_perr_SHIFT 31 558 #define lpfc_port_smphr_perr_MASK 0x1 559 #define lpfc_port_smphr_perr_WORD word0 560 #define lpfc_port_smphr_sfi_SHIFT 30 561 #define lpfc_port_smphr_sfi_MASK 0x1 562 #define lpfc_port_smphr_sfi_WORD word0 563 #define lpfc_port_smphr_nip_SHIFT 29 564 #define lpfc_port_smphr_nip_MASK 0x1 565 #define lpfc_port_smphr_nip_WORD word0 566 #define lpfc_port_smphr_ipc_SHIFT 28 567 #define lpfc_port_smphr_ipc_MASK 0x1 568 #define lpfc_port_smphr_ipc_WORD word0 569 #define lpfc_port_smphr_scr1_SHIFT 27 570 #define lpfc_port_smphr_scr1_MASK 0x1 571 #define lpfc_port_smphr_scr1_WORD word0 572 #define lpfc_port_smphr_scr2_SHIFT 26 573 #define lpfc_port_smphr_scr2_MASK 0x1 574 #define lpfc_port_smphr_scr2_WORD word0 575 #define lpfc_port_smphr_host_scratch_SHIFT 16 576 #define lpfc_port_smphr_host_scratch_MASK 0xFF 577 #define lpfc_port_smphr_host_scratch_WORD word0 578 #define lpfc_port_smphr_port_status_SHIFT 0 579 #define lpfc_port_smphr_port_status_MASK 0xFFFF 580 #define lpfc_port_smphr_port_status_WORD word0 581 582 #define LPFC_POST_STAGE_POWER_ON_RESET 0x0000 583 #define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001 584 #define LPFC_POST_STAGE_HOST_RDY 0x0002 585 #define LPFC_POST_STAGE_BE_RESET 0x0003 586 #define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100 587 #define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101 588 #define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200 589 #define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201 590 #define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300 591 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301 592 #define LPFC_POST_STAGE_DDR_TEST_START 0x0400 593 #define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401 594 #define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600 595 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601 596 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700 597 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701 598 #define LPFC_POST_STAGE_ARMFW_START 0x0800 599 #define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900 600 #define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901 601 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00 602 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01 603 #define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00 604 #define LPFC_POST_STAGE_SWITCH_LINK 0x0B01 605 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02 606 #define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03 607 #define LPFC_POST_STAGE_PARSE_XML 0x0B04 608 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05 609 #define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06 610 #define LPFC_POST_STAGE_RC_DONE 0x0B07 611 #define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08 612 #define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00 613 #define LPFC_POST_STAGE_PORT_READY 0xC000 614 #define LPFC_POST_STAGE_PORT_UE 0xF000 615 616 #define LPFC_CTL_PORT_STA_OFFSET 0x404 617 #define lpfc_sliport_status_err_SHIFT 31 618 #define lpfc_sliport_status_err_MASK 0x1 619 #define lpfc_sliport_status_err_WORD word0 620 #define lpfc_sliport_status_end_SHIFT 30 621 #define lpfc_sliport_status_end_MASK 0x1 622 #define lpfc_sliport_status_end_WORD word0 623 #define lpfc_sliport_status_oti_SHIFT 29 624 #define lpfc_sliport_status_oti_MASK 0x1 625 #define lpfc_sliport_status_oti_WORD word0 626 #define lpfc_sliport_status_rn_SHIFT 24 627 #define lpfc_sliport_status_rn_MASK 0x1 628 #define lpfc_sliport_status_rn_WORD word0 629 #define lpfc_sliport_status_rdy_SHIFT 23 630 #define lpfc_sliport_status_rdy_MASK 0x1 631 #define lpfc_sliport_status_rdy_WORD word0 632 #define MAX_IF_TYPE_2_RESETS 6 633 634 #define LPFC_CTL_PORT_CTL_OFFSET 0x408 635 #define lpfc_sliport_ctrl_end_SHIFT 30 636 #define lpfc_sliport_ctrl_end_MASK 0x1 637 #define lpfc_sliport_ctrl_end_WORD word0 638 #define LPFC_SLIPORT_LITTLE_ENDIAN 0 639 #define LPFC_SLIPORT_BIG_ENDIAN 1 640 #define lpfc_sliport_ctrl_ip_SHIFT 27 641 #define lpfc_sliport_ctrl_ip_MASK 0x1 642 #define lpfc_sliport_ctrl_ip_WORD word0 643 #define LPFC_SLIPORT_INIT_PORT 1 644 645 #define LPFC_CTL_PORT_ER1_OFFSET 0x40C 646 #define LPFC_CTL_PORT_ER2_OFFSET 0x410 647 648 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically 649 * reside in BAR 2. 650 */ 651 #define LPFC_SLIPORT_IF0_SMPHR 0x00AC 652 653 #define LPFC_IMR_MASK_ALL 0xFFFFFFFF 654 #define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF 655 656 #define LPFC_HST_ISR0 0x0C18 657 #define LPFC_HST_ISR1 0x0C1C 658 #define LPFC_HST_ISR2 0x0C20 659 #define LPFC_HST_ISR3 0x0C24 660 #define LPFC_HST_ISR4 0x0C28 661 662 #define LPFC_HST_IMR0 0x0C48 663 #define LPFC_HST_IMR1 0x0C4C 664 #define LPFC_HST_IMR2 0x0C50 665 #define LPFC_HST_IMR3 0x0C54 666 #define LPFC_HST_IMR4 0x0C58 667 668 #define LPFC_HST_ISCR0 0x0C78 669 #define LPFC_HST_ISCR1 0x0C7C 670 #define LPFC_HST_ISCR2 0x0C80 671 #define LPFC_HST_ISCR3 0x0C84 672 #define LPFC_HST_ISCR4 0x0C88 673 674 #define LPFC_SLI4_INTR0 BIT0 675 #define LPFC_SLI4_INTR1 BIT1 676 #define LPFC_SLI4_INTR2 BIT2 677 #define LPFC_SLI4_INTR3 BIT3 678 #define LPFC_SLI4_INTR4 BIT4 679 #define LPFC_SLI4_INTR5 BIT5 680 #define LPFC_SLI4_INTR6 BIT6 681 #define LPFC_SLI4_INTR7 BIT7 682 #define LPFC_SLI4_INTR8 BIT8 683 #define LPFC_SLI4_INTR9 BIT9 684 #define LPFC_SLI4_INTR10 BIT10 685 #define LPFC_SLI4_INTR11 BIT11 686 #define LPFC_SLI4_INTR12 BIT12 687 #define LPFC_SLI4_INTR13 BIT13 688 #define LPFC_SLI4_INTR14 BIT14 689 #define LPFC_SLI4_INTR15 BIT15 690 #define LPFC_SLI4_INTR16 BIT16 691 #define LPFC_SLI4_INTR17 BIT17 692 #define LPFC_SLI4_INTR18 BIT18 693 #define LPFC_SLI4_INTR19 BIT19 694 #define LPFC_SLI4_INTR20 BIT20 695 #define LPFC_SLI4_INTR21 BIT21 696 #define LPFC_SLI4_INTR22 BIT22 697 #define LPFC_SLI4_INTR23 BIT23 698 #define LPFC_SLI4_INTR24 BIT24 699 #define LPFC_SLI4_INTR25 BIT25 700 #define LPFC_SLI4_INTR26 BIT26 701 #define LPFC_SLI4_INTR27 BIT27 702 #define LPFC_SLI4_INTR28 BIT28 703 #define LPFC_SLI4_INTR29 BIT29 704 #define LPFC_SLI4_INTR30 BIT30 705 #define LPFC_SLI4_INTR31 BIT31 706 707 /* 708 * The Doorbell registers defined here exist in different BAR 709 * register sets depending on the UCNA Port's reported if_type 710 * value. For UCNA ports running SLI4 and if_type 0, they reside in 711 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in 712 * BAR0. The offsets are the same so the driver must account for 713 * any base address difference. 714 */ 715 #define LPFC_ULP0_RQ_DOORBELL 0x00A0 716 #define LPFC_ULP1_RQ_DOORBELL 0x00C0 717 #define lpfc_rq_db_list_fm_num_posted_SHIFT 24 718 #define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF 719 #define lpfc_rq_db_list_fm_num_posted_WORD word0 720 #define lpfc_rq_db_list_fm_index_SHIFT 16 721 #define lpfc_rq_db_list_fm_index_MASK 0x00FF 722 #define lpfc_rq_db_list_fm_index_WORD word0 723 #define lpfc_rq_db_list_fm_id_SHIFT 0 724 #define lpfc_rq_db_list_fm_id_MASK 0xFFFF 725 #define lpfc_rq_db_list_fm_id_WORD word0 726 #define lpfc_rq_db_ring_fm_num_posted_SHIFT 16 727 #define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF 728 #define lpfc_rq_db_ring_fm_num_posted_WORD word0 729 #define lpfc_rq_db_ring_fm_id_SHIFT 0 730 #define lpfc_rq_db_ring_fm_id_MASK 0xFFFF 731 #define lpfc_rq_db_ring_fm_id_WORD word0 732 733 #define LPFC_ULP0_WQ_DOORBELL 0x0040 734 #define LPFC_ULP1_WQ_DOORBELL 0x0060 735 #define lpfc_wq_db_list_fm_num_posted_SHIFT 24 736 #define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF 737 #define lpfc_wq_db_list_fm_num_posted_WORD word0 738 #define lpfc_wq_db_list_fm_index_SHIFT 16 739 #define lpfc_wq_db_list_fm_index_MASK 0x00FF 740 #define lpfc_wq_db_list_fm_index_WORD word0 741 #define lpfc_wq_db_list_fm_id_SHIFT 0 742 #define lpfc_wq_db_list_fm_id_MASK 0xFFFF 743 #define lpfc_wq_db_list_fm_id_WORD word0 744 #define lpfc_wq_db_ring_fm_num_posted_SHIFT 16 745 #define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF 746 #define lpfc_wq_db_ring_fm_num_posted_WORD word0 747 #define lpfc_wq_db_ring_fm_id_SHIFT 0 748 #define lpfc_wq_db_ring_fm_id_MASK 0xFFFF 749 #define lpfc_wq_db_ring_fm_id_WORD word0 750 751 #define LPFC_EQCQ_DOORBELL 0x0120 752 #define lpfc_eqcq_doorbell_se_SHIFT 31 753 #define lpfc_eqcq_doorbell_se_MASK 0x0001 754 #define lpfc_eqcq_doorbell_se_WORD word0 755 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0 756 #define LPFC_EQCQ_SOLICIT_ENABLE_ON 1 757 #define lpfc_eqcq_doorbell_arm_SHIFT 29 758 #define lpfc_eqcq_doorbell_arm_MASK 0x0001 759 #define lpfc_eqcq_doorbell_arm_WORD word0 760 #define lpfc_eqcq_doorbell_num_released_SHIFT 16 761 #define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF 762 #define lpfc_eqcq_doorbell_num_released_WORD word0 763 #define lpfc_eqcq_doorbell_qt_SHIFT 10 764 #define lpfc_eqcq_doorbell_qt_MASK 0x0001 765 #define lpfc_eqcq_doorbell_qt_WORD word0 766 #define LPFC_QUEUE_TYPE_COMPLETION 0 767 #define LPFC_QUEUE_TYPE_EVENT 1 768 #define lpfc_eqcq_doorbell_eqci_SHIFT 9 769 #define lpfc_eqcq_doorbell_eqci_MASK 0x0001 770 #define lpfc_eqcq_doorbell_eqci_WORD word0 771 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0 772 #define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF 773 #define lpfc_eqcq_doorbell_cqid_lo_WORD word0 774 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11 775 #define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F 776 #define lpfc_eqcq_doorbell_cqid_hi_WORD word0 777 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0 778 #define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF 779 #define lpfc_eqcq_doorbell_eqid_lo_WORD word0 780 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11 781 #define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F 782 #define lpfc_eqcq_doorbell_eqid_hi_WORD word0 783 #define LPFC_CQID_HI_FIELD_SHIFT 10 784 #define LPFC_EQID_HI_FIELD_SHIFT 9 785 786 #define LPFC_BMBX 0x0160 787 #define lpfc_bmbx_addr_SHIFT 2 788 #define lpfc_bmbx_addr_MASK 0x3FFFFFFF 789 #define lpfc_bmbx_addr_WORD word0 790 #define lpfc_bmbx_hi_SHIFT 1 791 #define lpfc_bmbx_hi_MASK 0x0001 792 #define lpfc_bmbx_hi_WORD word0 793 #define lpfc_bmbx_rdy_SHIFT 0 794 #define lpfc_bmbx_rdy_MASK 0x0001 795 #define lpfc_bmbx_rdy_WORD word0 796 797 #define LPFC_MQ_DOORBELL 0x0140 798 #define lpfc_mq_doorbell_num_posted_SHIFT 16 799 #define lpfc_mq_doorbell_num_posted_MASK 0x3FFF 800 #define lpfc_mq_doorbell_num_posted_WORD word0 801 #define lpfc_mq_doorbell_id_SHIFT 0 802 #define lpfc_mq_doorbell_id_MASK 0xFFFF 803 #define lpfc_mq_doorbell_id_WORD word0 804 805 struct lpfc_sli4_cfg_mhdr { 806 uint32_t word1; 807 #define lpfc_mbox_hdr_emb_SHIFT 0 808 #define lpfc_mbox_hdr_emb_MASK 0x00000001 809 #define lpfc_mbox_hdr_emb_WORD word1 810 #define lpfc_mbox_hdr_sge_cnt_SHIFT 3 811 #define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F 812 #define lpfc_mbox_hdr_sge_cnt_WORD word1 813 uint32_t payload_length; 814 uint32_t tag_lo; 815 uint32_t tag_hi; 816 uint32_t reserved5; 817 }; 818 819 union lpfc_sli4_cfg_shdr { 820 struct { 821 uint32_t word6; 822 #define lpfc_mbox_hdr_opcode_SHIFT 0 823 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 824 #define lpfc_mbox_hdr_opcode_WORD word6 825 #define lpfc_mbox_hdr_subsystem_SHIFT 8 826 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 827 #define lpfc_mbox_hdr_subsystem_WORD word6 828 #define lpfc_mbox_hdr_port_number_SHIFT 16 829 #define lpfc_mbox_hdr_port_number_MASK 0x000000FF 830 #define lpfc_mbox_hdr_port_number_WORD word6 831 #define lpfc_mbox_hdr_domain_SHIFT 24 832 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 833 #define lpfc_mbox_hdr_domain_WORD word6 834 uint32_t timeout; 835 uint32_t request_length; 836 uint32_t word9; 837 #define lpfc_mbox_hdr_version_SHIFT 0 838 #define lpfc_mbox_hdr_version_MASK 0x000000FF 839 #define lpfc_mbox_hdr_version_WORD word9 840 #define lpfc_mbox_hdr_pf_num_SHIFT 16 841 #define lpfc_mbox_hdr_pf_num_MASK 0x000000FF 842 #define lpfc_mbox_hdr_pf_num_WORD word9 843 #define lpfc_mbox_hdr_vh_num_SHIFT 24 844 #define lpfc_mbox_hdr_vh_num_MASK 0x000000FF 845 #define lpfc_mbox_hdr_vh_num_WORD word9 846 #define LPFC_Q_CREATE_VERSION_2 2 847 #define LPFC_Q_CREATE_VERSION_1 1 848 #define LPFC_Q_CREATE_VERSION_0 0 849 #define LPFC_OPCODE_VERSION_0 0 850 #define LPFC_OPCODE_VERSION_1 1 851 } request; 852 struct { 853 uint32_t word6; 854 #define lpfc_mbox_hdr_opcode_SHIFT 0 855 #define lpfc_mbox_hdr_opcode_MASK 0x000000FF 856 #define lpfc_mbox_hdr_opcode_WORD word6 857 #define lpfc_mbox_hdr_subsystem_SHIFT 8 858 #define lpfc_mbox_hdr_subsystem_MASK 0x000000FF 859 #define lpfc_mbox_hdr_subsystem_WORD word6 860 #define lpfc_mbox_hdr_domain_SHIFT 24 861 #define lpfc_mbox_hdr_domain_MASK 0x000000FF 862 #define lpfc_mbox_hdr_domain_WORD word6 863 uint32_t word7; 864 #define lpfc_mbox_hdr_status_SHIFT 0 865 #define lpfc_mbox_hdr_status_MASK 0x000000FF 866 #define lpfc_mbox_hdr_status_WORD word7 867 #define lpfc_mbox_hdr_add_status_SHIFT 8 868 #define lpfc_mbox_hdr_add_status_MASK 0x000000FF 869 #define lpfc_mbox_hdr_add_status_WORD word7 870 uint32_t response_length; 871 uint32_t actual_response_length; 872 } response; 873 }; 874 875 /* Mailbox Header structures. 876 * struct mbox_header is defined for first generation SLI4_CFG mailbox 877 * calls deployed for BE-based ports. 878 * 879 * struct sli4_mbox_header is defined for second generation SLI4 880 * ports that don't deploy the SLI4_CFG mechanism. 881 */ 882 struct mbox_header { 883 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 884 union lpfc_sli4_cfg_shdr cfg_shdr; 885 }; 886 887 #define LPFC_EXTENT_LOCAL 0 888 #define LPFC_TIMEOUT_DEFAULT 0 889 #define LPFC_EXTENT_VERSION_DEFAULT 0 890 891 /* Subsystem Definitions */ 892 #define LPFC_MBOX_SUBSYSTEM_NA 0x0 893 #define LPFC_MBOX_SUBSYSTEM_COMMON 0x1 894 #define LPFC_MBOX_SUBSYSTEM_FCOE 0xC 895 896 /* Device Specific Definitions */ 897 898 /* The HOST ENDIAN defines are in Big Endian format. */ 899 #define HOST_ENDIAN_LOW_WORD0 0xFF3412FF 900 #define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF 901 902 /* Common Opcodes */ 903 #define LPFC_MBOX_OPCODE_NA 0x00 904 #define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C 905 #define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D 906 #define LPFC_MBOX_OPCODE_MQ_CREATE 0x15 907 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20 908 #define LPFC_MBOX_OPCODE_NOP 0x21 909 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29 910 #define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35 911 #define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36 912 #define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37 913 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A 914 #define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D 915 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E 916 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43 917 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45 918 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46 919 #define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D 920 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A 921 #define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B 922 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73 923 #define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74 924 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A 925 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B 926 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C 927 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D 928 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0 929 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1 930 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4 931 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5 932 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6 933 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8 934 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9 935 #define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB 936 #define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC 937 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD 938 #define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE 939 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5 940 941 /* FCoE Opcodes */ 942 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01 943 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02 944 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03 945 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04 946 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05 947 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06 948 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08 949 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09 950 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A 951 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B 952 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10 953 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21 954 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22 955 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23 956 957 /* Mailbox command structures */ 958 struct eq_context { 959 uint32_t word0; 960 #define lpfc_eq_context_size_SHIFT 31 961 #define lpfc_eq_context_size_MASK 0x00000001 962 #define lpfc_eq_context_size_WORD word0 963 #define LPFC_EQE_SIZE_4 0x0 964 #define LPFC_EQE_SIZE_16 0x1 965 #define lpfc_eq_context_valid_SHIFT 29 966 #define lpfc_eq_context_valid_MASK 0x00000001 967 #define lpfc_eq_context_valid_WORD word0 968 uint32_t word1; 969 #define lpfc_eq_context_count_SHIFT 26 970 #define lpfc_eq_context_count_MASK 0x00000003 971 #define lpfc_eq_context_count_WORD word1 972 #define LPFC_EQ_CNT_256 0x0 973 #define LPFC_EQ_CNT_512 0x1 974 #define LPFC_EQ_CNT_1024 0x2 975 #define LPFC_EQ_CNT_2048 0x3 976 #define LPFC_EQ_CNT_4096 0x4 977 uint32_t word2; 978 #define lpfc_eq_context_delay_multi_SHIFT 13 979 #define lpfc_eq_context_delay_multi_MASK 0x000003FF 980 #define lpfc_eq_context_delay_multi_WORD word2 981 uint32_t reserved3; 982 }; 983 984 struct eq_delay_info { 985 uint32_t eq_id; 986 uint32_t phase; 987 uint32_t delay_multi; 988 }; 989 #define LPFC_MAX_EQ_DELAY 8 990 991 struct sgl_page_pairs { 992 uint32_t sgl_pg0_addr_lo; 993 uint32_t sgl_pg0_addr_hi; 994 uint32_t sgl_pg1_addr_lo; 995 uint32_t sgl_pg1_addr_hi; 996 }; 997 998 struct lpfc_mbx_post_sgl_pages { 999 struct mbox_header header; 1000 uint32_t word0; 1001 #define lpfc_post_sgl_pages_xri_SHIFT 0 1002 #define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF 1003 #define lpfc_post_sgl_pages_xri_WORD word0 1004 #define lpfc_post_sgl_pages_xricnt_SHIFT 16 1005 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF 1006 #define lpfc_post_sgl_pages_xricnt_WORD word0 1007 struct sgl_page_pairs sgl_pg_pairs[1]; 1008 }; 1009 1010 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */ 1011 struct lpfc_mbx_post_uembed_sgl_page1 { 1012 union lpfc_sli4_cfg_shdr cfg_shdr; 1013 uint32_t word0; 1014 struct sgl_page_pairs sgl_pg_pairs; 1015 }; 1016 1017 struct lpfc_mbx_sge { 1018 uint32_t pa_lo; 1019 uint32_t pa_hi; 1020 uint32_t length; 1021 }; 1022 1023 struct lpfc_mbx_nembed_cmd { 1024 struct lpfc_sli4_cfg_mhdr cfg_mhdr; 1025 #define LPFC_SLI4_MBX_SGE_MAX_PAGES 19 1026 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1027 }; 1028 1029 struct lpfc_mbx_nembed_sge_virt { 1030 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES]; 1031 }; 1032 1033 struct lpfc_mbx_eq_create { 1034 struct mbox_header header; 1035 union { 1036 struct { 1037 uint32_t word0; 1038 #define lpfc_mbx_eq_create_num_pages_SHIFT 0 1039 #define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF 1040 #define lpfc_mbx_eq_create_num_pages_WORD word0 1041 struct eq_context context; 1042 struct dma_address page[LPFC_MAX_EQ_PAGE]; 1043 } request; 1044 struct { 1045 uint32_t word0; 1046 #define lpfc_mbx_eq_create_q_id_SHIFT 0 1047 #define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF 1048 #define lpfc_mbx_eq_create_q_id_WORD word0 1049 } response; 1050 } u; 1051 }; 1052 1053 struct lpfc_mbx_modify_eq_delay { 1054 struct mbox_header header; 1055 union { 1056 struct { 1057 uint32_t num_eq; 1058 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY]; 1059 } request; 1060 struct { 1061 uint32_t word0; 1062 } response; 1063 } u; 1064 }; 1065 1066 struct lpfc_mbx_eq_destroy { 1067 struct mbox_header header; 1068 union { 1069 struct { 1070 uint32_t word0; 1071 #define lpfc_mbx_eq_destroy_q_id_SHIFT 0 1072 #define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF 1073 #define lpfc_mbx_eq_destroy_q_id_WORD word0 1074 } request; 1075 struct { 1076 uint32_t word0; 1077 } response; 1078 } u; 1079 }; 1080 1081 struct lpfc_mbx_nop { 1082 struct mbox_header header; 1083 uint32_t context[2]; 1084 }; 1085 1086 struct cq_context { 1087 uint32_t word0; 1088 #define lpfc_cq_context_event_SHIFT 31 1089 #define lpfc_cq_context_event_MASK 0x00000001 1090 #define lpfc_cq_context_event_WORD word0 1091 #define lpfc_cq_context_valid_SHIFT 29 1092 #define lpfc_cq_context_valid_MASK 0x00000001 1093 #define lpfc_cq_context_valid_WORD word0 1094 #define lpfc_cq_context_count_SHIFT 27 1095 #define lpfc_cq_context_count_MASK 0x00000003 1096 #define lpfc_cq_context_count_WORD word0 1097 #define LPFC_CQ_CNT_256 0x0 1098 #define LPFC_CQ_CNT_512 0x1 1099 #define LPFC_CQ_CNT_1024 0x2 1100 uint32_t word1; 1101 #define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */ 1102 #define lpfc_cq_eq_id_MASK 0x000000FF 1103 #define lpfc_cq_eq_id_WORD word1 1104 #define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */ 1105 #define lpfc_cq_eq_id_2_MASK 0x0000FFFF 1106 #define lpfc_cq_eq_id_2_WORD word1 1107 uint32_t reserved0; 1108 uint32_t reserved1; 1109 }; 1110 1111 struct lpfc_mbx_cq_create { 1112 struct mbox_header header; 1113 union { 1114 struct { 1115 uint32_t word0; 1116 #define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */ 1117 #define lpfc_mbx_cq_create_page_size_MASK 0x000000FF 1118 #define lpfc_mbx_cq_create_page_size_WORD word0 1119 #define lpfc_mbx_cq_create_num_pages_SHIFT 0 1120 #define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF 1121 #define lpfc_mbx_cq_create_num_pages_WORD word0 1122 struct cq_context context; 1123 struct dma_address page[LPFC_MAX_CQ_PAGE]; 1124 } request; 1125 struct { 1126 uint32_t word0; 1127 #define lpfc_mbx_cq_create_q_id_SHIFT 0 1128 #define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF 1129 #define lpfc_mbx_cq_create_q_id_WORD word0 1130 } response; 1131 } u; 1132 }; 1133 1134 struct lpfc_mbx_cq_destroy { 1135 struct mbox_header header; 1136 union { 1137 struct { 1138 uint32_t word0; 1139 #define lpfc_mbx_cq_destroy_q_id_SHIFT 0 1140 #define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF 1141 #define lpfc_mbx_cq_destroy_q_id_WORD word0 1142 } request; 1143 struct { 1144 uint32_t word0; 1145 } response; 1146 } u; 1147 }; 1148 1149 struct wq_context { 1150 uint32_t reserved0; 1151 uint32_t reserved1; 1152 uint32_t reserved2; 1153 uint32_t reserved3; 1154 }; 1155 1156 struct lpfc_mbx_wq_create { 1157 struct mbox_header header; 1158 union { 1159 struct { /* Version 0 Request */ 1160 uint32_t word0; 1161 #define lpfc_mbx_wq_create_num_pages_SHIFT 0 1162 #define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF 1163 #define lpfc_mbx_wq_create_num_pages_WORD word0 1164 #define lpfc_mbx_wq_create_dua_SHIFT 8 1165 #define lpfc_mbx_wq_create_dua_MASK 0x00000001 1166 #define lpfc_mbx_wq_create_dua_WORD word0 1167 #define lpfc_mbx_wq_create_cq_id_SHIFT 16 1168 #define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF 1169 #define lpfc_mbx_wq_create_cq_id_WORD word0 1170 struct dma_address page[LPFC_MAX_WQ_PAGE_V0]; 1171 uint32_t word9; 1172 #define lpfc_mbx_wq_create_bua_SHIFT 0 1173 #define lpfc_mbx_wq_create_bua_MASK 0x00000001 1174 #define lpfc_mbx_wq_create_bua_WORD word9 1175 #define lpfc_mbx_wq_create_ulp_num_SHIFT 8 1176 #define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF 1177 #define lpfc_mbx_wq_create_ulp_num_WORD word9 1178 } request; 1179 struct { /* Version 1 Request */ 1180 uint32_t word0; /* Word 0 is the same as in v0 */ 1181 uint32_t word1; 1182 #define lpfc_mbx_wq_create_page_size_SHIFT 0 1183 #define lpfc_mbx_wq_create_page_size_MASK 0x000000FF 1184 #define lpfc_mbx_wq_create_page_size_WORD word1 1185 #define lpfc_mbx_wq_create_wqe_size_SHIFT 8 1186 #define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F 1187 #define lpfc_mbx_wq_create_wqe_size_WORD word1 1188 #define LPFC_WQ_WQE_SIZE_64 0x5 1189 #define LPFC_WQ_WQE_SIZE_128 0x6 1190 #define lpfc_mbx_wq_create_wqe_count_SHIFT 16 1191 #define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF 1192 #define lpfc_mbx_wq_create_wqe_count_WORD word1 1193 uint32_t word2; 1194 struct dma_address page[LPFC_MAX_WQ_PAGE-1]; 1195 } request_1; 1196 struct { 1197 uint32_t word0; 1198 #define lpfc_mbx_wq_create_q_id_SHIFT 0 1199 #define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF 1200 #define lpfc_mbx_wq_create_q_id_WORD word0 1201 uint32_t doorbell_offset; 1202 uint32_t word2; 1203 #define lpfc_mbx_wq_create_bar_set_SHIFT 0 1204 #define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF 1205 #define lpfc_mbx_wq_create_bar_set_WORD word2 1206 #define WQ_PCI_BAR_0_AND_1 0x00 1207 #define WQ_PCI_BAR_2_AND_3 0x01 1208 #define WQ_PCI_BAR_4_AND_5 0x02 1209 #define lpfc_mbx_wq_create_db_format_SHIFT 16 1210 #define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF 1211 #define lpfc_mbx_wq_create_db_format_WORD word2 1212 } response; 1213 } u; 1214 }; 1215 1216 struct lpfc_mbx_wq_destroy { 1217 struct mbox_header header; 1218 union { 1219 struct { 1220 uint32_t word0; 1221 #define lpfc_mbx_wq_destroy_q_id_SHIFT 0 1222 #define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF 1223 #define lpfc_mbx_wq_destroy_q_id_WORD word0 1224 } request; 1225 struct { 1226 uint32_t word0; 1227 } response; 1228 } u; 1229 }; 1230 1231 #define LPFC_HDR_BUF_SIZE 128 1232 #define LPFC_DATA_BUF_SIZE 2048 1233 struct rq_context { 1234 uint32_t word0; 1235 #define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */ 1236 #define lpfc_rq_context_rqe_count_MASK 0x0000000F 1237 #define lpfc_rq_context_rqe_count_WORD word0 1238 #define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */ 1239 #define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */ 1240 #define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */ 1241 #define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */ 1242 #define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1 Only */ 1243 #define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF 1244 #define lpfc_rq_context_rqe_count_1_WORD word0 1245 #define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1 Only */ 1246 #define lpfc_rq_context_rqe_size_MASK 0x0000000F 1247 #define lpfc_rq_context_rqe_size_WORD word0 1248 #define LPFC_RQE_SIZE_8 2 1249 #define LPFC_RQE_SIZE_16 3 1250 #define LPFC_RQE_SIZE_32 4 1251 #define LPFC_RQE_SIZE_64 5 1252 #define LPFC_RQE_SIZE_128 6 1253 #define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */ 1254 #define lpfc_rq_context_page_size_MASK 0x000000FF 1255 #define lpfc_rq_context_page_size_WORD word0 1256 uint32_t reserved1; 1257 uint32_t word2; 1258 #define lpfc_rq_context_cq_id_SHIFT 16 1259 #define lpfc_rq_context_cq_id_MASK 0x000003FF 1260 #define lpfc_rq_context_cq_id_WORD word2 1261 #define lpfc_rq_context_buf_size_SHIFT 0 1262 #define lpfc_rq_context_buf_size_MASK 0x0000FFFF 1263 #define lpfc_rq_context_buf_size_WORD word2 1264 uint32_t buffer_size; /* Version 1 Only */ 1265 }; 1266 1267 struct lpfc_mbx_rq_create { 1268 struct mbox_header header; 1269 union { 1270 struct { 1271 uint32_t word0; 1272 #define lpfc_mbx_rq_create_num_pages_SHIFT 0 1273 #define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF 1274 #define lpfc_mbx_rq_create_num_pages_WORD word0 1275 #define lpfc_mbx_rq_create_dua_SHIFT 16 1276 #define lpfc_mbx_rq_create_dua_MASK 0x00000001 1277 #define lpfc_mbx_rq_create_dua_WORD word0 1278 #define lpfc_mbx_rq_create_bqu_SHIFT 17 1279 #define lpfc_mbx_rq_create_bqu_MASK 0x00000001 1280 #define lpfc_mbx_rq_create_bqu_WORD word0 1281 #define lpfc_mbx_rq_create_ulp_num_SHIFT 24 1282 #define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF 1283 #define lpfc_mbx_rq_create_ulp_num_WORD word0 1284 struct rq_context context; 1285 struct dma_address page[LPFC_MAX_WQ_PAGE]; 1286 } request; 1287 struct { 1288 uint32_t word0; 1289 #define lpfc_mbx_rq_create_q_id_SHIFT 0 1290 #define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF 1291 #define lpfc_mbx_rq_create_q_id_WORD word0 1292 uint32_t doorbell_offset; 1293 uint32_t word2; 1294 #define lpfc_mbx_rq_create_bar_set_SHIFT 0 1295 #define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF 1296 #define lpfc_mbx_rq_create_bar_set_WORD word2 1297 #define lpfc_mbx_rq_create_db_format_SHIFT 16 1298 #define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF 1299 #define lpfc_mbx_rq_create_db_format_WORD word2 1300 } response; 1301 } u; 1302 }; 1303 1304 struct lpfc_mbx_rq_destroy { 1305 struct mbox_header header; 1306 union { 1307 struct { 1308 uint32_t word0; 1309 #define lpfc_mbx_rq_destroy_q_id_SHIFT 0 1310 #define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF 1311 #define lpfc_mbx_rq_destroy_q_id_WORD word0 1312 } request; 1313 struct { 1314 uint32_t word0; 1315 } response; 1316 } u; 1317 }; 1318 1319 struct mq_context { 1320 uint32_t word0; 1321 #define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */ 1322 #define lpfc_mq_context_cq_id_MASK 0x000003FF 1323 #define lpfc_mq_context_cq_id_WORD word0 1324 #define lpfc_mq_context_ring_size_SHIFT 16 1325 #define lpfc_mq_context_ring_size_MASK 0x0000000F 1326 #define lpfc_mq_context_ring_size_WORD word0 1327 #define LPFC_MQ_RING_SIZE_16 0x5 1328 #define LPFC_MQ_RING_SIZE_32 0x6 1329 #define LPFC_MQ_RING_SIZE_64 0x7 1330 #define LPFC_MQ_RING_SIZE_128 0x8 1331 uint32_t word1; 1332 #define lpfc_mq_context_valid_SHIFT 31 1333 #define lpfc_mq_context_valid_MASK 0x00000001 1334 #define lpfc_mq_context_valid_WORD word1 1335 uint32_t reserved2; 1336 uint32_t reserved3; 1337 }; 1338 1339 struct lpfc_mbx_mq_create { 1340 struct mbox_header header; 1341 union { 1342 struct { 1343 uint32_t word0; 1344 #define lpfc_mbx_mq_create_num_pages_SHIFT 0 1345 #define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF 1346 #define lpfc_mbx_mq_create_num_pages_WORD word0 1347 struct mq_context context; 1348 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1349 } request; 1350 struct { 1351 uint32_t word0; 1352 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1353 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1354 #define lpfc_mbx_mq_create_q_id_WORD word0 1355 } response; 1356 } u; 1357 }; 1358 1359 struct lpfc_mbx_mq_create_ext { 1360 struct mbox_header header; 1361 union { 1362 struct { 1363 uint32_t word0; 1364 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0 1365 #define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF 1366 #define lpfc_mbx_mq_create_ext_num_pages_WORD word0 1367 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */ 1368 #define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF 1369 #define lpfc_mbx_mq_create_ext_cq_id_WORD word0 1370 uint32_t async_evt_bmap; 1371 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK 1372 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001 1373 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap 1374 #define LPFC_EVT_CODE_LINK_NO_LINK 0x0 1375 #define LPFC_EVT_CODE_LINK_10_MBIT 0x1 1376 #define LPFC_EVT_CODE_LINK_100_MBIT 0x2 1377 #define LPFC_EVT_CODE_LINK_1_GBIT 0x3 1378 #define LPFC_EVT_CODE_LINK_10_GBIT 0x4 1379 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE 1380 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001 1381 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap 1382 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5 1383 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001 1384 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap 1385 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC 1386 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001 1387 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap 1388 #define LPFC_EVT_CODE_FC_NO_LINK 0x0 1389 #define LPFC_EVT_CODE_FC_1_GBAUD 0x1 1390 #define LPFC_EVT_CODE_FC_2_GBAUD 0x2 1391 #define LPFC_EVT_CODE_FC_4_GBAUD 0x4 1392 #define LPFC_EVT_CODE_FC_8_GBAUD 0x8 1393 #define LPFC_EVT_CODE_FC_10_GBAUD 0xA 1394 #define LPFC_EVT_CODE_FC_16_GBAUD 0x10 1395 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI 1396 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001 1397 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap 1398 struct mq_context context; 1399 struct dma_address page[LPFC_MAX_MQ_PAGE]; 1400 } request; 1401 struct { 1402 uint32_t word0; 1403 #define lpfc_mbx_mq_create_q_id_SHIFT 0 1404 #define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF 1405 #define lpfc_mbx_mq_create_q_id_WORD word0 1406 } response; 1407 } u; 1408 #define LPFC_ASYNC_EVENT_LINK_STATE 0x2 1409 #define LPFC_ASYNC_EVENT_FCF_STATE 0x4 1410 #define LPFC_ASYNC_EVENT_GROUP5 0x20 1411 }; 1412 1413 struct lpfc_mbx_mq_destroy { 1414 struct mbox_header header; 1415 union { 1416 struct { 1417 uint32_t word0; 1418 #define lpfc_mbx_mq_destroy_q_id_SHIFT 0 1419 #define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF 1420 #define lpfc_mbx_mq_destroy_q_id_WORD word0 1421 } request; 1422 struct { 1423 uint32_t word0; 1424 } response; 1425 } u; 1426 }; 1427 1428 /* Start Gen 2 SLI4 Mailbox definitions: */ 1429 1430 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */ 1431 #define LPFC_RSC_TYPE_FCOE_VFI 0x20 1432 #define LPFC_RSC_TYPE_FCOE_VPI 0x21 1433 #define LPFC_RSC_TYPE_FCOE_RPI 0x22 1434 #define LPFC_RSC_TYPE_FCOE_XRI 0x23 1435 1436 struct lpfc_mbx_get_rsrc_extent_info { 1437 struct mbox_header header; 1438 union { 1439 struct { 1440 uint32_t word4; 1441 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0 1442 #define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF 1443 #define lpfc_mbx_get_rsrc_extent_info_type_WORD word4 1444 } req; 1445 struct { 1446 uint32_t word4; 1447 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0 1448 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF 1449 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4 1450 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16 1451 #define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF 1452 #define lpfc_mbx_get_rsrc_extent_info_size_WORD word4 1453 } rsp; 1454 } u; 1455 }; 1456 1457 struct lpfc_mbx_query_fw_config { 1458 struct mbox_header header; 1459 struct { 1460 uint32_t config_number; 1461 #define LPFC_FC_FCOE 0x00000007 1462 uint32_t asic_revision; 1463 uint32_t physical_port; 1464 uint32_t function_mode; 1465 #define LPFC_FCOE_INI_MODE 0x00000040 1466 #define LPFC_FCOE_TGT_MODE 0x00000080 1467 #define LPFC_DUA_MODE 0x00000800 1468 uint32_t ulp0_mode; 1469 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040 1470 #define LPFC_ULP_FCOE_TGT_MODE 0x00000080 1471 uint32_t ulp0_nap_words[12]; 1472 uint32_t ulp1_mode; 1473 uint32_t ulp1_nap_words[12]; 1474 uint32_t function_capabilities; 1475 uint32_t cqid_base; 1476 uint32_t cqid_tot; 1477 uint32_t eqid_base; 1478 uint32_t eqid_tot; 1479 uint32_t ulp0_nap2_words[2]; 1480 uint32_t ulp1_nap2_words[2]; 1481 } rsp; 1482 }; 1483 1484 struct lpfc_mbx_set_beacon_config { 1485 struct mbox_header header; 1486 uint32_t word4; 1487 #define lpfc_mbx_set_beacon_port_num_SHIFT 0 1488 #define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F 1489 #define lpfc_mbx_set_beacon_port_num_WORD word4 1490 #define lpfc_mbx_set_beacon_port_type_SHIFT 6 1491 #define lpfc_mbx_set_beacon_port_type_MASK 0x00000003 1492 #define lpfc_mbx_set_beacon_port_type_WORD word4 1493 #define lpfc_mbx_set_beacon_state_SHIFT 8 1494 #define lpfc_mbx_set_beacon_state_MASK 0x000000FF 1495 #define lpfc_mbx_set_beacon_state_WORD word4 1496 #define lpfc_mbx_set_beacon_duration_SHIFT 16 1497 #define lpfc_mbx_set_beacon_duration_MASK 0x000000FF 1498 #define lpfc_mbx_set_beacon_duration_WORD word4 1499 #define lpfc_mbx_set_beacon_status_duration_SHIFT 24 1500 #define lpfc_mbx_set_beacon_status_duration_MASK 0x000000FF 1501 #define lpfc_mbx_set_beacon_status_duration_WORD word4 1502 }; 1503 1504 struct lpfc_id_range { 1505 uint32_t word5; 1506 #define lpfc_mbx_rsrc_id_word4_0_SHIFT 0 1507 #define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF 1508 #define lpfc_mbx_rsrc_id_word4_0_WORD word5 1509 #define lpfc_mbx_rsrc_id_word4_1_SHIFT 16 1510 #define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF 1511 #define lpfc_mbx_rsrc_id_word4_1_WORD word5 1512 }; 1513 1514 struct lpfc_mbx_set_link_diag_state { 1515 struct mbox_header header; 1516 union { 1517 struct { 1518 uint32_t word0; 1519 #define lpfc_mbx_set_diag_state_diag_SHIFT 0 1520 #define lpfc_mbx_set_diag_state_diag_MASK 0x00000001 1521 #define lpfc_mbx_set_diag_state_diag_WORD word0 1522 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2 1523 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001 1524 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0 1525 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0 1526 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1 1527 #define lpfc_mbx_set_diag_state_link_num_SHIFT 16 1528 #define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F 1529 #define lpfc_mbx_set_diag_state_link_num_WORD word0 1530 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22 1531 #define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003 1532 #define lpfc_mbx_set_diag_state_link_type_WORD word0 1533 } req; 1534 struct { 1535 uint32_t word0; 1536 } rsp; 1537 } u; 1538 }; 1539 1540 struct lpfc_mbx_set_link_diag_loopback { 1541 struct mbox_header header; 1542 union { 1543 struct { 1544 uint32_t word0; 1545 #define lpfc_mbx_set_diag_lpbk_type_SHIFT 0 1546 #define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003 1547 #define lpfc_mbx_set_diag_lpbk_type_WORD word0 1548 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0 1549 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1 1550 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2 1551 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16 1552 #define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F 1553 #define lpfc_mbx_set_diag_lpbk_link_num_WORD word0 1554 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22 1555 #define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003 1556 #define lpfc_mbx_set_diag_lpbk_link_type_WORD word0 1557 } req; 1558 struct { 1559 uint32_t word0; 1560 } rsp; 1561 } u; 1562 }; 1563 1564 struct lpfc_mbx_run_link_diag_test { 1565 struct mbox_header header; 1566 union { 1567 struct { 1568 uint32_t word0; 1569 #define lpfc_mbx_run_diag_test_link_num_SHIFT 16 1570 #define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F 1571 #define lpfc_mbx_run_diag_test_link_num_WORD word0 1572 #define lpfc_mbx_run_diag_test_link_type_SHIFT 22 1573 #define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003 1574 #define lpfc_mbx_run_diag_test_link_type_WORD word0 1575 uint32_t word1; 1576 #define lpfc_mbx_run_diag_test_test_id_SHIFT 0 1577 #define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF 1578 #define lpfc_mbx_run_diag_test_test_id_WORD word1 1579 #define lpfc_mbx_run_diag_test_loops_SHIFT 16 1580 #define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF 1581 #define lpfc_mbx_run_diag_test_loops_WORD word1 1582 uint32_t word2; 1583 #define lpfc_mbx_run_diag_test_test_ver_SHIFT 0 1584 #define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF 1585 #define lpfc_mbx_run_diag_test_test_ver_WORD word2 1586 #define lpfc_mbx_run_diag_test_err_act_SHIFT 16 1587 #define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF 1588 #define lpfc_mbx_run_diag_test_err_act_WORD word2 1589 } req; 1590 struct { 1591 uint32_t word0; 1592 } rsp; 1593 } u; 1594 }; 1595 1596 /* 1597 * struct lpfc_mbx_alloc_rsrc_extents: 1598 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires 1599 * 6 words of header + 4 words of shared subcommand header + 1600 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total. 1601 * 1602 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes 1603 * for extents payload. 1604 * 1605 * 212/2 (bytes per extent) = 106 extents. 1606 * 106/2 (extents per word) = 53 words. 1607 * lpfc_id_range id is statically size to 53. 1608 * 1609 * This mailbox definition is used for ALLOC or GET_ALLOCATED 1610 * extent ranges. For ALLOC, the type and cnt are required. 1611 * For GET_ALLOCATED, only the type is required. 1612 */ 1613 struct lpfc_mbx_alloc_rsrc_extents { 1614 struct mbox_header header; 1615 union { 1616 struct { 1617 uint32_t word4; 1618 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0 1619 #define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF 1620 #define lpfc_mbx_alloc_rsrc_extents_type_WORD word4 1621 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16 1622 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF 1623 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4 1624 } req; 1625 struct { 1626 uint32_t word4; 1627 #define lpfc_mbx_rsrc_cnt_SHIFT 0 1628 #define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF 1629 #define lpfc_mbx_rsrc_cnt_WORD word4 1630 struct lpfc_id_range id[53]; 1631 } rsp; 1632 } u; 1633 }; 1634 1635 /* 1636 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this 1637 * structure shares the same SHIFT/MASK/WORD defines provided in the 1638 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in 1639 * the structures defined above. This non-embedded structure provides for the 1640 * maximum number of extents supported by the port. 1641 */ 1642 struct lpfc_mbx_nembed_rsrc_extent { 1643 union lpfc_sli4_cfg_shdr cfg_shdr; 1644 uint32_t word4; 1645 struct lpfc_id_range id; 1646 }; 1647 1648 struct lpfc_mbx_dealloc_rsrc_extents { 1649 struct mbox_header header; 1650 struct { 1651 uint32_t word4; 1652 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0 1653 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF 1654 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4 1655 } req; 1656 1657 }; 1658 1659 /* Start SLI4 FCoE specific mbox structures. */ 1660 1661 struct lpfc_mbx_post_hdr_tmpl { 1662 struct mbox_header header; 1663 uint32_t word10; 1664 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0 1665 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF 1666 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10 1667 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16 1668 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF 1669 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10 1670 uint32_t rpi_paddr_lo; 1671 uint32_t rpi_paddr_hi; 1672 }; 1673 1674 struct sli4_sge { /* SLI-4 */ 1675 uint32_t addr_hi; 1676 uint32_t addr_lo; 1677 1678 uint32_t word2; 1679 #define lpfc_sli4_sge_offset_SHIFT 0 1680 #define lpfc_sli4_sge_offset_MASK 0x07FFFFFF 1681 #define lpfc_sli4_sge_offset_WORD word2 1682 #define lpfc_sli4_sge_type_SHIFT 27 1683 #define lpfc_sli4_sge_type_MASK 0x0000000F 1684 #define lpfc_sli4_sge_type_WORD word2 1685 #define LPFC_SGE_TYPE_DATA 0x0 1686 #define LPFC_SGE_TYPE_DIF 0x4 1687 #define LPFC_SGE_TYPE_LSP 0x5 1688 #define LPFC_SGE_TYPE_PEDIF 0x6 1689 #define LPFC_SGE_TYPE_PESEED 0x7 1690 #define LPFC_SGE_TYPE_DISEED 0x8 1691 #define LPFC_SGE_TYPE_ENC 0x9 1692 #define LPFC_SGE_TYPE_ATM 0xA 1693 #define LPFC_SGE_TYPE_SKIP 0xC 1694 #define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1695 #define lpfc_sli4_sge_last_MASK 0x00000001 1696 #define lpfc_sli4_sge_last_WORD word2 1697 uint32_t sge_len; 1698 }; 1699 1700 struct sli4_sge_diseed { /* SLI-4 */ 1701 uint32_t ref_tag; 1702 uint32_t ref_tag_tran; 1703 1704 uint32_t word2; 1705 #define lpfc_sli4_sge_dif_apptran_SHIFT 0 1706 #define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF 1707 #define lpfc_sli4_sge_dif_apptran_WORD word2 1708 #define lpfc_sli4_sge_dif_af_SHIFT 24 1709 #define lpfc_sli4_sge_dif_af_MASK 0x00000001 1710 #define lpfc_sli4_sge_dif_af_WORD word2 1711 #define lpfc_sli4_sge_dif_na_SHIFT 25 1712 #define lpfc_sli4_sge_dif_na_MASK 0x00000001 1713 #define lpfc_sli4_sge_dif_na_WORD word2 1714 #define lpfc_sli4_sge_dif_hi_SHIFT 26 1715 #define lpfc_sli4_sge_dif_hi_MASK 0x00000001 1716 #define lpfc_sli4_sge_dif_hi_WORD word2 1717 #define lpfc_sli4_sge_dif_type_SHIFT 27 1718 #define lpfc_sli4_sge_dif_type_MASK 0x0000000F 1719 #define lpfc_sli4_sge_dif_type_WORD word2 1720 #define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */ 1721 #define lpfc_sli4_sge_dif_last_MASK 0x00000001 1722 #define lpfc_sli4_sge_dif_last_WORD word2 1723 uint32_t word3; 1724 #define lpfc_sli4_sge_dif_apptag_SHIFT 0 1725 #define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF 1726 #define lpfc_sli4_sge_dif_apptag_WORD word3 1727 #define lpfc_sli4_sge_dif_bs_SHIFT 16 1728 #define lpfc_sli4_sge_dif_bs_MASK 0x00000007 1729 #define lpfc_sli4_sge_dif_bs_WORD word3 1730 #define lpfc_sli4_sge_dif_ai_SHIFT 19 1731 #define lpfc_sli4_sge_dif_ai_MASK 0x00000001 1732 #define lpfc_sli4_sge_dif_ai_WORD word3 1733 #define lpfc_sli4_sge_dif_me_SHIFT 20 1734 #define lpfc_sli4_sge_dif_me_MASK 0x00000001 1735 #define lpfc_sli4_sge_dif_me_WORD word3 1736 #define lpfc_sli4_sge_dif_re_SHIFT 21 1737 #define lpfc_sli4_sge_dif_re_MASK 0x00000001 1738 #define lpfc_sli4_sge_dif_re_WORD word3 1739 #define lpfc_sli4_sge_dif_ce_SHIFT 22 1740 #define lpfc_sli4_sge_dif_ce_MASK 0x00000001 1741 #define lpfc_sli4_sge_dif_ce_WORD word3 1742 #define lpfc_sli4_sge_dif_nr_SHIFT 23 1743 #define lpfc_sli4_sge_dif_nr_MASK 0x00000001 1744 #define lpfc_sli4_sge_dif_nr_WORD word3 1745 #define lpfc_sli4_sge_dif_oprx_SHIFT 24 1746 #define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F 1747 #define lpfc_sli4_sge_dif_oprx_WORD word3 1748 #define lpfc_sli4_sge_dif_optx_SHIFT 28 1749 #define lpfc_sli4_sge_dif_optx_MASK 0x0000000F 1750 #define lpfc_sli4_sge_dif_optx_WORD word3 1751 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */ 1752 }; 1753 1754 struct fcf_record { 1755 uint32_t max_rcv_size; 1756 uint32_t fka_adv_period; 1757 uint32_t fip_priority; 1758 uint32_t word3; 1759 #define lpfc_fcf_record_mac_0_SHIFT 0 1760 #define lpfc_fcf_record_mac_0_MASK 0x000000FF 1761 #define lpfc_fcf_record_mac_0_WORD word3 1762 #define lpfc_fcf_record_mac_1_SHIFT 8 1763 #define lpfc_fcf_record_mac_1_MASK 0x000000FF 1764 #define lpfc_fcf_record_mac_1_WORD word3 1765 #define lpfc_fcf_record_mac_2_SHIFT 16 1766 #define lpfc_fcf_record_mac_2_MASK 0x000000FF 1767 #define lpfc_fcf_record_mac_2_WORD word3 1768 #define lpfc_fcf_record_mac_3_SHIFT 24 1769 #define lpfc_fcf_record_mac_3_MASK 0x000000FF 1770 #define lpfc_fcf_record_mac_3_WORD word3 1771 uint32_t word4; 1772 #define lpfc_fcf_record_mac_4_SHIFT 0 1773 #define lpfc_fcf_record_mac_4_MASK 0x000000FF 1774 #define lpfc_fcf_record_mac_4_WORD word4 1775 #define lpfc_fcf_record_mac_5_SHIFT 8 1776 #define lpfc_fcf_record_mac_5_MASK 0x000000FF 1777 #define lpfc_fcf_record_mac_5_WORD word4 1778 #define lpfc_fcf_record_fcf_avail_SHIFT 16 1779 #define lpfc_fcf_record_fcf_avail_MASK 0x000000FF 1780 #define lpfc_fcf_record_fcf_avail_WORD word4 1781 #define lpfc_fcf_record_mac_addr_prov_SHIFT 24 1782 #define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF 1783 #define lpfc_fcf_record_mac_addr_prov_WORD word4 1784 #define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */ 1785 #define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */ 1786 uint32_t word5; 1787 #define lpfc_fcf_record_fab_name_0_SHIFT 0 1788 #define lpfc_fcf_record_fab_name_0_MASK 0x000000FF 1789 #define lpfc_fcf_record_fab_name_0_WORD word5 1790 #define lpfc_fcf_record_fab_name_1_SHIFT 8 1791 #define lpfc_fcf_record_fab_name_1_MASK 0x000000FF 1792 #define lpfc_fcf_record_fab_name_1_WORD word5 1793 #define lpfc_fcf_record_fab_name_2_SHIFT 16 1794 #define lpfc_fcf_record_fab_name_2_MASK 0x000000FF 1795 #define lpfc_fcf_record_fab_name_2_WORD word5 1796 #define lpfc_fcf_record_fab_name_3_SHIFT 24 1797 #define lpfc_fcf_record_fab_name_3_MASK 0x000000FF 1798 #define lpfc_fcf_record_fab_name_3_WORD word5 1799 uint32_t word6; 1800 #define lpfc_fcf_record_fab_name_4_SHIFT 0 1801 #define lpfc_fcf_record_fab_name_4_MASK 0x000000FF 1802 #define lpfc_fcf_record_fab_name_4_WORD word6 1803 #define lpfc_fcf_record_fab_name_5_SHIFT 8 1804 #define lpfc_fcf_record_fab_name_5_MASK 0x000000FF 1805 #define lpfc_fcf_record_fab_name_5_WORD word6 1806 #define lpfc_fcf_record_fab_name_6_SHIFT 16 1807 #define lpfc_fcf_record_fab_name_6_MASK 0x000000FF 1808 #define lpfc_fcf_record_fab_name_6_WORD word6 1809 #define lpfc_fcf_record_fab_name_7_SHIFT 24 1810 #define lpfc_fcf_record_fab_name_7_MASK 0x000000FF 1811 #define lpfc_fcf_record_fab_name_7_WORD word6 1812 uint32_t word7; 1813 #define lpfc_fcf_record_fc_map_0_SHIFT 0 1814 #define lpfc_fcf_record_fc_map_0_MASK 0x000000FF 1815 #define lpfc_fcf_record_fc_map_0_WORD word7 1816 #define lpfc_fcf_record_fc_map_1_SHIFT 8 1817 #define lpfc_fcf_record_fc_map_1_MASK 0x000000FF 1818 #define lpfc_fcf_record_fc_map_1_WORD word7 1819 #define lpfc_fcf_record_fc_map_2_SHIFT 16 1820 #define lpfc_fcf_record_fc_map_2_MASK 0x000000FF 1821 #define lpfc_fcf_record_fc_map_2_WORD word7 1822 #define lpfc_fcf_record_fcf_valid_SHIFT 24 1823 #define lpfc_fcf_record_fcf_valid_MASK 0x00000001 1824 #define lpfc_fcf_record_fcf_valid_WORD word7 1825 #define lpfc_fcf_record_fcf_fc_SHIFT 25 1826 #define lpfc_fcf_record_fcf_fc_MASK 0x00000001 1827 #define lpfc_fcf_record_fcf_fc_WORD word7 1828 #define lpfc_fcf_record_fcf_sol_SHIFT 31 1829 #define lpfc_fcf_record_fcf_sol_MASK 0x00000001 1830 #define lpfc_fcf_record_fcf_sol_WORD word7 1831 uint32_t word8; 1832 #define lpfc_fcf_record_fcf_index_SHIFT 0 1833 #define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF 1834 #define lpfc_fcf_record_fcf_index_WORD word8 1835 #define lpfc_fcf_record_fcf_state_SHIFT 16 1836 #define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF 1837 #define lpfc_fcf_record_fcf_state_WORD word8 1838 uint8_t vlan_bitmap[512]; 1839 uint32_t word137; 1840 #define lpfc_fcf_record_switch_name_0_SHIFT 0 1841 #define lpfc_fcf_record_switch_name_0_MASK 0x000000FF 1842 #define lpfc_fcf_record_switch_name_0_WORD word137 1843 #define lpfc_fcf_record_switch_name_1_SHIFT 8 1844 #define lpfc_fcf_record_switch_name_1_MASK 0x000000FF 1845 #define lpfc_fcf_record_switch_name_1_WORD word137 1846 #define lpfc_fcf_record_switch_name_2_SHIFT 16 1847 #define lpfc_fcf_record_switch_name_2_MASK 0x000000FF 1848 #define lpfc_fcf_record_switch_name_2_WORD word137 1849 #define lpfc_fcf_record_switch_name_3_SHIFT 24 1850 #define lpfc_fcf_record_switch_name_3_MASK 0x000000FF 1851 #define lpfc_fcf_record_switch_name_3_WORD word137 1852 uint32_t word138; 1853 #define lpfc_fcf_record_switch_name_4_SHIFT 0 1854 #define lpfc_fcf_record_switch_name_4_MASK 0x000000FF 1855 #define lpfc_fcf_record_switch_name_4_WORD word138 1856 #define lpfc_fcf_record_switch_name_5_SHIFT 8 1857 #define lpfc_fcf_record_switch_name_5_MASK 0x000000FF 1858 #define lpfc_fcf_record_switch_name_5_WORD word138 1859 #define lpfc_fcf_record_switch_name_6_SHIFT 16 1860 #define lpfc_fcf_record_switch_name_6_MASK 0x000000FF 1861 #define lpfc_fcf_record_switch_name_6_WORD word138 1862 #define lpfc_fcf_record_switch_name_7_SHIFT 24 1863 #define lpfc_fcf_record_switch_name_7_MASK 0x000000FF 1864 #define lpfc_fcf_record_switch_name_7_WORD word138 1865 }; 1866 1867 struct lpfc_mbx_read_fcf_tbl { 1868 union lpfc_sli4_cfg_shdr cfg_shdr; 1869 union { 1870 struct { 1871 uint32_t word10; 1872 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0 1873 #define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF 1874 #define lpfc_mbx_read_fcf_tbl_indx_WORD word10 1875 } request; 1876 struct { 1877 uint32_t eventag; 1878 } response; 1879 } u; 1880 uint32_t word11; 1881 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0 1882 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF 1883 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11 1884 }; 1885 1886 struct lpfc_mbx_add_fcf_tbl_entry { 1887 union lpfc_sli4_cfg_shdr cfg_shdr; 1888 uint32_t word10; 1889 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0 1890 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF 1891 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10 1892 struct lpfc_mbx_sge fcf_sge; 1893 }; 1894 1895 struct lpfc_mbx_del_fcf_tbl_entry { 1896 struct mbox_header header; 1897 uint32_t word10; 1898 #define lpfc_mbx_del_fcf_tbl_count_SHIFT 0 1899 #define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF 1900 #define lpfc_mbx_del_fcf_tbl_count_WORD word10 1901 #define lpfc_mbx_del_fcf_tbl_index_SHIFT 16 1902 #define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF 1903 #define lpfc_mbx_del_fcf_tbl_index_WORD word10 1904 }; 1905 1906 struct lpfc_mbx_redisc_fcf_tbl { 1907 struct mbox_header header; 1908 uint32_t word10; 1909 #define lpfc_mbx_redisc_fcf_count_SHIFT 0 1910 #define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF 1911 #define lpfc_mbx_redisc_fcf_count_WORD word10 1912 uint32_t resvd; 1913 uint32_t word12; 1914 #define lpfc_mbx_redisc_fcf_index_SHIFT 0 1915 #define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF 1916 #define lpfc_mbx_redisc_fcf_index_WORD word12 1917 }; 1918 1919 /* Status field for embedded SLI_CONFIG mailbox command */ 1920 #define STATUS_SUCCESS 0x0 1921 #define STATUS_FAILED 0x1 1922 #define STATUS_ILLEGAL_REQUEST 0x2 1923 #define STATUS_ILLEGAL_FIELD 0x3 1924 #define STATUS_INSUFFICIENT_BUFFER 0x4 1925 #define STATUS_UNAUTHORIZED_REQUEST 0x5 1926 #define STATUS_FLASHROM_SAVE_FAILED 0x17 1927 #define STATUS_FLASHROM_RESTORE_FAILED 0x18 1928 #define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a 1929 #define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b 1930 #define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c 1931 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d 1932 #define STATUS_ASSERT_FAILED 0x1e 1933 #define STATUS_INVALID_SESSION 0x1f 1934 #define STATUS_INVALID_CONNECTION 0x20 1935 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21 1936 #define STATUS_BTL_NO_FREE_SLOT_PATH 0x24 1937 #define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25 1938 #define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26 1939 #define STATUS_FLASHROM_READ_FAILED 0x27 1940 #define STATUS_POLL_IOCTL_TIMEOUT 0x28 1941 #define STATUS_ERROR_ACITMAIN 0x2a 1942 #define STATUS_REBOOT_REQUIRED 0x2c 1943 #define STATUS_FCF_IN_USE 0x3a 1944 #define STATUS_FCF_TABLE_EMPTY 0x43 1945 1946 /* 1947 * Additional status field for embedded SLI_CONFIG mailbox 1948 * command. 1949 */ 1950 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67 1951 1952 struct lpfc_mbx_sli4_config { 1953 struct mbox_header header; 1954 }; 1955 1956 struct lpfc_mbx_init_vfi { 1957 uint32_t word1; 1958 #define lpfc_init_vfi_vr_SHIFT 31 1959 #define lpfc_init_vfi_vr_MASK 0x00000001 1960 #define lpfc_init_vfi_vr_WORD word1 1961 #define lpfc_init_vfi_vt_SHIFT 30 1962 #define lpfc_init_vfi_vt_MASK 0x00000001 1963 #define lpfc_init_vfi_vt_WORD word1 1964 #define lpfc_init_vfi_vf_SHIFT 29 1965 #define lpfc_init_vfi_vf_MASK 0x00000001 1966 #define lpfc_init_vfi_vf_WORD word1 1967 #define lpfc_init_vfi_vp_SHIFT 28 1968 #define lpfc_init_vfi_vp_MASK 0x00000001 1969 #define lpfc_init_vfi_vp_WORD word1 1970 #define lpfc_init_vfi_vfi_SHIFT 0 1971 #define lpfc_init_vfi_vfi_MASK 0x0000FFFF 1972 #define lpfc_init_vfi_vfi_WORD word1 1973 uint32_t word2; 1974 #define lpfc_init_vfi_vpi_SHIFT 16 1975 #define lpfc_init_vfi_vpi_MASK 0x0000FFFF 1976 #define lpfc_init_vfi_vpi_WORD word2 1977 #define lpfc_init_vfi_fcfi_SHIFT 0 1978 #define lpfc_init_vfi_fcfi_MASK 0x0000FFFF 1979 #define lpfc_init_vfi_fcfi_WORD word2 1980 uint32_t word3; 1981 #define lpfc_init_vfi_pri_SHIFT 13 1982 #define lpfc_init_vfi_pri_MASK 0x00000007 1983 #define lpfc_init_vfi_pri_WORD word3 1984 #define lpfc_init_vfi_vf_id_SHIFT 1 1985 #define lpfc_init_vfi_vf_id_MASK 0x00000FFF 1986 #define lpfc_init_vfi_vf_id_WORD word3 1987 uint32_t word4; 1988 #define lpfc_init_vfi_hop_count_SHIFT 24 1989 #define lpfc_init_vfi_hop_count_MASK 0x000000FF 1990 #define lpfc_init_vfi_hop_count_WORD word4 1991 }; 1992 #define MBX_VFI_IN_USE 0x9F02 1993 1994 1995 struct lpfc_mbx_reg_vfi { 1996 uint32_t word1; 1997 #define lpfc_reg_vfi_upd_SHIFT 29 1998 #define lpfc_reg_vfi_upd_MASK 0x00000001 1999 #define lpfc_reg_vfi_upd_WORD word1 2000 #define lpfc_reg_vfi_vp_SHIFT 28 2001 #define lpfc_reg_vfi_vp_MASK 0x00000001 2002 #define lpfc_reg_vfi_vp_WORD word1 2003 #define lpfc_reg_vfi_vfi_SHIFT 0 2004 #define lpfc_reg_vfi_vfi_MASK 0x0000FFFF 2005 #define lpfc_reg_vfi_vfi_WORD word1 2006 uint32_t word2; 2007 #define lpfc_reg_vfi_vpi_SHIFT 16 2008 #define lpfc_reg_vfi_vpi_MASK 0x0000FFFF 2009 #define lpfc_reg_vfi_vpi_WORD word2 2010 #define lpfc_reg_vfi_fcfi_SHIFT 0 2011 #define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF 2012 #define lpfc_reg_vfi_fcfi_WORD word2 2013 uint32_t wwn[2]; 2014 struct ulp_bde64 bde; 2015 uint32_t e_d_tov; 2016 uint32_t r_a_tov; 2017 uint32_t word10; 2018 #define lpfc_reg_vfi_nport_id_SHIFT 0 2019 #define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF 2020 #define lpfc_reg_vfi_nport_id_WORD word10 2021 }; 2022 2023 struct lpfc_mbx_init_vpi { 2024 uint32_t word1; 2025 #define lpfc_init_vpi_vfi_SHIFT 16 2026 #define lpfc_init_vpi_vfi_MASK 0x0000FFFF 2027 #define lpfc_init_vpi_vfi_WORD word1 2028 #define lpfc_init_vpi_vpi_SHIFT 0 2029 #define lpfc_init_vpi_vpi_MASK 0x0000FFFF 2030 #define lpfc_init_vpi_vpi_WORD word1 2031 }; 2032 2033 struct lpfc_mbx_read_vpi { 2034 uint32_t word1_rsvd; 2035 uint32_t word2; 2036 #define lpfc_mbx_read_vpi_vnportid_SHIFT 0 2037 #define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF 2038 #define lpfc_mbx_read_vpi_vnportid_WORD word2 2039 uint32_t word3_rsvd; 2040 uint32_t word4; 2041 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0 2042 #define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF 2043 #define lpfc_mbx_read_vpi_acq_alpa_WORD word4 2044 #define lpfc_mbx_read_vpi_pb_SHIFT 15 2045 #define lpfc_mbx_read_vpi_pb_MASK 0x00000001 2046 #define lpfc_mbx_read_vpi_pb_WORD word4 2047 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16 2048 #define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF 2049 #define lpfc_mbx_read_vpi_spec_alpa_WORD word4 2050 #define lpfc_mbx_read_vpi_ns_SHIFT 30 2051 #define lpfc_mbx_read_vpi_ns_MASK 0x00000001 2052 #define lpfc_mbx_read_vpi_ns_WORD word4 2053 #define lpfc_mbx_read_vpi_hl_SHIFT 31 2054 #define lpfc_mbx_read_vpi_hl_MASK 0x00000001 2055 #define lpfc_mbx_read_vpi_hl_WORD word4 2056 uint32_t word5_rsvd; 2057 uint32_t word6; 2058 #define lpfc_mbx_read_vpi_vpi_SHIFT 0 2059 #define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF 2060 #define lpfc_mbx_read_vpi_vpi_WORD word6 2061 uint32_t word7; 2062 #define lpfc_mbx_read_vpi_mac_0_SHIFT 0 2063 #define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF 2064 #define lpfc_mbx_read_vpi_mac_0_WORD word7 2065 #define lpfc_mbx_read_vpi_mac_1_SHIFT 8 2066 #define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF 2067 #define lpfc_mbx_read_vpi_mac_1_WORD word7 2068 #define lpfc_mbx_read_vpi_mac_2_SHIFT 16 2069 #define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF 2070 #define lpfc_mbx_read_vpi_mac_2_WORD word7 2071 #define lpfc_mbx_read_vpi_mac_3_SHIFT 24 2072 #define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF 2073 #define lpfc_mbx_read_vpi_mac_3_WORD word7 2074 uint32_t word8; 2075 #define lpfc_mbx_read_vpi_mac_4_SHIFT 0 2076 #define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF 2077 #define lpfc_mbx_read_vpi_mac_4_WORD word8 2078 #define lpfc_mbx_read_vpi_mac_5_SHIFT 8 2079 #define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF 2080 #define lpfc_mbx_read_vpi_mac_5_WORD word8 2081 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16 2082 #define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF 2083 #define lpfc_mbx_read_vpi_vlan_tag_WORD word8 2084 #define lpfc_mbx_read_vpi_vv_SHIFT 28 2085 #define lpfc_mbx_read_vpi_vv_MASK 0x0000001 2086 #define lpfc_mbx_read_vpi_vv_WORD word8 2087 }; 2088 2089 struct lpfc_mbx_unreg_vfi { 2090 uint32_t word1_rsvd; 2091 uint32_t word2; 2092 #define lpfc_unreg_vfi_vfi_SHIFT 0 2093 #define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF 2094 #define lpfc_unreg_vfi_vfi_WORD word2 2095 }; 2096 2097 struct lpfc_mbx_resume_rpi { 2098 uint32_t word1; 2099 #define lpfc_resume_rpi_index_SHIFT 0 2100 #define lpfc_resume_rpi_index_MASK 0x0000FFFF 2101 #define lpfc_resume_rpi_index_WORD word1 2102 #define lpfc_resume_rpi_ii_SHIFT 30 2103 #define lpfc_resume_rpi_ii_MASK 0x00000003 2104 #define lpfc_resume_rpi_ii_WORD word1 2105 #define RESUME_INDEX_RPI 0 2106 #define RESUME_INDEX_VPI 1 2107 #define RESUME_INDEX_VFI 2 2108 #define RESUME_INDEX_FCFI 3 2109 uint32_t event_tag; 2110 }; 2111 2112 #define REG_FCF_INVALID_QID 0xFFFF 2113 struct lpfc_mbx_reg_fcfi { 2114 uint32_t word1; 2115 #define lpfc_reg_fcfi_info_index_SHIFT 0 2116 #define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF 2117 #define lpfc_reg_fcfi_info_index_WORD word1 2118 #define lpfc_reg_fcfi_fcfi_SHIFT 16 2119 #define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF 2120 #define lpfc_reg_fcfi_fcfi_WORD word1 2121 uint32_t word2; 2122 #define lpfc_reg_fcfi_rq_id1_SHIFT 0 2123 #define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF 2124 #define lpfc_reg_fcfi_rq_id1_WORD word2 2125 #define lpfc_reg_fcfi_rq_id0_SHIFT 16 2126 #define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF 2127 #define lpfc_reg_fcfi_rq_id0_WORD word2 2128 uint32_t word3; 2129 #define lpfc_reg_fcfi_rq_id3_SHIFT 0 2130 #define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF 2131 #define lpfc_reg_fcfi_rq_id3_WORD word3 2132 #define lpfc_reg_fcfi_rq_id2_SHIFT 16 2133 #define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF 2134 #define lpfc_reg_fcfi_rq_id2_WORD word3 2135 uint32_t word4; 2136 #define lpfc_reg_fcfi_type_match0_SHIFT 24 2137 #define lpfc_reg_fcfi_type_match0_MASK 0x000000FF 2138 #define lpfc_reg_fcfi_type_match0_WORD word4 2139 #define lpfc_reg_fcfi_type_mask0_SHIFT 16 2140 #define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF 2141 #define lpfc_reg_fcfi_type_mask0_WORD word4 2142 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8 2143 #define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF 2144 #define lpfc_reg_fcfi_rctl_match0_WORD word4 2145 #define lpfc_reg_fcfi_rctl_mask0_SHIFT 0 2146 #define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF 2147 #define lpfc_reg_fcfi_rctl_mask0_WORD word4 2148 uint32_t word5; 2149 #define lpfc_reg_fcfi_type_match1_SHIFT 24 2150 #define lpfc_reg_fcfi_type_match1_MASK 0x000000FF 2151 #define lpfc_reg_fcfi_type_match1_WORD word5 2152 #define lpfc_reg_fcfi_type_mask1_SHIFT 16 2153 #define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF 2154 #define lpfc_reg_fcfi_type_mask1_WORD word5 2155 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8 2156 #define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF 2157 #define lpfc_reg_fcfi_rctl_match1_WORD word5 2158 #define lpfc_reg_fcfi_rctl_mask1_SHIFT 0 2159 #define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF 2160 #define lpfc_reg_fcfi_rctl_mask1_WORD word5 2161 uint32_t word6; 2162 #define lpfc_reg_fcfi_type_match2_SHIFT 24 2163 #define lpfc_reg_fcfi_type_match2_MASK 0x000000FF 2164 #define lpfc_reg_fcfi_type_match2_WORD word6 2165 #define lpfc_reg_fcfi_type_mask2_SHIFT 16 2166 #define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF 2167 #define lpfc_reg_fcfi_type_mask2_WORD word6 2168 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8 2169 #define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF 2170 #define lpfc_reg_fcfi_rctl_match2_WORD word6 2171 #define lpfc_reg_fcfi_rctl_mask2_SHIFT 0 2172 #define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF 2173 #define lpfc_reg_fcfi_rctl_mask2_WORD word6 2174 uint32_t word7; 2175 #define lpfc_reg_fcfi_type_match3_SHIFT 24 2176 #define lpfc_reg_fcfi_type_match3_MASK 0x000000FF 2177 #define lpfc_reg_fcfi_type_match3_WORD word7 2178 #define lpfc_reg_fcfi_type_mask3_SHIFT 16 2179 #define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF 2180 #define lpfc_reg_fcfi_type_mask3_WORD word7 2181 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8 2182 #define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF 2183 #define lpfc_reg_fcfi_rctl_match3_WORD word7 2184 #define lpfc_reg_fcfi_rctl_mask3_SHIFT 0 2185 #define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF 2186 #define lpfc_reg_fcfi_rctl_mask3_WORD word7 2187 uint32_t word8; 2188 #define lpfc_reg_fcfi_mam_SHIFT 13 2189 #define lpfc_reg_fcfi_mam_MASK 0x00000003 2190 #define lpfc_reg_fcfi_mam_WORD word8 2191 #define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */ 2192 #define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */ 2193 #define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */ 2194 #define lpfc_reg_fcfi_vv_SHIFT 12 2195 #define lpfc_reg_fcfi_vv_MASK 0x00000001 2196 #define lpfc_reg_fcfi_vv_WORD word8 2197 #define lpfc_reg_fcfi_vlan_tag_SHIFT 0 2198 #define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF 2199 #define lpfc_reg_fcfi_vlan_tag_WORD word8 2200 }; 2201 2202 struct lpfc_mbx_unreg_fcfi { 2203 uint32_t word1_rsv; 2204 uint32_t word2; 2205 #define lpfc_unreg_fcfi_SHIFT 0 2206 #define lpfc_unreg_fcfi_MASK 0x0000FFFF 2207 #define lpfc_unreg_fcfi_WORD word2 2208 }; 2209 2210 struct lpfc_mbx_read_rev { 2211 uint32_t word1; 2212 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16 2213 #define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F 2214 #define lpfc_mbx_rd_rev_sli_lvl_WORD word1 2215 #define lpfc_mbx_rd_rev_fcoe_SHIFT 20 2216 #define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001 2217 #define lpfc_mbx_rd_rev_fcoe_WORD word1 2218 #define lpfc_mbx_rd_rev_cee_ver_SHIFT 21 2219 #define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003 2220 #define lpfc_mbx_rd_rev_cee_ver_WORD word1 2221 #define LPFC_PREDCBX_CEE_MODE 0 2222 #define LPFC_DCBX_CEE_MODE 1 2223 #define lpfc_mbx_rd_rev_vpd_SHIFT 29 2224 #define lpfc_mbx_rd_rev_vpd_MASK 0x00000001 2225 #define lpfc_mbx_rd_rev_vpd_WORD word1 2226 uint32_t first_hw_rev; 2227 uint32_t second_hw_rev; 2228 uint32_t word4_rsvd; 2229 uint32_t third_hw_rev; 2230 uint32_t word6; 2231 #define lpfc_mbx_rd_rev_fcph_low_SHIFT 0 2232 #define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF 2233 #define lpfc_mbx_rd_rev_fcph_low_WORD word6 2234 #define lpfc_mbx_rd_rev_fcph_high_SHIFT 8 2235 #define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF 2236 #define lpfc_mbx_rd_rev_fcph_high_WORD word6 2237 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16 2238 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF 2239 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6 2240 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24 2241 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF 2242 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6 2243 uint32_t word7_rsvd; 2244 uint32_t fw_id_rev; 2245 uint8_t fw_name[16]; 2246 uint32_t ulp_fw_id_rev; 2247 uint8_t ulp_fw_name[16]; 2248 uint32_t word18_47_rsvd[30]; 2249 uint32_t word48; 2250 #define lpfc_mbx_rd_rev_avail_len_SHIFT 0 2251 #define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF 2252 #define lpfc_mbx_rd_rev_avail_len_WORD word48 2253 uint32_t vpd_paddr_low; 2254 uint32_t vpd_paddr_high; 2255 uint32_t avail_vpd_len; 2256 uint32_t rsvd_52_63[12]; 2257 }; 2258 2259 struct lpfc_mbx_read_config { 2260 uint32_t word1; 2261 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31 2262 #define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001 2263 #define lpfc_mbx_rd_conf_extnts_inuse_WORD word1 2264 uint32_t word2; 2265 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0 2266 #define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F 2267 #define lpfc_mbx_rd_conf_lnk_numb_WORD word2 2268 #define lpfc_mbx_rd_conf_lnk_type_SHIFT 6 2269 #define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003 2270 #define lpfc_mbx_rd_conf_lnk_type_WORD word2 2271 #define LPFC_LNK_TYPE_GE 0 2272 #define LPFC_LNK_TYPE_FC 1 2273 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8 2274 #define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001 2275 #define lpfc_mbx_rd_conf_lnk_ldv_WORD word2 2276 #define lpfc_mbx_rd_conf_topology_SHIFT 24 2277 #define lpfc_mbx_rd_conf_topology_MASK 0x000000FF 2278 #define lpfc_mbx_rd_conf_topology_WORD word2 2279 uint32_t rsvd_3; 2280 uint32_t word4; 2281 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0 2282 #define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF 2283 #define lpfc_mbx_rd_conf_e_d_tov_WORD word4 2284 uint32_t rsvd_5; 2285 uint32_t word6; 2286 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0 2287 #define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF 2288 #define lpfc_mbx_rd_conf_r_a_tov_WORD word6 2289 uint32_t rsvd_7; 2290 uint32_t rsvd_8; 2291 uint32_t word9; 2292 #define lpfc_mbx_rd_conf_lmt_SHIFT 0 2293 #define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF 2294 #define lpfc_mbx_rd_conf_lmt_WORD word9 2295 uint32_t rsvd_10; 2296 uint32_t rsvd_11; 2297 uint32_t word12; 2298 #define lpfc_mbx_rd_conf_xri_base_SHIFT 0 2299 #define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF 2300 #define lpfc_mbx_rd_conf_xri_base_WORD word12 2301 #define lpfc_mbx_rd_conf_xri_count_SHIFT 16 2302 #define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF 2303 #define lpfc_mbx_rd_conf_xri_count_WORD word12 2304 uint32_t word13; 2305 #define lpfc_mbx_rd_conf_rpi_base_SHIFT 0 2306 #define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF 2307 #define lpfc_mbx_rd_conf_rpi_base_WORD word13 2308 #define lpfc_mbx_rd_conf_rpi_count_SHIFT 16 2309 #define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF 2310 #define lpfc_mbx_rd_conf_rpi_count_WORD word13 2311 uint32_t word14; 2312 #define lpfc_mbx_rd_conf_vpi_base_SHIFT 0 2313 #define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF 2314 #define lpfc_mbx_rd_conf_vpi_base_WORD word14 2315 #define lpfc_mbx_rd_conf_vpi_count_SHIFT 16 2316 #define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF 2317 #define lpfc_mbx_rd_conf_vpi_count_WORD word14 2318 uint32_t word15; 2319 #define lpfc_mbx_rd_conf_vfi_base_SHIFT 0 2320 #define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF 2321 #define lpfc_mbx_rd_conf_vfi_base_WORD word15 2322 #define lpfc_mbx_rd_conf_vfi_count_SHIFT 16 2323 #define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF 2324 #define lpfc_mbx_rd_conf_vfi_count_WORD word15 2325 uint32_t word16; 2326 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16 2327 #define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF 2328 #define lpfc_mbx_rd_conf_fcfi_count_WORD word16 2329 uint32_t word17; 2330 #define lpfc_mbx_rd_conf_rq_count_SHIFT 0 2331 #define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF 2332 #define lpfc_mbx_rd_conf_rq_count_WORD word17 2333 #define lpfc_mbx_rd_conf_eq_count_SHIFT 16 2334 #define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF 2335 #define lpfc_mbx_rd_conf_eq_count_WORD word17 2336 uint32_t word18; 2337 #define lpfc_mbx_rd_conf_wq_count_SHIFT 0 2338 #define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF 2339 #define lpfc_mbx_rd_conf_wq_count_WORD word18 2340 #define lpfc_mbx_rd_conf_cq_count_SHIFT 16 2341 #define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF 2342 #define lpfc_mbx_rd_conf_cq_count_WORD word18 2343 }; 2344 2345 struct lpfc_mbx_request_features { 2346 uint32_t word1; 2347 #define lpfc_mbx_rq_ftr_qry_SHIFT 0 2348 #define lpfc_mbx_rq_ftr_qry_MASK 0x00000001 2349 #define lpfc_mbx_rq_ftr_qry_WORD word1 2350 uint32_t word2; 2351 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0 2352 #define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001 2353 #define lpfc_mbx_rq_ftr_rq_iaab_WORD word2 2354 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1 2355 #define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001 2356 #define lpfc_mbx_rq_ftr_rq_npiv_WORD word2 2357 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2 2358 #define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001 2359 #define lpfc_mbx_rq_ftr_rq_dif_WORD word2 2360 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3 2361 #define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001 2362 #define lpfc_mbx_rq_ftr_rq_vf_WORD word2 2363 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4 2364 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001 2365 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2 2366 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5 2367 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001 2368 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2 2369 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6 2370 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001 2371 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2 2372 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7 2373 #define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001 2374 #define lpfc_mbx_rq_ftr_rq_ifip_WORD word2 2375 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT 11 2376 #define lpfc_mbx_rq_ftr_rq_perfh_MASK 0x00000001 2377 #define lpfc_mbx_rq_ftr_rq_perfh_WORD word2 2378 uint32_t word3; 2379 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0 2380 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001 2381 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3 2382 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1 2383 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001 2384 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3 2385 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2 2386 #define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001 2387 #define lpfc_mbx_rq_ftr_rsp_dif_WORD word3 2388 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3 2389 #define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001 2390 #define lpfc_mbx_rq_ftr_rsp_vf_WORD word3 2391 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4 2392 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001 2393 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3 2394 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5 2395 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001 2396 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3 2397 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6 2398 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001 2399 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3 2400 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7 2401 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001 2402 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3 2403 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT 11 2404 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK 0x00000001 2405 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD word3 2406 }; 2407 2408 struct lpfc_mbx_supp_pages { 2409 uint32_t word1; 2410 #define qs_SHIFT 0 2411 #define qs_MASK 0x00000001 2412 #define qs_WORD word1 2413 #define wr_SHIFT 1 2414 #define wr_MASK 0x00000001 2415 #define wr_WORD word1 2416 #define pf_SHIFT 8 2417 #define pf_MASK 0x000000ff 2418 #define pf_WORD word1 2419 #define cpn_SHIFT 16 2420 #define cpn_MASK 0x000000ff 2421 #define cpn_WORD word1 2422 uint32_t word2; 2423 #define list_offset_SHIFT 0 2424 #define list_offset_MASK 0x000000ff 2425 #define list_offset_WORD word2 2426 #define next_offset_SHIFT 8 2427 #define next_offset_MASK 0x000000ff 2428 #define next_offset_WORD word2 2429 #define elem_cnt_SHIFT 16 2430 #define elem_cnt_MASK 0x000000ff 2431 #define elem_cnt_WORD word2 2432 uint32_t word3; 2433 #define pn_0_SHIFT 24 2434 #define pn_0_MASK 0x000000ff 2435 #define pn_0_WORD word3 2436 #define pn_1_SHIFT 16 2437 #define pn_1_MASK 0x000000ff 2438 #define pn_1_WORD word3 2439 #define pn_2_SHIFT 8 2440 #define pn_2_MASK 0x000000ff 2441 #define pn_2_WORD word3 2442 #define pn_3_SHIFT 0 2443 #define pn_3_MASK 0x000000ff 2444 #define pn_3_WORD word3 2445 uint32_t word4; 2446 #define pn_4_SHIFT 24 2447 #define pn_4_MASK 0x000000ff 2448 #define pn_4_WORD word4 2449 #define pn_5_SHIFT 16 2450 #define pn_5_MASK 0x000000ff 2451 #define pn_5_WORD word4 2452 #define pn_6_SHIFT 8 2453 #define pn_6_MASK 0x000000ff 2454 #define pn_6_WORD word4 2455 #define pn_7_SHIFT 0 2456 #define pn_7_MASK 0x000000ff 2457 #define pn_7_WORD word4 2458 uint32_t rsvd[27]; 2459 #define LPFC_SUPP_PAGES 0 2460 #define LPFC_BLOCK_GUARD_PROFILES 1 2461 #define LPFC_SLI4_PARAMETERS 2 2462 }; 2463 2464 struct lpfc_mbx_memory_dump_type3 { 2465 uint32_t word1; 2466 #define lpfc_mbx_memory_dump_type3_type_SHIFT 0 2467 #define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f 2468 #define lpfc_mbx_memory_dump_type3_type_WORD word1 2469 #define lpfc_mbx_memory_dump_type3_link_SHIFT 24 2470 #define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff 2471 #define lpfc_mbx_memory_dump_type3_link_WORD word1 2472 uint32_t word2; 2473 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0 2474 #define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff 2475 #define lpfc_mbx_memory_dump_type3_page_no_WORD word2 2476 #define lpfc_mbx_memory_dump_type3_offset_SHIFT 16 2477 #define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff 2478 #define lpfc_mbx_memory_dump_type3_offset_WORD word2 2479 uint32_t word3; 2480 #define lpfc_mbx_memory_dump_type3_length_SHIFT 0 2481 #define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff 2482 #define lpfc_mbx_memory_dump_type3_length_WORD word3 2483 uint32_t addr_lo; 2484 uint32_t addr_hi; 2485 uint32_t return_len; 2486 }; 2487 2488 #define DMP_PAGE_A0 0xa0 2489 #define DMP_PAGE_A2 0xa2 2490 #define DMP_SFF_PAGE_A0_SIZE 256 2491 #define DMP_SFF_PAGE_A2_SIZE 256 2492 2493 #define SFP_WAVELENGTH_LC1310 1310 2494 #define SFP_WAVELENGTH_LL1550 1550 2495 2496 2497 /* 2498 * * SFF-8472 TABLE 3.4 2499 * */ 2500 #define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */ 2501 #define SFF_PG0_CONNECTOR_SC 0x01 /* SC */ 2502 #define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */ 2503 #define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */ 2504 #define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */ 2505 #define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */ 2506 #define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */ 2507 #define SFF_PG0_CONNECTOR_LC 0x07 /* LC */ 2508 #define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */ 2509 #define SFF_PG0_CONNECTOR_MU 0x09 /* MU */ 2510 #define SFF_PG0_CONNECTOR_SF 0x0A /* SG */ 2511 #define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */ 2512 #define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */ 2513 #define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */ 2514 #define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */ 2515 #define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */ 2516 2517 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */ 2518 2519 #define SSF_IDENTIFIER 0 2520 #define SSF_EXT_IDENTIFIER 1 2521 #define SSF_CONNECTOR 2 2522 #define SSF_TRANSCEIVER_CODE_B0 3 2523 #define SSF_TRANSCEIVER_CODE_B1 4 2524 #define SSF_TRANSCEIVER_CODE_B2 5 2525 #define SSF_TRANSCEIVER_CODE_B3 6 2526 #define SSF_TRANSCEIVER_CODE_B4 7 2527 #define SSF_TRANSCEIVER_CODE_B5 8 2528 #define SSF_TRANSCEIVER_CODE_B6 9 2529 #define SSF_TRANSCEIVER_CODE_B7 10 2530 #define SSF_ENCODING 11 2531 #define SSF_BR_NOMINAL 12 2532 #define SSF_RATE_IDENTIFIER 13 2533 #define SSF_LENGTH_9UM_KM 14 2534 #define SSF_LENGTH_9UM 15 2535 #define SSF_LENGTH_50UM_OM2 16 2536 #define SSF_LENGTH_62UM_OM1 17 2537 #define SFF_LENGTH_COPPER 18 2538 #define SSF_LENGTH_50UM_OM3 19 2539 #define SSF_VENDOR_NAME 20 2540 #define SSF_VENDOR_OUI 36 2541 #define SSF_VENDOR_PN 40 2542 #define SSF_VENDOR_REV 56 2543 #define SSF_WAVELENGTH_B1 60 2544 #define SSF_WAVELENGTH_B0 61 2545 #define SSF_CC_BASE 63 2546 #define SSF_OPTIONS_B1 64 2547 #define SSF_OPTIONS_B0 65 2548 #define SSF_BR_MAX 66 2549 #define SSF_BR_MIN 67 2550 #define SSF_VENDOR_SN 68 2551 #define SSF_DATE_CODE 84 2552 #define SSF_MONITORING_TYPEDIAGNOSTIC 92 2553 #define SSF_ENHANCED_OPTIONS 93 2554 #define SFF_8472_COMPLIANCE 94 2555 #define SSF_CC_EXT 95 2556 #define SSF_A0_VENDOR_SPECIFIC 96 2557 2558 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */ 2559 2560 #define SSF_TEMP_HIGH_ALARM 0 2561 #define SSF_TEMP_LOW_ALARM 2 2562 #define SSF_TEMP_HIGH_WARNING 4 2563 #define SSF_TEMP_LOW_WARNING 6 2564 #define SSF_VOLTAGE_HIGH_ALARM 8 2565 #define SSF_VOLTAGE_LOW_ALARM 10 2566 #define SSF_VOLTAGE_HIGH_WARNING 12 2567 #define SSF_VOLTAGE_LOW_WARNING 14 2568 #define SSF_BIAS_HIGH_ALARM 16 2569 #define SSF_BIAS_LOW_ALARM 18 2570 #define SSF_BIAS_HIGH_WARNING 20 2571 #define SSF_BIAS_LOW_WARNING 22 2572 #define SSF_TXPOWER_HIGH_ALARM 24 2573 #define SSF_TXPOWER_LOW_ALARM 26 2574 #define SSF_TXPOWER_HIGH_WARNING 28 2575 #define SSF_TXPOWER_LOW_WARNING 30 2576 #define SSF_RXPOWER_HIGH_ALARM 32 2577 #define SSF_RXPOWER_LOW_ALARM 34 2578 #define SSF_RXPOWER_HIGH_WARNING 36 2579 #define SSF_RXPOWER_LOW_WARNING 38 2580 #define SSF_EXT_CAL_CONSTANTS 56 2581 #define SSF_CC_DMI 95 2582 #define SFF_TEMPERATURE_B1 96 2583 #define SFF_TEMPERATURE_B0 97 2584 #define SFF_VCC_B1 98 2585 #define SFF_VCC_B0 99 2586 #define SFF_TX_BIAS_CURRENT_B1 100 2587 #define SFF_TX_BIAS_CURRENT_B0 101 2588 #define SFF_TXPOWER_B1 102 2589 #define SFF_TXPOWER_B0 103 2590 #define SFF_RXPOWER_B1 104 2591 #define SFF_RXPOWER_B0 105 2592 #define SSF_STATUS_CONTROL 110 2593 #define SSF_ALARM_FLAGS_B1 112 2594 #define SSF_ALARM_FLAGS_B0 113 2595 #define SSF_WARNING_FLAGS_B1 116 2596 #define SSF_WARNING_FLAGS_B0 117 2597 #define SSF_EXT_TATUS_CONTROL_B1 118 2598 #define SSF_EXT_TATUS_CONTROL_B0 119 2599 #define SSF_A2_VENDOR_SPECIFIC 120 2600 #define SSF_USER_EEPROM 128 2601 #define SSF_VENDOR_CONTROL 148 2602 2603 2604 /* 2605 * Tranceiver codes Fibre Channel SFF-8472 2606 * Table 3.5. 2607 */ 2608 2609 struct sff_trasnceiver_codes_byte0 { 2610 uint8_t inifiband:4; 2611 uint8_t teng_ethernet:4; 2612 }; 2613 2614 struct sff_trasnceiver_codes_byte1 { 2615 uint8_t sonet:6; 2616 uint8_t escon:2; 2617 }; 2618 2619 struct sff_trasnceiver_codes_byte2 { 2620 uint8_t soNet:8; 2621 }; 2622 2623 struct sff_trasnceiver_codes_byte3 { 2624 uint8_t ethernet:8; 2625 }; 2626 2627 struct sff_trasnceiver_codes_byte4 { 2628 uint8_t fc_el_lo:1; 2629 uint8_t fc_lw_laser:1; 2630 uint8_t fc_sw_laser:1; 2631 uint8_t fc_md_distance:1; 2632 uint8_t fc_lg_distance:1; 2633 uint8_t fc_int_distance:1; 2634 uint8_t fc_short_distance:1; 2635 uint8_t fc_vld_distance:1; 2636 }; 2637 2638 struct sff_trasnceiver_codes_byte5 { 2639 uint8_t reserved1:1; 2640 uint8_t reserved2:1; 2641 uint8_t fc_sfp_active:1; /* Active cable */ 2642 uint8_t fc_sfp_passive:1; /* Passive cable */ 2643 uint8_t fc_lw_laser:1; /* Longwave laser */ 2644 uint8_t fc_sw_laser_sl:1; 2645 uint8_t fc_sw_laser_sn:1; 2646 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */ 2647 }; 2648 2649 struct sff_trasnceiver_codes_byte6 { 2650 uint8_t fc_tm_sm:1; /* Single Mode */ 2651 uint8_t reserved:1; 2652 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */ 2653 uint8_t fc_tm_tv:1; /* Video Coax (TV) */ 2654 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */ 2655 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */ 2656 uint8_t fc_tm_tw:1; /* Twin Axial Pair */ 2657 }; 2658 2659 struct sff_trasnceiver_codes_byte7 { 2660 uint8_t fc_sp_100MB:1; /* 100 MB/sec */ 2661 uint8_t reserve:1; 2662 uint8_t fc_sp_200mb:1; /* 200 MB/sec */ 2663 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */ 2664 uint8_t fc_sp_400MB:1; /* 400 MB/sec */ 2665 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */ 2666 uint8_t fc_sp_800MB:1; /* 800 MB/sec */ 2667 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */ 2668 }; 2669 2670 /* User writable non-volatile memory, SFF-8472 Table 3.20 */ 2671 struct user_eeprom { 2672 uint8_t vendor_name[16]; 2673 uint8_t vendor_oui[3]; 2674 uint8_t vendor_pn[816]; 2675 uint8_t vendor_rev[4]; 2676 uint8_t vendor_sn[16]; 2677 uint8_t datecode[6]; 2678 uint8_t lot_code[2]; 2679 uint8_t reserved191[57]; 2680 }; 2681 2682 struct lpfc_mbx_pc_sli4_params { 2683 uint32_t word1; 2684 #define qs_SHIFT 0 2685 #define qs_MASK 0x00000001 2686 #define qs_WORD word1 2687 #define wr_SHIFT 1 2688 #define wr_MASK 0x00000001 2689 #define wr_WORD word1 2690 #define pf_SHIFT 8 2691 #define pf_MASK 0x000000ff 2692 #define pf_WORD word1 2693 #define cpn_SHIFT 16 2694 #define cpn_MASK 0x000000ff 2695 #define cpn_WORD word1 2696 uint32_t word2; 2697 #define if_type_SHIFT 0 2698 #define if_type_MASK 0x00000007 2699 #define if_type_WORD word2 2700 #define sli_rev_SHIFT 4 2701 #define sli_rev_MASK 0x0000000f 2702 #define sli_rev_WORD word2 2703 #define sli_family_SHIFT 8 2704 #define sli_family_MASK 0x000000ff 2705 #define sli_family_WORD word2 2706 #define featurelevel_1_SHIFT 16 2707 #define featurelevel_1_MASK 0x000000ff 2708 #define featurelevel_1_WORD word2 2709 #define featurelevel_2_SHIFT 24 2710 #define featurelevel_2_MASK 0x0000001f 2711 #define featurelevel_2_WORD word2 2712 uint32_t word3; 2713 #define fcoe_SHIFT 0 2714 #define fcoe_MASK 0x00000001 2715 #define fcoe_WORD word3 2716 #define fc_SHIFT 1 2717 #define fc_MASK 0x00000001 2718 #define fc_WORD word3 2719 #define nic_SHIFT 2 2720 #define nic_MASK 0x00000001 2721 #define nic_WORD word3 2722 #define iscsi_SHIFT 3 2723 #define iscsi_MASK 0x00000001 2724 #define iscsi_WORD word3 2725 #define rdma_SHIFT 4 2726 #define rdma_MASK 0x00000001 2727 #define rdma_WORD word3 2728 uint32_t sge_supp_len; 2729 #define SLI4_PAGE_SIZE 4096 2730 uint32_t word5; 2731 #define if_page_sz_SHIFT 0 2732 #define if_page_sz_MASK 0x0000ffff 2733 #define if_page_sz_WORD word5 2734 #define loopbk_scope_SHIFT 24 2735 #define loopbk_scope_MASK 0x0000000f 2736 #define loopbk_scope_WORD word5 2737 #define rq_db_window_SHIFT 28 2738 #define rq_db_window_MASK 0x0000000f 2739 #define rq_db_window_WORD word5 2740 uint32_t word6; 2741 #define eq_pages_SHIFT 0 2742 #define eq_pages_MASK 0x0000000f 2743 #define eq_pages_WORD word6 2744 #define eqe_size_SHIFT 8 2745 #define eqe_size_MASK 0x000000ff 2746 #define eqe_size_WORD word6 2747 uint32_t word7; 2748 #define cq_pages_SHIFT 0 2749 #define cq_pages_MASK 0x0000000f 2750 #define cq_pages_WORD word7 2751 #define cqe_size_SHIFT 8 2752 #define cqe_size_MASK 0x000000ff 2753 #define cqe_size_WORD word7 2754 uint32_t word8; 2755 #define mq_pages_SHIFT 0 2756 #define mq_pages_MASK 0x0000000f 2757 #define mq_pages_WORD word8 2758 #define mqe_size_SHIFT 8 2759 #define mqe_size_MASK 0x000000ff 2760 #define mqe_size_WORD word8 2761 #define mq_elem_cnt_SHIFT 16 2762 #define mq_elem_cnt_MASK 0x000000ff 2763 #define mq_elem_cnt_WORD word8 2764 uint32_t word9; 2765 #define wq_pages_SHIFT 0 2766 #define wq_pages_MASK 0x0000ffff 2767 #define wq_pages_WORD word9 2768 #define wqe_size_SHIFT 8 2769 #define wqe_size_MASK 0x000000ff 2770 #define wqe_size_WORD word9 2771 uint32_t word10; 2772 #define rq_pages_SHIFT 0 2773 #define rq_pages_MASK 0x0000ffff 2774 #define rq_pages_WORD word10 2775 #define rqe_size_SHIFT 8 2776 #define rqe_size_MASK 0x000000ff 2777 #define rqe_size_WORD word10 2778 uint32_t word11; 2779 #define hdr_pages_SHIFT 0 2780 #define hdr_pages_MASK 0x0000000f 2781 #define hdr_pages_WORD word11 2782 #define hdr_size_SHIFT 8 2783 #define hdr_size_MASK 0x0000000f 2784 #define hdr_size_WORD word11 2785 #define hdr_pp_align_SHIFT 16 2786 #define hdr_pp_align_MASK 0x0000ffff 2787 #define hdr_pp_align_WORD word11 2788 uint32_t word12; 2789 #define sgl_pages_SHIFT 0 2790 #define sgl_pages_MASK 0x0000000f 2791 #define sgl_pages_WORD word12 2792 #define sgl_pp_align_SHIFT 16 2793 #define sgl_pp_align_MASK 0x0000ffff 2794 #define sgl_pp_align_WORD word12 2795 uint32_t rsvd_13_63[51]; 2796 }; 2797 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \ 2798 &(~((SLI4_PAGE_SIZE)-1))) 2799 2800 struct lpfc_sli4_parameters { 2801 uint32_t word0; 2802 #define cfg_prot_type_SHIFT 0 2803 #define cfg_prot_type_MASK 0x000000FF 2804 #define cfg_prot_type_WORD word0 2805 uint32_t word1; 2806 #define cfg_ft_SHIFT 0 2807 #define cfg_ft_MASK 0x00000001 2808 #define cfg_ft_WORD word1 2809 #define cfg_sli_rev_SHIFT 4 2810 #define cfg_sli_rev_MASK 0x0000000f 2811 #define cfg_sli_rev_WORD word1 2812 #define cfg_sli_family_SHIFT 8 2813 #define cfg_sli_family_MASK 0x0000000f 2814 #define cfg_sli_family_WORD word1 2815 #define cfg_if_type_SHIFT 12 2816 #define cfg_if_type_MASK 0x0000000f 2817 #define cfg_if_type_WORD word1 2818 #define cfg_sli_hint_1_SHIFT 16 2819 #define cfg_sli_hint_1_MASK 0x000000ff 2820 #define cfg_sli_hint_1_WORD word1 2821 #define cfg_sli_hint_2_SHIFT 24 2822 #define cfg_sli_hint_2_MASK 0x0000001f 2823 #define cfg_sli_hint_2_WORD word1 2824 uint32_t word2; 2825 uint32_t word3; 2826 uint32_t word4; 2827 #define cfg_cqv_SHIFT 14 2828 #define cfg_cqv_MASK 0x00000003 2829 #define cfg_cqv_WORD word4 2830 uint32_t word5; 2831 uint32_t word6; 2832 #define cfg_mqv_SHIFT 14 2833 #define cfg_mqv_MASK 0x00000003 2834 #define cfg_mqv_WORD word6 2835 uint32_t word7; 2836 uint32_t word8; 2837 #define cfg_wqsize_SHIFT 8 2838 #define cfg_wqsize_MASK 0x0000000f 2839 #define cfg_wqsize_WORD word8 2840 #define cfg_wqv_SHIFT 14 2841 #define cfg_wqv_MASK 0x00000003 2842 #define cfg_wqv_WORD word8 2843 uint32_t word9; 2844 uint32_t word10; 2845 #define cfg_rqv_SHIFT 14 2846 #define cfg_rqv_MASK 0x00000003 2847 #define cfg_rqv_WORD word10 2848 uint32_t word11; 2849 #define cfg_rq_db_window_SHIFT 28 2850 #define cfg_rq_db_window_MASK 0x0000000f 2851 #define cfg_rq_db_window_WORD word11 2852 uint32_t word12; 2853 #define cfg_fcoe_SHIFT 0 2854 #define cfg_fcoe_MASK 0x00000001 2855 #define cfg_fcoe_WORD word12 2856 #define cfg_ext_SHIFT 1 2857 #define cfg_ext_MASK 0x00000001 2858 #define cfg_ext_WORD word12 2859 #define cfg_hdrr_SHIFT 2 2860 #define cfg_hdrr_MASK 0x00000001 2861 #define cfg_hdrr_WORD word12 2862 #define cfg_phwq_SHIFT 15 2863 #define cfg_phwq_MASK 0x00000001 2864 #define cfg_phwq_WORD word12 2865 #define cfg_oas_SHIFT 25 2866 #define cfg_oas_MASK 0x00000001 2867 #define cfg_oas_WORD word12 2868 #define cfg_loopbk_scope_SHIFT 28 2869 #define cfg_loopbk_scope_MASK 0x0000000f 2870 #define cfg_loopbk_scope_WORD word12 2871 uint32_t sge_supp_len; 2872 uint32_t word14; 2873 #define cfg_sgl_page_cnt_SHIFT 0 2874 #define cfg_sgl_page_cnt_MASK 0x0000000f 2875 #define cfg_sgl_page_cnt_WORD word14 2876 #define cfg_sgl_page_size_SHIFT 8 2877 #define cfg_sgl_page_size_MASK 0x000000ff 2878 #define cfg_sgl_page_size_WORD word14 2879 #define cfg_sgl_pp_align_SHIFT 16 2880 #define cfg_sgl_pp_align_MASK 0x000000ff 2881 #define cfg_sgl_pp_align_WORD word14 2882 uint32_t word15; 2883 uint32_t word16; 2884 uint32_t word17; 2885 uint32_t word18; 2886 uint32_t word19; 2887 #define cfg_ext_embed_cb_SHIFT 0 2888 #define cfg_ext_embed_cb_MASK 0x00000001 2889 #define cfg_ext_embed_cb_WORD word19 2890 }; 2891 2892 struct lpfc_mbx_get_sli4_parameters { 2893 struct mbox_header header; 2894 struct lpfc_sli4_parameters sli4_parameters; 2895 }; 2896 2897 struct lpfc_rscr_desc_generic { 2898 #define LPFC_RSRC_DESC_WSIZE 22 2899 uint32_t desc[LPFC_RSRC_DESC_WSIZE]; 2900 }; 2901 2902 struct lpfc_rsrc_desc_pcie { 2903 uint32_t word0; 2904 #define lpfc_rsrc_desc_pcie_type_SHIFT 0 2905 #define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff 2906 #define lpfc_rsrc_desc_pcie_type_WORD word0 2907 #define LPFC_RSRC_DESC_TYPE_PCIE 0x40 2908 #define lpfc_rsrc_desc_pcie_length_SHIFT 8 2909 #define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff 2910 #define lpfc_rsrc_desc_pcie_length_WORD word0 2911 uint32_t word1; 2912 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0 2913 #define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff 2914 #define lpfc_rsrc_desc_pcie_pfnum_WORD word1 2915 uint32_t reserved; 2916 uint32_t word3; 2917 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0 2918 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff 2919 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3 2920 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8 2921 #define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff 2922 #define lpfc_rsrc_desc_pcie_pf_sta_WORD word3 2923 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16 2924 #define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff 2925 #define lpfc_rsrc_desc_pcie_pf_type_WORD word3 2926 uint32_t word4; 2927 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0 2928 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff 2929 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4 2930 }; 2931 2932 struct lpfc_rsrc_desc_fcfcoe { 2933 uint32_t word0; 2934 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0 2935 #define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff 2936 #define lpfc_rsrc_desc_fcfcoe_type_WORD word0 2937 #define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43 2938 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8 2939 #define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff 2940 #define lpfc_rsrc_desc_fcfcoe_length_WORD word0 2941 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0 2942 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72 2943 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88 2944 uint32_t word1; 2945 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0 2946 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff 2947 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1 2948 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16 2949 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff 2950 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1 2951 uint32_t word2; 2952 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0 2953 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff 2954 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2 2955 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16 2956 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff 2957 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2 2958 uint32_t word3; 2959 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0 2960 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff 2961 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3 2962 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16 2963 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff 2964 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3 2965 uint32_t word4; 2966 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0 2967 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff 2968 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4 2969 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16 2970 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff 2971 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4 2972 uint32_t word5; 2973 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0 2974 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff 2975 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5 2976 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16 2977 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff 2978 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5 2979 uint32_t word6; 2980 uint32_t word7; 2981 uint32_t word8; 2982 uint32_t word9; 2983 uint32_t word10; 2984 uint32_t word11; 2985 uint32_t word12; 2986 uint32_t word13; 2987 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0 2988 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f 2989 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13 2990 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6 2991 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003 2992 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13 2993 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8 2994 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001 2995 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13 2996 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9 2997 #define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001 2998 #define lpfc_rsrc_desc_fcfcoe_lld_WORD word13 2999 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16 3000 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff 3001 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13 3002 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */ 3003 uint32_t bw_min; 3004 uint32_t bw_max; 3005 uint32_t iops_min; 3006 uint32_t iops_max; 3007 uint32_t reserved[4]; 3008 }; 3009 3010 struct lpfc_func_cfg { 3011 #define LPFC_RSRC_DESC_MAX_NUM 2 3012 uint32_t rsrc_desc_count; 3013 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3014 }; 3015 3016 struct lpfc_mbx_get_func_cfg { 3017 struct mbox_header header; 3018 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3019 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3020 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3021 struct lpfc_func_cfg func_cfg; 3022 }; 3023 3024 struct lpfc_prof_cfg { 3025 #define LPFC_RSRC_DESC_MAX_NUM 2 3026 uint32_t rsrc_desc_count; 3027 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM]; 3028 }; 3029 3030 struct lpfc_mbx_get_prof_cfg { 3031 struct mbox_header header; 3032 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0 3033 #define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1 3034 #define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2 3035 union { 3036 struct { 3037 uint32_t word10; 3038 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0 3039 #define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff 3040 #define lpfc_mbx_get_prof_cfg_prof_id_WORD word10 3041 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8 3042 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003 3043 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10 3044 } request; 3045 struct { 3046 struct lpfc_prof_cfg prof_cfg; 3047 } response; 3048 } u; 3049 }; 3050 3051 struct lpfc_controller_attribute { 3052 uint32_t version_string[8]; 3053 uint32_t manufacturer_name[8]; 3054 uint32_t supported_modes; 3055 uint32_t word17; 3056 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT 0 3057 #define lpfc_cntl_attr_eprom_ver_lo_MASK 0x000000ff 3058 #define lpfc_cntl_attr_eprom_ver_lo_WORD word17 3059 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT 8 3060 #define lpfc_cntl_attr_eprom_ver_hi_MASK 0x000000ff 3061 #define lpfc_cntl_attr_eprom_ver_hi_WORD word17 3062 uint32_t mbx_da_struct_ver; 3063 uint32_t ep_fw_da_struct_ver; 3064 uint32_t ncsi_ver_str[3]; 3065 uint32_t dflt_ext_timeout; 3066 uint32_t model_number[8]; 3067 uint32_t description[16]; 3068 uint32_t serial_number[8]; 3069 uint32_t ip_ver_str[8]; 3070 uint32_t fw_ver_str[8]; 3071 uint32_t bios_ver_str[8]; 3072 uint32_t redboot_ver_str[8]; 3073 uint32_t driver_ver_str[8]; 3074 uint32_t flash_fw_ver_str[8]; 3075 uint32_t functionality; 3076 uint32_t word105; 3077 #define lpfc_cntl_attr_max_cbd_len_SHIFT 0 3078 #define lpfc_cntl_attr_max_cbd_len_MASK 0x0000ffff 3079 #define lpfc_cntl_attr_max_cbd_len_WORD word105 3080 #define lpfc_cntl_attr_asic_rev_SHIFT 16 3081 #define lpfc_cntl_attr_asic_rev_MASK 0x000000ff 3082 #define lpfc_cntl_attr_asic_rev_WORD word105 3083 #define lpfc_cntl_attr_gen_guid0_SHIFT 24 3084 #define lpfc_cntl_attr_gen_guid0_MASK 0x000000ff 3085 #define lpfc_cntl_attr_gen_guid0_WORD word105 3086 uint32_t gen_guid1_12[3]; 3087 uint32_t word109; 3088 #define lpfc_cntl_attr_gen_guid13_14_SHIFT 0 3089 #define lpfc_cntl_attr_gen_guid13_14_MASK 0x0000ffff 3090 #define lpfc_cntl_attr_gen_guid13_14_WORD word109 3091 #define lpfc_cntl_attr_gen_guid15_SHIFT 16 3092 #define lpfc_cntl_attr_gen_guid15_MASK 0x000000ff 3093 #define lpfc_cntl_attr_gen_guid15_WORD word109 3094 #define lpfc_cntl_attr_hba_port_cnt_SHIFT 24 3095 #define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff 3096 #define lpfc_cntl_attr_hba_port_cnt_WORD word109 3097 uint32_t word110; 3098 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT 0 3099 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK 0x0000ffff 3100 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD word110 3101 #define lpfc_cntl_attr_multi_func_dev_SHIFT 24 3102 #define lpfc_cntl_attr_multi_func_dev_MASK 0x000000ff 3103 #define lpfc_cntl_attr_multi_func_dev_WORD word110 3104 uint32_t word111; 3105 #define lpfc_cntl_attr_cache_valid_SHIFT 0 3106 #define lpfc_cntl_attr_cache_valid_MASK 0x000000ff 3107 #define lpfc_cntl_attr_cache_valid_WORD word111 3108 #define lpfc_cntl_attr_hba_status_SHIFT 8 3109 #define lpfc_cntl_attr_hba_status_MASK 0x000000ff 3110 #define lpfc_cntl_attr_hba_status_WORD word111 3111 #define lpfc_cntl_attr_max_domain_SHIFT 16 3112 #define lpfc_cntl_attr_max_domain_MASK 0x000000ff 3113 #define lpfc_cntl_attr_max_domain_WORD word111 3114 #define lpfc_cntl_attr_lnk_numb_SHIFT 24 3115 #define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f 3116 #define lpfc_cntl_attr_lnk_numb_WORD word111 3117 #define lpfc_cntl_attr_lnk_type_SHIFT 30 3118 #define lpfc_cntl_attr_lnk_type_MASK 0x00000003 3119 #define lpfc_cntl_attr_lnk_type_WORD word111 3120 uint32_t fw_post_status; 3121 uint32_t hba_mtu[8]; 3122 uint32_t word121; 3123 uint32_t reserved1[3]; 3124 uint32_t word125; 3125 #define lpfc_cntl_attr_pci_vendor_id_SHIFT 0 3126 #define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff 3127 #define lpfc_cntl_attr_pci_vendor_id_WORD word125 3128 #define lpfc_cntl_attr_pci_device_id_SHIFT 16 3129 #define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff 3130 #define lpfc_cntl_attr_pci_device_id_WORD word125 3131 uint32_t word126; 3132 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0 3133 #define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff 3134 #define lpfc_cntl_attr_pci_subvdr_id_WORD word126 3135 #define lpfc_cntl_attr_pci_subsys_id_SHIFT 16 3136 #define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff 3137 #define lpfc_cntl_attr_pci_subsys_id_WORD word126 3138 uint32_t word127; 3139 #define lpfc_cntl_attr_pci_bus_num_SHIFT 0 3140 #define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff 3141 #define lpfc_cntl_attr_pci_bus_num_WORD word127 3142 #define lpfc_cntl_attr_pci_dev_num_SHIFT 8 3143 #define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff 3144 #define lpfc_cntl_attr_pci_dev_num_WORD word127 3145 #define lpfc_cntl_attr_pci_fnc_num_SHIFT 16 3146 #define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff 3147 #define lpfc_cntl_attr_pci_fnc_num_WORD word127 3148 #define lpfc_cntl_attr_inf_type_SHIFT 24 3149 #define lpfc_cntl_attr_inf_type_MASK 0x000000ff 3150 #define lpfc_cntl_attr_inf_type_WORD word127 3151 uint32_t unique_id[2]; 3152 uint32_t word130; 3153 #define lpfc_cntl_attr_num_netfil_SHIFT 0 3154 #define lpfc_cntl_attr_num_netfil_MASK 0x000000ff 3155 #define lpfc_cntl_attr_num_netfil_WORD word130 3156 uint32_t reserved2[4]; 3157 }; 3158 3159 struct lpfc_mbx_get_cntl_attributes { 3160 union lpfc_sli4_cfg_shdr cfg_shdr; 3161 struct lpfc_controller_attribute cntl_attr; 3162 }; 3163 3164 struct lpfc_mbx_get_port_name { 3165 struct mbox_header header; 3166 union { 3167 struct { 3168 uint32_t word4; 3169 #define lpfc_mbx_get_port_name_lnk_type_SHIFT 0 3170 #define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003 3171 #define lpfc_mbx_get_port_name_lnk_type_WORD word4 3172 } request; 3173 struct { 3174 uint32_t word4; 3175 #define lpfc_mbx_get_port_name_name0_SHIFT 0 3176 #define lpfc_mbx_get_port_name_name0_MASK 0x000000FF 3177 #define lpfc_mbx_get_port_name_name0_WORD word4 3178 #define lpfc_mbx_get_port_name_name1_SHIFT 8 3179 #define lpfc_mbx_get_port_name_name1_MASK 0x000000FF 3180 #define lpfc_mbx_get_port_name_name1_WORD word4 3181 #define lpfc_mbx_get_port_name_name2_SHIFT 16 3182 #define lpfc_mbx_get_port_name_name2_MASK 0x000000FF 3183 #define lpfc_mbx_get_port_name_name2_WORD word4 3184 #define lpfc_mbx_get_port_name_name3_SHIFT 24 3185 #define lpfc_mbx_get_port_name_name3_MASK 0x000000FF 3186 #define lpfc_mbx_get_port_name_name3_WORD word4 3187 #define LPFC_LINK_NUMBER_0 0 3188 #define LPFC_LINK_NUMBER_1 1 3189 #define LPFC_LINK_NUMBER_2 2 3190 #define LPFC_LINK_NUMBER_3 3 3191 } response; 3192 } u; 3193 }; 3194 3195 /* Mailbox Completion Queue Error Messages */ 3196 #define MB_CQE_STATUS_SUCCESS 0x0 3197 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1 3198 #define MB_CQE_STATUS_INVALID_PARAMETER 0x2 3199 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3 3200 #define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4 3201 #define MB_CQE_STATUS_DMA_FAILED 0x5 3202 3203 #define LPFC_MBX_WR_CONFIG_MAX_BDE 8 3204 struct lpfc_mbx_wr_object { 3205 struct mbox_header header; 3206 union { 3207 struct { 3208 uint32_t word4; 3209 #define lpfc_wr_object_eof_SHIFT 31 3210 #define lpfc_wr_object_eof_MASK 0x00000001 3211 #define lpfc_wr_object_eof_WORD word4 3212 #define lpfc_wr_object_write_length_SHIFT 0 3213 #define lpfc_wr_object_write_length_MASK 0x00FFFFFF 3214 #define lpfc_wr_object_write_length_WORD word4 3215 uint32_t write_offset; 3216 uint32_t object_name[26]; 3217 uint32_t bde_count; 3218 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE]; 3219 } request; 3220 struct { 3221 uint32_t actual_write_length; 3222 } response; 3223 } u; 3224 }; 3225 3226 /* mailbox queue entry structure */ 3227 struct lpfc_mqe { 3228 uint32_t word0; 3229 #define lpfc_mqe_status_SHIFT 16 3230 #define lpfc_mqe_status_MASK 0x0000FFFF 3231 #define lpfc_mqe_status_WORD word0 3232 #define lpfc_mqe_command_SHIFT 8 3233 #define lpfc_mqe_command_MASK 0x000000FF 3234 #define lpfc_mqe_command_WORD word0 3235 union { 3236 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1]; 3237 /* sli4 mailbox commands */ 3238 struct lpfc_mbx_sli4_config sli4_config; 3239 struct lpfc_mbx_init_vfi init_vfi; 3240 struct lpfc_mbx_reg_vfi reg_vfi; 3241 struct lpfc_mbx_reg_vfi unreg_vfi; 3242 struct lpfc_mbx_init_vpi init_vpi; 3243 struct lpfc_mbx_resume_rpi resume_rpi; 3244 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl; 3245 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry; 3246 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry; 3247 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl; 3248 struct lpfc_mbx_reg_fcfi reg_fcfi; 3249 struct lpfc_mbx_unreg_fcfi unreg_fcfi; 3250 struct lpfc_mbx_mq_create mq_create; 3251 struct lpfc_mbx_mq_create_ext mq_create_ext; 3252 struct lpfc_mbx_eq_create eq_create; 3253 struct lpfc_mbx_modify_eq_delay eq_delay; 3254 struct lpfc_mbx_cq_create cq_create; 3255 struct lpfc_mbx_wq_create wq_create; 3256 struct lpfc_mbx_rq_create rq_create; 3257 struct lpfc_mbx_mq_destroy mq_destroy; 3258 struct lpfc_mbx_eq_destroy eq_destroy; 3259 struct lpfc_mbx_cq_destroy cq_destroy; 3260 struct lpfc_mbx_wq_destroy wq_destroy; 3261 struct lpfc_mbx_rq_destroy rq_destroy; 3262 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info; 3263 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents; 3264 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents; 3265 struct lpfc_mbx_post_sgl_pages post_sgl_pages; 3266 struct lpfc_mbx_nembed_cmd nembed_cmd; 3267 struct lpfc_mbx_read_rev read_rev; 3268 struct lpfc_mbx_read_vpi read_vpi; 3269 struct lpfc_mbx_read_config rd_config; 3270 struct lpfc_mbx_request_features req_ftrs; 3271 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl; 3272 struct lpfc_mbx_query_fw_config query_fw_cfg; 3273 struct lpfc_mbx_set_beacon_config beacon_config; 3274 struct lpfc_mbx_supp_pages supp_pages; 3275 struct lpfc_mbx_pc_sli4_params sli4_params; 3276 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters; 3277 struct lpfc_mbx_set_link_diag_state link_diag_state; 3278 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback; 3279 struct lpfc_mbx_run_link_diag_test link_diag_test; 3280 struct lpfc_mbx_get_func_cfg get_func_cfg; 3281 struct lpfc_mbx_get_prof_cfg get_prof_cfg; 3282 struct lpfc_mbx_wr_object wr_object; 3283 struct lpfc_mbx_get_port_name get_port_name; 3284 struct lpfc_mbx_memory_dump_type3 mem_dump_type3; 3285 struct lpfc_mbx_nop nop; 3286 } un; 3287 }; 3288 3289 struct lpfc_mcqe { 3290 uint32_t word0; 3291 #define lpfc_mcqe_status_SHIFT 0 3292 #define lpfc_mcqe_status_MASK 0x0000FFFF 3293 #define lpfc_mcqe_status_WORD word0 3294 #define lpfc_mcqe_ext_status_SHIFT 16 3295 #define lpfc_mcqe_ext_status_MASK 0x0000FFFF 3296 #define lpfc_mcqe_ext_status_WORD word0 3297 uint32_t mcqe_tag0; 3298 uint32_t mcqe_tag1; 3299 uint32_t trailer; 3300 #define lpfc_trailer_valid_SHIFT 31 3301 #define lpfc_trailer_valid_MASK 0x00000001 3302 #define lpfc_trailer_valid_WORD trailer 3303 #define lpfc_trailer_async_SHIFT 30 3304 #define lpfc_trailer_async_MASK 0x00000001 3305 #define lpfc_trailer_async_WORD trailer 3306 #define lpfc_trailer_hpi_SHIFT 29 3307 #define lpfc_trailer_hpi_MASK 0x00000001 3308 #define lpfc_trailer_hpi_WORD trailer 3309 #define lpfc_trailer_completed_SHIFT 28 3310 #define lpfc_trailer_completed_MASK 0x00000001 3311 #define lpfc_trailer_completed_WORD trailer 3312 #define lpfc_trailer_consumed_SHIFT 27 3313 #define lpfc_trailer_consumed_MASK 0x00000001 3314 #define lpfc_trailer_consumed_WORD trailer 3315 #define lpfc_trailer_type_SHIFT 16 3316 #define lpfc_trailer_type_MASK 0x000000FF 3317 #define lpfc_trailer_type_WORD trailer 3318 #define lpfc_trailer_code_SHIFT 8 3319 #define lpfc_trailer_code_MASK 0x000000FF 3320 #define lpfc_trailer_code_WORD trailer 3321 #define LPFC_TRAILER_CODE_LINK 0x1 3322 #define LPFC_TRAILER_CODE_FCOE 0x2 3323 #define LPFC_TRAILER_CODE_DCBX 0x3 3324 #define LPFC_TRAILER_CODE_GRP5 0x5 3325 #define LPFC_TRAILER_CODE_FC 0x10 3326 #define LPFC_TRAILER_CODE_SLI 0x11 3327 }; 3328 3329 struct lpfc_acqe_link { 3330 uint32_t word0; 3331 #define lpfc_acqe_link_speed_SHIFT 24 3332 #define lpfc_acqe_link_speed_MASK 0x000000FF 3333 #define lpfc_acqe_link_speed_WORD word0 3334 #define LPFC_ASYNC_LINK_SPEED_ZERO 0x0 3335 #define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1 3336 #define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2 3337 #define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3 3338 #define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4 3339 #define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5 3340 #define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6 3341 #define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7 3342 #define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8 3343 #define lpfc_acqe_link_duplex_SHIFT 16 3344 #define lpfc_acqe_link_duplex_MASK 0x000000FF 3345 #define lpfc_acqe_link_duplex_WORD word0 3346 #define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0 3347 #define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1 3348 #define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2 3349 #define lpfc_acqe_link_status_SHIFT 8 3350 #define lpfc_acqe_link_status_MASK 0x000000FF 3351 #define lpfc_acqe_link_status_WORD word0 3352 #define LPFC_ASYNC_LINK_STATUS_DOWN 0x0 3353 #define LPFC_ASYNC_LINK_STATUS_UP 0x1 3354 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2 3355 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3 3356 #define lpfc_acqe_link_type_SHIFT 6 3357 #define lpfc_acqe_link_type_MASK 0x00000003 3358 #define lpfc_acqe_link_type_WORD word0 3359 #define lpfc_acqe_link_number_SHIFT 0 3360 #define lpfc_acqe_link_number_MASK 0x0000003F 3361 #define lpfc_acqe_link_number_WORD word0 3362 uint32_t word1; 3363 #define lpfc_acqe_link_fault_SHIFT 0 3364 #define lpfc_acqe_link_fault_MASK 0x000000FF 3365 #define lpfc_acqe_link_fault_WORD word1 3366 #define LPFC_ASYNC_LINK_FAULT_NONE 0x0 3367 #define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1 3368 #define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2 3369 #define lpfc_acqe_logical_link_speed_SHIFT 16 3370 #define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF 3371 #define lpfc_acqe_logical_link_speed_WORD word1 3372 uint32_t event_tag; 3373 uint32_t trailer; 3374 #define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0 3375 #define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1 3376 }; 3377 3378 struct lpfc_acqe_fip { 3379 uint32_t index; 3380 uint32_t word1; 3381 #define lpfc_acqe_fip_fcf_count_SHIFT 0 3382 #define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF 3383 #define lpfc_acqe_fip_fcf_count_WORD word1 3384 #define lpfc_acqe_fip_event_type_SHIFT 16 3385 #define lpfc_acqe_fip_event_type_MASK 0x0000FFFF 3386 #define lpfc_acqe_fip_event_type_WORD word1 3387 uint32_t event_tag; 3388 uint32_t trailer; 3389 #define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1 3390 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2 3391 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3 3392 #define LPFC_FIP_EVENT_TYPE_CVL 0x4 3393 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5 3394 }; 3395 3396 struct lpfc_acqe_dcbx { 3397 uint32_t tlv_ttl; 3398 uint32_t reserved; 3399 uint32_t event_tag; 3400 uint32_t trailer; 3401 }; 3402 3403 struct lpfc_acqe_grp5 { 3404 uint32_t word0; 3405 #define lpfc_acqe_grp5_type_SHIFT 6 3406 #define lpfc_acqe_grp5_type_MASK 0x00000003 3407 #define lpfc_acqe_grp5_type_WORD word0 3408 #define lpfc_acqe_grp5_number_SHIFT 0 3409 #define lpfc_acqe_grp5_number_MASK 0x0000003F 3410 #define lpfc_acqe_grp5_number_WORD word0 3411 uint32_t word1; 3412 #define lpfc_acqe_grp5_llink_spd_SHIFT 16 3413 #define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF 3414 #define lpfc_acqe_grp5_llink_spd_WORD word1 3415 uint32_t event_tag; 3416 uint32_t trailer; 3417 }; 3418 3419 struct lpfc_acqe_fc_la { 3420 uint32_t word0; 3421 #define lpfc_acqe_fc_la_speed_SHIFT 24 3422 #define lpfc_acqe_fc_la_speed_MASK 0x000000FF 3423 #define lpfc_acqe_fc_la_speed_WORD word0 3424 #define LPFC_FC_LA_SPEED_UNKNOWN 0x0 3425 #define LPFC_FC_LA_SPEED_1G 0x1 3426 #define LPFC_FC_LA_SPEED_2G 0x2 3427 #define LPFC_FC_LA_SPEED_4G 0x4 3428 #define LPFC_FC_LA_SPEED_8G 0x8 3429 #define LPFC_FC_LA_SPEED_10G 0xA 3430 #define LPFC_FC_LA_SPEED_16G 0x10 3431 #define LPFC_FC_LA_SPEED_32G 0x20 3432 #define lpfc_acqe_fc_la_topology_SHIFT 16 3433 #define lpfc_acqe_fc_la_topology_MASK 0x000000FF 3434 #define lpfc_acqe_fc_la_topology_WORD word0 3435 #define LPFC_FC_LA_TOP_UNKOWN 0x0 3436 #define LPFC_FC_LA_TOP_P2P 0x1 3437 #define LPFC_FC_LA_TOP_FCAL 0x2 3438 #define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3 3439 #define LPFC_FC_LA_TOP_SERDES_LOOP 0x4 3440 #define lpfc_acqe_fc_la_att_type_SHIFT 8 3441 #define lpfc_acqe_fc_la_att_type_MASK 0x000000FF 3442 #define lpfc_acqe_fc_la_att_type_WORD word0 3443 #define LPFC_FC_LA_TYPE_LINK_UP 0x1 3444 #define LPFC_FC_LA_TYPE_LINK_DOWN 0x2 3445 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3 3446 #define lpfc_acqe_fc_la_port_type_SHIFT 6 3447 #define lpfc_acqe_fc_la_port_type_MASK 0x00000003 3448 #define lpfc_acqe_fc_la_port_type_WORD word0 3449 #define LPFC_LINK_TYPE_ETHERNET 0x0 3450 #define LPFC_LINK_TYPE_FC 0x1 3451 #define lpfc_acqe_fc_la_port_number_SHIFT 0 3452 #define lpfc_acqe_fc_la_port_number_MASK 0x0000003F 3453 #define lpfc_acqe_fc_la_port_number_WORD word0 3454 uint32_t word1; 3455 #define lpfc_acqe_fc_la_llink_spd_SHIFT 16 3456 #define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF 3457 #define lpfc_acqe_fc_la_llink_spd_WORD word1 3458 #define lpfc_acqe_fc_la_fault_SHIFT 0 3459 #define lpfc_acqe_fc_la_fault_MASK 0x000000FF 3460 #define lpfc_acqe_fc_la_fault_WORD word1 3461 #define LPFC_FC_LA_FAULT_NONE 0x0 3462 #define LPFC_FC_LA_FAULT_LOCAL 0x1 3463 #define LPFC_FC_LA_FAULT_REMOTE 0x2 3464 uint32_t event_tag; 3465 uint32_t trailer; 3466 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1 3467 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2 3468 }; 3469 3470 struct lpfc_acqe_misconfigured_event { 3471 struct { 3472 uint32_t word0; 3473 #define lpfc_sli_misconfigured_port0_state_SHIFT 0 3474 #define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF 3475 #define lpfc_sli_misconfigured_port0_state_WORD word0 3476 #define lpfc_sli_misconfigured_port1_state_SHIFT 8 3477 #define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF 3478 #define lpfc_sli_misconfigured_port1_state_WORD word0 3479 #define lpfc_sli_misconfigured_port2_state_SHIFT 16 3480 #define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF 3481 #define lpfc_sli_misconfigured_port2_state_WORD word0 3482 #define lpfc_sli_misconfigured_port3_state_SHIFT 24 3483 #define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF 3484 #define lpfc_sli_misconfigured_port3_state_WORD word0 3485 uint32_t word1; 3486 #define lpfc_sli_misconfigured_port0_op_SHIFT 0 3487 #define lpfc_sli_misconfigured_port0_op_MASK 0x00000001 3488 #define lpfc_sli_misconfigured_port0_op_WORD word1 3489 #define lpfc_sli_misconfigured_port0_severity_SHIFT 1 3490 #define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003 3491 #define lpfc_sli_misconfigured_port0_severity_WORD word1 3492 #define lpfc_sli_misconfigured_port1_op_SHIFT 8 3493 #define lpfc_sli_misconfigured_port1_op_MASK 0x00000001 3494 #define lpfc_sli_misconfigured_port1_op_WORD word1 3495 #define lpfc_sli_misconfigured_port1_severity_SHIFT 9 3496 #define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003 3497 #define lpfc_sli_misconfigured_port1_severity_WORD word1 3498 #define lpfc_sli_misconfigured_port2_op_SHIFT 16 3499 #define lpfc_sli_misconfigured_port2_op_MASK 0x00000001 3500 #define lpfc_sli_misconfigured_port2_op_WORD word1 3501 #define lpfc_sli_misconfigured_port2_severity_SHIFT 17 3502 #define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003 3503 #define lpfc_sli_misconfigured_port2_severity_WORD word1 3504 #define lpfc_sli_misconfigured_port3_op_SHIFT 24 3505 #define lpfc_sli_misconfigured_port3_op_MASK 0x00000001 3506 #define lpfc_sli_misconfigured_port3_op_WORD word1 3507 #define lpfc_sli_misconfigured_port3_severity_SHIFT 25 3508 #define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003 3509 #define lpfc_sli_misconfigured_port3_severity_WORD word1 3510 } theEvent; 3511 #define LPFC_SLI_EVENT_STATUS_VALID 0x00 3512 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01 3513 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02 3514 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03 3515 #define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04 3516 #define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05 3517 }; 3518 3519 struct lpfc_acqe_sli { 3520 uint32_t event_data1; 3521 uint32_t event_data2; 3522 uint32_t reserved; 3523 uint32_t trailer; 3524 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1 3525 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2 3526 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3 3527 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4 3528 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5 3529 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9 3530 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA 3531 }; 3532 3533 /* 3534 * Define the bootstrap mailbox (bmbx) region used to communicate 3535 * mailbox command between the host and port. The mailbox consists 3536 * of a payload area of 256 bytes and a completion queue of length 3537 * 16 bytes. 3538 */ 3539 struct lpfc_bmbx_create { 3540 struct lpfc_mqe mqe; 3541 struct lpfc_mcqe mcqe; 3542 }; 3543 3544 #define SGL_ALIGN_SZ 64 3545 #define SGL_PAGE_SIZE 4096 3546 /* align SGL addr on a size boundary - adjust address up */ 3547 #define NO_XRI 0xffff 3548 3549 struct wqe_common { 3550 uint32_t word6; 3551 #define wqe_xri_tag_SHIFT 0 3552 #define wqe_xri_tag_MASK 0x0000FFFF 3553 #define wqe_xri_tag_WORD word6 3554 #define wqe_ctxt_tag_SHIFT 16 3555 #define wqe_ctxt_tag_MASK 0x0000FFFF 3556 #define wqe_ctxt_tag_WORD word6 3557 uint32_t word7; 3558 #define wqe_dif_SHIFT 0 3559 #define wqe_dif_MASK 0x00000003 3560 #define wqe_dif_WORD word7 3561 #define LPFC_WQE_DIF_PASSTHRU 1 3562 #define LPFC_WQE_DIF_STRIP 2 3563 #define LPFC_WQE_DIF_INSERT 3 3564 #define wqe_ct_SHIFT 2 3565 #define wqe_ct_MASK 0x00000003 3566 #define wqe_ct_WORD word7 3567 #define wqe_status_SHIFT 4 3568 #define wqe_status_MASK 0x0000000f 3569 #define wqe_status_WORD word7 3570 #define wqe_cmnd_SHIFT 8 3571 #define wqe_cmnd_MASK 0x000000ff 3572 #define wqe_cmnd_WORD word7 3573 #define wqe_class_SHIFT 16 3574 #define wqe_class_MASK 0x00000007 3575 #define wqe_class_WORD word7 3576 #define wqe_ar_SHIFT 19 3577 #define wqe_ar_MASK 0x00000001 3578 #define wqe_ar_WORD word7 3579 #define wqe_ag_SHIFT wqe_ar_SHIFT 3580 #define wqe_ag_MASK wqe_ar_MASK 3581 #define wqe_ag_WORD wqe_ar_WORD 3582 #define wqe_pu_SHIFT 20 3583 #define wqe_pu_MASK 0x00000003 3584 #define wqe_pu_WORD word7 3585 #define wqe_erp_SHIFT 22 3586 #define wqe_erp_MASK 0x00000001 3587 #define wqe_erp_WORD word7 3588 #define wqe_conf_SHIFT wqe_erp_SHIFT 3589 #define wqe_conf_MASK wqe_erp_MASK 3590 #define wqe_conf_WORD wqe_erp_WORD 3591 #define wqe_lnk_SHIFT 23 3592 #define wqe_lnk_MASK 0x00000001 3593 #define wqe_lnk_WORD word7 3594 #define wqe_tmo_SHIFT 24 3595 #define wqe_tmo_MASK 0x000000ff 3596 #define wqe_tmo_WORD word7 3597 uint32_t abort_tag; /* word 8 in WQE */ 3598 uint32_t word9; 3599 #define wqe_reqtag_SHIFT 0 3600 #define wqe_reqtag_MASK 0x0000FFFF 3601 #define wqe_reqtag_WORD word9 3602 #define wqe_temp_rpi_SHIFT 16 3603 #define wqe_temp_rpi_MASK 0x0000FFFF 3604 #define wqe_temp_rpi_WORD word9 3605 #define wqe_rcvoxid_SHIFT 16 3606 #define wqe_rcvoxid_MASK 0x0000FFFF 3607 #define wqe_rcvoxid_WORD word9 3608 uint32_t word10; 3609 #define wqe_ebde_cnt_SHIFT 0 3610 #define wqe_ebde_cnt_MASK 0x0000000f 3611 #define wqe_ebde_cnt_WORD word10 3612 #define wqe_oas_SHIFT 6 3613 #define wqe_oas_MASK 0x00000001 3614 #define wqe_oas_WORD word10 3615 #define wqe_lenloc_SHIFT 7 3616 #define wqe_lenloc_MASK 0x00000003 3617 #define wqe_lenloc_WORD word10 3618 #define LPFC_WQE_LENLOC_NONE 0 3619 #define LPFC_WQE_LENLOC_WORD3 1 3620 #define LPFC_WQE_LENLOC_WORD12 2 3621 #define LPFC_WQE_LENLOC_WORD4 3 3622 #define wqe_qosd_SHIFT 9 3623 #define wqe_qosd_MASK 0x00000001 3624 #define wqe_qosd_WORD word10 3625 #define wqe_xbl_SHIFT 11 3626 #define wqe_xbl_MASK 0x00000001 3627 #define wqe_xbl_WORD word10 3628 #define wqe_iod_SHIFT 13 3629 #define wqe_iod_MASK 0x00000001 3630 #define wqe_iod_WORD word10 3631 #define LPFC_WQE_IOD_WRITE 0 3632 #define LPFC_WQE_IOD_READ 1 3633 #define wqe_dbde_SHIFT 14 3634 #define wqe_dbde_MASK 0x00000001 3635 #define wqe_dbde_WORD word10 3636 #define wqe_wqes_SHIFT 15 3637 #define wqe_wqes_MASK 0x00000001 3638 #define wqe_wqes_WORD word10 3639 /* Note that this field overlaps above fields */ 3640 #define wqe_wqid_SHIFT 1 3641 #define wqe_wqid_MASK 0x00007fff 3642 #define wqe_wqid_WORD word10 3643 #define wqe_pri_SHIFT 16 3644 #define wqe_pri_MASK 0x00000007 3645 #define wqe_pri_WORD word10 3646 #define wqe_pv_SHIFT 19 3647 #define wqe_pv_MASK 0x00000001 3648 #define wqe_pv_WORD word10 3649 #define wqe_xc_SHIFT 21 3650 #define wqe_xc_MASK 0x00000001 3651 #define wqe_xc_WORD word10 3652 #define wqe_sr_SHIFT 22 3653 #define wqe_sr_MASK 0x00000001 3654 #define wqe_sr_WORD word10 3655 #define wqe_ccpe_SHIFT 23 3656 #define wqe_ccpe_MASK 0x00000001 3657 #define wqe_ccpe_WORD word10 3658 #define wqe_ccp_SHIFT 24 3659 #define wqe_ccp_MASK 0x000000ff 3660 #define wqe_ccp_WORD word10 3661 uint32_t word11; 3662 #define wqe_cmd_type_SHIFT 0 3663 #define wqe_cmd_type_MASK 0x0000000f 3664 #define wqe_cmd_type_WORD word11 3665 #define wqe_els_id_SHIFT 4 3666 #define wqe_els_id_MASK 0x00000003 3667 #define wqe_els_id_WORD word11 3668 #define LPFC_ELS_ID_FLOGI 3 3669 #define LPFC_ELS_ID_FDISC 2 3670 #define LPFC_ELS_ID_LOGO 1 3671 #define LPFC_ELS_ID_DEFAULT 0 3672 #define wqe_wqec_SHIFT 7 3673 #define wqe_wqec_MASK 0x00000001 3674 #define wqe_wqec_WORD word11 3675 #define wqe_cqid_SHIFT 16 3676 #define wqe_cqid_MASK 0x0000ffff 3677 #define wqe_cqid_WORD word11 3678 #define LPFC_WQE_CQ_ID_DEFAULT 0xffff 3679 }; 3680 3681 struct wqe_did { 3682 uint32_t word5; 3683 #define wqe_els_did_SHIFT 0 3684 #define wqe_els_did_MASK 0x00FFFFFF 3685 #define wqe_els_did_WORD word5 3686 #define wqe_xmit_bls_pt_SHIFT 28 3687 #define wqe_xmit_bls_pt_MASK 0x00000003 3688 #define wqe_xmit_bls_pt_WORD word5 3689 #define wqe_xmit_bls_ar_SHIFT 30 3690 #define wqe_xmit_bls_ar_MASK 0x00000001 3691 #define wqe_xmit_bls_ar_WORD word5 3692 #define wqe_xmit_bls_xo_SHIFT 31 3693 #define wqe_xmit_bls_xo_MASK 0x00000001 3694 #define wqe_xmit_bls_xo_WORD word5 3695 }; 3696 3697 struct lpfc_wqe_generic{ 3698 struct ulp_bde64 bde; 3699 uint32_t word3; 3700 uint32_t word4; 3701 uint32_t word5; 3702 struct wqe_common wqe_com; 3703 uint32_t payload[4]; 3704 }; 3705 3706 struct els_request64_wqe { 3707 struct ulp_bde64 bde; 3708 uint32_t payload_len; 3709 uint32_t word4; 3710 #define els_req64_sid_SHIFT 0 3711 #define els_req64_sid_MASK 0x00FFFFFF 3712 #define els_req64_sid_WORD word4 3713 #define els_req64_sp_SHIFT 24 3714 #define els_req64_sp_MASK 0x00000001 3715 #define els_req64_sp_WORD word4 3716 #define els_req64_vf_SHIFT 25 3717 #define els_req64_vf_MASK 0x00000001 3718 #define els_req64_vf_WORD word4 3719 struct wqe_did wqe_dest; 3720 struct wqe_common wqe_com; /* words 6-11 */ 3721 uint32_t word12; 3722 #define els_req64_vfid_SHIFT 1 3723 #define els_req64_vfid_MASK 0x00000FFF 3724 #define els_req64_vfid_WORD word12 3725 #define els_req64_pri_SHIFT 13 3726 #define els_req64_pri_MASK 0x00000007 3727 #define els_req64_pri_WORD word12 3728 uint32_t word13; 3729 #define els_req64_hopcnt_SHIFT 24 3730 #define els_req64_hopcnt_MASK 0x000000ff 3731 #define els_req64_hopcnt_WORD word13 3732 uint32_t word14; 3733 uint32_t max_response_payload_len; 3734 }; 3735 3736 struct xmit_els_rsp64_wqe { 3737 struct ulp_bde64 bde; 3738 uint32_t response_payload_len; 3739 uint32_t word4; 3740 #define els_rsp64_sid_SHIFT 0 3741 #define els_rsp64_sid_MASK 0x00FFFFFF 3742 #define els_rsp64_sid_WORD word4 3743 #define els_rsp64_sp_SHIFT 24 3744 #define els_rsp64_sp_MASK 0x00000001 3745 #define els_rsp64_sp_WORD word4 3746 struct wqe_did wqe_dest; 3747 struct wqe_common wqe_com; /* words 6-11 */ 3748 uint32_t word12; 3749 #define wqe_rsp_temp_rpi_SHIFT 0 3750 #define wqe_rsp_temp_rpi_MASK 0x0000FFFF 3751 #define wqe_rsp_temp_rpi_WORD word12 3752 uint32_t rsvd_13_15[3]; 3753 }; 3754 3755 struct xmit_bls_rsp64_wqe { 3756 uint32_t payload0; 3757 /* Payload0 for BA_ACC */ 3758 #define xmit_bls_rsp64_acc_seq_id_SHIFT 16 3759 #define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff 3760 #define xmit_bls_rsp64_acc_seq_id_WORD payload0 3761 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24 3762 #define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff 3763 #define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0 3764 /* Payload0 for BA_RJT */ 3765 #define xmit_bls_rsp64_rjt_vspec_SHIFT 0 3766 #define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff 3767 #define xmit_bls_rsp64_rjt_vspec_WORD payload0 3768 #define xmit_bls_rsp64_rjt_expc_SHIFT 8 3769 #define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff 3770 #define xmit_bls_rsp64_rjt_expc_WORD payload0 3771 #define xmit_bls_rsp64_rjt_rsnc_SHIFT 16 3772 #define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff 3773 #define xmit_bls_rsp64_rjt_rsnc_WORD payload0 3774 uint32_t word1; 3775 #define xmit_bls_rsp64_rxid_SHIFT 0 3776 #define xmit_bls_rsp64_rxid_MASK 0x0000ffff 3777 #define xmit_bls_rsp64_rxid_WORD word1 3778 #define xmit_bls_rsp64_oxid_SHIFT 16 3779 #define xmit_bls_rsp64_oxid_MASK 0x0000ffff 3780 #define xmit_bls_rsp64_oxid_WORD word1 3781 uint32_t word2; 3782 #define xmit_bls_rsp64_seqcnthi_SHIFT 0 3783 #define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff 3784 #define xmit_bls_rsp64_seqcnthi_WORD word2 3785 #define xmit_bls_rsp64_seqcntlo_SHIFT 16 3786 #define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff 3787 #define xmit_bls_rsp64_seqcntlo_WORD word2 3788 uint32_t rsrvd3; 3789 uint32_t rsrvd4; 3790 struct wqe_did wqe_dest; 3791 struct wqe_common wqe_com; /* words 6-11 */ 3792 uint32_t word12; 3793 #define xmit_bls_rsp64_temprpi_SHIFT 0 3794 #define xmit_bls_rsp64_temprpi_MASK 0x0000ffff 3795 #define xmit_bls_rsp64_temprpi_WORD word12 3796 uint32_t rsvd_13_15[3]; 3797 }; 3798 3799 struct wqe_rctl_dfctl { 3800 uint32_t word5; 3801 #define wqe_si_SHIFT 2 3802 #define wqe_si_MASK 0x000000001 3803 #define wqe_si_WORD word5 3804 #define wqe_la_SHIFT 3 3805 #define wqe_la_MASK 0x000000001 3806 #define wqe_la_WORD word5 3807 #define wqe_xo_SHIFT 6 3808 #define wqe_xo_MASK 0x000000001 3809 #define wqe_xo_WORD word5 3810 #define wqe_ls_SHIFT 7 3811 #define wqe_ls_MASK 0x000000001 3812 #define wqe_ls_WORD word5 3813 #define wqe_dfctl_SHIFT 8 3814 #define wqe_dfctl_MASK 0x0000000ff 3815 #define wqe_dfctl_WORD word5 3816 #define wqe_type_SHIFT 16 3817 #define wqe_type_MASK 0x0000000ff 3818 #define wqe_type_WORD word5 3819 #define wqe_rctl_SHIFT 24 3820 #define wqe_rctl_MASK 0x0000000ff 3821 #define wqe_rctl_WORD word5 3822 }; 3823 3824 struct xmit_seq64_wqe { 3825 struct ulp_bde64 bde; 3826 uint32_t rsvd3; 3827 uint32_t relative_offset; 3828 struct wqe_rctl_dfctl wge_ctl; 3829 struct wqe_common wqe_com; /* words 6-11 */ 3830 uint32_t xmit_len; 3831 uint32_t rsvd_12_15[3]; 3832 }; 3833 struct xmit_bcast64_wqe { 3834 struct ulp_bde64 bde; 3835 uint32_t seq_payload_len; 3836 uint32_t rsvd4; 3837 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3838 struct wqe_common wqe_com; /* words 6-11 */ 3839 uint32_t rsvd_12_15[4]; 3840 }; 3841 3842 struct gen_req64_wqe { 3843 struct ulp_bde64 bde; 3844 uint32_t request_payload_len; 3845 uint32_t relative_offset; 3846 struct wqe_rctl_dfctl wge_ctl; /* word 5 */ 3847 struct wqe_common wqe_com; /* words 6-11 */ 3848 uint32_t rsvd_12_14[3]; 3849 uint32_t max_response_payload_len; 3850 }; 3851 3852 struct create_xri_wqe { 3853 uint32_t rsrvd[5]; /* words 0-4 */ 3854 struct wqe_did wqe_dest; /* word 5 */ 3855 struct wqe_common wqe_com; /* words 6-11 */ 3856 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3857 }; 3858 3859 #define T_REQUEST_TAG 3 3860 #define T_XRI_TAG 1 3861 3862 struct abort_cmd_wqe { 3863 uint32_t rsrvd[3]; 3864 uint32_t word3; 3865 #define abort_cmd_ia_SHIFT 0 3866 #define abort_cmd_ia_MASK 0x000000001 3867 #define abort_cmd_ia_WORD word3 3868 #define abort_cmd_criteria_SHIFT 8 3869 #define abort_cmd_criteria_MASK 0x0000000ff 3870 #define abort_cmd_criteria_WORD word3 3871 uint32_t rsrvd4; 3872 uint32_t rsrvd5; 3873 struct wqe_common wqe_com; /* words 6-11 */ 3874 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3875 }; 3876 3877 struct fcp_iwrite64_wqe { 3878 struct ulp_bde64 bde; 3879 uint32_t word3; 3880 #define cmd_buff_len_SHIFT 16 3881 #define cmd_buff_len_MASK 0x00000ffff 3882 #define cmd_buff_len_WORD word3 3883 #define payload_offset_len_SHIFT 0 3884 #define payload_offset_len_MASK 0x0000ffff 3885 #define payload_offset_len_WORD word3 3886 uint32_t total_xfer_len; 3887 uint32_t initial_xfer_len; 3888 struct wqe_common wqe_com; /* words 6-11 */ 3889 uint32_t rsrvd12; 3890 struct ulp_bde64 ph_bde; /* words 13-15 */ 3891 }; 3892 3893 struct fcp_iread64_wqe { 3894 struct ulp_bde64 bde; 3895 uint32_t word3; 3896 #define cmd_buff_len_SHIFT 16 3897 #define cmd_buff_len_MASK 0x00000ffff 3898 #define cmd_buff_len_WORD word3 3899 #define payload_offset_len_SHIFT 0 3900 #define payload_offset_len_MASK 0x0000ffff 3901 #define payload_offset_len_WORD word3 3902 uint32_t total_xfer_len; /* word 4 */ 3903 uint32_t rsrvd5; /* word 5 */ 3904 struct wqe_common wqe_com; /* words 6-11 */ 3905 uint32_t rsrvd12; 3906 struct ulp_bde64 ph_bde; /* words 13-15 */ 3907 }; 3908 3909 struct fcp_icmnd64_wqe { 3910 struct ulp_bde64 bde; /* words 0-2 */ 3911 uint32_t word3; 3912 #define cmd_buff_len_SHIFT 16 3913 #define cmd_buff_len_MASK 0x00000ffff 3914 #define cmd_buff_len_WORD word3 3915 #define payload_offset_len_SHIFT 0 3916 #define payload_offset_len_MASK 0x0000ffff 3917 #define payload_offset_len_WORD word3 3918 uint32_t rsrvd4; /* word 4 */ 3919 uint32_t rsrvd5; /* word 5 */ 3920 struct wqe_common wqe_com; /* words 6-11 */ 3921 uint32_t rsvd_12_15[4]; /* word 12-15 */ 3922 }; 3923 3924 3925 union lpfc_wqe { 3926 uint32_t words[16]; 3927 struct lpfc_wqe_generic generic; 3928 struct fcp_icmnd64_wqe fcp_icmd; 3929 struct fcp_iread64_wqe fcp_iread; 3930 struct fcp_iwrite64_wqe fcp_iwrite; 3931 struct abort_cmd_wqe abort_cmd; 3932 struct create_xri_wqe create_xri; 3933 struct xmit_bcast64_wqe xmit_bcast64; 3934 struct xmit_seq64_wqe xmit_sequence; 3935 struct xmit_bls_rsp64_wqe xmit_bls_rsp; 3936 struct xmit_els_rsp64_wqe xmit_els_rsp; 3937 struct els_request64_wqe els_req; 3938 struct gen_req64_wqe gen_req; 3939 }; 3940 3941 union lpfc_wqe128 { 3942 uint32_t words[32]; 3943 struct lpfc_wqe_generic generic; 3944 struct fcp_icmnd64_wqe fcp_icmd; 3945 struct fcp_iread64_wqe fcp_iread; 3946 struct fcp_iwrite64_wqe fcp_iwrite; 3947 struct xmit_seq64_wqe xmit_sequence; 3948 struct gen_req64_wqe gen_req; 3949 }; 3950 3951 #define LPFC_GROUP_OJECT_MAGIC_NUM 0xfeaa0001 3952 #define LPFC_FILE_TYPE_GROUP 0xf7 3953 #define LPFC_FILE_ID_GROUP 0xa2 3954 struct lpfc_grp_hdr { 3955 uint32_t size; 3956 uint32_t magic_number; 3957 uint32_t word2; 3958 #define lpfc_grp_hdr_file_type_SHIFT 24 3959 #define lpfc_grp_hdr_file_type_MASK 0x000000FF 3960 #define lpfc_grp_hdr_file_type_WORD word2 3961 #define lpfc_grp_hdr_id_SHIFT 16 3962 #define lpfc_grp_hdr_id_MASK 0x000000FF 3963 #define lpfc_grp_hdr_id_WORD word2 3964 uint8_t rev_name[128]; 3965 uint8_t date[12]; 3966 uint8_t revision[32]; 3967 }; 3968 3969 #define FCP_COMMAND 0x0 3970 #define FCP_COMMAND_DATA_OUT 0x1 3971 #define ELS_COMMAND_NON_FIP 0xC 3972 #define ELS_COMMAND_FIP 0xD 3973 #define OTHER_COMMAND 0x8 3974 3975 #define LPFC_FW_DUMP 1 3976 #define LPFC_FW_RESET 2 3977 #define LPFC_DV_RESET 3 3978