1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2010 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 #define SLI2_IOCB_CMD_SIZE 32 63 #define SLI2_IOCB_RSP_SIZE 32 64 #define SLI3_IOCB_CMD_SIZE 128 65 #define SLI3_IOCB_RSP_SIZE 64 66 67 68 /* vendor ID used in SCSI netlink calls */ 69 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 70 71 /* Common Transport structures and definitions */ 72 73 union CtRevisionId { 74 /* Structure is in Big Endian format */ 75 struct { 76 uint32_t Revision:8; 77 uint32_t InId:24; 78 } bits; 79 uint32_t word; 80 }; 81 82 union CtCommandResponse { 83 /* Structure is in Big Endian format */ 84 struct { 85 uint32_t CmdRsp:16; 86 uint32_t Size:16; 87 } bits; 88 uint32_t word; 89 }; 90 91 #define FC4_FEATURE_INIT 0x2 92 #define FC4_FEATURE_TARGET 0x1 93 94 struct lpfc_sli_ct_request { 95 /* Structure is in Big Endian format */ 96 union CtRevisionId RevisionId; 97 uint8_t FsType; 98 uint8_t FsSubType; 99 uint8_t Options; 100 uint8_t Rsrvd1; 101 union CtCommandResponse CommandResponse; 102 uint8_t Rsrvd2; 103 uint8_t ReasonCode; 104 uint8_t Explanation; 105 uint8_t VendorUnique; 106 107 union { 108 uint32_t PortID; 109 struct gid { 110 uint8_t PortType; /* for GID_PT requests */ 111 uint8_t DomainScope; 112 uint8_t AreaScope; 113 uint8_t Fc4Type; /* for GID_FT requests */ 114 } gid; 115 struct rft { 116 uint32_t PortId; /* For RFT_ID requests */ 117 118 #ifdef __BIG_ENDIAN_BITFIELD 119 uint32_t rsvd0:16; 120 uint32_t rsvd1:7; 121 uint32_t fcpReg:1; /* Type 8 */ 122 uint32_t rsvd2:2; 123 uint32_t ipReg:1; /* Type 5 */ 124 uint32_t rsvd3:5; 125 #else /* __LITTLE_ENDIAN_BITFIELD */ 126 uint32_t rsvd0:16; 127 uint32_t fcpReg:1; /* Type 8 */ 128 uint32_t rsvd1:7; 129 uint32_t rsvd3:5; 130 uint32_t ipReg:1; /* Type 5 */ 131 uint32_t rsvd2:2; 132 #endif 133 134 uint32_t rsvd[7]; 135 } rft; 136 struct rnn { 137 uint32_t PortId; /* For RNN_ID requests */ 138 uint8_t wwnn[8]; 139 } rnn; 140 struct rsnn { /* For RSNN_ID requests */ 141 uint8_t wwnn[8]; 142 uint8_t len; 143 uint8_t symbname[255]; 144 } rsnn; 145 struct da_id { /* For DA_ID requests */ 146 uint32_t port_id; 147 } da_id; 148 struct rspn { /* For RSPN_ID requests */ 149 uint32_t PortId; 150 uint8_t len; 151 uint8_t symbname[255]; 152 } rspn; 153 struct gff { 154 uint32_t PortId; 155 } gff; 156 struct gff_acc { 157 uint8_t fbits[128]; 158 } gff_acc; 159 #define FCP_TYPE_FEATURE_OFFSET 7 160 struct rff { 161 uint32_t PortId; 162 uint8_t reserved[2]; 163 uint8_t fbits; 164 uint8_t type_code; /* type=8 for FCP */ 165 } rff; 166 } un; 167 }; 168 169 #define SLI_CT_REVISION 1 170 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 171 sizeof(struct gid)) 172 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 173 sizeof(struct gff)) 174 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 175 sizeof(struct rft)) 176 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 177 sizeof(struct rff)) 178 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 179 sizeof(struct rnn)) 180 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 181 sizeof(struct rsnn)) 182 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 183 sizeof(struct da_id)) 184 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 185 sizeof(struct rspn)) 186 187 /* 188 * FsType Definitions 189 */ 190 191 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 192 #define SLI_CT_TIME_SERVICE 0xFB 193 #define SLI_CT_DIRECTORY_SERVICE 0xFC 194 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 195 196 /* 197 * Directory Service Subtypes 198 */ 199 200 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 201 202 /* 203 * Response Codes 204 */ 205 206 #define SLI_CT_RESPONSE_FS_RJT 0x8001 207 #define SLI_CT_RESPONSE_FS_ACC 0x8002 208 209 /* 210 * Reason Codes 211 */ 212 213 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 214 #define SLI_CT_INVALID_COMMAND 0x01 215 #define SLI_CT_INVALID_VERSION 0x02 216 #define SLI_CT_LOGICAL_ERROR 0x03 217 #define SLI_CT_INVALID_IU_SIZE 0x04 218 #define SLI_CT_LOGICAL_BUSY 0x05 219 #define SLI_CT_PROTOCOL_ERROR 0x07 220 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 221 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 222 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 223 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 224 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 225 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 226 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 227 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 228 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 229 #define SLI_CT_VENDOR_UNIQUE 0xff 230 231 /* 232 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 233 */ 234 235 #define SLI_CT_NO_PORT_ID 0x01 236 #define SLI_CT_NO_PORT_NAME 0x02 237 #define SLI_CT_NO_NODE_NAME 0x03 238 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 239 #define SLI_CT_NO_IP_ADDRESS 0x05 240 #define SLI_CT_NO_IPA 0x06 241 #define SLI_CT_NO_FC4_TYPES 0x07 242 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 243 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 244 #define SLI_CT_NO_PORT_TYPE 0x0A 245 #define SLI_CT_ACCESS_DENIED 0x10 246 #define SLI_CT_INVALID_PORT_ID 0x11 247 #define SLI_CT_DATABASE_EMPTY 0x12 248 249 /* 250 * Name Server Command Codes 251 */ 252 253 #define SLI_CTNS_GA_NXT 0x0100 254 #define SLI_CTNS_GPN_ID 0x0112 255 #define SLI_CTNS_GNN_ID 0x0113 256 #define SLI_CTNS_GCS_ID 0x0114 257 #define SLI_CTNS_GFT_ID 0x0117 258 #define SLI_CTNS_GSPN_ID 0x0118 259 #define SLI_CTNS_GPT_ID 0x011A 260 #define SLI_CTNS_GFF_ID 0x011F 261 #define SLI_CTNS_GID_PN 0x0121 262 #define SLI_CTNS_GID_NN 0x0131 263 #define SLI_CTNS_GIP_NN 0x0135 264 #define SLI_CTNS_GIPA_NN 0x0136 265 #define SLI_CTNS_GSNN_NN 0x0139 266 #define SLI_CTNS_GNN_IP 0x0153 267 #define SLI_CTNS_GIPA_IP 0x0156 268 #define SLI_CTNS_GID_FT 0x0171 269 #define SLI_CTNS_GID_PT 0x01A1 270 #define SLI_CTNS_RPN_ID 0x0212 271 #define SLI_CTNS_RNN_ID 0x0213 272 #define SLI_CTNS_RCS_ID 0x0214 273 #define SLI_CTNS_RFT_ID 0x0217 274 #define SLI_CTNS_RSPN_ID 0x0218 275 #define SLI_CTNS_RPT_ID 0x021A 276 #define SLI_CTNS_RFF_ID 0x021F 277 #define SLI_CTNS_RIP_NN 0x0235 278 #define SLI_CTNS_RIPA_NN 0x0236 279 #define SLI_CTNS_RSNN_NN 0x0239 280 #define SLI_CTNS_DA_ID 0x0300 281 282 /* 283 * Port Types 284 */ 285 286 #define SLI_CTPT_N_PORT 0x01 287 #define SLI_CTPT_NL_PORT 0x02 288 #define SLI_CTPT_FNL_PORT 0x03 289 #define SLI_CTPT_IP 0x04 290 #define SLI_CTPT_FCP 0x08 291 #define SLI_CTPT_NX_PORT 0x7F 292 #define SLI_CTPT_F_PORT 0x81 293 #define SLI_CTPT_FL_PORT 0x82 294 #define SLI_CTPT_E_PORT 0x84 295 296 #define SLI_CT_LAST_ENTRY 0x80000000 297 298 /* Fibre Channel Service Parameter definitions */ 299 300 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 301 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 302 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 303 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 304 305 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 306 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 307 #define FC_PH3 0x20 /* FC-PH-3 version */ 308 309 #define FF_FRAME_SIZE 2048 310 311 struct lpfc_name { 312 union { 313 struct { 314 #ifdef __BIG_ENDIAN_BITFIELD 315 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 317 8:11 of IEEE ext */ 318 #else /* __LITTLE_ENDIAN_BITFIELD */ 319 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 320 8:11 of IEEE ext */ 321 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 322 #endif 323 324 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 325 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 326 #define NAME_FC_TYPE 0x3 /* FC native name type */ 327 #define NAME_IP_TYPE 0x4 /* IP address */ 328 #define NAME_CCITT_TYPE 0xC 329 #define NAME_CCITT_GR_TYPE 0xE 330 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 331 extended Lsb */ 332 uint8_t IEEE[6]; /* FC IEEE address */ 333 } s; 334 uint8_t wwn[8]; 335 } u; 336 }; 337 338 struct csp { 339 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 340 uint8_t fcphLow; 341 uint8_t bbCreditMsb; 342 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 343 344 #ifdef __BIG_ENDIAN_BITFIELD 345 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 346 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 347 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 348 uint16_t fPort:1; /* FC Word 1, bit 28 */ 349 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 350 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 351 uint16_t multicast:1; /* FC Word 1, bit 25 */ 352 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 353 354 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 355 uint16_t simplex:1; /* FC Word 1, bit 22 */ 356 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 357 uint16_t dhd:1; /* FC Word 1, bit 18 */ 358 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 359 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 360 #else /* __LITTLE_ENDIAN_BITFIELD */ 361 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 362 uint16_t multicast:1; /* FC Word 1, bit 25 */ 363 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 364 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 365 uint16_t fPort:1; /* FC Word 1, bit 28 */ 366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 367 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 368 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 369 370 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 371 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 372 uint16_t dhd:1; /* FC Word 1, bit 18 */ 373 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 374 uint16_t simplex:1; /* FC Word 1, bit 22 */ 375 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 376 #endif 377 378 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 379 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 380 union { 381 struct { 382 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 383 384 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 385 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 386 387 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 388 } nPort; 389 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 390 } w2; 391 392 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 393 }; 394 395 struct class_parms { 396 #ifdef __BIG_ENDIAN_BITFIELD 397 uint8_t classValid:1; /* FC Word 0, bit 31 */ 398 uint8_t intermix:1; /* FC Word 0, bit 30 */ 399 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 400 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 401 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 402 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 403 #else /* __LITTLE_ENDIAN_BITFIELD */ 404 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 405 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 406 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 407 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 408 uint8_t intermix:1; /* FC Word 0, bit 30 */ 409 uint8_t classValid:1; /* FC Word 0, bit 31 */ 410 411 #endif 412 413 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 414 415 #ifdef __BIG_ENDIAN_BITFIELD 416 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 417 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 418 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 419 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 420 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 421 #else /* __LITTLE_ENDIAN_BITFIELD */ 422 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 423 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 424 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 425 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 426 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 427 #endif 428 429 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 430 431 #ifdef __BIG_ENDIAN_BITFIELD 432 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 433 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 435 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 437 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 438 #else /* __LITTLE_ENDIAN_BITFIELD */ 439 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 440 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 441 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 442 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 443 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 444 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 445 #endif 446 447 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 448 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 449 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 450 451 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 452 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 453 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 454 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 455 456 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 457 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 458 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 459 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 460 }; 461 462 struct serv_parm { /* Structure is in Big Endian format */ 463 struct csp cmn; 464 struct lpfc_name portName; 465 struct lpfc_name nodeName; 466 struct class_parms cls1; 467 struct class_parms cls2; 468 struct class_parms cls3; 469 struct class_parms cls4; 470 uint8_t vendorVersion[16]; 471 }; 472 473 /* 474 * Virtual Fabric Tagging Header 475 */ 476 struct fc_vft_header { 477 uint32_t word0; 478 #define fc_vft_hdr_r_ctl_SHIFT 24 479 #define fc_vft_hdr_r_ctl_MASK 0xFF 480 #define fc_vft_hdr_r_ctl_WORD word0 481 #define fc_vft_hdr_ver_SHIFT 22 482 #define fc_vft_hdr_ver_MASK 0x3 483 #define fc_vft_hdr_ver_WORD word0 484 #define fc_vft_hdr_type_SHIFT 18 485 #define fc_vft_hdr_type_MASK 0xF 486 #define fc_vft_hdr_type_WORD word0 487 #define fc_vft_hdr_e_SHIFT 16 488 #define fc_vft_hdr_e_MASK 0x1 489 #define fc_vft_hdr_e_WORD word0 490 #define fc_vft_hdr_priority_SHIFT 13 491 #define fc_vft_hdr_priority_MASK 0x7 492 #define fc_vft_hdr_priority_WORD word0 493 #define fc_vft_hdr_vf_id_SHIFT 1 494 #define fc_vft_hdr_vf_id_MASK 0xFFF 495 #define fc_vft_hdr_vf_id_WORD word0 496 uint32_t word1; 497 #define fc_vft_hdr_hopct_SHIFT 24 498 #define fc_vft_hdr_hopct_MASK 0xFF 499 #define fc_vft_hdr_hopct_WORD word1 500 }; 501 502 /* 503 * Extended Link Service LS_COMMAND codes (Payload Word 0) 504 */ 505 #ifdef __BIG_ENDIAN_BITFIELD 506 #define ELS_CMD_MASK 0xffff0000 507 #define ELS_RSP_MASK 0xff000000 508 #define ELS_CMD_LS_RJT 0x01000000 509 #define ELS_CMD_ACC 0x02000000 510 #define ELS_CMD_PLOGI 0x03000000 511 #define ELS_CMD_FLOGI 0x04000000 512 #define ELS_CMD_LOGO 0x05000000 513 #define ELS_CMD_ABTX 0x06000000 514 #define ELS_CMD_RCS 0x07000000 515 #define ELS_CMD_RES 0x08000000 516 #define ELS_CMD_RSS 0x09000000 517 #define ELS_CMD_RSI 0x0A000000 518 #define ELS_CMD_ESTS 0x0B000000 519 #define ELS_CMD_ESTC 0x0C000000 520 #define ELS_CMD_ADVC 0x0D000000 521 #define ELS_CMD_RTV 0x0E000000 522 #define ELS_CMD_RLS 0x0F000000 523 #define ELS_CMD_ECHO 0x10000000 524 #define ELS_CMD_TEST 0x11000000 525 #define ELS_CMD_RRQ 0x12000000 526 #define ELS_CMD_PRLI 0x20100014 527 #define ELS_CMD_PRLO 0x21100014 528 #define ELS_CMD_PRLO_ACC 0x02100014 529 #define ELS_CMD_PDISC 0x50000000 530 #define ELS_CMD_FDISC 0x51000000 531 #define ELS_CMD_ADISC 0x52000000 532 #define ELS_CMD_FARP 0x54000000 533 #define ELS_CMD_FARPR 0x55000000 534 #define ELS_CMD_RPS 0x56000000 535 #define ELS_CMD_RPL 0x57000000 536 #define ELS_CMD_FAN 0x60000000 537 #define ELS_CMD_RSCN 0x61040000 538 #define ELS_CMD_SCR 0x62000000 539 #define ELS_CMD_RNID 0x78000000 540 #define ELS_CMD_LIRR 0x7A000000 541 #else /* __LITTLE_ENDIAN_BITFIELD */ 542 #define ELS_CMD_MASK 0xffff 543 #define ELS_RSP_MASK 0xff 544 #define ELS_CMD_LS_RJT 0x01 545 #define ELS_CMD_ACC 0x02 546 #define ELS_CMD_PLOGI 0x03 547 #define ELS_CMD_FLOGI 0x04 548 #define ELS_CMD_LOGO 0x05 549 #define ELS_CMD_ABTX 0x06 550 #define ELS_CMD_RCS 0x07 551 #define ELS_CMD_RES 0x08 552 #define ELS_CMD_RSS 0x09 553 #define ELS_CMD_RSI 0x0A 554 #define ELS_CMD_ESTS 0x0B 555 #define ELS_CMD_ESTC 0x0C 556 #define ELS_CMD_ADVC 0x0D 557 #define ELS_CMD_RTV 0x0E 558 #define ELS_CMD_RLS 0x0F 559 #define ELS_CMD_ECHO 0x10 560 #define ELS_CMD_TEST 0x11 561 #define ELS_CMD_RRQ 0x12 562 #define ELS_CMD_PRLI 0x14001020 563 #define ELS_CMD_PRLO 0x14001021 564 #define ELS_CMD_PRLO_ACC 0x14001002 565 #define ELS_CMD_PDISC 0x50 566 #define ELS_CMD_FDISC 0x51 567 #define ELS_CMD_ADISC 0x52 568 #define ELS_CMD_FARP 0x54 569 #define ELS_CMD_FARPR 0x55 570 #define ELS_CMD_RPS 0x56 571 #define ELS_CMD_RPL 0x57 572 #define ELS_CMD_FAN 0x60 573 #define ELS_CMD_RSCN 0x0461 574 #define ELS_CMD_SCR 0x62 575 #define ELS_CMD_RNID 0x78 576 #define ELS_CMD_LIRR 0x7A 577 #endif 578 579 /* 580 * LS_RJT Payload Definition 581 */ 582 583 struct ls_rjt { /* Structure is in Big Endian format */ 584 union { 585 uint32_t lsRjtError; 586 struct { 587 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 588 589 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 590 /* LS_RJT reason codes */ 591 #define LSRJT_INVALID_CMD 0x01 592 #define LSRJT_LOGICAL_ERR 0x03 593 #define LSRJT_LOGICAL_BSY 0x05 594 #define LSRJT_PROTOCOL_ERR 0x07 595 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 596 #define LSRJT_CMD_UNSUPPORTED 0x0B 597 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 598 599 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 600 /* LS_RJT reason explanation */ 601 #define LSEXP_NOTHING_MORE 0x00 602 #define LSEXP_SPARM_OPTIONS 0x01 603 #define LSEXP_SPARM_ICTL 0x03 604 #define LSEXP_SPARM_RCTL 0x05 605 #define LSEXP_SPARM_RCV_SIZE 0x07 606 #define LSEXP_SPARM_CONCUR_SEQ 0x09 607 #define LSEXP_SPARM_CREDIT 0x0B 608 #define LSEXP_INVALID_PNAME 0x0D 609 #define LSEXP_INVALID_NNAME 0x0E 610 #define LSEXP_INVALID_CSP 0x0F 611 #define LSEXP_INVALID_ASSOC_HDR 0x11 612 #define LSEXP_ASSOC_HDR_REQ 0x13 613 #define LSEXP_INVALID_O_SID 0x15 614 #define LSEXP_INVALID_OX_RX 0x17 615 #define LSEXP_CMD_IN_PROGRESS 0x19 616 #define LSEXP_PORT_LOGIN_REQ 0x1E 617 #define LSEXP_INVALID_NPORT_ID 0x1F 618 #define LSEXP_INVALID_SEQ_ID 0x21 619 #define LSEXP_INVALID_XCHG 0x23 620 #define LSEXP_INACTIVE_XCHG 0x25 621 #define LSEXP_RQ_REQUIRED 0x27 622 #define LSEXP_OUT_OF_RESOURCE 0x29 623 #define LSEXP_CANT_GIVE_DATA 0x2A 624 #define LSEXP_REQ_UNSUPPORTED 0x2C 625 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 626 } b; 627 } un; 628 }; 629 630 /* 631 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 632 */ 633 634 typedef struct _LOGO { /* Structure is in Big Endian format */ 635 union { 636 uint32_t nPortId32; /* Access nPortId as a word */ 637 struct { 638 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 639 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 640 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 641 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 642 } b; 643 } un; 644 struct lpfc_name portName; /* N_port name field */ 645 } LOGO; 646 647 /* 648 * FCP Login (PRLI Request / ACC) Payload Definition 649 */ 650 651 #define PRLX_PAGE_LEN 0x10 652 #define TPRLO_PAGE_LEN 0x14 653 654 typedef struct _PRLI { /* Structure is in Big Endian format */ 655 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 656 657 #define PRLI_FCP_TYPE 0x08 658 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 659 660 #ifdef __BIG_ENDIAN_BITFIELD 661 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 662 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 663 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 664 665 /* ACC = imagePairEstablished */ 666 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 667 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 668 #else /* __LITTLE_ENDIAN_BITFIELD */ 669 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 670 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 671 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 672 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 673 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 674 /* ACC = imagePairEstablished */ 675 #endif 676 677 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 678 #define PRLI_NO_RESOURCES 0x2 679 #define PRLI_INIT_INCOMPLETE 0x3 680 #define PRLI_NO_SUCH_PA 0x4 681 #define PRLI_PREDEF_CONFIG 0x5 682 #define PRLI_PARTIAL_SUCCESS 0x6 683 #define PRLI_INVALID_PAGE_CNT 0x7 684 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 685 686 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 687 688 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 689 690 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 691 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 692 693 #ifdef __BIG_ENDIAN_BITFIELD 694 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 695 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 696 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 697 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 698 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 699 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 700 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 701 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 702 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 703 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 704 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 705 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 706 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 707 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 708 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 709 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 710 #else /* __LITTLE_ENDIAN_BITFIELD */ 711 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 712 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 713 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 714 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 715 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 716 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 717 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 718 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 719 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 720 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 721 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 722 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 723 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 724 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 725 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 726 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 727 #endif 728 } PRLI; 729 730 /* 731 * FCP Logout (PRLO Request / ACC) Payload Definition 732 */ 733 734 typedef struct _PRLO { /* Structure is in Big Endian format */ 735 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 736 737 #define PRLO_FCP_TYPE 0x08 738 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 739 740 #ifdef __BIG_ENDIAN_BITFIELD 741 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 742 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 743 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 744 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 745 #else /* __LITTLE_ENDIAN_BITFIELD */ 746 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 747 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 748 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 749 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 750 #endif 751 752 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 753 #define PRLO_NO_SUCH_IMAGE 0x4 754 #define PRLO_INVALID_PAGE_CNT 0x7 755 756 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 757 758 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 759 760 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 761 762 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 763 } PRLO; 764 765 typedef struct _ADISC { /* Structure is in Big Endian format */ 766 uint32_t hardAL_PA; 767 struct lpfc_name portName; 768 struct lpfc_name nodeName; 769 uint32_t DID; 770 } ADISC; 771 772 typedef struct _FARP { /* Structure is in Big Endian format */ 773 uint32_t Mflags:8; 774 uint32_t Odid:24; 775 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 776 action */ 777 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 778 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 779 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 780 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 781 supported */ 782 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 783 supported */ 784 uint32_t Rflags:8; 785 uint32_t Rdid:24; 786 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 787 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 788 struct lpfc_name OportName; 789 struct lpfc_name OnodeName; 790 struct lpfc_name RportName; 791 struct lpfc_name RnodeName; 792 uint8_t Oipaddr[16]; 793 uint8_t Ripaddr[16]; 794 } FARP; 795 796 typedef struct _FAN { /* Structure is in Big Endian format */ 797 uint32_t Fdid; 798 struct lpfc_name FportName; 799 struct lpfc_name FnodeName; 800 } FAN; 801 802 typedef struct _SCR { /* Structure is in Big Endian format */ 803 uint8_t resvd1; 804 uint8_t resvd2; 805 uint8_t resvd3; 806 uint8_t Function; 807 #define SCR_FUNC_FABRIC 0x01 808 #define SCR_FUNC_NPORT 0x02 809 #define SCR_FUNC_FULL 0x03 810 #define SCR_CLEAR 0xff 811 } SCR; 812 813 typedef struct _RNID_TOP_DISC { 814 struct lpfc_name portName; 815 uint8_t resvd[8]; 816 uint32_t unitType; 817 #define RNID_HBA 0x7 818 #define RNID_HOST 0xa 819 #define RNID_DRIVER 0xd 820 uint32_t physPort; 821 uint32_t attachedNodes; 822 uint16_t ipVersion; 823 #define RNID_IPV4 0x1 824 #define RNID_IPV6 0x2 825 uint16_t UDPport; 826 uint8_t ipAddr[16]; 827 uint16_t resvd1; 828 uint16_t flags; 829 #define RNID_TD_SUPPORT 0x1 830 #define RNID_LP_VALID 0x2 831 } RNID_TOP_DISC; 832 833 typedef struct _RNID { /* Structure is in Big Endian format */ 834 uint8_t Format; 835 #define RNID_TOPOLOGY_DISC 0xdf 836 uint8_t CommonLen; 837 uint8_t resvd1; 838 uint8_t SpecificLen; 839 struct lpfc_name portName; 840 struct lpfc_name nodeName; 841 union { 842 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 843 } un; 844 } RNID; 845 846 typedef struct _RPS { /* Structure is in Big Endian format */ 847 union { 848 uint32_t portNum; 849 struct lpfc_name portName; 850 } un; 851 } RPS; 852 853 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 854 uint16_t rsvd1; 855 uint16_t portStatus; 856 uint32_t linkFailureCnt; 857 uint32_t lossSyncCnt; 858 uint32_t lossSignalCnt; 859 uint32_t primSeqErrCnt; 860 uint32_t invalidXmitWord; 861 uint32_t crcCnt; 862 } RPS_RSP; 863 864 struct RLS { /* Structure is in Big Endian format */ 865 uint32_t rls; 866 #define rls_rsvd_SHIFT 24 867 #define rls_rsvd_MASK 0x000000ff 868 #define rls_rsvd_WORD rls 869 #define rls_did_SHIFT 0 870 #define rls_did_MASK 0x00ffffff 871 #define rls_did_WORD rls 872 }; 873 874 struct RLS_RSP { /* Structure is in Big Endian format */ 875 uint32_t linkFailureCnt; 876 uint32_t lossSyncCnt; 877 uint32_t lossSignalCnt; 878 uint32_t primSeqErrCnt; 879 uint32_t invalidXmitWord; 880 uint32_t crcCnt; 881 }; 882 883 struct RTV_RSP { /* Structure is in Big Endian format */ 884 uint32_t ratov; 885 uint32_t edtov; 886 uint32_t qtov; 887 #define qtov_rsvd0_SHIFT 28 888 #define qtov_rsvd0_MASK 0x0000000f 889 #define qtov_rsvd0_WORD qtov /* reserved */ 890 #define qtov_edtovres_SHIFT 27 891 #define qtov_edtovres_MASK 0x00000001 892 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 893 #define qtov__rsvd1_SHIFT 19 894 #define qtov_rsvd1_MASK 0x0000003f 895 #define qtov_rsvd1_WORD qtov /* reserved */ 896 #define qtov_rttov_SHIFT 18 897 #define qtov_rttov_MASK 0x00000001 898 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 899 #define qtov_rsvd2_SHIFT 0 900 #define qtov_rsvd2_MASK 0x0003ffff 901 #define qtov_rsvd2_WORD qtov /* reserved */ 902 }; 903 904 905 typedef struct _RPL { /* Structure is in Big Endian format */ 906 uint32_t maxsize; 907 uint32_t index; 908 } RPL; 909 910 typedef struct _PORT_NUM_BLK { 911 uint32_t portNum; 912 uint32_t portID; 913 struct lpfc_name portName; 914 } PORT_NUM_BLK; 915 916 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 917 uint32_t listLen; 918 uint32_t index; 919 PORT_NUM_BLK port_num_blk; 920 } RPL_RSP; 921 922 /* This is used for RSCN command */ 923 typedef struct _D_ID { /* Structure is in Big Endian format */ 924 union { 925 uint32_t word; 926 struct { 927 #ifdef __BIG_ENDIAN_BITFIELD 928 uint8_t resv; 929 uint8_t domain; 930 uint8_t area; 931 uint8_t id; 932 #else /* __LITTLE_ENDIAN_BITFIELD */ 933 uint8_t id; 934 uint8_t area; 935 uint8_t domain; 936 uint8_t resv; 937 #endif 938 } b; 939 } un; 940 } D_ID; 941 942 #define RSCN_ADDRESS_FORMAT_PORT 0x0 943 #define RSCN_ADDRESS_FORMAT_AREA 0x1 944 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 945 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 946 #define RSCN_ADDRESS_FORMAT_MASK 0x3 947 948 /* 949 * Structure to define all ELS Payload types 950 */ 951 952 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 953 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 954 uint8_t elsByte1; 955 uint8_t elsByte2; 956 uint8_t elsByte3; 957 union { 958 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 959 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 960 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 961 PRLI prli; /* Payload for PRLI/ACC */ 962 PRLO prlo; /* Payload for PRLO/ACC */ 963 ADISC adisc; /* Payload for ADISC/ACC */ 964 FARP farp; /* Payload for FARP/ACC */ 965 FAN fan; /* Payload for FAN */ 966 SCR scr; /* Payload for SCR/ACC */ 967 RNID rnid; /* Payload for RNID */ 968 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 969 } un; 970 } ELS_PKT; 971 972 /* 973 * FDMI 974 * HBA MAnagement Operations Command Codes 975 */ 976 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 977 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 978 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 979 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 980 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 981 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 982 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 983 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 984 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 985 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 986 987 /* 988 * Management Service Subtypes 989 */ 990 #define SLI_CT_FDMI_Subtypes 0x10 991 992 /* 993 * HBA Management Service Reject Code 994 */ 995 #define REJECT_CODE 0x9 /* Unable to perform command request */ 996 997 /* 998 * HBA Management Service Reject Reason Code 999 * Please refer to the Reason Codes above 1000 */ 1001 1002 /* 1003 * HBA Attribute Types 1004 */ 1005 #define NODE_NAME 0x1 1006 #define MANUFACTURER 0x2 1007 #define SERIAL_NUMBER 0x3 1008 #define MODEL 0x4 1009 #define MODEL_DESCRIPTION 0x5 1010 #define HARDWARE_VERSION 0x6 1011 #define DRIVER_VERSION 0x7 1012 #define OPTION_ROM_VERSION 0x8 1013 #define FIRMWARE_VERSION 0x9 1014 #define OS_NAME_VERSION 0xa 1015 #define MAX_CT_PAYLOAD_LEN 0xb 1016 1017 /* 1018 * Port Attrubute Types 1019 */ 1020 #define SUPPORTED_FC4_TYPES 0x1 1021 #define SUPPORTED_SPEED 0x2 1022 #define PORT_SPEED 0x3 1023 #define MAX_FRAME_SIZE 0x4 1024 #define OS_DEVICE_NAME 0x5 1025 #define HOST_NAME 0x6 1026 1027 union AttributesDef { 1028 /* Structure is in Big Endian format */ 1029 struct { 1030 uint32_t AttrType:16; 1031 uint32_t AttrLen:16; 1032 } bits; 1033 uint32_t word; 1034 }; 1035 1036 1037 /* 1038 * HBA Attribute Entry (8 - 260 bytes) 1039 */ 1040 typedef struct { 1041 union AttributesDef ad; 1042 union { 1043 uint32_t VendorSpecific; 1044 uint8_t Manufacturer[64]; 1045 uint8_t SerialNumber[64]; 1046 uint8_t Model[256]; 1047 uint8_t ModelDescription[256]; 1048 uint8_t HardwareVersion[256]; 1049 uint8_t DriverVersion[256]; 1050 uint8_t OptionROMVersion[256]; 1051 uint8_t FirmwareVersion[256]; 1052 struct lpfc_name NodeName; 1053 uint8_t SupportFC4Types[32]; 1054 uint32_t SupportSpeed; 1055 uint32_t PortSpeed; 1056 uint32_t MaxFrameSize; 1057 uint8_t OsDeviceName[256]; 1058 uint8_t OsNameVersion[256]; 1059 uint32_t MaxCTPayloadLen; 1060 uint8_t HostName[256]; 1061 } un; 1062 } ATTRIBUTE_ENTRY; 1063 1064 /* 1065 * HBA Attribute Block 1066 */ 1067 typedef struct { 1068 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1069 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1070 } ATTRIBUTE_BLOCK; 1071 1072 /* 1073 * Port Entry 1074 */ 1075 typedef struct { 1076 struct lpfc_name PortName; 1077 } PORT_ENTRY; 1078 1079 /* 1080 * HBA Identifier 1081 */ 1082 typedef struct { 1083 struct lpfc_name PortName; 1084 } HBA_IDENTIFIER; 1085 1086 /* 1087 * Registered Port List Format 1088 */ 1089 typedef struct { 1090 uint32_t EntryCnt; 1091 PORT_ENTRY pe; /* Variable-length array */ 1092 } REG_PORT_LIST; 1093 1094 /* 1095 * Register HBA(RHBA) 1096 */ 1097 typedef struct { 1098 HBA_IDENTIFIER hi; 1099 REG_PORT_LIST rpl; /* variable-length array */ 1100 /* ATTRIBUTE_BLOCK ab; */ 1101 } REG_HBA; 1102 1103 /* 1104 * Register HBA Attributes (RHAT) 1105 */ 1106 typedef struct { 1107 struct lpfc_name HBA_PortName; 1108 ATTRIBUTE_BLOCK ab; 1109 } REG_HBA_ATTRIBUTE; 1110 1111 /* 1112 * Register Port Attributes (RPA) 1113 */ 1114 typedef struct { 1115 struct lpfc_name PortName; 1116 ATTRIBUTE_BLOCK ab; 1117 } REG_PORT_ATTRIBUTE; 1118 1119 /* 1120 * Get Registered HBA List (GRHL) Accept Payload Format 1121 */ 1122 typedef struct { 1123 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1124 struct lpfc_name HBA_PortName; /* Variable-length array */ 1125 } GRHL_ACC_PAYLOAD; 1126 1127 /* 1128 * Get Registered Port List (GRPL) Accept Payload Format 1129 */ 1130 typedef struct { 1131 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1132 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1133 } GRPL_ACC_PAYLOAD; 1134 1135 /* 1136 * Get Port Attributes (GPAT) Accept Payload Format 1137 */ 1138 1139 typedef struct { 1140 ATTRIBUTE_BLOCK pab; 1141 } GPAT_ACC_PAYLOAD; 1142 1143 1144 /* 1145 * Begin HBA configuration parameters. 1146 * The PCI configuration register BAR assignments are: 1147 * BAR0, offset 0x10 - SLIM base memory address 1148 * BAR1, offset 0x14 - SLIM base memory high address 1149 * BAR2, offset 0x18 - REGISTER base memory address 1150 * BAR3, offset 0x1c - REGISTER base memory high address 1151 * BAR4, offset 0x20 - BIU I/O registers 1152 * BAR5, offset 0x24 - REGISTER base io high address 1153 */ 1154 1155 /* Number of rings currently used and available. */ 1156 #define MAX_CONFIGURED_RINGS 3 1157 #define MAX_RINGS 4 1158 1159 /* IOCB / Mailbox is owned by FireFly */ 1160 #define OWN_CHIP 1 1161 1162 /* IOCB / Mailbox is owned by Host */ 1163 #define OWN_HOST 0 1164 1165 /* Number of 4-byte words in an IOCB. */ 1166 #define IOCB_WORD_SZ 8 1167 1168 /* network headers for Dfctl field */ 1169 #define FC_NET_HDR 0x20 1170 1171 /* Start FireFly Register definitions */ 1172 #define PCI_VENDOR_ID_EMULEX 0x10df 1173 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1174 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1175 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1176 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1177 #define PCI_DEVICE_ID_SAT_MID 0xf015 1178 #define PCI_DEVICE_ID_RFLY 0xf095 1179 #define PCI_DEVICE_ID_PFLY 0xf098 1180 #define PCI_DEVICE_ID_LP101 0xf0a1 1181 #define PCI_DEVICE_ID_TFLY 0xf0a5 1182 #define PCI_DEVICE_ID_BSMB 0xf0d1 1183 #define PCI_DEVICE_ID_BMID 0xf0d5 1184 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1185 #define PCI_DEVICE_ID_ZMID 0xf0e5 1186 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1187 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1188 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1189 #define PCI_DEVICE_ID_SAT 0xf100 1190 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1191 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1192 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1193 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1194 #define PCI_DEVICE_ID_CENTAUR 0xf900 1195 #define PCI_DEVICE_ID_PEGASUS 0xf980 1196 #define PCI_DEVICE_ID_THOR 0xfa00 1197 #define PCI_DEVICE_ID_VIPER 0xfb00 1198 #define PCI_DEVICE_ID_LP10000S 0xfc00 1199 #define PCI_DEVICE_ID_LP11000S 0xfc10 1200 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1201 #define PCI_DEVICE_ID_SAT_S 0xfc40 1202 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1203 #define PCI_DEVICE_ID_HELIOS 0xfd00 1204 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1205 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1206 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1207 #define PCI_DEVICE_ID_HORNET 0xfe05 1208 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1209 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1210 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1211 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1212 #define PCI_DEVICE_ID_TOMCAT 0x0714 1213 #define PCI_DEVICE_ID_FALCON 0xf180 1214 #define PCI_DEVICE_ID_BALIUS 0xe131 1215 1216 #define JEDEC_ID_ADDRESS 0x0080001c 1217 #define FIREFLY_JEDEC_ID 0x1ACC 1218 #define SUPERFLY_JEDEC_ID 0x0020 1219 #define DRAGONFLY_JEDEC_ID 0x0021 1220 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1221 #define CENTAUR_2G_JEDEC_ID 0x0026 1222 #define CENTAUR_1G_JEDEC_ID 0x0028 1223 #define PEGASUS_ORION_JEDEC_ID 0x0036 1224 #define PEGASUS_JEDEC_ID 0x0038 1225 #define THOR_JEDEC_ID 0x0012 1226 #define HELIOS_JEDEC_ID 0x0364 1227 #define ZEPHYR_JEDEC_ID 0x0577 1228 #define VIPER_JEDEC_ID 0x4838 1229 #define SATURN_JEDEC_ID 0x1004 1230 #define HORNET_JDEC_ID 0x2057706D 1231 1232 #define JEDEC_ID_MASK 0x0FFFF000 1233 #define JEDEC_ID_SHIFT 12 1234 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1235 1236 typedef struct { /* FireFly BIU registers */ 1237 uint32_t hostAtt; /* See definitions for Host Attention 1238 register */ 1239 uint32_t chipAtt; /* See definitions for Chip Attention 1240 register */ 1241 uint32_t hostStatus; /* See definitions for Host Status register */ 1242 uint32_t hostControl; /* See definitions for Host Control register */ 1243 uint32_t buiConfig; /* See definitions for BIU configuration 1244 register */ 1245 } FF_REGS; 1246 1247 /* IO Register size in bytes */ 1248 #define FF_REG_AREA_SIZE 256 1249 1250 /* Host Attention Register */ 1251 1252 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1253 1254 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1255 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1256 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1257 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1258 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1259 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1260 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1261 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1262 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1263 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1264 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1265 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1266 #define HA_LATT 0x20000000 /* Bit 29 */ 1267 #define HA_MBATT 0x40000000 /* Bit 30 */ 1268 #define HA_ERATT 0x80000000 /* Bit 31 */ 1269 1270 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1271 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1272 #define HA_RXATT 0x00000008 /* Bit 3 */ 1273 #define HA_RXMASK 0x0000000f 1274 1275 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1276 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1277 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1278 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1279 1280 #define HA_R0_POS 3 1281 #define HA_R1_POS 7 1282 #define HA_R2_POS 11 1283 #define HA_R3_POS 15 1284 #define HA_LE_POS 29 1285 #define HA_MB_POS 30 1286 #define HA_ER_POS 31 1287 /* Chip Attention Register */ 1288 1289 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1290 1291 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1292 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1293 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1294 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1295 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1296 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1297 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1298 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1299 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1300 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1301 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1302 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1303 #define CA_MBATT 0x40000000 /* Bit 30 */ 1304 1305 /* Host Status Register */ 1306 1307 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1308 1309 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1310 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1311 #define HS_FFER8 0x01000000 /* Bit 24 */ 1312 #define HS_FFER7 0x02000000 /* Bit 25 */ 1313 #define HS_FFER6 0x04000000 /* Bit 26 */ 1314 #define HS_FFER5 0x08000000 /* Bit 27 */ 1315 #define HS_FFER4 0x10000000 /* Bit 28 */ 1316 #define HS_FFER3 0x20000000 /* Bit 29 */ 1317 #define HS_FFER2 0x40000000 /* Bit 30 */ 1318 #define HS_FFER1 0x80000000 /* Bit 31 */ 1319 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1320 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1321 1322 /* Host Control Register */ 1323 1324 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1325 1326 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1327 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1328 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1329 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1330 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1331 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1332 #define HC_INITMB 0x04000000 /* Bit 26 */ 1333 #define HC_INITFF 0x08000000 /* Bit 27 */ 1334 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1335 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1336 1337 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1338 #define MSIX_DFLT_ID 0 1339 #define MSIX_RNG0_ID 0 1340 #define MSIX_RNG1_ID 1 1341 #define MSIX_RNG2_ID 2 1342 #define MSIX_RNG3_ID 3 1343 1344 #define MSIX_LINK_ID 4 1345 #define MSIX_MBOX_ID 5 1346 1347 #define MSIX_SPARE0_ID 6 1348 #define MSIX_SPARE1_ID 7 1349 1350 /* Mailbox Commands */ 1351 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1352 #define MBX_LOAD_SM 0x01 1353 #define MBX_READ_NV 0x02 1354 #define MBX_WRITE_NV 0x03 1355 #define MBX_RUN_BIU_DIAG 0x04 1356 #define MBX_INIT_LINK 0x05 1357 #define MBX_DOWN_LINK 0x06 1358 #define MBX_CONFIG_LINK 0x07 1359 #define MBX_CONFIG_RING 0x09 1360 #define MBX_RESET_RING 0x0A 1361 #define MBX_READ_CONFIG 0x0B 1362 #define MBX_READ_RCONFIG 0x0C 1363 #define MBX_READ_SPARM 0x0D 1364 #define MBX_READ_STATUS 0x0E 1365 #define MBX_READ_RPI 0x0F 1366 #define MBX_READ_XRI 0x10 1367 #define MBX_READ_REV 0x11 1368 #define MBX_READ_LNK_STAT 0x12 1369 #define MBX_REG_LOGIN 0x13 1370 #define MBX_UNREG_LOGIN 0x14 1371 #define MBX_READ_LA 0x15 1372 #define MBX_CLEAR_LA 0x16 1373 #define MBX_DUMP_MEMORY 0x17 1374 #define MBX_DUMP_CONTEXT 0x18 1375 #define MBX_RUN_DIAGS 0x19 1376 #define MBX_RESTART 0x1A 1377 #define MBX_UPDATE_CFG 0x1B 1378 #define MBX_DOWN_LOAD 0x1C 1379 #define MBX_DEL_LD_ENTRY 0x1D 1380 #define MBX_RUN_PROGRAM 0x1E 1381 #define MBX_SET_MASK 0x20 1382 #define MBX_SET_VARIABLE 0x21 1383 #define MBX_UNREG_D_ID 0x23 1384 #define MBX_KILL_BOARD 0x24 1385 #define MBX_CONFIG_FARP 0x25 1386 #define MBX_BEACON 0x2A 1387 #define MBX_CONFIG_MSI 0x30 1388 #define MBX_HEARTBEAT 0x31 1389 #define MBX_WRITE_VPARMS 0x32 1390 #define MBX_ASYNCEVT_ENABLE 0x33 1391 #define MBX_READ_EVENT_LOG_STATUS 0x37 1392 #define MBX_READ_EVENT_LOG 0x38 1393 #define MBX_WRITE_EVENT_LOG 0x39 1394 1395 #define MBX_PORT_CAPABILITIES 0x3B 1396 #define MBX_PORT_IOV_CONTROL 0x3C 1397 1398 #define MBX_CONFIG_HBQ 0x7C 1399 #define MBX_LOAD_AREA 0x81 1400 #define MBX_RUN_BIU_DIAG64 0x84 1401 #define MBX_CONFIG_PORT 0x88 1402 #define MBX_READ_SPARM64 0x8D 1403 #define MBX_READ_RPI64 0x8F 1404 #define MBX_REG_LOGIN64 0x93 1405 #define MBX_READ_LA64 0x95 1406 #define MBX_REG_VPI 0x96 1407 #define MBX_UNREG_VPI 0x97 1408 1409 #define MBX_WRITE_WWN 0x98 1410 #define MBX_SET_DEBUG 0x99 1411 #define MBX_LOAD_EXP_ROM 0x9C 1412 #define MBX_SLI4_CONFIG 0x9B 1413 #define MBX_SLI4_REQ_FTRS 0x9D 1414 #define MBX_MAX_CMDS 0x9E 1415 #define MBX_RESUME_RPI 0x9E 1416 #define MBX_SLI2_CMD_MASK 0x80 1417 #define MBX_REG_VFI 0x9F 1418 #define MBX_REG_FCFI 0xA0 1419 #define MBX_UNREG_VFI 0xA1 1420 #define MBX_UNREG_FCFI 0xA2 1421 #define MBX_INIT_VFI 0xA3 1422 #define MBX_INIT_VPI 0xA4 1423 1424 #define MBX_AUTH_PORT 0xF8 1425 #define MBX_SECURITY_MGMT 0xF9 1426 1427 /* IOCB Commands */ 1428 1429 #define CMD_RCV_SEQUENCE_CX 0x01 1430 #define CMD_XMIT_SEQUENCE_CR 0x02 1431 #define CMD_XMIT_SEQUENCE_CX 0x03 1432 #define CMD_XMIT_BCAST_CN 0x04 1433 #define CMD_XMIT_BCAST_CX 0x05 1434 #define CMD_QUE_RING_BUF_CN 0x06 1435 #define CMD_QUE_XRI_BUF_CX 0x07 1436 #define CMD_IOCB_CONTINUE_CN 0x08 1437 #define CMD_RET_XRI_BUF_CX 0x09 1438 #define CMD_ELS_REQUEST_CR 0x0A 1439 #define CMD_ELS_REQUEST_CX 0x0B 1440 #define CMD_RCV_ELS_REQ_CX 0x0D 1441 #define CMD_ABORT_XRI_CN 0x0E 1442 #define CMD_ABORT_XRI_CX 0x0F 1443 #define CMD_CLOSE_XRI_CN 0x10 1444 #define CMD_CLOSE_XRI_CX 0x11 1445 #define CMD_CREATE_XRI_CR 0x12 1446 #define CMD_CREATE_XRI_CX 0x13 1447 #define CMD_GET_RPI_CN 0x14 1448 #define CMD_XMIT_ELS_RSP_CX 0x15 1449 #define CMD_GET_RPI_CR 0x16 1450 #define CMD_XRI_ABORTED_CX 0x17 1451 #define CMD_FCP_IWRITE_CR 0x18 1452 #define CMD_FCP_IWRITE_CX 0x19 1453 #define CMD_FCP_IREAD_CR 0x1A 1454 #define CMD_FCP_IREAD_CX 0x1B 1455 #define CMD_FCP_ICMND_CR 0x1C 1456 #define CMD_FCP_ICMND_CX 0x1D 1457 #define CMD_FCP_TSEND_CX 0x1F 1458 #define CMD_FCP_TRECEIVE_CX 0x21 1459 #define CMD_FCP_TRSP_CX 0x23 1460 #define CMD_FCP_AUTO_TRSP_CX 0x29 1461 1462 #define CMD_ADAPTER_MSG 0x20 1463 #define CMD_ADAPTER_DUMP 0x22 1464 1465 /* SLI_2 IOCB Command Set */ 1466 1467 #define CMD_ASYNC_STATUS 0x7C 1468 #define CMD_RCV_SEQUENCE64_CX 0x81 1469 #define CMD_XMIT_SEQUENCE64_CR 0x82 1470 #define CMD_XMIT_SEQUENCE64_CX 0x83 1471 #define CMD_XMIT_BCAST64_CN 0x84 1472 #define CMD_XMIT_BCAST64_CX 0x85 1473 #define CMD_QUE_RING_BUF64_CN 0x86 1474 #define CMD_QUE_XRI_BUF64_CX 0x87 1475 #define CMD_IOCB_CONTINUE64_CN 0x88 1476 #define CMD_RET_XRI_BUF64_CX 0x89 1477 #define CMD_ELS_REQUEST64_CR 0x8A 1478 #define CMD_ELS_REQUEST64_CX 0x8B 1479 #define CMD_ABORT_MXRI64_CN 0x8C 1480 #define CMD_RCV_ELS_REQ64_CX 0x8D 1481 #define CMD_XMIT_ELS_RSP64_CX 0x95 1482 #define CMD_XMIT_BLS_RSP64_CX 0x97 1483 #define CMD_FCP_IWRITE64_CR 0x98 1484 #define CMD_FCP_IWRITE64_CX 0x99 1485 #define CMD_FCP_IREAD64_CR 0x9A 1486 #define CMD_FCP_IREAD64_CX 0x9B 1487 #define CMD_FCP_ICMND64_CR 0x9C 1488 #define CMD_FCP_ICMND64_CX 0x9D 1489 #define CMD_FCP_TSEND64_CX 0x9F 1490 #define CMD_FCP_TRECEIVE64_CX 0xA1 1491 #define CMD_FCP_TRSP64_CX 0xA3 1492 1493 #define CMD_QUE_XRI64_CX 0xB3 1494 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1495 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1496 #define CMD_IOCB_RET_XRI64_CX 0xB9 1497 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1498 1499 #define CMD_GEN_REQUEST64_CR 0xC2 1500 #define CMD_GEN_REQUEST64_CX 0xC3 1501 1502 /* Unhandled SLI-3 Commands */ 1503 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1504 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1505 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1506 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1507 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1508 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1509 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1510 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1511 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1512 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1513 #define CMD_IOCB_LOGENTRY_CN 0x94 1514 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1515 1516 /* Data Security SLI Commands */ 1517 #define DSSCMD_IWRITE64_CR 0xF8 1518 #define DSSCMD_IWRITE64_CX 0xF9 1519 #define DSSCMD_IREAD64_CR 0xFA 1520 #define DSSCMD_IREAD64_CX 0xFB 1521 1522 #define CMD_MAX_IOCB_CMD 0xFB 1523 #define CMD_IOCB_MASK 0xff 1524 1525 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1526 iocb */ 1527 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1528 /* 1529 * Define Status 1530 */ 1531 #define MBX_SUCCESS 0 1532 #define MBXERR_NUM_RINGS 1 1533 #define MBXERR_NUM_IOCBS 2 1534 #define MBXERR_IOCBS_EXCEEDED 3 1535 #define MBXERR_BAD_RING_NUMBER 4 1536 #define MBXERR_MASK_ENTRIES_RANGE 5 1537 #define MBXERR_MASKS_EXCEEDED 6 1538 #define MBXERR_BAD_PROFILE 7 1539 #define MBXERR_BAD_DEF_CLASS 8 1540 #define MBXERR_BAD_MAX_RESPONDER 9 1541 #define MBXERR_BAD_MAX_ORIGINATOR 10 1542 #define MBXERR_RPI_REGISTERED 11 1543 #define MBXERR_RPI_FULL 12 1544 #define MBXERR_NO_RESOURCES 13 1545 #define MBXERR_BAD_RCV_LENGTH 14 1546 #define MBXERR_DMA_ERROR 15 1547 #define MBXERR_ERROR 16 1548 #define MBXERR_LINK_DOWN 0x33 1549 #define MBXERR_SEC_NO_PERMISSION 0xF02 1550 #define MBX_NOT_FINISHED 255 1551 1552 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1553 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1554 1555 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1556 1557 /* 1558 * Begin Structure Definitions for Mailbox Commands 1559 */ 1560 1561 typedef struct { 1562 #ifdef __BIG_ENDIAN_BITFIELD 1563 uint8_t tval; 1564 uint8_t tmask; 1565 uint8_t rval; 1566 uint8_t rmask; 1567 #else /* __LITTLE_ENDIAN_BITFIELD */ 1568 uint8_t rmask; 1569 uint8_t rval; 1570 uint8_t tmask; 1571 uint8_t tval; 1572 #endif 1573 } RR_REG; 1574 1575 struct ulp_bde { 1576 uint32_t bdeAddress; 1577 #ifdef __BIG_ENDIAN_BITFIELD 1578 uint32_t bdeReserved:4; 1579 uint32_t bdeAddrHigh:4; 1580 uint32_t bdeSize:24; 1581 #else /* __LITTLE_ENDIAN_BITFIELD */ 1582 uint32_t bdeSize:24; 1583 uint32_t bdeAddrHigh:4; 1584 uint32_t bdeReserved:4; 1585 #endif 1586 }; 1587 1588 typedef struct ULP_BDL { /* SLI-2 */ 1589 #ifdef __BIG_ENDIAN_BITFIELD 1590 uint32_t bdeFlags:8; /* BDL Flags */ 1591 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1592 #else /* __LITTLE_ENDIAN_BITFIELD */ 1593 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1594 uint32_t bdeFlags:8; /* BDL Flags */ 1595 #endif 1596 1597 uint32_t addrLow; /* Address 0:31 */ 1598 uint32_t addrHigh; /* Address 32:63 */ 1599 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1600 } ULP_BDL; 1601 1602 /* 1603 * BlockGuard Definitions 1604 */ 1605 1606 enum lpfc_protgrp_type { 1607 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1608 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1609 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1610 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1611 }; 1612 1613 /* PDE Descriptors */ 1614 #define LPFC_PDE5_DESCRIPTOR 0x85 1615 #define LPFC_PDE6_DESCRIPTOR 0x86 1616 #define LPFC_PDE7_DESCRIPTOR 0x87 1617 1618 /* BlockGuard Opcodes */ 1619 #define BG_OP_IN_NODIF_OUT_CRC 0x0 1620 #define BG_OP_IN_CRC_OUT_NODIF 0x1 1621 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 1622 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 1623 #define BG_OP_IN_CRC_OUT_CRC 0x4 1624 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 1625 #define BG_OP_IN_CRC_OUT_CSUM 0x6 1626 #define BG_OP_IN_CSUM_OUT_CRC 0x7 1627 1628 struct lpfc_pde5 { 1629 uint32_t word0; 1630 #define pde5_type_SHIFT 24 1631 #define pde5_type_MASK 0x000000ff 1632 #define pde5_type_WORD word0 1633 #define pde5_rsvd0_SHIFT 0 1634 #define pde5_rsvd0_MASK 0x00ffffff 1635 #define pde5_rsvd0_WORD word0 1636 uint32_t reftag; /* Reference Tag Value */ 1637 uint32_t reftagtr; /* Reference Tag Translation Value */ 1638 }; 1639 1640 struct lpfc_pde6 { 1641 uint32_t word0; 1642 #define pde6_type_SHIFT 24 1643 #define pde6_type_MASK 0x000000ff 1644 #define pde6_type_WORD word0 1645 #define pde6_rsvd0_SHIFT 0 1646 #define pde6_rsvd0_MASK 0x00ffffff 1647 #define pde6_rsvd0_WORD word0 1648 uint32_t word1; 1649 #define pde6_rsvd1_SHIFT 26 1650 #define pde6_rsvd1_MASK 0x0000003f 1651 #define pde6_rsvd1_WORD word1 1652 #define pde6_na_SHIFT 25 1653 #define pde6_na_MASK 0x00000001 1654 #define pde6_na_WORD word1 1655 #define pde6_rsvd2_SHIFT 16 1656 #define pde6_rsvd2_MASK 0x000001FF 1657 #define pde6_rsvd2_WORD word1 1658 #define pde6_apptagtr_SHIFT 0 1659 #define pde6_apptagtr_MASK 0x0000ffff 1660 #define pde6_apptagtr_WORD word1 1661 uint32_t word2; 1662 #define pde6_optx_SHIFT 28 1663 #define pde6_optx_MASK 0x0000000f 1664 #define pde6_optx_WORD word2 1665 #define pde6_oprx_SHIFT 24 1666 #define pde6_oprx_MASK 0x0000000f 1667 #define pde6_oprx_WORD word2 1668 #define pde6_nr_SHIFT 23 1669 #define pde6_nr_MASK 0x00000001 1670 #define pde6_nr_WORD word2 1671 #define pde6_ce_SHIFT 22 1672 #define pde6_ce_MASK 0x00000001 1673 #define pde6_ce_WORD word2 1674 #define pde6_re_SHIFT 21 1675 #define pde6_re_MASK 0x00000001 1676 #define pde6_re_WORD word2 1677 #define pde6_ae_SHIFT 20 1678 #define pde6_ae_MASK 0x00000001 1679 #define pde6_ae_WORD word2 1680 #define pde6_ai_SHIFT 19 1681 #define pde6_ai_MASK 0x00000001 1682 #define pde6_ai_WORD word2 1683 #define pde6_bs_SHIFT 16 1684 #define pde6_bs_MASK 0x00000007 1685 #define pde6_bs_WORD word2 1686 #define pde6_apptagval_SHIFT 0 1687 #define pde6_apptagval_MASK 0x0000ffff 1688 #define pde6_apptagval_WORD word2 1689 }; 1690 1691 1692 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1693 1694 typedef struct { 1695 #ifdef __BIG_ENDIAN_BITFIELD 1696 uint32_t rsvd2:25; 1697 uint32_t acknowledgment:1; 1698 uint32_t version:1; 1699 uint32_t erase_or_prog:1; 1700 uint32_t update_flash:1; 1701 uint32_t update_ram:1; 1702 uint32_t method:1; 1703 uint32_t load_cmplt:1; 1704 #else /* __LITTLE_ENDIAN_BITFIELD */ 1705 uint32_t load_cmplt:1; 1706 uint32_t method:1; 1707 uint32_t update_ram:1; 1708 uint32_t update_flash:1; 1709 uint32_t erase_or_prog:1; 1710 uint32_t version:1; 1711 uint32_t acknowledgment:1; 1712 uint32_t rsvd2:25; 1713 #endif 1714 1715 uint32_t dl_to_adr_low; 1716 uint32_t dl_to_adr_high; 1717 uint32_t dl_len; 1718 union { 1719 uint32_t dl_from_mbx_offset; 1720 struct ulp_bde dl_from_bde; 1721 struct ulp_bde64 dl_from_bde64; 1722 } un; 1723 1724 } LOAD_SM_VAR; 1725 1726 /* Structure for MB Command READ_NVPARM (02) */ 1727 1728 typedef struct { 1729 uint32_t rsvd1[3]; /* Read as all one's */ 1730 uint32_t rsvd2; /* Read as all zero's */ 1731 uint32_t portname[2]; /* N_PORT name */ 1732 uint32_t nodename[2]; /* NODE name */ 1733 1734 #ifdef __BIG_ENDIAN_BITFIELD 1735 uint32_t pref_DID:24; 1736 uint32_t hardAL_PA:8; 1737 #else /* __LITTLE_ENDIAN_BITFIELD */ 1738 uint32_t hardAL_PA:8; 1739 uint32_t pref_DID:24; 1740 #endif 1741 1742 uint32_t rsvd3[21]; /* Read as all one's */ 1743 } READ_NV_VAR; 1744 1745 /* Structure for MB Command WRITE_NVPARMS (03) */ 1746 1747 typedef struct { 1748 uint32_t rsvd1[3]; /* Must be all one's */ 1749 uint32_t rsvd2; /* Must be all zero's */ 1750 uint32_t portname[2]; /* N_PORT name */ 1751 uint32_t nodename[2]; /* NODE name */ 1752 1753 #ifdef __BIG_ENDIAN_BITFIELD 1754 uint32_t pref_DID:24; 1755 uint32_t hardAL_PA:8; 1756 #else /* __LITTLE_ENDIAN_BITFIELD */ 1757 uint32_t hardAL_PA:8; 1758 uint32_t pref_DID:24; 1759 #endif 1760 1761 uint32_t rsvd3[21]; /* Must be all one's */ 1762 } WRITE_NV_VAR; 1763 1764 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1765 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1766 1767 typedef struct { 1768 uint32_t rsvd1; 1769 union { 1770 struct { 1771 struct ulp_bde xmit_bde; 1772 struct ulp_bde rcv_bde; 1773 } s1; 1774 struct { 1775 struct ulp_bde64 xmit_bde64; 1776 struct ulp_bde64 rcv_bde64; 1777 } s2; 1778 } un; 1779 } BIU_DIAG_VAR; 1780 1781 /* Structure for MB command READ_EVENT_LOG (0x38) */ 1782 struct READ_EVENT_LOG_VAR { 1783 uint32_t word1; 1784 #define lpfc_event_log_SHIFT 29 1785 #define lpfc_event_log_MASK 0x00000001 1786 #define lpfc_event_log_WORD word1 1787 #define USE_MAILBOX_RESPONSE 1 1788 uint32_t offset; 1789 struct ulp_bde64 rcv_bde64; 1790 }; 1791 1792 /* Structure for MB Command INIT_LINK (05) */ 1793 1794 typedef struct { 1795 #ifdef __BIG_ENDIAN_BITFIELD 1796 uint32_t rsvd1:24; 1797 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1798 #else /* __LITTLE_ENDIAN_BITFIELD */ 1799 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1800 uint32_t rsvd1:24; 1801 #endif 1802 1803 #ifdef __BIG_ENDIAN_BITFIELD 1804 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1805 uint8_t rsvd2; 1806 uint16_t link_flags; 1807 #else /* __LITTLE_ENDIAN_BITFIELD */ 1808 uint16_t link_flags; 1809 uint8_t rsvd2; 1810 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1811 #endif 1812 1813 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1814 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1815 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1816 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1817 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1818 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1819 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1820 1821 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1822 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1823 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1824 1825 uint32_t link_speed; 1826 #define LINK_SPEED_AUTO 0 /* Auto selection */ 1827 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1828 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1829 #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1830 #define LINK_SPEED_8G 8 /* 8 Gigabaud */ 1831 #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1832 1833 } INIT_LINK_VAR; 1834 1835 /* Structure for MB Command DOWN_LINK (06) */ 1836 1837 typedef struct { 1838 uint32_t rsvd1; 1839 } DOWN_LINK_VAR; 1840 1841 /* Structure for MB Command CONFIG_LINK (07) */ 1842 1843 typedef struct { 1844 #ifdef __BIG_ENDIAN_BITFIELD 1845 uint32_t cr:1; 1846 uint32_t ci:1; 1847 uint32_t cr_delay:6; 1848 uint32_t cr_count:8; 1849 uint32_t rsvd1:8; 1850 uint32_t MaxBBC:8; 1851 #else /* __LITTLE_ENDIAN_BITFIELD */ 1852 uint32_t MaxBBC:8; 1853 uint32_t rsvd1:8; 1854 uint32_t cr_count:8; 1855 uint32_t cr_delay:6; 1856 uint32_t ci:1; 1857 uint32_t cr:1; 1858 #endif 1859 1860 uint32_t myId; 1861 uint32_t rsvd2; 1862 uint32_t edtov; 1863 uint32_t arbtov; 1864 uint32_t ratov; 1865 uint32_t rttov; 1866 uint32_t altov; 1867 uint32_t crtov; 1868 uint32_t citov; 1869 #ifdef __BIG_ENDIAN_BITFIELD 1870 uint32_t rrq_enable:1; 1871 uint32_t rrq_immed:1; 1872 uint32_t rsvd4:29; 1873 uint32_t ack0_enable:1; 1874 #else /* __LITTLE_ENDIAN_BITFIELD */ 1875 uint32_t ack0_enable:1; 1876 uint32_t rsvd4:29; 1877 uint32_t rrq_immed:1; 1878 uint32_t rrq_enable:1; 1879 #endif 1880 } CONFIG_LINK; 1881 1882 /* Structure for MB Command PART_SLIM (08) 1883 * will be removed since SLI1 is no longer supported! 1884 */ 1885 typedef struct { 1886 #ifdef __BIG_ENDIAN_BITFIELD 1887 uint16_t offCiocb; 1888 uint16_t numCiocb; 1889 uint16_t offRiocb; 1890 uint16_t numRiocb; 1891 #else /* __LITTLE_ENDIAN_BITFIELD */ 1892 uint16_t numCiocb; 1893 uint16_t offCiocb; 1894 uint16_t numRiocb; 1895 uint16_t offRiocb; 1896 #endif 1897 } RING_DEF; 1898 1899 typedef struct { 1900 #ifdef __BIG_ENDIAN_BITFIELD 1901 uint32_t unused1:24; 1902 uint32_t numRing:8; 1903 #else /* __LITTLE_ENDIAN_BITFIELD */ 1904 uint32_t numRing:8; 1905 uint32_t unused1:24; 1906 #endif 1907 1908 RING_DEF ringdef[4]; 1909 uint32_t hbainit; 1910 } PART_SLIM_VAR; 1911 1912 /* Structure for MB Command CONFIG_RING (09) */ 1913 1914 typedef struct { 1915 #ifdef __BIG_ENDIAN_BITFIELD 1916 uint32_t unused2:6; 1917 uint32_t recvSeq:1; 1918 uint32_t recvNotify:1; 1919 uint32_t numMask:8; 1920 uint32_t profile:8; 1921 uint32_t unused1:4; 1922 uint32_t ring:4; 1923 #else /* __LITTLE_ENDIAN_BITFIELD */ 1924 uint32_t ring:4; 1925 uint32_t unused1:4; 1926 uint32_t profile:8; 1927 uint32_t numMask:8; 1928 uint32_t recvNotify:1; 1929 uint32_t recvSeq:1; 1930 uint32_t unused2:6; 1931 #endif 1932 1933 #ifdef __BIG_ENDIAN_BITFIELD 1934 uint16_t maxRespXchg; 1935 uint16_t maxOrigXchg; 1936 #else /* __LITTLE_ENDIAN_BITFIELD */ 1937 uint16_t maxOrigXchg; 1938 uint16_t maxRespXchg; 1939 #endif 1940 1941 RR_REG rrRegs[6]; 1942 } CONFIG_RING_VAR; 1943 1944 /* Structure for MB Command RESET_RING (10) */ 1945 1946 typedef struct { 1947 uint32_t ring_no; 1948 } RESET_RING_VAR; 1949 1950 /* Structure for MB Command READ_CONFIG (11) */ 1951 1952 typedef struct { 1953 #ifdef __BIG_ENDIAN_BITFIELD 1954 uint32_t cr:1; 1955 uint32_t ci:1; 1956 uint32_t cr_delay:6; 1957 uint32_t cr_count:8; 1958 uint32_t InitBBC:8; 1959 uint32_t MaxBBC:8; 1960 #else /* __LITTLE_ENDIAN_BITFIELD */ 1961 uint32_t MaxBBC:8; 1962 uint32_t InitBBC:8; 1963 uint32_t cr_count:8; 1964 uint32_t cr_delay:6; 1965 uint32_t ci:1; 1966 uint32_t cr:1; 1967 #endif 1968 1969 #ifdef __BIG_ENDIAN_BITFIELD 1970 uint32_t topology:8; 1971 uint32_t myDid:24; 1972 #else /* __LITTLE_ENDIAN_BITFIELD */ 1973 uint32_t myDid:24; 1974 uint32_t topology:8; 1975 #endif 1976 1977 /* Defines for topology (defined previously) */ 1978 #ifdef __BIG_ENDIAN_BITFIELD 1979 uint32_t AR:1; 1980 uint32_t IR:1; 1981 uint32_t rsvd1:29; 1982 uint32_t ack0:1; 1983 #else /* __LITTLE_ENDIAN_BITFIELD */ 1984 uint32_t ack0:1; 1985 uint32_t rsvd1:29; 1986 uint32_t IR:1; 1987 uint32_t AR:1; 1988 #endif 1989 1990 uint32_t edtov; 1991 uint32_t arbtov; 1992 uint32_t ratov; 1993 uint32_t rttov; 1994 uint32_t altov; 1995 uint32_t lmt; 1996 #define LMT_RESERVED 0x000 /* Not used */ 1997 #define LMT_1Gb 0x004 1998 #define LMT_2Gb 0x008 1999 #define LMT_4Gb 0x040 2000 #define LMT_8Gb 0x080 2001 #define LMT_10Gb 0x100 2002 uint32_t rsvd2; 2003 uint32_t rsvd3; 2004 uint32_t max_xri; 2005 uint32_t max_iocb; 2006 uint32_t max_rpi; 2007 uint32_t avail_xri; 2008 uint32_t avail_iocb; 2009 uint32_t avail_rpi; 2010 uint32_t max_vpi; 2011 uint32_t rsvd4; 2012 uint32_t rsvd5; 2013 uint32_t avail_vpi; 2014 } READ_CONFIG_VAR; 2015 2016 /* Structure for MB Command READ_RCONFIG (12) */ 2017 2018 typedef struct { 2019 #ifdef __BIG_ENDIAN_BITFIELD 2020 uint32_t rsvd2:7; 2021 uint32_t recvNotify:1; 2022 uint32_t numMask:8; 2023 uint32_t profile:8; 2024 uint32_t rsvd1:4; 2025 uint32_t ring:4; 2026 #else /* __LITTLE_ENDIAN_BITFIELD */ 2027 uint32_t ring:4; 2028 uint32_t rsvd1:4; 2029 uint32_t profile:8; 2030 uint32_t numMask:8; 2031 uint32_t recvNotify:1; 2032 uint32_t rsvd2:7; 2033 #endif 2034 2035 #ifdef __BIG_ENDIAN_BITFIELD 2036 uint16_t maxResp; 2037 uint16_t maxOrig; 2038 #else /* __LITTLE_ENDIAN_BITFIELD */ 2039 uint16_t maxOrig; 2040 uint16_t maxResp; 2041 #endif 2042 2043 RR_REG rrRegs[6]; 2044 2045 #ifdef __BIG_ENDIAN_BITFIELD 2046 uint16_t cmdRingOffset; 2047 uint16_t cmdEntryCnt; 2048 uint16_t rspRingOffset; 2049 uint16_t rspEntryCnt; 2050 uint16_t nextCmdOffset; 2051 uint16_t rsvd3; 2052 uint16_t nextRspOffset; 2053 uint16_t rsvd4; 2054 #else /* __LITTLE_ENDIAN_BITFIELD */ 2055 uint16_t cmdEntryCnt; 2056 uint16_t cmdRingOffset; 2057 uint16_t rspEntryCnt; 2058 uint16_t rspRingOffset; 2059 uint16_t rsvd3; 2060 uint16_t nextCmdOffset; 2061 uint16_t rsvd4; 2062 uint16_t nextRspOffset; 2063 #endif 2064 } READ_RCONF_VAR; 2065 2066 /* Structure for MB Command READ_SPARM (13) */ 2067 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2068 2069 typedef struct { 2070 uint32_t rsvd1; 2071 uint32_t rsvd2; 2072 union { 2073 struct ulp_bde sp; /* This BDE points to struct serv_parm 2074 structure */ 2075 struct ulp_bde64 sp64; 2076 } un; 2077 #ifdef __BIG_ENDIAN_BITFIELD 2078 uint16_t rsvd3; 2079 uint16_t vpi; 2080 #else /* __LITTLE_ENDIAN_BITFIELD */ 2081 uint16_t vpi; 2082 uint16_t rsvd3; 2083 #endif 2084 } READ_SPARM_VAR; 2085 2086 /* Structure for MB Command READ_STATUS (14) */ 2087 2088 typedef struct { 2089 #ifdef __BIG_ENDIAN_BITFIELD 2090 uint32_t rsvd1:31; 2091 uint32_t clrCounters:1; 2092 uint16_t activeXriCnt; 2093 uint16_t activeRpiCnt; 2094 #else /* __LITTLE_ENDIAN_BITFIELD */ 2095 uint32_t clrCounters:1; 2096 uint32_t rsvd1:31; 2097 uint16_t activeRpiCnt; 2098 uint16_t activeXriCnt; 2099 #endif 2100 2101 uint32_t xmitByteCnt; 2102 uint32_t rcvByteCnt; 2103 uint32_t xmitFrameCnt; 2104 uint32_t rcvFrameCnt; 2105 uint32_t xmitSeqCnt; 2106 uint32_t rcvSeqCnt; 2107 uint32_t totalOrigExchanges; 2108 uint32_t totalRespExchanges; 2109 uint32_t rcvPbsyCnt; 2110 uint32_t rcvFbsyCnt; 2111 } READ_STATUS_VAR; 2112 2113 /* Structure for MB Command READ_RPI (15) */ 2114 /* Structure for MB Command READ_RPI64 (0x8F) */ 2115 2116 typedef struct { 2117 #ifdef __BIG_ENDIAN_BITFIELD 2118 uint16_t nextRpi; 2119 uint16_t reqRpi; 2120 uint32_t rsvd2:8; 2121 uint32_t DID:24; 2122 #else /* __LITTLE_ENDIAN_BITFIELD */ 2123 uint16_t reqRpi; 2124 uint16_t nextRpi; 2125 uint32_t DID:24; 2126 uint32_t rsvd2:8; 2127 #endif 2128 2129 union { 2130 struct ulp_bde sp; 2131 struct ulp_bde64 sp64; 2132 } un; 2133 2134 } READ_RPI_VAR; 2135 2136 /* Structure for MB Command READ_XRI (16) */ 2137 2138 typedef struct { 2139 #ifdef __BIG_ENDIAN_BITFIELD 2140 uint16_t nextXri; 2141 uint16_t reqXri; 2142 uint16_t rsvd1; 2143 uint16_t rpi; 2144 uint32_t rsvd2:8; 2145 uint32_t DID:24; 2146 uint32_t rsvd3:8; 2147 uint32_t SID:24; 2148 uint32_t rsvd4; 2149 uint8_t seqId; 2150 uint8_t rsvd5; 2151 uint16_t seqCount; 2152 uint16_t oxId; 2153 uint16_t rxId; 2154 uint32_t rsvd6:30; 2155 uint32_t si:1; 2156 uint32_t exchOrig:1; 2157 #else /* __LITTLE_ENDIAN_BITFIELD */ 2158 uint16_t reqXri; 2159 uint16_t nextXri; 2160 uint16_t rpi; 2161 uint16_t rsvd1; 2162 uint32_t DID:24; 2163 uint32_t rsvd2:8; 2164 uint32_t SID:24; 2165 uint32_t rsvd3:8; 2166 uint32_t rsvd4; 2167 uint16_t seqCount; 2168 uint8_t rsvd5; 2169 uint8_t seqId; 2170 uint16_t rxId; 2171 uint16_t oxId; 2172 uint32_t exchOrig:1; 2173 uint32_t si:1; 2174 uint32_t rsvd6:30; 2175 #endif 2176 } READ_XRI_VAR; 2177 2178 /* Structure for MB Command READ_REV (17) */ 2179 2180 typedef struct { 2181 #ifdef __BIG_ENDIAN_BITFIELD 2182 uint32_t cv:1; 2183 uint32_t rr:1; 2184 uint32_t rsvd2:2; 2185 uint32_t v3req:1; 2186 uint32_t v3rsp:1; 2187 uint32_t rsvd1:25; 2188 uint32_t rv:1; 2189 #else /* __LITTLE_ENDIAN_BITFIELD */ 2190 uint32_t rv:1; 2191 uint32_t rsvd1:25; 2192 uint32_t v3rsp:1; 2193 uint32_t v3req:1; 2194 uint32_t rsvd2:2; 2195 uint32_t rr:1; 2196 uint32_t cv:1; 2197 #endif 2198 2199 uint32_t biuRev; 2200 uint32_t smRev; 2201 union { 2202 uint32_t smFwRev; 2203 struct { 2204 #ifdef __BIG_ENDIAN_BITFIELD 2205 uint8_t ProgType; 2206 uint8_t ProgId; 2207 uint16_t ProgVer:4; 2208 uint16_t ProgRev:4; 2209 uint16_t ProgFixLvl:2; 2210 uint16_t ProgDistType:2; 2211 uint16_t DistCnt:4; 2212 #else /* __LITTLE_ENDIAN_BITFIELD */ 2213 uint16_t DistCnt:4; 2214 uint16_t ProgDistType:2; 2215 uint16_t ProgFixLvl:2; 2216 uint16_t ProgRev:4; 2217 uint16_t ProgVer:4; 2218 uint8_t ProgId; 2219 uint8_t ProgType; 2220 #endif 2221 2222 } b; 2223 } un; 2224 uint32_t endecRev; 2225 #ifdef __BIG_ENDIAN_BITFIELD 2226 uint8_t feaLevelHigh; 2227 uint8_t feaLevelLow; 2228 uint8_t fcphHigh; 2229 uint8_t fcphLow; 2230 #else /* __LITTLE_ENDIAN_BITFIELD */ 2231 uint8_t fcphLow; 2232 uint8_t fcphHigh; 2233 uint8_t feaLevelLow; 2234 uint8_t feaLevelHigh; 2235 #endif 2236 2237 uint32_t postKernRev; 2238 uint32_t opFwRev; 2239 uint8_t opFwName[16]; 2240 uint32_t sli1FwRev; 2241 uint8_t sli1FwName[16]; 2242 uint32_t sli2FwRev; 2243 uint8_t sli2FwName[16]; 2244 uint32_t sli3Feat; 2245 uint32_t RandomData[6]; 2246 } READ_REV_VAR; 2247 2248 /* Structure for MB Command READ_LINK_STAT (18) */ 2249 2250 typedef struct { 2251 uint32_t rsvd1; 2252 uint32_t linkFailureCnt; 2253 uint32_t lossSyncCnt; 2254 2255 uint32_t lossSignalCnt; 2256 uint32_t primSeqErrCnt; 2257 uint32_t invalidXmitWord; 2258 uint32_t crcCnt; 2259 uint32_t primSeqTimeout; 2260 uint32_t elasticOverrun; 2261 uint32_t arbTimeout; 2262 } READ_LNK_VAR; 2263 2264 /* Structure for MB Command REG_LOGIN (19) */ 2265 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2266 2267 typedef struct { 2268 #ifdef __BIG_ENDIAN_BITFIELD 2269 uint16_t rsvd1; 2270 uint16_t rpi; 2271 uint32_t rsvd2:8; 2272 uint32_t did:24; 2273 #else /* __LITTLE_ENDIAN_BITFIELD */ 2274 uint16_t rpi; 2275 uint16_t rsvd1; 2276 uint32_t did:24; 2277 uint32_t rsvd2:8; 2278 #endif 2279 2280 union { 2281 struct ulp_bde sp; 2282 struct ulp_bde64 sp64; 2283 } un; 2284 2285 #ifdef __BIG_ENDIAN_BITFIELD 2286 uint16_t rsvd6; 2287 uint16_t vpi; 2288 #else /* __LITTLE_ENDIAN_BITFIELD */ 2289 uint16_t vpi; 2290 uint16_t rsvd6; 2291 #endif 2292 2293 } REG_LOGIN_VAR; 2294 2295 /* Word 30 contents for REG_LOGIN */ 2296 typedef union { 2297 struct { 2298 #ifdef __BIG_ENDIAN_BITFIELD 2299 uint16_t rsvd1:12; 2300 uint16_t wd30_class:4; 2301 uint16_t xri; 2302 #else /* __LITTLE_ENDIAN_BITFIELD */ 2303 uint16_t xri; 2304 uint16_t wd30_class:4; 2305 uint16_t rsvd1:12; 2306 #endif 2307 } f; 2308 uint32_t word; 2309 } REG_WD30; 2310 2311 /* Structure for MB Command UNREG_LOGIN (20) */ 2312 2313 typedef struct { 2314 #ifdef __BIG_ENDIAN_BITFIELD 2315 uint16_t rsvd1; 2316 uint16_t rpi; 2317 uint32_t rsvd2; 2318 uint32_t rsvd3; 2319 uint32_t rsvd4; 2320 uint32_t rsvd5; 2321 uint16_t rsvd6; 2322 uint16_t vpi; 2323 #else /* __LITTLE_ENDIAN_BITFIELD */ 2324 uint16_t rpi; 2325 uint16_t rsvd1; 2326 uint32_t rsvd2; 2327 uint32_t rsvd3; 2328 uint32_t rsvd4; 2329 uint32_t rsvd5; 2330 uint16_t vpi; 2331 uint16_t rsvd6; 2332 #endif 2333 } UNREG_LOGIN_VAR; 2334 2335 /* Structure for MB Command REG_VPI (0x96) */ 2336 typedef struct { 2337 #ifdef __BIG_ENDIAN_BITFIELD 2338 uint32_t rsvd1; 2339 uint32_t rsvd2:7; 2340 uint32_t upd:1; 2341 uint32_t sid:24; 2342 uint32_t wwn[2]; 2343 uint32_t rsvd5; 2344 uint16_t vfi; 2345 uint16_t vpi; 2346 #else /* __LITTLE_ENDIAN */ 2347 uint32_t rsvd1; 2348 uint32_t sid:24; 2349 uint32_t upd:1; 2350 uint32_t rsvd2:7; 2351 uint32_t wwn[2]; 2352 uint32_t rsvd5; 2353 uint16_t vpi; 2354 uint16_t vfi; 2355 #endif 2356 } REG_VPI_VAR; 2357 2358 /* Structure for MB Command UNREG_VPI (0x97) */ 2359 typedef struct { 2360 uint32_t rsvd1; 2361 #ifdef __BIG_ENDIAN_BITFIELD 2362 uint16_t rsvd2; 2363 uint16_t sli4_vpi; 2364 #else /* __LITTLE_ENDIAN */ 2365 uint16_t sli4_vpi; 2366 uint16_t rsvd2; 2367 #endif 2368 uint32_t rsvd3; 2369 uint32_t rsvd4; 2370 uint32_t rsvd5; 2371 #ifdef __BIG_ENDIAN_BITFIELD 2372 uint16_t rsvd6; 2373 uint16_t vpi; 2374 #else /* __LITTLE_ENDIAN */ 2375 uint16_t vpi; 2376 uint16_t rsvd6; 2377 #endif 2378 } UNREG_VPI_VAR; 2379 2380 /* Structure for MB Command UNREG_D_ID (0x23) */ 2381 2382 typedef struct { 2383 uint32_t did; 2384 uint32_t rsvd2; 2385 uint32_t rsvd3; 2386 uint32_t rsvd4; 2387 uint32_t rsvd5; 2388 #ifdef __BIG_ENDIAN_BITFIELD 2389 uint16_t rsvd6; 2390 uint16_t vpi; 2391 #else 2392 uint16_t vpi; 2393 uint16_t rsvd6; 2394 #endif 2395 } UNREG_D_ID_VAR; 2396 2397 /* Structure for MB Command READ_LA (21) */ 2398 /* Structure for MB Command READ_LA64 (0x95) */ 2399 2400 typedef struct { 2401 uint32_t eventTag; /* Event tag */ 2402 #ifdef __BIG_ENDIAN_BITFIELD 2403 uint32_t rsvd1:19; 2404 uint32_t fa:1; 2405 uint32_t mm:1; /* Menlo Maintenance mode enabled */ 2406 uint32_t rx:1; 2407 uint32_t pb:1; 2408 uint32_t il:1; 2409 uint32_t attType:8; 2410 #else /* __LITTLE_ENDIAN_BITFIELD */ 2411 uint32_t attType:8; 2412 uint32_t il:1; 2413 uint32_t pb:1; 2414 uint32_t rx:1; 2415 uint32_t mm:1; 2416 uint32_t fa:1; 2417 uint32_t rsvd1:19; 2418 #endif 2419 2420 #define AT_RESERVED 0x00 /* Reserved - attType */ 2421 #define AT_LINK_UP 0x01 /* Link is up */ 2422 #define AT_LINK_DOWN 0x02 /* Link is down */ 2423 2424 #ifdef __BIG_ENDIAN_BITFIELD 2425 uint8_t granted_AL_PA; 2426 uint8_t lipAlPs; 2427 uint8_t lipType; 2428 uint8_t topology; 2429 #else /* __LITTLE_ENDIAN_BITFIELD */ 2430 uint8_t topology; 2431 uint8_t lipType; 2432 uint8_t lipAlPs; 2433 uint8_t granted_AL_PA; 2434 #endif 2435 2436 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2437 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2438 #define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */ 2439 2440 union { 2441 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2442 to */ 2443 /* store the LILP AL_PA position map into */ 2444 struct ulp_bde64 lilpBde64; 2445 } un; 2446 2447 #ifdef __BIG_ENDIAN_BITFIELD 2448 uint32_t Dlu:1; 2449 uint32_t Dtf:1; 2450 uint32_t Drsvd2:14; 2451 uint32_t DlnkSpeed:8; 2452 uint32_t DnlPort:4; 2453 uint32_t Dtx:2; 2454 uint32_t Drx:2; 2455 #else /* __LITTLE_ENDIAN_BITFIELD */ 2456 uint32_t Drx:2; 2457 uint32_t Dtx:2; 2458 uint32_t DnlPort:4; 2459 uint32_t DlnkSpeed:8; 2460 uint32_t Drsvd2:14; 2461 uint32_t Dtf:1; 2462 uint32_t Dlu:1; 2463 #endif 2464 2465 #ifdef __BIG_ENDIAN_BITFIELD 2466 uint32_t Ulu:1; 2467 uint32_t Utf:1; 2468 uint32_t Ursvd2:14; 2469 uint32_t UlnkSpeed:8; 2470 uint32_t UnlPort:4; 2471 uint32_t Utx:2; 2472 uint32_t Urx:2; 2473 #else /* __LITTLE_ENDIAN_BITFIELD */ 2474 uint32_t Urx:2; 2475 uint32_t Utx:2; 2476 uint32_t UnlPort:4; 2477 uint32_t UlnkSpeed:8; 2478 uint32_t Ursvd2:14; 2479 uint32_t Utf:1; 2480 uint32_t Ulu:1; 2481 #endif 2482 2483 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2484 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2485 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2486 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2487 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2488 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2489 2490 } READ_LA_VAR; 2491 2492 /* Structure for MB Command CLEAR_LA (22) */ 2493 2494 typedef struct { 2495 uint32_t eventTag; /* Event tag */ 2496 uint32_t rsvd1; 2497 } CLEAR_LA_VAR; 2498 2499 /* Structure for MB Command DUMP */ 2500 2501 typedef struct { 2502 #ifdef __BIG_ENDIAN_BITFIELD 2503 uint32_t rsvd:25; 2504 uint32_t ra:1; 2505 uint32_t co:1; 2506 uint32_t cv:1; 2507 uint32_t type:4; 2508 uint32_t entry_index:16; 2509 uint32_t region_id:16; 2510 #else /* __LITTLE_ENDIAN_BITFIELD */ 2511 uint32_t type:4; 2512 uint32_t cv:1; 2513 uint32_t co:1; 2514 uint32_t ra:1; 2515 uint32_t rsvd:25; 2516 uint32_t region_id:16; 2517 uint32_t entry_index:16; 2518 #endif 2519 2520 uint32_t sli4_length; 2521 uint32_t word_cnt; 2522 uint32_t resp_offset; 2523 } DUMP_VAR; 2524 2525 #define DMP_MEM_REG 0x1 2526 #define DMP_NV_PARAMS 0x2 2527 2528 #define DMP_REGION_VPD 0xe 2529 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2530 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2531 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2532 2533 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2534 #define DMP_VPORT_REGION_SIZE 0x200 2535 #define DMP_MBOX_OFFSET_WORD 0x5 2536 2537 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2538 #define DMP_RGN23_SIZE 0x400 2539 2540 #define WAKE_UP_PARMS_REGION_ID 4 2541 #define WAKE_UP_PARMS_WORD_SIZE 15 2542 2543 struct vport_rec { 2544 uint8_t wwpn[8]; 2545 uint8_t wwnn[8]; 2546 }; 2547 2548 #define VPORT_INFO_SIG 0x32324752 2549 #define VPORT_INFO_REV_MASK 0xff 2550 #define VPORT_INFO_REV 0x1 2551 #define MAX_STATIC_VPORT_COUNT 16 2552 struct static_vport_info { 2553 uint32_t signature; 2554 uint32_t rev; 2555 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2556 uint32_t resvd[66]; 2557 }; 2558 2559 /* Option rom version structure */ 2560 struct prog_id { 2561 #ifdef __BIG_ENDIAN_BITFIELD 2562 uint8_t type; 2563 uint8_t id; 2564 uint32_t ver:4; /* Major Version */ 2565 uint32_t rev:4; /* Revision */ 2566 uint32_t lev:2; /* Level */ 2567 uint32_t dist:2; /* Dist Type */ 2568 uint32_t num:4; /* number after dist type */ 2569 #else /* __LITTLE_ENDIAN_BITFIELD */ 2570 uint32_t num:4; /* number after dist type */ 2571 uint32_t dist:2; /* Dist Type */ 2572 uint32_t lev:2; /* Level */ 2573 uint32_t rev:4; /* Revision */ 2574 uint32_t ver:4; /* Major Version */ 2575 uint8_t id; 2576 uint8_t type; 2577 #endif 2578 }; 2579 2580 /* Structure for MB Command UPDATE_CFG (0x1B) */ 2581 2582 struct update_cfg_var { 2583 #ifdef __BIG_ENDIAN_BITFIELD 2584 uint32_t rsvd2:16; 2585 uint32_t type:8; 2586 uint32_t rsvd:1; 2587 uint32_t ra:1; 2588 uint32_t co:1; 2589 uint32_t cv:1; 2590 uint32_t req:4; 2591 uint32_t entry_length:16; 2592 uint32_t region_id:16; 2593 #else /* __LITTLE_ENDIAN_BITFIELD */ 2594 uint32_t req:4; 2595 uint32_t cv:1; 2596 uint32_t co:1; 2597 uint32_t ra:1; 2598 uint32_t rsvd:1; 2599 uint32_t type:8; 2600 uint32_t rsvd2:16; 2601 uint32_t region_id:16; 2602 uint32_t entry_length:16; 2603 #endif 2604 2605 uint32_t resp_info; 2606 uint32_t byte_cnt; 2607 uint32_t data_offset; 2608 }; 2609 2610 struct hbq_mask { 2611 #ifdef __BIG_ENDIAN_BITFIELD 2612 uint8_t tmatch; 2613 uint8_t tmask; 2614 uint8_t rctlmatch; 2615 uint8_t rctlmask; 2616 #else /* __LITTLE_ENDIAN */ 2617 uint8_t rctlmask; 2618 uint8_t rctlmatch; 2619 uint8_t tmask; 2620 uint8_t tmatch; 2621 #endif 2622 }; 2623 2624 2625 /* Structure for MB Command CONFIG_HBQ (7c) */ 2626 2627 struct config_hbq_var { 2628 #ifdef __BIG_ENDIAN_BITFIELD 2629 uint32_t rsvd1 :7; 2630 uint32_t recvNotify :1; /* Receive Notification */ 2631 uint32_t numMask :8; /* # Mask Entries */ 2632 uint32_t profile :8; /* Selection Profile */ 2633 uint32_t rsvd2 :8; 2634 #else /* __LITTLE_ENDIAN */ 2635 uint32_t rsvd2 :8; 2636 uint32_t profile :8; /* Selection Profile */ 2637 uint32_t numMask :8; /* # Mask Entries */ 2638 uint32_t recvNotify :1; /* Receive Notification */ 2639 uint32_t rsvd1 :7; 2640 #endif 2641 2642 #ifdef __BIG_ENDIAN_BITFIELD 2643 uint32_t hbqId :16; 2644 uint32_t rsvd3 :12; 2645 uint32_t ringMask :4; 2646 #else /* __LITTLE_ENDIAN */ 2647 uint32_t ringMask :4; 2648 uint32_t rsvd3 :12; 2649 uint32_t hbqId :16; 2650 #endif 2651 2652 #ifdef __BIG_ENDIAN_BITFIELD 2653 uint32_t entry_count :16; 2654 uint32_t rsvd4 :8; 2655 uint32_t headerLen :8; 2656 #else /* __LITTLE_ENDIAN */ 2657 uint32_t headerLen :8; 2658 uint32_t rsvd4 :8; 2659 uint32_t entry_count :16; 2660 #endif 2661 2662 uint32_t hbqaddrLow; 2663 uint32_t hbqaddrHigh; 2664 2665 #ifdef __BIG_ENDIAN_BITFIELD 2666 uint32_t rsvd5 :31; 2667 uint32_t logEntry :1; 2668 #else /* __LITTLE_ENDIAN */ 2669 uint32_t logEntry :1; 2670 uint32_t rsvd5 :31; 2671 #endif 2672 2673 uint32_t rsvd6; /* w7 */ 2674 uint32_t rsvd7; /* w8 */ 2675 uint32_t rsvd8; /* w9 */ 2676 2677 struct hbq_mask hbqMasks[6]; 2678 2679 2680 union { 2681 uint32_t allprofiles[12]; 2682 2683 struct { 2684 #ifdef __BIG_ENDIAN_BITFIELD 2685 uint32_t seqlenoff :16; 2686 uint32_t maxlen :16; 2687 #else /* __LITTLE_ENDIAN */ 2688 uint32_t maxlen :16; 2689 uint32_t seqlenoff :16; 2690 #endif 2691 #ifdef __BIG_ENDIAN_BITFIELD 2692 uint32_t rsvd1 :28; 2693 uint32_t seqlenbcnt :4; 2694 #else /* __LITTLE_ENDIAN */ 2695 uint32_t seqlenbcnt :4; 2696 uint32_t rsvd1 :28; 2697 #endif 2698 uint32_t rsvd[10]; 2699 } profile2; 2700 2701 struct { 2702 #ifdef __BIG_ENDIAN_BITFIELD 2703 uint32_t seqlenoff :16; 2704 uint32_t maxlen :16; 2705 #else /* __LITTLE_ENDIAN */ 2706 uint32_t maxlen :16; 2707 uint32_t seqlenoff :16; 2708 #endif 2709 #ifdef __BIG_ENDIAN_BITFIELD 2710 uint32_t cmdcodeoff :28; 2711 uint32_t rsvd1 :12; 2712 uint32_t seqlenbcnt :4; 2713 #else /* __LITTLE_ENDIAN */ 2714 uint32_t seqlenbcnt :4; 2715 uint32_t rsvd1 :12; 2716 uint32_t cmdcodeoff :28; 2717 #endif 2718 uint32_t cmdmatch[8]; 2719 2720 uint32_t rsvd[2]; 2721 } profile3; 2722 2723 struct { 2724 #ifdef __BIG_ENDIAN_BITFIELD 2725 uint32_t seqlenoff :16; 2726 uint32_t maxlen :16; 2727 #else /* __LITTLE_ENDIAN */ 2728 uint32_t maxlen :16; 2729 uint32_t seqlenoff :16; 2730 #endif 2731 #ifdef __BIG_ENDIAN_BITFIELD 2732 uint32_t cmdcodeoff :28; 2733 uint32_t rsvd1 :12; 2734 uint32_t seqlenbcnt :4; 2735 #else /* __LITTLE_ENDIAN */ 2736 uint32_t seqlenbcnt :4; 2737 uint32_t rsvd1 :12; 2738 uint32_t cmdcodeoff :28; 2739 #endif 2740 uint32_t cmdmatch[8]; 2741 2742 uint32_t rsvd[2]; 2743 } profile5; 2744 2745 } profiles; 2746 2747 }; 2748 2749 2750 2751 /* Structure for MB Command CONFIG_PORT (0x88) */ 2752 typedef struct { 2753 #ifdef __BIG_ENDIAN_BITFIELD 2754 uint32_t cBE : 1; 2755 uint32_t cET : 1; 2756 uint32_t cHpcb : 1; 2757 uint32_t cMA : 1; 2758 uint32_t sli_mode : 4; 2759 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2760 * config block */ 2761 #else /* __LITTLE_ENDIAN */ 2762 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2763 * config block */ 2764 uint32_t sli_mode : 4; 2765 uint32_t cMA : 1; 2766 uint32_t cHpcb : 1; 2767 uint32_t cET : 1; 2768 uint32_t cBE : 1; 2769 #endif 2770 2771 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2772 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2773 uint32_t hbainit[5]; 2774 #ifdef __BIG_ENDIAN_BITFIELD 2775 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2776 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2777 #else /* __LITTLE_ENDIAN */ 2778 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2779 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2780 #endif 2781 2782 #ifdef __BIG_ENDIAN_BITFIELD 2783 uint32_t rsvd1 : 19; /* Reserved */ 2784 uint32_t cdss : 1; /* Configure Data Security SLI */ 2785 uint32_t rsvd2 : 3; /* Reserved */ 2786 uint32_t cbg : 1; /* Configure BlockGuard */ 2787 uint32_t cmv : 1; /* Configure Max VPIs */ 2788 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2789 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2790 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2791 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2792 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2793 uint32_t cmx : 1; /* Configure Max XRIs */ 2794 uint32_t cmr : 1; /* Configure Max RPIs */ 2795 #else /* __LITTLE_ENDIAN */ 2796 uint32_t cmr : 1; /* Configure Max RPIs */ 2797 uint32_t cmx : 1; /* Configure Max XRIs */ 2798 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2799 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2800 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2801 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2802 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2803 uint32_t cmv : 1; /* Configure Max VPIs */ 2804 uint32_t cbg : 1; /* Configure BlockGuard */ 2805 uint32_t rsvd2 : 3; /* Reserved */ 2806 uint32_t cdss : 1; /* Configure Data Security SLI */ 2807 uint32_t rsvd1 : 19; /* Reserved */ 2808 #endif 2809 #ifdef __BIG_ENDIAN_BITFIELD 2810 uint32_t rsvd3 : 19; /* Reserved */ 2811 uint32_t gdss : 1; /* Configure Data Security SLI */ 2812 uint32_t rsvd4 : 3; /* Reserved */ 2813 uint32_t gbg : 1; /* Grant BlockGuard */ 2814 uint32_t gmv : 1; /* Grant Max VPIs */ 2815 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2816 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2817 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2818 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2819 uint32_t gerbm : 1; /* Grant ERBM Request */ 2820 uint32_t gmx : 1; /* Grant Max XRIs */ 2821 uint32_t gmr : 1; /* Grant Max RPIs */ 2822 #else /* __LITTLE_ENDIAN */ 2823 uint32_t gmr : 1; /* Grant Max RPIs */ 2824 uint32_t gmx : 1; /* Grant Max XRIs */ 2825 uint32_t gerbm : 1; /* Grant ERBM Request */ 2826 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2827 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2828 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2829 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2830 uint32_t gmv : 1; /* Grant Max VPIs */ 2831 uint32_t gbg : 1; /* Grant BlockGuard */ 2832 uint32_t rsvd4 : 3; /* Reserved */ 2833 uint32_t gdss : 1; /* Configure Data Security SLI */ 2834 uint32_t rsvd3 : 19; /* Reserved */ 2835 #endif 2836 2837 #ifdef __BIG_ENDIAN_BITFIELD 2838 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2839 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2840 #else /* __LITTLE_ENDIAN */ 2841 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2842 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2843 #endif 2844 2845 #ifdef __BIG_ENDIAN_BITFIELD 2846 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2847 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2848 #else /* __LITTLE_ENDIAN */ 2849 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2850 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2851 #endif 2852 2853 uint32_t rsvd6; /* Reserved */ 2854 2855 #ifdef __BIG_ENDIAN_BITFIELD 2856 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2857 uint32_t fips_level : 4; /* FIPS Level */ 2858 uint32_t sec_err : 9; /* security crypto error */ 2859 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2860 #else /* __LITTLE_ENDIAN */ 2861 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2862 uint32_t sec_err : 9; /* security crypto error */ 2863 uint32_t fips_level : 4; /* FIPS Level */ 2864 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2865 #endif 2866 2867 } CONFIG_PORT_VAR; 2868 2869 /* Structure for MB Command CONFIG_MSI (0x30) */ 2870 struct config_msi_var { 2871 #ifdef __BIG_ENDIAN_BITFIELD 2872 uint32_t dfltMsgNum:8; /* Default message number */ 2873 uint32_t rsvd1:11; /* Reserved */ 2874 uint32_t NID:5; /* Number of secondary attention IDs */ 2875 uint32_t rsvd2:5; /* Reserved */ 2876 uint32_t dfltPresent:1; /* Default message number present */ 2877 uint32_t addFlag:1; /* Add association flag */ 2878 uint32_t reportFlag:1; /* Report association flag */ 2879 #else /* __LITTLE_ENDIAN_BITFIELD */ 2880 uint32_t reportFlag:1; /* Report association flag */ 2881 uint32_t addFlag:1; /* Add association flag */ 2882 uint32_t dfltPresent:1; /* Default message number present */ 2883 uint32_t rsvd2:5; /* Reserved */ 2884 uint32_t NID:5; /* Number of secondary attention IDs */ 2885 uint32_t rsvd1:11; /* Reserved */ 2886 uint32_t dfltMsgNum:8; /* Default message number */ 2887 #endif 2888 uint32_t attentionConditions[2]; 2889 uint8_t attentionId[16]; 2890 uint8_t messageNumberByHA[64]; 2891 uint8_t messageNumberByID[16]; 2892 uint32_t autoClearHA[2]; 2893 #ifdef __BIG_ENDIAN_BITFIELD 2894 uint32_t rsvd3:16; 2895 uint32_t autoClearID:16; 2896 #else /* __LITTLE_ENDIAN_BITFIELD */ 2897 uint32_t autoClearID:16; 2898 uint32_t rsvd3:16; 2899 #endif 2900 uint32_t rsvd4; 2901 }; 2902 2903 /* SLI-2 Port Control Block */ 2904 2905 /* SLIM POINTER */ 2906 #define SLIMOFF 0x30 /* WORD */ 2907 2908 typedef struct _SLI2_RDSC { 2909 uint32_t cmdEntries; 2910 uint32_t cmdAddrLow; 2911 uint32_t cmdAddrHigh; 2912 2913 uint32_t rspEntries; 2914 uint32_t rspAddrLow; 2915 uint32_t rspAddrHigh; 2916 } SLI2_RDSC; 2917 2918 typedef struct _PCB { 2919 #ifdef __BIG_ENDIAN_BITFIELD 2920 uint32_t type:8; 2921 #define TYPE_NATIVE_SLI2 0x01; 2922 uint32_t feature:8; 2923 #define FEATURE_INITIAL_SLI2 0x01; 2924 uint32_t rsvd:12; 2925 uint32_t maxRing:4; 2926 #else /* __LITTLE_ENDIAN_BITFIELD */ 2927 uint32_t maxRing:4; 2928 uint32_t rsvd:12; 2929 uint32_t feature:8; 2930 #define FEATURE_INITIAL_SLI2 0x01; 2931 uint32_t type:8; 2932 #define TYPE_NATIVE_SLI2 0x01; 2933 #endif 2934 2935 uint32_t mailBoxSize; 2936 uint32_t mbAddrLow; 2937 uint32_t mbAddrHigh; 2938 2939 uint32_t hgpAddrLow; 2940 uint32_t hgpAddrHigh; 2941 2942 uint32_t pgpAddrLow; 2943 uint32_t pgpAddrHigh; 2944 SLI2_RDSC rdsc[MAX_RINGS]; 2945 } PCB_t; 2946 2947 /* NEW_FEATURE */ 2948 typedef struct { 2949 #ifdef __BIG_ENDIAN_BITFIELD 2950 uint32_t rsvd0:27; 2951 uint32_t discardFarp:1; 2952 uint32_t IPEnable:1; 2953 uint32_t nodeName:1; 2954 uint32_t portName:1; 2955 uint32_t filterEnable:1; 2956 #else /* __LITTLE_ENDIAN_BITFIELD */ 2957 uint32_t filterEnable:1; 2958 uint32_t portName:1; 2959 uint32_t nodeName:1; 2960 uint32_t IPEnable:1; 2961 uint32_t discardFarp:1; 2962 uint32_t rsvd:27; 2963 #endif 2964 2965 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2966 uint8_t nodename[8]; 2967 uint32_t rsvd1; 2968 uint32_t rsvd2; 2969 uint32_t rsvd3; 2970 uint32_t IPAddress; 2971 } CONFIG_FARP_VAR; 2972 2973 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 2974 2975 typedef struct { 2976 #ifdef __BIG_ENDIAN_BITFIELD 2977 uint32_t rsvd:30; 2978 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2979 #else /* __LITTLE_ENDIAN */ 2980 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2981 uint32_t rsvd:30; 2982 #endif 2983 } ASYNCEVT_ENABLE_VAR; 2984 2985 /* Union of all Mailbox Command types */ 2986 #define MAILBOX_CMD_WSIZE 32 2987 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2988 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 2989 #define MAILBOX_EXT_WSIZE 512 2990 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 2991 #define MAILBOX_HBA_EXT_OFFSET 0x100 2992 /* max mbox xmit size is a page size for sysfs IO operations */ 2993 #define MAILBOX_MAX_XMIT_SIZE PAGE_SIZE 2994 2995 typedef union { 2996 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 2997 * feature/max ring number 2998 */ 2999 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3000 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3001 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3002 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3003 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3004 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3005 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3006 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3007 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3008 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3009 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3010 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3011 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3012 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3013 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3014 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3015 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3016 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3017 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3018 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3019 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 3020 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3021 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3022 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3023 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3024 * NEW_FEATURE 3025 */ 3026 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3027 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3028 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3029 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3030 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3031 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3032 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3033 * (READ_EVENT_LOG) 3034 */ 3035 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3036 } MAILVARIANTS; 3037 3038 /* 3039 * SLI-2 specific structures 3040 */ 3041 3042 struct lpfc_hgp { 3043 __le32 cmdPutInx; 3044 __le32 rspGetInx; 3045 }; 3046 3047 struct lpfc_pgp { 3048 __le32 cmdGetInx; 3049 __le32 rspPutInx; 3050 }; 3051 3052 struct sli2_desc { 3053 uint32_t unused1[16]; 3054 struct lpfc_hgp host[MAX_RINGS]; 3055 struct lpfc_pgp port[MAX_RINGS]; 3056 }; 3057 3058 struct sli3_desc { 3059 struct lpfc_hgp host[MAX_RINGS]; 3060 uint32_t reserved[8]; 3061 uint32_t hbq_put[16]; 3062 }; 3063 3064 struct sli3_pgp { 3065 struct lpfc_pgp port[MAX_RINGS]; 3066 uint32_t hbq_get[16]; 3067 }; 3068 3069 union sli_var { 3070 struct sli2_desc s2; 3071 struct sli3_desc s3; 3072 struct sli3_pgp s3_pgp; 3073 }; 3074 3075 typedef struct { 3076 #ifdef __BIG_ENDIAN_BITFIELD 3077 uint16_t mbxStatus; 3078 uint8_t mbxCommand; 3079 uint8_t mbxReserved:6; 3080 uint8_t mbxHc:1; 3081 uint8_t mbxOwner:1; /* Low order bit first word */ 3082 #else /* __LITTLE_ENDIAN_BITFIELD */ 3083 uint8_t mbxOwner:1; /* Low order bit first word */ 3084 uint8_t mbxHc:1; 3085 uint8_t mbxReserved:6; 3086 uint8_t mbxCommand; 3087 uint16_t mbxStatus; 3088 #endif 3089 3090 MAILVARIANTS un; 3091 union sli_var us; 3092 } MAILBOX_t; 3093 3094 /* 3095 * Begin Structure Definitions for IOCB Commands 3096 */ 3097 3098 typedef struct { 3099 #ifdef __BIG_ENDIAN_BITFIELD 3100 uint8_t statAction; 3101 uint8_t statRsn; 3102 uint8_t statBaExp; 3103 uint8_t statLocalError; 3104 #else /* __LITTLE_ENDIAN_BITFIELD */ 3105 uint8_t statLocalError; 3106 uint8_t statBaExp; 3107 uint8_t statRsn; 3108 uint8_t statAction; 3109 #endif 3110 /* statRsn P/F_RJT reason codes */ 3111 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3112 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3113 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3114 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3115 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3116 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3117 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3118 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3119 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3120 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3121 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3122 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3123 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3124 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3125 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3126 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3127 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3128 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3129 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3130 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3131 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3132 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3133 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3134 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3135 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3136 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3137 3138 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3139 #define IOERR_MISSING_CONTINUE 0x01 3140 #define IOERR_SEQUENCE_TIMEOUT 0x02 3141 #define IOERR_INTERNAL_ERROR 0x03 3142 #define IOERR_INVALID_RPI 0x04 3143 #define IOERR_NO_XRI 0x05 3144 #define IOERR_ILLEGAL_COMMAND 0x06 3145 #define IOERR_XCHG_DROPPED 0x07 3146 #define IOERR_ILLEGAL_FIELD 0x08 3147 #define IOERR_BAD_CONTINUE 0x09 3148 #define IOERR_TOO_MANY_BUFFERS 0x0A 3149 #define IOERR_RCV_BUFFER_WAITING 0x0B 3150 #define IOERR_NO_CONNECTION 0x0C 3151 #define IOERR_TX_DMA_FAILED 0x0D 3152 #define IOERR_RX_DMA_FAILED 0x0E 3153 #define IOERR_ILLEGAL_FRAME 0x0F 3154 #define IOERR_EXTRA_DATA 0x10 3155 #define IOERR_NO_RESOURCES 0x11 3156 #define IOERR_RESERVED 0x12 3157 #define IOERR_ILLEGAL_LENGTH 0x13 3158 #define IOERR_UNSUPPORTED_FEATURE 0x14 3159 #define IOERR_ABORT_IN_PROGRESS 0x15 3160 #define IOERR_ABORT_REQUESTED 0x16 3161 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3162 #define IOERR_LOOP_OPEN_FAILURE 0x18 3163 #define IOERR_RING_RESET 0x19 3164 #define IOERR_LINK_DOWN 0x1A 3165 #define IOERR_CORRUPTED_DATA 0x1B 3166 #define IOERR_CORRUPTED_RPI 0x1C 3167 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3168 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3169 #define IOERR_DUP_FRAME 0x1F 3170 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3171 #define IOERR_BAD_HOST_ADDRESS 0x21 3172 #define IOERR_RCV_HDRBUF_WAITING 0x22 3173 #define IOERR_MISSING_HDR_BUFFER 0x23 3174 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3175 #define IOERR_ABORTMULT_REQUESTED 0x25 3176 #define IOERR_BUFFER_SHORTAGE 0x28 3177 #define IOERR_DEFAULT 0x29 3178 #define IOERR_CNT 0x2A 3179 #define IOERR_SLER_FAILURE 0x46 3180 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3181 #define IOERR_SLER_REC_RJT_ERR 0x48 3182 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3183 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3184 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3185 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3186 #define IOERR_SLER_ABTS_ERR 0x4E 3187 3188 #define IOERR_DRVR_MASK 0x100 3189 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3190 #define IOERR_SLI_BRESET 0x102 3191 #define IOERR_SLI_ABORTED 0x103 3192 } PARM_ERR; 3193 3194 typedef union { 3195 struct { 3196 #ifdef __BIG_ENDIAN_BITFIELD 3197 uint8_t Rctl; /* R_CTL field */ 3198 uint8_t Type; /* TYPE field */ 3199 uint8_t Dfctl; /* DF_CTL field */ 3200 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3201 #else /* __LITTLE_ENDIAN_BITFIELD */ 3202 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3203 uint8_t Dfctl; /* DF_CTL field */ 3204 uint8_t Type; /* TYPE field */ 3205 uint8_t Rctl; /* R_CTL field */ 3206 #endif 3207 3208 #define BC 0x02 /* Broadcast Received - Fctl */ 3209 #define SI 0x04 /* Sequence Initiative */ 3210 #define LA 0x08 /* Ignore Link Attention state */ 3211 #define LS 0x80 /* Last Sequence */ 3212 } hcsw; 3213 uint32_t reserved; 3214 } WORD5; 3215 3216 /* IOCB Command template for a generic response */ 3217 typedef struct { 3218 uint32_t reserved[4]; 3219 PARM_ERR perr; 3220 } GENERIC_RSP; 3221 3222 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3223 typedef struct { 3224 struct ulp_bde xrsqbde[2]; 3225 uint32_t xrsqRo; /* Starting Relative Offset */ 3226 WORD5 w5; /* Header control/status word */ 3227 } XR_SEQ_FIELDS; 3228 3229 /* IOCB Command template for ELS_REQUEST */ 3230 typedef struct { 3231 struct ulp_bde elsReq; 3232 struct ulp_bde elsRsp; 3233 3234 #ifdef __BIG_ENDIAN_BITFIELD 3235 uint32_t word4Rsvd:7; 3236 uint32_t fl:1; 3237 uint32_t myID:24; 3238 uint32_t word5Rsvd:8; 3239 uint32_t remoteID:24; 3240 #else /* __LITTLE_ENDIAN_BITFIELD */ 3241 uint32_t myID:24; 3242 uint32_t fl:1; 3243 uint32_t word4Rsvd:7; 3244 uint32_t remoteID:24; 3245 uint32_t word5Rsvd:8; 3246 #endif 3247 } ELS_REQUEST; 3248 3249 /* IOCB Command template for RCV_ELS_REQ */ 3250 typedef struct { 3251 struct ulp_bde elsReq[2]; 3252 uint32_t parmRo; 3253 3254 #ifdef __BIG_ENDIAN_BITFIELD 3255 uint32_t word5Rsvd:8; 3256 uint32_t remoteID:24; 3257 #else /* __LITTLE_ENDIAN_BITFIELD */ 3258 uint32_t remoteID:24; 3259 uint32_t word5Rsvd:8; 3260 #endif 3261 } RCV_ELS_REQ; 3262 3263 /* IOCB Command template for ABORT / CLOSE_XRI */ 3264 typedef struct { 3265 uint32_t rsvd[3]; 3266 uint32_t abortType; 3267 #define ABORT_TYPE_ABTX 0x00000000 3268 #define ABORT_TYPE_ABTS 0x00000001 3269 uint32_t parm; 3270 #ifdef __BIG_ENDIAN_BITFIELD 3271 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3272 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3273 #else /* __LITTLE_ENDIAN_BITFIELD */ 3274 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3275 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3276 #endif 3277 } AC_XRI; 3278 3279 /* IOCB Command template for ABORT_MXRI64 */ 3280 typedef struct { 3281 uint32_t rsvd[3]; 3282 uint32_t abortType; 3283 uint32_t parm; 3284 uint32_t iotag32; 3285 } A_MXRI64; 3286 3287 /* IOCB Command template for GET_RPI */ 3288 typedef struct { 3289 uint32_t rsvd[4]; 3290 uint32_t parmRo; 3291 #ifdef __BIG_ENDIAN_BITFIELD 3292 uint32_t word5Rsvd:8; 3293 uint32_t remoteID:24; 3294 #else /* __LITTLE_ENDIAN_BITFIELD */ 3295 uint32_t remoteID:24; 3296 uint32_t word5Rsvd:8; 3297 #endif 3298 } GET_RPI; 3299 3300 /* IOCB Command template for all FCP Initiator commands */ 3301 typedef struct { 3302 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3303 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3304 uint32_t fcpi_parm; 3305 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3306 } FCPI_FIELDS; 3307 3308 /* IOCB Command template for all FCP Target commands */ 3309 typedef struct { 3310 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3311 uint32_t fcpt_Offset; 3312 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3313 } FCPT_FIELDS; 3314 3315 /* SLI-2 IOCB structure definitions */ 3316 3317 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3318 typedef struct { 3319 ULP_BDL bdl; 3320 uint32_t xrsqRo; /* Starting Relative Offset */ 3321 WORD5 w5; /* Header control/status word */ 3322 } XMT_SEQ_FIELDS64; 3323 3324 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3325 typedef struct { 3326 struct ulp_bde64 rcvBde; 3327 uint32_t rsvd1; 3328 uint32_t xrsqRo; /* Starting Relative Offset */ 3329 WORD5 w5; /* Header control/status word */ 3330 } RCV_SEQ_FIELDS64; 3331 3332 /* IOCB Command template for ELS_REQUEST64 */ 3333 typedef struct { 3334 ULP_BDL bdl; 3335 #ifdef __BIG_ENDIAN_BITFIELD 3336 uint32_t word4Rsvd:7; 3337 uint32_t fl:1; 3338 uint32_t myID:24; 3339 uint32_t word5Rsvd:8; 3340 uint32_t remoteID:24; 3341 #else /* __LITTLE_ENDIAN_BITFIELD */ 3342 uint32_t myID:24; 3343 uint32_t fl:1; 3344 uint32_t word4Rsvd:7; 3345 uint32_t remoteID:24; 3346 uint32_t word5Rsvd:8; 3347 #endif 3348 } ELS_REQUEST64; 3349 3350 /* IOCB Command template for GEN_REQUEST64 */ 3351 typedef struct { 3352 ULP_BDL bdl; 3353 uint32_t xrsqRo; /* Starting Relative Offset */ 3354 WORD5 w5; /* Header control/status word */ 3355 } GEN_REQUEST64; 3356 3357 /* IOCB Command template for RCV_ELS_REQ64 */ 3358 typedef struct { 3359 struct ulp_bde64 elsReq; 3360 uint32_t rcvd1; 3361 uint32_t parmRo; 3362 3363 #ifdef __BIG_ENDIAN_BITFIELD 3364 uint32_t word5Rsvd:8; 3365 uint32_t remoteID:24; 3366 #else /* __LITTLE_ENDIAN_BITFIELD */ 3367 uint32_t remoteID:24; 3368 uint32_t word5Rsvd:8; 3369 #endif 3370 } RCV_ELS_REQ64; 3371 3372 /* IOCB Command template for RCV_SEQ64 */ 3373 struct rcv_seq64 { 3374 struct ulp_bde64 elsReq; 3375 uint32_t hbq_1; 3376 uint32_t parmRo; 3377 #ifdef __BIG_ENDIAN_BITFIELD 3378 uint32_t rctl:8; 3379 uint32_t type:8; 3380 uint32_t dfctl:8; 3381 uint32_t ls:1; 3382 uint32_t fs:1; 3383 uint32_t rsvd2:3; 3384 uint32_t si:1; 3385 uint32_t bc:1; 3386 uint32_t rsvd3:1; 3387 #else /* __LITTLE_ENDIAN_BITFIELD */ 3388 uint32_t rsvd3:1; 3389 uint32_t bc:1; 3390 uint32_t si:1; 3391 uint32_t rsvd2:3; 3392 uint32_t fs:1; 3393 uint32_t ls:1; 3394 uint32_t dfctl:8; 3395 uint32_t type:8; 3396 uint32_t rctl:8; 3397 #endif 3398 }; 3399 3400 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3401 typedef struct { 3402 ULP_BDL bdl; 3403 uint32_t fcpi_parm; 3404 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3405 } FCPI_FIELDS64; 3406 3407 /* IOCB Command template for all 64 bit FCP Target commands */ 3408 typedef struct { 3409 ULP_BDL bdl; 3410 uint32_t fcpt_Offset; 3411 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3412 } FCPT_FIELDS64; 3413 3414 /* IOCB Command template for Async Status iocb commands */ 3415 typedef struct { 3416 uint32_t rsvd[4]; 3417 uint32_t param; 3418 #ifdef __BIG_ENDIAN_BITFIELD 3419 uint16_t evt_code; /* High order bits word 5 */ 3420 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3421 #else /* __LITTLE_ENDIAN_BITFIELD */ 3422 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3423 uint16_t evt_code; /* Low order bits word 5 */ 3424 #endif 3425 } ASYNCSTAT_FIELDS; 3426 #define ASYNC_TEMP_WARN 0x100 3427 #define ASYNC_TEMP_SAFE 0x101 3428 3429 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3430 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3431 3432 struct rcv_sli3 { 3433 uint32_t word8Rsvd; 3434 #ifdef __BIG_ENDIAN_BITFIELD 3435 uint16_t vpi; 3436 uint16_t word9Rsvd; 3437 #else /* __LITTLE_ENDIAN */ 3438 uint16_t word9Rsvd; 3439 uint16_t vpi; 3440 #endif 3441 uint32_t word10Rsvd; 3442 uint32_t acc_len; /* accumulated length */ 3443 struct ulp_bde64 bde2; 3444 }; 3445 3446 /* Structure used for a single HBQ entry */ 3447 struct lpfc_hbq_entry { 3448 struct ulp_bde64 bde; 3449 uint32_t buffer_tag; 3450 }; 3451 3452 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3453 typedef struct { 3454 struct lpfc_hbq_entry buff; 3455 uint32_t rsvd; 3456 uint32_t rsvd1; 3457 } QUE_XRI64_CX_FIELDS; 3458 3459 struct que_xri64cx_ext_fields { 3460 uint32_t iotag64_low; 3461 uint32_t iotag64_high; 3462 uint32_t ebde_count; 3463 uint32_t rsvd; 3464 struct lpfc_hbq_entry buff[5]; 3465 }; 3466 3467 struct sli3_bg_fields { 3468 uint32_t filler[6]; /* word 8-13 in IOCB */ 3469 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3470 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3471 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3472 #define BGS_BIDIR_BG_PROF_SHIFT 24 3473 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3474 #define BGS_BIDIR_ERR_COND_SHIFT 16 3475 #define BGS_BG_PROFILE_MASK 0x0000ff00 3476 #define BGS_BG_PROFILE_SHIFT 8 3477 #define BGS_INVALID_PROF_MASK 0x00000020 3478 #define BGS_INVALID_PROF_SHIFT 5 3479 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3480 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3481 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3482 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3483 #define BGS_REFTAG_ERR_MASK 0x00000004 3484 #define BGS_REFTAG_ERR_SHIFT 2 3485 #define BGS_APPTAG_ERR_MASK 0x00000002 3486 #define BGS_APPTAG_ERR_SHIFT 1 3487 #define BGS_GUARD_ERR_MASK 0x00000001 3488 #define BGS_GUARD_ERR_SHIFT 0 3489 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3490 }; 3491 3492 static inline uint32_t 3493 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3494 { 3495 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 3496 BGS_BIDIR_BG_PROF_SHIFT; 3497 } 3498 3499 static inline uint32_t 3500 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3501 { 3502 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3503 BGS_BIDIR_ERR_COND_SHIFT; 3504 } 3505 3506 static inline uint32_t 3507 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3508 { 3509 return (bgstat & BGS_BG_PROFILE_MASK) >> 3510 BGS_BG_PROFILE_SHIFT; 3511 } 3512 3513 static inline uint32_t 3514 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3515 { 3516 return (bgstat & BGS_INVALID_PROF_MASK) >> 3517 BGS_INVALID_PROF_SHIFT; 3518 } 3519 3520 static inline uint32_t 3521 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3522 { 3523 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 3524 BGS_UNINIT_DIF_BLOCK_SHIFT; 3525 } 3526 3527 static inline uint32_t 3528 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3529 { 3530 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3531 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3532 } 3533 3534 static inline uint32_t 3535 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3536 { 3537 return (bgstat & BGS_REFTAG_ERR_MASK) >> 3538 BGS_REFTAG_ERR_SHIFT; 3539 } 3540 3541 static inline uint32_t 3542 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3543 { 3544 return (bgstat & BGS_APPTAG_ERR_MASK) >> 3545 BGS_APPTAG_ERR_SHIFT; 3546 } 3547 3548 static inline uint32_t 3549 lpfc_bgs_get_guard_err(uint32_t bgstat) 3550 { 3551 return (bgstat & BGS_GUARD_ERR_MASK) >> 3552 BGS_GUARD_ERR_SHIFT; 3553 } 3554 3555 #define LPFC_EXT_DATA_BDE_COUNT 3 3556 struct fcp_irw_ext { 3557 uint32_t io_tag64_low; 3558 uint32_t io_tag64_high; 3559 #ifdef __BIG_ENDIAN_BITFIELD 3560 uint8_t reserved1; 3561 uint8_t reserved2; 3562 uint8_t reserved3; 3563 uint8_t ebde_count; 3564 #else /* __LITTLE_ENDIAN */ 3565 uint8_t ebde_count; 3566 uint8_t reserved3; 3567 uint8_t reserved2; 3568 uint8_t reserved1; 3569 #endif 3570 uint32_t reserved4; 3571 struct ulp_bde64 rbde; /* response bde */ 3572 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 3573 uint8_t icd[32]; /* immediate command data (32 bytes) */ 3574 }; 3575 3576 typedef struct _IOCB { /* IOCB structure */ 3577 union { 3578 GENERIC_RSP grsp; /* Generic response */ 3579 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3580 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3581 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3582 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3583 A_MXRI64 amxri; /* abort multiple xri command overlay */ 3584 GET_RPI getrpi; /* GET_RPI template */ 3585 FCPI_FIELDS fcpi; /* FCP Initiator template */ 3586 FCPT_FIELDS fcpt; /* FCP target template */ 3587 3588 /* SLI-2 structures */ 3589 3590 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3591 * bde_64s */ 3592 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3593 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3594 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3595 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3596 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3597 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 3598 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 3599 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 3600 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3601 struct sli4_bls_acc bls_acc; /* UNSOL ABTS BLS_ACC params */ 3602 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3603 } un; 3604 union { 3605 struct { 3606 #ifdef __BIG_ENDIAN_BITFIELD 3607 uint16_t ulpContext; /* High order bits word 6 */ 3608 uint16_t ulpIoTag; /* Low order bits word 6 */ 3609 #else /* __LITTLE_ENDIAN_BITFIELD */ 3610 uint16_t ulpIoTag; /* Low order bits word 6 */ 3611 uint16_t ulpContext; /* High order bits word 6 */ 3612 #endif 3613 } t1; 3614 struct { 3615 #ifdef __BIG_ENDIAN_BITFIELD 3616 uint16_t ulpContext; /* High order bits word 6 */ 3617 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3618 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3619 #else /* __LITTLE_ENDIAN_BITFIELD */ 3620 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3621 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3622 uint16_t ulpContext; /* High order bits word 6 */ 3623 #endif 3624 } t2; 3625 } un1; 3626 #define ulpContext un1.t1.ulpContext 3627 #define ulpIoTag un1.t1.ulpIoTag 3628 #define ulpIoTag0 un1.t2.ulpIoTag0 3629 3630 #ifdef __BIG_ENDIAN_BITFIELD 3631 uint32_t ulpTimeout:8; 3632 uint32_t ulpXS:1; 3633 uint32_t ulpFCP2Rcvy:1; 3634 uint32_t ulpPU:2; 3635 uint32_t ulpIr:1; 3636 uint32_t ulpClass:3; 3637 uint32_t ulpCommand:8; 3638 uint32_t ulpStatus:4; 3639 uint32_t ulpBdeCount:2; 3640 uint32_t ulpLe:1; 3641 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3642 #else /* __LITTLE_ENDIAN_BITFIELD */ 3643 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3644 uint32_t ulpLe:1; 3645 uint32_t ulpBdeCount:2; 3646 uint32_t ulpStatus:4; 3647 uint32_t ulpCommand:8; 3648 uint32_t ulpClass:3; 3649 uint32_t ulpIr:1; 3650 uint32_t ulpPU:2; 3651 uint32_t ulpFCP2Rcvy:1; 3652 uint32_t ulpXS:1; 3653 uint32_t ulpTimeout:8; 3654 #endif 3655 3656 union { 3657 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 3658 3659 /* words 8-31 used for que_xri_cx iocb */ 3660 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 3661 struct fcp_irw_ext fcp_ext; 3662 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 3663 3664 /* words 8-15 for BlockGuard */ 3665 struct sli3_bg_fields sli3_bg; 3666 } unsli3; 3667 3668 #define ulpCt_h ulpXS 3669 #define ulpCt_l ulpFCP2Rcvy 3670 3671 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3672 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3673 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3674 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3675 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3676 #define PARM_NPIV_DID 3 3677 #define CLASS1 0 /* Class 1 */ 3678 #define CLASS2 1 /* Class 2 */ 3679 #define CLASS3 2 /* Class 3 */ 3680 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3681 3682 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3683 #define IOSTAT_FCP_RSP_ERROR 0x1 3684 #define IOSTAT_REMOTE_STOP 0x2 3685 #define IOSTAT_LOCAL_REJECT 0x3 3686 #define IOSTAT_NPORT_RJT 0x4 3687 #define IOSTAT_FABRIC_RJT 0x5 3688 #define IOSTAT_NPORT_BSY 0x6 3689 #define IOSTAT_FABRIC_BSY 0x7 3690 #define IOSTAT_INTERMED_RSP 0x8 3691 #define IOSTAT_LS_RJT 0x9 3692 #define IOSTAT_BA_RJT 0xA 3693 #define IOSTAT_RSVD1 0xB 3694 #define IOSTAT_RSVD2 0xC 3695 #define IOSTAT_RSVD3 0xD 3696 #define IOSTAT_RSVD4 0xE 3697 #define IOSTAT_NEED_BUFFER 0xF 3698 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3699 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3700 #define IOSTAT_CNT 0x11 3701 3702 } IOCB_t; 3703 3704 3705 #define SLI1_SLIM_SIZE (4 * 1024) 3706 3707 /* Up to 498 IOCBs will fit into 16k 3708 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3709 */ 3710 #define SLI2_SLIM_SIZE (64 * 1024) 3711 3712 /* Maximum IOCBs that will fit in SLI2 slim */ 3713 #define MAX_SLI2_IOCB 498 3714 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3715 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 3716 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 3717 3718 /* HBQ entries are 4 words each = 4k */ 3719 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3720 lpfc_sli_hbq_count()) 3721 3722 struct lpfc_sli2_slim { 3723 MAILBOX_t mbx; 3724 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 3725 PCB_t pcb; 3726 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3727 }; 3728 3729 /* 3730 * This function checks PCI device to allow special handling for LC HBAs. 3731 * 3732 * Parameters: 3733 * device : struct pci_dev 's device field 3734 * 3735 * return 1 => TRUE 3736 * 0 => FALSE 3737 */ 3738 static inline int 3739 lpfc_is_LC_HBA(unsigned short device) 3740 { 3741 if ((device == PCI_DEVICE_ID_TFLY) || 3742 (device == PCI_DEVICE_ID_PFLY) || 3743 (device == PCI_DEVICE_ID_LP101) || 3744 (device == PCI_DEVICE_ID_BMID) || 3745 (device == PCI_DEVICE_ID_BSMB) || 3746 (device == PCI_DEVICE_ID_ZMID) || 3747 (device == PCI_DEVICE_ID_ZSMB) || 3748 (device == PCI_DEVICE_ID_SAT_MID) || 3749 (device == PCI_DEVICE_ID_SAT_SMB) || 3750 (device == PCI_DEVICE_ID_RFLY)) 3751 return 1; 3752 else 3753 return 0; 3754 } 3755 3756 /* 3757 * Determine if an IOCB failed because of a link event or firmware reset. 3758 */ 3759 3760 static inline int 3761 lpfc_error_lost_link(IOCB_t *iocbp) 3762 { 3763 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3764 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3765 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3766 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3767 } 3768 3769 #define MENLO_TRANSPORT_TYPE 0xfe 3770 #define MENLO_CONTEXT 0 3771 #define MENLO_PU 3 3772 #define MENLO_TIMEOUT 30 3773 #define SETVAR_MLOMNT 0x103107 3774 #define SETVAR_MLORST 0x103007 3775 3776 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 3777