1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2008 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 #define SLI2_IOCB_CMD_SIZE 32 63 #define SLI2_IOCB_RSP_SIZE 32 64 #define SLI3_IOCB_CMD_SIZE 128 65 #define SLI3_IOCB_RSP_SIZE 64 66 67 68 /* vendor ID used in SCSI netlink calls */ 69 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 70 71 /* Common Transport structures and definitions */ 72 73 union CtRevisionId { 74 /* Structure is in Big Endian format */ 75 struct { 76 uint32_t Revision:8; 77 uint32_t InId:24; 78 } bits; 79 uint32_t word; 80 }; 81 82 union CtCommandResponse { 83 /* Structure is in Big Endian format */ 84 struct { 85 uint32_t CmdRsp:16; 86 uint32_t Size:16; 87 } bits; 88 uint32_t word; 89 }; 90 91 #define FC4_FEATURE_INIT 0x2 92 #define FC4_FEATURE_TARGET 0x1 93 94 struct lpfc_sli_ct_request { 95 /* Structure is in Big Endian format */ 96 union CtRevisionId RevisionId; 97 uint8_t FsType; 98 uint8_t FsSubType; 99 uint8_t Options; 100 uint8_t Rsrvd1; 101 union CtCommandResponse CommandResponse; 102 uint8_t Rsrvd2; 103 uint8_t ReasonCode; 104 uint8_t Explanation; 105 uint8_t VendorUnique; 106 107 union { 108 uint32_t PortID; 109 struct gid { 110 uint8_t PortType; /* for GID_PT requests */ 111 uint8_t DomainScope; 112 uint8_t AreaScope; 113 uint8_t Fc4Type; /* for GID_FT requests */ 114 } gid; 115 struct rft { 116 uint32_t PortId; /* For RFT_ID requests */ 117 118 #ifdef __BIG_ENDIAN_BITFIELD 119 uint32_t rsvd0:16; 120 uint32_t rsvd1:7; 121 uint32_t fcpReg:1; /* Type 8 */ 122 uint32_t rsvd2:2; 123 uint32_t ipReg:1; /* Type 5 */ 124 uint32_t rsvd3:5; 125 #else /* __LITTLE_ENDIAN_BITFIELD */ 126 uint32_t rsvd0:16; 127 uint32_t fcpReg:1; /* Type 8 */ 128 uint32_t rsvd1:7; 129 uint32_t rsvd3:5; 130 uint32_t ipReg:1; /* Type 5 */ 131 uint32_t rsvd2:2; 132 #endif 133 134 uint32_t rsvd[7]; 135 } rft; 136 struct rnn { 137 uint32_t PortId; /* For RNN_ID requests */ 138 uint8_t wwnn[8]; 139 } rnn; 140 struct rsnn { /* For RSNN_ID requests */ 141 uint8_t wwnn[8]; 142 uint8_t len; 143 uint8_t symbname[255]; 144 } rsnn; 145 struct da_id { /* For DA_ID requests */ 146 uint32_t port_id; 147 } da_id; 148 struct rspn { /* For RSPN_ID requests */ 149 uint32_t PortId; 150 uint8_t len; 151 uint8_t symbname[255]; 152 } rspn; 153 struct gff { 154 uint32_t PortId; 155 } gff; 156 struct gff_acc { 157 uint8_t fbits[128]; 158 } gff_acc; 159 #define FCP_TYPE_FEATURE_OFFSET 7 160 struct rff { 161 uint32_t PortId; 162 uint8_t reserved[2]; 163 uint8_t fbits; 164 uint8_t type_code; /* type=8 for FCP */ 165 } rff; 166 } un; 167 }; 168 169 #define SLI_CT_REVISION 1 170 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 171 sizeof(struct gid)) 172 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 173 sizeof(struct gff)) 174 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 175 sizeof(struct rft)) 176 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 177 sizeof(struct rff)) 178 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 179 sizeof(struct rnn)) 180 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 181 sizeof(struct rsnn)) 182 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 183 sizeof(struct da_id)) 184 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 185 sizeof(struct rspn)) 186 187 /* 188 * FsType Definitions 189 */ 190 191 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 192 #define SLI_CT_TIME_SERVICE 0xFB 193 #define SLI_CT_DIRECTORY_SERVICE 0xFC 194 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 195 196 /* 197 * Directory Service Subtypes 198 */ 199 200 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 201 202 /* 203 * Response Codes 204 */ 205 206 #define SLI_CT_RESPONSE_FS_RJT 0x8001 207 #define SLI_CT_RESPONSE_FS_ACC 0x8002 208 209 /* 210 * Reason Codes 211 */ 212 213 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 214 #define SLI_CT_INVALID_COMMAND 0x01 215 #define SLI_CT_INVALID_VERSION 0x02 216 #define SLI_CT_LOGICAL_ERROR 0x03 217 #define SLI_CT_INVALID_IU_SIZE 0x04 218 #define SLI_CT_LOGICAL_BUSY 0x05 219 #define SLI_CT_PROTOCOL_ERROR 0x07 220 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 221 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 222 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 223 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 224 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 225 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 226 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 227 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 228 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 229 #define SLI_CT_VENDOR_UNIQUE 0xff 230 231 /* 232 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 233 */ 234 235 #define SLI_CT_NO_PORT_ID 0x01 236 #define SLI_CT_NO_PORT_NAME 0x02 237 #define SLI_CT_NO_NODE_NAME 0x03 238 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 239 #define SLI_CT_NO_IP_ADDRESS 0x05 240 #define SLI_CT_NO_IPA 0x06 241 #define SLI_CT_NO_FC4_TYPES 0x07 242 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 243 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 244 #define SLI_CT_NO_PORT_TYPE 0x0A 245 #define SLI_CT_ACCESS_DENIED 0x10 246 #define SLI_CT_INVALID_PORT_ID 0x11 247 #define SLI_CT_DATABASE_EMPTY 0x12 248 249 /* 250 * Name Server Command Codes 251 */ 252 253 #define SLI_CTNS_GA_NXT 0x0100 254 #define SLI_CTNS_GPN_ID 0x0112 255 #define SLI_CTNS_GNN_ID 0x0113 256 #define SLI_CTNS_GCS_ID 0x0114 257 #define SLI_CTNS_GFT_ID 0x0117 258 #define SLI_CTNS_GSPN_ID 0x0118 259 #define SLI_CTNS_GPT_ID 0x011A 260 #define SLI_CTNS_GFF_ID 0x011F 261 #define SLI_CTNS_GID_PN 0x0121 262 #define SLI_CTNS_GID_NN 0x0131 263 #define SLI_CTNS_GIP_NN 0x0135 264 #define SLI_CTNS_GIPA_NN 0x0136 265 #define SLI_CTNS_GSNN_NN 0x0139 266 #define SLI_CTNS_GNN_IP 0x0153 267 #define SLI_CTNS_GIPA_IP 0x0156 268 #define SLI_CTNS_GID_FT 0x0171 269 #define SLI_CTNS_GID_PT 0x01A1 270 #define SLI_CTNS_RPN_ID 0x0212 271 #define SLI_CTNS_RNN_ID 0x0213 272 #define SLI_CTNS_RCS_ID 0x0214 273 #define SLI_CTNS_RFT_ID 0x0217 274 #define SLI_CTNS_RSPN_ID 0x0218 275 #define SLI_CTNS_RPT_ID 0x021A 276 #define SLI_CTNS_RFF_ID 0x021F 277 #define SLI_CTNS_RIP_NN 0x0235 278 #define SLI_CTNS_RIPA_NN 0x0236 279 #define SLI_CTNS_RSNN_NN 0x0239 280 #define SLI_CTNS_DA_ID 0x0300 281 282 /* 283 * Port Types 284 */ 285 286 #define SLI_CTPT_N_PORT 0x01 287 #define SLI_CTPT_NL_PORT 0x02 288 #define SLI_CTPT_FNL_PORT 0x03 289 #define SLI_CTPT_IP 0x04 290 #define SLI_CTPT_FCP 0x08 291 #define SLI_CTPT_NX_PORT 0x7F 292 #define SLI_CTPT_F_PORT 0x81 293 #define SLI_CTPT_FL_PORT 0x82 294 #define SLI_CTPT_E_PORT 0x84 295 296 #define SLI_CT_LAST_ENTRY 0x80000000 297 298 /* Fibre Channel Service Parameter definitions */ 299 300 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 301 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 302 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 303 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 304 305 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 306 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 307 #define FC_PH3 0x20 /* FC-PH-3 version */ 308 309 #define FF_FRAME_SIZE 2048 310 311 struct lpfc_name { 312 union { 313 struct { 314 #ifdef __BIG_ENDIAN_BITFIELD 315 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 317 8:11 of IEEE ext */ 318 #else /* __LITTLE_ENDIAN_BITFIELD */ 319 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 320 8:11 of IEEE ext */ 321 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 322 #endif 323 324 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 325 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 326 #define NAME_FC_TYPE 0x3 /* FC native name type */ 327 #define NAME_IP_TYPE 0x4 /* IP address */ 328 #define NAME_CCITT_TYPE 0xC 329 #define NAME_CCITT_GR_TYPE 0xE 330 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 331 extended Lsb */ 332 uint8_t IEEE[6]; /* FC IEEE address */ 333 } s; 334 uint8_t wwn[8]; 335 } u; 336 }; 337 338 struct csp { 339 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 340 uint8_t fcphLow; 341 uint8_t bbCreditMsb; 342 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 343 344 #ifdef __BIG_ENDIAN_BITFIELD 345 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 346 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 347 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 348 uint16_t fPort:1; /* FC Word 1, bit 28 */ 349 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 350 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 351 uint16_t multicast:1; /* FC Word 1, bit 25 */ 352 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 353 354 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 355 uint16_t simplex:1; /* FC Word 1, bit 22 */ 356 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 357 uint16_t dhd:1; /* FC Word 1, bit 18 */ 358 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 359 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 360 #else /* __LITTLE_ENDIAN_BITFIELD */ 361 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 362 uint16_t multicast:1; /* FC Word 1, bit 25 */ 363 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 364 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 365 uint16_t fPort:1; /* FC Word 1, bit 28 */ 366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 367 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 368 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 369 370 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 371 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 372 uint16_t dhd:1; /* FC Word 1, bit 18 */ 373 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 374 uint16_t simplex:1; /* FC Word 1, bit 22 */ 375 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 376 #endif 377 378 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 379 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 380 union { 381 struct { 382 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 383 384 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 385 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 386 387 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 388 } nPort; 389 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 390 } w2; 391 392 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 393 }; 394 395 struct class_parms { 396 #ifdef __BIG_ENDIAN_BITFIELD 397 uint8_t classValid:1; /* FC Word 0, bit 31 */ 398 uint8_t intermix:1; /* FC Word 0, bit 30 */ 399 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 400 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 401 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 402 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 403 #else /* __LITTLE_ENDIAN_BITFIELD */ 404 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 405 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 406 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 407 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 408 uint8_t intermix:1; /* FC Word 0, bit 30 */ 409 uint8_t classValid:1; /* FC Word 0, bit 31 */ 410 411 #endif 412 413 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 414 415 #ifdef __BIG_ENDIAN_BITFIELD 416 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 417 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 418 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 419 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 420 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 421 #else /* __LITTLE_ENDIAN_BITFIELD */ 422 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 423 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 424 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 425 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 426 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 427 #endif 428 429 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 430 431 #ifdef __BIG_ENDIAN_BITFIELD 432 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 433 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 435 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 436 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 437 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 438 #else /* __LITTLE_ENDIAN_BITFIELD */ 439 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 440 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 441 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 442 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 443 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 444 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 445 #endif 446 447 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 448 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 449 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 450 451 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 452 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 453 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 454 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 455 456 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 457 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 458 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 459 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 460 }; 461 462 struct serv_parm { /* Structure is in Big Endian format */ 463 struct csp cmn; 464 struct lpfc_name portName; 465 struct lpfc_name nodeName; 466 struct class_parms cls1; 467 struct class_parms cls2; 468 struct class_parms cls3; 469 struct class_parms cls4; 470 uint8_t vendorVersion[16]; 471 }; 472 473 /* 474 * Extended Link Service LS_COMMAND codes (Payload Word 0) 475 */ 476 #ifdef __BIG_ENDIAN_BITFIELD 477 #define ELS_CMD_MASK 0xffff0000 478 #define ELS_RSP_MASK 0xff000000 479 #define ELS_CMD_LS_RJT 0x01000000 480 #define ELS_CMD_ACC 0x02000000 481 #define ELS_CMD_PLOGI 0x03000000 482 #define ELS_CMD_FLOGI 0x04000000 483 #define ELS_CMD_LOGO 0x05000000 484 #define ELS_CMD_ABTX 0x06000000 485 #define ELS_CMD_RCS 0x07000000 486 #define ELS_CMD_RES 0x08000000 487 #define ELS_CMD_RSS 0x09000000 488 #define ELS_CMD_RSI 0x0A000000 489 #define ELS_CMD_ESTS 0x0B000000 490 #define ELS_CMD_ESTC 0x0C000000 491 #define ELS_CMD_ADVC 0x0D000000 492 #define ELS_CMD_RTV 0x0E000000 493 #define ELS_CMD_RLS 0x0F000000 494 #define ELS_CMD_ECHO 0x10000000 495 #define ELS_CMD_TEST 0x11000000 496 #define ELS_CMD_RRQ 0x12000000 497 #define ELS_CMD_PRLI 0x20100014 498 #define ELS_CMD_PRLO 0x21100014 499 #define ELS_CMD_PRLO_ACC 0x02100014 500 #define ELS_CMD_PDISC 0x50000000 501 #define ELS_CMD_FDISC 0x51000000 502 #define ELS_CMD_ADISC 0x52000000 503 #define ELS_CMD_FARP 0x54000000 504 #define ELS_CMD_FARPR 0x55000000 505 #define ELS_CMD_RPS 0x56000000 506 #define ELS_CMD_RPL 0x57000000 507 #define ELS_CMD_FAN 0x60000000 508 #define ELS_CMD_RSCN 0x61040000 509 #define ELS_CMD_SCR 0x62000000 510 #define ELS_CMD_RNID 0x78000000 511 #define ELS_CMD_LIRR 0x7A000000 512 #else /* __LITTLE_ENDIAN_BITFIELD */ 513 #define ELS_CMD_MASK 0xffff 514 #define ELS_RSP_MASK 0xff 515 #define ELS_CMD_LS_RJT 0x01 516 #define ELS_CMD_ACC 0x02 517 #define ELS_CMD_PLOGI 0x03 518 #define ELS_CMD_FLOGI 0x04 519 #define ELS_CMD_LOGO 0x05 520 #define ELS_CMD_ABTX 0x06 521 #define ELS_CMD_RCS 0x07 522 #define ELS_CMD_RES 0x08 523 #define ELS_CMD_RSS 0x09 524 #define ELS_CMD_RSI 0x0A 525 #define ELS_CMD_ESTS 0x0B 526 #define ELS_CMD_ESTC 0x0C 527 #define ELS_CMD_ADVC 0x0D 528 #define ELS_CMD_RTV 0x0E 529 #define ELS_CMD_RLS 0x0F 530 #define ELS_CMD_ECHO 0x10 531 #define ELS_CMD_TEST 0x11 532 #define ELS_CMD_RRQ 0x12 533 #define ELS_CMD_PRLI 0x14001020 534 #define ELS_CMD_PRLO 0x14001021 535 #define ELS_CMD_PRLO_ACC 0x14001002 536 #define ELS_CMD_PDISC 0x50 537 #define ELS_CMD_FDISC 0x51 538 #define ELS_CMD_ADISC 0x52 539 #define ELS_CMD_FARP 0x54 540 #define ELS_CMD_FARPR 0x55 541 #define ELS_CMD_RPS 0x56 542 #define ELS_CMD_RPL 0x57 543 #define ELS_CMD_FAN 0x60 544 #define ELS_CMD_RSCN 0x0461 545 #define ELS_CMD_SCR 0x62 546 #define ELS_CMD_RNID 0x78 547 #define ELS_CMD_LIRR 0x7A 548 #endif 549 550 /* 551 * LS_RJT Payload Definition 552 */ 553 554 struct ls_rjt { /* Structure is in Big Endian format */ 555 union { 556 uint32_t lsRjtError; 557 struct { 558 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 559 560 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 561 /* LS_RJT reason codes */ 562 #define LSRJT_INVALID_CMD 0x01 563 #define LSRJT_LOGICAL_ERR 0x03 564 #define LSRJT_LOGICAL_BSY 0x05 565 #define LSRJT_PROTOCOL_ERR 0x07 566 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 567 #define LSRJT_CMD_UNSUPPORTED 0x0B 568 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 569 570 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 571 /* LS_RJT reason explanation */ 572 #define LSEXP_NOTHING_MORE 0x00 573 #define LSEXP_SPARM_OPTIONS 0x01 574 #define LSEXP_SPARM_ICTL 0x03 575 #define LSEXP_SPARM_RCTL 0x05 576 #define LSEXP_SPARM_RCV_SIZE 0x07 577 #define LSEXP_SPARM_CONCUR_SEQ 0x09 578 #define LSEXP_SPARM_CREDIT 0x0B 579 #define LSEXP_INVALID_PNAME 0x0D 580 #define LSEXP_INVALID_NNAME 0x0E 581 #define LSEXP_INVALID_CSP 0x0F 582 #define LSEXP_INVALID_ASSOC_HDR 0x11 583 #define LSEXP_ASSOC_HDR_REQ 0x13 584 #define LSEXP_INVALID_O_SID 0x15 585 #define LSEXP_INVALID_OX_RX 0x17 586 #define LSEXP_CMD_IN_PROGRESS 0x19 587 #define LSEXP_PORT_LOGIN_REQ 0x1E 588 #define LSEXP_INVALID_NPORT_ID 0x1F 589 #define LSEXP_INVALID_SEQ_ID 0x21 590 #define LSEXP_INVALID_XCHG 0x23 591 #define LSEXP_INACTIVE_XCHG 0x25 592 #define LSEXP_RQ_REQUIRED 0x27 593 #define LSEXP_OUT_OF_RESOURCE 0x29 594 #define LSEXP_CANT_GIVE_DATA 0x2A 595 #define LSEXP_REQ_UNSUPPORTED 0x2C 596 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 597 } b; 598 } un; 599 }; 600 601 /* 602 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 603 */ 604 605 typedef struct _LOGO { /* Structure is in Big Endian format */ 606 union { 607 uint32_t nPortId32; /* Access nPortId as a word */ 608 struct { 609 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 610 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 611 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 612 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 613 } b; 614 } un; 615 struct lpfc_name portName; /* N_port name field */ 616 } LOGO; 617 618 /* 619 * FCP Login (PRLI Request / ACC) Payload Definition 620 */ 621 622 #define PRLX_PAGE_LEN 0x10 623 #define TPRLO_PAGE_LEN 0x14 624 625 typedef struct _PRLI { /* Structure is in Big Endian format */ 626 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 627 628 #define PRLI_FCP_TYPE 0x08 629 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 630 631 #ifdef __BIG_ENDIAN_BITFIELD 632 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 633 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 634 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 635 636 /* ACC = imagePairEstablished */ 637 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 638 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 639 #else /* __LITTLE_ENDIAN_BITFIELD */ 640 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 641 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 642 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 643 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 644 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 645 /* ACC = imagePairEstablished */ 646 #endif 647 648 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 649 #define PRLI_NO_RESOURCES 0x2 650 #define PRLI_INIT_INCOMPLETE 0x3 651 #define PRLI_NO_SUCH_PA 0x4 652 #define PRLI_PREDEF_CONFIG 0x5 653 #define PRLI_PARTIAL_SUCCESS 0x6 654 #define PRLI_INVALID_PAGE_CNT 0x7 655 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 656 657 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 658 659 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 660 661 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 662 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 663 664 #ifdef __BIG_ENDIAN_BITFIELD 665 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 666 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 667 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 668 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 669 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 670 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 671 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 672 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 673 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 674 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 675 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 676 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 677 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 678 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 679 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 680 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 681 #else /* __LITTLE_ENDIAN_BITFIELD */ 682 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 683 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 684 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 685 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 686 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 687 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 688 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 689 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 690 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 691 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 692 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 693 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 694 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 695 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 696 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 697 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 698 #endif 699 } PRLI; 700 701 /* 702 * FCP Logout (PRLO Request / ACC) Payload Definition 703 */ 704 705 typedef struct _PRLO { /* Structure is in Big Endian format */ 706 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 707 708 #define PRLO_FCP_TYPE 0x08 709 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 710 711 #ifdef __BIG_ENDIAN_BITFIELD 712 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 713 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 714 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 715 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 716 #else /* __LITTLE_ENDIAN_BITFIELD */ 717 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 718 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 719 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 720 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 721 #endif 722 723 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 724 #define PRLO_NO_SUCH_IMAGE 0x4 725 #define PRLO_INVALID_PAGE_CNT 0x7 726 727 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 728 729 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 730 731 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 732 733 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 734 } PRLO; 735 736 typedef struct _ADISC { /* Structure is in Big Endian format */ 737 uint32_t hardAL_PA; 738 struct lpfc_name portName; 739 struct lpfc_name nodeName; 740 uint32_t DID; 741 } ADISC; 742 743 typedef struct _FARP { /* Structure is in Big Endian format */ 744 uint32_t Mflags:8; 745 uint32_t Odid:24; 746 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 747 action */ 748 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 749 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 750 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 751 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 752 supported */ 753 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 754 supported */ 755 uint32_t Rflags:8; 756 uint32_t Rdid:24; 757 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 758 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 759 struct lpfc_name OportName; 760 struct lpfc_name OnodeName; 761 struct lpfc_name RportName; 762 struct lpfc_name RnodeName; 763 uint8_t Oipaddr[16]; 764 uint8_t Ripaddr[16]; 765 } FARP; 766 767 typedef struct _FAN { /* Structure is in Big Endian format */ 768 uint32_t Fdid; 769 struct lpfc_name FportName; 770 struct lpfc_name FnodeName; 771 } FAN; 772 773 typedef struct _SCR { /* Structure is in Big Endian format */ 774 uint8_t resvd1; 775 uint8_t resvd2; 776 uint8_t resvd3; 777 uint8_t Function; 778 #define SCR_FUNC_FABRIC 0x01 779 #define SCR_FUNC_NPORT 0x02 780 #define SCR_FUNC_FULL 0x03 781 #define SCR_CLEAR 0xff 782 } SCR; 783 784 typedef struct _RNID_TOP_DISC { 785 struct lpfc_name portName; 786 uint8_t resvd[8]; 787 uint32_t unitType; 788 #define RNID_HBA 0x7 789 #define RNID_HOST 0xa 790 #define RNID_DRIVER 0xd 791 uint32_t physPort; 792 uint32_t attachedNodes; 793 uint16_t ipVersion; 794 #define RNID_IPV4 0x1 795 #define RNID_IPV6 0x2 796 uint16_t UDPport; 797 uint8_t ipAddr[16]; 798 uint16_t resvd1; 799 uint16_t flags; 800 #define RNID_TD_SUPPORT 0x1 801 #define RNID_LP_VALID 0x2 802 } RNID_TOP_DISC; 803 804 typedef struct _RNID { /* Structure is in Big Endian format */ 805 uint8_t Format; 806 #define RNID_TOPOLOGY_DISC 0xdf 807 uint8_t CommonLen; 808 uint8_t resvd1; 809 uint8_t SpecificLen; 810 struct lpfc_name portName; 811 struct lpfc_name nodeName; 812 union { 813 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 814 } un; 815 } RNID; 816 817 typedef struct _RPS { /* Structure is in Big Endian format */ 818 union { 819 uint32_t portNum; 820 struct lpfc_name portName; 821 } un; 822 } RPS; 823 824 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 825 uint16_t rsvd1; 826 uint16_t portStatus; 827 uint32_t linkFailureCnt; 828 uint32_t lossSyncCnt; 829 uint32_t lossSignalCnt; 830 uint32_t primSeqErrCnt; 831 uint32_t invalidXmitWord; 832 uint32_t crcCnt; 833 } RPS_RSP; 834 835 typedef struct _RPL { /* Structure is in Big Endian format */ 836 uint32_t maxsize; 837 uint32_t index; 838 } RPL; 839 840 typedef struct _PORT_NUM_BLK { 841 uint32_t portNum; 842 uint32_t portID; 843 struct lpfc_name portName; 844 } PORT_NUM_BLK; 845 846 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 847 uint32_t listLen; 848 uint32_t index; 849 PORT_NUM_BLK port_num_blk; 850 } RPL_RSP; 851 852 /* This is used for RSCN command */ 853 typedef struct _D_ID { /* Structure is in Big Endian format */ 854 union { 855 uint32_t word; 856 struct { 857 #ifdef __BIG_ENDIAN_BITFIELD 858 uint8_t resv; 859 uint8_t domain; 860 uint8_t area; 861 uint8_t id; 862 #else /* __LITTLE_ENDIAN_BITFIELD */ 863 uint8_t id; 864 uint8_t area; 865 uint8_t domain; 866 uint8_t resv; 867 #endif 868 } b; 869 } un; 870 } D_ID; 871 872 #define RSCN_ADDRESS_FORMAT_PORT 0x0 873 #define RSCN_ADDRESS_FORMAT_AREA 0x1 874 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 875 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 876 #define RSCN_ADDRESS_FORMAT_MASK 0x3 877 878 /* 879 * Structure to define all ELS Payload types 880 */ 881 882 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 883 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 884 uint8_t elsByte1; 885 uint8_t elsByte2; 886 uint8_t elsByte3; 887 union { 888 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 889 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 890 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 891 PRLI prli; /* Payload for PRLI/ACC */ 892 PRLO prlo; /* Payload for PRLO/ACC */ 893 ADISC adisc; /* Payload for ADISC/ACC */ 894 FARP farp; /* Payload for FARP/ACC */ 895 FAN fan; /* Payload for FAN */ 896 SCR scr; /* Payload for SCR/ACC */ 897 RNID rnid; /* Payload for RNID */ 898 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 899 } un; 900 } ELS_PKT; 901 902 /* 903 * FDMI 904 * HBA MAnagement Operations Command Codes 905 */ 906 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 907 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 908 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 909 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 910 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 911 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 912 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 913 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 914 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 915 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 916 917 /* 918 * Management Service Subtypes 919 */ 920 #define SLI_CT_FDMI_Subtypes 0x10 921 922 /* 923 * HBA Management Service Reject Code 924 */ 925 #define REJECT_CODE 0x9 /* Unable to perform command request */ 926 927 /* 928 * HBA Management Service Reject Reason Code 929 * Please refer to the Reason Codes above 930 */ 931 932 /* 933 * HBA Attribute Types 934 */ 935 #define NODE_NAME 0x1 936 #define MANUFACTURER 0x2 937 #define SERIAL_NUMBER 0x3 938 #define MODEL 0x4 939 #define MODEL_DESCRIPTION 0x5 940 #define HARDWARE_VERSION 0x6 941 #define DRIVER_VERSION 0x7 942 #define OPTION_ROM_VERSION 0x8 943 #define FIRMWARE_VERSION 0x9 944 #define OS_NAME_VERSION 0xa 945 #define MAX_CT_PAYLOAD_LEN 0xb 946 947 /* 948 * Port Attrubute Types 949 */ 950 #define SUPPORTED_FC4_TYPES 0x1 951 #define SUPPORTED_SPEED 0x2 952 #define PORT_SPEED 0x3 953 #define MAX_FRAME_SIZE 0x4 954 #define OS_DEVICE_NAME 0x5 955 #define HOST_NAME 0x6 956 957 union AttributesDef { 958 /* Structure is in Big Endian format */ 959 struct { 960 uint32_t AttrType:16; 961 uint32_t AttrLen:16; 962 } bits; 963 uint32_t word; 964 }; 965 966 967 /* 968 * HBA Attribute Entry (8 - 260 bytes) 969 */ 970 typedef struct { 971 union AttributesDef ad; 972 union { 973 uint32_t VendorSpecific; 974 uint8_t Manufacturer[64]; 975 uint8_t SerialNumber[64]; 976 uint8_t Model[256]; 977 uint8_t ModelDescription[256]; 978 uint8_t HardwareVersion[256]; 979 uint8_t DriverVersion[256]; 980 uint8_t OptionROMVersion[256]; 981 uint8_t FirmwareVersion[256]; 982 struct lpfc_name NodeName; 983 uint8_t SupportFC4Types[32]; 984 uint32_t SupportSpeed; 985 uint32_t PortSpeed; 986 uint32_t MaxFrameSize; 987 uint8_t OsDeviceName[256]; 988 uint8_t OsNameVersion[256]; 989 uint32_t MaxCTPayloadLen; 990 uint8_t HostName[256]; 991 } un; 992 } ATTRIBUTE_ENTRY; 993 994 /* 995 * HBA Attribute Block 996 */ 997 typedef struct { 998 uint32_t EntryCnt; /* Number of HBA attribute entries */ 999 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 1000 } ATTRIBUTE_BLOCK; 1001 1002 /* 1003 * Port Entry 1004 */ 1005 typedef struct { 1006 struct lpfc_name PortName; 1007 } PORT_ENTRY; 1008 1009 /* 1010 * HBA Identifier 1011 */ 1012 typedef struct { 1013 struct lpfc_name PortName; 1014 } HBA_IDENTIFIER; 1015 1016 /* 1017 * Registered Port List Format 1018 */ 1019 typedef struct { 1020 uint32_t EntryCnt; 1021 PORT_ENTRY pe; /* Variable-length array */ 1022 } REG_PORT_LIST; 1023 1024 /* 1025 * Register HBA(RHBA) 1026 */ 1027 typedef struct { 1028 HBA_IDENTIFIER hi; 1029 REG_PORT_LIST rpl; /* variable-length array */ 1030 /* ATTRIBUTE_BLOCK ab; */ 1031 } REG_HBA; 1032 1033 /* 1034 * Register HBA Attributes (RHAT) 1035 */ 1036 typedef struct { 1037 struct lpfc_name HBA_PortName; 1038 ATTRIBUTE_BLOCK ab; 1039 } REG_HBA_ATTRIBUTE; 1040 1041 /* 1042 * Register Port Attributes (RPA) 1043 */ 1044 typedef struct { 1045 struct lpfc_name PortName; 1046 ATTRIBUTE_BLOCK ab; 1047 } REG_PORT_ATTRIBUTE; 1048 1049 /* 1050 * Get Registered HBA List (GRHL) Accept Payload Format 1051 */ 1052 typedef struct { 1053 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1054 struct lpfc_name HBA_PortName; /* Variable-length array */ 1055 } GRHL_ACC_PAYLOAD; 1056 1057 /* 1058 * Get Registered Port List (GRPL) Accept Payload Format 1059 */ 1060 typedef struct { 1061 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1062 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1063 } GRPL_ACC_PAYLOAD; 1064 1065 /* 1066 * Get Port Attributes (GPAT) Accept Payload Format 1067 */ 1068 1069 typedef struct { 1070 ATTRIBUTE_BLOCK pab; 1071 } GPAT_ACC_PAYLOAD; 1072 1073 1074 /* 1075 * Begin HBA configuration parameters. 1076 * The PCI configuration register BAR assignments are: 1077 * BAR0, offset 0x10 - SLIM base memory address 1078 * BAR1, offset 0x14 - SLIM base memory high address 1079 * BAR2, offset 0x18 - REGISTER base memory address 1080 * BAR3, offset 0x1c - REGISTER base memory high address 1081 * BAR4, offset 0x20 - BIU I/O registers 1082 * BAR5, offset 0x24 - REGISTER base io high address 1083 */ 1084 1085 /* Number of rings currently used and available. */ 1086 #define MAX_CONFIGURED_RINGS 3 1087 #define MAX_RINGS 4 1088 1089 /* IOCB / Mailbox is owned by FireFly */ 1090 #define OWN_CHIP 1 1091 1092 /* IOCB / Mailbox is owned by Host */ 1093 #define OWN_HOST 0 1094 1095 /* Number of 4-byte words in an IOCB. */ 1096 #define IOCB_WORD_SZ 8 1097 1098 /* defines for type field in fc header */ 1099 #define FC_ELS_DATA 0x1 1100 #define FC_LLC_SNAP 0x5 1101 #define FC_FCP_DATA 0x8 1102 #define FC_COMMON_TRANSPORT_ULP 0x20 1103 1104 /* defines for rctl field in fc header */ 1105 #define FC_DEV_DATA 0x0 1106 #define FC_UNSOL_CTL 0x2 1107 #define FC_SOL_CTL 0x3 1108 #define FC_UNSOL_DATA 0x4 1109 #define FC_FCP_CMND 0x6 1110 #define FC_ELS_REQ 0x22 1111 #define FC_ELS_RSP 0x23 1112 1113 /* network headers for Dfctl field */ 1114 #define FC_NET_HDR 0x20 1115 1116 /* Start FireFly Register definitions */ 1117 #define PCI_VENDOR_ID_EMULEX 0x10df 1118 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1119 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1120 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1121 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1122 #define PCI_DEVICE_ID_SAT_MID 0xf015 1123 #define PCI_DEVICE_ID_RFLY 0xf095 1124 #define PCI_DEVICE_ID_PFLY 0xf098 1125 #define PCI_DEVICE_ID_LP101 0xf0a1 1126 #define PCI_DEVICE_ID_TFLY 0xf0a5 1127 #define PCI_DEVICE_ID_BSMB 0xf0d1 1128 #define PCI_DEVICE_ID_BMID 0xf0d5 1129 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1130 #define PCI_DEVICE_ID_ZMID 0xf0e5 1131 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1132 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1133 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1134 #define PCI_DEVICE_ID_SAT 0xf100 1135 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1136 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1137 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1138 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1139 #define PCI_DEVICE_ID_CENTAUR 0xf900 1140 #define PCI_DEVICE_ID_PEGASUS 0xf980 1141 #define PCI_DEVICE_ID_THOR 0xfa00 1142 #define PCI_DEVICE_ID_VIPER 0xfb00 1143 #define PCI_DEVICE_ID_LP10000S 0xfc00 1144 #define PCI_DEVICE_ID_LP11000S 0xfc10 1145 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1146 #define PCI_DEVICE_ID_SAT_S 0xfc40 1147 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1148 #define PCI_DEVICE_ID_HELIOS 0xfd00 1149 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1150 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1151 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1152 #define PCI_DEVICE_ID_HORNET 0xfe05 1153 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1154 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1155 1156 #define JEDEC_ID_ADDRESS 0x0080001c 1157 #define FIREFLY_JEDEC_ID 0x1ACC 1158 #define SUPERFLY_JEDEC_ID 0x0020 1159 #define DRAGONFLY_JEDEC_ID 0x0021 1160 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1161 #define CENTAUR_2G_JEDEC_ID 0x0026 1162 #define CENTAUR_1G_JEDEC_ID 0x0028 1163 #define PEGASUS_ORION_JEDEC_ID 0x0036 1164 #define PEGASUS_JEDEC_ID 0x0038 1165 #define THOR_JEDEC_ID 0x0012 1166 #define HELIOS_JEDEC_ID 0x0364 1167 #define ZEPHYR_JEDEC_ID 0x0577 1168 #define VIPER_JEDEC_ID 0x4838 1169 #define SATURN_JEDEC_ID 0x1004 1170 #define HORNET_JDEC_ID 0x2057706D 1171 1172 #define JEDEC_ID_MASK 0x0FFFF000 1173 #define JEDEC_ID_SHIFT 12 1174 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1175 1176 typedef struct { /* FireFly BIU registers */ 1177 uint32_t hostAtt; /* See definitions for Host Attention 1178 register */ 1179 uint32_t chipAtt; /* See definitions for Chip Attention 1180 register */ 1181 uint32_t hostStatus; /* See definitions for Host Status register */ 1182 uint32_t hostControl; /* See definitions for Host Control register */ 1183 uint32_t buiConfig; /* See definitions for BIU configuration 1184 register */ 1185 } FF_REGS; 1186 1187 /* IO Register size in bytes */ 1188 #define FF_REG_AREA_SIZE 256 1189 1190 /* Host Attention Register */ 1191 1192 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1193 1194 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1195 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1196 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1197 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1198 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1199 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1200 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1201 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1202 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1203 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1204 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1205 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1206 #define HA_LATT 0x20000000 /* Bit 29 */ 1207 #define HA_MBATT 0x40000000 /* Bit 30 */ 1208 #define HA_ERATT 0x80000000 /* Bit 31 */ 1209 1210 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1211 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1212 #define HA_RXATT 0x00000008 /* Bit 3 */ 1213 #define HA_RXMASK 0x0000000f 1214 1215 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1216 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1217 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1218 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1219 1220 #define HA_R0_POS 3 1221 #define HA_R1_POS 7 1222 #define HA_R2_POS 11 1223 #define HA_R3_POS 15 1224 #define HA_LE_POS 29 1225 #define HA_MB_POS 30 1226 #define HA_ER_POS 31 1227 /* Chip Attention Register */ 1228 1229 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1230 1231 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1232 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1233 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1234 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1235 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1236 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1237 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1238 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1239 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1240 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1241 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1242 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1243 #define CA_MBATT 0x40000000 /* Bit 30 */ 1244 1245 /* Host Status Register */ 1246 1247 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1248 1249 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1250 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1251 #define HS_FFER8 0x01000000 /* Bit 24 */ 1252 #define HS_FFER7 0x02000000 /* Bit 25 */ 1253 #define HS_FFER6 0x04000000 /* Bit 26 */ 1254 #define HS_FFER5 0x08000000 /* Bit 27 */ 1255 #define HS_FFER4 0x10000000 /* Bit 28 */ 1256 #define HS_FFER3 0x20000000 /* Bit 29 */ 1257 #define HS_FFER2 0x40000000 /* Bit 30 */ 1258 #define HS_FFER1 0x80000000 /* Bit 31 */ 1259 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1260 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1261 1262 /* Host Control Register */ 1263 1264 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1265 1266 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1267 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1268 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1269 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1270 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1271 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1272 #define HC_INITMB 0x04000000 /* Bit 26 */ 1273 #define HC_INITFF 0x08000000 /* Bit 27 */ 1274 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1275 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1276 1277 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1278 #define MSIX_DFLT_ID 0 1279 #define MSIX_RNG0_ID 0 1280 #define MSIX_RNG1_ID 1 1281 #define MSIX_RNG2_ID 2 1282 #define MSIX_RNG3_ID 3 1283 1284 #define MSIX_LINK_ID 4 1285 #define MSIX_MBOX_ID 5 1286 1287 #define MSIX_SPARE0_ID 6 1288 #define MSIX_SPARE1_ID 7 1289 1290 /* Mailbox Commands */ 1291 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1292 #define MBX_LOAD_SM 0x01 1293 #define MBX_READ_NV 0x02 1294 #define MBX_WRITE_NV 0x03 1295 #define MBX_RUN_BIU_DIAG 0x04 1296 #define MBX_INIT_LINK 0x05 1297 #define MBX_DOWN_LINK 0x06 1298 #define MBX_CONFIG_LINK 0x07 1299 #define MBX_CONFIG_RING 0x09 1300 #define MBX_RESET_RING 0x0A 1301 #define MBX_READ_CONFIG 0x0B 1302 #define MBX_READ_RCONFIG 0x0C 1303 #define MBX_READ_SPARM 0x0D 1304 #define MBX_READ_STATUS 0x0E 1305 #define MBX_READ_RPI 0x0F 1306 #define MBX_READ_XRI 0x10 1307 #define MBX_READ_REV 0x11 1308 #define MBX_READ_LNK_STAT 0x12 1309 #define MBX_REG_LOGIN 0x13 1310 #define MBX_UNREG_LOGIN 0x14 1311 #define MBX_READ_LA 0x15 1312 #define MBX_CLEAR_LA 0x16 1313 #define MBX_DUMP_MEMORY 0x17 1314 #define MBX_DUMP_CONTEXT 0x18 1315 #define MBX_RUN_DIAGS 0x19 1316 #define MBX_RESTART 0x1A 1317 #define MBX_UPDATE_CFG 0x1B 1318 #define MBX_DOWN_LOAD 0x1C 1319 #define MBX_DEL_LD_ENTRY 0x1D 1320 #define MBX_RUN_PROGRAM 0x1E 1321 #define MBX_SET_MASK 0x20 1322 #define MBX_SET_VARIABLE 0x21 1323 #define MBX_UNREG_D_ID 0x23 1324 #define MBX_KILL_BOARD 0x24 1325 #define MBX_CONFIG_FARP 0x25 1326 #define MBX_BEACON 0x2A 1327 #define MBX_CONFIG_MSI 0x30 1328 #define MBX_HEARTBEAT 0x31 1329 #define MBX_WRITE_VPARMS 0x32 1330 #define MBX_ASYNCEVT_ENABLE 0x33 1331 1332 #define MBX_PORT_CAPABILITIES 0x3B 1333 #define MBX_PORT_IOV_CONTROL 0x3C 1334 1335 #define MBX_CONFIG_HBQ 0x7C 1336 #define MBX_LOAD_AREA 0x81 1337 #define MBX_RUN_BIU_DIAG64 0x84 1338 #define MBX_CONFIG_PORT 0x88 1339 #define MBX_READ_SPARM64 0x8D 1340 #define MBX_READ_RPI64 0x8F 1341 #define MBX_REG_LOGIN64 0x93 1342 #define MBX_READ_LA64 0x95 1343 #define MBX_REG_VPI 0x96 1344 #define MBX_UNREG_VPI 0x97 1345 #define MBX_REG_VNPID 0x96 1346 #define MBX_UNREG_VNPID 0x97 1347 1348 #define MBX_WRITE_WWN 0x98 1349 #define MBX_SET_DEBUG 0x99 1350 #define MBX_LOAD_EXP_ROM 0x9C 1351 1352 #define MBX_MAX_CMDS 0x9D 1353 #define MBX_SLI2_CMD_MASK 0x80 1354 1355 /* IOCB Commands */ 1356 1357 #define CMD_RCV_SEQUENCE_CX 0x01 1358 #define CMD_XMIT_SEQUENCE_CR 0x02 1359 #define CMD_XMIT_SEQUENCE_CX 0x03 1360 #define CMD_XMIT_BCAST_CN 0x04 1361 #define CMD_XMIT_BCAST_CX 0x05 1362 #define CMD_QUE_RING_BUF_CN 0x06 1363 #define CMD_QUE_XRI_BUF_CX 0x07 1364 #define CMD_IOCB_CONTINUE_CN 0x08 1365 #define CMD_RET_XRI_BUF_CX 0x09 1366 #define CMD_ELS_REQUEST_CR 0x0A 1367 #define CMD_ELS_REQUEST_CX 0x0B 1368 #define CMD_RCV_ELS_REQ_CX 0x0D 1369 #define CMD_ABORT_XRI_CN 0x0E 1370 #define CMD_ABORT_XRI_CX 0x0F 1371 #define CMD_CLOSE_XRI_CN 0x10 1372 #define CMD_CLOSE_XRI_CX 0x11 1373 #define CMD_CREATE_XRI_CR 0x12 1374 #define CMD_CREATE_XRI_CX 0x13 1375 #define CMD_GET_RPI_CN 0x14 1376 #define CMD_XMIT_ELS_RSP_CX 0x15 1377 #define CMD_GET_RPI_CR 0x16 1378 #define CMD_XRI_ABORTED_CX 0x17 1379 #define CMD_FCP_IWRITE_CR 0x18 1380 #define CMD_FCP_IWRITE_CX 0x19 1381 #define CMD_FCP_IREAD_CR 0x1A 1382 #define CMD_FCP_IREAD_CX 0x1B 1383 #define CMD_FCP_ICMND_CR 0x1C 1384 #define CMD_FCP_ICMND_CX 0x1D 1385 #define CMD_FCP_TSEND_CX 0x1F 1386 #define CMD_FCP_TRECEIVE_CX 0x21 1387 #define CMD_FCP_TRSP_CX 0x23 1388 #define CMD_FCP_AUTO_TRSP_CX 0x29 1389 1390 #define CMD_ADAPTER_MSG 0x20 1391 #define CMD_ADAPTER_DUMP 0x22 1392 1393 /* SLI_2 IOCB Command Set */ 1394 1395 #define CMD_ASYNC_STATUS 0x7C 1396 #define CMD_RCV_SEQUENCE64_CX 0x81 1397 #define CMD_XMIT_SEQUENCE64_CR 0x82 1398 #define CMD_XMIT_SEQUENCE64_CX 0x83 1399 #define CMD_XMIT_BCAST64_CN 0x84 1400 #define CMD_XMIT_BCAST64_CX 0x85 1401 #define CMD_QUE_RING_BUF64_CN 0x86 1402 #define CMD_QUE_XRI_BUF64_CX 0x87 1403 #define CMD_IOCB_CONTINUE64_CN 0x88 1404 #define CMD_RET_XRI_BUF64_CX 0x89 1405 #define CMD_ELS_REQUEST64_CR 0x8A 1406 #define CMD_ELS_REQUEST64_CX 0x8B 1407 #define CMD_ABORT_MXRI64_CN 0x8C 1408 #define CMD_RCV_ELS_REQ64_CX 0x8D 1409 #define CMD_XMIT_ELS_RSP64_CX 0x95 1410 #define CMD_FCP_IWRITE64_CR 0x98 1411 #define CMD_FCP_IWRITE64_CX 0x99 1412 #define CMD_FCP_IREAD64_CR 0x9A 1413 #define CMD_FCP_IREAD64_CX 0x9B 1414 #define CMD_FCP_ICMND64_CR 0x9C 1415 #define CMD_FCP_ICMND64_CX 0x9D 1416 #define CMD_FCP_TSEND64_CX 0x9F 1417 #define CMD_FCP_TRECEIVE64_CX 0xA1 1418 #define CMD_FCP_TRSP64_CX 0xA3 1419 1420 #define CMD_QUE_XRI64_CX 0xB3 1421 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1422 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1423 #define CMD_IOCB_RET_XRI64_CX 0xB9 1424 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1425 1426 #define CMD_GEN_REQUEST64_CR 0xC2 1427 #define CMD_GEN_REQUEST64_CX 0xC3 1428 1429 /* Unhandled SLI-3 Commands */ 1430 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1431 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1432 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1433 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1434 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1435 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1436 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1437 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1438 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1439 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1440 #define CMD_IOCB_LOGENTRY_CN 0x94 1441 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1442 1443 #define CMD_MAX_IOCB_CMD 0xE6 1444 #define CMD_IOCB_MASK 0xff 1445 1446 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1447 iocb */ 1448 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1449 /* 1450 * Define Status 1451 */ 1452 #define MBX_SUCCESS 0 1453 #define MBXERR_NUM_RINGS 1 1454 #define MBXERR_NUM_IOCBS 2 1455 #define MBXERR_IOCBS_EXCEEDED 3 1456 #define MBXERR_BAD_RING_NUMBER 4 1457 #define MBXERR_MASK_ENTRIES_RANGE 5 1458 #define MBXERR_MASKS_EXCEEDED 6 1459 #define MBXERR_BAD_PROFILE 7 1460 #define MBXERR_BAD_DEF_CLASS 8 1461 #define MBXERR_BAD_MAX_RESPONDER 9 1462 #define MBXERR_BAD_MAX_ORIGINATOR 10 1463 #define MBXERR_RPI_REGISTERED 11 1464 #define MBXERR_RPI_FULL 12 1465 #define MBXERR_NO_RESOURCES 13 1466 #define MBXERR_BAD_RCV_LENGTH 14 1467 #define MBXERR_DMA_ERROR 15 1468 #define MBXERR_ERROR 16 1469 #define MBX_NOT_FINISHED 255 1470 1471 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1472 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1473 1474 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1475 1476 /* 1477 * Begin Structure Definitions for Mailbox Commands 1478 */ 1479 1480 typedef struct { 1481 #ifdef __BIG_ENDIAN_BITFIELD 1482 uint8_t tval; 1483 uint8_t tmask; 1484 uint8_t rval; 1485 uint8_t rmask; 1486 #else /* __LITTLE_ENDIAN_BITFIELD */ 1487 uint8_t rmask; 1488 uint8_t rval; 1489 uint8_t tmask; 1490 uint8_t tval; 1491 #endif 1492 } RR_REG; 1493 1494 struct ulp_bde { 1495 uint32_t bdeAddress; 1496 #ifdef __BIG_ENDIAN_BITFIELD 1497 uint32_t bdeReserved:4; 1498 uint32_t bdeAddrHigh:4; 1499 uint32_t bdeSize:24; 1500 #else /* __LITTLE_ENDIAN_BITFIELD */ 1501 uint32_t bdeSize:24; 1502 uint32_t bdeAddrHigh:4; 1503 uint32_t bdeReserved:4; 1504 #endif 1505 }; 1506 1507 struct ulp_bde64 { /* SLI-2 */ 1508 union ULP_BDE_TUS { 1509 uint32_t w; 1510 struct { 1511 #ifdef __BIG_ENDIAN_BITFIELD 1512 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1513 VALUE !! */ 1514 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1515 #else /* __LITTLE_ENDIAN_BITFIELD */ 1516 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1517 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1518 VALUE !! */ 1519 #endif 1520 #define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */ 1521 #define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */ 1522 #define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */ 1523 #define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */ 1524 #define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */ 1525 #define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */ 1526 #define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */ 1527 } f; 1528 } tus; 1529 uint32_t addrLow; 1530 uint32_t addrHigh; 1531 }; 1532 1533 typedef struct ULP_BDL { /* SLI-2 */ 1534 #ifdef __BIG_ENDIAN_BITFIELD 1535 uint32_t bdeFlags:8; /* BDL Flags */ 1536 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1537 #else /* __LITTLE_ENDIAN_BITFIELD */ 1538 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1539 uint32_t bdeFlags:8; /* BDL Flags */ 1540 #endif 1541 1542 uint32_t addrLow; /* Address 0:31 */ 1543 uint32_t addrHigh; /* Address 32:63 */ 1544 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1545 } ULP_BDL; 1546 1547 /* 1548 * BlockGuard Definitions 1549 */ 1550 1551 enum lpfc_protgrp_type { 1552 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1553 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1554 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1555 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1556 }; 1557 1558 /* PDE Descriptors */ 1559 #define LPFC_PDE1_DESCRIPTOR 0x81 1560 #define LPFC_PDE2_DESCRIPTOR 0x82 1561 #define LPFC_PDE3_DESCRIPTOR 0x83 1562 1563 /* BlockGuard Profiles */ 1564 enum lpfc_bg_prof_codes { 1565 LPFC_PROF_INVALID, 1566 LPFC_PROF_A1 = 128, /* Full Protection */ 1567 LPFC_PROF_A2, /* Disabled Protection Checks:A2~A4 */ 1568 LPFC_PROF_A3, 1569 LPFC_PROF_A4, 1570 LPFC_PROF_B1, /* Embedded DIFs: B1~B3 */ 1571 LPFC_PROF_B2, 1572 LPFC_PROF_B3, 1573 LPFC_PROF_C1, /* Separate DIFs: C1~C3 */ 1574 LPFC_PROF_C2, 1575 LPFC_PROF_C3, 1576 LPFC_PROF_D1, /* Full Protection */ 1577 LPFC_PROF_D2, /* Partial Protection & Check Disabling */ 1578 LPFC_PROF_D3, 1579 LPFC_PROF_E1, /* E1~E4:out - check-only, in - update apptag */ 1580 LPFC_PROF_E2, 1581 LPFC_PROF_E3, 1582 LPFC_PROF_E4, 1583 LPFC_PROF_F1, /* Full Translation - F1 Prot Descriptor */ 1584 /* F1 Translation BDE */ 1585 LPFC_PROF_ANT1, /* TCP checksum, DIF inline with data buffers */ 1586 LPFC_PROF_AST1, /* TCP checksum, DIF split from data buffer */ 1587 LPFC_PROF_ANT2, 1588 LPFC_PROF_AST2 1589 }; 1590 1591 /* BlockGuard error-control defines */ 1592 #define BG_EC_STOP_ERR 0x00 1593 #define BG_EC_CONT_ERR 0x01 1594 #define BG_EC_IGN_UNINIT_STOP_ERR 0x10 1595 #define BG_EC_IGN_UNINIT_CONT_ERR 0x11 1596 1597 /* PDE (Protection Descriptor Entry) word 0 bit masks and shifts */ 1598 #define PDE_DESC_TYPE_MASK 0xff000000 1599 #define PDE_DESC_TYPE_SHIFT 24 1600 #define PDE_BG_PROFILE_MASK 0x00ff0000 1601 #define PDE_BG_PROFILE_SHIFT 16 1602 #define PDE_BLOCK_LEN_MASK 0x0000fffc 1603 #define PDE_BLOCK_LEN_SHIFT 2 1604 #define PDE_ERR_CTRL_MASK 0x00000003 1605 #define PDE_ERR_CTRL_SHIFT 0 1606 /* PDE word 1 bit masks and shifts */ 1607 #define PDE_APPTAG_MASK_MASK 0xffff0000 1608 #define PDE_APPTAG_MASK_SHIFT 16 1609 #define PDE_APPTAG_VAL_MASK 0x0000ffff 1610 #define PDE_APPTAG_VAL_SHIFT 0 1611 struct lpfc_pde { 1612 uint32_t parms; /* bitfields of descriptor, prof, len, and ec */ 1613 uint32_t apptag; /* bitfields of app tag maskand app tag value */ 1614 uint32_t reftag; /* reference tag occupying all 32 bits */ 1615 }; 1616 1617 /* inline function to set fields in parms of PDE */ 1618 static inline void 1619 lpfc_pde_set_bg_parms(struct lpfc_pde *p, u8 desc, u8 prof, u16 len, u8 ec) 1620 { 1621 uint32_t *wp = &p->parms; 1622 1623 /* spec indicates that adapter appends two 0's to length field */ 1624 len = len >> 2; 1625 1626 *wp &= 0; 1627 *wp |= ((desc << PDE_DESC_TYPE_SHIFT) & PDE_DESC_TYPE_MASK); 1628 *wp |= ((prof << PDE_BG_PROFILE_SHIFT) & PDE_BG_PROFILE_MASK); 1629 *wp |= ((len << PDE_BLOCK_LEN_SHIFT) & PDE_BLOCK_LEN_MASK); 1630 *wp |= ((ec << PDE_ERR_CTRL_SHIFT) & PDE_ERR_CTRL_MASK); 1631 *wp = le32_to_cpu(*wp); 1632 } 1633 1634 /* inline function to set apptag and reftag fields of PDE */ 1635 static inline void 1636 lpfc_pde_set_dif_parms(struct lpfc_pde *p, u16 apptagmask, u16 apptagval, 1637 u32 reftag) 1638 { 1639 uint32_t *wp = &p->apptag; 1640 *wp &= 0; 1641 *wp |= ((apptagmask << PDE_APPTAG_MASK_SHIFT) & PDE_APPTAG_MASK_MASK); 1642 *wp |= ((apptagval << PDE_APPTAG_VAL_SHIFT) & PDE_APPTAG_VAL_MASK); 1643 *wp = le32_to_cpu(*wp); 1644 wp = &p->reftag; 1645 *wp = le32_to_cpu(reftag); 1646 } 1647 1648 1649 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1650 1651 typedef struct { 1652 #ifdef __BIG_ENDIAN_BITFIELD 1653 uint32_t rsvd2:25; 1654 uint32_t acknowledgment:1; 1655 uint32_t version:1; 1656 uint32_t erase_or_prog:1; 1657 uint32_t update_flash:1; 1658 uint32_t update_ram:1; 1659 uint32_t method:1; 1660 uint32_t load_cmplt:1; 1661 #else /* __LITTLE_ENDIAN_BITFIELD */ 1662 uint32_t load_cmplt:1; 1663 uint32_t method:1; 1664 uint32_t update_ram:1; 1665 uint32_t update_flash:1; 1666 uint32_t erase_or_prog:1; 1667 uint32_t version:1; 1668 uint32_t acknowledgment:1; 1669 uint32_t rsvd2:25; 1670 #endif 1671 1672 uint32_t dl_to_adr_low; 1673 uint32_t dl_to_adr_high; 1674 uint32_t dl_len; 1675 union { 1676 uint32_t dl_from_mbx_offset; 1677 struct ulp_bde dl_from_bde; 1678 struct ulp_bde64 dl_from_bde64; 1679 } un; 1680 1681 } LOAD_SM_VAR; 1682 1683 /* Structure for MB Command READ_NVPARM (02) */ 1684 1685 typedef struct { 1686 uint32_t rsvd1[3]; /* Read as all one's */ 1687 uint32_t rsvd2; /* Read as all zero's */ 1688 uint32_t portname[2]; /* N_PORT name */ 1689 uint32_t nodename[2]; /* NODE name */ 1690 1691 #ifdef __BIG_ENDIAN_BITFIELD 1692 uint32_t pref_DID:24; 1693 uint32_t hardAL_PA:8; 1694 #else /* __LITTLE_ENDIAN_BITFIELD */ 1695 uint32_t hardAL_PA:8; 1696 uint32_t pref_DID:24; 1697 #endif 1698 1699 uint32_t rsvd3[21]; /* Read as all one's */ 1700 } READ_NV_VAR; 1701 1702 /* Structure for MB Command WRITE_NVPARMS (03) */ 1703 1704 typedef struct { 1705 uint32_t rsvd1[3]; /* Must be all one's */ 1706 uint32_t rsvd2; /* Must be all zero's */ 1707 uint32_t portname[2]; /* N_PORT name */ 1708 uint32_t nodename[2]; /* NODE name */ 1709 1710 #ifdef __BIG_ENDIAN_BITFIELD 1711 uint32_t pref_DID:24; 1712 uint32_t hardAL_PA:8; 1713 #else /* __LITTLE_ENDIAN_BITFIELD */ 1714 uint32_t hardAL_PA:8; 1715 uint32_t pref_DID:24; 1716 #endif 1717 1718 uint32_t rsvd3[21]; /* Must be all one's */ 1719 } WRITE_NV_VAR; 1720 1721 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1722 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1723 1724 typedef struct { 1725 uint32_t rsvd1; 1726 union { 1727 struct { 1728 struct ulp_bde xmit_bde; 1729 struct ulp_bde rcv_bde; 1730 } s1; 1731 struct { 1732 struct ulp_bde64 xmit_bde64; 1733 struct ulp_bde64 rcv_bde64; 1734 } s2; 1735 } un; 1736 } BIU_DIAG_VAR; 1737 1738 /* Structure for MB Command INIT_LINK (05) */ 1739 1740 typedef struct { 1741 #ifdef __BIG_ENDIAN_BITFIELD 1742 uint32_t rsvd1:24; 1743 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1744 #else /* __LITTLE_ENDIAN_BITFIELD */ 1745 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1746 uint32_t rsvd1:24; 1747 #endif 1748 1749 #ifdef __BIG_ENDIAN_BITFIELD 1750 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1751 uint8_t rsvd2; 1752 uint16_t link_flags; 1753 #else /* __LITTLE_ENDIAN_BITFIELD */ 1754 uint16_t link_flags; 1755 uint8_t rsvd2; 1756 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1757 #endif 1758 1759 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1760 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1761 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1762 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1763 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1764 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1765 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1766 1767 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1768 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1769 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1770 1771 uint32_t link_speed; 1772 #define LINK_SPEED_AUTO 0 /* Auto selection */ 1773 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1774 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1775 #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1776 #define LINK_SPEED_8G 8 /* 8 Gigabaud */ 1777 #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1778 1779 } INIT_LINK_VAR; 1780 1781 /* Structure for MB Command DOWN_LINK (06) */ 1782 1783 typedef struct { 1784 uint32_t rsvd1; 1785 } DOWN_LINK_VAR; 1786 1787 /* Structure for MB Command CONFIG_LINK (07) */ 1788 1789 typedef struct { 1790 #ifdef __BIG_ENDIAN_BITFIELD 1791 uint32_t cr:1; 1792 uint32_t ci:1; 1793 uint32_t cr_delay:6; 1794 uint32_t cr_count:8; 1795 uint32_t rsvd1:8; 1796 uint32_t MaxBBC:8; 1797 #else /* __LITTLE_ENDIAN_BITFIELD */ 1798 uint32_t MaxBBC:8; 1799 uint32_t rsvd1:8; 1800 uint32_t cr_count:8; 1801 uint32_t cr_delay:6; 1802 uint32_t ci:1; 1803 uint32_t cr:1; 1804 #endif 1805 1806 uint32_t myId; 1807 uint32_t rsvd2; 1808 uint32_t edtov; 1809 uint32_t arbtov; 1810 uint32_t ratov; 1811 uint32_t rttov; 1812 uint32_t altov; 1813 uint32_t crtov; 1814 uint32_t citov; 1815 #ifdef __BIG_ENDIAN_BITFIELD 1816 uint32_t rrq_enable:1; 1817 uint32_t rrq_immed:1; 1818 uint32_t rsvd4:29; 1819 uint32_t ack0_enable:1; 1820 #else /* __LITTLE_ENDIAN_BITFIELD */ 1821 uint32_t ack0_enable:1; 1822 uint32_t rsvd4:29; 1823 uint32_t rrq_immed:1; 1824 uint32_t rrq_enable:1; 1825 #endif 1826 } CONFIG_LINK; 1827 1828 /* Structure for MB Command PART_SLIM (08) 1829 * will be removed since SLI1 is no longer supported! 1830 */ 1831 typedef struct { 1832 #ifdef __BIG_ENDIAN_BITFIELD 1833 uint16_t offCiocb; 1834 uint16_t numCiocb; 1835 uint16_t offRiocb; 1836 uint16_t numRiocb; 1837 #else /* __LITTLE_ENDIAN_BITFIELD */ 1838 uint16_t numCiocb; 1839 uint16_t offCiocb; 1840 uint16_t numRiocb; 1841 uint16_t offRiocb; 1842 #endif 1843 } RING_DEF; 1844 1845 typedef struct { 1846 #ifdef __BIG_ENDIAN_BITFIELD 1847 uint32_t unused1:24; 1848 uint32_t numRing:8; 1849 #else /* __LITTLE_ENDIAN_BITFIELD */ 1850 uint32_t numRing:8; 1851 uint32_t unused1:24; 1852 #endif 1853 1854 RING_DEF ringdef[4]; 1855 uint32_t hbainit; 1856 } PART_SLIM_VAR; 1857 1858 /* Structure for MB Command CONFIG_RING (09) */ 1859 1860 typedef struct { 1861 #ifdef __BIG_ENDIAN_BITFIELD 1862 uint32_t unused2:6; 1863 uint32_t recvSeq:1; 1864 uint32_t recvNotify:1; 1865 uint32_t numMask:8; 1866 uint32_t profile:8; 1867 uint32_t unused1:4; 1868 uint32_t ring:4; 1869 #else /* __LITTLE_ENDIAN_BITFIELD */ 1870 uint32_t ring:4; 1871 uint32_t unused1:4; 1872 uint32_t profile:8; 1873 uint32_t numMask:8; 1874 uint32_t recvNotify:1; 1875 uint32_t recvSeq:1; 1876 uint32_t unused2:6; 1877 #endif 1878 1879 #ifdef __BIG_ENDIAN_BITFIELD 1880 uint16_t maxRespXchg; 1881 uint16_t maxOrigXchg; 1882 #else /* __LITTLE_ENDIAN_BITFIELD */ 1883 uint16_t maxOrigXchg; 1884 uint16_t maxRespXchg; 1885 #endif 1886 1887 RR_REG rrRegs[6]; 1888 } CONFIG_RING_VAR; 1889 1890 /* Structure for MB Command RESET_RING (10) */ 1891 1892 typedef struct { 1893 uint32_t ring_no; 1894 } RESET_RING_VAR; 1895 1896 /* Structure for MB Command READ_CONFIG (11) */ 1897 1898 typedef struct { 1899 #ifdef __BIG_ENDIAN_BITFIELD 1900 uint32_t cr:1; 1901 uint32_t ci:1; 1902 uint32_t cr_delay:6; 1903 uint32_t cr_count:8; 1904 uint32_t InitBBC:8; 1905 uint32_t MaxBBC:8; 1906 #else /* __LITTLE_ENDIAN_BITFIELD */ 1907 uint32_t MaxBBC:8; 1908 uint32_t InitBBC:8; 1909 uint32_t cr_count:8; 1910 uint32_t cr_delay:6; 1911 uint32_t ci:1; 1912 uint32_t cr:1; 1913 #endif 1914 1915 #ifdef __BIG_ENDIAN_BITFIELD 1916 uint32_t topology:8; 1917 uint32_t myDid:24; 1918 #else /* __LITTLE_ENDIAN_BITFIELD */ 1919 uint32_t myDid:24; 1920 uint32_t topology:8; 1921 #endif 1922 1923 /* Defines for topology (defined previously) */ 1924 #ifdef __BIG_ENDIAN_BITFIELD 1925 uint32_t AR:1; 1926 uint32_t IR:1; 1927 uint32_t rsvd1:29; 1928 uint32_t ack0:1; 1929 #else /* __LITTLE_ENDIAN_BITFIELD */ 1930 uint32_t ack0:1; 1931 uint32_t rsvd1:29; 1932 uint32_t IR:1; 1933 uint32_t AR:1; 1934 #endif 1935 1936 uint32_t edtov; 1937 uint32_t arbtov; 1938 uint32_t ratov; 1939 uint32_t rttov; 1940 uint32_t altov; 1941 uint32_t lmt; 1942 #define LMT_RESERVED 0x000 /* Not used */ 1943 #define LMT_1Gb 0x004 1944 #define LMT_2Gb 0x008 1945 #define LMT_4Gb 0x040 1946 #define LMT_8Gb 0x080 1947 #define LMT_10Gb 0x100 1948 uint32_t rsvd2; 1949 uint32_t rsvd3; 1950 uint32_t max_xri; 1951 uint32_t max_iocb; 1952 uint32_t max_rpi; 1953 uint32_t avail_xri; 1954 uint32_t avail_iocb; 1955 uint32_t avail_rpi; 1956 uint32_t max_vpi; 1957 uint32_t rsvd4; 1958 uint32_t rsvd5; 1959 uint32_t avail_vpi; 1960 } READ_CONFIG_VAR; 1961 1962 /* Structure for MB Command READ_RCONFIG (12) */ 1963 1964 typedef struct { 1965 #ifdef __BIG_ENDIAN_BITFIELD 1966 uint32_t rsvd2:7; 1967 uint32_t recvNotify:1; 1968 uint32_t numMask:8; 1969 uint32_t profile:8; 1970 uint32_t rsvd1:4; 1971 uint32_t ring:4; 1972 #else /* __LITTLE_ENDIAN_BITFIELD */ 1973 uint32_t ring:4; 1974 uint32_t rsvd1:4; 1975 uint32_t profile:8; 1976 uint32_t numMask:8; 1977 uint32_t recvNotify:1; 1978 uint32_t rsvd2:7; 1979 #endif 1980 1981 #ifdef __BIG_ENDIAN_BITFIELD 1982 uint16_t maxResp; 1983 uint16_t maxOrig; 1984 #else /* __LITTLE_ENDIAN_BITFIELD */ 1985 uint16_t maxOrig; 1986 uint16_t maxResp; 1987 #endif 1988 1989 RR_REG rrRegs[6]; 1990 1991 #ifdef __BIG_ENDIAN_BITFIELD 1992 uint16_t cmdRingOffset; 1993 uint16_t cmdEntryCnt; 1994 uint16_t rspRingOffset; 1995 uint16_t rspEntryCnt; 1996 uint16_t nextCmdOffset; 1997 uint16_t rsvd3; 1998 uint16_t nextRspOffset; 1999 uint16_t rsvd4; 2000 #else /* __LITTLE_ENDIAN_BITFIELD */ 2001 uint16_t cmdEntryCnt; 2002 uint16_t cmdRingOffset; 2003 uint16_t rspEntryCnt; 2004 uint16_t rspRingOffset; 2005 uint16_t rsvd3; 2006 uint16_t nextCmdOffset; 2007 uint16_t rsvd4; 2008 uint16_t nextRspOffset; 2009 #endif 2010 } READ_RCONF_VAR; 2011 2012 /* Structure for MB Command READ_SPARM (13) */ 2013 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2014 2015 typedef struct { 2016 uint32_t rsvd1; 2017 uint32_t rsvd2; 2018 union { 2019 struct ulp_bde sp; /* This BDE points to struct serv_parm 2020 structure */ 2021 struct ulp_bde64 sp64; 2022 } un; 2023 #ifdef __BIG_ENDIAN_BITFIELD 2024 uint16_t rsvd3; 2025 uint16_t vpi; 2026 #else /* __LITTLE_ENDIAN_BITFIELD */ 2027 uint16_t vpi; 2028 uint16_t rsvd3; 2029 #endif 2030 } READ_SPARM_VAR; 2031 2032 /* Structure for MB Command READ_STATUS (14) */ 2033 2034 typedef struct { 2035 #ifdef __BIG_ENDIAN_BITFIELD 2036 uint32_t rsvd1:31; 2037 uint32_t clrCounters:1; 2038 uint16_t activeXriCnt; 2039 uint16_t activeRpiCnt; 2040 #else /* __LITTLE_ENDIAN_BITFIELD */ 2041 uint32_t clrCounters:1; 2042 uint32_t rsvd1:31; 2043 uint16_t activeRpiCnt; 2044 uint16_t activeXriCnt; 2045 #endif 2046 2047 uint32_t xmitByteCnt; 2048 uint32_t rcvByteCnt; 2049 uint32_t xmitFrameCnt; 2050 uint32_t rcvFrameCnt; 2051 uint32_t xmitSeqCnt; 2052 uint32_t rcvSeqCnt; 2053 uint32_t totalOrigExchanges; 2054 uint32_t totalRespExchanges; 2055 uint32_t rcvPbsyCnt; 2056 uint32_t rcvFbsyCnt; 2057 } READ_STATUS_VAR; 2058 2059 /* Structure for MB Command READ_RPI (15) */ 2060 /* Structure for MB Command READ_RPI64 (0x8F) */ 2061 2062 typedef struct { 2063 #ifdef __BIG_ENDIAN_BITFIELD 2064 uint16_t nextRpi; 2065 uint16_t reqRpi; 2066 uint32_t rsvd2:8; 2067 uint32_t DID:24; 2068 #else /* __LITTLE_ENDIAN_BITFIELD */ 2069 uint16_t reqRpi; 2070 uint16_t nextRpi; 2071 uint32_t DID:24; 2072 uint32_t rsvd2:8; 2073 #endif 2074 2075 union { 2076 struct ulp_bde sp; 2077 struct ulp_bde64 sp64; 2078 } un; 2079 2080 } READ_RPI_VAR; 2081 2082 /* Structure for MB Command READ_XRI (16) */ 2083 2084 typedef struct { 2085 #ifdef __BIG_ENDIAN_BITFIELD 2086 uint16_t nextXri; 2087 uint16_t reqXri; 2088 uint16_t rsvd1; 2089 uint16_t rpi; 2090 uint32_t rsvd2:8; 2091 uint32_t DID:24; 2092 uint32_t rsvd3:8; 2093 uint32_t SID:24; 2094 uint32_t rsvd4; 2095 uint8_t seqId; 2096 uint8_t rsvd5; 2097 uint16_t seqCount; 2098 uint16_t oxId; 2099 uint16_t rxId; 2100 uint32_t rsvd6:30; 2101 uint32_t si:1; 2102 uint32_t exchOrig:1; 2103 #else /* __LITTLE_ENDIAN_BITFIELD */ 2104 uint16_t reqXri; 2105 uint16_t nextXri; 2106 uint16_t rpi; 2107 uint16_t rsvd1; 2108 uint32_t DID:24; 2109 uint32_t rsvd2:8; 2110 uint32_t SID:24; 2111 uint32_t rsvd3:8; 2112 uint32_t rsvd4; 2113 uint16_t seqCount; 2114 uint8_t rsvd5; 2115 uint8_t seqId; 2116 uint16_t rxId; 2117 uint16_t oxId; 2118 uint32_t exchOrig:1; 2119 uint32_t si:1; 2120 uint32_t rsvd6:30; 2121 #endif 2122 } READ_XRI_VAR; 2123 2124 /* Structure for MB Command READ_REV (17) */ 2125 2126 typedef struct { 2127 #ifdef __BIG_ENDIAN_BITFIELD 2128 uint32_t cv:1; 2129 uint32_t rr:1; 2130 uint32_t rsvd2:2; 2131 uint32_t v3req:1; 2132 uint32_t v3rsp:1; 2133 uint32_t rsvd1:25; 2134 uint32_t rv:1; 2135 #else /* __LITTLE_ENDIAN_BITFIELD */ 2136 uint32_t rv:1; 2137 uint32_t rsvd1:25; 2138 uint32_t v3rsp:1; 2139 uint32_t v3req:1; 2140 uint32_t rsvd2:2; 2141 uint32_t rr:1; 2142 uint32_t cv:1; 2143 #endif 2144 2145 uint32_t biuRev; 2146 uint32_t smRev; 2147 union { 2148 uint32_t smFwRev; 2149 struct { 2150 #ifdef __BIG_ENDIAN_BITFIELD 2151 uint8_t ProgType; 2152 uint8_t ProgId; 2153 uint16_t ProgVer:4; 2154 uint16_t ProgRev:4; 2155 uint16_t ProgFixLvl:2; 2156 uint16_t ProgDistType:2; 2157 uint16_t DistCnt:4; 2158 #else /* __LITTLE_ENDIAN_BITFIELD */ 2159 uint16_t DistCnt:4; 2160 uint16_t ProgDistType:2; 2161 uint16_t ProgFixLvl:2; 2162 uint16_t ProgRev:4; 2163 uint16_t ProgVer:4; 2164 uint8_t ProgId; 2165 uint8_t ProgType; 2166 #endif 2167 2168 } b; 2169 } un; 2170 uint32_t endecRev; 2171 #ifdef __BIG_ENDIAN_BITFIELD 2172 uint8_t feaLevelHigh; 2173 uint8_t feaLevelLow; 2174 uint8_t fcphHigh; 2175 uint8_t fcphLow; 2176 #else /* __LITTLE_ENDIAN_BITFIELD */ 2177 uint8_t fcphLow; 2178 uint8_t fcphHigh; 2179 uint8_t feaLevelLow; 2180 uint8_t feaLevelHigh; 2181 #endif 2182 2183 uint32_t postKernRev; 2184 uint32_t opFwRev; 2185 uint8_t opFwName[16]; 2186 uint32_t sli1FwRev; 2187 uint8_t sli1FwName[16]; 2188 uint32_t sli2FwRev; 2189 uint8_t sli2FwName[16]; 2190 uint32_t sli3Feat; 2191 uint32_t RandomData[6]; 2192 } READ_REV_VAR; 2193 2194 /* Structure for MB Command READ_LINK_STAT (18) */ 2195 2196 typedef struct { 2197 uint32_t rsvd1; 2198 uint32_t linkFailureCnt; 2199 uint32_t lossSyncCnt; 2200 2201 uint32_t lossSignalCnt; 2202 uint32_t primSeqErrCnt; 2203 uint32_t invalidXmitWord; 2204 uint32_t crcCnt; 2205 uint32_t primSeqTimeout; 2206 uint32_t elasticOverrun; 2207 uint32_t arbTimeout; 2208 } READ_LNK_VAR; 2209 2210 /* Structure for MB Command REG_LOGIN (19) */ 2211 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2212 2213 typedef struct { 2214 #ifdef __BIG_ENDIAN_BITFIELD 2215 uint16_t rsvd1; 2216 uint16_t rpi; 2217 uint32_t rsvd2:8; 2218 uint32_t did:24; 2219 #else /* __LITTLE_ENDIAN_BITFIELD */ 2220 uint16_t rpi; 2221 uint16_t rsvd1; 2222 uint32_t did:24; 2223 uint32_t rsvd2:8; 2224 #endif 2225 2226 union { 2227 struct ulp_bde sp; 2228 struct ulp_bde64 sp64; 2229 } un; 2230 2231 #ifdef __BIG_ENDIAN_BITFIELD 2232 uint16_t rsvd6; 2233 uint16_t vpi; 2234 #else /* __LITTLE_ENDIAN_BITFIELD */ 2235 uint16_t vpi; 2236 uint16_t rsvd6; 2237 #endif 2238 2239 } REG_LOGIN_VAR; 2240 2241 /* Word 30 contents for REG_LOGIN */ 2242 typedef union { 2243 struct { 2244 #ifdef __BIG_ENDIAN_BITFIELD 2245 uint16_t rsvd1:12; 2246 uint16_t wd30_class:4; 2247 uint16_t xri; 2248 #else /* __LITTLE_ENDIAN_BITFIELD */ 2249 uint16_t xri; 2250 uint16_t wd30_class:4; 2251 uint16_t rsvd1:12; 2252 #endif 2253 } f; 2254 uint32_t word; 2255 } REG_WD30; 2256 2257 /* Structure for MB Command UNREG_LOGIN (20) */ 2258 2259 typedef struct { 2260 #ifdef __BIG_ENDIAN_BITFIELD 2261 uint16_t rsvd1; 2262 uint16_t rpi; 2263 uint32_t rsvd2; 2264 uint32_t rsvd3; 2265 uint32_t rsvd4; 2266 uint32_t rsvd5; 2267 uint16_t rsvd6; 2268 uint16_t vpi; 2269 #else /* __LITTLE_ENDIAN_BITFIELD */ 2270 uint16_t rpi; 2271 uint16_t rsvd1; 2272 uint32_t rsvd2; 2273 uint32_t rsvd3; 2274 uint32_t rsvd4; 2275 uint32_t rsvd5; 2276 uint16_t vpi; 2277 uint16_t rsvd6; 2278 #endif 2279 } UNREG_LOGIN_VAR; 2280 2281 /* Structure for MB Command REG_VPI (0x96) */ 2282 typedef struct { 2283 #ifdef __BIG_ENDIAN_BITFIELD 2284 uint32_t rsvd1; 2285 uint32_t rsvd2:8; 2286 uint32_t sid:24; 2287 uint32_t rsvd3; 2288 uint32_t rsvd4; 2289 uint32_t rsvd5; 2290 uint16_t rsvd6; 2291 uint16_t vpi; 2292 #else /* __LITTLE_ENDIAN */ 2293 uint32_t rsvd1; 2294 uint32_t sid:24; 2295 uint32_t rsvd2:8; 2296 uint32_t rsvd3; 2297 uint32_t rsvd4; 2298 uint32_t rsvd5; 2299 uint16_t vpi; 2300 uint16_t rsvd6; 2301 #endif 2302 } REG_VPI_VAR; 2303 2304 /* Structure for MB Command UNREG_VPI (0x97) */ 2305 typedef struct { 2306 uint32_t rsvd1; 2307 uint32_t rsvd2; 2308 uint32_t rsvd3; 2309 uint32_t rsvd4; 2310 uint32_t rsvd5; 2311 #ifdef __BIG_ENDIAN_BITFIELD 2312 uint16_t rsvd6; 2313 uint16_t vpi; 2314 #else /* __LITTLE_ENDIAN */ 2315 uint16_t vpi; 2316 uint16_t rsvd6; 2317 #endif 2318 } UNREG_VPI_VAR; 2319 2320 /* Structure for MB Command UNREG_D_ID (0x23) */ 2321 2322 typedef struct { 2323 uint32_t did; 2324 uint32_t rsvd2; 2325 uint32_t rsvd3; 2326 uint32_t rsvd4; 2327 uint32_t rsvd5; 2328 #ifdef __BIG_ENDIAN_BITFIELD 2329 uint16_t rsvd6; 2330 uint16_t vpi; 2331 #else 2332 uint16_t vpi; 2333 uint16_t rsvd6; 2334 #endif 2335 } UNREG_D_ID_VAR; 2336 2337 /* Structure for MB Command READ_LA (21) */ 2338 /* Structure for MB Command READ_LA64 (0x95) */ 2339 2340 typedef struct { 2341 uint32_t eventTag; /* Event tag */ 2342 #ifdef __BIG_ENDIAN_BITFIELD 2343 uint32_t rsvd1:19; 2344 uint32_t fa:1; 2345 uint32_t mm:1; /* Menlo Maintenance mode enabled */ 2346 uint32_t rx:1; 2347 uint32_t pb:1; 2348 uint32_t il:1; 2349 uint32_t attType:8; 2350 #else /* __LITTLE_ENDIAN_BITFIELD */ 2351 uint32_t attType:8; 2352 uint32_t il:1; 2353 uint32_t pb:1; 2354 uint32_t rx:1; 2355 uint32_t mm:1; 2356 uint32_t fa:1; 2357 uint32_t rsvd1:19; 2358 #endif 2359 2360 #define AT_RESERVED 0x00 /* Reserved - attType */ 2361 #define AT_LINK_UP 0x01 /* Link is up */ 2362 #define AT_LINK_DOWN 0x02 /* Link is down */ 2363 2364 #ifdef __BIG_ENDIAN_BITFIELD 2365 uint8_t granted_AL_PA; 2366 uint8_t lipAlPs; 2367 uint8_t lipType; 2368 uint8_t topology; 2369 #else /* __LITTLE_ENDIAN_BITFIELD */ 2370 uint8_t topology; 2371 uint8_t lipType; 2372 uint8_t lipAlPs; 2373 uint8_t granted_AL_PA; 2374 #endif 2375 2376 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2377 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2378 #define TOPOLOGY_LNK_MENLO_MAINTENANCE 0x05 /* maint mode zephtr to menlo */ 2379 2380 union { 2381 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2382 to */ 2383 /* store the LILP AL_PA position map into */ 2384 struct ulp_bde64 lilpBde64; 2385 } un; 2386 2387 #ifdef __BIG_ENDIAN_BITFIELD 2388 uint32_t Dlu:1; 2389 uint32_t Dtf:1; 2390 uint32_t Drsvd2:14; 2391 uint32_t DlnkSpeed:8; 2392 uint32_t DnlPort:4; 2393 uint32_t Dtx:2; 2394 uint32_t Drx:2; 2395 #else /* __LITTLE_ENDIAN_BITFIELD */ 2396 uint32_t Drx:2; 2397 uint32_t Dtx:2; 2398 uint32_t DnlPort:4; 2399 uint32_t DlnkSpeed:8; 2400 uint32_t Drsvd2:14; 2401 uint32_t Dtf:1; 2402 uint32_t Dlu:1; 2403 #endif 2404 2405 #ifdef __BIG_ENDIAN_BITFIELD 2406 uint32_t Ulu:1; 2407 uint32_t Utf:1; 2408 uint32_t Ursvd2:14; 2409 uint32_t UlnkSpeed:8; 2410 uint32_t UnlPort:4; 2411 uint32_t Utx:2; 2412 uint32_t Urx:2; 2413 #else /* __LITTLE_ENDIAN_BITFIELD */ 2414 uint32_t Urx:2; 2415 uint32_t Utx:2; 2416 uint32_t UnlPort:4; 2417 uint32_t UlnkSpeed:8; 2418 uint32_t Ursvd2:14; 2419 uint32_t Utf:1; 2420 uint32_t Ulu:1; 2421 #endif 2422 2423 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2424 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2425 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2426 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2427 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2428 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2429 2430 } READ_LA_VAR; 2431 2432 /* Structure for MB Command CLEAR_LA (22) */ 2433 2434 typedef struct { 2435 uint32_t eventTag; /* Event tag */ 2436 uint32_t rsvd1; 2437 } CLEAR_LA_VAR; 2438 2439 /* Structure for MB Command DUMP */ 2440 2441 typedef struct { 2442 #ifdef __BIG_ENDIAN_BITFIELD 2443 uint32_t rsvd:25; 2444 uint32_t ra:1; 2445 uint32_t co:1; 2446 uint32_t cv:1; 2447 uint32_t type:4; 2448 uint32_t entry_index:16; 2449 uint32_t region_id:16; 2450 #else /* __LITTLE_ENDIAN_BITFIELD */ 2451 uint32_t type:4; 2452 uint32_t cv:1; 2453 uint32_t co:1; 2454 uint32_t ra:1; 2455 uint32_t rsvd:25; 2456 uint32_t region_id:16; 2457 uint32_t entry_index:16; 2458 #endif 2459 2460 uint32_t rsvd1; 2461 uint32_t word_cnt; 2462 uint32_t resp_offset; 2463 } DUMP_VAR; 2464 2465 #define DMP_MEM_REG 0x1 2466 #define DMP_NV_PARAMS 0x2 2467 2468 #define DMP_REGION_VPD 0xe 2469 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2470 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2471 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2472 2473 #define WAKE_UP_PARMS_REGION_ID 4 2474 #define WAKE_UP_PARMS_WORD_SIZE 15 2475 2476 /* Option rom version structure */ 2477 struct prog_id { 2478 #ifdef __BIG_ENDIAN_BITFIELD 2479 uint8_t type; 2480 uint8_t id; 2481 uint32_t ver:4; /* Major Version */ 2482 uint32_t rev:4; /* Revision */ 2483 uint32_t lev:2; /* Level */ 2484 uint32_t dist:2; /* Dist Type */ 2485 uint32_t num:4; /* number after dist type */ 2486 #else /* __LITTLE_ENDIAN_BITFIELD */ 2487 uint32_t num:4; /* number after dist type */ 2488 uint32_t dist:2; /* Dist Type */ 2489 uint32_t lev:2; /* Level */ 2490 uint32_t rev:4; /* Revision */ 2491 uint32_t ver:4; /* Major Version */ 2492 uint8_t id; 2493 uint8_t type; 2494 #endif 2495 }; 2496 2497 /* Structure for MB Command UPDATE_CFG (0x1B) */ 2498 2499 struct update_cfg_var { 2500 #ifdef __BIG_ENDIAN_BITFIELD 2501 uint32_t rsvd2:16; 2502 uint32_t type:8; 2503 uint32_t rsvd:1; 2504 uint32_t ra:1; 2505 uint32_t co:1; 2506 uint32_t cv:1; 2507 uint32_t req:4; 2508 uint32_t entry_length:16; 2509 uint32_t region_id:16; 2510 #else /* __LITTLE_ENDIAN_BITFIELD */ 2511 uint32_t req:4; 2512 uint32_t cv:1; 2513 uint32_t co:1; 2514 uint32_t ra:1; 2515 uint32_t rsvd:1; 2516 uint32_t type:8; 2517 uint32_t rsvd2:16; 2518 uint32_t region_id:16; 2519 uint32_t entry_length:16; 2520 #endif 2521 2522 uint32_t resp_info; 2523 uint32_t byte_cnt; 2524 uint32_t data_offset; 2525 }; 2526 2527 struct hbq_mask { 2528 #ifdef __BIG_ENDIAN_BITFIELD 2529 uint8_t tmatch; 2530 uint8_t tmask; 2531 uint8_t rctlmatch; 2532 uint8_t rctlmask; 2533 #else /* __LITTLE_ENDIAN */ 2534 uint8_t rctlmask; 2535 uint8_t rctlmatch; 2536 uint8_t tmask; 2537 uint8_t tmatch; 2538 #endif 2539 }; 2540 2541 2542 /* Structure for MB Command CONFIG_HBQ (7c) */ 2543 2544 struct config_hbq_var { 2545 #ifdef __BIG_ENDIAN_BITFIELD 2546 uint32_t rsvd1 :7; 2547 uint32_t recvNotify :1; /* Receive Notification */ 2548 uint32_t numMask :8; /* # Mask Entries */ 2549 uint32_t profile :8; /* Selection Profile */ 2550 uint32_t rsvd2 :8; 2551 #else /* __LITTLE_ENDIAN */ 2552 uint32_t rsvd2 :8; 2553 uint32_t profile :8; /* Selection Profile */ 2554 uint32_t numMask :8; /* # Mask Entries */ 2555 uint32_t recvNotify :1; /* Receive Notification */ 2556 uint32_t rsvd1 :7; 2557 #endif 2558 2559 #ifdef __BIG_ENDIAN_BITFIELD 2560 uint32_t hbqId :16; 2561 uint32_t rsvd3 :12; 2562 uint32_t ringMask :4; 2563 #else /* __LITTLE_ENDIAN */ 2564 uint32_t ringMask :4; 2565 uint32_t rsvd3 :12; 2566 uint32_t hbqId :16; 2567 #endif 2568 2569 #ifdef __BIG_ENDIAN_BITFIELD 2570 uint32_t entry_count :16; 2571 uint32_t rsvd4 :8; 2572 uint32_t headerLen :8; 2573 #else /* __LITTLE_ENDIAN */ 2574 uint32_t headerLen :8; 2575 uint32_t rsvd4 :8; 2576 uint32_t entry_count :16; 2577 #endif 2578 2579 uint32_t hbqaddrLow; 2580 uint32_t hbqaddrHigh; 2581 2582 #ifdef __BIG_ENDIAN_BITFIELD 2583 uint32_t rsvd5 :31; 2584 uint32_t logEntry :1; 2585 #else /* __LITTLE_ENDIAN */ 2586 uint32_t logEntry :1; 2587 uint32_t rsvd5 :31; 2588 #endif 2589 2590 uint32_t rsvd6; /* w7 */ 2591 uint32_t rsvd7; /* w8 */ 2592 uint32_t rsvd8; /* w9 */ 2593 2594 struct hbq_mask hbqMasks[6]; 2595 2596 2597 union { 2598 uint32_t allprofiles[12]; 2599 2600 struct { 2601 #ifdef __BIG_ENDIAN_BITFIELD 2602 uint32_t seqlenoff :16; 2603 uint32_t maxlen :16; 2604 #else /* __LITTLE_ENDIAN */ 2605 uint32_t maxlen :16; 2606 uint32_t seqlenoff :16; 2607 #endif 2608 #ifdef __BIG_ENDIAN_BITFIELD 2609 uint32_t rsvd1 :28; 2610 uint32_t seqlenbcnt :4; 2611 #else /* __LITTLE_ENDIAN */ 2612 uint32_t seqlenbcnt :4; 2613 uint32_t rsvd1 :28; 2614 #endif 2615 uint32_t rsvd[10]; 2616 } profile2; 2617 2618 struct { 2619 #ifdef __BIG_ENDIAN_BITFIELD 2620 uint32_t seqlenoff :16; 2621 uint32_t maxlen :16; 2622 #else /* __LITTLE_ENDIAN */ 2623 uint32_t maxlen :16; 2624 uint32_t seqlenoff :16; 2625 #endif 2626 #ifdef __BIG_ENDIAN_BITFIELD 2627 uint32_t cmdcodeoff :28; 2628 uint32_t rsvd1 :12; 2629 uint32_t seqlenbcnt :4; 2630 #else /* __LITTLE_ENDIAN */ 2631 uint32_t seqlenbcnt :4; 2632 uint32_t rsvd1 :12; 2633 uint32_t cmdcodeoff :28; 2634 #endif 2635 uint32_t cmdmatch[8]; 2636 2637 uint32_t rsvd[2]; 2638 } profile3; 2639 2640 struct { 2641 #ifdef __BIG_ENDIAN_BITFIELD 2642 uint32_t seqlenoff :16; 2643 uint32_t maxlen :16; 2644 #else /* __LITTLE_ENDIAN */ 2645 uint32_t maxlen :16; 2646 uint32_t seqlenoff :16; 2647 #endif 2648 #ifdef __BIG_ENDIAN_BITFIELD 2649 uint32_t cmdcodeoff :28; 2650 uint32_t rsvd1 :12; 2651 uint32_t seqlenbcnt :4; 2652 #else /* __LITTLE_ENDIAN */ 2653 uint32_t seqlenbcnt :4; 2654 uint32_t rsvd1 :12; 2655 uint32_t cmdcodeoff :28; 2656 #endif 2657 uint32_t cmdmatch[8]; 2658 2659 uint32_t rsvd[2]; 2660 } profile5; 2661 2662 } profiles; 2663 2664 }; 2665 2666 2667 2668 /* Structure for MB Command CONFIG_PORT (0x88) */ 2669 typedef struct { 2670 #ifdef __BIG_ENDIAN_BITFIELD 2671 uint32_t cBE : 1; 2672 uint32_t cET : 1; 2673 uint32_t cHpcb : 1; 2674 uint32_t cMA : 1; 2675 uint32_t sli_mode : 4; 2676 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2677 * config block */ 2678 #else /* __LITTLE_ENDIAN */ 2679 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2680 * config block */ 2681 uint32_t sli_mode : 4; 2682 uint32_t cMA : 1; 2683 uint32_t cHpcb : 1; 2684 uint32_t cET : 1; 2685 uint32_t cBE : 1; 2686 #endif 2687 2688 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2689 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2690 uint32_t hbainit[5]; 2691 #ifdef __BIG_ENDIAN_BITFIELD 2692 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2693 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2694 #else /* __LITTLE_ENDIAN */ 2695 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2696 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2697 #endif 2698 2699 #ifdef __BIG_ENDIAN_BITFIELD 2700 uint32_t rsvd1 : 23; /* Reserved */ 2701 uint32_t cbg : 1; /* Configure BlockGuard */ 2702 uint32_t cmv : 1; /* Configure Max VPIs */ 2703 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2704 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2705 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2706 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2707 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2708 uint32_t cmx : 1; /* Configure Max XRIs */ 2709 uint32_t cmr : 1; /* Configure Max RPIs */ 2710 #else /* __LITTLE_ENDIAN */ 2711 uint32_t cmr : 1; /* Configure Max RPIs */ 2712 uint32_t cmx : 1; /* Configure Max XRIs */ 2713 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2714 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2715 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2716 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2717 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2718 uint32_t cmv : 1; /* Configure Max VPIs */ 2719 uint32_t cbg : 1; /* Configure BlockGuard */ 2720 uint32_t rsvd1 : 23; /* Reserved */ 2721 #endif 2722 #ifdef __BIG_ENDIAN_BITFIELD 2723 uint32_t rsvd2 : 23; /* Reserved */ 2724 uint32_t gbg : 1; /* Grant BlockGuard */ 2725 uint32_t gmv : 1; /* Grant Max VPIs */ 2726 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2727 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2728 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2729 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2730 uint32_t gerbm : 1; /* Grant ERBM Request */ 2731 uint32_t gmx : 1; /* Grant Max XRIs */ 2732 uint32_t gmr : 1; /* Grant Max RPIs */ 2733 #else /* __LITTLE_ENDIAN */ 2734 uint32_t gmr : 1; /* Grant Max RPIs */ 2735 uint32_t gmx : 1; /* Grant Max XRIs */ 2736 uint32_t gerbm : 1; /* Grant ERBM Request */ 2737 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2738 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2739 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2740 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2741 uint32_t gmv : 1; /* Grant Max VPIs */ 2742 uint32_t gbg : 1; /* Grant BlockGuard */ 2743 uint32_t rsvd2 : 23; /* Reserved */ 2744 #endif 2745 2746 #ifdef __BIG_ENDIAN_BITFIELD 2747 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2748 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2749 #else /* __LITTLE_ENDIAN */ 2750 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2751 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2752 #endif 2753 2754 #ifdef __BIG_ENDIAN_BITFIELD 2755 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2756 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */ 2757 #else /* __LITTLE_ENDIAN */ 2758 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */ 2759 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2760 #endif 2761 2762 uint32_t rsvd4; /* Reserved */ 2763 2764 #ifdef __BIG_ENDIAN_BITFIELD 2765 uint32_t rsvd5 : 16; /* Reserved */ 2766 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2767 #else /* __LITTLE_ENDIAN */ 2768 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2769 uint32_t rsvd5 : 16; /* Reserved */ 2770 #endif 2771 2772 } CONFIG_PORT_VAR; 2773 2774 /* Structure for MB Command CONFIG_MSI (0x30) */ 2775 struct config_msi_var { 2776 #ifdef __BIG_ENDIAN_BITFIELD 2777 uint32_t dfltMsgNum:8; /* Default message number */ 2778 uint32_t rsvd1:11; /* Reserved */ 2779 uint32_t NID:5; /* Number of secondary attention IDs */ 2780 uint32_t rsvd2:5; /* Reserved */ 2781 uint32_t dfltPresent:1; /* Default message number present */ 2782 uint32_t addFlag:1; /* Add association flag */ 2783 uint32_t reportFlag:1; /* Report association flag */ 2784 #else /* __LITTLE_ENDIAN_BITFIELD */ 2785 uint32_t reportFlag:1; /* Report association flag */ 2786 uint32_t addFlag:1; /* Add association flag */ 2787 uint32_t dfltPresent:1; /* Default message number present */ 2788 uint32_t rsvd2:5; /* Reserved */ 2789 uint32_t NID:5; /* Number of secondary attention IDs */ 2790 uint32_t rsvd1:11; /* Reserved */ 2791 uint32_t dfltMsgNum:8; /* Default message number */ 2792 #endif 2793 uint32_t attentionConditions[2]; 2794 uint8_t attentionId[16]; 2795 uint8_t messageNumberByHA[64]; 2796 uint8_t messageNumberByID[16]; 2797 uint32_t autoClearHA[2]; 2798 #ifdef __BIG_ENDIAN_BITFIELD 2799 uint32_t rsvd3:16; 2800 uint32_t autoClearID:16; 2801 #else /* __LITTLE_ENDIAN_BITFIELD */ 2802 uint32_t autoClearID:16; 2803 uint32_t rsvd3:16; 2804 #endif 2805 uint32_t rsvd4; 2806 }; 2807 2808 /* SLI-2 Port Control Block */ 2809 2810 /* SLIM POINTER */ 2811 #define SLIMOFF 0x30 /* WORD */ 2812 2813 typedef struct _SLI2_RDSC { 2814 uint32_t cmdEntries; 2815 uint32_t cmdAddrLow; 2816 uint32_t cmdAddrHigh; 2817 2818 uint32_t rspEntries; 2819 uint32_t rspAddrLow; 2820 uint32_t rspAddrHigh; 2821 } SLI2_RDSC; 2822 2823 typedef struct _PCB { 2824 #ifdef __BIG_ENDIAN_BITFIELD 2825 uint32_t type:8; 2826 #define TYPE_NATIVE_SLI2 0x01; 2827 uint32_t feature:8; 2828 #define FEATURE_INITIAL_SLI2 0x01; 2829 uint32_t rsvd:12; 2830 uint32_t maxRing:4; 2831 #else /* __LITTLE_ENDIAN_BITFIELD */ 2832 uint32_t maxRing:4; 2833 uint32_t rsvd:12; 2834 uint32_t feature:8; 2835 #define FEATURE_INITIAL_SLI2 0x01; 2836 uint32_t type:8; 2837 #define TYPE_NATIVE_SLI2 0x01; 2838 #endif 2839 2840 uint32_t mailBoxSize; 2841 uint32_t mbAddrLow; 2842 uint32_t mbAddrHigh; 2843 2844 uint32_t hgpAddrLow; 2845 uint32_t hgpAddrHigh; 2846 2847 uint32_t pgpAddrLow; 2848 uint32_t pgpAddrHigh; 2849 SLI2_RDSC rdsc[MAX_RINGS]; 2850 } PCB_t; 2851 2852 /* NEW_FEATURE */ 2853 typedef struct { 2854 #ifdef __BIG_ENDIAN_BITFIELD 2855 uint32_t rsvd0:27; 2856 uint32_t discardFarp:1; 2857 uint32_t IPEnable:1; 2858 uint32_t nodeName:1; 2859 uint32_t portName:1; 2860 uint32_t filterEnable:1; 2861 #else /* __LITTLE_ENDIAN_BITFIELD */ 2862 uint32_t filterEnable:1; 2863 uint32_t portName:1; 2864 uint32_t nodeName:1; 2865 uint32_t IPEnable:1; 2866 uint32_t discardFarp:1; 2867 uint32_t rsvd:27; 2868 #endif 2869 2870 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2871 uint8_t nodename[8]; 2872 uint32_t rsvd1; 2873 uint32_t rsvd2; 2874 uint32_t rsvd3; 2875 uint32_t IPAddress; 2876 } CONFIG_FARP_VAR; 2877 2878 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 2879 2880 typedef struct { 2881 #ifdef __BIG_ENDIAN_BITFIELD 2882 uint32_t rsvd:30; 2883 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2884 #else /* __LITTLE_ENDIAN */ 2885 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2886 uint32_t rsvd:30; 2887 #endif 2888 } ASYNCEVT_ENABLE_VAR; 2889 2890 /* Union of all Mailbox Command types */ 2891 #define MAILBOX_CMD_WSIZE 32 2892 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2893 2894 typedef union { 2895 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 2896 * feature/max ring number 2897 */ 2898 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2899 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2900 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2901 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2902 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2903 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2904 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2905 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2906 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2907 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2908 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2909 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2910 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2911 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2912 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2913 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2914 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2915 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2916 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2917 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2918 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2919 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2920 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2921 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2922 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 2923 * NEW_FEATURE 2924 */ 2925 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 2926 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 2927 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2928 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 2929 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 2930 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 2931 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 2932 } MAILVARIANTS; 2933 2934 /* 2935 * SLI-2 specific structures 2936 */ 2937 2938 struct lpfc_hgp { 2939 __le32 cmdPutInx; 2940 __le32 rspGetInx; 2941 }; 2942 2943 struct lpfc_pgp { 2944 __le32 cmdGetInx; 2945 __le32 rspPutInx; 2946 }; 2947 2948 struct sli2_desc { 2949 uint32_t unused1[16]; 2950 struct lpfc_hgp host[MAX_RINGS]; 2951 struct lpfc_pgp port[MAX_RINGS]; 2952 }; 2953 2954 struct sli3_desc { 2955 struct lpfc_hgp host[MAX_RINGS]; 2956 uint32_t reserved[8]; 2957 uint32_t hbq_put[16]; 2958 }; 2959 2960 struct sli3_pgp { 2961 struct lpfc_pgp port[MAX_RINGS]; 2962 uint32_t hbq_get[16]; 2963 }; 2964 2965 struct sli3_inb_pgp { 2966 uint32_t ha_copy; 2967 uint32_t counter; 2968 struct lpfc_pgp port[MAX_RINGS]; 2969 uint32_t hbq_get[16]; 2970 }; 2971 2972 union sli_var { 2973 struct sli2_desc s2; 2974 struct sli3_desc s3; 2975 struct sli3_pgp s3_pgp; 2976 struct sli3_inb_pgp s3_inb_pgp; 2977 }; 2978 2979 typedef struct { 2980 #ifdef __BIG_ENDIAN_BITFIELD 2981 uint16_t mbxStatus; 2982 uint8_t mbxCommand; 2983 uint8_t mbxReserved:6; 2984 uint8_t mbxHc:1; 2985 uint8_t mbxOwner:1; /* Low order bit first word */ 2986 #else /* __LITTLE_ENDIAN_BITFIELD */ 2987 uint8_t mbxOwner:1; /* Low order bit first word */ 2988 uint8_t mbxHc:1; 2989 uint8_t mbxReserved:6; 2990 uint8_t mbxCommand; 2991 uint16_t mbxStatus; 2992 #endif 2993 2994 MAILVARIANTS un; 2995 union sli_var us; 2996 } MAILBOX_t; 2997 2998 /* 2999 * Begin Structure Definitions for IOCB Commands 3000 */ 3001 3002 typedef struct { 3003 #ifdef __BIG_ENDIAN_BITFIELD 3004 uint8_t statAction; 3005 uint8_t statRsn; 3006 uint8_t statBaExp; 3007 uint8_t statLocalError; 3008 #else /* __LITTLE_ENDIAN_BITFIELD */ 3009 uint8_t statLocalError; 3010 uint8_t statBaExp; 3011 uint8_t statRsn; 3012 uint8_t statAction; 3013 #endif 3014 /* statRsn P/F_RJT reason codes */ 3015 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3016 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3017 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3018 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3019 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3020 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3021 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3022 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3023 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3024 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3025 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3026 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3027 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3028 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3029 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3030 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3031 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3032 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3033 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3034 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3035 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3036 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3037 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3038 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3039 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3040 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3041 3042 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3043 #define IOERR_MISSING_CONTINUE 0x01 3044 #define IOERR_SEQUENCE_TIMEOUT 0x02 3045 #define IOERR_INTERNAL_ERROR 0x03 3046 #define IOERR_INVALID_RPI 0x04 3047 #define IOERR_NO_XRI 0x05 3048 #define IOERR_ILLEGAL_COMMAND 0x06 3049 #define IOERR_XCHG_DROPPED 0x07 3050 #define IOERR_ILLEGAL_FIELD 0x08 3051 #define IOERR_BAD_CONTINUE 0x09 3052 #define IOERR_TOO_MANY_BUFFERS 0x0A 3053 #define IOERR_RCV_BUFFER_WAITING 0x0B 3054 #define IOERR_NO_CONNECTION 0x0C 3055 #define IOERR_TX_DMA_FAILED 0x0D 3056 #define IOERR_RX_DMA_FAILED 0x0E 3057 #define IOERR_ILLEGAL_FRAME 0x0F 3058 #define IOERR_EXTRA_DATA 0x10 3059 #define IOERR_NO_RESOURCES 0x11 3060 #define IOERR_RESERVED 0x12 3061 #define IOERR_ILLEGAL_LENGTH 0x13 3062 #define IOERR_UNSUPPORTED_FEATURE 0x14 3063 #define IOERR_ABORT_IN_PROGRESS 0x15 3064 #define IOERR_ABORT_REQUESTED 0x16 3065 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3066 #define IOERR_LOOP_OPEN_FAILURE 0x18 3067 #define IOERR_RING_RESET 0x19 3068 #define IOERR_LINK_DOWN 0x1A 3069 #define IOERR_CORRUPTED_DATA 0x1B 3070 #define IOERR_CORRUPTED_RPI 0x1C 3071 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3072 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3073 #define IOERR_DUP_FRAME 0x1F 3074 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3075 #define IOERR_BAD_HOST_ADDRESS 0x21 3076 #define IOERR_RCV_HDRBUF_WAITING 0x22 3077 #define IOERR_MISSING_HDR_BUFFER 0x23 3078 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3079 #define IOERR_ABORTMULT_REQUESTED 0x25 3080 #define IOERR_BUFFER_SHORTAGE 0x28 3081 #define IOERR_DEFAULT 0x29 3082 #define IOERR_CNT 0x2A 3083 3084 #define IOERR_DRVR_MASK 0x100 3085 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3086 #define IOERR_SLI_BRESET 0x102 3087 #define IOERR_SLI_ABORTED 0x103 3088 } PARM_ERR; 3089 3090 typedef union { 3091 struct { 3092 #ifdef __BIG_ENDIAN_BITFIELD 3093 uint8_t Rctl; /* R_CTL field */ 3094 uint8_t Type; /* TYPE field */ 3095 uint8_t Dfctl; /* DF_CTL field */ 3096 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3097 #else /* __LITTLE_ENDIAN_BITFIELD */ 3098 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3099 uint8_t Dfctl; /* DF_CTL field */ 3100 uint8_t Type; /* TYPE field */ 3101 uint8_t Rctl; /* R_CTL field */ 3102 #endif 3103 3104 #define BC 0x02 /* Broadcast Received - Fctl */ 3105 #define SI 0x04 /* Sequence Initiative */ 3106 #define LA 0x08 /* Ignore Link Attention state */ 3107 #define LS 0x80 /* Last Sequence */ 3108 } hcsw; 3109 uint32_t reserved; 3110 } WORD5; 3111 3112 /* IOCB Command template for a generic response */ 3113 typedef struct { 3114 uint32_t reserved[4]; 3115 PARM_ERR perr; 3116 } GENERIC_RSP; 3117 3118 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3119 typedef struct { 3120 struct ulp_bde xrsqbde[2]; 3121 uint32_t xrsqRo; /* Starting Relative Offset */ 3122 WORD5 w5; /* Header control/status word */ 3123 } XR_SEQ_FIELDS; 3124 3125 /* IOCB Command template for ELS_REQUEST */ 3126 typedef struct { 3127 struct ulp_bde elsReq; 3128 struct ulp_bde elsRsp; 3129 3130 #ifdef __BIG_ENDIAN_BITFIELD 3131 uint32_t word4Rsvd:7; 3132 uint32_t fl:1; 3133 uint32_t myID:24; 3134 uint32_t word5Rsvd:8; 3135 uint32_t remoteID:24; 3136 #else /* __LITTLE_ENDIAN_BITFIELD */ 3137 uint32_t myID:24; 3138 uint32_t fl:1; 3139 uint32_t word4Rsvd:7; 3140 uint32_t remoteID:24; 3141 uint32_t word5Rsvd:8; 3142 #endif 3143 } ELS_REQUEST; 3144 3145 /* IOCB Command template for RCV_ELS_REQ */ 3146 typedef struct { 3147 struct ulp_bde elsReq[2]; 3148 uint32_t parmRo; 3149 3150 #ifdef __BIG_ENDIAN_BITFIELD 3151 uint32_t word5Rsvd:8; 3152 uint32_t remoteID:24; 3153 #else /* __LITTLE_ENDIAN_BITFIELD */ 3154 uint32_t remoteID:24; 3155 uint32_t word5Rsvd:8; 3156 #endif 3157 } RCV_ELS_REQ; 3158 3159 /* IOCB Command template for ABORT / CLOSE_XRI */ 3160 typedef struct { 3161 uint32_t rsvd[3]; 3162 uint32_t abortType; 3163 #define ABORT_TYPE_ABTX 0x00000000 3164 #define ABORT_TYPE_ABTS 0x00000001 3165 uint32_t parm; 3166 #ifdef __BIG_ENDIAN_BITFIELD 3167 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3168 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3169 #else /* __LITTLE_ENDIAN_BITFIELD */ 3170 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3171 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3172 #endif 3173 } AC_XRI; 3174 3175 /* IOCB Command template for ABORT_MXRI64 */ 3176 typedef struct { 3177 uint32_t rsvd[3]; 3178 uint32_t abortType; 3179 uint32_t parm; 3180 uint32_t iotag32; 3181 } A_MXRI64; 3182 3183 /* IOCB Command template for GET_RPI */ 3184 typedef struct { 3185 uint32_t rsvd[4]; 3186 uint32_t parmRo; 3187 #ifdef __BIG_ENDIAN_BITFIELD 3188 uint32_t word5Rsvd:8; 3189 uint32_t remoteID:24; 3190 #else /* __LITTLE_ENDIAN_BITFIELD */ 3191 uint32_t remoteID:24; 3192 uint32_t word5Rsvd:8; 3193 #endif 3194 } GET_RPI; 3195 3196 /* IOCB Command template for all FCP Initiator commands */ 3197 typedef struct { 3198 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3199 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3200 uint32_t fcpi_parm; 3201 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3202 } FCPI_FIELDS; 3203 3204 /* IOCB Command template for all FCP Target commands */ 3205 typedef struct { 3206 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3207 uint32_t fcpt_Offset; 3208 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3209 } FCPT_FIELDS; 3210 3211 /* SLI-2 IOCB structure definitions */ 3212 3213 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3214 typedef struct { 3215 ULP_BDL bdl; 3216 uint32_t xrsqRo; /* Starting Relative Offset */ 3217 WORD5 w5; /* Header control/status word */ 3218 } XMT_SEQ_FIELDS64; 3219 3220 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3221 typedef struct { 3222 struct ulp_bde64 rcvBde; 3223 uint32_t rsvd1; 3224 uint32_t xrsqRo; /* Starting Relative Offset */ 3225 WORD5 w5; /* Header control/status word */ 3226 } RCV_SEQ_FIELDS64; 3227 3228 /* IOCB Command template for ELS_REQUEST64 */ 3229 typedef struct { 3230 ULP_BDL bdl; 3231 #ifdef __BIG_ENDIAN_BITFIELD 3232 uint32_t word4Rsvd:7; 3233 uint32_t fl:1; 3234 uint32_t myID:24; 3235 uint32_t word5Rsvd:8; 3236 uint32_t remoteID:24; 3237 #else /* __LITTLE_ENDIAN_BITFIELD */ 3238 uint32_t myID:24; 3239 uint32_t fl:1; 3240 uint32_t word4Rsvd:7; 3241 uint32_t remoteID:24; 3242 uint32_t word5Rsvd:8; 3243 #endif 3244 } ELS_REQUEST64; 3245 3246 /* IOCB Command template for GEN_REQUEST64 */ 3247 typedef struct { 3248 ULP_BDL bdl; 3249 uint32_t xrsqRo; /* Starting Relative Offset */ 3250 WORD5 w5; /* Header control/status word */ 3251 } GEN_REQUEST64; 3252 3253 /* IOCB Command template for RCV_ELS_REQ64 */ 3254 typedef struct { 3255 struct ulp_bde64 elsReq; 3256 uint32_t rcvd1; 3257 uint32_t parmRo; 3258 3259 #ifdef __BIG_ENDIAN_BITFIELD 3260 uint32_t word5Rsvd:8; 3261 uint32_t remoteID:24; 3262 #else /* __LITTLE_ENDIAN_BITFIELD */ 3263 uint32_t remoteID:24; 3264 uint32_t word5Rsvd:8; 3265 #endif 3266 } RCV_ELS_REQ64; 3267 3268 /* IOCB Command template for RCV_SEQ64 */ 3269 struct rcv_seq64 { 3270 struct ulp_bde64 elsReq; 3271 uint32_t hbq_1; 3272 uint32_t parmRo; 3273 #ifdef __BIG_ENDIAN_BITFIELD 3274 uint32_t rctl:8; 3275 uint32_t type:8; 3276 uint32_t dfctl:8; 3277 uint32_t ls:1; 3278 uint32_t fs:1; 3279 uint32_t rsvd2:3; 3280 uint32_t si:1; 3281 uint32_t bc:1; 3282 uint32_t rsvd3:1; 3283 #else /* __LITTLE_ENDIAN_BITFIELD */ 3284 uint32_t rsvd3:1; 3285 uint32_t bc:1; 3286 uint32_t si:1; 3287 uint32_t rsvd2:3; 3288 uint32_t fs:1; 3289 uint32_t ls:1; 3290 uint32_t dfctl:8; 3291 uint32_t type:8; 3292 uint32_t rctl:8; 3293 #endif 3294 }; 3295 3296 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3297 typedef struct { 3298 ULP_BDL bdl; 3299 uint32_t fcpi_parm; 3300 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3301 } FCPI_FIELDS64; 3302 3303 /* IOCB Command template for all 64 bit FCP Target commands */ 3304 typedef struct { 3305 ULP_BDL bdl; 3306 uint32_t fcpt_Offset; 3307 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3308 } FCPT_FIELDS64; 3309 3310 /* IOCB Command template for Async Status iocb commands */ 3311 typedef struct { 3312 uint32_t rsvd[4]; 3313 uint32_t param; 3314 #ifdef __BIG_ENDIAN_BITFIELD 3315 uint16_t evt_code; /* High order bits word 5 */ 3316 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3317 #else /* __LITTLE_ENDIAN_BITFIELD */ 3318 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3319 uint16_t evt_code; /* Low order bits word 5 */ 3320 #endif 3321 } ASYNCSTAT_FIELDS; 3322 #define ASYNC_TEMP_WARN 0x100 3323 #define ASYNC_TEMP_SAFE 0x101 3324 3325 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3326 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3327 3328 struct rcv_sli3 { 3329 uint32_t word8Rsvd; 3330 #ifdef __BIG_ENDIAN_BITFIELD 3331 uint16_t vpi; 3332 uint16_t word9Rsvd; 3333 #else /* __LITTLE_ENDIAN */ 3334 uint16_t word9Rsvd; 3335 uint16_t vpi; 3336 #endif 3337 uint32_t word10Rsvd; 3338 uint32_t acc_len; /* accumulated length */ 3339 struct ulp_bde64 bde2; 3340 }; 3341 3342 /* Structure used for a single HBQ entry */ 3343 struct lpfc_hbq_entry { 3344 struct ulp_bde64 bde; 3345 uint32_t buffer_tag; 3346 }; 3347 3348 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3349 typedef struct { 3350 struct lpfc_hbq_entry buff; 3351 uint32_t rsvd; 3352 uint32_t rsvd1; 3353 } QUE_XRI64_CX_FIELDS; 3354 3355 struct que_xri64cx_ext_fields { 3356 uint32_t iotag64_low; 3357 uint32_t iotag64_high; 3358 uint32_t ebde_count; 3359 uint32_t rsvd; 3360 struct lpfc_hbq_entry buff[5]; 3361 }; 3362 3363 struct sli3_bg_fields { 3364 uint32_t filler[6]; /* word 8-13 in IOCB */ 3365 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3366 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3367 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3368 #define BGS_BIDIR_BG_PROF_SHIFT 24 3369 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3370 #define BGS_BIDIR_ERR_COND_SHIFT 16 3371 #define BGS_BG_PROFILE_MASK 0x0000ff00 3372 #define BGS_BG_PROFILE_SHIFT 8 3373 #define BGS_INVALID_PROF_MASK 0x00000020 3374 #define BGS_INVALID_PROF_SHIFT 5 3375 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3376 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3377 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3378 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3379 #define BGS_REFTAG_ERR_MASK 0x00000004 3380 #define BGS_REFTAG_ERR_SHIFT 2 3381 #define BGS_APPTAG_ERR_MASK 0x00000002 3382 #define BGS_APPTAG_ERR_SHIFT 1 3383 #define BGS_GUARD_ERR_MASK 0x00000001 3384 #define BGS_GUARD_ERR_SHIFT 0 3385 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3386 }; 3387 3388 static inline uint32_t 3389 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3390 { 3391 return (le32_to_cpu(bgstat) & BGS_BIDIR_BG_PROF_MASK) >> 3392 BGS_BIDIR_BG_PROF_SHIFT; 3393 } 3394 3395 static inline uint32_t 3396 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3397 { 3398 return (le32_to_cpu(bgstat) & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3399 BGS_BIDIR_ERR_COND_SHIFT; 3400 } 3401 3402 static inline uint32_t 3403 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3404 { 3405 return (le32_to_cpu(bgstat) & BGS_BG_PROFILE_MASK) >> 3406 BGS_BG_PROFILE_SHIFT; 3407 } 3408 3409 static inline uint32_t 3410 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3411 { 3412 return (le32_to_cpu(bgstat) & BGS_INVALID_PROF_MASK) >> 3413 BGS_INVALID_PROF_SHIFT; 3414 } 3415 3416 static inline uint32_t 3417 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3418 { 3419 return (le32_to_cpu(bgstat) & BGS_UNINIT_DIF_BLOCK_MASK) >> 3420 BGS_UNINIT_DIF_BLOCK_SHIFT; 3421 } 3422 3423 static inline uint32_t 3424 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3425 { 3426 return (le32_to_cpu(bgstat) & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3427 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3428 } 3429 3430 static inline uint32_t 3431 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3432 { 3433 return (le32_to_cpu(bgstat) & BGS_REFTAG_ERR_MASK) >> 3434 BGS_REFTAG_ERR_SHIFT; 3435 } 3436 3437 static inline uint32_t 3438 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3439 { 3440 return (le32_to_cpu(bgstat) & BGS_APPTAG_ERR_MASK) >> 3441 BGS_APPTAG_ERR_SHIFT; 3442 } 3443 3444 static inline uint32_t 3445 lpfc_bgs_get_guard_err(uint32_t bgstat) 3446 { 3447 return (le32_to_cpu(bgstat) & BGS_GUARD_ERR_MASK) >> 3448 BGS_GUARD_ERR_SHIFT; 3449 } 3450 3451 #define LPFC_EXT_DATA_BDE_COUNT 3 3452 struct fcp_irw_ext { 3453 uint32_t io_tag64_low; 3454 uint32_t io_tag64_high; 3455 #ifdef __BIG_ENDIAN_BITFIELD 3456 uint8_t reserved1; 3457 uint8_t reserved2; 3458 uint8_t reserved3; 3459 uint8_t ebde_count; 3460 #else /* __LITTLE_ENDIAN */ 3461 uint8_t ebde_count; 3462 uint8_t reserved3; 3463 uint8_t reserved2; 3464 uint8_t reserved1; 3465 #endif 3466 uint32_t reserved4; 3467 struct ulp_bde64 rbde; /* response bde */ 3468 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 3469 uint8_t icd[32]; /* immediate command data (32 bytes) */ 3470 }; 3471 3472 typedef struct _IOCB { /* IOCB structure */ 3473 union { 3474 GENERIC_RSP grsp; /* Generic response */ 3475 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3476 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3477 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3478 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3479 A_MXRI64 amxri; /* abort multiple xri command overlay */ 3480 GET_RPI getrpi; /* GET_RPI template */ 3481 FCPI_FIELDS fcpi; /* FCP Initiator template */ 3482 FCPT_FIELDS fcpt; /* FCP target template */ 3483 3484 /* SLI-2 structures */ 3485 3486 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3487 * bde_64s */ 3488 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3489 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3490 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3491 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3492 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3493 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 3494 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 3495 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 3496 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3497 3498 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3499 } un; 3500 union { 3501 struct { 3502 #ifdef __BIG_ENDIAN_BITFIELD 3503 uint16_t ulpContext; /* High order bits word 6 */ 3504 uint16_t ulpIoTag; /* Low order bits word 6 */ 3505 #else /* __LITTLE_ENDIAN_BITFIELD */ 3506 uint16_t ulpIoTag; /* Low order bits word 6 */ 3507 uint16_t ulpContext; /* High order bits word 6 */ 3508 #endif 3509 } t1; 3510 struct { 3511 #ifdef __BIG_ENDIAN_BITFIELD 3512 uint16_t ulpContext; /* High order bits word 6 */ 3513 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3514 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3515 #else /* __LITTLE_ENDIAN_BITFIELD */ 3516 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3517 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3518 uint16_t ulpContext; /* High order bits word 6 */ 3519 #endif 3520 } t2; 3521 } un1; 3522 #define ulpContext un1.t1.ulpContext 3523 #define ulpIoTag un1.t1.ulpIoTag 3524 #define ulpIoTag0 un1.t2.ulpIoTag0 3525 3526 #ifdef __BIG_ENDIAN_BITFIELD 3527 uint32_t ulpTimeout:8; 3528 uint32_t ulpXS:1; 3529 uint32_t ulpFCP2Rcvy:1; 3530 uint32_t ulpPU:2; 3531 uint32_t ulpIr:1; 3532 uint32_t ulpClass:3; 3533 uint32_t ulpCommand:8; 3534 uint32_t ulpStatus:4; 3535 uint32_t ulpBdeCount:2; 3536 uint32_t ulpLe:1; 3537 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3538 #else /* __LITTLE_ENDIAN_BITFIELD */ 3539 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3540 uint32_t ulpLe:1; 3541 uint32_t ulpBdeCount:2; 3542 uint32_t ulpStatus:4; 3543 uint32_t ulpCommand:8; 3544 uint32_t ulpClass:3; 3545 uint32_t ulpIr:1; 3546 uint32_t ulpPU:2; 3547 uint32_t ulpFCP2Rcvy:1; 3548 uint32_t ulpXS:1; 3549 uint32_t ulpTimeout:8; 3550 #endif 3551 3552 union { 3553 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 3554 3555 /* words 8-31 used for que_xri_cx iocb */ 3556 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 3557 struct fcp_irw_ext fcp_ext; 3558 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 3559 3560 /* words 8-15 for BlockGuard */ 3561 struct sli3_bg_fields sli3_bg; 3562 } unsli3; 3563 3564 #define ulpCt_h ulpXS 3565 #define ulpCt_l ulpFCP2Rcvy 3566 3567 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3568 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3569 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3570 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3571 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3572 #define PARM_NPIV_DID 3 3573 #define CLASS1 0 /* Class 1 */ 3574 #define CLASS2 1 /* Class 2 */ 3575 #define CLASS3 2 /* Class 3 */ 3576 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3577 3578 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3579 #define IOSTAT_FCP_RSP_ERROR 0x1 3580 #define IOSTAT_REMOTE_STOP 0x2 3581 #define IOSTAT_LOCAL_REJECT 0x3 3582 #define IOSTAT_NPORT_RJT 0x4 3583 #define IOSTAT_FABRIC_RJT 0x5 3584 #define IOSTAT_NPORT_BSY 0x6 3585 #define IOSTAT_FABRIC_BSY 0x7 3586 #define IOSTAT_INTERMED_RSP 0x8 3587 #define IOSTAT_LS_RJT 0x9 3588 #define IOSTAT_BA_RJT 0xA 3589 #define IOSTAT_RSVD1 0xB 3590 #define IOSTAT_RSVD2 0xC 3591 #define IOSTAT_RSVD3 0xD 3592 #define IOSTAT_RSVD4 0xE 3593 #define IOSTAT_NEED_BUFFER 0xF 3594 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3595 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3596 #define IOSTAT_CNT 0x11 3597 3598 } IOCB_t; 3599 3600 3601 #define SLI1_SLIM_SIZE (4 * 1024) 3602 3603 /* Up to 498 IOCBs will fit into 16k 3604 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3605 */ 3606 #define SLI2_SLIM_SIZE (64 * 1024) 3607 3608 /* Maximum IOCBs that will fit in SLI2 slim */ 3609 #define MAX_SLI2_IOCB 498 3610 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3611 (sizeof(MAILBOX_t) + sizeof(PCB_t))) 3612 3613 /* HBQ entries are 4 words each = 4k */ 3614 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3615 lpfc_sli_hbq_count()) 3616 3617 struct lpfc_sli2_slim { 3618 MAILBOX_t mbx; 3619 PCB_t pcb; 3620 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3621 }; 3622 3623 /* 3624 * This function checks PCI device to allow special handling for LC HBAs. 3625 * 3626 * Parameters: 3627 * device : struct pci_dev 's device field 3628 * 3629 * return 1 => TRUE 3630 * 0 => FALSE 3631 */ 3632 static inline int 3633 lpfc_is_LC_HBA(unsigned short device) 3634 { 3635 if ((device == PCI_DEVICE_ID_TFLY) || 3636 (device == PCI_DEVICE_ID_PFLY) || 3637 (device == PCI_DEVICE_ID_LP101) || 3638 (device == PCI_DEVICE_ID_BMID) || 3639 (device == PCI_DEVICE_ID_BSMB) || 3640 (device == PCI_DEVICE_ID_ZMID) || 3641 (device == PCI_DEVICE_ID_ZSMB) || 3642 (device == PCI_DEVICE_ID_SAT_MID) || 3643 (device == PCI_DEVICE_ID_SAT_SMB) || 3644 (device == PCI_DEVICE_ID_RFLY)) 3645 return 1; 3646 else 3647 return 0; 3648 } 3649 3650 /* 3651 * Determine if an IOCB failed because of a link event or firmware reset. 3652 */ 3653 3654 static inline int 3655 lpfc_error_lost_link(IOCB_t *iocbp) 3656 { 3657 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3658 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3659 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3660 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3661 } 3662 3663 #define MENLO_TRANSPORT_TYPE 0xfe 3664 #define MENLO_CONTEXT 0 3665 #define MENLO_PU 3 3666 #define MENLO_TIMEOUT 30 3667 #define SETVAR_MLOMNT 0x103107 3668 #define SETVAR_MLORST 0x103007 3669