1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 #define LPFC_FCP_OAS_RING 3 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 uint32_t CmdRsp:16; 90 uint32_t Size:16; 91 } bits; 92 uint32_t word; 93 }; 94 95 #define FC4_FEATURE_INIT 0x2 96 #define FC4_FEATURE_TARGET 0x1 97 98 struct lpfc_sli_ct_request { 99 /* Structure is in Big Endian format */ 100 union CtRevisionId RevisionId; 101 uint8_t FsType; 102 uint8_t FsSubType; 103 uint8_t Options; 104 uint8_t Rsrvd1; 105 union CtCommandResponse CommandResponse; 106 uint8_t Rsrvd2; 107 uint8_t ReasonCode; 108 uint8_t Explanation; 109 uint8_t VendorUnique; 110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 111 112 union { 113 uint32_t PortID; 114 struct gid { 115 uint8_t PortType; /* for GID_PT requests */ 116 uint8_t DomainScope; 117 uint8_t AreaScope; 118 uint8_t Fc4Type; /* for GID_FT requests */ 119 } gid; 120 struct rft { 121 uint32_t PortId; /* For RFT_ID requests */ 122 123 #ifdef __BIG_ENDIAN_BITFIELD 124 uint32_t rsvd0:16; 125 uint32_t rsvd1:7; 126 uint32_t fcpReg:1; /* Type 8 */ 127 uint32_t rsvd2:2; 128 uint32_t ipReg:1; /* Type 5 */ 129 uint32_t rsvd3:5; 130 #else /* __LITTLE_ENDIAN_BITFIELD */ 131 uint32_t rsvd0:16; 132 uint32_t fcpReg:1; /* Type 8 */ 133 uint32_t rsvd1:7; 134 uint32_t rsvd3:5; 135 uint32_t ipReg:1; /* Type 5 */ 136 uint32_t rsvd2:2; 137 #endif 138 139 uint32_t rsvd[7]; 140 } rft; 141 struct rnn { 142 uint32_t PortId; /* For RNN_ID requests */ 143 uint8_t wwnn[8]; 144 } rnn; 145 struct rsnn { /* For RSNN_ID requests */ 146 uint8_t wwnn[8]; 147 uint8_t len; 148 uint8_t symbname[255]; 149 } rsnn; 150 struct da_id { /* For DA_ID requests */ 151 uint32_t port_id; 152 } da_id; 153 struct rspn { /* For RSPN_ID requests */ 154 uint32_t PortId; 155 uint8_t len; 156 uint8_t symbname[255]; 157 } rspn; 158 struct gff { 159 uint32_t PortId; 160 } gff; 161 struct gff_acc { 162 uint8_t fbits[128]; 163 } gff_acc; 164 #define FCP_TYPE_FEATURE_OFFSET 7 165 struct rff { 166 uint32_t PortId; 167 uint8_t reserved[2]; 168 uint8_t fbits; 169 uint8_t type_code; /* type=8 for FCP */ 170 } rff; 171 } un; 172 }; 173 174 #define LPFC_MAX_CT_SIZE (60 * 4096) 175 176 #define SLI_CT_REVISION 1 177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 178 sizeof(struct gid)) 179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 180 sizeof(struct gff)) 181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 182 sizeof(struct rft)) 183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 184 sizeof(struct rff)) 185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 186 sizeof(struct rnn)) 187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 188 sizeof(struct rsnn)) 189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 190 sizeof(struct da_id)) 191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 192 sizeof(struct rspn)) 193 194 /* 195 * FsType Definitions 196 */ 197 198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 199 #define SLI_CT_TIME_SERVICE 0xFB 200 #define SLI_CT_DIRECTORY_SERVICE 0xFC 201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 202 203 /* 204 * Directory Service Subtypes 205 */ 206 207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 208 209 /* 210 * Response Codes 211 */ 212 213 #define SLI_CT_RESPONSE_FS_RJT 0x8001 214 #define SLI_CT_RESPONSE_FS_ACC 0x8002 215 216 /* 217 * Reason Codes 218 */ 219 220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 221 #define SLI_CT_INVALID_COMMAND 0x01 222 #define SLI_CT_INVALID_VERSION 0x02 223 #define SLI_CT_LOGICAL_ERROR 0x03 224 #define SLI_CT_INVALID_IU_SIZE 0x04 225 #define SLI_CT_LOGICAL_BUSY 0x05 226 #define SLI_CT_PROTOCOL_ERROR 0x07 227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 236 #define SLI_CT_VENDOR_UNIQUE 0xff 237 238 /* 239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 240 */ 241 242 #define SLI_CT_NO_PORT_ID 0x01 243 #define SLI_CT_NO_PORT_NAME 0x02 244 #define SLI_CT_NO_NODE_NAME 0x03 245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 246 #define SLI_CT_NO_IP_ADDRESS 0x05 247 #define SLI_CT_NO_IPA 0x06 248 #define SLI_CT_NO_FC4_TYPES 0x07 249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 251 #define SLI_CT_NO_PORT_TYPE 0x0A 252 #define SLI_CT_ACCESS_DENIED 0x10 253 #define SLI_CT_INVALID_PORT_ID 0x11 254 #define SLI_CT_DATABASE_EMPTY 0x12 255 256 /* 257 * Name Server Command Codes 258 */ 259 260 #define SLI_CTNS_GA_NXT 0x0100 261 #define SLI_CTNS_GPN_ID 0x0112 262 #define SLI_CTNS_GNN_ID 0x0113 263 #define SLI_CTNS_GCS_ID 0x0114 264 #define SLI_CTNS_GFT_ID 0x0117 265 #define SLI_CTNS_GSPN_ID 0x0118 266 #define SLI_CTNS_GPT_ID 0x011A 267 #define SLI_CTNS_GFF_ID 0x011F 268 #define SLI_CTNS_GID_PN 0x0121 269 #define SLI_CTNS_GID_NN 0x0131 270 #define SLI_CTNS_GIP_NN 0x0135 271 #define SLI_CTNS_GIPA_NN 0x0136 272 #define SLI_CTNS_GSNN_NN 0x0139 273 #define SLI_CTNS_GNN_IP 0x0153 274 #define SLI_CTNS_GIPA_IP 0x0156 275 #define SLI_CTNS_GID_FT 0x0171 276 #define SLI_CTNS_GID_PT 0x01A1 277 #define SLI_CTNS_RPN_ID 0x0212 278 #define SLI_CTNS_RNN_ID 0x0213 279 #define SLI_CTNS_RCS_ID 0x0214 280 #define SLI_CTNS_RFT_ID 0x0217 281 #define SLI_CTNS_RSPN_ID 0x0218 282 #define SLI_CTNS_RPT_ID 0x021A 283 #define SLI_CTNS_RFF_ID 0x021F 284 #define SLI_CTNS_RIP_NN 0x0235 285 #define SLI_CTNS_RIPA_NN 0x0236 286 #define SLI_CTNS_RSNN_NN 0x0239 287 #define SLI_CTNS_DA_ID 0x0300 288 289 /* 290 * Port Types 291 */ 292 293 #define SLI_CTPT_N_PORT 0x01 294 #define SLI_CTPT_NL_PORT 0x02 295 #define SLI_CTPT_FNL_PORT 0x03 296 #define SLI_CTPT_IP 0x04 297 #define SLI_CTPT_FCP 0x08 298 #define SLI_CTPT_NX_PORT 0x7F 299 #define SLI_CTPT_F_PORT 0x81 300 #define SLI_CTPT_FL_PORT 0x82 301 #define SLI_CTPT_E_PORT 0x84 302 303 #define SLI_CT_LAST_ENTRY 0x80000000 304 305 /* Fibre Channel Service Parameter definitions */ 306 307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 311 312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 314 #define FC_PH3 0x20 /* FC-PH-3 version */ 315 316 #define FF_FRAME_SIZE 2048 317 318 struct lpfc_name { 319 union { 320 struct { 321 #ifdef __BIG_ENDIAN_BITFIELD 322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 324 8:11 of IEEE ext */ 325 #else /* __LITTLE_ENDIAN_BITFIELD */ 326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 327 8:11 of IEEE ext */ 328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 329 #endif 330 331 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 333 #define NAME_FC_TYPE 0x3 /* FC native name type */ 334 #define NAME_IP_TYPE 0x4 /* IP address */ 335 #define NAME_CCITT_TYPE 0xC 336 #define NAME_CCITT_GR_TYPE 0xE 337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 338 extended Lsb */ 339 uint8_t IEEE[6]; /* FC IEEE address */ 340 } s; 341 uint8_t wwn[8]; 342 } u; 343 }; 344 345 struct csp { 346 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 347 uint8_t fcphLow; 348 uint8_t bbCreditMsb; 349 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 350 351 /* 352 * Word 1 Bit 31 in common service parameter is overloaded. 353 * Word 1 Bit 31 in FLOGI request is multiple NPort request 354 * Word 1 Bit 31 in FLOGI response is clean address bit 355 */ 356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 357 /* 358 * Word 1 Bit 30 in common service parameter is overloaded. 359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 360 * Word 1 Bit 30 in PLOGI request is random offset 361 */ 362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 363 #ifdef __BIG_ENDIAN_BITFIELD 364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 365 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 367 uint16_t fPort:1; /* FC Word 1, bit 28 */ 368 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 370 uint16_t multicast:1; /* FC Word 1, bit 25 */ 371 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 372 373 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 374 uint16_t simplex:1; /* FC Word 1, bit 22 */ 375 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 376 uint16_t dhd:1; /* FC Word 1, bit 18 */ 377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 379 #else /* __LITTLE_ENDIAN_BITFIELD */ 380 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 381 uint16_t multicast:1; /* FC Word 1, bit 25 */ 382 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 383 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 384 uint16_t fPort:1; /* FC Word 1, bit 28 */ 385 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 386 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 387 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 388 389 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 390 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 391 uint16_t dhd:1; /* FC Word 1, bit 18 */ 392 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 393 uint16_t simplex:1; /* FC Word 1, bit 22 */ 394 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 395 #endif 396 397 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 398 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 399 union { 400 struct { 401 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 402 403 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 404 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 405 406 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 407 } nPort; 408 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 409 } w2; 410 411 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 412 }; 413 414 struct class_parms { 415 #ifdef __BIG_ENDIAN_BITFIELD 416 uint8_t classValid:1; /* FC Word 0, bit 31 */ 417 uint8_t intermix:1; /* FC Word 0, bit 30 */ 418 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 419 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 420 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 421 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 422 #else /* __LITTLE_ENDIAN_BITFIELD */ 423 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 424 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 426 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 427 uint8_t intermix:1; /* FC Word 0, bit 30 */ 428 uint8_t classValid:1; /* FC Word 0, bit 31 */ 429 430 #endif 431 432 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 433 434 #ifdef __BIG_ENDIAN_BITFIELD 435 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 436 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 437 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 438 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 439 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 440 #else /* __LITTLE_ENDIAN_BITFIELD */ 441 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 442 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 444 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 445 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 446 #endif 447 448 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 449 450 #ifdef __BIG_ENDIAN_BITFIELD 451 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 452 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 453 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 454 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 455 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 456 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 457 #else /* __LITTLE_ENDIAN_BITFIELD */ 458 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 459 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 461 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 462 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 463 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 464 #endif 465 466 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 467 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 468 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 469 470 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 471 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 472 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 473 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 474 475 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 476 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 477 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 478 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 479 }; 480 481 struct serv_parm { /* Structure is in Big Endian format */ 482 struct csp cmn; 483 struct lpfc_name portName; 484 struct lpfc_name nodeName; 485 struct class_parms cls1; 486 struct class_parms cls2; 487 struct class_parms cls3; 488 struct class_parms cls4; 489 uint8_t vendorVersion[16]; 490 }; 491 492 /* 493 * Virtual Fabric Tagging Header 494 */ 495 struct fc_vft_header { 496 uint32_t word0; 497 #define fc_vft_hdr_r_ctl_SHIFT 24 498 #define fc_vft_hdr_r_ctl_MASK 0xFF 499 #define fc_vft_hdr_r_ctl_WORD word0 500 #define fc_vft_hdr_ver_SHIFT 22 501 #define fc_vft_hdr_ver_MASK 0x3 502 #define fc_vft_hdr_ver_WORD word0 503 #define fc_vft_hdr_type_SHIFT 18 504 #define fc_vft_hdr_type_MASK 0xF 505 #define fc_vft_hdr_type_WORD word0 506 #define fc_vft_hdr_e_SHIFT 16 507 #define fc_vft_hdr_e_MASK 0x1 508 #define fc_vft_hdr_e_WORD word0 509 #define fc_vft_hdr_priority_SHIFT 13 510 #define fc_vft_hdr_priority_MASK 0x7 511 #define fc_vft_hdr_priority_WORD word0 512 #define fc_vft_hdr_vf_id_SHIFT 1 513 #define fc_vft_hdr_vf_id_MASK 0xFFF 514 #define fc_vft_hdr_vf_id_WORD word0 515 uint32_t word1; 516 #define fc_vft_hdr_hopct_SHIFT 24 517 #define fc_vft_hdr_hopct_MASK 0xFF 518 #define fc_vft_hdr_hopct_WORD word1 519 }; 520 521 /* 522 * Extended Link Service LS_COMMAND codes (Payload Word 0) 523 */ 524 #ifdef __BIG_ENDIAN_BITFIELD 525 #define ELS_CMD_MASK 0xffff0000 526 #define ELS_RSP_MASK 0xff000000 527 #define ELS_CMD_LS_RJT 0x01000000 528 #define ELS_CMD_ACC 0x02000000 529 #define ELS_CMD_PLOGI 0x03000000 530 #define ELS_CMD_FLOGI 0x04000000 531 #define ELS_CMD_LOGO 0x05000000 532 #define ELS_CMD_ABTX 0x06000000 533 #define ELS_CMD_RCS 0x07000000 534 #define ELS_CMD_RES 0x08000000 535 #define ELS_CMD_RSS 0x09000000 536 #define ELS_CMD_RSI 0x0A000000 537 #define ELS_CMD_ESTS 0x0B000000 538 #define ELS_CMD_ESTC 0x0C000000 539 #define ELS_CMD_ADVC 0x0D000000 540 #define ELS_CMD_RTV 0x0E000000 541 #define ELS_CMD_RLS 0x0F000000 542 #define ELS_CMD_ECHO 0x10000000 543 #define ELS_CMD_TEST 0x11000000 544 #define ELS_CMD_RRQ 0x12000000 545 #define ELS_CMD_REC 0x13000000 546 #define ELS_CMD_RDP 0x18000000 547 #define ELS_CMD_PRLI 0x20100014 548 #define ELS_CMD_PRLO 0x21100014 549 #define ELS_CMD_PRLO_ACC 0x02100014 550 #define ELS_CMD_PDISC 0x50000000 551 #define ELS_CMD_FDISC 0x51000000 552 #define ELS_CMD_ADISC 0x52000000 553 #define ELS_CMD_FARP 0x54000000 554 #define ELS_CMD_FARPR 0x55000000 555 #define ELS_CMD_RPS 0x56000000 556 #define ELS_CMD_RPL 0x57000000 557 #define ELS_CMD_FAN 0x60000000 558 #define ELS_CMD_RSCN 0x61040000 559 #define ELS_CMD_SCR 0x62000000 560 #define ELS_CMD_RNID 0x78000000 561 #define ELS_CMD_LIRR 0x7A000000 562 #define ELS_CMD_LCB 0x81000000 563 #else /* __LITTLE_ENDIAN_BITFIELD */ 564 #define ELS_CMD_MASK 0xffff 565 #define ELS_RSP_MASK 0xff 566 #define ELS_CMD_LS_RJT 0x01 567 #define ELS_CMD_ACC 0x02 568 #define ELS_CMD_PLOGI 0x03 569 #define ELS_CMD_FLOGI 0x04 570 #define ELS_CMD_LOGO 0x05 571 #define ELS_CMD_ABTX 0x06 572 #define ELS_CMD_RCS 0x07 573 #define ELS_CMD_RES 0x08 574 #define ELS_CMD_RSS 0x09 575 #define ELS_CMD_RSI 0x0A 576 #define ELS_CMD_ESTS 0x0B 577 #define ELS_CMD_ESTC 0x0C 578 #define ELS_CMD_ADVC 0x0D 579 #define ELS_CMD_RTV 0x0E 580 #define ELS_CMD_RLS 0x0F 581 #define ELS_CMD_ECHO 0x10 582 #define ELS_CMD_TEST 0x11 583 #define ELS_CMD_RRQ 0x12 584 #define ELS_CMD_REC 0x13 585 #define ELS_CMD_RDP 0x18 586 #define ELS_CMD_PRLI 0x14001020 587 #define ELS_CMD_PRLO 0x14001021 588 #define ELS_CMD_PRLO_ACC 0x14001002 589 #define ELS_CMD_PDISC 0x50 590 #define ELS_CMD_FDISC 0x51 591 #define ELS_CMD_ADISC 0x52 592 #define ELS_CMD_FARP 0x54 593 #define ELS_CMD_FARPR 0x55 594 #define ELS_CMD_RPS 0x56 595 #define ELS_CMD_RPL 0x57 596 #define ELS_CMD_FAN 0x60 597 #define ELS_CMD_RSCN 0x0461 598 #define ELS_CMD_SCR 0x62 599 #define ELS_CMD_RNID 0x78 600 #define ELS_CMD_LIRR 0x7A 601 #define ELS_CMD_LCB 0x81 602 #endif 603 604 /* 605 * LS_RJT Payload Definition 606 */ 607 608 struct ls_rjt { /* Structure is in Big Endian format */ 609 union { 610 uint32_t lsRjtError; 611 struct { 612 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 613 614 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 615 /* LS_RJT reason codes */ 616 #define LSRJT_INVALID_CMD 0x01 617 #define LSRJT_LOGICAL_ERR 0x03 618 #define LSRJT_LOGICAL_BSY 0x05 619 #define LSRJT_PROTOCOL_ERR 0x07 620 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 621 #define LSRJT_CMD_UNSUPPORTED 0x0B 622 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 623 624 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 625 /* LS_RJT reason explanation */ 626 #define LSEXP_NOTHING_MORE 0x00 627 #define LSEXP_SPARM_OPTIONS 0x01 628 #define LSEXP_SPARM_ICTL 0x03 629 #define LSEXP_SPARM_RCTL 0x05 630 #define LSEXP_SPARM_RCV_SIZE 0x07 631 #define LSEXP_SPARM_CONCUR_SEQ 0x09 632 #define LSEXP_SPARM_CREDIT 0x0B 633 #define LSEXP_INVALID_PNAME 0x0D 634 #define LSEXP_INVALID_NNAME 0x0E 635 #define LSEXP_INVALID_CSP 0x0F 636 #define LSEXP_INVALID_ASSOC_HDR 0x11 637 #define LSEXP_ASSOC_HDR_REQ 0x13 638 #define LSEXP_INVALID_O_SID 0x15 639 #define LSEXP_INVALID_OX_RX 0x17 640 #define LSEXP_CMD_IN_PROGRESS 0x19 641 #define LSEXP_PORT_LOGIN_REQ 0x1E 642 #define LSEXP_INVALID_NPORT_ID 0x1F 643 #define LSEXP_INVALID_SEQ_ID 0x21 644 #define LSEXP_INVALID_XCHG 0x23 645 #define LSEXP_INACTIVE_XCHG 0x25 646 #define LSEXP_RQ_REQUIRED 0x27 647 #define LSEXP_OUT_OF_RESOURCE 0x29 648 #define LSEXP_CANT_GIVE_DATA 0x2A 649 #define LSEXP_REQ_UNSUPPORTED 0x2C 650 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 651 } b; 652 } un; 653 }; 654 655 /* 656 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 657 */ 658 659 typedef struct _LOGO { /* Structure is in Big Endian format */ 660 union { 661 uint32_t nPortId32; /* Access nPortId as a word */ 662 struct { 663 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 664 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 665 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 666 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 667 } b; 668 } un; 669 struct lpfc_name portName; /* N_port name field */ 670 } LOGO; 671 672 /* 673 * FCP Login (PRLI Request / ACC) Payload Definition 674 */ 675 676 #define PRLX_PAGE_LEN 0x10 677 #define TPRLO_PAGE_LEN 0x14 678 679 typedef struct _PRLI { /* Structure is in Big Endian format */ 680 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 681 682 #define PRLI_FCP_TYPE 0x08 683 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 684 685 #ifdef __BIG_ENDIAN_BITFIELD 686 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 687 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 688 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 689 690 /* ACC = imagePairEstablished */ 691 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 692 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 693 #else /* __LITTLE_ENDIAN_BITFIELD */ 694 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 695 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 696 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 697 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 698 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 699 /* ACC = imagePairEstablished */ 700 #endif 701 702 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 703 #define PRLI_NO_RESOURCES 0x2 704 #define PRLI_INIT_INCOMPLETE 0x3 705 #define PRLI_NO_SUCH_PA 0x4 706 #define PRLI_PREDEF_CONFIG 0x5 707 #define PRLI_PARTIAL_SUCCESS 0x6 708 #define PRLI_INVALID_PAGE_CNT 0x7 709 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 710 711 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 712 713 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 714 715 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 716 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 717 718 #ifdef __BIG_ENDIAN_BITFIELD 719 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 720 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 721 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 722 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 723 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 724 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 725 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 726 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 727 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 728 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 729 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 730 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 731 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 732 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 733 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 734 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 735 #else /* __LITTLE_ENDIAN_BITFIELD */ 736 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 737 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 738 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 739 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 740 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 741 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 742 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 743 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 744 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 745 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 746 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 747 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 748 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 749 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 750 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 751 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 752 #endif 753 } PRLI; 754 755 /* 756 * FCP Logout (PRLO Request / ACC) Payload Definition 757 */ 758 759 typedef struct _PRLO { /* Structure is in Big Endian format */ 760 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 761 762 #define PRLO_FCP_TYPE 0x08 763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 764 765 #ifdef __BIG_ENDIAN_BITFIELD 766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 768 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 769 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 770 #else /* __LITTLE_ENDIAN_BITFIELD */ 771 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 772 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 774 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 775 #endif 776 777 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 778 #define PRLO_NO_SUCH_IMAGE 0x4 779 #define PRLO_INVALID_PAGE_CNT 0x7 780 781 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 782 783 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 784 785 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 786 787 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 788 } PRLO; 789 790 typedef struct _ADISC { /* Structure is in Big Endian format */ 791 uint32_t hardAL_PA; 792 struct lpfc_name portName; 793 struct lpfc_name nodeName; 794 uint32_t DID; 795 } ADISC; 796 797 typedef struct _FARP { /* Structure is in Big Endian format */ 798 uint32_t Mflags:8; 799 uint32_t Odid:24; 800 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 801 action */ 802 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 803 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 804 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 805 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 806 supported */ 807 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 808 supported */ 809 uint32_t Rflags:8; 810 uint32_t Rdid:24; 811 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 812 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 813 struct lpfc_name OportName; 814 struct lpfc_name OnodeName; 815 struct lpfc_name RportName; 816 struct lpfc_name RnodeName; 817 uint8_t Oipaddr[16]; 818 uint8_t Ripaddr[16]; 819 } FARP; 820 821 typedef struct _FAN { /* Structure is in Big Endian format */ 822 uint32_t Fdid; 823 struct lpfc_name FportName; 824 struct lpfc_name FnodeName; 825 } FAN; 826 827 typedef struct _SCR { /* Structure is in Big Endian format */ 828 uint8_t resvd1; 829 uint8_t resvd2; 830 uint8_t resvd3; 831 uint8_t Function; 832 #define SCR_FUNC_FABRIC 0x01 833 #define SCR_FUNC_NPORT 0x02 834 #define SCR_FUNC_FULL 0x03 835 #define SCR_CLEAR 0xff 836 } SCR; 837 838 typedef struct _RNID_TOP_DISC { 839 struct lpfc_name portName; 840 uint8_t resvd[8]; 841 uint32_t unitType; 842 #define RNID_HBA 0x7 843 #define RNID_HOST 0xa 844 #define RNID_DRIVER 0xd 845 uint32_t physPort; 846 uint32_t attachedNodes; 847 uint16_t ipVersion; 848 #define RNID_IPV4 0x1 849 #define RNID_IPV6 0x2 850 uint16_t UDPport; 851 uint8_t ipAddr[16]; 852 uint16_t resvd1; 853 uint16_t flags; 854 #define RNID_TD_SUPPORT 0x1 855 #define RNID_LP_VALID 0x2 856 } RNID_TOP_DISC; 857 858 typedef struct _RNID { /* Structure is in Big Endian format */ 859 uint8_t Format; 860 #define RNID_TOPOLOGY_DISC 0xdf 861 uint8_t CommonLen; 862 uint8_t resvd1; 863 uint8_t SpecificLen; 864 struct lpfc_name portName; 865 struct lpfc_name nodeName; 866 union { 867 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 868 } un; 869 } RNID; 870 871 typedef struct _RPS { /* Structure is in Big Endian format */ 872 union { 873 uint32_t portNum; 874 struct lpfc_name portName; 875 } un; 876 } RPS; 877 878 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 879 uint16_t rsvd1; 880 uint16_t portStatus; 881 uint32_t linkFailureCnt; 882 uint32_t lossSyncCnt; 883 uint32_t lossSignalCnt; 884 uint32_t primSeqErrCnt; 885 uint32_t invalidXmitWord; 886 uint32_t crcCnt; 887 } RPS_RSP; 888 889 struct RLS { /* Structure is in Big Endian format */ 890 uint32_t rls; 891 #define rls_rsvd_SHIFT 24 892 #define rls_rsvd_MASK 0x000000ff 893 #define rls_rsvd_WORD rls 894 #define rls_did_SHIFT 0 895 #define rls_did_MASK 0x00ffffff 896 #define rls_did_WORD rls 897 }; 898 899 struct RLS_RSP { /* Structure is in Big Endian format */ 900 uint32_t linkFailureCnt; 901 uint32_t lossSyncCnt; 902 uint32_t lossSignalCnt; 903 uint32_t primSeqErrCnt; 904 uint32_t invalidXmitWord; 905 uint32_t crcCnt; 906 }; 907 908 struct RRQ { /* Structure is in Big Endian format */ 909 uint32_t rrq; 910 #define rrq_rsvd_SHIFT 24 911 #define rrq_rsvd_MASK 0x000000ff 912 #define rrq_rsvd_WORD rrq 913 #define rrq_did_SHIFT 0 914 #define rrq_did_MASK 0x00ffffff 915 #define rrq_did_WORD rrq 916 uint32_t rrq_exchg; 917 #define rrq_oxid_SHIFT 16 918 #define rrq_oxid_MASK 0xffff 919 #define rrq_oxid_WORD rrq_exchg 920 #define rrq_rxid_SHIFT 0 921 #define rrq_rxid_MASK 0xffff 922 #define rrq_rxid_WORD rrq_exchg 923 }; 924 925 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 926 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 927 928 struct RTV_RSP { /* Structure is in Big Endian format */ 929 uint32_t ratov; 930 uint32_t edtov; 931 uint32_t qtov; 932 #define qtov_rsvd0_SHIFT 28 933 #define qtov_rsvd0_MASK 0x0000000f 934 #define qtov_rsvd0_WORD qtov /* reserved */ 935 #define qtov_edtovres_SHIFT 27 936 #define qtov_edtovres_MASK 0x00000001 937 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 938 #define qtov__rsvd1_SHIFT 19 939 #define qtov_rsvd1_MASK 0x0000003f 940 #define qtov_rsvd1_WORD qtov /* reserved */ 941 #define qtov_rttov_SHIFT 18 942 #define qtov_rttov_MASK 0x00000001 943 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 944 #define qtov_rsvd2_SHIFT 0 945 #define qtov_rsvd2_MASK 0x0003ffff 946 #define qtov_rsvd2_WORD qtov /* reserved */ 947 }; 948 949 950 typedef struct _RPL { /* Structure is in Big Endian format */ 951 uint32_t maxsize; 952 uint32_t index; 953 } RPL; 954 955 typedef struct _PORT_NUM_BLK { 956 uint32_t portNum; 957 uint32_t portID; 958 struct lpfc_name portName; 959 } PORT_NUM_BLK; 960 961 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 962 uint32_t listLen; 963 uint32_t index; 964 PORT_NUM_BLK port_num_blk; 965 } RPL_RSP; 966 967 /* This is used for RSCN command */ 968 typedef struct _D_ID { /* Structure is in Big Endian format */ 969 union { 970 uint32_t word; 971 struct { 972 #ifdef __BIG_ENDIAN_BITFIELD 973 uint8_t resv; 974 uint8_t domain; 975 uint8_t area; 976 uint8_t id; 977 #else /* __LITTLE_ENDIAN_BITFIELD */ 978 uint8_t id; 979 uint8_t area; 980 uint8_t domain; 981 uint8_t resv; 982 #endif 983 } b; 984 } un; 985 } D_ID; 986 987 #define RSCN_ADDRESS_FORMAT_PORT 0x0 988 #define RSCN_ADDRESS_FORMAT_AREA 0x1 989 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 990 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 991 #define RSCN_ADDRESS_FORMAT_MASK 0x3 992 993 /* 994 * Structure to define all ELS Payload types 995 */ 996 997 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 998 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 999 uint8_t elsByte1; 1000 uint8_t elsByte2; 1001 uint8_t elsByte3; 1002 union { 1003 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1004 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1005 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1006 PRLI prli; /* Payload for PRLI/ACC */ 1007 PRLO prlo; /* Payload for PRLO/ACC */ 1008 ADISC adisc; /* Payload for ADISC/ACC */ 1009 FARP farp; /* Payload for FARP/ACC */ 1010 FAN fan; /* Payload for FAN */ 1011 SCR scr; /* Payload for SCR/ACC */ 1012 RNID rnid; /* Payload for RNID */ 1013 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1014 } un; 1015 } ELS_PKT; 1016 1017 /* 1018 * Link Cable Beacon (LCB) ELS Frame 1019 */ 1020 1021 struct fc_lcb_request_frame { 1022 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1023 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1024 #define LPFC_LCB_ON 0x1 1025 #define LPFC_LCB_OFF 0x2 1026 uint8_t reserved[3]; 1027 1028 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1029 #define LPFC_LCB_GREEN 0x1 1030 #define LPFC_LCB_AMBER 0x2 1031 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1032 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1033 }; 1034 1035 /* 1036 * Link Cable Beacon (LCB) ELS Response Frame 1037 */ 1038 struct fc_lcb_res_frame { 1039 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1040 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1041 uint8_t reserved[3]; 1042 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1043 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1044 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1045 }; 1046 1047 /* 1048 * Read Diagnostic Parameters (RDP) ELS frame. 1049 */ 1050 #define SFF_PG0_IDENT_SFP 0x3 1051 1052 #define SFP_FLAG_PT_OPTICAL 0x0 1053 #define SFP_FLAG_PT_SWLASER 0x01 1054 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1055 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1056 #define SFP_FLAG_PT_MASK 0x0F 1057 #define SFP_FLAG_PT_SHIFT 0 1058 1059 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1060 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1061 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1062 1063 #define SFP_FLAG_IS_DESC_VALID 0x01 1064 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1065 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1066 1067 #define SFP_FLAG_CT_UNKNOWN 0x0 1068 #define SFP_FLAG_CT_SFP_PLUS 0x01 1069 #define SFP_FLAG_CT_MASK 0x3C 1070 #define SFP_FLAG_CT_SHIFT 6 1071 1072 struct fc_rdp_port_name_info { 1073 uint8_t wwnn[8]; 1074 uint8_t wwpn[8]; 1075 }; 1076 1077 1078 /* 1079 * Link Error Status Block Structure (FC-FS-3) for RDP 1080 * This similar to RPS ELS 1081 */ 1082 struct fc_link_status { 1083 uint32_t link_failure_cnt; 1084 uint32_t loss_of_synch_cnt; 1085 uint32_t loss_of_signal_cnt; 1086 uint32_t primitive_seq_proto_err; 1087 uint32_t invalid_trans_word; 1088 uint32_t invalid_crc_cnt; 1089 1090 }; 1091 1092 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1093 struct fc_rdp_port_name_desc { 1094 uint32_t tag; /* 0001 0003h */ 1095 uint32_t length; /* set to size of payload struct */ 1096 struct fc_rdp_port_name_info port_names; 1097 }; 1098 1099 1100 struct fc_rdp_fec_info { 1101 uint32_t CorrectedBlocks; 1102 uint32_t UncorrectableBlocks; 1103 }; 1104 1105 #define RDP_FEC_DESC_TAG 0x00010005 1106 struct fc_fec_rdp_desc { 1107 uint32_t tag; 1108 uint32_t length; 1109 struct fc_rdp_fec_info info; 1110 }; 1111 1112 struct fc_rdp_link_error_status_payload_info { 1113 struct fc_link_status link_status; /* 24 bytes */ 1114 uint32_t port_type; /* bits 31-30 only */ 1115 }; 1116 1117 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1118 struct fc_rdp_link_error_status_desc { 1119 uint32_t tag; /* 0001 0002h */ 1120 uint32_t length; /* set to size of payload struct */ 1121 struct fc_rdp_link_error_status_payload_info info; 1122 }; 1123 1124 #define VN_PT_PHY_UNKNOWN 0x00 1125 #define VN_PT_PHY_PF_PORT 0x01 1126 #define VN_PT_PHY_ETH_MAC 0x10 1127 #define VN_PT_PHY_SHIFT 30 1128 1129 #define RDP_PS_1GB 0x8000 1130 #define RDP_PS_2GB 0x4000 1131 #define RDP_PS_4GB 0x2000 1132 #define RDP_PS_10GB 0x1000 1133 #define RDP_PS_8GB 0x0800 1134 #define RDP_PS_16GB 0x0400 1135 #define RDP_PS_32GB 0x0200 1136 1137 #define RDP_CAP_USER_CONFIGURED 0x0002 1138 #define RDP_CAP_UNKNOWN 0x0001 1139 #define RDP_PS_UNKNOWN 0x0002 1140 #define RDP_PS_NOT_ESTABLISHED 0x0001 1141 1142 struct fc_rdp_port_speed { 1143 uint16_t capabilities; 1144 uint16_t speed; 1145 }; 1146 1147 struct fc_rdp_port_speed_info { 1148 struct fc_rdp_port_speed port_speed; 1149 }; 1150 1151 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1152 struct fc_rdp_port_speed_desc { 1153 uint32_t tag; /* 00010001h */ 1154 uint32_t length; /* set to size of payload struct */ 1155 struct fc_rdp_port_speed_info info; 1156 }; 1157 1158 #define RDP_NPORT_ID_SIZE 4 1159 #define RDP_N_PORT_DESC_TAG 0x00000003 1160 struct fc_rdp_nport_desc { 1161 uint32_t tag; /* 0000 0003h, big endian */ 1162 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1163 uint32_t nport_id : 12; 1164 uint32_t reserved : 8; 1165 }; 1166 1167 1168 struct fc_rdp_link_service_info { 1169 uint32_t els_req; /* Request payload word 0 value.*/ 1170 }; 1171 1172 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1173 struct fc_rdp_link_service_desc { 1174 uint32_t tag; /* Descriptor tag 1 */ 1175 uint32_t length; /* set to size of payload struct. */ 1176 struct fc_rdp_link_service_info payload; 1177 /* must be ELS req Word 0(0x18) */ 1178 }; 1179 1180 struct fc_rdp_sfp_info { 1181 uint16_t temperature; 1182 uint16_t vcc; 1183 uint16_t tx_bias; 1184 uint16_t tx_power; 1185 uint16_t rx_power; 1186 uint16_t flags; 1187 }; 1188 1189 #define RDP_SFP_DESC_TAG 0x00010000 1190 struct fc_rdp_sfp_desc { 1191 uint32_t tag; 1192 uint32_t length; /* set to size of sfp_info struct */ 1193 struct fc_rdp_sfp_info sfp_info; 1194 }; 1195 1196 /* Buffer Credit Descriptor */ 1197 struct fc_rdp_bbc_info { 1198 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1199 uint32_t attached_port_bbc; 1200 uint32_t rtt; /* Round trip time */ 1201 }; 1202 #define RDP_BBC_DESC_TAG 0x00010006 1203 struct fc_rdp_bbc_desc { 1204 uint32_t tag; 1205 uint32_t length; 1206 struct fc_rdp_bbc_info bbc_info; 1207 }; 1208 1209 #define RDP_OED_TEMPERATURE 0x1 1210 #define RDP_OED_VOLTAGE 0x2 1211 #define RDP_OED_TXBIAS 0x3 1212 #define RDP_OED_TXPOWER 0x4 1213 #define RDP_OED_RXPOWER 0x5 1214 1215 #define RDP_OED_TYPE_SHIFT 28 1216 /* Optical Element Data descriptor */ 1217 struct fc_rdp_oed_info { 1218 uint16_t hi_alarm; 1219 uint16_t lo_alarm; 1220 uint16_t hi_warning; 1221 uint16_t lo_warning; 1222 uint32_t function_flags; 1223 }; 1224 #define RDP_OED_DESC_TAG 0x00010007 1225 struct fc_rdp_oed_sfp_desc { 1226 uint32_t tag; 1227 uint32_t length; 1228 struct fc_rdp_oed_info oed_info; 1229 }; 1230 1231 /* Optical Product Data descriptor */ 1232 struct fc_rdp_opd_sfp_info { 1233 uint8_t vendor_name[16]; 1234 uint8_t model_number[16]; 1235 uint8_t serial_number[16]; 1236 uint8_t reserved[2]; 1237 uint8_t revision[2]; 1238 uint8_t date[8]; 1239 }; 1240 1241 #define RDP_OPD_DESC_TAG 0x00010008 1242 struct fc_rdp_opd_sfp_desc { 1243 uint32_t tag; 1244 uint32_t length; 1245 struct fc_rdp_opd_sfp_info opd_info; 1246 }; 1247 1248 struct fc_rdp_req_frame { 1249 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1250 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1251 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1252 }; 1253 1254 1255 struct fc_rdp_res_frame { 1256 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1257 uint32_t length; /* FC Word 1 */ 1258 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1259 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1260 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */ 1261 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */ 1262 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */ 1263 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */ 1264 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 34-38*/ 1265 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 39-43*/ 1266 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 44-48*/ 1267 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 49-53*/ 1268 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 54-58*/ 1269 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 59-63*/ 1270 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 64-80*/ 1271 struct fc_fec_rdp_desc fec_desc; /* FC word 81-84*/ 1272 }; 1273 1274 1275 #define RDP_DESC_PAYLOAD_SIZE (sizeof(struct fc_rdp_link_service_desc) \ 1276 + sizeof(struct fc_rdp_sfp_desc) \ 1277 + sizeof(struct fc_rdp_port_speed_desc) \ 1278 + sizeof(struct fc_rdp_link_error_status_desc) \ 1279 + (sizeof(struct fc_rdp_port_name_desc) * 2) \ 1280 + sizeof(struct fc_rdp_bbc_desc) \ 1281 + (sizeof(struct fc_rdp_oed_sfp_desc) * 5) \ 1282 + sizeof(struct fc_rdp_opd_sfp_desc)) 1283 1284 1285 /******** FDMI ********/ 1286 1287 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1288 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1289 1290 /* 1291 * Registered Port List Format 1292 */ 1293 struct lpfc_fdmi_reg_port_list { 1294 uint32_t EntryCnt; 1295 uint32_t pe; /* Variable-length array */ 1296 }; 1297 1298 1299 /* Definitions for HBA / Port attribute entries */ 1300 1301 struct lpfc_fdmi_attr_def { /* Defined in TLV format */ 1302 /* Structure is in Big Endian format */ 1303 uint32_t AttrType:16; 1304 uint32_t AttrLen:16; 1305 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */ 1306 }; 1307 1308 1309 /* Attribute Entry */ 1310 struct lpfc_fdmi_attr_entry { 1311 union { 1312 uint32_t AttrInt; 1313 uint8_t AttrTypes[32]; 1314 uint8_t AttrString[256]; 1315 struct lpfc_name AttrWWN; 1316 } un; 1317 }; 1318 1319 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry) 1320 1321 /* 1322 * HBA Attribute Block 1323 */ 1324 struct lpfc_fdmi_attr_block { 1325 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1326 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */ 1327 }; 1328 1329 /* 1330 * Port Entry 1331 */ 1332 struct lpfc_fdmi_port_entry { 1333 struct lpfc_name PortName; 1334 }; 1335 1336 /* 1337 * HBA Identifier 1338 */ 1339 struct lpfc_fdmi_hba_ident { 1340 struct lpfc_name PortName; 1341 }; 1342 1343 /* 1344 * Register HBA(RHBA) 1345 */ 1346 struct lpfc_fdmi_reg_hba { 1347 struct lpfc_fdmi_hba_ident hi; 1348 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */ 1349 /* struct lpfc_fdmi_attr_block ab; */ 1350 }; 1351 1352 /* 1353 * Register HBA Attributes (RHAT) 1354 */ 1355 struct lpfc_fdmi_reg_hbaattr { 1356 struct lpfc_name HBA_PortName; 1357 struct lpfc_fdmi_attr_block ab; 1358 }; 1359 1360 /* 1361 * Register Port Attributes (RPA) 1362 */ 1363 struct lpfc_fdmi_reg_portattr { 1364 struct lpfc_name PortName; 1365 struct lpfc_fdmi_attr_block ab; 1366 }; 1367 1368 /* 1369 * HBA MAnagement Operations Command Codes 1370 */ 1371 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1372 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1373 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1374 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1375 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1376 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1377 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1378 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1379 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1380 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1381 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1382 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1383 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1384 1385 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1386 1387 /* 1388 * HBA Attribute Types 1389 */ 1390 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1391 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1392 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1393 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1394 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1395 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1396 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1397 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1398 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1399 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1400 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1401 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1402 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1403 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1404 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1405 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1406 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1407 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1408 1409 /* Bit mask for all individual HBA attributes */ 1410 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1411 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1412 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1413 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1414 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1415 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1416 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1417 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1418 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1419 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1420 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1421 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1422 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1423 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1424 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1425 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1426 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1427 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1428 1429 /* Bit mask for FDMI-1 defined HBA attributes */ 1430 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1431 1432 /* Bit mask for FDMI-2 defined HBA attributes */ 1433 /* Skip vendor_info and bios_state */ 1434 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1435 1436 /* 1437 * Port Attrubute Types 1438 */ 1439 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1440 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1441 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1442 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1443 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1444 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1445 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1446 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1447 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1448 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1449 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1450 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1451 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1452 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1453 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1454 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1455 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1456 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1457 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1458 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1459 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1460 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1461 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1462 1463 /* Bit mask for all individual PORT attributes */ 1464 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1465 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1466 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1467 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1468 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1469 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1470 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1471 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1472 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1473 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1474 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1475 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1476 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1477 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1478 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1479 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1480 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1481 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1482 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1483 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1484 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1485 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1486 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1487 1488 /* Bit mask for FDMI-1 defined PORT attributes */ 1489 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1490 1491 /* Bit mask for FDMI-2 defined PORT attributes */ 1492 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1493 1494 /* Bit mask for Smart SAN defined PORT attributes */ 1495 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1496 1497 /* Defines for PORT port state attribute */ 1498 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1499 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1500 1501 /* Defines for PORT port type attribute */ 1502 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1503 #define LPFC_FDMI_PORTTYPE_NPORT 1 1504 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1505 1506 /* 1507 * Begin HBA configuration parameters. 1508 * The PCI configuration register BAR assignments are: 1509 * BAR0, offset 0x10 - SLIM base memory address 1510 * BAR1, offset 0x14 - SLIM base memory high address 1511 * BAR2, offset 0x18 - REGISTER base memory address 1512 * BAR3, offset 0x1c - REGISTER base memory high address 1513 * BAR4, offset 0x20 - BIU I/O registers 1514 * BAR5, offset 0x24 - REGISTER base io high address 1515 */ 1516 1517 /* Number of rings currently used and available. */ 1518 #define MAX_SLI3_CONFIGURED_RINGS 3 1519 #define MAX_SLI3_RINGS 4 1520 1521 /* IOCB / Mailbox is owned by FireFly */ 1522 #define OWN_CHIP 1 1523 1524 /* IOCB / Mailbox is owned by Host */ 1525 #define OWN_HOST 0 1526 1527 /* Number of 4-byte words in an IOCB. */ 1528 #define IOCB_WORD_SZ 8 1529 1530 /* network headers for Dfctl field */ 1531 #define FC_NET_HDR 0x20 1532 1533 /* Start FireFly Register definitions */ 1534 #define PCI_VENDOR_ID_EMULEX 0x10df 1535 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1536 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1537 #define PCI_DEVICE_ID_BALIUS 0xe131 1538 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1539 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1540 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1541 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1542 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1543 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1544 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1545 #define PCI_DEVICE_ID_SAT_MID 0xf015 1546 #define PCI_DEVICE_ID_RFLY 0xf095 1547 #define PCI_DEVICE_ID_PFLY 0xf098 1548 #define PCI_DEVICE_ID_LP101 0xf0a1 1549 #define PCI_DEVICE_ID_TFLY 0xf0a5 1550 #define PCI_DEVICE_ID_BSMB 0xf0d1 1551 #define PCI_DEVICE_ID_BMID 0xf0d5 1552 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1553 #define PCI_DEVICE_ID_ZMID 0xf0e5 1554 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1555 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1556 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1557 #define PCI_DEVICE_ID_SAT 0xf100 1558 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1559 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1560 #define PCI_DEVICE_ID_FALCON 0xf180 1561 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1562 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1563 #define PCI_DEVICE_ID_CENTAUR 0xf900 1564 #define PCI_DEVICE_ID_PEGASUS 0xf980 1565 #define PCI_DEVICE_ID_THOR 0xfa00 1566 #define PCI_DEVICE_ID_VIPER 0xfb00 1567 #define PCI_DEVICE_ID_LP10000S 0xfc00 1568 #define PCI_DEVICE_ID_LP11000S 0xfc10 1569 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1570 #define PCI_DEVICE_ID_SAT_S 0xfc40 1571 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1572 #define PCI_DEVICE_ID_HELIOS 0xfd00 1573 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1574 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1575 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1576 #define PCI_DEVICE_ID_HORNET 0xfe05 1577 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1578 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1579 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1580 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1581 #define PCI_DEVICE_ID_TOMCAT 0x0714 1582 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1583 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1584 1585 #define JEDEC_ID_ADDRESS 0x0080001c 1586 #define FIREFLY_JEDEC_ID 0x1ACC 1587 #define SUPERFLY_JEDEC_ID 0x0020 1588 #define DRAGONFLY_JEDEC_ID 0x0021 1589 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1590 #define CENTAUR_2G_JEDEC_ID 0x0026 1591 #define CENTAUR_1G_JEDEC_ID 0x0028 1592 #define PEGASUS_ORION_JEDEC_ID 0x0036 1593 #define PEGASUS_JEDEC_ID 0x0038 1594 #define THOR_JEDEC_ID 0x0012 1595 #define HELIOS_JEDEC_ID 0x0364 1596 #define ZEPHYR_JEDEC_ID 0x0577 1597 #define VIPER_JEDEC_ID 0x4838 1598 #define SATURN_JEDEC_ID 0x1004 1599 #define HORNET_JDEC_ID 0x2057706D 1600 1601 #define JEDEC_ID_MASK 0x0FFFF000 1602 #define JEDEC_ID_SHIFT 12 1603 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1604 1605 typedef struct { /* FireFly BIU registers */ 1606 uint32_t hostAtt; /* See definitions for Host Attention 1607 register */ 1608 uint32_t chipAtt; /* See definitions for Chip Attention 1609 register */ 1610 uint32_t hostStatus; /* See definitions for Host Status register */ 1611 uint32_t hostControl; /* See definitions for Host Control register */ 1612 uint32_t buiConfig; /* See definitions for BIU configuration 1613 register */ 1614 } FF_REGS; 1615 1616 /* IO Register size in bytes */ 1617 #define FF_REG_AREA_SIZE 256 1618 1619 /* Host Attention Register */ 1620 1621 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1622 1623 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1624 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1625 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1626 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1627 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1628 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1629 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1630 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1631 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1632 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1633 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1634 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1635 #define HA_LATT 0x20000000 /* Bit 29 */ 1636 #define HA_MBATT 0x40000000 /* Bit 30 */ 1637 #define HA_ERATT 0x80000000 /* Bit 31 */ 1638 1639 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1640 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1641 #define HA_RXATT 0x00000008 /* Bit 3 */ 1642 #define HA_RXMASK 0x0000000f 1643 1644 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1645 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1646 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1647 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1648 1649 #define HA_R0_POS 3 1650 #define HA_R1_POS 7 1651 #define HA_R2_POS 11 1652 #define HA_R3_POS 15 1653 #define HA_LE_POS 29 1654 #define HA_MB_POS 30 1655 #define HA_ER_POS 31 1656 /* Chip Attention Register */ 1657 1658 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1659 1660 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1661 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1662 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1663 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1664 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1665 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1666 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1667 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1668 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1669 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1670 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1671 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1672 #define CA_MBATT 0x40000000 /* Bit 30 */ 1673 1674 /* Host Status Register */ 1675 1676 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1677 1678 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1679 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1680 #define HS_FFER8 0x01000000 /* Bit 24 */ 1681 #define HS_FFER7 0x02000000 /* Bit 25 */ 1682 #define HS_FFER6 0x04000000 /* Bit 26 */ 1683 #define HS_FFER5 0x08000000 /* Bit 27 */ 1684 #define HS_FFER4 0x10000000 /* Bit 28 */ 1685 #define HS_FFER3 0x20000000 /* Bit 29 */ 1686 #define HS_FFER2 0x40000000 /* Bit 30 */ 1687 #define HS_FFER1 0x80000000 /* Bit 31 */ 1688 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1689 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1690 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1691 /* Host Control Register */ 1692 1693 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1694 1695 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1696 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1697 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1698 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1699 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1700 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1701 #define HC_INITMB 0x04000000 /* Bit 26 */ 1702 #define HC_INITFF 0x08000000 /* Bit 27 */ 1703 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1704 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1705 1706 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1707 #define MSIX_DFLT_ID 0 1708 #define MSIX_RNG0_ID 0 1709 #define MSIX_RNG1_ID 1 1710 #define MSIX_RNG2_ID 2 1711 #define MSIX_RNG3_ID 3 1712 1713 #define MSIX_LINK_ID 4 1714 #define MSIX_MBOX_ID 5 1715 1716 #define MSIX_SPARE0_ID 6 1717 #define MSIX_SPARE1_ID 7 1718 1719 /* Mailbox Commands */ 1720 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1721 #define MBX_LOAD_SM 0x01 1722 #define MBX_READ_NV 0x02 1723 #define MBX_WRITE_NV 0x03 1724 #define MBX_RUN_BIU_DIAG 0x04 1725 #define MBX_INIT_LINK 0x05 1726 #define MBX_DOWN_LINK 0x06 1727 #define MBX_CONFIG_LINK 0x07 1728 #define MBX_CONFIG_RING 0x09 1729 #define MBX_RESET_RING 0x0A 1730 #define MBX_READ_CONFIG 0x0B 1731 #define MBX_READ_RCONFIG 0x0C 1732 #define MBX_READ_SPARM 0x0D 1733 #define MBX_READ_STATUS 0x0E 1734 #define MBX_READ_RPI 0x0F 1735 #define MBX_READ_XRI 0x10 1736 #define MBX_READ_REV 0x11 1737 #define MBX_READ_LNK_STAT 0x12 1738 #define MBX_REG_LOGIN 0x13 1739 #define MBX_UNREG_LOGIN 0x14 1740 #define MBX_CLEAR_LA 0x16 1741 #define MBX_DUMP_MEMORY 0x17 1742 #define MBX_DUMP_CONTEXT 0x18 1743 #define MBX_RUN_DIAGS 0x19 1744 #define MBX_RESTART 0x1A 1745 #define MBX_UPDATE_CFG 0x1B 1746 #define MBX_DOWN_LOAD 0x1C 1747 #define MBX_DEL_LD_ENTRY 0x1D 1748 #define MBX_RUN_PROGRAM 0x1E 1749 #define MBX_SET_MASK 0x20 1750 #define MBX_SET_VARIABLE 0x21 1751 #define MBX_UNREG_D_ID 0x23 1752 #define MBX_KILL_BOARD 0x24 1753 #define MBX_CONFIG_FARP 0x25 1754 #define MBX_BEACON 0x2A 1755 #define MBX_CONFIG_MSI 0x30 1756 #define MBX_HEARTBEAT 0x31 1757 #define MBX_WRITE_VPARMS 0x32 1758 #define MBX_ASYNCEVT_ENABLE 0x33 1759 #define MBX_READ_EVENT_LOG_STATUS 0x37 1760 #define MBX_READ_EVENT_LOG 0x38 1761 #define MBX_WRITE_EVENT_LOG 0x39 1762 1763 #define MBX_PORT_CAPABILITIES 0x3B 1764 #define MBX_PORT_IOV_CONTROL 0x3C 1765 1766 #define MBX_CONFIG_HBQ 0x7C 1767 #define MBX_LOAD_AREA 0x81 1768 #define MBX_RUN_BIU_DIAG64 0x84 1769 #define MBX_CONFIG_PORT 0x88 1770 #define MBX_READ_SPARM64 0x8D 1771 #define MBX_READ_RPI64 0x8F 1772 #define MBX_REG_LOGIN64 0x93 1773 #define MBX_READ_TOPOLOGY 0x95 1774 #define MBX_REG_VPI 0x96 1775 #define MBX_UNREG_VPI 0x97 1776 1777 #define MBX_WRITE_WWN 0x98 1778 #define MBX_SET_DEBUG 0x99 1779 #define MBX_LOAD_EXP_ROM 0x9C 1780 #define MBX_SLI4_CONFIG 0x9B 1781 #define MBX_SLI4_REQ_FTRS 0x9D 1782 #define MBX_MAX_CMDS 0x9E 1783 #define MBX_RESUME_RPI 0x9E 1784 #define MBX_SLI2_CMD_MASK 0x80 1785 #define MBX_REG_VFI 0x9F 1786 #define MBX_REG_FCFI 0xA0 1787 #define MBX_UNREG_VFI 0xA1 1788 #define MBX_UNREG_FCFI 0xA2 1789 #define MBX_INIT_VFI 0xA3 1790 #define MBX_INIT_VPI 0xA4 1791 #define MBX_ACCESS_VDATA 0xA5 1792 1793 #define MBX_AUTH_PORT 0xF8 1794 #define MBX_SECURITY_MGMT 0xF9 1795 1796 /* IOCB Commands */ 1797 1798 #define CMD_RCV_SEQUENCE_CX 0x01 1799 #define CMD_XMIT_SEQUENCE_CR 0x02 1800 #define CMD_XMIT_SEQUENCE_CX 0x03 1801 #define CMD_XMIT_BCAST_CN 0x04 1802 #define CMD_XMIT_BCAST_CX 0x05 1803 #define CMD_QUE_RING_BUF_CN 0x06 1804 #define CMD_QUE_XRI_BUF_CX 0x07 1805 #define CMD_IOCB_CONTINUE_CN 0x08 1806 #define CMD_RET_XRI_BUF_CX 0x09 1807 #define CMD_ELS_REQUEST_CR 0x0A 1808 #define CMD_ELS_REQUEST_CX 0x0B 1809 #define CMD_RCV_ELS_REQ_CX 0x0D 1810 #define CMD_ABORT_XRI_CN 0x0E 1811 #define CMD_ABORT_XRI_CX 0x0F 1812 #define CMD_CLOSE_XRI_CN 0x10 1813 #define CMD_CLOSE_XRI_CX 0x11 1814 #define CMD_CREATE_XRI_CR 0x12 1815 #define CMD_CREATE_XRI_CX 0x13 1816 #define CMD_GET_RPI_CN 0x14 1817 #define CMD_XMIT_ELS_RSP_CX 0x15 1818 #define CMD_GET_RPI_CR 0x16 1819 #define CMD_XRI_ABORTED_CX 0x17 1820 #define CMD_FCP_IWRITE_CR 0x18 1821 #define CMD_FCP_IWRITE_CX 0x19 1822 #define CMD_FCP_IREAD_CR 0x1A 1823 #define CMD_FCP_IREAD_CX 0x1B 1824 #define CMD_FCP_ICMND_CR 0x1C 1825 #define CMD_FCP_ICMND_CX 0x1D 1826 #define CMD_FCP_TSEND_CX 0x1F 1827 #define CMD_FCP_TRECEIVE_CX 0x21 1828 #define CMD_FCP_TRSP_CX 0x23 1829 #define CMD_FCP_AUTO_TRSP_CX 0x29 1830 1831 #define CMD_ADAPTER_MSG 0x20 1832 #define CMD_ADAPTER_DUMP 0x22 1833 1834 /* SLI_2 IOCB Command Set */ 1835 1836 #define CMD_ASYNC_STATUS 0x7C 1837 #define CMD_RCV_SEQUENCE64_CX 0x81 1838 #define CMD_XMIT_SEQUENCE64_CR 0x82 1839 #define CMD_XMIT_SEQUENCE64_CX 0x83 1840 #define CMD_XMIT_BCAST64_CN 0x84 1841 #define CMD_XMIT_BCAST64_CX 0x85 1842 #define CMD_QUE_RING_BUF64_CN 0x86 1843 #define CMD_QUE_XRI_BUF64_CX 0x87 1844 #define CMD_IOCB_CONTINUE64_CN 0x88 1845 #define CMD_RET_XRI_BUF64_CX 0x89 1846 #define CMD_ELS_REQUEST64_CR 0x8A 1847 #define CMD_ELS_REQUEST64_CX 0x8B 1848 #define CMD_ABORT_MXRI64_CN 0x8C 1849 #define CMD_RCV_ELS_REQ64_CX 0x8D 1850 #define CMD_XMIT_ELS_RSP64_CX 0x95 1851 #define CMD_XMIT_BLS_RSP64_CX 0x97 1852 #define CMD_FCP_IWRITE64_CR 0x98 1853 #define CMD_FCP_IWRITE64_CX 0x99 1854 #define CMD_FCP_IREAD64_CR 0x9A 1855 #define CMD_FCP_IREAD64_CX 0x9B 1856 #define CMD_FCP_ICMND64_CR 0x9C 1857 #define CMD_FCP_ICMND64_CX 0x9D 1858 #define CMD_FCP_TSEND64_CX 0x9F 1859 #define CMD_FCP_TRECEIVE64_CX 0xA1 1860 #define CMD_FCP_TRSP64_CX 0xA3 1861 1862 #define CMD_QUE_XRI64_CX 0xB3 1863 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1864 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1865 #define CMD_IOCB_RET_XRI64_CX 0xB9 1866 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1867 1868 #define CMD_GEN_REQUEST64_CR 0xC2 1869 #define CMD_GEN_REQUEST64_CX 0xC3 1870 1871 /* Unhandled SLI-3 Commands */ 1872 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1873 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1874 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1875 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1876 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1877 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1878 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1879 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1880 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1881 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1882 #define CMD_IOCB_LOGENTRY_CN 0x94 1883 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1884 1885 /* Data Security SLI Commands */ 1886 #define DSSCMD_IWRITE64_CR 0xF8 1887 #define DSSCMD_IWRITE64_CX 0xF9 1888 #define DSSCMD_IREAD64_CR 0xFA 1889 #define DSSCMD_IREAD64_CX 0xFB 1890 1891 #define CMD_MAX_IOCB_CMD 0xFB 1892 #define CMD_IOCB_MASK 0xff 1893 1894 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1895 iocb */ 1896 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1897 /* 1898 * Define Status 1899 */ 1900 #define MBX_SUCCESS 0 1901 #define MBXERR_NUM_RINGS 1 1902 #define MBXERR_NUM_IOCBS 2 1903 #define MBXERR_IOCBS_EXCEEDED 3 1904 #define MBXERR_BAD_RING_NUMBER 4 1905 #define MBXERR_MASK_ENTRIES_RANGE 5 1906 #define MBXERR_MASKS_EXCEEDED 6 1907 #define MBXERR_BAD_PROFILE 7 1908 #define MBXERR_BAD_DEF_CLASS 8 1909 #define MBXERR_BAD_MAX_RESPONDER 9 1910 #define MBXERR_BAD_MAX_ORIGINATOR 10 1911 #define MBXERR_RPI_REGISTERED 11 1912 #define MBXERR_RPI_FULL 12 1913 #define MBXERR_NO_RESOURCES 13 1914 #define MBXERR_BAD_RCV_LENGTH 14 1915 #define MBXERR_DMA_ERROR 15 1916 #define MBXERR_ERROR 16 1917 #define MBXERR_LINK_DOWN 0x33 1918 #define MBXERR_SEC_NO_PERMISSION 0xF02 1919 #define MBX_NOT_FINISHED 255 1920 1921 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1922 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1923 1924 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1925 1926 /* 1927 * return code Fail 1928 */ 1929 #define FAILURE 1 1930 1931 /* 1932 * Begin Structure Definitions for Mailbox Commands 1933 */ 1934 1935 typedef struct { 1936 #ifdef __BIG_ENDIAN_BITFIELD 1937 uint8_t tval; 1938 uint8_t tmask; 1939 uint8_t rval; 1940 uint8_t rmask; 1941 #else /* __LITTLE_ENDIAN_BITFIELD */ 1942 uint8_t rmask; 1943 uint8_t rval; 1944 uint8_t tmask; 1945 uint8_t tval; 1946 #endif 1947 } RR_REG; 1948 1949 struct ulp_bde { 1950 uint32_t bdeAddress; 1951 #ifdef __BIG_ENDIAN_BITFIELD 1952 uint32_t bdeReserved:4; 1953 uint32_t bdeAddrHigh:4; 1954 uint32_t bdeSize:24; 1955 #else /* __LITTLE_ENDIAN_BITFIELD */ 1956 uint32_t bdeSize:24; 1957 uint32_t bdeAddrHigh:4; 1958 uint32_t bdeReserved:4; 1959 #endif 1960 }; 1961 1962 typedef struct ULP_BDL { /* SLI-2 */ 1963 #ifdef __BIG_ENDIAN_BITFIELD 1964 uint32_t bdeFlags:8; /* BDL Flags */ 1965 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1966 #else /* __LITTLE_ENDIAN_BITFIELD */ 1967 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1968 uint32_t bdeFlags:8; /* BDL Flags */ 1969 #endif 1970 1971 uint32_t addrLow; /* Address 0:31 */ 1972 uint32_t addrHigh; /* Address 32:63 */ 1973 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1974 } ULP_BDL; 1975 1976 /* 1977 * BlockGuard Definitions 1978 */ 1979 1980 enum lpfc_protgrp_type { 1981 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1982 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1983 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1984 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1985 }; 1986 1987 /* PDE Descriptors */ 1988 #define LPFC_PDE5_DESCRIPTOR 0x85 1989 #define LPFC_PDE6_DESCRIPTOR 0x86 1990 #define LPFC_PDE7_DESCRIPTOR 0x87 1991 1992 /* BlockGuard Opcodes */ 1993 #define BG_OP_IN_NODIF_OUT_CRC 0x0 1994 #define BG_OP_IN_CRC_OUT_NODIF 0x1 1995 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 1996 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 1997 #define BG_OP_IN_CRC_OUT_CRC 0x4 1998 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 1999 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2000 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2001 #define BG_OP_RAW_MODE 0x8 2002 2003 struct lpfc_pde5 { 2004 uint32_t word0; 2005 #define pde5_type_SHIFT 24 2006 #define pde5_type_MASK 0x000000ff 2007 #define pde5_type_WORD word0 2008 #define pde5_rsvd0_SHIFT 0 2009 #define pde5_rsvd0_MASK 0x00ffffff 2010 #define pde5_rsvd0_WORD word0 2011 uint32_t reftag; /* Reference Tag Value */ 2012 uint32_t reftagtr; /* Reference Tag Translation Value */ 2013 }; 2014 2015 struct lpfc_pde6 { 2016 uint32_t word0; 2017 #define pde6_type_SHIFT 24 2018 #define pde6_type_MASK 0x000000ff 2019 #define pde6_type_WORD word0 2020 #define pde6_rsvd0_SHIFT 0 2021 #define pde6_rsvd0_MASK 0x00ffffff 2022 #define pde6_rsvd0_WORD word0 2023 uint32_t word1; 2024 #define pde6_rsvd1_SHIFT 26 2025 #define pde6_rsvd1_MASK 0x0000003f 2026 #define pde6_rsvd1_WORD word1 2027 #define pde6_na_SHIFT 25 2028 #define pde6_na_MASK 0x00000001 2029 #define pde6_na_WORD word1 2030 #define pde6_rsvd2_SHIFT 16 2031 #define pde6_rsvd2_MASK 0x000001FF 2032 #define pde6_rsvd2_WORD word1 2033 #define pde6_apptagtr_SHIFT 0 2034 #define pde6_apptagtr_MASK 0x0000ffff 2035 #define pde6_apptagtr_WORD word1 2036 uint32_t word2; 2037 #define pde6_optx_SHIFT 28 2038 #define pde6_optx_MASK 0x0000000f 2039 #define pde6_optx_WORD word2 2040 #define pde6_oprx_SHIFT 24 2041 #define pde6_oprx_MASK 0x0000000f 2042 #define pde6_oprx_WORD word2 2043 #define pde6_nr_SHIFT 23 2044 #define pde6_nr_MASK 0x00000001 2045 #define pde6_nr_WORD word2 2046 #define pde6_ce_SHIFT 22 2047 #define pde6_ce_MASK 0x00000001 2048 #define pde6_ce_WORD word2 2049 #define pde6_re_SHIFT 21 2050 #define pde6_re_MASK 0x00000001 2051 #define pde6_re_WORD word2 2052 #define pde6_ae_SHIFT 20 2053 #define pde6_ae_MASK 0x00000001 2054 #define pde6_ae_WORD word2 2055 #define pde6_ai_SHIFT 19 2056 #define pde6_ai_MASK 0x00000001 2057 #define pde6_ai_WORD word2 2058 #define pde6_bs_SHIFT 16 2059 #define pde6_bs_MASK 0x00000007 2060 #define pde6_bs_WORD word2 2061 #define pde6_apptagval_SHIFT 0 2062 #define pde6_apptagval_MASK 0x0000ffff 2063 #define pde6_apptagval_WORD word2 2064 }; 2065 2066 struct lpfc_pde7 { 2067 uint32_t word0; 2068 #define pde7_type_SHIFT 24 2069 #define pde7_type_MASK 0x000000ff 2070 #define pde7_type_WORD word0 2071 #define pde7_rsvd0_SHIFT 0 2072 #define pde7_rsvd0_MASK 0x00ffffff 2073 #define pde7_rsvd0_WORD word0 2074 uint32_t addrHigh; 2075 uint32_t addrLow; 2076 }; 2077 2078 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2079 2080 typedef struct { 2081 #ifdef __BIG_ENDIAN_BITFIELD 2082 uint32_t rsvd2:25; 2083 uint32_t acknowledgment:1; 2084 uint32_t version:1; 2085 uint32_t erase_or_prog:1; 2086 uint32_t update_flash:1; 2087 uint32_t update_ram:1; 2088 uint32_t method:1; 2089 uint32_t load_cmplt:1; 2090 #else /* __LITTLE_ENDIAN_BITFIELD */ 2091 uint32_t load_cmplt:1; 2092 uint32_t method:1; 2093 uint32_t update_ram:1; 2094 uint32_t update_flash:1; 2095 uint32_t erase_or_prog:1; 2096 uint32_t version:1; 2097 uint32_t acknowledgment:1; 2098 uint32_t rsvd2:25; 2099 #endif 2100 2101 uint32_t dl_to_adr_low; 2102 uint32_t dl_to_adr_high; 2103 uint32_t dl_len; 2104 union { 2105 uint32_t dl_from_mbx_offset; 2106 struct ulp_bde dl_from_bde; 2107 struct ulp_bde64 dl_from_bde64; 2108 } un; 2109 2110 } LOAD_SM_VAR; 2111 2112 /* Structure for MB Command READ_NVPARM (02) */ 2113 2114 typedef struct { 2115 uint32_t rsvd1[3]; /* Read as all one's */ 2116 uint32_t rsvd2; /* Read as all zero's */ 2117 uint32_t portname[2]; /* N_PORT name */ 2118 uint32_t nodename[2]; /* NODE name */ 2119 2120 #ifdef __BIG_ENDIAN_BITFIELD 2121 uint32_t pref_DID:24; 2122 uint32_t hardAL_PA:8; 2123 #else /* __LITTLE_ENDIAN_BITFIELD */ 2124 uint32_t hardAL_PA:8; 2125 uint32_t pref_DID:24; 2126 #endif 2127 2128 uint32_t rsvd3[21]; /* Read as all one's */ 2129 } READ_NV_VAR; 2130 2131 /* Structure for MB Command WRITE_NVPARMS (03) */ 2132 2133 typedef struct { 2134 uint32_t rsvd1[3]; /* Must be all one's */ 2135 uint32_t rsvd2; /* Must be all zero's */ 2136 uint32_t portname[2]; /* N_PORT name */ 2137 uint32_t nodename[2]; /* NODE name */ 2138 2139 #ifdef __BIG_ENDIAN_BITFIELD 2140 uint32_t pref_DID:24; 2141 uint32_t hardAL_PA:8; 2142 #else /* __LITTLE_ENDIAN_BITFIELD */ 2143 uint32_t hardAL_PA:8; 2144 uint32_t pref_DID:24; 2145 #endif 2146 2147 uint32_t rsvd3[21]; /* Must be all one's */ 2148 } WRITE_NV_VAR; 2149 2150 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2151 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2152 2153 typedef struct { 2154 uint32_t rsvd1; 2155 union { 2156 struct { 2157 struct ulp_bde xmit_bde; 2158 struct ulp_bde rcv_bde; 2159 } s1; 2160 struct { 2161 struct ulp_bde64 xmit_bde64; 2162 struct ulp_bde64 rcv_bde64; 2163 } s2; 2164 } un; 2165 } BIU_DIAG_VAR; 2166 2167 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2168 struct READ_EVENT_LOG_VAR { 2169 uint32_t word1; 2170 #define lpfc_event_log_SHIFT 29 2171 #define lpfc_event_log_MASK 0x00000001 2172 #define lpfc_event_log_WORD word1 2173 #define USE_MAILBOX_RESPONSE 1 2174 uint32_t offset; 2175 struct ulp_bde64 rcv_bde64; 2176 }; 2177 2178 /* Structure for MB Command INIT_LINK (05) */ 2179 2180 typedef struct { 2181 #ifdef __BIG_ENDIAN_BITFIELD 2182 uint32_t rsvd1:24; 2183 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2184 #else /* __LITTLE_ENDIAN_BITFIELD */ 2185 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2186 uint32_t rsvd1:24; 2187 #endif 2188 2189 #ifdef __BIG_ENDIAN_BITFIELD 2190 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2191 uint8_t rsvd2; 2192 uint16_t link_flags; 2193 #else /* __LITTLE_ENDIAN_BITFIELD */ 2194 uint16_t link_flags; 2195 uint8_t rsvd2; 2196 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2197 #endif 2198 2199 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2200 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2201 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2202 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2203 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2204 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2205 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2206 2207 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2208 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2209 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2210 2211 uint32_t link_speed; 2212 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2213 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2214 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2215 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2216 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2217 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2218 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2219 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2220 2221 } INIT_LINK_VAR; 2222 2223 /* Structure for MB Command DOWN_LINK (06) */ 2224 2225 typedef struct { 2226 uint32_t rsvd1; 2227 } DOWN_LINK_VAR; 2228 2229 /* Structure for MB Command CONFIG_LINK (07) */ 2230 2231 typedef struct { 2232 #ifdef __BIG_ENDIAN_BITFIELD 2233 uint32_t cr:1; 2234 uint32_t ci:1; 2235 uint32_t cr_delay:6; 2236 uint32_t cr_count:8; 2237 uint32_t rsvd1:8; 2238 uint32_t MaxBBC:8; 2239 #else /* __LITTLE_ENDIAN_BITFIELD */ 2240 uint32_t MaxBBC:8; 2241 uint32_t rsvd1:8; 2242 uint32_t cr_count:8; 2243 uint32_t cr_delay:6; 2244 uint32_t ci:1; 2245 uint32_t cr:1; 2246 #endif 2247 2248 uint32_t myId; 2249 uint32_t rsvd2; 2250 uint32_t edtov; 2251 uint32_t arbtov; 2252 uint32_t ratov; 2253 uint32_t rttov; 2254 uint32_t altov; 2255 uint32_t crtov; 2256 uint32_t citov; 2257 #ifdef __BIG_ENDIAN_BITFIELD 2258 uint32_t rrq_enable:1; 2259 uint32_t rrq_immed:1; 2260 uint32_t rsvd4:29; 2261 uint32_t ack0_enable:1; 2262 #else /* __LITTLE_ENDIAN_BITFIELD */ 2263 uint32_t ack0_enable:1; 2264 uint32_t rsvd4:29; 2265 uint32_t rrq_immed:1; 2266 uint32_t rrq_enable:1; 2267 #endif 2268 } CONFIG_LINK; 2269 2270 /* Structure for MB Command PART_SLIM (08) 2271 * will be removed since SLI1 is no longer supported! 2272 */ 2273 typedef struct { 2274 #ifdef __BIG_ENDIAN_BITFIELD 2275 uint16_t offCiocb; 2276 uint16_t numCiocb; 2277 uint16_t offRiocb; 2278 uint16_t numRiocb; 2279 #else /* __LITTLE_ENDIAN_BITFIELD */ 2280 uint16_t numCiocb; 2281 uint16_t offCiocb; 2282 uint16_t numRiocb; 2283 uint16_t offRiocb; 2284 #endif 2285 } RING_DEF; 2286 2287 typedef struct { 2288 #ifdef __BIG_ENDIAN_BITFIELD 2289 uint32_t unused1:24; 2290 uint32_t numRing:8; 2291 #else /* __LITTLE_ENDIAN_BITFIELD */ 2292 uint32_t numRing:8; 2293 uint32_t unused1:24; 2294 #endif 2295 2296 RING_DEF ringdef[4]; 2297 uint32_t hbainit; 2298 } PART_SLIM_VAR; 2299 2300 /* Structure for MB Command CONFIG_RING (09) */ 2301 2302 typedef struct { 2303 #ifdef __BIG_ENDIAN_BITFIELD 2304 uint32_t unused2:6; 2305 uint32_t recvSeq:1; 2306 uint32_t recvNotify:1; 2307 uint32_t numMask:8; 2308 uint32_t profile:8; 2309 uint32_t unused1:4; 2310 uint32_t ring:4; 2311 #else /* __LITTLE_ENDIAN_BITFIELD */ 2312 uint32_t ring:4; 2313 uint32_t unused1:4; 2314 uint32_t profile:8; 2315 uint32_t numMask:8; 2316 uint32_t recvNotify:1; 2317 uint32_t recvSeq:1; 2318 uint32_t unused2:6; 2319 #endif 2320 2321 #ifdef __BIG_ENDIAN_BITFIELD 2322 uint16_t maxRespXchg; 2323 uint16_t maxOrigXchg; 2324 #else /* __LITTLE_ENDIAN_BITFIELD */ 2325 uint16_t maxOrigXchg; 2326 uint16_t maxRespXchg; 2327 #endif 2328 2329 RR_REG rrRegs[6]; 2330 } CONFIG_RING_VAR; 2331 2332 /* Structure for MB Command RESET_RING (10) */ 2333 2334 typedef struct { 2335 uint32_t ring_no; 2336 } RESET_RING_VAR; 2337 2338 /* Structure for MB Command READ_CONFIG (11) */ 2339 2340 typedef struct { 2341 #ifdef __BIG_ENDIAN_BITFIELD 2342 uint32_t cr:1; 2343 uint32_t ci:1; 2344 uint32_t cr_delay:6; 2345 uint32_t cr_count:8; 2346 uint32_t InitBBC:8; 2347 uint32_t MaxBBC:8; 2348 #else /* __LITTLE_ENDIAN_BITFIELD */ 2349 uint32_t MaxBBC:8; 2350 uint32_t InitBBC:8; 2351 uint32_t cr_count:8; 2352 uint32_t cr_delay:6; 2353 uint32_t ci:1; 2354 uint32_t cr:1; 2355 #endif 2356 2357 #ifdef __BIG_ENDIAN_BITFIELD 2358 uint32_t topology:8; 2359 uint32_t myDid:24; 2360 #else /* __LITTLE_ENDIAN_BITFIELD */ 2361 uint32_t myDid:24; 2362 uint32_t topology:8; 2363 #endif 2364 2365 /* Defines for topology (defined previously) */ 2366 #ifdef __BIG_ENDIAN_BITFIELD 2367 uint32_t AR:1; 2368 uint32_t IR:1; 2369 uint32_t rsvd1:29; 2370 uint32_t ack0:1; 2371 #else /* __LITTLE_ENDIAN_BITFIELD */ 2372 uint32_t ack0:1; 2373 uint32_t rsvd1:29; 2374 uint32_t IR:1; 2375 uint32_t AR:1; 2376 #endif 2377 2378 uint32_t edtov; 2379 uint32_t arbtov; 2380 uint32_t ratov; 2381 uint32_t rttov; 2382 uint32_t altov; 2383 uint32_t lmt; 2384 #define LMT_RESERVED 0x000 /* Not used */ 2385 #define LMT_1Gb 0x004 2386 #define LMT_2Gb 0x008 2387 #define LMT_4Gb 0x040 2388 #define LMT_8Gb 0x080 2389 #define LMT_10Gb 0x100 2390 #define LMT_16Gb 0x200 2391 #define LMT_32Gb 0x400 2392 uint32_t rsvd2; 2393 uint32_t rsvd3; 2394 uint32_t max_xri; 2395 uint32_t max_iocb; 2396 uint32_t max_rpi; 2397 uint32_t avail_xri; 2398 uint32_t avail_iocb; 2399 uint32_t avail_rpi; 2400 uint32_t max_vpi; 2401 uint32_t rsvd4; 2402 uint32_t rsvd5; 2403 uint32_t avail_vpi; 2404 } READ_CONFIG_VAR; 2405 2406 /* Structure for MB Command READ_RCONFIG (12) */ 2407 2408 typedef struct { 2409 #ifdef __BIG_ENDIAN_BITFIELD 2410 uint32_t rsvd2:7; 2411 uint32_t recvNotify:1; 2412 uint32_t numMask:8; 2413 uint32_t profile:8; 2414 uint32_t rsvd1:4; 2415 uint32_t ring:4; 2416 #else /* __LITTLE_ENDIAN_BITFIELD */ 2417 uint32_t ring:4; 2418 uint32_t rsvd1:4; 2419 uint32_t profile:8; 2420 uint32_t numMask:8; 2421 uint32_t recvNotify:1; 2422 uint32_t rsvd2:7; 2423 #endif 2424 2425 #ifdef __BIG_ENDIAN_BITFIELD 2426 uint16_t maxResp; 2427 uint16_t maxOrig; 2428 #else /* __LITTLE_ENDIAN_BITFIELD */ 2429 uint16_t maxOrig; 2430 uint16_t maxResp; 2431 #endif 2432 2433 RR_REG rrRegs[6]; 2434 2435 #ifdef __BIG_ENDIAN_BITFIELD 2436 uint16_t cmdRingOffset; 2437 uint16_t cmdEntryCnt; 2438 uint16_t rspRingOffset; 2439 uint16_t rspEntryCnt; 2440 uint16_t nextCmdOffset; 2441 uint16_t rsvd3; 2442 uint16_t nextRspOffset; 2443 uint16_t rsvd4; 2444 #else /* __LITTLE_ENDIAN_BITFIELD */ 2445 uint16_t cmdEntryCnt; 2446 uint16_t cmdRingOffset; 2447 uint16_t rspEntryCnt; 2448 uint16_t rspRingOffset; 2449 uint16_t rsvd3; 2450 uint16_t nextCmdOffset; 2451 uint16_t rsvd4; 2452 uint16_t nextRspOffset; 2453 #endif 2454 } READ_RCONF_VAR; 2455 2456 /* Structure for MB Command READ_SPARM (13) */ 2457 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2458 2459 typedef struct { 2460 uint32_t rsvd1; 2461 uint32_t rsvd2; 2462 union { 2463 struct ulp_bde sp; /* This BDE points to struct serv_parm 2464 structure */ 2465 struct ulp_bde64 sp64; 2466 } un; 2467 #ifdef __BIG_ENDIAN_BITFIELD 2468 uint16_t rsvd3; 2469 uint16_t vpi; 2470 #else /* __LITTLE_ENDIAN_BITFIELD */ 2471 uint16_t vpi; 2472 uint16_t rsvd3; 2473 #endif 2474 } READ_SPARM_VAR; 2475 2476 /* Structure for MB Command READ_STATUS (14) */ 2477 2478 typedef struct { 2479 #ifdef __BIG_ENDIAN_BITFIELD 2480 uint32_t rsvd1:31; 2481 uint32_t clrCounters:1; 2482 uint16_t activeXriCnt; 2483 uint16_t activeRpiCnt; 2484 #else /* __LITTLE_ENDIAN_BITFIELD */ 2485 uint32_t clrCounters:1; 2486 uint32_t rsvd1:31; 2487 uint16_t activeRpiCnt; 2488 uint16_t activeXriCnt; 2489 #endif 2490 2491 uint32_t xmitByteCnt; 2492 uint32_t rcvByteCnt; 2493 uint32_t xmitFrameCnt; 2494 uint32_t rcvFrameCnt; 2495 uint32_t xmitSeqCnt; 2496 uint32_t rcvSeqCnt; 2497 uint32_t totalOrigExchanges; 2498 uint32_t totalRespExchanges; 2499 uint32_t rcvPbsyCnt; 2500 uint32_t rcvFbsyCnt; 2501 } READ_STATUS_VAR; 2502 2503 /* Structure for MB Command READ_RPI (15) */ 2504 /* Structure for MB Command READ_RPI64 (0x8F) */ 2505 2506 typedef struct { 2507 #ifdef __BIG_ENDIAN_BITFIELD 2508 uint16_t nextRpi; 2509 uint16_t reqRpi; 2510 uint32_t rsvd2:8; 2511 uint32_t DID:24; 2512 #else /* __LITTLE_ENDIAN_BITFIELD */ 2513 uint16_t reqRpi; 2514 uint16_t nextRpi; 2515 uint32_t DID:24; 2516 uint32_t rsvd2:8; 2517 #endif 2518 2519 union { 2520 struct ulp_bde sp; 2521 struct ulp_bde64 sp64; 2522 } un; 2523 2524 } READ_RPI_VAR; 2525 2526 /* Structure for MB Command READ_XRI (16) */ 2527 2528 typedef struct { 2529 #ifdef __BIG_ENDIAN_BITFIELD 2530 uint16_t nextXri; 2531 uint16_t reqXri; 2532 uint16_t rsvd1; 2533 uint16_t rpi; 2534 uint32_t rsvd2:8; 2535 uint32_t DID:24; 2536 uint32_t rsvd3:8; 2537 uint32_t SID:24; 2538 uint32_t rsvd4; 2539 uint8_t seqId; 2540 uint8_t rsvd5; 2541 uint16_t seqCount; 2542 uint16_t oxId; 2543 uint16_t rxId; 2544 uint32_t rsvd6:30; 2545 uint32_t si:1; 2546 uint32_t exchOrig:1; 2547 #else /* __LITTLE_ENDIAN_BITFIELD */ 2548 uint16_t reqXri; 2549 uint16_t nextXri; 2550 uint16_t rpi; 2551 uint16_t rsvd1; 2552 uint32_t DID:24; 2553 uint32_t rsvd2:8; 2554 uint32_t SID:24; 2555 uint32_t rsvd3:8; 2556 uint32_t rsvd4; 2557 uint16_t seqCount; 2558 uint8_t rsvd5; 2559 uint8_t seqId; 2560 uint16_t rxId; 2561 uint16_t oxId; 2562 uint32_t exchOrig:1; 2563 uint32_t si:1; 2564 uint32_t rsvd6:30; 2565 #endif 2566 } READ_XRI_VAR; 2567 2568 /* Structure for MB Command READ_REV (17) */ 2569 2570 typedef struct { 2571 #ifdef __BIG_ENDIAN_BITFIELD 2572 uint32_t cv:1; 2573 uint32_t rr:1; 2574 uint32_t rsvd2:2; 2575 uint32_t v3req:1; 2576 uint32_t v3rsp:1; 2577 uint32_t rsvd1:25; 2578 uint32_t rv:1; 2579 #else /* __LITTLE_ENDIAN_BITFIELD */ 2580 uint32_t rv:1; 2581 uint32_t rsvd1:25; 2582 uint32_t v3rsp:1; 2583 uint32_t v3req:1; 2584 uint32_t rsvd2:2; 2585 uint32_t rr:1; 2586 uint32_t cv:1; 2587 #endif 2588 2589 uint32_t biuRev; 2590 uint32_t smRev; 2591 union { 2592 uint32_t smFwRev; 2593 struct { 2594 #ifdef __BIG_ENDIAN_BITFIELD 2595 uint8_t ProgType; 2596 uint8_t ProgId; 2597 uint16_t ProgVer:4; 2598 uint16_t ProgRev:4; 2599 uint16_t ProgFixLvl:2; 2600 uint16_t ProgDistType:2; 2601 uint16_t DistCnt:4; 2602 #else /* __LITTLE_ENDIAN_BITFIELD */ 2603 uint16_t DistCnt:4; 2604 uint16_t ProgDistType:2; 2605 uint16_t ProgFixLvl:2; 2606 uint16_t ProgRev:4; 2607 uint16_t ProgVer:4; 2608 uint8_t ProgId; 2609 uint8_t ProgType; 2610 #endif 2611 2612 } b; 2613 } un; 2614 uint32_t endecRev; 2615 #ifdef __BIG_ENDIAN_BITFIELD 2616 uint8_t feaLevelHigh; 2617 uint8_t feaLevelLow; 2618 uint8_t fcphHigh; 2619 uint8_t fcphLow; 2620 #else /* __LITTLE_ENDIAN_BITFIELD */ 2621 uint8_t fcphLow; 2622 uint8_t fcphHigh; 2623 uint8_t feaLevelLow; 2624 uint8_t feaLevelHigh; 2625 #endif 2626 2627 uint32_t postKernRev; 2628 uint32_t opFwRev; 2629 uint8_t opFwName[16]; 2630 uint32_t sli1FwRev; 2631 uint8_t sli1FwName[16]; 2632 uint32_t sli2FwRev; 2633 uint8_t sli2FwName[16]; 2634 uint32_t sli3Feat; 2635 uint32_t RandomData[6]; 2636 } READ_REV_VAR; 2637 2638 /* Structure for MB Command READ_LINK_STAT (18) */ 2639 2640 typedef struct { 2641 uint32_t word0; 2642 2643 #define lpfc_read_link_stat_rec_SHIFT 0 2644 #define lpfc_read_link_stat_rec_MASK 0x1 2645 #define lpfc_read_link_stat_rec_WORD word0 2646 2647 #define lpfc_read_link_stat_gec_SHIFT 1 2648 #define lpfc_read_link_stat_gec_MASK 0x1 2649 #define lpfc_read_link_stat_gec_WORD word0 2650 2651 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2652 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2653 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2654 2655 #define lpfc_read_link_stat_rsvd_SHIFT 24 2656 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2657 #define lpfc_read_link_stat_rsvd_WORD word0 2658 2659 #define lpfc_read_link_stat_gec2_SHIFT 29 2660 #define lpfc_read_link_stat_gec2_MASK 0x1 2661 #define lpfc_read_link_stat_gec2_WORD word0 2662 2663 #define lpfc_read_link_stat_clrc_SHIFT 30 2664 #define lpfc_read_link_stat_clrc_MASK 0x1 2665 #define lpfc_read_link_stat_clrc_WORD word0 2666 2667 #define lpfc_read_link_stat_clof_SHIFT 31 2668 #define lpfc_read_link_stat_clof_MASK 0x1 2669 #define lpfc_read_link_stat_clof_WORD word0 2670 2671 uint32_t linkFailureCnt; 2672 uint32_t lossSyncCnt; 2673 uint32_t lossSignalCnt; 2674 uint32_t primSeqErrCnt; 2675 uint32_t invalidXmitWord; 2676 uint32_t crcCnt; 2677 uint32_t primSeqTimeout; 2678 uint32_t elasticOverrun; 2679 uint32_t arbTimeout; 2680 uint32_t advRecBufCredit; 2681 uint32_t curRecBufCredit; 2682 uint32_t advTransBufCredit; 2683 uint32_t curTransBufCredit; 2684 uint32_t recEofCount; 2685 uint32_t recEofdtiCount; 2686 uint32_t recEofniCount; 2687 uint32_t recSofcount; 2688 uint32_t rsvd1; 2689 uint32_t rsvd2; 2690 uint32_t recDrpXriCount; 2691 uint32_t fecCorrBlkCount; 2692 uint32_t fecUncorrBlkCount; 2693 } READ_LNK_VAR; 2694 2695 /* Structure for MB Command REG_LOGIN (19) */ 2696 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2697 2698 typedef struct { 2699 #ifdef __BIG_ENDIAN_BITFIELD 2700 uint16_t rsvd1; 2701 uint16_t rpi; 2702 uint32_t rsvd2:8; 2703 uint32_t did:24; 2704 #else /* __LITTLE_ENDIAN_BITFIELD */ 2705 uint16_t rpi; 2706 uint16_t rsvd1; 2707 uint32_t did:24; 2708 uint32_t rsvd2:8; 2709 #endif 2710 2711 union { 2712 struct ulp_bde sp; 2713 struct ulp_bde64 sp64; 2714 } un; 2715 2716 #ifdef __BIG_ENDIAN_BITFIELD 2717 uint16_t rsvd6; 2718 uint16_t vpi; 2719 #else /* __LITTLE_ENDIAN_BITFIELD */ 2720 uint16_t vpi; 2721 uint16_t rsvd6; 2722 #endif 2723 2724 } REG_LOGIN_VAR; 2725 2726 /* Word 30 contents for REG_LOGIN */ 2727 typedef union { 2728 struct { 2729 #ifdef __BIG_ENDIAN_BITFIELD 2730 uint16_t rsvd1:12; 2731 uint16_t wd30_class:4; 2732 uint16_t xri; 2733 #else /* __LITTLE_ENDIAN_BITFIELD */ 2734 uint16_t xri; 2735 uint16_t wd30_class:4; 2736 uint16_t rsvd1:12; 2737 #endif 2738 } f; 2739 uint32_t word; 2740 } REG_WD30; 2741 2742 /* Structure for MB Command UNREG_LOGIN (20) */ 2743 2744 typedef struct { 2745 #ifdef __BIG_ENDIAN_BITFIELD 2746 uint16_t rsvd1; 2747 uint16_t rpi; 2748 uint32_t rsvd2; 2749 uint32_t rsvd3; 2750 uint32_t rsvd4; 2751 uint32_t rsvd5; 2752 uint16_t rsvd6; 2753 uint16_t vpi; 2754 #else /* __LITTLE_ENDIAN_BITFIELD */ 2755 uint16_t rpi; 2756 uint16_t rsvd1; 2757 uint32_t rsvd2; 2758 uint32_t rsvd3; 2759 uint32_t rsvd4; 2760 uint32_t rsvd5; 2761 uint16_t vpi; 2762 uint16_t rsvd6; 2763 #endif 2764 } UNREG_LOGIN_VAR; 2765 2766 /* Structure for MB Command REG_VPI (0x96) */ 2767 typedef struct { 2768 #ifdef __BIG_ENDIAN_BITFIELD 2769 uint32_t rsvd1; 2770 uint32_t rsvd2:7; 2771 uint32_t upd:1; 2772 uint32_t sid:24; 2773 uint32_t wwn[2]; 2774 uint32_t rsvd5; 2775 uint16_t vfi; 2776 uint16_t vpi; 2777 #else /* __LITTLE_ENDIAN */ 2778 uint32_t rsvd1; 2779 uint32_t sid:24; 2780 uint32_t upd:1; 2781 uint32_t rsvd2:7; 2782 uint32_t wwn[2]; 2783 uint32_t rsvd5; 2784 uint16_t vpi; 2785 uint16_t vfi; 2786 #endif 2787 } REG_VPI_VAR; 2788 2789 /* Structure for MB Command UNREG_VPI (0x97) */ 2790 typedef struct { 2791 uint32_t rsvd1; 2792 #ifdef __BIG_ENDIAN_BITFIELD 2793 uint16_t rsvd2; 2794 uint16_t sli4_vpi; 2795 #else /* __LITTLE_ENDIAN */ 2796 uint16_t sli4_vpi; 2797 uint16_t rsvd2; 2798 #endif 2799 uint32_t rsvd3; 2800 uint32_t rsvd4; 2801 uint32_t rsvd5; 2802 #ifdef __BIG_ENDIAN_BITFIELD 2803 uint16_t rsvd6; 2804 uint16_t vpi; 2805 #else /* __LITTLE_ENDIAN */ 2806 uint16_t vpi; 2807 uint16_t rsvd6; 2808 #endif 2809 } UNREG_VPI_VAR; 2810 2811 /* Structure for MB Command UNREG_D_ID (0x23) */ 2812 2813 typedef struct { 2814 uint32_t did; 2815 uint32_t rsvd2; 2816 uint32_t rsvd3; 2817 uint32_t rsvd4; 2818 uint32_t rsvd5; 2819 #ifdef __BIG_ENDIAN_BITFIELD 2820 uint16_t rsvd6; 2821 uint16_t vpi; 2822 #else 2823 uint16_t vpi; 2824 uint16_t rsvd6; 2825 #endif 2826 } UNREG_D_ID_VAR; 2827 2828 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 2829 struct lpfc_mbx_read_top { 2830 uint32_t eventTag; /* Event tag */ 2831 uint32_t word2; 2832 #define lpfc_mbx_read_top_fa_SHIFT 12 2833 #define lpfc_mbx_read_top_fa_MASK 0x00000001 2834 #define lpfc_mbx_read_top_fa_WORD word2 2835 #define lpfc_mbx_read_top_mm_SHIFT 11 2836 #define lpfc_mbx_read_top_mm_MASK 0x00000001 2837 #define lpfc_mbx_read_top_mm_WORD word2 2838 #define lpfc_mbx_read_top_pb_SHIFT 9 2839 #define lpfc_mbx_read_top_pb_MASK 0X00000001 2840 #define lpfc_mbx_read_top_pb_WORD word2 2841 #define lpfc_mbx_read_top_il_SHIFT 8 2842 #define lpfc_mbx_read_top_il_MASK 0x00000001 2843 #define lpfc_mbx_read_top_il_WORD word2 2844 #define lpfc_mbx_read_top_att_type_SHIFT 0 2845 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 2846 #define lpfc_mbx_read_top_att_type_WORD word2 2847 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 2848 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 2849 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 2850 uint32_t word3; 2851 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 2852 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 2853 #define lpfc_mbx_read_top_alpa_granted_WORD word3 2854 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 2855 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 2856 #define lpfc_mbx_read_top_lip_alps_WORD word3 2857 #define lpfc_mbx_read_top_lip_type_SHIFT 8 2858 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 2859 #define lpfc_mbx_read_top_lip_type_WORD word3 2860 #define lpfc_mbx_read_top_topology_SHIFT 0 2861 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 2862 #define lpfc_mbx_read_top_topology_WORD word3 2863 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2864 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2865 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2866 /* store the LILP AL_PA position map into */ 2867 struct ulp_bde64 lilpBde64; 2868 #define LPFC_ALPA_MAP_SIZE 128 2869 uint32_t word7; 2870 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 2871 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 2872 #define lpfc_mbx_read_top_ld_lu_WORD word7 2873 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 2874 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 2875 #define lpfc_mbx_read_top_ld_tf_WORD word7 2876 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 2877 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 2878 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 2879 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 2880 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 2881 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 2882 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 2883 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 2884 #define lpfc_mbx_read_top_ld_tx_WORD word7 2885 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 2886 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 2887 #define lpfc_mbx_read_top_ld_rx_WORD word7 2888 uint32_t word8; 2889 #define lpfc_mbx_read_top_lu_SHIFT 31 2890 #define lpfc_mbx_read_top_lu_MASK 0x00000001 2891 #define lpfc_mbx_read_top_lu_WORD word8 2892 #define lpfc_mbx_read_top_tf_SHIFT 30 2893 #define lpfc_mbx_read_top_tf_MASK 0x00000001 2894 #define lpfc_mbx_read_top_tf_WORD word8 2895 #define lpfc_mbx_read_top_link_spd_SHIFT 8 2896 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 2897 #define lpfc_mbx_read_top_link_spd_WORD word8 2898 #define lpfc_mbx_read_top_nl_port_SHIFT 4 2899 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 2900 #define lpfc_mbx_read_top_nl_port_WORD word8 2901 #define lpfc_mbx_read_top_tx_SHIFT 2 2902 #define lpfc_mbx_read_top_tx_MASK 0x00000003 2903 #define lpfc_mbx_read_top_tx_WORD word8 2904 #define lpfc_mbx_read_top_rx_SHIFT 0 2905 #define lpfc_mbx_read_top_rx_MASK 0x00000003 2906 #define lpfc_mbx_read_top_rx_WORD word8 2907 #define LPFC_LINK_SPEED_UNKNOWN 0x0 2908 #define LPFC_LINK_SPEED_1GHZ 0x04 2909 #define LPFC_LINK_SPEED_2GHZ 0x08 2910 #define LPFC_LINK_SPEED_4GHZ 0x10 2911 #define LPFC_LINK_SPEED_8GHZ 0x20 2912 #define LPFC_LINK_SPEED_10GHZ 0x40 2913 #define LPFC_LINK_SPEED_16GHZ 0x80 2914 #define LPFC_LINK_SPEED_32GHZ 0x90 2915 }; 2916 2917 /* Structure for MB Command CLEAR_LA (22) */ 2918 2919 typedef struct { 2920 uint32_t eventTag; /* Event tag */ 2921 uint32_t rsvd1; 2922 } CLEAR_LA_VAR; 2923 2924 /* Structure for MB Command DUMP */ 2925 2926 typedef struct { 2927 #ifdef __BIG_ENDIAN_BITFIELD 2928 uint32_t rsvd:25; 2929 uint32_t ra:1; 2930 uint32_t co:1; 2931 uint32_t cv:1; 2932 uint32_t type:4; 2933 uint32_t entry_index:16; 2934 uint32_t region_id:16; 2935 #else /* __LITTLE_ENDIAN_BITFIELD */ 2936 uint32_t type:4; 2937 uint32_t cv:1; 2938 uint32_t co:1; 2939 uint32_t ra:1; 2940 uint32_t rsvd:25; 2941 uint32_t region_id:16; 2942 uint32_t entry_index:16; 2943 #endif 2944 2945 uint32_t sli4_length; 2946 uint32_t word_cnt; 2947 uint32_t resp_offset; 2948 } DUMP_VAR; 2949 2950 #define DMP_MEM_REG 0x1 2951 #define DMP_NV_PARAMS 0x2 2952 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 2953 #define DMP_WELL_KNOWN 0x4 2954 2955 #define DMP_REGION_VPD 0xe 2956 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2957 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2958 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2959 2960 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2961 #define DMP_VPORT_REGION_SIZE 0x200 2962 #define DMP_MBOX_OFFSET_WORD 0x5 2963 2964 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2965 #define DMP_RGN23_SIZE 0x400 2966 2967 #define WAKE_UP_PARMS_REGION_ID 4 2968 #define WAKE_UP_PARMS_WORD_SIZE 15 2969 2970 struct vport_rec { 2971 uint8_t wwpn[8]; 2972 uint8_t wwnn[8]; 2973 }; 2974 2975 #define VPORT_INFO_SIG 0x32324752 2976 #define VPORT_INFO_REV_MASK 0xff 2977 #define VPORT_INFO_REV 0x1 2978 #define MAX_STATIC_VPORT_COUNT 16 2979 struct static_vport_info { 2980 uint32_t signature; 2981 uint32_t rev; 2982 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2983 uint32_t resvd[66]; 2984 }; 2985 2986 /* Option rom version structure */ 2987 struct prog_id { 2988 #ifdef __BIG_ENDIAN_BITFIELD 2989 uint8_t type; 2990 uint8_t id; 2991 uint32_t ver:4; /* Major Version */ 2992 uint32_t rev:4; /* Revision */ 2993 uint32_t lev:2; /* Level */ 2994 uint32_t dist:2; /* Dist Type */ 2995 uint32_t num:4; /* number after dist type */ 2996 #else /* __LITTLE_ENDIAN_BITFIELD */ 2997 uint32_t num:4; /* number after dist type */ 2998 uint32_t dist:2; /* Dist Type */ 2999 uint32_t lev:2; /* Level */ 3000 uint32_t rev:4; /* Revision */ 3001 uint32_t ver:4; /* Major Version */ 3002 uint8_t id; 3003 uint8_t type; 3004 #endif 3005 }; 3006 3007 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3008 3009 struct update_cfg_var { 3010 #ifdef __BIG_ENDIAN_BITFIELD 3011 uint32_t rsvd2:16; 3012 uint32_t type:8; 3013 uint32_t rsvd:1; 3014 uint32_t ra:1; 3015 uint32_t co:1; 3016 uint32_t cv:1; 3017 uint32_t req:4; 3018 uint32_t entry_length:16; 3019 uint32_t region_id:16; 3020 #else /* __LITTLE_ENDIAN_BITFIELD */ 3021 uint32_t req:4; 3022 uint32_t cv:1; 3023 uint32_t co:1; 3024 uint32_t ra:1; 3025 uint32_t rsvd:1; 3026 uint32_t type:8; 3027 uint32_t rsvd2:16; 3028 uint32_t region_id:16; 3029 uint32_t entry_length:16; 3030 #endif 3031 3032 uint32_t resp_info; 3033 uint32_t byte_cnt; 3034 uint32_t data_offset; 3035 }; 3036 3037 struct hbq_mask { 3038 #ifdef __BIG_ENDIAN_BITFIELD 3039 uint8_t tmatch; 3040 uint8_t tmask; 3041 uint8_t rctlmatch; 3042 uint8_t rctlmask; 3043 #else /* __LITTLE_ENDIAN */ 3044 uint8_t rctlmask; 3045 uint8_t rctlmatch; 3046 uint8_t tmask; 3047 uint8_t tmatch; 3048 #endif 3049 }; 3050 3051 3052 /* Structure for MB Command CONFIG_HBQ (7c) */ 3053 3054 struct config_hbq_var { 3055 #ifdef __BIG_ENDIAN_BITFIELD 3056 uint32_t rsvd1 :7; 3057 uint32_t recvNotify :1; /* Receive Notification */ 3058 uint32_t numMask :8; /* # Mask Entries */ 3059 uint32_t profile :8; /* Selection Profile */ 3060 uint32_t rsvd2 :8; 3061 #else /* __LITTLE_ENDIAN */ 3062 uint32_t rsvd2 :8; 3063 uint32_t profile :8; /* Selection Profile */ 3064 uint32_t numMask :8; /* # Mask Entries */ 3065 uint32_t recvNotify :1; /* Receive Notification */ 3066 uint32_t rsvd1 :7; 3067 #endif 3068 3069 #ifdef __BIG_ENDIAN_BITFIELD 3070 uint32_t hbqId :16; 3071 uint32_t rsvd3 :12; 3072 uint32_t ringMask :4; 3073 #else /* __LITTLE_ENDIAN */ 3074 uint32_t ringMask :4; 3075 uint32_t rsvd3 :12; 3076 uint32_t hbqId :16; 3077 #endif 3078 3079 #ifdef __BIG_ENDIAN_BITFIELD 3080 uint32_t entry_count :16; 3081 uint32_t rsvd4 :8; 3082 uint32_t headerLen :8; 3083 #else /* __LITTLE_ENDIAN */ 3084 uint32_t headerLen :8; 3085 uint32_t rsvd4 :8; 3086 uint32_t entry_count :16; 3087 #endif 3088 3089 uint32_t hbqaddrLow; 3090 uint32_t hbqaddrHigh; 3091 3092 #ifdef __BIG_ENDIAN_BITFIELD 3093 uint32_t rsvd5 :31; 3094 uint32_t logEntry :1; 3095 #else /* __LITTLE_ENDIAN */ 3096 uint32_t logEntry :1; 3097 uint32_t rsvd5 :31; 3098 #endif 3099 3100 uint32_t rsvd6; /* w7 */ 3101 uint32_t rsvd7; /* w8 */ 3102 uint32_t rsvd8; /* w9 */ 3103 3104 struct hbq_mask hbqMasks[6]; 3105 3106 3107 union { 3108 uint32_t allprofiles[12]; 3109 3110 struct { 3111 #ifdef __BIG_ENDIAN_BITFIELD 3112 uint32_t seqlenoff :16; 3113 uint32_t maxlen :16; 3114 #else /* __LITTLE_ENDIAN */ 3115 uint32_t maxlen :16; 3116 uint32_t seqlenoff :16; 3117 #endif 3118 #ifdef __BIG_ENDIAN_BITFIELD 3119 uint32_t rsvd1 :28; 3120 uint32_t seqlenbcnt :4; 3121 #else /* __LITTLE_ENDIAN */ 3122 uint32_t seqlenbcnt :4; 3123 uint32_t rsvd1 :28; 3124 #endif 3125 uint32_t rsvd[10]; 3126 } profile2; 3127 3128 struct { 3129 #ifdef __BIG_ENDIAN_BITFIELD 3130 uint32_t seqlenoff :16; 3131 uint32_t maxlen :16; 3132 #else /* __LITTLE_ENDIAN */ 3133 uint32_t maxlen :16; 3134 uint32_t seqlenoff :16; 3135 #endif 3136 #ifdef __BIG_ENDIAN_BITFIELD 3137 uint32_t cmdcodeoff :28; 3138 uint32_t rsvd1 :12; 3139 uint32_t seqlenbcnt :4; 3140 #else /* __LITTLE_ENDIAN */ 3141 uint32_t seqlenbcnt :4; 3142 uint32_t rsvd1 :12; 3143 uint32_t cmdcodeoff :28; 3144 #endif 3145 uint32_t cmdmatch[8]; 3146 3147 uint32_t rsvd[2]; 3148 } profile3; 3149 3150 struct { 3151 #ifdef __BIG_ENDIAN_BITFIELD 3152 uint32_t seqlenoff :16; 3153 uint32_t maxlen :16; 3154 #else /* __LITTLE_ENDIAN */ 3155 uint32_t maxlen :16; 3156 uint32_t seqlenoff :16; 3157 #endif 3158 #ifdef __BIG_ENDIAN_BITFIELD 3159 uint32_t cmdcodeoff :28; 3160 uint32_t rsvd1 :12; 3161 uint32_t seqlenbcnt :4; 3162 #else /* __LITTLE_ENDIAN */ 3163 uint32_t seqlenbcnt :4; 3164 uint32_t rsvd1 :12; 3165 uint32_t cmdcodeoff :28; 3166 #endif 3167 uint32_t cmdmatch[8]; 3168 3169 uint32_t rsvd[2]; 3170 } profile5; 3171 3172 } profiles; 3173 3174 }; 3175 3176 3177 3178 /* Structure for MB Command CONFIG_PORT (0x88) */ 3179 typedef struct { 3180 #ifdef __BIG_ENDIAN_BITFIELD 3181 uint32_t cBE : 1; 3182 uint32_t cET : 1; 3183 uint32_t cHpcb : 1; 3184 uint32_t cMA : 1; 3185 uint32_t sli_mode : 4; 3186 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3187 * config block */ 3188 #else /* __LITTLE_ENDIAN */ 3189 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3190 * config block */ 3191 uint32_t sli_mode : 4; 3192 uint32_t cMA : 1; 3193 uint32_t cHpcb : 1; 3194 uint32_t cET : 1; 3195 uint32_t cBE : 1; 3196 #endif 3197 3198 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3199 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3200 uint32_t hbainit[5]; 3201 #ifdef __BIG_ENDIAN_BITFIELD 3202 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3203 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3204 #else /* __LITTLE_ENDIAN */ 3205 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3206 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3207 #endif 3208 3209 #ifdef __BIG_ENDIAN_BITFIELD 3210 uint32_t rsvd1 : 19; /* Reserved */ 3211 uint32_t cdss : 1; /* Configure Data Security SLI */ 3212 uint32_t casabt : 1; /* Configure async abts status notice */ 3213 uint32_t rsvd2 : 2; /* Reserved */ 3214 uint32_t cbg : 1; /* Configure BlockGuard */ 3215 uint32_t cmv : 1; /* Configure Max VPIs */ 3216 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3217 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3218 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3219 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3220 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3221 uint32_t cmx : 1; /* Configure Max XRIs */ 3222 uint32_t cmr : 1; /* Configure Max RPIs */ 3223 #else /* __LITTLE_ENDIAN */ 3224 uint32_t cmr : 1; /* Configure Max RPIs */ 3225 uint32_t cmx : 1; /* Configure Max XRIs */ 3226 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3227 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3228 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3229 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3230 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3231 uint32_t cmv : 1; /* Configure Max VPIs */ 3232 uint32_t cbg : 1; /* Configure BlockGuard */ 3233 uint32_t rsvd2 : 2; /* Reserved */ 3234 uint32_t casabt : 1; /* Configure async abts status notice */ 3235 uint32_t cdss : 1; /* Configure Data Security SLI */ 3236 uint32_t rsvd1 : 19; /* Reserved */ 3237 #endif 3238 #ifdef __BIG_ENDIAN_BITFIELD 3239 uint32_t rsvd3 : 19; /* Reserved */ 3240 uint32_t gdss : 1; /* Configure Data Security SLI */ 3241 uint32_t gasabt : 1; /* Grant async abts status notice */ 3242 uint32_t rsvd4 : 2; /* Reserved */ 3243 uint32_t gbg : 1; /* Grant BlockGuard */ 3244 uint32_t gmv : 1; /* Grant Max VPIs */ 3245 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3246 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3247 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3248 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3249 uint32_t gerbm : 1; /* Grant ERBM Request */ 3250 uint32_t gmx : 1; /* Grant Max XRIs */ 3251 uint32_t gmr : 1; /* Grant Max RPIs */ 3252 #else /* __LITTLE_ENDIAN */ 3253 uint32_t gmr : 1; /* Grant Max RPIs */ 3254 uint32_t gmx : 1; /* Grant Max XRIs */ 3255 uint32_t gerbm : 1; /* Grant ERBM Request */ 3256 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3257 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3258 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3259 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3260 uint32_t gmv : 1; /* Grant Max VPIs */ 3261 uint32_t gbg : 1; /* Grant BlockGuard */ 3262 uint32_t rsvd4 : 2; /* Reserved */ 3263 uint32_t gasabt : 1; /* Grant async abts status notice */ 3264 uint32_t gdss : 1; /* Configure Data Security SLI */ 3265 uint32_t rsvd3 : 19; /* Reserved */ 3266 #endif 3267 3268 #ifdef __BIG_ENDIAN_BITFIELD 3269 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3270 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3271 #else /* __LITTLE_ENDIAN */ 3272 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3273 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3274 #endif 3275 3276 #ifdef __BIG_ENDIAN_BITFIELD 3277 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3278 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3279 #else /* __LITTLE_ENDIAN */ 3280 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3281 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3282 #endif 3283 3284 uint32_t rsvd6; /* Reserved */ 3285 3286 #ifdef __BIG_ENDIAN_BITFIELD 3287 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 3288 uint32_t fips_level : 4; /* FIPS Level */ 3289 uint32_t sec_err : 9; /* security crypto error */ 3290 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3291 #else /* __LITTLE_ENDIAN */ 3292 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3293 uint32_t sec_err : 9; /* security crypto error */ 3294 uint32_t fips_level : 4; /* FIPS Level */ 3295 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 3296 #endif 3297 3298 } CONFIG_PORT_VAR; 3299 3300 /* Structure for MB Command CONFIG_MSI (0x30) */ 3301 struct config_msi_var { 3302 #ifdef __BIG_ENDIAN_BITFIELD 3303 uint32_t dfltMsgNum:8; /* Default message number */ 3304 uint32_t rsvd1:11; /* Reserved */ 3305 uint32_t NID:5; /* Number of secondary attention IDs */ 3306 uint32_t rsvd2:5; /* Reserved */ 3307 uint32_t dfltPresent:1; /* Default message number present */ 3308 uint32_t addFlag:1; /* Add association flag */ 3309 uint32_t reportFlag:1; /* Report association flag */ 3310 #else /* __LITTLE_ENDIAN_BITFIELD */ 3311 uint32_t reportFlag:1; /* Report association flag */ 3312 uint32_t addFlag:1; /* Add association flag */ 3313 uint32_t dfltPresent:1; /* Default message number present */ 3314 uint32_t rsvd2:5; /* Reserved */ 3315 uint32_t NID:5; /* Number of secondary attention IDs */ 3316 uint32_t rsvd1:11; /* Reserved */ 3317 uint32_t dfltMsgNum:8; /* Default message number */ 3318 #endif 3319 uint32_t attentionConditions[2]; 3320 uint8_t attentionId[16]; 3321 uint8_t messageNumberByHA[64]; 3322 uint8_t messageNumberByID[16]; 3323 uint32_t autoClearHA[2]; 3324 #ifdef __BIG_ENDIAN_BITFIELD 3325 uint32_t rsvd3:16; 3326 uint32_t autoClearID:16; 3327 #else /* __LITTLE_ENDIAN_BITFIELD */ 3328 uint32_t autoClearID:16; 3329 uint32_t rsvd3:16; 3330 #endif 3331 uint32_t rsvd4; 3332 }; 3333 3334 /* SLI-2 Port Control Block */ 3335 3336 /* SLIM POINTER */ 3337 #define SLIMOFF 0x30 /* WORD */ 3338 3339 typedef struct _SLI2_RDSC { 3340 uint32_t cmdEntries; 3341 uint32_t cmdAddrLow; 3342 uint32_t cmdAddrHigh; 3343 3344 uint32_t rspEntries; 3345 uint32_t rspAddrLow; 3346 uint32_t rspAddrHigh; 3347 } SLI2_RDSC; 3348 3349 typedef struct _PCB { 3350 #ifdef __BIG_ENDIAN_BITFIELD 3351 uint32_t type:8; 3352 #define TYPE_NATIVE_SLI2 0x01 3353 uint32_t feature:8; 3354 #define FEATURE_INITIAL_SLI2 0x01 3355 uint32_t rsvd:12; 3356 uint32_t maxRing:4; 3357 #else /* __LITTLE_ENDIAN_BITFIELD */ 3358 uint32_t maxRing:4; 3359 uint32_t rsvd:12; 3360 uint32_t feature:8; 3361 #define FEATURE_INITIAL_SLI2 0x01 3362 uint32_t type:8; 3363 #define TYPE_NATIVE_SLI2 0x01 3364 #endif 3365 3366 uint32_t mailBoxSize; 3367 uint32_t mbAddrLow; 3368 uint32_t mbAddrHigh; 3369 3370 uint32_t hgpAddrLow; 3371 uint32_t hgpAddrHigh; 3372 3373 uint32_t pgpAddrLow; 3374 uint32_t pgpAddrHigh; 3375 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3376 } PCB_t; 3377 3378 /* NEW_FEATURE */ 3379 typedef struct { 3380 #ifdef __BIG_ENDIAN_BITFIELD 3381 uint32_t rsvd0:27; 3382 uint32_t discardFarp:1; 3383 uint32_t IPEnable:1; 3384 uint32_t nodeName:1; 3385 uint32_t portName:1; 3386 uint32_t filterEnable:1; 3387 #else /* __LITTLE_ENDIAN_BITFIELD */ 3388 uint32_t filterEnable:1; 3389 uint32_t portName:1; 3390 uint32_t nodeName:1; 3391 uint32_t IPEnable:1; 3392 uint32_t discardFarp:1; 3393 uint32_t rsvd:27; 3394 #endif 3395 3396 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3397 uint8_t nodename[8]; 3398 uint32_t rsvd1; 3399 uint32_t rsvd2; 3400 uint32_t rsvd3; 3401 uint32_t IPAddress; 3402 } CONFIG_FARP_VAR; 3403 3404 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3405 3406 typedef struct { 3407 #ifdef __BIG_ENDIAN_BITFIELD 3408 uint32_t rsvd:30; 3409 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3410 #else /* __LITTLE_ENDIAN */ 3411 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3412 uint32_t rsvd:30; 3413 #endif 3414 } ASYNCEVT_ENABLE_VAR; 3415 3416 /* Union of all Mailbox Command types */ 3417 #define MAILBOX_CMD_WSIZE 32 3418 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3419 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3420 #define MAILBOX_EXT_WSIZE 512 3421 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3422 #define MAILBOX_HBA_EXT_OFFSET 0x100 3423 /* max mbox xmit size is a page size for sysfs IO operations */ 3424 #define MAILBOX_SYSFS_MAX 4096 3425 3426 typedef union { 3427 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3428 * feature/max ring number 3429 */ 3430 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3431 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3432 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3433 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3434 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3435 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3436 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3437 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3438 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3439 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3440 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3441 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3442 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3443 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3444 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3445 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3446 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3447 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3448 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3449 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3450 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3451 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3452 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3453 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3454 * NEW_FEATURE 3455 */ 3456 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3457 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3458 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3459 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3460 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3461 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3462 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3463 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3464 * (READ_EVENT_LOG) 3465 */ 3466 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3467 } MAILVARIANTS; 3468 3469 /* 3470 * SLI-2 specific structures 3471 */ 3472 3473 struct lpfc_hgp { 3474 __le32 cmdPutInx; 3475 __le32 rspGetInx; 3476 }; 3477 3478 struct lpfc_pgp { 3479 __le32 cmdGetInx; 3480 __le32 rspPutInx; 3481 }; 3482 3483 struct sli2_desc { 3484 uint32_t unused1[16]; 3485 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3486 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3487 }; 3488 3489 struct sli3_desc { 3490 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3491 uint32_t reserved[8]; 3492 uint32_t hbq_put[16]; 3493 }; 3494 3495 struct sli3_pgp { 3496 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3497 uint32_t hbq_get[16]; 3498 }; 3499 3500 union sli_var { 3501 struct sli2_desc s2; 3502 struct sli3_desc s3; 3503 struct sli3_pgp s3_pgp; 3504 }; 3505 3506 typedef struct { 3507 #ifdef __BIG_ENDIAN_BITFIELD 3508 uint16_t mbxStatus; 3509 uint8_t mbxCommand; 3510 uint8_t mbxReserved:6; 3511 uint8_t mbxHc:1; 3512 uint8_t mbxOwner:1; /* Low order bit first word */ 3513 #else /* __LITTLE_ENDIAN_BITFIELD */ 3514 uint8_t mbxOwner:1; /* Low order bit first word */ 3515 uint8_t mbxHc:1; 3516 uint8_t mbxReserved:6; 3517 uint8_t mbxCommand; 3518 uint16_t mbxStatus; 3519 #endif 3520 3521 MAILVARIANTS un; 3522 union sli_var us; 3523 } MAILBOX_t; 3524 3525 /* 3526 * Begin Structure Definitions for IOCB Commands 3527 */ 3528 3529 typedef struct { 3530 #ifdef __BIG_ENDIAN_BITFIELD 3531 uint8_t statAction; 3532 uint8_t statRsn; 3533 uint8_t statBaExp; 3534 uint8_t statLocalError; 3535 #else /* __LITTLE_ENDIAN_BITFIELD */ 3536 uint8_t statLocalError; 3537 uint8_t statBaExp; 3538 uint8_t statRsn; 3539 uint8_t statAction; 3540 #endif 3541 /* statRsn P/F_RJT reason codes */ 3542 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3543 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3544 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3545 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3546 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3547 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3548 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3549 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3550 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3551 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3552 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3553 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3554 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3555 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3556 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3557 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3558 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3559 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3560 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3561 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3562 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3563 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3564 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3565 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3566 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3567 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3568 3569 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3570 #define IOERR_MISSING_CONTINUE 0x01 3571 #define IOERR_SEQUENCE_TIMEOUT 0x02 3572 #define IOERR_INTERNAL_ERROR 0x03 3573 #define IOERR_INVALID_RPI 0x04 3574 #define IOERR_NO_XRI 0x05 3575 #define IOERR_ILLEGAL_COMMAND 0x06 3576 #define IOERR_XCHG_DROPPED 0x07 3577 #define IOERR_ILLEGAL_FIELD 0x08 3578 #define IOERR_BAD_CONTINUE 0x09 3579 #define IOERR_TOO_MANY_BUFFERS 0x0A 3580 #define IOERR_RCV_BUFFER_WAITING 0x0B 3581 #define IOERR_NO_CONNECTION 0x0C 3582 #define IOERR_TX_DMA_FAILED 0x0D 3583 #define IOERR_RX_DMA_FAILED 0x0E 3584 #define IOERR_ILLEGAL_FRAME 0x0F 3585 #define IOERR_EXTRA_DATA 0x10 3586 #define IOERR_NO_RESOURCES 0x11 3587 #define IOERR_RESERVED 0x12 3588 #define IOERR_ILLEGAL_LENGTH 0x13 3589 #define IOERR_UNSUPPORTED_FEATURE 0x14 3590 #define IOERR_ABORT_IN_PROGRESS 0x15 3591 #define IOERR_ABORT_REQUESTED 0x16 3592 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3593 #define IOERR_LOOP_OPEN_FAILURE 0x18 3594 #define IOERR_RING_RESET 0x19 3595 #define IOERR_LINK_DOWN 0x1A 3596 #define IOERR_CORRUPTED_DATA 0x1B 3597 #define IOERR_CORRUPTED_RPI 0x1C 3598 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3599 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3600 #define IOERR_DUP_FRAME 0x1F 3601 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3602 #define IOERR_BAD_HOST_ADDRESS 0x21 3603 #define IOERR_RCV_HDRBUF_WAITING 0x22 3604 #define IOERR_MISSING_HDR_BUFFER 0x23 3605 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3606 #define IOERR_ABORTMULT_REQUESTED 0x25 3607 #define IOERR_BUFFER_SHORTAGE 0x28 3608 #define IOERR_DEFAULT 0x29 3609 #define IOERR_CNT 0x2A 3610 #define IOERR_SLER_FAILURE 0x46 3611 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3612 #define IOERR_SLER_REC_RJT_ERR 0x48 3613 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3614 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3615 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3616 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3617 #define IOERR_SLER_ABTS_ERR 0x4E 3618 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3619 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3620 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3621 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3622 #define IOERR_DRVR_MASK 0x100 3623 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3624 #define IOERR_SLI_BRESET 0x102 3625 #define IOERR_SLI_ABORTED 0x103 3626 #define IOERR_PARAM_MASK 0x1ff 3627 } PARM_ERR; 3628 3629 typedef union { 3630 struct { 3631 #ifdef __BIG_ENDIAN_BITFIELD 3632 uint8_t Rctl; /* R_CTL field */ 3633 uint8_t Type; /* TYPE field */ 3634 uint8_t Dfctl; /* DF_CTL field */ 3635 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3636 #else /* __LITTLE_ENDIAN_BITFIELD */ 3637 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3638 uint8_t Dfctl; /* DF_CTL field */ 3639 uint8_t Type; /* TYPE field */ 3640 uint8_t Rctl; /* R_CTL field */ 3641 #endif 3642 3643 #define BC 0x02 /* Broadcast Received - Fctl */ 3644 #define SI 0x04 /* Sequence Initiative */ 3645 #define LA 0x08 /* Ignore Link Attention state */ 3646 #define LS 0x80 /* Last Sequence */ 3647 } hcsw; 3648 uint32_t reserved; 3649 } WORD5; 3650 3651 /* IOCB Command template for a generic response */ 3652 typedef struct { 3653 uint32_t reserved[4]; 3654 PARM_ERR perr; 3655 } GENERIC_RSP; 3656 3657 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3658 typedef struct { 3659 struct ulp_bde xrsqbde[2]; 3660 uint32_t xrsqRo; /* Starting Relative Offset */ 3661 WORD5 w5; /* Header control/status word */ 3662 } XR_SEQ_FIELDS; 3663 3664 /* IOCB Command template for ELS_REQUEST */ 3665 typedef struct { 3666 struct ulp_bde elsReq; 3667 struct ulp_bde elsRsp; 3668 3669 #ifdef __BIG_ENDIAN_BITFIELD 3670 uint32_t word4Rsvd:7; 3671 uint32_t fl:1; 3672 uint32_t myID:24; 3673 uint32_t word5Rsvd:8; 3674 uint32_t remoteID:24; 3675 #else /* __LITTLE_ENDIAN_BITFIELD */ 3676 uint32_t myID:24; 3677 uint32_t fl:1; 3678 uint32_t word4Rsvd:7; 3679 uint32_t remoteID:24; 3680 uint32_t word5Rsvd:8; 3681 #endif 3682 } ELS_REQUEST; 3683 3684 /* IOCB Command template for RCV_ELS_REQ */ 3685 typedef struct { 3686 struct ulp_bde elsReq[2]; 3687 uint32_t parmRo; 3688 3689 #ifdef __BIG_ENDIAN_BITFIELD 3690 uint32_t word5Rsvd:8; 3691 uint32_t remoteID:24; 3692 #else /* __LITTLE_ENDIAN_BITFIELD */ 3693 uint32_t remoteID:24; 3694 uint32_t word5Rsvd:8; 3695 #endif 3696 } RCV_ELS_REQ; 3697 3698 /* IOCB Command template for ABORT / CLOSE_XRI */ 3699 typedef struct { 3700 uint32_t rsvd[3]; 3701 uint32_t abortType; 3702 #define ABORT_TYPE_ABTX 0x00000000 3703 #define ABORT_TYPE_ABTS 0x00000001 3704 uint32_t parm; 3705 #ifdef __BIG_ENDIAN_BITFIELD 3706 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3707 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3708 #else /* __LITTLE_ENDIAN_BITFIELD */ 3709 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3710 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3711 #endif 3712 } AC_XRI; 3713 3714 /* IOCB Command template for ABORT_MXRI64 */ 3715 typedef struct { 3716 uint32_t rsvd[3]; 3717 uint32_t abortType; 3718 uint32_t parm; 3719 uint32_t iotag32; 3720 } A_MXRI64; 3721 3722 /* IOCB Command template for GET_RPI */ 3723 typedef struct { 3724 uint32_t rsvd[4]; 3725 uint32_t parmRo; 3726 #ifdef __BIG_ENDIAN_BITFIELD 3727 uint32_t word5Rsvd:8; 3728 uint32_t remoteID:24; 3729 #else /* __LITTLE_ENDIAN_BITFIELD */ 3730 uint32_t remoteID:24; 3731 uint32_t word5Rsvd:8; 3732 #endif 3733 } GET_RPI; 3734 3735 /* IOCB Command template for all FCP Initiator commands */ 3736 typedef struct { 3737 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3738 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3739 uint32_t fcpi_parm; 3740 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3741 } FCPI_FIELDS; 3742 3743 /* IOCB Command template for all FCP Target commands */ 3744 typedef struct { 3745 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3746 uint32_t fcpt_Offset; 3747 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3748 } FCPT_FIELDS; 3749 3750 /* SLI-2 IOCB structure definitions */ 3751 3752 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3753 typedef struct { 3754 ULP_BDL bdl; 3755 uint32_t xrsqRo; /* Starting Relative Offset */ 3756 WORD5 w5; /* Header control/status word */ 3757 } XMT_SEQ_FIELDS64; 3758 3759 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 3760 #define xmit_els_remoteID xrsqRo 3761 3762 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3763 typedef struct { 3764 struct ulp_bde64 rcvBde; 3765 uint32_t rsvd1; 3766 uint32_t xrsqRo; /* Starting Relative Offset */ 3767 WORD5 w5; /* Header control/status word */ 3768 } RCV_SEQ_FIELDS64; 3769 3770 /* IOCB Command template for ELS_REQUEST64 */ 3771 typedef struct { 3772 ULP_BDL bdl; 3773 #ifdef __BIG_ENDIAN_BITFIELD 3774 uint32_t word4Rsvd:7; 3775 uint32_t fl:1; 3776 uint32_t myID:24; 3777 uint32_t word5Rsvd:8; 3778 uint32_t remoteID:24; 3779 #else /* __LITTLE_ENDIAN_BITFIELD */ 3780 uint32_t myID:24; 3781 uint32_t fl:1; 3782 uint32_t word4Rsvd:7; 3783 uint32_t remoteID:24; 3784 uint32_t word5Rsvd:8; 3785 #endif 3786 } ELS_REQUEST64; 3787 3788 /* IOCB Command template for GEN_REQUEST64 */ 3789 typedef struct { 3790 ULP_BDL bdl; 3791 uint32_t xrsqRo; /* Starting Relative Offset */ 3792 WORD5 w5; /* Header control/status word */ 3793 } GEN_REQUEST64; 3794 3795 /* IOCB Command template for RCV_ELS_REQ64 */ 3796 typedef struct { 3797 struct ulp_bde64 elsReq; 3798 uint32_t rcvd1; 3799 uint32_t parmRo; 3800 3801 #ifdef __BIG_ENDIAN_BITFIELD 3802 uint32_t word5Rsvd:8; 3803 uint32_t remoteID:24; 3804 #else /* __LITTLE_ENDIAN_BITFIELD */ 3805 uint32_t remoteID:24; 3806 uint32_t word5Rsvd:8; 3807 #endif 3808 } RCV_ELS_REQ64; 3809 3810 /* IOCB Command template for RCV_SEQ64 */ 3811 struct rcv_seq64 { 3812 struct ulp_bde64 elsReq; 3813 uint32_t hbq_1; 3814 uint32_t parmRo; 3815 #ifdef __BIG_ENDIAN_BITFIELD 3816 uint32_t rctl:8; 3817 uint32_t type:8; 3818 uint32_t dfctl:8; 3819 uint32_t ls:1; 3820 uint32_t fs:1; 3821 uint32_t rsvd2:3; 3822 uint32_t si:1; 3823 uint32_t bc:1; 3824 uint32_t rsvd3:1; 3825 #else /* __LITTLE_ENDIAN_BITFIELD */ 3826 uint32_t rsvd3:1; 3827 uint32_t bc:1; 3828 uint32_t si:1; 3829 uint32_t rsvd2:3; 3830 uint32_t fs:1; 3831 uint32_t ls:1; 3832 uint32_t dfctl:8; 3833 uint32_t type:8; 3834 uint32_t rctl:8; 3835 #endif 3836 }; 3837 3838 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3839 typedef struct { 3840 ULP_BDL bdl; 3841 uint32_t fcpi_parm; 3842 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3843 } FCPI_FIELDS64; 3844 3845 /* IOCB Command template for all 64 bit FCP Target commands */ 3846 typedef struct { 3847 ULP_BDL bdl; 3848 uint32_t fcpt_Offset; 3849 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3850 } FCPT_FIELDS64; 3851 3852 /* IOCB Command template for Async Status iocb commands */ 3853 typedef struct { 3854 uint32_t rsvd[4]; 3855 uint32_t param; 3856 #ifdef __BIG_ENDIAN_BITFIELD 3857 uint16_t evt_code; /* High order bits word 5 */ 3858 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3859 #else /* __LITTLE_ENDIAN_BITFIELD */ 3860 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3861 uint16_t evt_code; /* Low order bits word 5 */ 3862 #endif 3863 } ASYNCSTAT_FIELDS; 3864 #define ASYNC_TEMP_WARN 0x100 3865 #define ASYNC_TEMP_SAFE 0x101 3866 #define ASYNC_STATUS_CN 0x102 3867 3868 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3869 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3870 3871 struct rcv_sli3 { 3872 #ifdef __BIG_ENDIAN_BITFIELD 3873 uint16_t ox_id; 3874 uint16_t seq_cnt; 3875 3876 uint16_t vpi; 3877 uint16_t word9Rsvd; 3878 #else /* __LITTLE_ENDIAN */ 3879 uint16_t seq_cnt; 3880 uint16_t ox_id; 3881 3882 uint16_t word9Rsvd; 3883 uint16_t vpi; 3884 #endif 3885 uint32_t word10Rsvd; 3886 uint32_t acc_len; /* accumulated length */ 3887 struct ulp_bde64 bde2; 3888 }; 3889 3890 /* Structure used for a single HBQ entry */ 3891 struct lpfc_hbq_entry { 3892 struct ulp_bde64 bde; 3893 uint32_t buffer_tag; 3894 }; 3895 3896 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3897 typedef struct { 3898 struct lpfc_hbq_entry buff; 3899 uint32_t rsvd; 3900 uint32_t rsvd1; 3901 } QUE_XRI64_CX_FIELDS; 3902 3903 struct que_xri64cx_ext_fields { 3904 uint32_t iotag64_low; 3905 uint32_t iotag64_high; 3906 uint32_t ebde_count; 3907 uint32_t rsvd; 3908 struct lpfc_hbq_entry buff[5]; 3909 }; 3910 3911 struct sli3_bg_fields { 3912 uint32_t filler[6]; /* word 8-13 in IOCB */ 3913 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3914 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3915 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3916 #define BGS_BIDIR_BG_PROF_SHIFT 24 3917 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3918 #define BGS_BIDIR_ERR_COND_SHIFT 16 3919 #define BGS_BG_PROFILE_MASK 0x0000ff00 3920 #define BGS_BG_PROFILE_SHIFT 8 3921 #define BGS_INVALID_PROF_MASK 0x00000020 3922 #define BGS_INVALID_PROF_SHIFT 5 3923 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3924 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3925 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3926 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3927 #define BGS_REFTAG_ERR_MASK 0x00000004 3928 #define BGS_REFTAG_ERR_SHIFT 2 3929 #define BGS_APPTAG_ERR_MASK 0x00000002 3930 #define BGS_APPTAG_ERR_SHIFT 1 3931 #define BGS_GUARD_ERR_MASK 0x00000001 3932 #define BGS_GUARD_ERR_SHIFT 0 3933 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3934 }; 3935 3936 static inline uint32_t 3937 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3938 { 3939 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 3940 BGS_BIDIR_BG_PROF_SHIFT; 3941 } 3942 3943 static inline uint32_t 3944 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3945 { 3946 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3947 BGS_BIDIR_ERR_COND_SHIFT; 3948 } 3949 3950 static inline uint32_t 3951 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3952 { 3953 return (bgstat & BGS_BG_PROFILE_MASK) >> 3954 BGS_BG_PROFILE_SHIFT; 3955 } 3956 3957 static inline uint32_t 3958 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3959 { 3960 return (bgstat & BGS_INVALID_PROF_MASK) >> 3961 BGS_INVALID_PROF_SHIFT; 3962 } 3963 3964 static inline uint32_t 3965 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3966 { 3967 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 3968 BGS_UNINIT_DIF_BLOCK_SHIFT; 3969 } 3970 3971 static inline uint32_t 3972 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3973 { 3974 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3975 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3976 } 3977 3978 static inline uint32_t 3979 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3980 { 3981 return (bgstat & BGS_REFTAG_ERR_MASK) >> 3982 BGS_REFTAG_ERR_SHIFT; 3983 } 3984 3985 static inline uint32_t 3986 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3987 { 3988 return (bgstat & BGS_APPTAG_ERR_MASK) >> 3989 BGS_APPTAG_ERR_SHIFT; 3990 } 3991 3992 static inline uint32_t 3993 lpfc_bgs_get_guard_err(uint32_t bgstat) 3994 { 3995 return (bgstat & BGS_GUARD_ERR_MASK) >> 3996 BGS_GUARD_ERR_SHIFT; 3997 } 3998 3999 #define LPFC_EXT_DATA_BDE_COUNT 3 4000 struct fcp_irw_ext { 4001 uint32_t io_tag64_low; 4002 uint32_t io_tag64_high; 4003 #ifdef __BIG_ENDIAN_BITFIELD 4004 uint8_t reserved1; 4005 uint8_t reserved2; 4006 uint8_t reserved3; 4007 uint8_t ebde_count; 4008 #else /* __LITTLE_ENDIAN */ 4009 uint8_t ebde_count; 4010 uint8_t reserved3; 4011 uint8_t reserved2; 4012 uint8_t reserved1; 4013 #endif 4014 uint32_t reserved4; 4015 struct ulp_bde64 rbde; /* response bde */ 4016 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4017 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4018 }; 4019 4020 typedef struct _IOCB { /* IOCB structure */ 4021 union { 4022 GENERIC_RSP grsp; /* Generic response */ 4023 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4024 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4025 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4026 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4027 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4028 GET_RPI getrpi; /* GET_RPI template */ 4029 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4030 FCPT_FIELDS fcpt; /* FCP target template */ 4031 4032 /* SLI-2 structures */ 4033 4034 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4035 * bde_64s */ 4036 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4037 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4038 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4039 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4040 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4041 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4042 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4043 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4044 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4045 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4046 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4047 } un; 4048 union { 4049 struct { 4050 #ifdef __BIG_ENDIAN_BITFIELD 4051 uint16_t ulpContext; /* High order bits word 6 */ 4052 uint16_t ulpIoTag; /* Low order bits word 6 */ 4053 #else /* __LITTLE_ENDIAN_BITFIELD */ 4054 uint16_t ulpIoTag; /* Low order bits word 6 */ 4055 uint16_t ulpContext; /* High order bits word 6 */ 4056 #endif 4057 } t1; 4058 struct { 4059 #ifdef __BIG_ENDIAN_BITFIELD 4060 uint16_t ulpContext; /* High order bits word 6 */ 4061 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4062 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4063 #else /* __LITTLE_ENDIAN_BITFIELD */ 4064 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4065 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4066 uint16_t ulpContext; /* High order bits word 6 */ 4067 #endif 4068 } t2; 4069 } un1; 4070 #define ulpContext un1.t1.ulpContext 4071 #define ulpIoTag un1.t1.ulpIoTag 4072 #define ulpIoTag0 un1.t2.ulpIoTag0 4073 4074 #ifdef __BIG_ENDIAN_BITFIELD 4075 uint32_t ulpTimeout:8; 4076 uint32_t ulpXS:1; 4077 uint32_t ulpFCP2Rcvy:1; 4078 uint32_t ulpPU:2; 4079 uint32_t ulpIr:1; 4080 uint32_t ulpClass:3; 4081 uint32_t ulpCommand:8; 4082 uint32_t ulpStatus:4; 4083 uint32_t ulpBdeCount:2; 4084 uint32_t ulpLe:1; 4085 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4086 #else /* __LITTLE_ENDIAN_BITFIELD */ 4087 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4088 uint32_t ulpLe:1; 4089 uint32_t ulpBdeCount:2; 4090 uint32_t ulpStatus:4; 4091 uint32_t ulpCommand:8; 4092 uint32_t ulpClass:3; 4093 uint32_t ulpIr:1; 4094 uint32_t ulpPU:2; 4095 uint32_t ulpFCP2Rcvy:1; 4096 uint32_t ulpXS:1; 4097 uint32_t ulpTimeout:8; 4098 #endif 4099 4100 union { 4101 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4102 4103 /* words 8-31 used for que_xri_cx iocb */ 4104 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4105 struct fcp_irw_ext fcp_ext; 4106 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4107 4108 /* words 8-15 for BlockGuard */ 4109 struct sli3_bg_fields sli3_bg; 4110 } unsli3; 4111 4112 #define ulpCt_h ulpXS 4113 #define ulpCt_l ulpFCP2Rcvy 4114 4115 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4116 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4117 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4118 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4119 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4120 #define PARM_NPIV_DID 3 4121 #define CLASS1 0 /* Class 1 */ 4122 #define CLASS2 1 /* Class 2 */ 4123 #define CLASS3 2 /* Class 3 */ 4124 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4125 4126 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4127 #define IOSTAT_FCP_RSP_ERROR 0x1 4128 #define IOSTAT_REMOTE_STOP 0x2 4129 #define IOSTAT_LOCAL_REJECT 0x3 4130 #define IOSTAT_NPORT_RJT 0x4 4131 #define IOSTAT_FABRIC_RJT 0x5 4132 #define IOSTAT_NPORT_BSY 0x6 4133 #define IOSTAT_FABRIC_BSY 0x7 4134 #define IOSTAT_INTERMED_RSP 0x8 4135 #define IOSTAT_LS_RJT 0x9 4136 #define IOSTAT_BA_RJT 0xA 4137 #define IOSTAT_RSVD1 0xB 4138 #define IOSTAT_RSVD2 0xC 4139 #define IOSTAT_RSVD3 0xD 4140 #define IOSTAT_RSVD4 0xE 4141 #define IOSTAT_NEED_BUFFER 0xF 4142 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4143 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4144 #define IOSTAT_CNT 0x11 4145 4146 } IOCB_t; 4147 4148 4149 #define SLI1_SLIM_SIZE (4 * 1024) 4150 4151 /* Up to 498 IOCBs will fit into 16k 4152 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4153 */ 4154 #define SLI2_SLIM_SIZE (64 * 1024) 4155 4156 /* Maximum IOCBs that will fit in SLI2 slim */ 4157 #define MAX_SLI2_IOCB 498 4158 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4159 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4160 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4161 4162 /* HBQ entries are 4 words each = 4k */ 4163 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4164 lpfc_sli_hbq_count()) 4165 4166 struct lpfc_sli2_slim { 4167 MAILBOX_t mbx; 4168 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4169 PCB_t pcb; 4170 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4171 }; 4172 4173 /* 4174 * This function checks PCI device to allow special handling for LC HBAs. 4175 * 4176 * Parameters: 4177 * device : struct pci_dev 's device field 4178 * 4179 * return 1 => TRUE 4180 * 0 => FALSE 4181 */ 4182 static inline int 4183 lpfc_is_LC_HBA(unsigned short device) 4184 { 4185 if ((device == PCI_DEVICE_ID_TFLY) || 4186 (device == PCI_DEVICE_ID_PFLY) || 4187 (device == PCI_DEVICE_ID_LP101) || 4188 (device == PCI_DEVICE_ID_BMID) || 4189 (device == PCI_DEVICE_ID_BSMB) || 4190 (device == PCI_DEVICE_ID_ZMID) || 4191 (device == PCI_DEVICE_ID_ZSMB) || 4192 (device == PCI_DEVICE_ID_SAT_MID) || 4193 (device == PCI_DEVICE_ID_SAT_SMB) || 4194 (device == PCI_DEVICE_ID_RFLY)) 4195 return 1; 4196 else 4197 return 0; 4198 } 4199 4200 /* 4201 * Determine if an IOCB failed because of a link event or firmware reset. 4202 */ 4203 4204 static inline int 4205 lpfc_error_lost_link(IOCB_t *iocbp) 4206 { 4207 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 4208 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 4209 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 4210 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 4211 } 4212 4213 #define MENLO_TRANSPORT_TYPE 0xfe 4214 #define MENLO_CONTEXT 0 4215 #define MENLO_PU 3 4216 #define MENLO_TIMEOUT 30 4217 #define SETVAR_MLOMNT 0x103107 4218 #define SETVAR_MLORST 0x103007 4219 4220 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4221