1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2005 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_IP_RING 1 /* ring 1 for IP commands */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 IP command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 IP response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 /* Common Transport structures and definitions */ 63 64 union CtRevisionId { 65 /* Structure is in Big Endian format */ 66 struct { 67 uint32_t Revision:8; 68 uint32_t InId:24; 69 } bits; 70 uint32_t word; 71 }; 72 73 union CtCommandResponse { 74 /* Structure is in Big Endian format */ 75 struct { 76 uint32_t CmdRsp:16; 77 uint32_t Size:16; 78 } bits; 79 uint32_t word; 80 }; 81 82 struct lpfc_sli_ct_request { 83 /* Structure is in Big Endian format */ 84 union CtRevisionId RevisionId; 85 uint8_t FsType; 86 uint8_t FsSubType; 87 uint8_t Options; 88 uint8_t Rsrvd1; 89 union CtCommandResponse CommandResponse; 90 uint8_t Rsrvd2; 91 uint8_t ReasonCode; 92 uint8_t Explanation; 93 uint8_t VendorUnique; 94 95 union { 96 uint32_t PortID; 97 struct gid { 98 uint8_t PortType; /* for GID_PT requests */ 99 uint8_t DomainScope; 100 uint8_t AreaScope; 101 uint8_t Fc4Type; /* for GID_FT requests */ 102 } gid; 103 struct rft { 104 uint32_t PortId; /* For RFT_ID requests */ 105 106 #ifdef __BIG_ENDIAN_BITFIELD 107 uint32_t rsvd0:16; 108 uint32_t rsvd1:7; 109 uint32_t fcpReg:1; /* Type 8 */ 110 uint32_t rsvd2:2; 111 uint32_t ipReg:1; /* Type 5 */ 112 uint32_t rsvd3:5; 113 #else /* __LITTLE_ENDIAN_BITFIELD */ 114 uint32_t rsvd0:16; 115 uint32_t fcpReg:1; /* Type 8 */ 116 uint32_t rsvd1:7; 117 uint32_t rsvd3:5; 118 uint32_t ipReg:1; /* Type 5 */ 119 uint32_t rsvd2:2; 120 #endif 121 122 uint32_t rsvd[7]; 123 } rft; 124 struct rnn { 125 uint32_t PortId; /* For RNN_ID requests */ 126 uint8_t wwnn[8]; 127 } rnn; 128 struct rsnn { /* For RSNN_ID requests */ 129 uint8_t wwnn[8]; 130 uint8_t len; 131 uint8_t symbname[255]; 132 } rsnn; 133 } un; 134 }; 135 136 #define SLI_CT_REVISION 1 137 #define GID_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 260) 138 #define RFT_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 228) 139 #define RNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request) - 252) 140 #define RSNN_REQUEST_SZ (sizeof(struct lpfc_sli_ct_request)) 141 142 /* 143 * FsType Definitions 144 */ 145 146 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 147 #define SLI_CT_TIME_SERVICE 0xFB 148 #define SLI_CT_DIRECTORY_SERVICE 0xFC 149 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 150 151 /* 152 * Directory Service Subtypes 153 */ 154 155 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 156 157 /* 158 * Response Codes 159 */ 160 161 #define SLI_CT_RESPONSE_FS_RJT 0x8001 162 #define SLI_CT_RESPONSE_FS_ACC 0x8002 163 164 /* 165 * Reason Codes 166 */ 167 168 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 169 #define SLI_CT_INVALID_COMMAND 0x01 170 #define SLI_CT_INVALID_VERSION 0x02 171 #define SLI_CT_LOGICAL_ERROR 0x03 172 #define SLI_CT_INVALID_IU_SIZE 0x04 173 #define SLI_CT_LOGICAL_BUSY 0x05 174 #define SLI_CT_PROTOCOL_ERROR 0x07 175 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 176 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 177 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 178 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 179 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 180 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 181 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 182 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 183 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 184 #define SLI_CT_VENDOR_UNIQUE 0xff 185 186 /* 187 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 188 */ 189 190 #define SLI_CT_NO_PORT_ID 0x01 191 #define SLI_CT_NO_PORT_NAME 0x02 192 #define SLI_CT_NO_NODE_NAME 0x03 193 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 194 #define SLI_CT_NO_IP_ADDRESS 0x05 195 #define SLI_CT_NO_IPA 0x06 196 #define SLI_CT_NO_FC4_TYPES 0x07 197 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 198 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 199 #define SLI_CT_NO_PORT_TYPE 0x0A 200 #define SLI_CT_ACCESS_DENIED 0x10 201 #define SLI_CT_INVALID_PORT_ID 0x11 202 #define SLI_CT_DATABASE_EMPTY 0x12 203 204 /* 205 * Name Server Command Codes 206 */ 207 208 #define SLI_CTNS_GA_NXT 0x0100 209 #define SLI_CTNS_GPN_ID 0x0112 210 #define SLI_CTNS_GNN_ID 0x0113 211 #define SLI_CTNS_GCS_ID 0x0114 212 #define SLI_CTNS_GFT_ID 0x0117 213 #define SLI_CTNS_GSPN_ID 0x0118 214 #define SLI_CTNS_GPT_ID 0x011A 215 #define SLI_CTNS_GID_PN 0x0121 216 #define SLI_CTNS_GID_NN 0x0131 217 #define SLI_CTNS_GIP_NN 0x0135 218 #define SLI_CTNS_GIPA_NN 0x0136 219 #define SLI_CTNS_GSNN_NN 0x0139 220 #define SLI_CTNS_GNN_IP 0x0153 221 #define SLI_CTNS_GIPA_IP 0x0156 222 #define SLI_CTNS_GID_FT 0x0171 223 #define SLI_CTNS_GID_PT 0x01A1 224 #define SLI_CTNS_RPN_ID 0x0212 225 #define SLI_CTNS_RNN_ID 0x0213 226 #define SLI_CTNS_RCS_ID 0x0214 227 #define SLI_CTNS_RFT_ID 0x0217 228 #define SLI_CTNS_RSPN_ID 0x0218 229 #define SLI_CTNS_RPT_ID 0x021A 230 #define SLI_CTNS_RIP_NN 0x0235 231 #define SLI_CTNS_RIPA_NN 0x0236 232 #define SLI_CTNS_RSNN_NN 0x0239 233 #define SLI_CTNS_DA_ID 0x0300 234 235 /* 236 * Port Types 237 */ 238 239 #define SLI_CTPT_N_PORT 0x01 240 #define SLI_CTPT_NL_PORT 0x02 241 #define SLI_CTPT_FNL_PORT 0x03 242 #define SLI_CTPT_IP 0x04 243 #define SLI_CTPT_FCP 0x08 244 #define SLI_CTPT_NX_PORT 0x7F 245 #define SLI_CTPT_F_PORT 0x81 246 #define SLI_CTPT_FL_PORT 0x82 247 #define SLI_CTPT_E_PORT 0x84 248 249 #define SLI_CT_LAST_ENTRY 0x80000000 250 251 /* Fibre Channel Service Parameter definitions */ 252 253 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 254 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 255 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 256 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 257 258 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 259 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 260 #define FC_PH3 0x20 /* FC-PH-3 version */ 261 262 #define FF_FRAME_SIZE 2048 263 264 struct lpfc_name { 265 union { 266 struct { 267 #ifdef __BIG_ENDIAN_BITFIELD 268 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 269 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 270 8:11 of IEEE ext */ 271 #else /* __LITTLE_ENDIAN_BITFIELD */ 272 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 273 8:11 of IEEE ext */ 274 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 275 #endif 276 277 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 278 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 279 #define NAME_FC_TYPE 0x3 /* FC native name type */ 280 #define NAME_IP_TYPE 0x4 /* IP address */ 281 #define NAME_CCITT_TYPE 0xC 282 #define NAME_CCITT_GR_TYPE 0xE 283 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 284 extended Lsb */ 285 uint8_t IEEE[6]; /* FC IEEE address */ 286 } s; 287 uint8_t wwn[8]; 288 } u; 289 }; 290 291 struct csp { 292 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 293 uint8_t fcphLow; 294 uint8_t bbCreditMsb; 295 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 296 297 #ifdef __BIG_ENDIAN_BITFIELD 298 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 299 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 300 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 301 uint16_t fPort:1; /* FC Word 1, bit 28 */ 302 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 303 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 304 uint16_t multicast:1; /* FC Word 1, bit 25 */ 305 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 306 307 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 308 uint16_t simplex:1; /* FC Word 1, bit 22 */ 309 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 310 uint16_t dhd:1; /* FC Word 1, bit 18 */ 311 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 312 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 313 #else /* __LITTLE_ENDIAN_BITFIELD */ 314 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 315 uint16_t multicast:1; /* FC Word 1, bit 25 */ 316 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 317 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 318 uint16_t fPort:1; /* FC Word 1, bit 28 */ 319 uint16_t word1Reserved2:1; /* FC Word 1, bit 29 */ 320 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 321 uint16_t increasingOffset:1; /* FC Word 1, bit 31 */ 322 323 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 324 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 325 uint16_t dhd:1; /* FC Word 1, bit 18 */ 326 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 327 uint16_t simplex:1; /* FC Word 1, bit 22 */ 328 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 329 #endif 330 331 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 332 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 333 union { 334 struct { 335 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 336 337 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 338 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 339 340 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 341 } nPort; 342 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 343 } w2; 344 345 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 346 }; 347 348 struct class_parms { 349 #ifdef __BIG_ENDIAN_BITFIELD 350 uint8_t classValid:1; /* FC Word 0, bit 31 */ 351 uint8_t intermix:1; /* FC Word 0, bit 30 */ 352 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 353 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 354 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 355 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 356 #else /* __LITTLE_ENDIAN_BITFIELD */ 357 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 358 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 359 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 360 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 361 uint8_t intermix:1; /* FC Word 0, bit 30 */ 362 uint8_t classValid:1; /* FC Word 0, bit 31 */ 363 364 #endif 365 366 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 367 368 #ifdef __BIG_ENDIAN_BITFIELD 369 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 370 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 371 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 372 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 373 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 374 #else /* __LITTLE_ENDIAN_BITFIELD */ 375 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 376 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 377 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 378 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 379 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 380 #endif 381 382 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 383 384 #ifdef __BIG_ENDIAN_BITFIELD 385 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 386 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 387 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 388 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 389 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 390 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 391 #else /* __LITTLE_ENDIAN_BITFIELD */ 392 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 393 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 394 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 395 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 396 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 397 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 398 #endif 399 400 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 401 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 402 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 403 404 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 405 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 406 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 407 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 408 409 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 410 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 411 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 412 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 413 }; 414 415 struct serv_parm { /* Structure is in Big Endian format */ 416 struct csp cmn; 417 struct lpfc_name portName; 418 struct lpfc_name nodeName; 419 struct class_parms cls1; 420 struct class_parms cls2; 421 struct class_parms cls3; 422 struct class_parms cls4; 423 uint8_t vendorVersion[16]; 424 }; 425 426 /* 427 * Extended Link Service LS_COMMAND codes (Payload Word 0) 428 */ 429 #ifdef __BIG_ENDIAN_BITFIELD 430 #define ELS_CMD_MASK 0xffff0000 431 #define ELS_RSP_MASK 0xff000000 432 #define ELS_CMD_LS_RJT 0x01000000 433 #define ELS_CMD_ACC 0x02000000 434 #define ELS_CMD_PLOGI 0x03000000 435 #define ELS_CMD_FLOGI 0x04000000 436 #define ELS_CMD_LOGO 0x05000000 437 #define ELS_CMD_ABTX 0x06000000 438 #define ELS_CMD_RCS 0x07000000 439 #define ELS_CMD_RES 0x08000000 440 #define ELS_CMD_RSS 0x09000000 441 #define ELS_CMD_RSI 0x0A000000 442 #define ELS_CMD_ESTS 0x0B000000 443 #define ELS_CMD_ESTC 0x0C000000 444 #define ELS_CMD_ADVC 0x0D000000 445 #define ELS_CMD_RTV 0x0E000000 446 #define ELS_CMD_RLS 0x0F000000 447 #define ELS_CMD_ECHO 0x10000000 448 #define ELS_CMD_TEST 0x11000000 449 #define ELS_CMD_RRQ 0x12000000 450 #define ELS_CMD_PRLI 0x20100014 451 #define ELS_CMD_PRLO 0x21100014 452 #define ELS_CMD_PDISC 0x50000000 453 #define ELS_CMD_FDISC 0x51000000 454 #define ELS_CMD_ADISC 0x52000000 455 #define ELS_CMD_FARP 0x54000000 456 #define ELS_CMD_FARPR 0x55000000 457 #define ELS_CMD_FAN 0x60000000 458 #define ELS_CMD_RSCN 0x61040000 459 #define ELS_CMD_SCR 0x62000000 460 #define ELS_CMD_RNID 0x78000000 461 #else /* __LITTLE_ENDIAN_BITFIELD */ 462 #define ELS_CMD_MASK 0xffff 463 #define ELS_RSP_MASK 0xff 464 #define ELS_CMD_LS_RJT 0x01 465 #define ELS_CMD_ACC 0x02 466 #define ELS_CMD_PLOGI 0x03 467 #define ELS_CMD_FLOGI 0x04 468 #define ELS_CMD_LOGO 0x05 469 #define ELS_CMD_ABTX 0x06 470 #define ELS_CMD_RCS 0x07 471 #define ELS_CMD_RES 0x08 472 #define ELS_CMD_RSS 0x09 473 #define ELS_CMD_RSI 0x0A 474 #define ELS_CMD_ESTS 0x0B 475 #define ELS_CMD_ESTC 0x0C 476 #define ELS_CMD_ADVC 0x0D 477 #define ELS_CMD_RTV 0x0E 478 #define ELS_CMD_RLS 0x0F 479 #define ELS_CMD_ECHO 0x10 480 #define ELS_CMD_TEST 0x11 481 #define ELS_CMD_RRQ 0x12 482 #define ELS_CMD_PRLI 0x14001020 483 #define ELS_CMD_PRLO 0x14001021 484 #define ELS_CMD_PDISC 0x50 485 #define ELS_CMD_FDISC 0x51 486 #define ELS_CMD_ADISC 0x52 487 #define ELS_CMD_FARP 0x54 488 #define ELS_CMD_FARPR 0x55 489 #define ELS_CMD_FAN 0x60 490 #define ELS_CMD_RSCN 0x0461 491 #define ELS_CMD_SCR 0x62 492 #define ELS_CMD_RNID 0x78 493 #endif 494 495 /* 496 * LS_RJT Payload Definition 497 */ 498 499 struct ls_rjt { /* Structure is in Big Endian format */ 500 union { 501 uint32_t lsRjtError; 502 struct { 503 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 504 505 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 506 /* LS_RJT reason codes */ 507 #define LSRJT_INVALID_CMD 0x01 508 #define LSRJT_LOGICAL_ERR 0x03 509 #define LSRJT_LOGICAL_BSY 0x05 510 #define LSRJT_PROTOCOL_ERR 0x07 511 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 512 #define LSRJT_CMD_UNSUPPORTED 0x0B 513 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 514 515 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 516 /* LS_RJT reason explanation */ 517 #define LSEXP_NOTHING_MORE 0x00 518 #define LSEXP_SPARM_OPTIONS 0x01 519 #define LSEXP_SPARM_ICTL 0x03 520 #define LSEXP_SPARM_RCTL 0x05 521 #define LSEXP_SPARM_RCV_SIZE 0x07 522 #define LSEXP_SPARM_CONCUR_SEQ 0x09 523 #define LSEXP_SPARM_CREDIT 0x0B 524 #define LSEXP_INVALID_PNAME 0x0D 525 #define LSEXP_INVALID_NNAME 0x0E 526 #define LSEXP_INVALID_CSP 0x0F 527 #define LSEXP_INVALID_ASSOC_HDR 0x11 528 #define LSEXP_ASSOC_HDR_REQ 0x13 529 #define LSEXP_INVALID_O_SID 0x15 530 #define LSEXP_INVALID_OX_RX 0x17 531 #define LSEXP_CMD_IN_PROGRESS 0x19 532 #define LSEXP_INVALID_NPORT_ID 0x1F 533 #define LSEXP_INVALID_SEQ_ID 0x21 534 #define LSEXP_INVALID_XCHG 0x23 535 #define LSEXP_INACTIVE_XCHG 0x25 536 #define LSEXP_RQ_REQUIRED 0x27 537 #define LSEXP_OUT_OF_RESOURCE 0x29 538 #define LSEXP_CANT_GIVE_DATA 0x2A 539 #define LSEXP_REQ_UNSUPPORTED 0x2C 540 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 541 } b; 542 } un; 543 }; 544 545 /* 546 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 547 */ 548 549 typedef struct _LOGO { /* Structure is in Big Endian format */ 550 union { 551 uint32_t nPortId32; /* Access nPortId as a word */ 552 struct { 553 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 554 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 555 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 556 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 557 } b; 558 } un; 559 struct lpfc_name portName; /* N_port name field */ 560 } LOGO; 561 562 /* 563 * FCP Login (PRLI Request / ACC) Payload Definition 564 */ 565 566 #define PRLX_PAGE_LEN 0x10 567 #define TPRLO_PAGE_LEN 0x14 568 569 typedef struct _PRLI { /* Structure is in Big Endian format */ 570 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 571 572 #define PRLI_FCP_TYPE 0x08 573 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 574 575 #ifdef __BIG_ENDIAN_BITFIELD 576 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 577 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 578 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 579 580 /* ACC = imagePairEstablished */ 581 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 582 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 583 #else /* __LITTLE_ENDIAN_BITFIELD */ 584 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 585 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 586 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 587 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 588 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 589 /* ACC = imagePairEstablished */ 590 #endif 591 592 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 593 #define PRLI_NO_RESOURCES 0x2 594 #define PRLI_INIT_INCOMPLETE 0x3 595 #define PRLI_NO_SUCH_PA 0x4 596 #define PRLI_PREDEF_CONFIG 0x5 597 #define PRLI_PARTIAL_SUCCESS 0x6 598 #define PRLI_INVALID_PAGE_CNT 0x7 599 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 600 601 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 602 603 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 604 605 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 606 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 607 608 #ifdef __BIG_ENDIAN_BITFIELD 609 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 610 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 611 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 612 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 613 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 614 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 615 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 616 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 617 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 618 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 619 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 620 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 621 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 622 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 623 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 624 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 625 #else /* __LITTLE_ENDIAN_BITFIELD */ 626 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 627 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 628 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 629 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 630 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 631 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 632 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 633 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 634 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 635 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 636 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 637 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 638 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 639 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 640 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 641 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 642 #endif 643 } PRLI; 644 645 /* 646 * FCP Logout (PRLO Request / ACC) Payload Definition 647 */ 648 649 typedef struct _PRLO { /* Structure is in Big Endian format */ 650 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 651 652 #define PRLO_FCP_TYPE 0x08 653 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 654 655 #ifdef __BIG_ENDIAN_BITFIELD 656 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 657 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 658 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 659 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 660 #else /* __LITTLE_ENDIAN_BITFIELD */ 661 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 662 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 663 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 664 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 665 #endif 666 667 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 668 #define PRLO_NO_SUCH_IMAGE 0x4 669 #define PRLO_INVALID_PAGE_CNT 0x7 670 671 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 672 673 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 674 675 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 676 677 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 678 } PRLO; 679 680 typedef struct _ADISC { /* Structure is in Big Endian format */ 681 uint32_t hardAL_PA; 682 struct lpfc_name portName; 683 struct lpfc_name nodeName; 684 uint32_t DID; 685 } ADISC; 686 687 typedef struct _FARP { /* Structure is in Big Endian format */ 688 uint32_t Mflags:8; 689 uint32_t Odid:24; 690 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 691 action */ 692 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 693 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 694 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 695 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 696 supported */ 697 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 698 supported */ 699 uint32_t Rflags:8; 700 uint32_t Rdid:24; 701 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 702 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 703 struct lpfc_name OportName; 704 struct lpfc_name OnodeName; 705 struct lpfc_name RportName; 706 struct lpfc_name RnodeName; 707 uint8_t Oipaddr[16]; 708 uint8_t Ripaddr[16]; 709 } FARP; 710 711 typedef struct _FAN { /* Structure is in Big Endian format */ 712 uint32_t Fdid; 713 struct lpfc_name FportName; 714 struct lpfc_name FnodeName; 715 } FAN; 716 717 typedef struct _SCR { /* Structure is in Big Endian format */ 718 uint8_t resvd1; 719 uint8_t resvd2; 720 uint8_t resvd3; 721 uint8_t Function; 722 #define SCR_FUNC_FABRIC 0x01 723 #define SCR_FUNC_NPORT 0x02 724 #define SCR_FUNC_FULL 0x03 725 #define SCR_CLEAR 0xff 726 } SCR; 727 728 typedef struct _RNID_TOP_DISC { 729 struct lpfc_name portName; 730 uint8_t resvd[8]; 731 uint32_t unitType; 732 #define RNID_HBA 0x7 733 #define RNID_HOST 0xa 734 #define RNID_DRIVER 0xd 735 uint32_t physPort; 736 uint32_t attachedNodes; 737 uint16_t ipVersion; 738 #define RNID_IPV4 0x1 739 #define RNID_IPV6 0x2 740 uint16_t UDPport; 741 uint8_t ipAddr[16]; 742 uint16_t resvd1; 743 uint16_t flags; 744 #define RNID_TD_SUPPORT 0x1 745 #define RNID_LP_VALID 0x2 746 } RNID_TOP_DISC; 747 748 typedef struct _RNID { /* Structure is in Big Endian format */ 749 uint8_t Format; 750 #define RNID_TOPOLOGY_DISC 0xdf 751 uint8_t CommonLen; 752 uint8_t resvd1; 753 uint8_t SpecificLen; 754 struct lpfc_name portName; 755 struct lpfc_name nodeName; 756 union { 757 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 758 } un; 759 } RNID; 760 761 typedef struct _RRQ { /* Structure is in Big Endian format */ 762 uint32_t SID; 763 uint16_t Oxid; 764 uint16_t Rxid; 765 uint8_t resv[32]; /* optional association hdr */ 766 } RRQ; 767 768 /* This is used for RSCN command */ 769 typedef struct _D_ID { /* Structure is in Big Endian format */ 770 union { 771 uint32_t word; 772 struct { 773 #ifdef __BIG_ENDIAN_BITFIELD 774 uint8_t resv; 775 uint8_t domain; 776 uint8_t area; 777 uint8_t id; 778 #else /* __LITTLE_ENDIAN_BITFIELD */ 779 uint8_t id; 780 uint8_t area; 781 uint8_t domain; 782 uint8_t resv; 783 #endif 784 } b; 785 } un; 786 } D_ID; 787 788 /* 789 * Structure to define all ELS Payload types 790 */ 791 792 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 793 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 794 uint8_t elsByte1; 795 uint8_t elsByte2; 796 uint8_t elsByte3; 797 union { 798 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 799 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 800 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 801 PRLI prli; /* Payload for PRLI/ACC */ 802 PRLO prlo; /* Payload for PRLO/ACC */ 803 ADISC adisc; /* Payload for ADISC/ACC */ 804 FARP farp; /* Payload for FARP/ACC */ 805 FAN fan; /* Payload for FAN */ 806 SCR scr; /* Payload for SCR/ACC */ 807 RRQ rrq; /* Payload for RRQ */ 808 RNID rnid; /* Payload for RNID */ 809 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 810 } un; 811 } ELS_PKT; 812 813 /* 814 * FDMI 815 * HBA MAnagement Operations Command Codes 816 */ 817 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 818 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 819 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 820 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 821 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 822 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 823 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 824 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 825 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 826 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 827 828 /* 829 * Management Service Subtypes 830 */ 831 #define SLI_CT_FDMI_Subtypes 0x10 832 833 /* 834 * HBA Management Service Reject Code 835 */ 836 #define REJECT_CODE 0x9 /* Unable to perform command request */ 837 838 /* 839 * HBA Management Service Reject Reason Code 840 * Please refer to the Reason Codes above 841 */ 842 843 /* 844 * HBA Attribute Types 845 */ 846 #define NODE_NAME 0x1 847 #define MANUFACTURER 0x2 848 #define SERIAL_NUMBER 0x3 849 #define MODEL 0x4 850 #define MODEL_DESCRIPTION 0x5 851 #define HARDWARE_VERSION 0x6 852 #define DRIVER_VERSION 0x7 853 #define OPTION_ROM_VERSION 0x8 854 #define FIRMWARE_VERSION 0x9 855 #define OS_NAME_VERSION 0xa 856 #define MAX_CT_PAYLOAD_LEN 0xb 857 858 /* 859 * Port Attrubute Types 860 */ 861 #define SUPPORTED_FC4_TYPES 0x1 862 #define SUPPORTED_SPEED 0x2 863 #define PORT_SPEED 0x3 864 #define MAX_FRAME_SIZE 0x4 865 #define OS_DEVICE_NAME 0x5 866 #define HOST_NAME 0x6 867 868 union AttributesDef { 869 /* Structure is in Big Endian format */ 870 struct { 871 uint32_t AttrType:16; 872 uint32_t AttrLen:16; 873 } bits; 874 uint32_t word; 875 }; 876 877 878 /* 879 * HBA Attribute Entry (8 - 260 bytes) 880 */ 881 typedef struct { 882 union AttributesDef ad; 883 union { 884 uint32_t VendorSpecific; 885 uint8_t Manufacturer[64]; 886 uint8_t SerialNumber[64]; 887 uint8_t Model[256]; 888 uint8_t ModelDescription[256]; 889 uint8_t HardwareVersion[256]; 890 uint8_t DriverVersion[256]; 891 uint8_t OptionROMVersion[256]; 892 uint8_t FirmwareVersion[256]; 893 struct lpfc_name NodeName; 894 uint8_t SupportFC4Types[32]; 895 uint32_t SupportSpeed; 896 uint32_t PortSpeed; 897 uint32_t MaxFrameSize; 898 uint8_t OsDeviceName[256]; 899 uint8_t OsNameVersion[256]; 900 uint32_t MaxCTPayloadLen; 901 uint8_t HostName[256]; 902 } un; 903 } ATTRIBUTE_ENTRY; 904 905 /* 906 * HBA Attribute Block 907 */ 908 typedef struct { 909 uint32_t EntryCnt; /* Number of HBA attribute entries */ 910 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 911 } ATTRIBUTE_BLOCK; 912 913 /* 914 * Port Entry 915 */ 916 typedef struct { 917 struct lpfc_name PortName; 918 } PORT_ENTRY; 919 920 /* 921 * HBA Identifier 922 */ 923 typedef struct { 924 struct lpfc_name PortName; 925 } HBA_IDENTIFIER; 926 927 /* 928 * Registered Port List Format 929 */ 930 typedef struct { 931 uint32_t EntryCnt; 932 PORT_ENTRY pe; /* Variable-length array */ 933 } REG_PORT_LIST; 934 935 /* 936 * Register HBA(RHBA) 937 */ 938 typedef struct { 939 HBA_IDENTIFIER hi; 940 REG_PORT_LIST rpl; /* variable-length array */ 941 /* ATTRIBUTE_BLOCK ab; */ 942 } REG_HBA; 943 944 /* 945 * Register HBA Attributes (RHAT) 946 */ 947 typedef struct { 948 struct lpfc_name HBA_PortName; 949 ATTRIBUTE_BLOCK ab; 950 } REG_HBA_ATTRIBUTE; 951 952 /* 953 * Register Port Attributes (RPA) 954 */ 955 typedef struct { 956 struct lpfc_name PortName; 957 ATTRIBUTE_BLOCK ab; 958 } REG_PORT_ATTRIBUTE; 959 960 /* 961 * Get Registered HBA List (GRHL) Accept Payload Format 962 */ 963 typedef struct { 964 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 965 struct lpfc_name HBA_PortName; /* Variable-length array */ 966 } GRHL_ACC_PAYLOAD; 967 968 /* 969 * Get Registered Port List (GRPL) Accept Payload Format 970 */ 971 typedef struct { 972 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 973 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 974 } GRPL_ACC_PAYLOAD; 975 976 /* 977 * Get Port Attributes (GPAT) Accept Payload Format 978 */ 979 980 typedef struct { 981 ATTRIBUTE_BLOCK pab; 982 } GPAT_ACC_PAYLOAD; 983 984 985 /* 986 * Begin HBA configuration parameters. 987 * The PCI configuration register BAR assignments are: 988 * BAR0, offset 0x10 - SLIM base memory address 989 * BAR1, offset 0x14 - SLIM base memory high address 990 * BAR2, offset 0x18 - REGISTER base memory address 991 * BAR3, offset 0x1c - REGISTER base memory high address 992 * BAR4, offset 0x20 - BIU I/O registers 993 * BAR5, offset 0x24 - REGISTER base io high address 994 */ 995 996 /* Number of rings currently used and available. */ 997 #define MAX_CONFIGURED_RINGS 3 998 #define MAX_RINGS 4 999 1000 /* IOCB / Mailbox is owned by FireFly */ 1001 #define OWN_CHIP 1 1002 1003 /* IOCB / Mailbox is owned by Host */ 1004 #define OWN_HOST 0 1005 1006 /* Number of 4-byte words in an IOCB. */ 1007 #define IOCB_WORD_SZ 8 1008 1009 /* defines for type field in fc header */ 1010 #define FC_ELS_DATA 0x1 1011 #define FC_LLC_SNAP 0x5 1012 #define FC_FCP_DATA 0x8 1013 #define FC_COMMON_TRANSPORT_ULP 0x20 1014 1015 /* defines for rctl field in fc header */ 1016 #define FC_DEV_DATA 0x0 1017 #define FC_UNSOL_CTL 0x2 1018 #define FC_SOL_CTL 0x3 1019 #define FC_UNSOL_DATA 0x4 1020 #define FC_FCP_CMND 0x6 1021 #define FC_ELS_REQ 0x22 1022 #define FC_ELS_RSP 0x23 1023 1024 /* network headers for Dfctl field */ 1025 #define FC_NET_HDR 0x20 1026 1027 /* Start FireFly Register definitions */ 1028 #define PCI_VENDOR_ID_EMULEX 0x10df 1029 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1030 #define PCI_DEVICE_ID_RFLY 0xf095 1031 #define PCI_DEVICE_ID_PFLY 0xf098 1032 #define PCI_DEVICE_ID_LP101 0xf0a1 1033 #define PCI_DEVICE_ID_TFLY 0xf0a5 1034 #define PCI_DEVICE_ID_BSMB 0xf0d1 1035 #define PCI_DEVICE_ID_BMID 0xf0d5 1036 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1037 #define PCI_DEVICE_ID_ZMID 0xf0e5 1038 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1039 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1040 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1041 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1042 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1043 #define PCI_DEVICE_ID_CENTAUR 0xf900 1044 #define PCI_DEVICE_ID_PEGASUS 0xf980 1045 #define PCI_DEVICE_ID_THOR 0xfa00 1046 #define PCI_DEVICE_ID_VIPER 0xfb00 1047 #define PCI_DEVICE_ID_LP10000S 0xfc00 1048 #define PCI_DEVICE_ID_LP11000S 0xfc10 1049 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1050 #define PCI_DEVICE_ID_HELIOS 0xfd00 1051 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1052 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1053 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1054 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1055 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1056 1057 #define PCI_SUBSYSTEM_ID_LP11000S 0xfc11 1058 #define PCI_SUBSYSTEM_ID_LP11002S 0xfc12 1059 #define PCI_SUBSYSTEM_ID_LPE11000S 0xfc21 1060 #define PCI_SUBSYSTEM_ID_LPE11002S 0xfc22 1061 #define PCI_SUBSYSTEM_ID_LPE11010S 0xfc2A 1062 1063 #define JEDEC_ID_ADDRESS 0x0080001c 1064 #define FIREFLY_JEDEC_ID 0x1ACC 1065 #define SUPERFLY_JEDEC_ID 0x0020 1066 #define DRAGONFLY_JEDEC_ID 0x0021 1067 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1068 #define CENTAUR_2G_JEDEC_ID 0x0026 1069 #define CENTAUR_1G_JEDEC_ID 0x0028 1070 #define PEGASUS_ORION_JEDEC_ID 0x0036 1071 #define PEGASUS_JEDEC_ID 0x0038 1072 #define THOR_JEDEC_ID 0x0012 1073 #define HELIOS_JEDEC_ID 0x0364 1074 #define ZEPHYR_JEDEC_ID 0x0577 1075 #define VIPER_JEDEC_ID 0x4838 1076 1077 #define JEDEC_ID_MASK 0x0FFFF000 1078 #define JEDEC_ID_SHIFT 12 1079 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1080 1081 typedef struct { /* FireFly BIU registers */ 1082 uint32_t hostAtt; /* See definitions for Host Attention 1083 register */ 1084 uint32_t chipAtt; /* See definitions for Chip Attention 1085 register */ 1086 uint32_t hostStatus; /* See definitions for Host Status register */ 1087 uint32_t hostControl; /* See definitions for Host Control register */ 1088 uint32_t buiConfig; /* See definitions for BIU configuration 1089 register */ 1090 } FF_REGS; 1091 1092 /* IO Register size in bytes */ 1093 #define FF_REG_AREA_SIZE 256 1094 1095 /* Host Attention Register */ 1096 1097 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1098 1099 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1100 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1101 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1102 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1103 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1104 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1105 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1106 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1107 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1108 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1109 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1110 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1111 #define HA_LATT 0x20000000 /* Bit 29 */ 1112 #define HA_MBATT 0x40000000 /* Bit 30 */ 1113 #define HA_ERATT 0x80000000 /* Bit 31 */ 1114 1115 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1116 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1117 #define HA_RXATT 0x00000008 /* Bit 3 */ 1118 #define HA_RXMASK 0x0000000f 1119 1120 /* Chip Attention Register */ 1121 1122 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1123 1124 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1125 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1126 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1127 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1128 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1129 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1130 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1131 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1132 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1133 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1134 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1135 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1136 #define CA_MBATT 0x40000000 /* Bit 30 */ 1137 1138 /* Host Status Register */ 1139 1140 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1141 1142 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1143 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1144 #define HS_FFER8 0x01000000 /* Bit 24 */ 1145 #define HS_FFER7 0x02000000 /* Bit 25 */ 1146 #define HS_FFER6 0x04000000 /* Bit 26 */ 1147 #define HS_FFER5 0x08000000 /* Bit 27 */ 1148 #define HS_FFER4 0x10000000 /* Bit 28 */ 1149 #define HS_FFER3 0x20000000 /* Bit 29 */ 1150 #define HS_FFER2 0x40000000 /* Bit 30 */ 1151 #define HS_FFER1 0x80000000 /* Bit 31 */ 1152 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */ 1153 1154 /* Host Control Register */ 1155 1156 #define HC_REG_OFFSET 12 /* Word offset from register base address */ 1157 1158 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1159 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1160 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1161 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1162 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1163 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1164 #define HC_INITMB 0x04000000 /* Bit 26 */ 1165 #define HC_INITFF 0x08000000 /* Bit 27 */ 1166 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1167 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1168 1169 /* Mailbox Commands */ 1170 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1171 #define MBX_LOAD_SM 0x01 1172 #define MBX_READ_NV 0x02 1173 #define MBX_WRITE_NV 0x03 1174 #define MBX_RUN_BIU_DIAG 0x04 1175 #define MBX_INIT_LINK 0x05 1176 #define MBX_DOWN_LINK 0x06 1177 #define MBX_CONFIG_LINK 0x07 1178 #define MBX_CONFIG_RING 0x09 1179 #define MBX_RESET_RING 0x0A 1180 #define MBX_READ_CONFIG 0x0B 1181 #define MBX_READ_RCONFIG 0x0C 1182 #define MBX_READ_SPARM 0x0D 1183 #define MBX_READ_STATUS 0x0E 1184 #define MBX_READ_RPI 0x0F 1185 #define MBX_READ_XRI 0x10 1186 #define MBX_READ_REV 0x11 1187 #define MBX_READ_LNK_STAT 0x12 1188 #define MBX_REG_LOGIN 0x13 1189 #define MBX_UNREG_LOGIN 0x14 1190 #define MBX_READ_LA 0x15 1191 #define MBX_CLEAR_LA 0x16 1192 #define MBX_DUMP_MEMORY 0x17 1193 #define MBX_DUMP_CONTEXT 0x18 1194 #define MBX_RUN_DIAGS 0x19 1195 #define MBX_RESTART 0x1A 1196 #define MBX_UPDATE_CFG 0x1B 1197 #define MBX_DOWN_LOAD 0x1C 1198 #define MBX_DEL_LD_ENTRY 0x1D 1199 #define MBX_RUN_PROGRAM 0x1E 1200 #define MBX_SET_MASK 0x20 1201 #define MBX_SET_SLIM 0x21 1202 #define MBX_UNREG_D_ID 0x23 1203 #define MBX_CONFIG_FARP 0x25 1204 1205 #define MBX_LOAD_AREA 0x81 1206 #define MBX_RUN_BIU_DIAG64 0x84 1207 #define MBX_CONFIG_PORT 0x88 1208 #define MBX_READ_SPARM64 0x8D 1209 #define MBX_READ_RPI64 0x8F 1210 #define MBX_REG_LOGIN64 0x93 1211 #define MBX_READ_LA64 0x95 1212 1213 #define MBX_FLASH_WR_ULA 0x98 1214 #define MBX_SET_DEBUG 0x99 1215 #define MBX_LOAD_EXP_ROM 0x9C 1216 1217 #define MBX_MAX_CMDS 0x9D 1218 #define MBX_SLI2_CMD_MASK 0x80 1219 1220 /* IOCB Commands */ 1221 1222 #define CMD_RCV_SEQUENCE_CX 0x01 1223 #define CMD_XMIT_SEQUENCE_CR 0x02 1224 #define CMD_XMIT_SEQUENCE_CX 0x03 1225 #define CMD_XMIT_BCAST_CN 0x04 1226 #define CMD_XMIT_BCAST_CX 0x05 1227 #define CMD_QUE_RING_BUF_CN 0x06 1228 #define CMD_QUE_XRI_BUF_CX 0x07 1229 #define CMD_IOCB_CONTINUE_CN 0x08 1230 #define CMD_RET_XRI_BUF_CX 0x09 1231 #define CMD_ELS_REQUEST_CR 0x0A 1232 #define CMD_ELS_REQUEST_CX 0x0B 1233 #define CMD_RCV_ELS_REQ_CX 0x0D 1234 #define CMD_ABORT_XRI_CN 0x0E 1235 #define CMD_ABORT_XRI_CX 0x0F 1236 #define CMD_CLOSE_XRI_CN 0x10 1237 #define CMD_CLOSE_XRI_CX 0x11 1238 #define CMD_CREATE_XRI_CR 0x12 1239 #define CMD_CREATE_XRI_CX 0x13 1240 #define CMD_GET_RPI_CN 0x14 1241 #define CMD_XMIT_ELS_RSP_CX 0x15 1242 #define CMD_GET_RPI_CR 0x16 1243 #define CMD_XRI_ABORTED_CX 0x17 1244 #define CMD_FCP_IWRITE_CR 0x18 1245 #define CMD_FCP_IWRITE_CX 0x19 1246 #define CMD_FCP_IREAD_CR 0x1A 1247 #define CMD_FCP_IREAD_CX 0x1B 1248 #define CMD_FCP_ICMND_CR 0x1C 1249 #define CMD_FCP_ICMND_CX 0x1D 1250 1251 #define CMD_ADAPTER_MSG 0x20 1252 #define CMD_ADAPTER_DUMP 0x22 1253 1254 /* SLI_2 IOCB Command Set */ 1255 1256 #define CMD_RCV_SEQUENCE64_CX 0x81 1257 #define CMD_XMIT_SEQUENCE64_CR 0x82 1258 #define CMD_XMIT_SEQUENCE64_CX 0x83 1259 #define CMD_XMIT_BCAST64_CN 0x84 1260 #define CMD_XMIT_BCAST64_CX 0x85 1261 #define CMD_QUE_RING_BUF64_CN 0x86 1262 #define CMD_QUE_XRI_BUF64_CX 0x87 1263 #define CMD_IOCB_CONTINUE64_CN 0x88 1264 #define CMD_RET_XRI_BUF64_CX 0x89 1265 #define CMD_ELS_REQUEST64_CR 0x8A 1266 #define CMD_ELS_REQUEST64_CX 0x8B 1267 #define CMD_ABORT_MXRI64_CN 0x8C 1268 #define CMD_RCV_ELS_REQ64_CX 0x8D 1269 #define CMD_XMIT_ELS_RSP64_CX 0x95 1270 #define CMD_FCP_IWRITE64_CR 0x98 1271 #define CMD_FCP_IWRITE64_CX 0x99 1272 #define CMD_FCP_IREAD64_CR 0x9A 1273 #define CMD_FCP_IREAD64_CX 0x9B 1274 #define CMD_FCP_ICMND64_CR 0x9C 1275 #define CMD_FCP_ICMND64_CX 0x9D 1276 1277 #define CMD_GEN_REQUEST64_CR 0xC2 1278 #define CMD_GEN_REQUEST64_CX 0xC3 1279 1280 #define CMD_MAX_IOCB_CMD 0xE6 1281 #define CMD_IOCB_MASK 0xff 1282 1283 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1284 iocb */ 1285 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1286 /* 1287 * Define Status 1288 */ 1289 #define MBX_SUCCESS 0 1290 #define MBXERR_NUM_RINGS 1 1291 #define MBXERR_NUM_IOCBS 2 1292 #define MBXERR_IOCBS_EXCEEDED 3 1293 #define MBXERR_BAD_RING_NUMBER 4 1294 #define MBXERR_MASK_ENTRIES_RANGE 5 1295 #define MBXERR_MASKS_EXCEEDED 6 1296 #define MBXERR_BAD_PROFILE 7 1297 #define MBXERR_BAD_DEF_CLASS 8 1298 #define MBXERR_BAD_MAX_RESPONDER 9 1299 #define MBXERR_BAD_MAX_ORIGINATOR 10 1300 #define MBXERR_RPI_REGISTERED 11 1301 #define MBXERR_RPI_FULL 12 1302 #define MBXERR_NO_RESOURCES 13 1303 #define MBXERR_BAD_RCV_LENGTH 14 1304 #define MBXERR_DMA_ERROR 15 1305 #define MBXERR_ERROR 16 1306 #define MBX_NOT_FINISHED 255 1307 1308 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1309 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1310 1311 /* 1312 * Begin Structure Definitions for Mailbox Commands 1313 */ 1314 1315 typedef struct { 1316 #ifdef __BIG_ENDIAN_BITFIELD 1317 uint8_t tval; 1318 uint8_t tmask; 1319 uint8_t rval; 1320 uint8_t rmask; 1321 #else /* __LITTLE_ENDIAN_BITFIELD */ 1322 uint8_t rmask; 1323 uint8_t rval; 1324 uint8_t tmask; 1325 uint8_t tval; 1326 #endif 1327 } RR_REG; 1328 1329 struct ulp_bde { 1330 uint32_t bdeAddress; 1331 #ifdef __BIG_ENDIAN_BITFIELD 1332 uint32_t bdeReserved:4; 1333 uint32_t bdeAddrHigh:4; 1334 uint32_t bdeSize:24; 1335 #else /* __LITTLE_ENDIAN_BITFIELD */ 1336 uint32_t bdeSize:24; 1337 uint32_t bdeAddrHigh:4; 1338 uint32_t bdeReserved:4; 1339 #endif 1340 }; 1341 1342 struct ulp_bde64 { /* SLI-2 */ 1343 union ULP_BDE_TUS { 1344 uint32_t w; 1345 struct { 1346 #ifdef __BIG_ENDIAN_BITFIELD 1347 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1348 VALUE !! */ 1349 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1350 #else /* __LITTLE_ENDIAN_BITFIELD */ 1351 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1352 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1353 VALUE !! */ 1354 #endif 1355 1356 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1357 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1358 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1359 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit 1360 buffer */ 1361 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit 1362 addr */ 1363 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1364 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1365 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1366 } f; 1367 } tus; 1368 uint32_t addrLow; 1369 uint32_t addrHigh; 1370 }; 1371 #define BDE64_SIZE_WORD 0 1372 #define BPL64_SIZE_WORD 0x40 1373 1374 typedef struct ULP_BDL { /* SLI-2 */ 1375 #ifdef __BIG_ENDIAN_BITFIELD 1376 uint32_t bdeFlags:8; /* BDL Flags */ 1377 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1378 #else /* __LITTLE_ENDIAN_BITFIELD */ 1379 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1380 uint32_t bdeFlags:8; /* BDL Flags */ 1381 #endif 1382 1383 uint32_t addrLow; /* Address 0:31 */ 1384 uint32_t addrHigh; /* Address 32:63 */ 1385 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1386 } ULP_BDL; 1387 1388 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1389 1390 typedef struct { 1391 #ifdef __BIG_ENDIAN_BITFIELD 1392 uint32_t rsvd2:25; 1393 uint32_t acknowledgment:1; 1394 uint32_t version:1; 1395 uint32_t erase_or_prog:1; 1396 uint32_t update_flash:1; 1397 uint32_t update_ram:1; 1398 uint32_t method:1; 1399 uint32_t load_cmplt:1; 1400 #else /* __LITTLE_ENDIAN_BITFIELD */ 1401 uint32_t load_cmplt:1; 1402 uint32_t method:1; 1403 uint32_t update_ram:1; 1404 uint32_t update_flash:1; 1405 uint32_t erase_or_prog:1; 1406 uint32_t version:1; 1407 uint32_t acknowledgment:1; 1408 uint32_t rsvd2:25; 1409 #endif 1410 1411 uint32_t dl_to_adr_low; 1412 uint32_t dl_to_adr_high; 1413 uint32_t dl_len; 1414 union { 1415 uint32_t dl_from_mbx_offset; 1416 struct ulp_bde dl_from_bde; 1417 struct ulp_bde64 dl_from_bde64; 1418 } un; 1419 1420 } LOAD_SM_VAR; 1421 1422 /* Structure for MB Command READ_NVPARM (02) */ 1423 1424 typedef struct { 1425 uint32_t rsvd1[3]; /* Read as all one's */ 1426 uint32_t rsvd2; /* Read as all zero's */ 1427 uint32_t portname[2]; /* N_PORT name */ 1428 uint32_t nodename[2]; /* NODE name */ 1429 1430 #ifdef __BIG_ENDIAN_BITFIELD 1431 uint32_t pref_DID:24; 1432 uint32_t hardAL_PA:8; 1433 #else /* __LITTLE_ENDIAN_BITFIELD */ 1434 uint32_t hardAL_PA:8; 1435 uint32_t pref_DID:24; 1436 #endif 1437 1438 uint32_t rsvd3[21]; /* Read as all one's */ 1439 } READ_NV_VAR; 1440 1441 /* Structure for MB Command WRITE_NVPARMS (03) */ 1442 1443 typedef struct { 1444 uint32_t rsvd1[3]; /* Must be all one's */ 1445 uint32_t rsvd2; /* Must be all zero's */ 1446 uint32_t portname[2]; /* N_PORT name */ 1447 uint32_t nodename[2]; /* NODE name */ 1448 1449 #ifdef __BIG_ENDIAN_BITFIELD 1450 uint32_t pref_DID:24; 1451 uint32_t hardAL_PA:8; 1452 #else /* __LITTLE_ENDIAN_BITFIELD */ 1453 uint32_t hardAL_PA:8; 1454 uint32_t pref_DID:24; 1455 #endif 1456 1457 uint32_t rsvd3[21]; /* Must be all one's */ 1458 } WRITE_NV_VAR; 1459 1460 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1461 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1462 1463 typedef struct { 1464 uint32_t rsvd1; 1465 union { 1466 struct { 1467 struct ulp_bde xmit_bde; 1468 struct ulp_bde rcv_bde; 1469 } s1; 1470 struct { 1471 struct ulp_bde64 xmit_bde64; 1472 struct ulp_bde64 rcv_bde64; 1473 } s2; 1474 } un; 1475 } BIU_DIAG_VAR; 1476 1477 /* Structure for MB Command INIT_LINK (05) */ 1478 1479 typedef struct { 1480 #ifdef __BIG_ENDIAN_BITFIELD 1481 uint32_t rsvd1:24; 1482 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1483 #else /* __LITTLE_ENDIAN_BITFIELD */ 1484 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1485 uint32_t rsvd1:24; 1486 #endif 1487 1488 #ifdef __BIG_ENDIAN_BITFIELD 1489 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1490 uint8_t rsvd2; 1491 uint16_t link_flags; 1492 #else /* __LITTLE_ENDIAN_BITFIELD */ 1493 uint16_t link_flags; 1494 uint8_t rsvd2; 1495 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1496 #endif 1497 1498 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1499 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1500 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1501 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1502 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1503 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1504 1505 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1506 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1507 1508 uint32_t link_speed; 1509 #define LINK_SPEED_AUTO 0 /* Auto selection */ 1510 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1511 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1512 #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1513 #define LINK_SPEED_8G 8 /* 4 Gigabaud */ 1514 #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1515 1516 } INIT_LINK_VAR; 1517 1518 /* Structure for MB Command DOWN_LINK (06) */ 1519 1520 typedef struct { 1521 uint32_t rsvd1; 1522 } DOWN_LINK_VAR; 1523 1524 /* Structure for MB Command CONFIG_LINK (07) */ 1525 1526 typedef struct { 1527 #ifdef __BIG_ENDIAN_BITFIELD 1528 uint32_t cr:1; 1529 uint32_t ci:1; 1530 uint32_t cr_delay:6; 1531 uint32_t cr_count:8; 1532 uint32_t rsvd1:8; 1533 uint32_t MaxBBC:8; 1534 #else /* __LITTLE_ENDIAN_BITFIELD */ 1535 uint32_t MaxBBC:8; 1536 uint32_t rsvd1:8; 1537 uint32_t cr_count:8; 1538 uint32_t cr_delay:6; 1539 uint32_t ci:1; 1540 uint32_t cr:1; 1541 #endif 1542 1543 uint32_t myId; 1544 uint32_t rsvd2; 1545 uint32_t edtov; 1546 uint32_t arbtov; 1547 uint32_t ratov; 1548 uint32_t rttov; 1549 uint32_t altov; 1550 uint32_t crtov; 1551 uint32_t citov; 1552 #ifdef __BIG_ENDIAN_BITFIELD 1553 uint32_t rrq_enable:1; 1554 uint32_t rrq_immed:1; 1555 uint32_t rsvd4:29; 1556 uint32_t ack0_enable:1; 1557 #else /* __LITTLE_ENDIAN_BITFIELD */ 1558 uint32_t ack0_enable:1; 1559 uint32_t rsvd4:29; 1560 uint32_t rrq_immed:1; 1561 uint32_t rrq_enable:1; 1562 #endif 1563 } CONFIG_LINK; 1564 1565 /* Structure for MB Command PART_SLIM (08) 1566 * will be removed since SLI1 is no longer supported! 1567 */ 1568 typedef struct { 1569 #ifdef __BIG_ENDIAN_BITFIELD 1570 uint16_t offCiocb; 1571 uint16_t numCiocb; 1572 uint16_t offRiocb; 1573 uint16_t numRiocb; 1574 #else /* __LITTLE_ENDIAN_BITFIELD */ 1575 uint16_t numCiocb; 1576 uint16_t offCiocb; 1577 uint16_t numRiocb; 1578 uint16_t offRiocb; 1579 #endif 1580 } RING_DEF; 1581 1582 typedef struct { 1583 #ifdef __BIG_ENDIAN_BITFIELD 1584 uint32_t unused1:24; 1585 uint32_t numRing:8; 1586 #else /* __LITTLE_ENDIAN_BITFIELD */ 1587 uint32_t numRing:8; 1588 uint32_t unused1:24; 1589 #endif 1590 1591 RING_DEF ringdef[4]; 1592 uint32_t hbainit; 1593 } PART_SLIM_VAR; 1594 1595 /* Structure for MB Command CONFIG_RING (09) */ 1596 1597 typedef struct { 1598 #ifdef __BIG_ENDIAN_BITFIELD 1599 uint32_t unused2:6; 1600 uint32_t recvSeq:1; 1601 uint32_t recvNotify:1; 1602 uint32_t numMask:8; 1603 uint32_t profile:8; 1604 uint32_t unused1:4; 1605 uint32_t ring:4; 1606 #else /* __LITTLE_ENDIAN_BITFIELD */ 1607 uint32_t ring:4; 1608 uint32_t unused1:4; 1609 uint32_t profile:8; 1610 uint32_t numMask:8; 1611 uint32_t recvNotify:1; 1612 uint32_t recvSeq:1; 1613 uint32_t unused2:6; 1614 #endif 1615 1616 #ifdef __BIG_ENDIAN_BITFIELD 1617 uint16_t maxRespXchg; 1618 uint16_t maxOrigXchg; 1619 #else /* __LITTLE_ENDIAN_BITFIELD */ 1620 uint16_t maxOrigXchg; 1621 uint16_t maxRespXchg; 1622 #endif 1623 1624 RR_REG rrRegs[6]; 1625 } CONFIG_RING_VAR; 1626 1627 /* Structure for MB Command RESET_RING (10) */ 1628 1629 typedef struct { 1630 uint32_t ring_no; 1631 } RESET_RING_VAR; 1632 1633 /* Structure for MB Command READ_CONFIG (11) */ 1634 1635 typedef struct { 1636 #ifdef __BIG_ENDIAN_BITFIELD 1637 uint32_t cr:1; 1638 uint32_t ci:1; 1639 uint32_t cr_delay:6; 1640 uint32_t cr_count:8; 1641 uint32_t InitBBC:8; 1642 uint32_t MaxBBC:8; 1643 #else /* __LITTLE_ENDIAN_BITFIELD */ 1644 uint32_t MaxBBC:8; 1645 uint32_t InitBBC:8; 1646 uint32_t cr_count:8; 1647 uint32_t cr_delay:6; 1648 uint32_t ci:1; 1649 uint32_t cr:1; 1650 #endif 1651 1652 #ifdef __BIG_ENDIAN_BITFIELD 1653 uint32_t topology:8; 1654 uint32_t myDid:24; 1655 #else /* __LITTLE_ENDIAN_BITFIELD */ 1656 uint32_t myDid:24; 1657 uint32_t topology:8; 1658 #endif 1659 1660 /* Defines for topology (defined previously) */ 1661 #ifdef __BIG_ENDIAN_BITFIELD 1662 uint32_t AR:1; 1663 uint32_t IR:1; 1664 uint32_t rsvd1:29; 1665 uint32_t ack0:1; 1666 #else /* __LITTLE_ENDIAN_BITFIELD */ 1667 uint32_t ack0:1; 1668 uint32_t rsvd1:29; 1669 uint32_t IR:1; 1670 uint32_t AR:1; 1671 #endif 1672 1673 uint32_t edtov; 1674 uint32_t arbtov; 1675 uint32_t ratov; 1676 uint32_t rttov; 1677 uint32_t altov; 1678 uint32_t lmt; 1679 #define LMT_RESERVED 0x0 /* Not used */ 1680 #define LMT_266_10bit 0x1 /* 265.625 Mbaud 10 bit iface */ 1681 #define LMT_532_10bit 0x2 /* 531.25 Mbaud 10 bit iface */ 1682 #define LMT_1063_20bit 0x3 /* 1062.5 Mbaud 20 bit iface */ 1683 #define LMT_1063_10bit 0x4 /* 1062.5 Mbaud 10 bit iface */ 1684 #define LMT_2125_10bit 0x8 /* 2125 Mbaud 10 bit iface */ 1685 #define LMT_4250_10bit 0x40 /* 4250 Mbaud 10 bit iface */ 1686 1687 uint32_t rsvd2; 1688 uint32_t rsvd3; 1689 uint32_t max_xri; 1690 uint32_t max_iocb; 1691 uint32_t max_rpi; 1692 uint32_t avail_xri; 1693 uint32_t avail_iocb; 1694 uint32_t avail_rpi; 1695 uint32_t default_rpi; 1696 } READ_CONFIG_VAR; 1697 1698 /* Structure for MB Command READ_RCONFIG (12) */ 1699 1700 typedef struct { 1701 #ifdef __BIG_ENDIAN_BITFIELD 1702 uint32_t rsvd2:7; 1703 uint32_t recvNotify:1; 1704 uint32_t numMask:8; 1705 uint32_t profile:8; 1706 uint32_t rsvd1:4; 1707 uint32_t ring:4; 1708 #else /* __LITTLE_ENDIAN_BITFIELD */ 1709 uint32_t ring:4; 1710 uint32_t rsvd1:4; 1711 uint32_t profile:8; 1712 uint32_t numMask:8; 1713 uint32_t recvNotify:1; 1714 uint32_t rsvd2:7; 1715 #endif 1716 1717 #ifdef __BIG_ENDIAN_BITFIELD 1718 uint16_t maxResp; 1719 uint16_t maxOrig; 1720 #else /* __LITTLE_ENDIAN_BITFIELD */ 1721 uint16_t maxOrig; 1722 uint16_t maxResp; 1723 #endif 1724 1725 RR_REG rrRegs[6]; 1726 1727 #ifdef __BIG_ENDIAN_BITFIELD 1728 uint16_t cmdRingOffset; 1729 uint16_t cmdEntryCnt; 1730 uint16_t rspRingOffset; 1731 uint16_t rspEntryCnt; 1732 uint16_t nextCmdOffset; 1733 uint16_t rsvd3; 1734 uint16_t nextRspOffset; 1735 uint16_t rsvd4; 1736 #else /* __LITTLE_ENDIAN_BITFIELD */ 1737 uint16_t cmdEntryCnt; 1738 uint16_t cmdRingOffset; 1739 uint16_t rspEntryCnt; 1740 uint16_t rspRingOffset; 1741 uint16_t rsvd3; 1742 uint16_t nextCmdOffset; 1743 uint16_t rsvd4; 1744 uint16_t nextRspOffset; 1745 #endif 1746 } READ_RCONF_VAR; 1747 1748 /* Structure for MB Command READ_SPARM (13) */ 1749 /* Structure for MB Command READ_SPARM64 (0x8D) */ 1750 1751 typedef struct { 1752 uint32_t rsvd1; 1753 uint32_t rsvd2; 1754 union { 1755 struct ulp_bde sp; /* This BDE points to struct serv_parm 1756 structure */ 1757 struct ulp_bde64 sp64; 1758 } un; 1759 } READ_SPARM_VAR; 1760 1761 /* Structure for MB Command READ_STATUS (14) */ 1762 1763 typedef struct { 1764 #ifdef __BIG_ENDIAN_BITFIELD 1765 uint32_t rsvd1:31; 1766 uint32_t clrCounters:1; 1767 uint16_t activeXriCnt; 1768 uint16_t activeRpiCnt; 1769 #else /* __LITTLE_ENDIAN_BITFIELD */ 1770 uint32_t clrCounters:1; 1771 uint32_t rsvd1:31; 1772 uint16_t activeRpiCnt; 1773 uint16_t activeXriCnt; 1774 #endif 1775 1776 uint32_t xmitByteCnt; 1777 uint32_t rcvByteCnt; 1778 uint32_t xmitFrameCnt; 1779 uint32_t rcvFrameCnt; 1780 uint32_t xmitSeqCnt; 1781 uint32_t rcvSeqCnt; 1782 uint32_t totalOrigExchanges; 1783 uint32_t totalRespExchanges; 1784 uint32_t rcvPbsyCnt; 1785 uint32_t rcvFbsyCnt; 1786 } READ_STATUS_VAR; 1787 1788 /* Structure for MB Command READ_RPI (15) */ 1789 /* Structure for MB Command READ_RPI64 (0x8F) */ 1790 1791 typedef struct { 1792 #ifdef __BIG_ENDIAN_BITFIELD 1793 uint16_t nextRpi; 1794 uint16_t reqRpi; 1795 uint32_t rsvd2:8; 1796 uint32_t DID:24; 1797 #else /* __LITTLE_ENDIAN_BITFIELD */ 1798 uint16_t reqRpi; 1799 uint16_t nextRpi; 1800 uint32_t DID:24; 1801 uint32_t rsvd2:8; 1802 #endif 1803 1804 union { 1805 struct ulp_bde sp; 1806 struct ulp_bde64 sp64; 1807 } un; 1808 1809 } READ_RPI_VAR; 1810 1811 /* Structure for MB Command READ_XRI (16) */ 1812 1813 typedef struct { 1814 #ifdef __BIG_ENDIAN_BITFIELD 1815 uint16_t nextXri; 1816 uint16_t reqXri; 1817 uint16_t rsvd1; 1818 uint16_t rpi; 1819 uint32_t rsvd2:8; 1820 uint32_t DID:24; 1821 uint32_t rsvd3:8; 1822 uint32_t SID:24; 1823 uint32_t rsvd4; 1824 uint8_t seqId; 1825 uint8_t rsvd5; 1826 uint16_t seqCount; 1827 uint16_t oxId; 1828 uint16_t rxId; 1829 uint32_t rsvd6:30; 1830 uint32_t si:1; 1831 uint32_t exchOrig:1; 1832 #else /* __LITTLE_ENDIAN_BITFIELD */ 1833 uint16_t reqXri; 1834 uint16_t nextXri; 1835 uint16_t rpi; 1836 uint16_t rsvd1; 1837 uint32_t DID:24; 1838 uint32_t rsvd2:8; 1839 uint32_t SID:24; 1840 uint32_t rsvd3:8; 1841 uint32_t rsvd4; 1842 uint16_t seqCount; 1843 uint8_t rsvd5; 1844 uint8_t seqId; 1845 uint16_t rxId; 1846 uint16_t oxId; 1847 uint32_t exchOrig:1; 1848 uint32_t si:1; 1849 uint32_t rsvd6:30; 1850 #endif 1851 } READ_XRI_VAR; 1852 1853 /* Structure for MB Command READ_REV (17) */ 1854 1855 typedef struct { 1856 #ifdef __BIG_ENDIAN_BITFIELD 1857 uint32_t cv:1; 1858 uint32_t rr:1; 1859 uint32_t rsvd1:29; 1860 uint32_t rv:1; 1861 #else /* __LITTLE_ENDIAN_BITFIELD */ 1862 uint32_t rv:1; 1863 uint32_t rsvd1:29; 1864 uint32_t rr:1; 1865 uint32_t cv:1; 1866 #endif 1867 1868 uint32_t biuRev; 1869 uint32_t smRev; 1870 union { 1871 uint32_t smFwRev; 1872 struct { 1873 #ifdef __BIG_ENDIAN_BITFIELD 1874 uint8_t ProgType; 1875 uint8_t ProgId; 1876 uint16_t ProgVer:4; 1877 uint16_t ProgRev:4; 1878 uint16_t ProgFixLvl:2; 1879 uint16_t ProgDistType:2; 1880 uint16_t DistCnt:4; 1881 #else /* __LITTLE_ENDIAN_BITFIELD */ 1882 uint16_t DistCnt:4; 1883 uint16_t ProgDistType:2; 1884 uint16_t ProgFixLvl:2; 1885 uint16_t ProgRev:4; 1886 uint16_t ProgVer:4; 1887 uint8_t ProgId; 1888 uint8_t ProgType; 1889 #endif 1890 1891 } b; 1892 } un; 1893 uint32_t endecRev; 1894 #ifdef __BIG_ENDIAN_BITFIELD 1895 uint8_t feaLevelHigh; 1896 uint8_t feaLevelLow; 1897 uint8_t fcphHigh; 1898 uint8_t fcphLow; 1899 #else /* __LITTLE_ENDIAN_BITFIELD */ 1900 uint8_t fcphLow; 1901 uint8_t fcphHigh; 1902 uint8_t feaLevelLow; 1903 uint8_t feaLevelHigh; 1904 #endif 1905 1906 uint32_t postKernRev; 1907 uint32_t opFwRev; 1908 uint8_t opFwName[16]; 1909 uint32_t sli1FwRev; 1910 uint8_t sli1FwName[16]; 1911 uint32_t sli2FwRev; 1912 uint8_t sli2FwName[16]; 1913 uint32_t rsvd2; 1914 uint32_t RandomData[7]; 1915 } READ_REV_VAR; 1916 1917 /* Structure for MB Command READ_LINK_STAT (18) */ 1918 1919 typedef struct { 1920 uint32_t rsvd1; 1921 uint32_t linkFailureCnt; 1922 uint32_t lossSyncCnt; 1923 1924 uint32_t lossSignalCnt; 1925 uint32_t primSeqErrCnt; 1926 uint32_t invalidXmitWord; 1927 uint32_t crcCnt; 1928 uint32_t primSeqTimeout; 1929 uint32_t elasticOverrun; 1930 uint32_t arbTimeout; 1931 } READ_LNK_VAR; 1932 1933 /* Structure for MB Command REG_LOGIN (19) */ 1934 /* Structure for MB Command REG_LOGIN64 (0x93) */ 1935 1936 typedef struct { 1937 #ifdef __BIG_ENDIAN_BITFIELD 1938 uint16_t rsvd1; 1939 uint16_t rpi; 1940 uint32_t rsvd2:8; 1941 uint32_t did:24; 1942 #else /* __LITTLE_ENDIAN_BITFIELD */ 1943 uint16_t rpi; 1944 uint16_t rsvd1; 1945 uint32_t did:24; 1946 uint32_t rsvd2:8; 1947 #endif 1948 1949 union { 1950 struct ulp_bde sp; 1951 struct ulp_bde64 sp64; 1952 } un; 1953 1954 } REG_LOGIN_VAR; 1955 1956 /* Word 30 contents for REG_LOGIN */ 1957 typedef union { 1958 struct { 1959 #ifdef __BIG_ENDIAN_BITFIELD 1960 uint16_t rsvd1:12; 1961 uint16_t wd30_class:4; 1962 uint16_t xri; 1963 #else /* __LITTLE_ENDIAN_BITFIELD */ 1964 uint16_t xri; 1965 uint16_t wd30_class:4; 1966 uint16_t rsvd1:12; 1967 #endif 1968 } f; 1969 uint32_t word; 1970 } REG_WD30; 1971 1972 /* Structure for MB Command UNREG_LOGIN (20) */ 1973 1974 typedef struct { 1975 #ifdef __BIG_ENDIAN_BITFIELD 1976 uint16_t rsvd1; 1977 uint16_t rpi; 1978 #else /* __LITTLE_ENDIAN_BITFIELD */ 1979 uint16_t rpi; 1980 uint16_t rsvd1; 1981 #endif 1982 } UNREG_LOGIN_VAR; 1983 1984 /* Structure for MB Command UNREG_D_ID (0x23) */ 1985 1986 typedef struct { 1987 uint32_t did; 1988 } UNREG_D_ID_VAR; 1989 1990 /* Structure for MB Command READ_LA (21) */ 1991 /* Structure for MB Command READ_LA64 (0x95) */ 1992 1993 typedef struct { 1994 uint32_t eventTag; /* Event tag */ 1995 #ifdef __BIG_ENDIAN_BITFIELD 1996 uint32_t rsvd1:22; 1997 uint32_t pb:1; 1998 uint32_t il:1; 1999 uint32_t attType:8; 2000 #else /* __LITTLE_ENDIAN_BITFIELD */ 2001 uint32_t attType:8; 2002 uint32_t il:1; 2003 uint32_t pb:1; 2004 uint32_t rsvd1:22; 2005 #endif 2006 2007 #define AT_RESERVED 0x00 /* Reserved - attType */ 2008 #define AT_LINK_UP 0x01 /* Link is up */ 2009 #define AT_LINK_DOWN 0x02 /* Link is down */ 2010 2011 #ifdef __BIG_ENDIAN_BITFIELD 2012 uint8_t granted_AL_PA; 2013 uint8_t lipAlPs; 2014 uint8_t lipType; 2015 uint8_t topology; 2016 #else /* __LITTLE_ENDIAN_BITFIELD */ 2017 uint8_t topology; 2018 uint8_t lipType; 2019 uint8_t lipAlPs; 2020 uint8_t granted_AL_PA; 2021 #endif 2022 2023 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2024 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2025 2026 union { 2027 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2028 to */ 2029 /* store the LILP AL_PA position map into */ 2030 struct ulp_bde64 lilpBde64; 2031 } un; 2032 2033 #ifdef __BIG_ENDIAN_BITFIELD 2034 uint32_t Dlu:1; 2035 uint32_t Dtf:1; 2036 uint32_t Drsvd2:14; 2037 uint32_t DlnkSpeed:8; 2038 uint32_t DnlPort:4; 2039 uint32_t Dtx:2; 2040 uint32_t Drx:2; 2041 #else /* __LITTLE_ENDIAN_BITFIELD */ 2042 uint32_t Drx:2; 2043 uint32_t Dtx:2; 2044 uint32_t DnlPort:4; 2045 uint32_t DlnkSpeed:8; 2046 uint32_t Drsvd2:14; 2047 uint32_t Dtf:1; 2048 uint32_t Dlu:1; 2049 #endif 2050 2051 #ifdef __BIG_ENDIAN_BITFIELD 2052 uint32_t Ulu:1; 2053 uint32_t Utf:1; 2054 uint32_t Ursvd2:14; 2055 uint32_t UlnkSpeed:8; 2056 uint32_t UnlPort:4; 2057 uint32_t Utx:2; 2058 uint32_t Urx:2; 2059 #else /* __LITTLE_ENDIAN_BITFIELD */ 2060 uint32_t Urx:2; 2061 uint32_t Utx:2; 2062 uint32_t UnlPort:4; 2063 uint32_t UlnkSpeed:8; 2064 uint32_t Ursvd2:14; 2065 uint32_t Utf:1; 2066 uint32_t Ulu:1; 2067 #endif 2068 2069 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2070 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2071 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2072 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2073 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2074 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2075 2076 } READ_LA_VAR; 2077 2078 /* Structure for MB Command CLEAR_LA (22) */ 2079 2080 typedef struct { 2081 uint32_t eventTag; /* Event tag */ 2082 uint32_t rsvd1; 2083 } CLEAR_LA_VAR; 2084 2085 /* Structure for MB Command DUMP */ 2086 2087 typedef struct { 2088 #ifdef __BIG_ENDIAN_BITFIELD 2089 uint32_t rsvd:25; 2090 uint32_t ra:1; 2091 uint32_t co:1; 2092 uint32_t cv:1; 2093 uint32_t type:4; 2094 uint32_t entry_index:16; 2095 uint32_t region_id:16; 2096 #else /* __LITTLE_ENDIAN_BITFIELD */ 2097 uint32_t type:4; 2098 uint32_t cv:1; 2099 uint32_t co:1; 2100 uint32_t ra:1; 2101 uint32_t rsvd:25; 2102 uint32_t region_id:16; 2103 uint32_t entry_index:16; 2104 #endif 2105 2106 uint32_t rsvd1; 2107 uint32_t word_cnt; 2108 uint32_t resp_offset; 2109 } DUMP_VAR; 2110 2111 #define DMP_MEM_REG 0x1 2112 #define DMP_NV_PARAMS 0x2 2113 2114 #define DMP_REGION_VPD 0xe 2115 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2116 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2117 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2118 2119 /* Structure for MB Command CONFIG_PORT (0x88) */ 2120 2121 typedef struct { 2122 uint32_t pcbLen; 2123 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2124 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2125 uint32_t hbainit[5]; 2126 } CONFIG_PORT_VAR; 2127 2128 /* SLI-2 Port Control Block */ 2129 2130 /* SLIM POINTER */ 2131 #define SLIMOFF 0x30 /* WORD */ 2132 2133 typedef struct _SLI2_RDSC { 2134 uint32_t cmdEntries; 2135 uint32_t cmdAddrLow; 2136 uint32_t cmdAddrHigh; 2137 2138 uint32_t rspEntries; 2139 uint32_t rspAddrLow; 2140 uint32_t rspAddrHigh; 2141 } SLI2_RDSC; 2142 2143 typedef struct _PCB { 2144 #ifdef __BIG_ENDIAN_BITFIELD 2145 uint32_t type:8; 2146 #define TYPE_NATIVE_SLI2 0x01; 2147 uint32_t feature:8; 2148 #define FEATURE_INITIAL_SLI2 0x01; 2149 uint32_t rsvd:12; 2150 uint32_t maxRing:4; 2151 #else /* __LITTLE_ENDIAN_BITFIELD */ 2152 uint32_t maxRing:4; 2153 uint32_t rsvd:12; 2154 uint32_t feature:8; 2155 #define FEATURE_INITIAL_SLI2 0x01; 2156 uint32_t type:8; 2157 #define TYPE_NATIVE_SLI2 0x01; 2158 #endif 2159 2160 uint32_t mailBoxSize; 2161 uint32_t mbAddrLow; 2162 uint32_t mbAddrHigh; 2163 2164 uint32_t hgpAddrLow; 2165 uint32_t hgpAddrHigh; 2166 2167 uint32_t pgpAddrLow; 2168 uint32_t pgpAddrHigh; 2169 SLI2_RDSC rdsc[MAX_RINGS]; 2170 } PCB_t; 2171 2172 /* NEW_FEATURE */ 2173 typedef struct { 2174 #ifdef __BIG_ENDIAN_BITFIELD 2175 uint32_t rsvd0:27; 2176 uint32_t discardFarp:1; 2177 uint32_t IPEnable:1; 2178 uint32_t nodeName:1; 2179 uint32_t portName:1; 2180 uint32_t filterEnable:1; 2181 #else /* __LITTLE_ENDIAN_BITFIELD */ 2182 uint32_t filterEnable:1; 2183 uint32_t portName:1; 2184 uint32_t nodeName:1; 2185 uint32_t IPEnable:1; 2186 uint32_t discardFarp:1; 2187 uint32_t rsvd:27; 2188 #endif 2189 2190 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2191 uint8_t nodename[8]; 2192 uint32_t rsvd1; 2193 uint32_t rsvd2; 2194 uint32_t rsvd3; 2195 uint32_t IPAddress; 2196 } CONFIG_FARP_VAR; 2197 2198 /* Union of all Mailbox Command types */ 2199 #define MAILBOX_CMD_WSIZE 32 2200 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2201 2202 typedef union { 2203 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; 2204 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2205 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2206 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2207 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2208 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2209 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2210 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2211 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2212 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2213 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2214 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2215 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2216 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2217 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2218 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2219 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2220 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2221 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2222 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2223 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2224 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2225 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2226 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2227 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2228 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) NEW_FEATURE */ 2229 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2230 } MAILVARIANTS; 2231 2232 /* 2233 * SLI-2 specific structures 2234 */ 2235 2236 struct lpfc_hgp { 2237 __le32 cmdPutInx; 2238 __le32 rspGetInx; 2239 }; 2240 2241 struct lpfc_pgp { 2242 __le32 cmdGetInx; 2243 __le32 rspPutInx; 2244 }; 2245 2246 typedef struct _SLI2_DESC { 2247 struct lpfc_hgp host[MAX_RINGS]; 2248 uint32_t unused1[16]; 2249 struct lpfc_pgp port[MAX_RINGS]; 2250 } SLI2_DESC; 2251 2252 typedef union { 2253 SLI2_DESC s2; 2254 } SLI_VAR; 2255 2256 typedef struct { 2257 #ifdef __BIG_ENDIAN_BITFIELD 2258 uint16_t mbxStatus; 2259 uint8_t mbxCommand; 2260 uint8_t mbxReserved:6; 2261 uint8_t mbxHc:1; 2262 uint8_t mbxOwner:1; /* Low order bit first word */ 2263 #else /* __LITTLE_ENDIAN_BITFIELD */ 2264 uint8_t mbxOwner:1; /* Low order bit first word */ 2265 uint8_t mbxHc:1; 2266 uint8_t mbxReserved:6; 2267 uint8_t mbxCommand; 2268 uint16_t mbxStatus; 2269 #endif 2270 2271 MAILVARIANTS un; 2272 SLI_VAR us; 2273 } MAILBOX_t; 2274 2275 /* 2276 * Begin Structure Definitions for IOCB Commands 2277 */ 2278 2279 typedef struct { 2280 #ifdef __BIG_ENDIAN_BITFIELD 2281 uint8_t statAction; 2282 uint8_t statRsn; 2283 uint8_t statBaExp; 2284 uint8_t statLocalError; 2285 #else /* __LITTLE_ENDIAN_BITFIELD */ 2286 uint8_t statLocalError; 2287 uint8_t statBaExp; 2288 uint8_t statRsn; 2289 uint8_t statAction; 2290 #endif 2291 /* statRsn P/F_RJT reason codes */ 2292 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 2293 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 2294 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 2295 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 2296 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 2297 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 2298 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 2299 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 2300 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 2301 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 2302 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 2303 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 2304 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 2305 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 2306 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 2307 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 2308 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 2309 #define RJT_PROT_ERR 0x12 /* Protocol error */ 2310 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 2311 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 2312 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 2313 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 2314 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 2315 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 2316 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 2317 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 2318 2319 #define IOERR_SUCCESS 0x00 /* statLocalError */ 2320 #define IOERR_MISSING_CONTINUE 0x01 2321 #define IOERR_SEQUENCE_TIMEOUT 0x02 2322 #define IOERR_INTERNAL_ERROR 0x03 2323 #define IOERR_INVALID_RPI 0x04 2324 #define IOERR_NO_XRI 0x05 2325 #define IOERR_ILLEGAL_COMMAND 0x06 2326 #define IOERR_XCHG_DROPPED 0x07 2327 #define IOERR_ILLEGAL_FIELD 0x08 2328 #define IOERR_BAD_CONTINUE 0x09 2329 #define IOERR_TOO_MANY_BUFFERS 0x0A 2330 #define IOERR_RCV_BUFFER_WAITING 0x0B 2331 #define IOERR_NO_CONNECTION 0x0C 2332 #define IOERR_TX_DMA_FAILED 0x0D 2333 #define IOERR_RX_DMA_FAILED 0x0E 2334 #define IOERR_ILLEGAL_FRAME 0x0F 2335 #define IOERR_EXTRA_DATA 0x10 2336 #define IOERR_NO_RESOURCES 0x11 2337 #define IOERR_RESERVED 0x12 2338 #define IOERR_ILLEGAL_LENGTH 0x13 2339 #define IOERR_UNSUPPORTED_FEATURE 0x14 2340 #define IOERR_ABORT_IN_PROGRESS 0x15 2341 #define IOERR_ABORT_REQUESTED 0x16 2342 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 2343 #define IOERR_LOOP_OPEN_FAILURE 0x18 2344 #define IOERR_RING_RESET 0x19 2345 #define IOERR_LINK_DOWN 0x1A 2346 #define IOERR_CORRUPTED_DATA 0x1B 2347 #define IOERR_CORRUPTED_RPI 0x1C 2348 #define IOERR_OUT_OF_ORDER_DATA 0x1D 2349 #define IOERR_OUT_OF_ORDER_ACK 0x1E 2350 #define IOERR_DUP_FRAME 0x1F 2351 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 2352 #define IOERR_BAD_HOST_ADDRESS 0x21 2353 #define IOERR_RCV_HDRBUF_WAITING 0x22 2354 #define IOERR_MISSING_HDR_BUFFER 0x23 2355 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 2356 #define IOERR_ABORTMULT_REQUESTED 0x25 2357 #define IOERR_BUFFER_SHORTAGE 0x28 2358 #define IOERR_DEFAULT 0x29 2359 #define IOERR_CNT 0x2A 2360 2361 #define IOERR_DRVR_MASK 0x100 2362 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 2363 #define IOERR_SLI_BRESET 0x102 2364 #define IOERR_SLI_ABORTED 0x103 2365 } PARM_ERR; 2366 2367 typedef union { 2368 struct { 2369 #ifdef __BIG_ENDIAN_BITFIELD 2370 uint8_t Rctl; /* R_CTL field */ 2371 uint8_t Type; /* TYPE field */ 2372 uint8_t Dfctl; /* DF_CTL field */ 2373 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2374 #else /* __LITTLE_ENDIAN_BITFIELD */ 2375 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2376 uint8_t Dfctl; /* DF_CTL field */ 2377 uint8_t Type; /* TYPE field */ 2378 uint8_t Rctl; /* R_CTL field */ 2379 #endif 2380 2381 #define BC 0x02 /* Broadcast Received - Fctl */ 2382 #define SI 0x04 /* Sequence Initiative */ 2383 #define LA 0x08 /* Ignore Link Attention state */ 2384 #define LS 0x80 /* Last Sequence */ 2385 } hcsw; 2386 uint32_t reserved; 2387 } WORD5; 2388 2389 /* IOCB Command template for a generic response */ 2390 typedef struct { 2391 uint32_t reserved[4]; 2392 PARM_ERR perr; 2393 } GENERIC_RSP; 2394 2395 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 2396 typedef struct { 2397 struct ulp_bde xrsqbde[2]; 2398 uint32_t xrsqRo; /* Starting Relative Offset */ 2399 WORD5 w5; /* Header control/status word */ 2400 } XR_SEQ_FIELDS; 2401 2402 /* IOCB Command template for ELS_REQUEST */ 2403 typedef struct { 2404 struct ulp_bde elsReq; 2405 struct ulp_bde elsRsp; 2406 2407 #ifdef __BIG_ENDIAN_BITFIELD 2408 uint32_t word4Rsvd:7; 2409 uint32_t fl:1; 2410 uint32_t myID:24; 2411 uint32_t word5Rsvd:8; 2412 uint32_t remoteID:24; 2413 #else /* __LITTLE_ENDIAN_BITFIELD */ 2414 uint32_t myID:24; 2415 uint32_t fl:1; 2416 uint32_t word4Rsvd:7; 2417 uint32_t remoteID:24; 2418 uint32_t word5Rsvd:8; 2419 #endif 2420 } ELS_REQUEST; 2421 2422 /* IOCB Command template for RCV_ELS_REQ */ 2423 typedef struct { 2424 struct ulp_bde elsReq[2]; 2425 uint32_t parmRo; 2426 2427 #ifdef __BIG_ENDIAN_BITFIELD 2428 uint32_t word5Rsvd:8; 2429 uint32_t remoteID:24; 2430 #else /* __LITTLE_ENDIAN_BITFIELD */ 2431 uint32_t remoteID:24; 2432 uint32_t word5Rsvd:8; 2433 #endif 2434 } RCV_ELS_REQ; 2435 2436 /* IOCB Command template for ABORT / CLOSE_XRI */ 2437 typedef struct { 2438 uint32_t rsvd[3]; 2439 uint32_t abortType; 2440 #define ABORT_TYPE_ABTX 0x00000000 2441 #define ABORT_TYPE_ABTS 0x00000001 2442 uint32_t parm; 2443 #ifdef __BIG_ENDIAN_BITFIELD 2444 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2445 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2446 #else /* __LITTLE_ENDIAN_BITFIELD */ 2447 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2448 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2449 #endif 2450 } AC_XRI; 2451 2452 /* IOCB Command template for ABORT_MXRI64 */ 2453 typedef struct { 2454 uint32_t rsvd[3]; 2455 uint32_t abortType; 2456 uint32_t parm; 2457 uint32_t iotag32; 2458 } A_MXRI64; 2459 2460 /* IOCB Command template for GET_RPI */ 2461 typedef struct { 2462 uint32_t rsvd[4]; 2463 uint32_t parmRo; 2464 #ifdef __BIG_ENDIAN_BITFIELD 2465 uint32_t word5Rsvd:8; 2466 uint32_t remoteID:24; 2467 #else /* __LITTLE_ENDIAN_BITFIELD */ 2468 uint32_t remoteID:24; 2469 uint32_t word5Rsvd:8; 2470 #endif 2471 } GET_RPI; 2472 2473 /* IOCB Command template for all FCP Initiator commands */ 2474 typedef struct { 2475 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 2476 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 2477 uint32_t fcpi_parm; 2478 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2479 } FCPI_FIELDS; 2480 2481 /* IOCB Command template for all FCP Target commands */ 2482 typedef struct { 2483 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 2484 uint32_t fcpt_Offset; 2485 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2486 } FCPT_FIELDS; 2487 2488 /* SLI-2 IOCB structure definitions */ 2489 2490 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 2491 typedef struct { 2492 ULP_BDL bdl; 2493 uint32_t xrsqRo; /* Starting Relative Offset */ 2494 WORD5 w5; /* Header control/status word */ 2495 } XMT_SEQ_FIELDS64; 2496 2497 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 2498 typedef struct { 2499 struct ulp_bde64 rcvBde; 2500 uint32_t rsvd1; 2501 uint32_t xrsqRo; /* Starting Relative Offset */ 2502 WORD5 w5; /* Header control/status word */ 2503 } RCV_SEQ_FIELDS64; 2504 2505 /* IOCB Command template for ELS_REQUEST64 */ 2506 typedef struct { 2507 ULP_BDL bdl; 2508 #ifdef __BIG_ENDIAN_BITFIELD 2509 uint32_t word4Rsvd:7; 2510 uint32_t fl:1; 2511 uint32_t myID:24; 2512 uint32_t word5Rsvd:8; 2513 uint32_t remoteID:24; 2514 #else /* __LITTLE_ENDIAN_BITFIELD */ 2515 uint32_t myID:24; 2516 uint32_t fl:1; 2517 uint32_t word4Rsvd:7; 2518 uint32_t remoteID:24; 2519 uint32_t word5Rsvd:8; 2520 #endif 2521 } ELS_REQUEST64; 2522 2523 /* IOCB Command template for GEN_REQUEST64 */ 2524 typedef struct { 2525 ULP_BDL bdl; 2526 uint32_t xrsqRo; /* Starting Relative Offset */ 2527 WORD5 w5; /* Header control/status word */ 2528 } GEN_REQUEST64; 2529 2530 /* IOCB Command template for RCV_ELS_REQ64 */ 2531 typedef struct { 2532 struct ulp_bde64 elsReq; 2533 uint32_t rcvd1; 2534 uint32_t parmRo; 2535 2536 #ifdef __BIG_ENDIAN_BITFIELD 2537 uint32_t word5Rsvd:8; 2538 uint32_t remoteID:24; 2539 #else /* __LITTLE_ENDIAN_BITFIELD */ 2540 uint32_t remoteID:24; 2541 uint32_t word5Rsvd:8; 2542 #endif 2543 } RCV_ELS_REQ64; 2544 2545 /* IOCB Command template for all 64 bit FCP Initiator commands */ 2546 typedef struct { 2547 ULP_BDL bdl; 2548 uint32_t fcpi_parm; 2549 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2550 } FCPI_FIELDS64; 2551 2552 /* IOCB Command template for all 64 bit FCP Target commands */ 2553 typedef struct { 2554 ULP_BDL bdl; 2555 uint32_t fcpt_Offset; 2556 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2557 } FCPT_FIELDS64; 2558 2559 typedef struct _IOCB { /* IOCB structure */ 2560 union { 2561 GENERIC_RSP grsp; /* Generic response */ 2562 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 2563 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 2564 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 2565 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 2566 A_MXRI64 amxri; /* abort multiple xri command overlay */ 2567 GET_RPI getrpi; /* GET_RPI template */ 2568 FCPI_FIELDS fcpi; /* FCP Initiator template */ 2569 FCPT_FIELDS fcpt; /* FCP target template */ 2570 2571 /* SLI-2 structures */ 2572 2573 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 2574 bde_64s */ 2575 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 2576 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 2577 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 2578 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 2579 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 2580 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 2581 2582 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 2583 } un; 2584 union { 2585 struct { 2586 #ifdef __BIG_ENDIAN_BITFIELD 2587 uint16_t ulpContext; /* High order bits word 6 */ 2588 uint16_t ulpIoTag; /* Low order bits word 6 */ 2589 #else /* __LITTLE_ENDIAN_BITFIELD */ 2590 uint16_t ulpIoTag; /* Low order bits word 6 */ 2591 uint16_t ulpContext; /* High order bits word 6 */ 2592 #endif 2593 } t1; 2594 struct { 2595 #ifdef __BIG_ENDIAN_BITFIELD 2596 uint16_t ulpContext; /* High order bits word 6 */ 2597 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 2598 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 2599 #else /* __LITTLE_ENDIAN_BITFIELD */ 2600 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 2601 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 2602 uint16_t ulpContext; /* High order bits word 6 */ 2603 #endif 2604 } t2; 2605 } un1; 2606 #define ulpContext un1.t1.ulpContext 2607 #define ulpIoTag un1.t1.ulpIoTag 2608 #define ulpIoTag0 un1.t2.ulpIoTag0 2609 2610 #ifdef __BIG_ENDIAN_BITFIELD 2611 uint32_t ulpTimeout:8; 2612 uint32_t ulpXS:1; 2613 uint32_t ulpFCP2Rcvy:1; 2614 uint32_t ulpPU:2; 2615 uint32_t ulpIr:1; 2616 uint32_t ulpClass:3; 2617 uint32_t ulpCommand:8; 2618 uint32_t ulpStatus:4; 2619 uint32_t ulpBdeCount:2; 2620 uint32_t ulpLe:1; 2621 uint32_t ulpOwner:1; /* Low order bit word 7 */ 2622 #else /* __LITTLE_ENDIAN_BITFIELD */ 2623 uint32_t ulpOwner:1; /* Low order bit word 7 */ 2624 uint32_t ulpLe:1; 2625 uint32_t ulpBdeCount:2; 2626 uint32_t ulpStatus:4; 2627 uint32_t ulpCommand:8; 2628 uint32_t ulpClass:3; 2629 uint32_t ulpIr:1; 2630 uint32_t ulpPU:2; 2631 uint32_t ulpFCP2Rcvy:1; 2632 uint32_t ulpXS:1; 2633 uint32_t ulpTimeout:8; 2634 #endif 2635 2636 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 2637 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 2638 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 2639 #define CLASS1 0 /* Class 1 */ 2640 #define CLASS2 1 /* Class 2 */ 2641 #define CLASS3 2 /* Class 3 */ 2642 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 2643 2644 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 2645 #define IOSTAT_FCP_RSP_ERROR 0x1 2646 #define IOSTAT_REMOTE_STOP 0x2 2647 #define IOSTAT_LOCAL_REJECT 0x3 2648 #define IOSTAT_NPORT_RJT 0x4 2649 #define IOSTAT_FABRIC_RJT 0x5 2650 #define IOSTAT_NPORT_BSY 0x6 2651 #define IOSTAT_FABRIC_BSY 0x7 2652 #define IOSTAT_INTERMED_RSP 0x8 2653 #define IOSTAT_LS_RJT 0x9 2654 #define IOSTAT_BA_RJT 0xA 2655 #define IOSTAT_RSVD1 0xB 2656 #define IOSTAT_RSVD2 0xC 2657 #define IOSTAT_RSVD3 0xD 2658 #define IOSTAT_RSVD4 0xE 2659 #define IOSTAT_RSVD5 0xF 2660 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 2661 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 2662 #define IOSTAT_CNT 0x11 2663 2664 } IOCB_t; 2665 2666 2667 #define SLI1_SLIM_SIZE (4 * 1024) 2668 2669 /* Up to 498 IOCBs will fit into 16k 2670 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 2671 */ 2672 #define SLI2_SLIM_SIZE (16 * 1024) 2673 2674 /* Maximum IOCBs that will fit in SLI2 slim */ 2675 #define MAX_SLI2_IOCB 498 2676 2677 struct lpfc_sli2_slim { 2678 MAILBOX_t mbx; 2679 PCB_t pcb; 2680 IOCB_t IOCBs[MAX_SLI2_IOCB]; 2681 }; 2682 2683 /******************************************************************* 2684 This macro check PCI device to allow special handling for LC HBAs. 2685 2686 Parameters: 2687 device : struct pci_dev 's device field 2688 2689 return 1 => TRUE 2690 0 => FALSE 2691 *******************************************************************/ 2692 static inline int 2693 lpfc_is_LC_HBA(unsigned short device) 2694 { 2695 if ((device == PCI_DEVICE_ID_TFLY) || 2696 (device == PCI_DEVICE_ID_PFLY) || 2697 (device == PCI_DEVICE_ID_LP101) || 2698 (device == PCI_DEVICE_ID_BMID) || 2699 (device == PCI_DEVICE_ID_BSMB) || 2700 (device == PCI_DEVICE_ID_ZMID) || 2701 (device == PCI_DEVICE_ID_ZSMB) || 2702 (device == PCI_DEVICE_ID_RFLY)) 2703 return 1; 2704 else 2705 return 0; 2706 } 2707