1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 #define LPFC_FCP_OAS_RING 3 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 uint32_t CmdRsp:16; 90 uint32_t Size:16; 91 } bits; 92 uint32_t word; 93 }; 94 95 #define FC4_FEATURE_INIT 0x2 96 #define FC4_FEATURE_TARGET 0x1 97 98 struct lpfc_sli_ct_request { 99 /* Structure is in Big Endian format */ 100 union CtRevisionId RevisionId; 101 uint8_t FsType; 102 uint8_t FsSubType; 103 uint8_t Options; 104 uint8_t Rsrvd1; 105 union CtCommandResponse CommandResponse; 106 uint8_t Rsrvd2; 107 uint8_t ReasonCode; 108 uint8_t Explanation; 109 uint8_t VendorUnique; 110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 111 112 union { 113 uint32_t PortID; 114 struct gid { 115 uint8_t PortType; /* for GID_PT requests */ 116 uint8_t DomainScope; 117 uint8_t AreaScope; 118 uint8_t Fc4Type; /* for GID_FT requests */ 119 } gid; 120 struct rft { 121 uint32_t PortId; /* For RFT_ID requests */ 122 123 #ifdef __BIG_ENDIAN_BITFIELD 124 uint32_t rsvd0:16; 125 uint32_t rsvd1:7; 126 uint32_t fcpReg:1; /* Type 8 */ 127 uint32_t rsvd2:2; 128 uint32_t ipReg:1; /* Type 5 */ 129 uint32_t rsvd3:5; 130 #else /* __LITTLE_ENDIAN_BITFIELD */ 131 uint32_t rsvd0:16; 132 uint32_t fcpReg:1; /* Type 8 */ 133 uint32_t rsvd1:7; 134 uint32_t rsvd3:5; 135 uint32_t ipReg:1; /* Type 5 */ 136 uint32_t rsvd2:2; 137 #endif 138 139 uint32_t rsvd[7]; 140 } rft; 141 struct rnn { 142 uint32_t PortId; /* For RNN_ID requests */ 143 uint8_t wwnn[8]; 144 } rnn; 145 struct rsnn { /* For RSNN_ID requests */ 146 uint8_t wwnn[8]; 147 uint8_t len; 148 uint8_t symbname[255]; 149 } rsnn; 150 struct da_id { /* For DA_ID requests */ 151 uint32_t port_id; 152 } da_id; 153 struct rspn { /* For RSPN_ID requests */ 154 uint32_t PortId; 155 uint8_t len; 156 uint8_t symbname[255]; 157 } rspn; 158 struct gff { 159 uint32_t PortId; 160 } gff; 161 struct gff_acc { 162 uint8_t fbits[128]; 163 } gff_acc; 164 #define FCP_TYPE_FEATURE_OFFSET 7 165 struct rff { 166 uint32_t PortId; 167 uint8_t reserved[2]; 168 uint8_t fbits; 169 uint8_t type_code; /* type=8 for FCP */ 170 } rff; 171 } un; 172 }; 173 174 #define LPFC_MAX_CT_SIZE (60 * 4096) 175 176 #define SLI_CT_REVISION 1 177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 178 sizeof(struct gid)) 179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 180 sizeof(struct gff)) 181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 182 sizeof(struct rft)) 183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 184 sizeof(struct rff)) 185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 186 sizeof(struct rnn)) 187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 188 sizeof(struct rsnn)) 189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 190 sizeof(struct da_id)) 191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 192 sizeof(struct rspn)) 193 194 /* 195 * FsType Definitions 196 */ 197 198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 199 #define SLI_CT_TIME_SERVICE 0xFB 200 #define SLI_CT_DIRECTORY_SERVICE 0xFC 201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 202 203 /* 204 * Directory Service Subtypes 205 */ 206 207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 208 209 /* 210 * Response Codes 211 */ 212 213 #define SLI_CT_RESPONSE_FS_RJT 0x8001 214 #define SLI_CT_RESPONSE_FS_ACC 0x8002 215 216 /* 217 * Reason Codes 218 */ 219 220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 221 #define SLI_CT_INVALID_COMMAND 0x01 222 #define SLI_CT_INVALID_VERSION 0x02 223 #define SLI_CT_LOGICAL_ERROR 0x03 224 #define SLI_CT_INVALID_IU_SIZE 0x04 225 #define SLI_CT_LOGICAL_BUSY 0x05 226 #define SLI_CT_PROTOCOL_ERROR 0x07 227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 236 #define SLI_CT_VENDOR_UNIQUE 0xff 237 238 /* 239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 240 */ 241 242 #define SLI_CT_NO_PORT_ID 0x01 243 #define SLI_CT_NO_PORT_NAME 0x02 244 #define SLI_CT_NO_NODE_NAME 0x03 245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 246 #define SLI_CT_NO_IP_ADDRESS 0x05 247 #define SLI_CT_NO_IPA 0x06 248 #define SLI_CT_NO_FC4_TYPES 0x07 249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 251 #define SLI_CT_NO_PORT_TYPE 0x0A 252 #define SLI_CT_ACCESS_DENIED 0x10 253 #define SLI_CT_INVALID_PORT_ID 0x11 254 #define SLI_CT_DATABASE_EMPTY 0x12 255 256 /* 257 * Name Server Command Codes 258 */ 259 260 #define SLI_CTNS_GA_NXT 0x0100 261 #define SLI_CTNS_GPN_ID 0x0112 262 #define SLI_CTNS_GNN_ID 0x0113 263 #define SLI_CTNS_GCS_ID 0x0114 264 #define SLI_CTNS_GFT_ID 0x0117 265 #define SLI_CTNS_GSPN_ID 0x0118 266 #define SLI_CTNS_GPT_ID 0x011A 267 #define SLI_CTNS_GFF_ID 0x011F 268 #define SLI_CTNS_GID_PN 0x0121 269 #define SLI_CTNS_GID_NN 0x0131 270 #define SLI_CTNS_GIP_NN 0x0135 271 #define SLI_CTNS_GIPA_NN 0x0136 272 #define SLI_CTNS_GSNN_NN 0x0139 273 #define SLI_CTNS_GNN_IP 0x0153 274 #define SLI_CTNS_GIPA_IP 0x0156 275 #define SLI_CTNS_GID_FT 0x0171 276 #define SLI_CTNS_GID_PT 0x01A1 277 #define SLI_CTNS_RPN_ID 0x0212 278 #define SLI_CTNS_RNN_ID 0x0213 279 #define SLI_CTNS_RCS_ID 0x0214 280 #define SLI_CTNS_RFT_ID 0x0217 281 #define SLI_CTNS_RSPN_ID 0x0218 282 #define SLI_CTNS_RPT_ID 0x021A 283 #define SLI_CTNS_RFF_ID 0x021F 284 #define SLI_CTNS_RIP_NN 0x0235 285 #define SLI_CTNS_RIPA_NN 0x0236 286 #define SLI_CTNS_RSNN_NN 0x0239 287 #define SLI_CTNS_DA_ID 0x0300 288 289 /* 290 * Port Types 291 */ 292 293 #define SLI_CTPT_N_PORT 0x01 294 #define SLI_CTPT_NL_PORT 0x02 295 #define SLI_CTPT_FNL_PORT 0x03 296 #define SLI_CTPT_IP 0x04 297 #define SLI_CTPT_FCP 0x08 298 #define SLI_CTPT_NX_PORT 0x7F 299 #define SLI_CTPT_F_PORT 0x81 300 #define SLI_CTPT_FL_PORT 0x82 301 #define SLI_CTPT_E_PORT 0x84 302 303 #define SLI_CT_LAST_ENTRY 0x80000000 304 305 /* Fibre Channel Service Parameter definitions */ 306 307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 311 312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 314 #define FC_PH3 0x20 /* FC-PH-3 version */ 315 316 #define FF_FRAME_SIZE 2048 317 318 struct lpfc_name { 319 union { 320 struct { 321 #ifdef __BIG_ENDIAN_BITFIELD 322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 324 8:11 of IEEE ext */ 325 #else /* __LITTLE_ENDIAN_BITFIELD */ 326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 327 8:11 of IEEE ext */ 328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 329 #endif 330 331 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 333 #define NAME_FC_TYPE 0x3 /* FC native name type */ 334 #define NAME_IP_TYPE 0x4 /* IP address */ 335 #define NAME_CCITT_TYPE 0xC 336 #define NAME_CCITT_GR_TYPE 0xE 337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 338 extended Lsb */ 339 uint8_t IEEE[6]; /* FC IEEE address */ 340 } s; 341 uint8_t wwn[8]; 342 } u; 343 }; 344 345 struct csp { 346 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 347 uint8_t fcphLow; 348 uint8_t bbCreditMsb; 349 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ 350 351 /* 352 * Word 1 Bit 31 in common service parameter is overloaded. 353 * Word 1 Bit 31 in FLOGI request is multiple NPort request 354 * Word 1 Bit 31 in FLOGI response is clean address bit 355 */ 356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 357 /* 358 * Word 1 Bit 30 in common service parameter is overloaded. 359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 360 * Word 1 Bit 30 in PLOGI request is random offset 361 */ 362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 363 /* 364 * Word 1 Bit 29 in common service parameter is overloaded. 365 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment 366 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level 367 */ 368 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ 369 #ifdef __BIG_ENDIAN_BITFIELD 370 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 371 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 372 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 373 uint16_t fPort:1; /* FC Word 1, bit 28 */ 374 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 375 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 376 uint16_t multicast:1; /* FC Word 1, bit 25 */ 377 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 378 379 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 380 uint16_t simplex:1; /* FC Word 1, bit 22 */ 381 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 382 uint16_t dhd:1; /* FC Word 1, bit 18 */ 383 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 384 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 385 #else /* __LITTLE_ENDIAN_BITFIELD */ 386 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 387 uint16_t multicast:1; /* FC Word 1, bit 25 */ 388 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 389 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 390 uint16_t fPort:1; /* FC Word 1, bit 28 */ 391 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 392 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 393 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 394 395 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 396 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 397 uint16_t dhd:1; /* FC Word 1, bit 18 */ 398 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 399 uint16_t simplex:1; /* FC Word 1, bit 22 */ 400 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 401 #endif 402 403 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 404 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 405 union { 406 struct { 407 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 408 409 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 410 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 411 412 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 413 } nPort; 414 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 415 } w2; 416 417 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 418 }; 419 420 struct class_parms { 421 #ifdef __BIG_ENDIAN_BITFIELD 422 uint8_t classValid:1; /* FC Word 0, bit 31 */ 423 uint8_t intermix:1; /* FC Word 0, bit 30 */ 424 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 426 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 427 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 428 #else /* __LITTLE_ENDIAN_BITFIELD */ 429 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 430 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 431 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 432 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 433 uint8_t intermix:1; /* FC Word 0, bit 30 */ 434 uint8_t classValid:1; /* FC Word 0, bit 31 */ 435 436 #endif 437 438 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 439 440 #ifdef __BIG_ENDIAN_BITFIELD 441 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 442 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 444 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 445 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 446 #else /* __LITTLE_ENDIAN_BITFIELD */ 447 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 448 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 449 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 450 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 451 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 452 #endif 453 454 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 455 456 #ifdef __BIG_ENDIAN_BITFIELD 457 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 458 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 459 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 461 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 462 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 463 #else /* __LITTLE_ENDIAN_BITFIELD */ 464 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 465 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 466 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 467 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 468 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 469 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 470 #endif 471 472 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 473 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 474 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 475 476 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 477 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 478 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 479 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 480 481 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 482 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 483 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 484 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 485 }; 486 487 struct serv_parm { /* Structure is in Big Endian format */ 488 struct csp cmn; 489 struct lpfc_name portName; 490 struct lpfc_name nodeName; 491 struct class_parms cls1; 492 struct class_parms cls2; 493 struct class_parms cls3; 494 struct class_parms cls4; 495 uint8_t vendorVersion[16]; 496 }; 497 498 /* 499 * Virtual Fabric Tagging Header 500 */ 501 struct fc_vft_header { 502 uint32_t word0; 503 #define fc_vft_hdr_r_ctl_SHIFT 24 504 #define fc_vft_hdr_r_ctl_MASK 0xFF 505 #define fc_vft_hdr_r_ctl_WORD word0 506 #define fc_vft_hdr_ver_SHIFT 22 507 #define fc_vft_hdr_ver_MASK 0x3 508 #define fc_vft_hdr_ver_WORD word0 509 #define fc_vft_hdr_type_SHIFT 18 510 #define fc_vft_hdr_type_MASK 0xF 511 #define fc_vft_hdr_type_WORD word0 512 #define fc_vft_hdr_e_SHIFT 16 513 #define fc_vft_hdr_e_MASK 0x1 514 #define fc_vft_hdr_e_WORD word0 515 #define fc_vft_hdr_priority_SHIFT 13 516 #define fc_vft_hdr_priority_MASK 0x7 517 #define fc_vft_hdr_priority_WORD word0 518 #define fc_vft_hdr_vf_id_SHIFT 1 519 #define fc_vft_hdr_vf_id_MASK 0xFFF 520 #define fc_vft_hdr_vf_id_WORD word0 521 uint32_t word1; 522 #define fc_vft_hdr_hopct_SHIFT 24 523 #define fc_vft_hdr_hopct_MASK 0xFF 524 #define fc_vft_hdr_hopct_WORD word1 525 }; 526 527 /* 528 * Extended Link Service LS_COMMAND codes (Payload Word 0) 529 */ 530 #ifdef __BIG_ENDIAN_BITFIELD 531 #define ELS_CMD_MASK 0xffff0000 532 #define ELS_RSP_MASK 0xff000000 533 #define ELS_CMD_LS_RJT 0x01000000 534 #define ELS_CMD_ACC 0x02000000 535 #define ELS_CMD_PLOGI 0x03000000 536 #define ELS_CMD_FLOGI 0x04000000 537 #define ELS_CMD_LOGO 0x05000000 538 #define ELS_CMD_ABTX 0x06000000 539 #define ELS_CMD_RCS 0x07000000 540 #define ELS_CMD_RES 0x08000000 541 #define ELS_CMD_RSS 0x09000000 542 #define ELS_CMD_RSI 0x0A000000 543 #define ELS_CMD_ESTS 0x0B000000 544 #define ELS_CMD_ESTC 0x0C000000 545 #define ELS_CMD_ADVC 0x0D000000 546 #define ELS_CMD_RTV 0x0E000000 547 #define ELS_CMD_RLS 0x0F000000 548 #define ELS_CMD_ECHO 0x10000000 549 #define ELS_CMD_TEST 0x11000000 550 #define ELS_CMD_RRQ 0x12000000 551 #define ELS_CMD_REC 0x13000000 552 #define ELS_CMD_RDP 0x18000000 553 #define ELS_CMD_PRLI 0x20100014 554 #define ELS_CMD_PRLO 0x21100014 555 #define ELS_CMD_PRLO_ACC 0x02100014 556 #define ELS_CMD_PDISC 0x50000000 557 #define ELS_CMD_FDISC 0x51000000 558 #define ELS_CMD_ADISC 0x52000000 559 #define ELS_CMD_FARP 0x54000000 560 #define ELS_CMD_FARPR 0x55000000 561 #define ELS_CMD_RPS 0x56000000 562 #define ELS_CMD_RPL 0x57000000 563 #define ELS_CMD_FAN 0x60000000 564 #define ELS_CMD_RSCN 0x61040000 565 #define ELS_CMD_SCR 0x62000000 566 #define ELS_CMD_RNID 0x78000000 567 #define ELS_CMD_LIRR 0x7A000000 568 #define ELS_CMD_LCB 0x81000000 569 #else /* __LITTLE_ENDIAN_BITFIELD */ 570 #define ELS_CMD_MASK 0xffff 571 #define ELS_RSP_MASK 0xff 572 #define ELS_CMD_LS_RJT 0x01 573 #define ELS_CMD_ACC 0x02 574 #define ELS_CMD_PLOGI 0x03 575 #define ELS_CMD_FLOGI 0x04 576 #define ELS_CMD_LOGO 0x05 577 #define ELS_CMD_ABTX 0x06 578 #define ELS_CMD_RCS 0x07 579 #define ELS_CMD_RES 0x08 580 #define ELS_CMD_RSS 0x09 581 #define ELS_CMD_RSI 0x0A 582 #define ELS_CMD_ESTS 0x0B 583 #define ELS_CMD_ESTC 0x0C 584 #define ELS_CMD_ADVC 0x0D 585 #define ELS_CMD_RTV 0x0E 586 #define ELS_CMD_RLS 0x0F 587 #define ELS_CMD_ECHO 0x10 588 #define ELS_CMD_TEST 0x11 589 #define ELS_CMD_RRQ 0x12 590 #define ELS_CMD_REC 0x13 591 #define ELS_CMD_RDP 0x18 592 #define ELS_CMD_PRLI 0x14001020 593 #define ELS_CMD_PRLO 0x14001021 594 #define ELS_CMD_PRLO_ACC 0x14001002 595 #define ELS_CMD_PDISC 0x50 596 #define ELS_CMD_FDISC 0x51 597 #define ELS_CMD_ADISC 0x52 598 #define ELS_CMD_FARP 0x54 599 #define ELS_CMD_FARPR 0x55 600 #define ELS_CMD_RPS 0x56 601 #define ELS_CMD_RPL 0x57 602 #define ELS_CMD_FAN 0x60 603 #define ELS_CMD_RSCN 0x0461 604 #define ELS_CMD_SCR 0x62 605 #define ELS_CMD_RNID 0x78 606 #define ELS_CMD_LIRR 0x7A 607 #define ELS_CMD_LCB 0x81 608 #endif 609 610 /* 611 * LS_RJT Payload Definition 612 */ 613 614 struct ls_rjt { /* Structure is in Big Endian format */ 615 union { 616 uint32_t lsRjtError; 617 struct { 618 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 619 620 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 621 /* LS_RJT reason codes */ 622 #define LSRJT_INVALID_CMD 0x01 623 #define LSRJT_LOGICAL_ERR 0x03 624 #define LSRJT_LOGICAL_BSY 0x05 625 #define LSRJT_PROTOCOL_ERR 0x07 626 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 627 #define LSRJT_CMD_UNSUPPORTED 0x0B 628 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 629 630 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 631 /* LS_RJT reason explanation */ 632 #define LSEXP_NOTHING_MORE 0x00 633 #define LSEXP_SPARM_OPTIONS 0x01 634 #define LSEXP_SPARM_ICTL 0x03 635 #define LSEXP_SPARM_RCTL 0x05 636 #define LSEXP_SPARM_RCV_SIZE 0x07 637 #define LSEXP_SPARM_CONCUR_SEQ 0x09 638 #define LSEXP_SPARM_CREDIT 0x0B 639 #define LSEXP_INVALID_PNAME 0x0D 640 #define LSEXP_INVALID_NNAME 0x0E 641 #define LSEXP_INVALID_CSP 0x0F 642 #define LSEXP_INVALID_ASSOC_HDR 0x11 643 #define LSEXP_ASSOC_HDR_REQ 0x13 644 #define LSEXP_INVALID_O_SID 0x15 645 #define LSEXP_INVALID_OX_RX 0x17 646 #define LSEXP_CMD_IN_PROGRESS 0x19 647 #define LSEXP_PORT_LOGIN_REQ 0x1E 648 #define LSEXP_INVALID_NPORT_ID 0x1F 649 #define LSEXP_INVALID_SEQ_ID 0x21 650 #define LSEXP_INVALID_XCHG 0x23 651 #define LSEXP_INACTIVE_XCHG 0x25 652 #define LSEXP_RQ_REQUIRED 0x27 653 #define LSEXP_OUT_OF_RESOURCE 0x29 654 #define LSEXP_CANT_GIVE_DATA 0x2A 655 #define LSEXP_REQ_UNSUPPORTED 0x2C 656 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 657 } b; 658 } un; 659 }; 660 661 /* 662 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 663 */ 664 665 typedef struct _LOGO { /* Structure is in Big Endian format */ 666 union { 667 uint32_t nPortId32; /* Access nPortId as a word */ 668 struct { 669 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 670 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 671 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 672 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 673 } b; 674 } un; 675 struct lpfc_name portName; /* N_port name field */ 676 } LOGO; 677 678 /* 679 * FCP Login (PRLI Request / ACC) Payload Definition 680 */ 681 682 #define PRLX_PAGE_LEN 0x10 683 #define TPRLO_PAGE_LEN 0x14 684 685 typedef struct _PRLI { /* Structure is in Big Endian format */ 686 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 687 688 #define PRLI_FCP_TYPE 0x08 689 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 690 691 #ifdef __BIG_ENDIAN_BITFIELD 692 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 693 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 694 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 695 696 /* ACC = imagePairEstablished */ 697 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 698 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 699 #else /* __LITTLE_ENDIAN_BITFIELD */ 700 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 701 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 702 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 703 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 704 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 705 /* ACC = imagePairEstablished */ 706 #endif 707 708 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 709 #define PRLI_NO_RESOURCES 0x2 710 #define PRLI_INIT_INCOMPLETE 0x3 711 #define PRLI_NO_SUCH_PA 0x4 712 #define PRLI_PREDEF_CONFIG 0x5 713 #define PRLI_PARTIAL_SUCCESS 0x6 714 #define PRLI_INVALID_PAGE_CNT 0x7 715 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 716 717 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 718 719 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 720 721 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 722 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 723 724 #ifdef __BIG_ENDIAN_BITFIELD 725 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 726 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 727 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 728 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 729 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 730 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 731 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 732 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 733 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 734 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 735 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 736 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 737 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 738 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 739 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 740 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 741 #else /* __LITTLE_ENDIAN_BITFIELD */ 742 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 743 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 744 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 745 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 746 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 747 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 748 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 749 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 750 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 751 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 752 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 753 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 754 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 755 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 756 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 757 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 758 #endif 759 } PRLI; 760 761 /* 762 * FCP Logout (PRLO Request / ACC) Payload Definition 763 */ 764 765 typedef struct _PRLO { /* Structure is in Big Endian format */ 766 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 767 768 #define PRLO_FCP_TYPE 0x08 769 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 770 771 #ifdef __BIG_ENDIAN_BITFIELD 772 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 774 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 775 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 776 #else /* __LITTLE_ENDIAN_BITFIELD */ 777 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 778 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 779 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 780 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 781 #endif 782 783 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 784 #define PRLO_NO_SUCH_IMAGE 0x4 785 #define PRLO_INVALID_PAGE_CNT 0x7 786 787 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 788 789 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 790 791 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 792 793 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 794 } PRLO; 795 796 typedef struct _ADISC { /* Structure is in Big Endian format */ 797 uint32_t hardAL_PA; 798 struct lpfc_name portName; 799 struct lpfc_name nodeName; 800 uint32_t DID; 801 } ADISC; 802 803 typedef struct _FARP { /* Structure is in Big Endian format */ 804 uint32_t Mflags:8; 805 uint32_t Odid:24; 806 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 807 action */ 808 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 809 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 810 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 811 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 812 supported */ 813 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 814 supported */ 815 uint32_t Rflags:8; 816 uint32_t Rdid:24; 817 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 818 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 819 struct lpfc_name OportName; 820 struct lpfc_name OnodeName; 821 struct lpfc_name RportName; 822 struct lpfc_name RnodeName; 823 uint8_t Oipaddr[16]; 824 uint8_t Ripaddr[16]; 825 } FARP; 826 827 typedef struct _FAN { /* Structure is in Big Endian format */ 828 uint32_t Fdid; 829 struct lpfc_name FportName; 830 struct lpfc_name FnodeName; 831 } FAN; 832 833 typedef struct _SCR { /* Structure is in Big Endian format */ 834 uint8_t resvd1; 835 uint8_t resvd2; 836 uint8_t resvd3; 837 uint8_t Function; 838 #define SCR_FUNC_FABRIC 0x01 839 #define SCR_FUNC_NPORT 0x02 840 #define SCR_FUNC_FULL 0x03 841 #define SCR_CLEAR 0xff 842 } SCR; 843 844 typedef struct _RNID_TOP_DISC { 845 struct lpfc_name portName; 846 uint8_t resvd[8]; 847 uint32_t unitType; 848 #define RNID_HBA 0x7 849 #define RNID_HOST 0xa 850 #define RNID_DRIVER 0xd 851 uint32_t physPort; 852 uint32_t attachedNodes; 853 uint16_t ipVersion; 854 #define RNID_IPV4 0x1 855 #define RNID_IPV6 0x2 856 uint16_t UDPport; 857 uint8_t ipAddr[16]; 858 uint16_t resvd1; 859 uint16_t flags; 860 #define RNID_TD_SUPPORT 0x1 861 #define RNID_LP_VALID 0x2 862 } RNID_TOP_DISC; 863 864 typedef struct _RNID { /* Structure is in Big Endian format */ 865 uint8_t Format; 866 #define RNID_TOPOLOGY_DISC 0xdf 867 uint8_t CommonLen; 868 uint8_t resvd1; 869 uint8_t SpecificLen; 870 struct lpfc_name portName; 871 struct lpfc_name nodeName; 872 union { 873 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 874 } un; 875 } RNID; 876 877 typedef struct _RPS { /* Structure is in Big Endian format */ 878 union { 879 uint32_t portNum; 880 struct lpfc_name portName; 881 } un; 882 } RPS; 883 884 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 885 uint16_t rsvd1; 886 uint16_t portStatus; 887 uint32_t linkFailureCnt; 888 uint32_t lossSyncCnt; 889 uint32_t lossSignalCnt; 890 uint32_t primSeqErrCnt; 891 uint32_t invalidXmitWord; 892 uint32_t crcCnt; 893 } RPS_RSP; 894 895 struct RLS { /* Structure is in Big Endian format */ 896 uint32_t rls; 897 #define rls_rsvd_SHIFT 24 898 #define rls_rsvd_MASK 0x000000ff 899 #define rls_rsvd_WORD rls 900 #define rls_did_SHIFT 0 901 #define rls_did_MASK 0x00ffffff 902 #define rls_did_WORD rls 903 }; 904 905 struct RLS_RSP { /* Structure is in Big Endian format */ 906 uint32_t linkFailureCnt; 907 uint32_t lossSyncCnt; 908 uint32_t lossSignalCnt; 909 uint32_t primSeqErrCnt; 910 uint32_t invalidXmitWord; 911 uint32_t crcCnt; 912 }; 913 914 struct RRQ { /* Structure is in Big Endian format */ 915 uint32_t rrq; 916 #define rrq_rsvd_SHIFT 24 917 #define rrq_rsvd_MASK 0x000000ff 918 #define rrq_rsvd_WORD rrq 919 #define rrq_did_SHIFT 0 920 #define rrq_did_MASK 0x00ffffff 921 #define rrq_did_WORD rrq 922 uint32_t rrq_exchg; 923 #define rrq_oxid_SHIFT 16 924 #define rrq_oxid_MASK 0xffff 925 #define rrq_oxid_WORD rrq_exchg 926 #define rrq_rxid_SHIFT 0 927 #define rrq_rxid_MASK 0xffff 928 #define rrq_rxid_WORD rrq_exchg 929 }; 930 931 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 932 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 933 934 struct RTV_RSP { /* Structure is in Big Endian format */ 935 uint32_t ratov; 936 uint32_t edtov; 937 uint32_t qtov; 938 #define qtov_rsvd0_SHIFT 28 939 #define qtov_rsvd0_MASK 0x0000000f 940 #define qtov_rsvd0_WORD qtov /* reserved */ 941 #define qtov_edtovres_SHIFT 27 942 #define qtov_edtovres_MASK 0x00000001 943 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 944 #define qtov__rsvd1_SHIFT 19 945 #define qtov_rsvd1_MASK 0x0000003f 946 #define qtov_rsvd1_WORD qtov /* reserved */ 947 #define qtov_rttov_SHIFT 18 948 #define qtov_rttov_MASK 0x00000001 949 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 950 #define qtov_rsvd2_SHIFT 0 951 #define qtov_rsvd2_MASK 0x0003ffff 952 #define qtov_rsvd2_WORD qtov /* reserved */ 953 }; 954 955 956 typedef struct _RPL { /* Structure is in Big Endian format */ 957 uint32_t maxsize; 958 uint32_t index; 959 } RPL; 960 961 typedef struct _PORT_NUM_BLK { 962 uint32_t portNum; 963 uint32_t portID; 964 struct lpfc_name portName; 965 } PORT_NUM_BLK; 966 967 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 968 uint32_t listLen; 969 uint32_t index; 970 PORT_NUM_BLK port_num_blk; 971 } RPL_RSP; 972 973 /* This is used for RSCN command */ 974 typedef struct _D_ID { /* Structure is in Big Endian format */ 975 union { 976 uint32_t word; 977 struct { 978 #ifdef __BIG_ENDIAN_BITFIELD 979 uint8_t resv; 980 uint8_t domain; 981 uint8_t area; 982 uint8_t id; 983 #else /* __LITTLE_ENDIAN_BITFIELD */ 984 uint8_t id; 985 uint8_t area; 986 uint8_t domain; 987 uint8_t resv; 988 #endif 989 } b; 990 } un; 991 } D_ID; 992 993 #define RSCN_ADDRESS_FORMAT_PORT 0x0 994 #define RSCN_ADDRESS_FORMAT_AREA 0x1 995 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 996 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 997 #define RSCN_ADDRESS_FORMAT_MASK 0x3 998 999 /* 1000 * Structure to define all ELS Payload types 1001 */ 1002 1003 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1004 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1005 uint8_t elsByte1; 1006 uint8_t elsByte2; 1007 uint8_t elsByte3; 1008 union { 1009 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1010 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1011 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1012 PRLI prli; /* Payload for PRLI/ACC */ 1013 PRLO prlo; /* Payload for PRLO/ACC */ 1014 ADISC adisc; /* Payload for ADISC/ACC */ 1015 FARP farp; /* Payload for FARP/ACC */ 1016 FAN fan; /* Payload for FAN */ 1017 SCR scr; /* Payload for SCR/ACC */ 1018 RNID rnid; /* Payload for RNID */ 1019 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1020 } un; 1021 } ELS_PKT; 1022 1023 /* 1024 * Link Cable Beacon (LCB) ELS Frame 1025 */ 1026 1027 struct fc_lcb_request_frame { 1028 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1029 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1030 #define LPFC_LCB_ON 0x1 1031 #define LPFC_LCB_OFF 0x2 1032 uint8_t reserved[3]; 1033 1034 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1035 #define LPFC_LCB_GREEN 0x1 1036 #define LPFC_LCB_AMBER 0x2 1037 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1038 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1039 }; 1040 1041 /* 1042 * Link Cable Beacon (LCB) ELS Response Frame 1043 */ 1044 struct fc_lcb_res_frame { 1045 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1046 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1047 uint8_t reserved[3]; 1048 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1049 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1050 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1051 }; 1052 1053 /* 1054 * Read Diagnostic Parameters (RDP) ELS frame. 1055 */ 1056 #define SFF_PG0_IDENT_SFP 0x3 1057 1058 #define SFP_FLAG_PT_OPTICAL 0x0 1059 #define SFP_FLAG_PT_SWLASER 0x01 1060 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1061 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1062 #define SFP_FLAG_PT_MASK 0x0F 1063 #define SFP_FLAG_PT_SHIFT 0 1064 1065 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1066 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1067 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1068 1069 #define SFP_FLAG_IS_DESC_VALID 0x01 1070 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1071 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1072 1073 #define SFP_FLAG_CT_UNKNOWN 0x0 1074 #define SFP_FLAG_CT_SFP_PLUS 0x01 1075 #define SFP_FLAG_CT_MASK 0x3C 1076 #define SFP_FLAG_CT_SHIFT 6 1077 1078 struct fc_rdp_port_name_info { 1079 uint8_t wwnn[8]; 1080 uint8_t wwpn[8]; 1081 }; 1082 1083 1084 /* 1085 * Link Error Status Block Structure (FC-FS-3) for RDP 1086 * This similar to RPS ELS 1087 */ 1088 struct fc_link_status { 1089 uint32_t link_failure_cnt; 1090 uint32_t loss_of_synch_cnt; 1091 uint32_t loss_of_signal_cnt; 1092 uint32_t primitive_seq_proto_err; 1093 uint32_t invalid_trans_word; 1094 uint32_t invalid_crc_cnt; 1095 1096 }; 1097 1098 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1099 struct fc_rdp_port_name_desc { 1100 uint32_t tag; /* 0001 0003h */ 1101 uint32_t length; /* set to size of payload struct */ 1102 struct fc_rdp_port_name_info port_names; 1103 }; 1104 1105 1106 struct fc_rdp_fec_info { 1107 uint32_t CorrectedBlocks; 1108 uint32_t UncorrectableBlocks; 1109 }; 1110 1111 #define RDP_FEC_DESC_TAG 0x00010005 1112 struct fc_fec_rdp_desc { 1113 uint32_t tag; 1114 uint32_t length; 1115 struct fc_rdp_fec_info info; 1116 }; 1117 1118 struct fc_rdp_link_error_status_payload_info { 1119 struct fc_link_status link_status; /* 24 bytes */ 1120 uint32_t port_type; /* bits 31-30 only */ 1121 }; 1122 1123 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1124 struct fc_rdp_link_error_status_desc { 1125 uint32_t tag; /* 0001 0002h */ 1126 uint32_t length; /* set to size of payload struct */ 1127 struct fc_rdp_link_error_status_payload_info info; 1128 }; 1129 1130 #define VN_PT_PHY_UNKNOWN 0x00 1131 #define VN_PT_PHY_PF_PORT 0x01 1132 #define VN_PT_PHY_ETH_MAC 0x10 1133 #define VN_PT_PHY_SHIFT 30 1134 1135 #define RDP_PS_1GB 0x8000 1136 #define RDP_PS_2GB 0x4000 1137 #define RDP_PS_4GB 0x2000 1138 #define RDP_PS_10GB 0x1000 1139 #define RDP_PS_8GB 0x0800 1140 #define RDP_PS_16GB 0x0400 1141 #define RDP_PS_32GB 0x0200 1142 1143 #define RDP_CAP_USER_CONFIGURED 0x0002 1144 #define RDP_CAP_UNKNOWN 0x0001 1145 #define RDP_PS_UNKNOWN 0x0002 1146 #define RDP_PS_NOT_ESTABLISHED 0x0001 1147 1148 struct fc_rdp_port_speed { 1149 uint16_t capabilities; 1150 uint16_t speed; 1151 }; 1152 1153 struct fc_rdp_port_speed_info { 1154 struct fc_rdp_port_speed port_speed; 1155 }; 1156 1157 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1158 struct fc_rdp_port_speed_desc { 1159 uint32_t tag; /* 00010001h */ 1160 uint32_t length; /* set to size of payload struct */ 1161 struct fc_rdp_port_speed_info info; 1162 }; 1163 1164 #define RDP_NPORT_ID_SIZE 4 1165 #define RDP_N_PORT_DESC_TAG 0x00000003 1166 struct fc_rdp_nport_desc { 1167 uint32_t tag; /* 0000 0003h, big endian */ 1168 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1169 uint32_t nport_id : 12; 1170 uint32_t reserved : 8; 1171 }; 1172 1173 1174 struct fc_rdp_link_service_info { 1175 uint32_t els_req; /* Request payload word 0 value.*/ 1176 }; 1177 1178 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1179 struct fc_rdp_link_service_desc { 1180 uint32_t tag; /* Descriptor tag 1 */ 1181 uint32_t length; /* set to size of payload struct. */ 1182 struct fc_rdp_link_service_info payload; 1183 /* must be ELS req Word 0(0x18) */ 1184 }; 1185 1186 struct fc_rdp_sfp_info { 1187 uint16_t temperature; 1188 uint16_t vcc; 1189 uint16_t tx_bias; 1190 uint16_t tx_power; 1191 uint16_t rx_power; 1192 uint16_t flags; 1193 }; 1194 1195 #define RDP_SFP_DESC_TAG 0x00010000 1196 struct fc_rdp_sfp_desc { 1197 uint32_t tag; 1198 uint32_t length; /* set to size of sfp_info struct */ 1199 struct fc_rdp_sfp_info sfp_info; 1200 }; 1201 1202 /* Buffer Credit Descriptor */ 1203 struct fc_rdp_bbc_info { 1204 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1205 uint32_t attached_port_bbc; 1206 uint32_t rtt; /* Round trip time */ 1207 }; 1208 #define RDP_BBC_DESC_TAG 0x00010006 1209 struct fc_rdp_bbc_desc { 1210 uint32_t tag; 1211 uint32_t length; 1212 struct fc_rdp_bbc_info bbc_info; 1213 }; 1214 1215 /* Optical Element Type Transgression Flags */ 1216 #define RDP_OET_LOW_WARNING 0x1 1217 #define RDP_OET_HIGH_WARNING 0x2 1218 #define RDP_OET_LOW_ALARM 0x4 1219 #define RDP_OET_HIGH_ALARM 0x8 1220 1221 #define RDP_OED_TEMPERATURE 0x1 1222 #define RDP_OED_VOLTAGE 0x2 1223 #define RDP_OED_TXBIAS 0x3 1224 #define RDP_OED_TXPOWER 0x4 1225 #define RDP_OED_RXPOWER 0x5 1226 1227 #define RDP_OED_TYPE_SHIFT 28 1228 /* Optical Element Data descriptor */ 1229 struct fc_rdp_oed_info { 1230 uint16_t hi_alarm; 1231 uint16_t lo_alarm; 1232 uint16_t hi_warning; 1233 uint16_t lo_warning; 1234 uint32_t function_flags; 1235 }; 1236 #define RDP_OED_DESC_TAG 0x00010007 1237 struct fc_rdp_oed_sfp_desc { 1238 uint32_t tag; 1239 uint32_t length; 1240 struct fc_rdp_oed_info oed_info; 1241 }; 1242 1243 /* Optical Product Data descriptor */ 1244 struct fc_rdp_opd_sfp_info { 1245 uint8_t vendor_name[16]; 1246 uint8_t model_number[16]; 1247 uint8_t serial_number[16]; 1248 uint8_t revision[2]; 1249 uint8_t reserved[2]; 1250 uint8_t date[8]; 1251 }; 1252 1253 #define RDP_OPD_DESC_TAG 0x00010008 1254 struct fc_rdp_opd_sfp_desc { 1255 uint32_t tag; 1256 uint32_t length; 1257 struct fc_rdp_opd_sfp_info opd_info; 1258 }; 1259 1260 struct fc_rdp_req_frame { 1261 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1262 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1263 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1264 }; 1265 1266 1267 struct fc_rdp_res_frame { 1268 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1269 uint32_t length; /* FC Word 1 */ 1270 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1271 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1272 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */ 1273 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */ 1274 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */ 1275 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */ 1276 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ 1277 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ 1278 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ 1279 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ 1280 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ 1281 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ 1282 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ 1283 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ 1284 }; 1285 1286 1287 /******** FDMI ********/ 1288 1289 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1290 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1291 1292 /* 1293 * Registered Port List Format 1294 */ 1295 struct lpfc_fdmi_reg_port_list { 1296 uint32_t EntryCnt; 1297 uint32_t pe; /* Variable-length array */ 1298 }; 1299 1300 1301 /* Definitions for HBA / Port attribute entries */ 1302 1303 struct lpfc_fdmi_attr_def { /* Defined in TLV format */ 1304 /* Structure is in Big Endian format */ 1305 uint32_t AttrType:16; 1306 uint32_t AttrLen:16; 1307 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */ 1308 }; 1309 1310 1311 /* Attribute Entry */ 1312 struct lpfc_fdmi_attr_entry { 1313 union { 1314 uint32_t AttrInt; 1315 uint8_t AttrTypes[32]; 1316 uint8_t AttrString[256]; 1317 struct lpfc_name AttrWWN; 1318 } un; 1319 }; 1320 1321 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry) 1322 1323 /* 1324 * HBA Attribute Block 1325 */ 1326 struct lpfc_fdmi_attr_block { 1327 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1328 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */ 1329 }; 1330 1331 /* 1332 * Port Entry 1333 */ 1334 struct lpfc_fdmi_port_entry { 1335 struct lpfc_name PortName; 1336 }; 1337 1338 /* 1339 * HBA Identifier 1340 */ 1341 struct lpfc_fdmi_hba_ident { 1342 struct lpfc_name PortName; 1343 }; 1344 1345 /* 1346 * Register HBA(RHBA) 1347 */ 1348 struct lpfc_fdmi_reg_hba { 1349 struct lpfc_fdmi_hba_ident hi; 1350 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */ 1351 /* struct lpfc_fdmi_attr_block ab; */ 1352 }; 1353 1354 /* 1355 * Register HBA Attributes (RHAT) 1356 */ 1357 struct lpfc_fdmi_reg_hbaattr { 1358 struct lpfc_name HBA_PortName; 1359 struct lpfc_fdmi_attr_block ab; 1360 }; 1361 1362 /* 1363 * Register Port Attributes (RPA) 1364 */ 1365 struct lpfc_fdmi_reg_portattr { 1366 struct lpfc_name PortName; 1367 struct lpfc_fdmi_attr_block ab; 1368 }; 1369 1370 /* 1371 * HBA MAnagement Operations Command Codes 1372 */ 1373 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1374 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1375 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1376 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1377 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1378 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1379 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1380 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1381 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1382 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1383 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1384 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1385 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1386 1387 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1388 1389 /* 1390 * HBA Attribute Types 1391 */ 1392 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1393 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1394 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1395 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1396 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1397 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1398 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1399 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1400 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1401 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1402 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1403 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1404 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1405 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1406 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1407 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1408 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1409 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1410 1411 /* Bit mask for all individual HBA attributes */ 1412 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1413 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1414 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1415 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1416 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1417 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1418 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1419 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1420 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1421 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1422 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1423 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1424 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1425 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1426 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1427 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1428 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1429 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1430 1431 /* Bit mask for FDMI-1 defined HBA attributes */ 1432 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1433 1434 /* Bit mask for FDMI-2 defined HBA attributes */ 1435 /* Skip vendor_info and bios_state */ 1436 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1437 1438 /* 1439 * Port Attrubute Types 1440 */ 1441 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1442 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1443 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1444 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1445 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1446 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1447 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1448 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1449 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1450 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1451 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1452 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1453 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1454 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1455 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1456 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1457 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1458 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1459 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1460 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1461 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1462 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1463 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1464 1465 /* Bit mask for all individual PORT attributes */ 1466 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1467 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1468 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1469 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1470 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1471 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1472 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1473 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1474 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1475 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1476 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1477 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1478 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1479 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1480 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1481 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1482 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1483 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1484 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1485 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1486 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1487 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1488 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1489 1490 /* Bit mask for FDMI-1 defined PORT attributes */ 1491 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1492 1493 /* Bit mask for FDMI-2 defined PORT attributes */ 1494 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1495 1496 /* Bit mask for Smart SAN defined PORT attributes */ 1497 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1498 1499 /* Defines for PORT port state attribute */ 1500 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1501 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1502 1503 /* Defines for PORT port type attribute */ 1504 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1505 #define LPFC_FDMI_PORTTYPE_NPORT 1 1506 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1507 1508 /* 1509 * Begin HBA configuration parameters. 1510 * The PCI configuration register BAR assignments are: 1511 * BAR0, offset 0x10 - SLIM base memory address 1512 * BAR1, offset 0x14 - SLIM base memory high address 1513 * BAR2, offset 0x18 - REGISTER base memory address 1514 * BAR3, offset 0x1c - REGISTER base memory high address 1515 * BAR4, offset 0x20 - BIU I/O registers 1516 * BAR5, offset 0x24 - REGISTER base io high address 1517 */ 1518 1519 /* Number of rings currently used and available. */ 1520 #define MAX_SLI3_CONFIGURED_RINGS 3 1521 #define MAX_SLI3_RINGS 4 1522 1523 /* IOCB / Mailbox is owned by FireFly */ 1524 #define OWN_CHIP 1 1525 1526 /* IOCB / Mailbox is owned by Host */ 1527 #define OWN_HOST 0 1528 1529 /* Number of 4-byte words in an IOCB. */ 1530 #define IOCB_WORD_SZ 8 1531 1532 /* network headers for Dfctl field */ 1533 #define FC_NET_HDR 0x20 1534 1535 /* Start FireFly Register definitions */ 1536 #define PCI_VENDOR_ID_EMULEX 0x10df 1537 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1538 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1539 #define PCI_DEVICE_ID_BALIUS 0xe131 1540 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1541 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1542 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1543 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1544 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1545 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1546 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1547 #define PCI_DEVICE_ID_SAT_MID 0xf015 1548 #define PCI_DEVICE_ID_RFLY 0xf095 1549 #define PCI_DEVICE_ID_PFLY 0xf098 1550 #define PCI_DEVICE_ID_LP101 0xf0a1 1551 #define PCI_DEVICE_ID_TFLY 0xf0a5 1552 #define PCI_DEVICE_ID_BSMB 0xf0d1 1553 #define PCI_DEVICE_ID_BMID 0xf0d5 1554 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1555 #define PCI_DEVICE_ID_ZMID 0xf0e5 1556 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1557 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1558 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1559 #define PCI_DEVICE_ID_SAT 0xf100 1560 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1561 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1562 #define PCI_DEVICE_ID_FALCON 0xf180 1563 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1564 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1565 #define PCI_DEVICE_ID_CENTAUR 0xf900 1566 #define PCI_DEVICE_ID_PEGASUS 0xf980 1567 #define PCI_DEVICE_ID_THOR 0xfa00 1568 #define PCI_DEVICE_ID_VIPER 0xfb00 1569 #define PCI_DEVICE_ID_LP10000S 0xfc00 1570 #define PCI_DEVICE_ID_LP11000S 0xfc10 1571 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1572 #define PCI_DEVICE_ID_SAT_S 0xfc40 1573 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1574 #define PCI_DEVICE_ID_HELIOS 0xfd00 1575 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1576 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1577 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1578 #define PCI_DEVICE_ID_HORNET 0xfe05 1579 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1580 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1581 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1582 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1583 #define PCI_DEVICE_ID_TOMCAT 0x0714 1584 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1585 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1586 1587 #define JEDEC_ID_ADDRESS 0x0080001c 1588 #define FIREFLY_JEDEC_ID 0x1ACC 1589 #define SUPERFLY_JEDEC_ID 0x0020 1590 #define DRAGONFLY_JEDEC_ID 0x0021 1591 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1592 #define CENTAUR_2G_JEDEC_ID 0x0026 1593 #define CENTAUR_1G_JEDEC_ID 0x0028 1594 #define PEGASUS_ORION_JEDEC_ID 0x0036 1595 #define PEGASUS_JEDEC_ID 0x0038 1596 #define THOR_JEDEC_ID 0x0012 1597 #define HELIOS_JEDEC_ID 0x0364 1598 #define ZEPHYR_JEDEC_ID 0x0577 1599 #define VIPER_JEDEC_ID 0x4838 1600 #define SATURN_JEDEC_ID 0x1004 1601 #define HORNET_JDEC_ID 0x2057706D 1602 1603 #define JEDEC_ID_MASK 0x0FFFF000 1604 #define JEDEC_ID_SHIFT 12 1605 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1606 1607 typedef struct { /* FireFly BIU registers */ 1608 uint32_t hostAtt; /* See definitions for Host Attention 1609 register */ 1610 uint32_t chipAtt; /* See definitions for Chip Attention 1611 register */ 1612 uint32_t hostStatus; /* See definitions for Host Status register */ 1613 uint32_t hostControl; /* See definitions for Host Control register */ 1614 uint32_t buiConfig; /* See definitions for BIU configuration 1615 register */ 1616 } FF_REGS; 1617 1618 /* IO Register size in bytes */ 1619 #define FF_REG_AREA_SIZE 256 1620 1621 /* Host Attention Register */ 1622 1623 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1624 1625 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1626 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1627 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1628 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1629 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1630 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1631 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1632 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1633 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1634 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1635 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1636 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1637 #define HA_LATT 0x20000000 /* Bit 29 */ 1638 #define HA_MBATT 0x40000000 /* Bit 30 */ 1639 #define HA_ERATT 0x80000000 /* Bit 31 */ 1640 1641 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1642 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1643 #define HA_RXATT 0x00000008 /* Bit 3 */ 1644 #define HA_RXMASK 0x0000000f 1645 1646 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1647 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1648 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1649 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1650 1651 #define HA_R0_POS 3 1652 #define HA_R1_POS 7 1653 #define HA_R2_POS 11 1654 #define HA_R3_POS 15 1655 #define HA_LE_POS 29 1656 #define HA_MB_POS 30 1657 #define HA_ER_POS 31 1658 /* Chip Attention Register */ 1659 1660 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1661 1662 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1663 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1664 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1665 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1666 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1667 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1668 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1669 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1670 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1671 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1672 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1673 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1674 #define CA_MBATT 0x40000000 /* Bit 30 */ 1675 1676 /* Host Status Register */ 1677 1678 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1679 1680 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1681 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1682 #define HS_FFER8 0x01000000 /* Bit 24 */ 1683 #define HS_FFER7 0x02000000 /* Bit 25 */ 1684 #define HS_FFER6 0x04000000 /* Bit 26 */ 1685 #define HS_FFER5 0x08000000 /* Bit 27 */ 1686 #define HS_FFER4 0x10000000 /* Bit 28 */ 1687 #define HS_FFER3 0x20000000 /* Bit 29 */ 1688 #define HS_FFER2 0x40000000 /* Bit 30 */ 1689 #define HS_FFER1 0x80000000 /* Bit 31 */ 1690 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1691 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1692 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1693 /* Host Control Register */ 1694 1695 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1696 1697 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1698 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1699 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1700 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1701 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1702 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1703 #define HC_INITMB 0x04000000 /* Bit 26 */ 1704 #define HC_INITFF 0x08000000 /* Bit 27 */ 1705 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1706 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1707 1708 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1709 #define MSIX_DFLT_ID 0 1710 #define MSIX_RNG0_ID 0 1711 #define MSIX_RNG1_ID 1 1712 #define MSIX_RNG2_ID 2 1713 #define MSIX_RNG3_ID 3 1714 1715 #define MSIX_LINK_ID 4 1716 #define MSIX_MBOX_ID 5 1717 1718 #define MSIX_SPARE0_ID 6 1719 #define MSIX_SPARE1_ID 7 1720 1721 /* Mailbox Commands */ 1722 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1723 #define MBX_LOAD_SM 0x01 1724 #define MBX_READ_NV 0x02 1725 #define MBX_WRITE_NV 0x03 1726 #define MBX_RUN_BIU_DIAG 0x04 1727 #define MBX_INIT_LINK 0x05 1728 #define MBX_DOWN_LINK 0x06 1729 #define MBX_CONFIG_LINK 0x07 1730 #define MBX_CONFIG_RING 0x09 1731 #define MBX_RESET_RING 0x0A 1732 #define MBX_READ_CONFIG 0x0B 1733 #define MBX_READ_RCONFIG 0x0C 1734 #define MBX_READ_SPARM 0x0D 1735 #define MBX_READ_STATUS 0x0E 1736 #define MBX_READ_RPI 0x0F 1737 #define MBX_READ_XRI 0x10 1738 #define MBX_READ_REV 0x11 1739 #define MBX_READ_LNK_STAT 0x12 1740 #define MBX_REG_LOGIN 0x13 1741 #define MBX_UNREG_LOGIN 0x14 1742 #define MBX_CLEAR_LA 0x16 1743 #define MBX_DUMP_MEMORY 0x17 1744 #define MBX_DUMP_CONTEXT 0x18 1745 #define MBX_RUN_DIAGS 0x19 1746 #define MBX_RESTART 0x1A 1747 #define MBX_UPDATE_CFG 0x1B 1748 #define MBX_DOWN_LOAD 0x1C 1749 #define MBX_DEL_LD_ENTRY 0x1D 1750 #define MBX_RUN_PROGRAM 0x1E 1751 #define MBX_SET_MASK 0x20 1752 #define MBX_SET_VARIABLE 0x21 1753 #define MBX_UNREG_D_ID 0x23 1754 #define MBX_KILL_BOARD 0x24 1755 #define MBX_CONFIG_FARP 0x25 1756 #define MBX_BEACON 0x2A 1757 #define MBX_CONFIG_MSI 0x30 1758 #define MBX_HEARTBEAT 0x31 1759 #define MBX_WRITE_VPARMS 0x32 1760 #define MBX_ASYNCEVT_ENABLE 0x33 1761 #define MBX_READ_EVENT_LOG_STATUS 0x37 1762 #define MBX_READ_EVENT_LOG 0x38 1763 #define MBX_WRITE_EVENT_LOG 0x39 1764 1765 #define MBX_PORT_CAPABILITIES 0x3B 1766 #define MBX_PORT_IOV_CONTROL 0x3C 1767 1768 #define MBX_CONFIG_HBQ 0x7C 1769 #define MBX_LOAD_AREA 0x81 1770 #define MBX_RUN_BIU_DIAG64 0x84 1771 #define MBX_CONFIG_PORT 0x88 1772 #define MBX_READ_SPARM64 0x8D 1773 #define MBX_READ_RPI64 0x8F 1774 #define MBX_REG_LOGIN64 0x93 1775 #define MBX_READ_TOPOLOGY 0x95 1776 #define MBX_REG_VPI 0x96 1777 #define MBX_UNREG_VPI 0x97 1778 1779 #define MBX_WRITE_WWN 0x98 1780 #define MBX_SET_DEBUG 0x99 1781 #define MBX_LOAD_EXP_ROM 0x9C 1782 #define MBX_SLI4_CONFIG 0x9B 1783 #define MBX_SLI4_REQ_FTRS 0x9D 1784 #define MBX_MAX_CMDS 0x9E 1785 #define MBX_RESUME_RPI 0x9E 1786 #define MBX_SLI2_CMD_MASK 0x80 1787 #define MBX_REG_VFI 0x9F 1788 #define MBX_REG_FCFI 0xA0 1789 #define MBX_UNREG_VFI 0xA1 1790 #define MBX_UNREG_FCFI 0xA2 1791 #define MBX_INIT_VFI 0xA3 1792 #define MBX_INIT_VPI 0xA4 1793 #define MBX_ACCESS_VDATA 0xA5 1794 1795 #define MBX_AUTH_PORT 0xF8 1796 #define MBX_SECURITY_MGMT 0xF9 1797 1798 /* IOCB Commands */ 1799 1800 #define CMD_RCV_SEQUENCE_CX 0x01 1801 #define CMD_XMIT_SEQUENCE_CR 0x02 1802 #define CMD_XMIT_SEQUENCE_CX 0x03 1803 #define CMD_XMIT_BCAST_CN 0x04 1804 #define CMD_XMIT_BCAST_CX 0x05 1805 #define CMD_QUE_RING_BUF_CN 0x06 1806 #define CMD_QUE_XRI_BUF_CX 0x07 1807 #define CMD_IOCB_CONTINUE_CN 0x08 1808 #define CMD_RET_XRI_BUF_CX 0x09 1809 #define CMD_ELS_REQUEST_CR 0x0A 1810 #define CMD_ELS_REQUEST_CX 0x0B 1811 #define CMD_RCV_ELS_REQ_CX 0x0D 1812 #define CMD_ABORT_XRI_CN 0x0E 1813 #define CMD_ABORT_XRI_CX 0x0F 1814 #define CMD_CLOSE_XRI_CN 0x10 1815 #define CMD_CLOSE_XRI_CX 0x11 1816 #define CMD_CREATE_XRI_CR 0x12 1817 #define CMD_CREATE_XRI_CX 0x13 1818 #define CMD_GET_RPI_CN 0x14 1819 #define CMD_XMIT_ELS_RSP_CX 0x15 1820 #define CMD_GET_RPI_CR 0x16 1821 #define CMD_XRI_ABORTED_CX 0x17 1822 #define CMD_FCP_IWRITE_CR 0x18 1823 #define CMD_FCP_IWRITE_CX 0x19 1824 #define CMD_FCP_IREAD_CR 0x1A 1825 #define CMD_FCP_IREAD_CX 0x1B 1826 #define CMD_FCP_ICMND_CR 0x1C 1827 #define CMD_FCP_ICMND_CX 0x1D 1828 #define CMD_FCP_TSEND_CX 0x1F 1829 #define CMD_FCP_TRECEIVE_CX 0x21 1830 #define CMD_FCP_TRSP_CX 0x23 1831 #define CMD_FCP_AUTO_TRSP_CX 0x29 1832 1833 #define CMD_ADAPTER_MSG 0x20 1834 #define CMD_ADAPTER_DUMP 0x22 1835 1836 /* SLI_2 IOCB Command Set */ 1837 1838 #define CMD_ASYNC_STATUS 0x7C 1839 #define CMD_RCV_SEQUENCE64_CX 0x81 1840 #define CMD_XMIT_SEQUENCE64_CR 0x82 1841 #define CMD_XMIT_SEQUENCE64_CX 0x83 1842 #define CMD_XMIT_BCAST64_CN 0x84 1843 #define CMD_XMIT_BCAST64_CX 0x85 1844 #define CMD_QUE_RING_BUF64_CN 0x86 1845 #define CMD_QUE_XRI_BUF64_CX 0x87 1846 #define CMD_IOCB_CONTINUE64_CN 0x88 1847 #define CMD_RET_XRI_BUF64_CX 0x89 1848 #define CMD_ELS_REQUEST64_CR 0x8A 1849 #define CMD_ELS_REQUEST64_CX 0x8B 1850 #define CMD_ABORT_MXRI64_CN 0x8C 1851 #define CMD_RCV_ELS_REQ64_CX 0x8D 1852 #define CMD_XMIT_ELS_RSP64_CX 0x95 1853 #define CMD_XMIT_BLS_RSP64_CX 0x97 1854 #define CMD_FCP_IWRITE64_CR 0x98 1855 #define CMD_FCP_IWRITE64_CX 0x99 1856 #define CMD_FCP_IREAD64_CR 0x9A 1857 #define CMD_FCP_IREAD64_CX 0x9B 1858 #define CMD_FCP_ICMND64_CR 0x9C 1859 #define CMD_FCP_ICMND64_CX 0x9D 1860 #define CMD_FCP_TSEND64_CX 0x9F 1861 #define CMD_FCP_TRECEIVE64_CX 0xA1 1862 #define CMD_FCP_TRSP64_CX 0xA3 1863 1864 #define CMD_QUE_XRI64_CX 0xB3 1865 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1866 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1867 #define CMD_IOCB_RET_XRI64_CX 0xB9 1868 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1869 1870 #define CMD_GEN_REQUEST64_CR 0xC2 1871 #define CMD_GEN_REQUEST64_CX 0xC3 1872 1873 /* Unhandled SLI-3 Commands */ 1874 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1875 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1876 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1877 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1878 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1879 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1880 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1881 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1882 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1883 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1884 #define CMD_IOCB_LOGENTRY_CN 0x94 1885 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1886 1887 /* Data Security SLI Commands */ 1888 #define DSSCMD_IWRITE64_CR 0xF8 1889 #define DSSCMD_IWRITE64_CX 0xF9 1890 #define DSSCMD_IREAD64_CR 0xFA 1891 #define DSSCMD_IREAD64_CX 0xFB 1892 1893 #define CMD_MAX_IOCB_CMD 0xFB 1894 #define CMD_IOCB_MASK 0xff 1895 1896 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1897 iocb */ 1898 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1899 /* 1900 * Define Status 1901 */ 1902 #define MBX_SUCCESS 0 1903 #define MBXERR_NUM_RINGS 1 1904 #define MBXERR_NUM_IOCBS 2 1905 #define MBXERR_IOCBS_EXCEEDED 3 1906 #define MBXERR_BAD_RING_NUMBER 4 1907 #define MBXERR_MASK_ENTRIES_RANGE 5 1908 #define MBXERR_MASKS_EXCEEDED 6 1909 #define MBXERR_BAD_PROFILE 7 1910 #define MBXERR_BAD_DEF_CLASS 8 1911 #define MBXERR_BAD_MAX_RESPONDER 9 1912 #define MBXERR_BAD_MAX_ORIGINATOR 10 1913 #define MBXERR_RPI_REGISTERED 11 1914 #define MBXERR_RPI_FULL 12 1915 #define MBXERR_NO_RESOURCES 13 1916 #define MBXERR_BAD_RCV_LENGTH 14 1917 #define MBXERR_DMA_ERROR 15 1918 #define MBXERR_ERROR 16 1919 #define MBXERR_LINK_DOWN 0x33 1920 #define MBXERR_SEC_NO_PERMISSION 0xF02 1921 #define MBX_NOT_FINISHED 255 1922 1923 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1924 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1925 1926 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1927 1928 /* 1929 * return code Fail 1930 */ 1931 #define FAILURE 1 1932 1933 /* 1934 * Begin Structure Definitions for Mailbox Commands 1935 */ 1936 1937 typedef struct { 1938 #ifdef __BIG_ENDIAN_BITFIELD 1939 uint8_t tval; 1940 uint8_t tmask; 1941 uint8_t rval; 1942 uint8_t rmask; 1943 #else /* __LITTLE_ENDIAN_BITFIELD */ 1944 uint8_t rmask; 1945 uint8_t rval; 1946 uint8_t tmask; 1947 uint8_t tval; 1948 #endif 1949 } RR_REG; 1950 1951 struct ulp_bde { 1952 uint32_t bdeAddress; 1953 #ifdef __BIG_ENDIAN_BITFIELD 1954 uint32_t bdeReserved:4; 1955 uint32_t bdeAddrHigh:4; 1956 uint32_t bdeSize:24; 1957 #else /* __LITTLE_ENDIAN_BITFIELD */ 1958 uint32_t bdeSize:24; 1959 uint32_t bdeAddrHigh:4; 1960 uint32_t bdeReserved:4; 1961 #endif 1962 }; 1963 1964 typedef struct ULP_BDL { /* SLI-2 */ 1965 #ifdef __BIG_ENDIAN_BITFIELD 1966 uint32_t bdeFlags:8; /* BDL Flags */ 1967 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1968 #else /* __LITTLE_ENDIAN_BITFIELD */ 1969 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1970 uint32_t bdeFlags:8; /* BDL Flags */ 1971 #endif 1972 1973 uint32_t addrLow; /* Address 0:31 */ 1974 uint32_t addrHigh; /* Address 32:63 */ 1975 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1976 } ULP_BDL; 1977 1978 /* 1979 * BlockGuard Definitions 1980 */ 1981 1982 enum lpfc_protgrp_type { 1983 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1984 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1985 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1986 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1987 }; 1988 1989 /* PDE Descriptors */ 1990 #define LPFC_PDE5_DESCRIPTOR 0x85 1991 #define LPFC_PDE6_DESCRIPTOR 0x86 1992 #define LPFC_PDE7_DESCRIPTOR 0x87 1993 1994 /* BlockGuard Opcodes */ 1995 #define BG_OP_IN_NODIF_OUT_CRC 0x0 1996 #define BG_OP_IN_CRC_OUT_NODIF 0x1 1997 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 1998 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 1999 #define BG_OP_IN_CRC_OUT_CRC 0x4 2000 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 2001 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2002 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2003 #define BG_OP_RAW_MODE 0x8 2004 2005 struct lpfc_pde5 { 2006 uint32_t word0; 2007 #define pde5_type_SHIFT 24 2008 #define pde5_type_MASK 0x000000ff 2009 #define pde5_type_WORD word0 2010 #define pde5_rsvd0_SHIFT 0 2011 #define pde5_rsvd0_MASK 0x00ffffff 2012 #define pde5_rsvd0_WORD word0 2013 uint32_t reftag; /* Reference Tag Value */ 2014 uint32_t reftagtr; /* Reference Tag Translation Value */ 2015 }; 2016 2017 struct lpfc_pde6 { 2018 uint32_t word0; 2019 #define pde6_type_SHIFT 24 2020 #define pde6_type_MASK 0x000000ff 2021 #define pde6_type_WORD word0 2022 #define pde6_rsvd0_SHIFT 0 2023 #define pde6_rsvd0_MASK 0x00ffffff 2024 #define pde6_rsvd0_WORD word0 2025 uint32_t word1; 2026 #define pde6_rsvd1_SHIFT 26 2027 #define pde6_rsvd1_MASK 0x0000003f 2028 #define pde6_rsvd1_WORD word1 2029 #define pde6_na_SHIFT 25 2030 #define pde6_na_MASK 0x00000001 2031 #define pde6_na_WORD word1 2032 #define pde6_rsvd2_SHIFT 16 2033 #define pde6_rsvd2_MASK 0x000001FF 2034 #define pde6_rsvd2_WORD word1 2035 #define pde6_apptagtr_SHIFT 0 2036 #define pde6_apptagtr_MASK 0x0000ffff 2037 #define pde6_apptagtr_WORD word1 2038 uint32_t word2; 2039 #define pde6_optx_SHIFT 28 2040 #define pde6_optx_MASK 0x0000000f 2041 #define pde6_optx_WORD word2 2042 #define pde6_oprx_SHIFT 24 2043 #define pde6_oprx_MASK 0x0000000f 2044 #define pde6_oprx_WORD word2 2045 #define pde6_nr_SHIFT 23 2046 #define pde6_nr_MASK 0x00000001 2047 #define pde6_nr_WORD word2 2048 #define pde6_ce_SHIFT 22 2049 #define pde6_ce_MASK 0x00000001 2050 #define pde6_ce_WORD word2 2051 #define pde6_re_SHIFT 21 2052 #define pde6_re_MASK 0x00000001 2053 #define pde6_re_WORD word2 2054 #define pde6_ae_SHIFT 20 2055 #define pde6_ae_MASK 0x00000001 2056 #define pde6_ae_WORD word2 2057 #define pde6_ai_SHIFT 19 2058 #define pde6_ai_MASK 0x00000001 2059 #define pde6_ai_WORD word2 2060 #define pde6_bs_SHIFT 16 2061 #define pde6_bs_MASK 0x00000007 2062 #define pde6_bs_WORD word2 2063 #define pde6_apptagval_SHIFT 0 2064 #define pde6_apptagval_MASK 0x0000ffff 2065 #define pde6_apptagval_WORD word2 2066 }; 2067 2068 struct lpfc_pde7 { 2069 uint32_t word0; 2070 #define pde7_type_SHIFT 24 2071 #define pde7_type_MASK 0x000000ff 2072 #define pde7_type_WORD word0 2073 #define pde7_rsvd0_SHIFT 0 2074 #define pde7_rsvd0_MASK 0x00ffffff 2075 #define pde7_rsvd0_WORD word0 2076 uint32_t addrHigh; 2077 uint32_t addrLow; 2078 }; 2079 2080 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2081 2082 typedef struct { 2083 #ifdef __BIG_ENDIAN_BITFIELD 2084 uint32_t rsvd2:25; 2085 uint32_t acknowledgment:1; 2086 uint32_t version:1; 2087 uint32_t erase_or_prog:1; 2088 uint32_t update_flash:1; 2089 uint32_t update_ram:1; 2090 uint32_t method:1; 2091 uint32_t load_cmplt:1; 2092 #else /* __LITTLE_ENDIAN_BITFIELD */ 2093 uint32_t load_cmplt:1; 2094 uint32_t method:1; 2095 uint32_t update_ram:1; 2096 uint32_t update_flash:1; 2097 uint32_t erase_or_prog:1; 2098 uint32_t version:1; 2099 uint32_t acknowledgment:1; 2100 uint32_t rsvd2:25; 2101 #endif 2102 2103 uint32_t dl_to_adr_low; 2104 uint32_t dl_to_adr_high; 2105 uint32_t dl_len; 2106 union { 2107 uint32_t dl_from_mbx_offset; 2108 struct ulp_bde dl_from_bde; 2109 struct ulp_bde64 dl_from_bde64; 2110 } un; 2111 2112 } LOAD_SM_VAR; 2113 2114 /* Structure for MB Command READ_NVPARM (02) */ 2115 2116 typedef struct { 2117 uint32_t rsvd1[3]; /* Read as all one's */ 2118 uint32_t rsvd2; /* Read as all zero's */ 2119 uint32_t portname[2]; /* N_PORT name */ 2120 uint32_t nodename[2]; /* NODE name */ 2121 2122 #ifdef __BIG_ENDIAN_BITFIELD 2123 uint32_t pref_DID:24; 2124 uint32_t hardAL_PA:8; 2125 #else /* __LITTLE_ENDIAN_BITFIELD */ 2126 uint32_t hardAL_PA:8; 2127 uint32_t pref_DID:24; 2128 #endif 2129 2130 uint32_t rsvd3[21]; /* Read as all one's */ 2131 } READ_NV_VAR; 2132 2133 /* Structure for MB Command WRITE_NVPARMS (03) */ 2134 2135 typedef struct { 2136 uint32_t rsvd1[3]; /* Must be all one's */ 2137 uint32_t rsvd2; /* Must be all zero's */ 2138 uint32_t portname[2]; /* N_PORT name */ 2139 uint32_t nodename[2]; /* NODE name */ 2140 2141 #ifdef __BIG_ENDIAN_BITFIELD 2142 uint32_t pref_DID:24; 2143 uint32_t hardAL_PA:8; 2144 #else /* __LITTLE_ENDIAN_BITFIELD */ 2145 uint32_t hardAL_PA:8; 2146 uint32_t pref_DID:24; 2147 #endif 2148 2149 uint32_t rsvd3[21]; /* Must be all one's */ 2150 } WRITE_NV_VAR; 2151 2152 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2153 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2154 2155 typedef struct { 2156 uint32_t rsvd1; 2157 union { 2158 struct { 2159 struct ulp_bde xmit_bde; 2160 struct ulp_bde rcv_bde; 2161 } s1; 2162 struct { 2163 struct ulp_bde64 xmit_bde64; 2164 struct ulp_bde64 rcv_bde64; 2165 } s2; 2166 } un; 2167 } BIU_DIAG_VAR; 2168 2169 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2170 struct READ_EVENT_LOG_VAR { 2171 uint32_t word1; 2172 #define lpfc_event_log_SHIFT 29 2173 #define lpfc_event_log_MASK 0x00000001 2174 #define lpfc_event_log_WORD word1 2175 #define USE_MAILBOX_RESPONSE 1 2176 uint32_t offset; 2177 struct ulp_bde64 rcv_bde64; 2178 }; 2179 2180 /* Structure for MB Command INIT_LINK (05) */ 2181 2182 typedef struct { 2183 #ifdef __BIG_ENDIAN_BITFIELD 2184 uint32_t rsvd1:24; 2185 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2186 #else /* __LITTLE_ENDIAN_BITFIELD */ 2187 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2188 uint32_t rsvd1:24; 2189 #endif 2190 2191 #ifdef __BIG_ENDIAN_BITFIELD 2192 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2193 uint8_t rsvd2; 2194 uint16_t link_flags; 2195 #else /* __LITTLE_ENDIAN_BITFIELD */ 2196 uint16_t link_flags; 2197 uint8_t rsvd2; 2198 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2199 #endif 2200 2201 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2202 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2203 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2204 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2205 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2206 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2207 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2208 2209 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2210 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2211 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2212 2213 uint32_t link_speed; 2214 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2215 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2216 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2217 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2218 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2219 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2220 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2221 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2222 2223 } INIT_LINK_VAR; 2224 2225 /* Structure for MB Command DOWN_LINK (06) */ 2226 2227 typedef struct { 2228 uint32_t rsvd1; 2229 } DOWN_LINK_VAR; 2230 2231 /* Structure for MB Command CONFIG_LINK (07) */ 2232 2233 typedef struct { 2234 #ifdef __BIG_ENDIAN_BITFIELD 2235 uint32_t cr:1; 2236 uint32_t ci:1; 2237 uint32_t cr_delay:6; 2238 uint32_t cr_count:8; 2239 uint32_t rsvd1:8; 2240 uint32_t MaxBBC:8; 2241 #else /* __LITTLE_ENDIAN_BITFIELD */ 2242 uint32_t MaxBBC:8; 2243 uint32_t rsvd1:8; 2244 uint32_t cr_count:8; 2245 uint32_t cr_delay:6; 2246 uint32_t ci:1; 2247 uint32_t cr:1; 2248 #endif 2249 2250 uint32_t myId; 2251 uint32_t rsvd2; 2252 uint32_t edtov; 2253 uint32_t arbtov; 2254 uint32_t ratov; 2255 uint32_t rttov; 2256 uint32_t altov; 2257 uint32_t crtov; 2258 uint32_t citov; 2259 #ifdef __BIG_ENDIAN_BITFIELD 2260 uint32_t rrq_enable:1; 2261 uint32_t rrq_immed:1; 2262 uint32_t rsvd4:29; 2263 uint32_t ack0_enable:1; 2264 #else /* __LITTLE_ENDIAN_BITFIELD */ 2265 uint32_t ack0_enable:1; 2266 uint32_t rsvd4:29; 2267 uint32_t rrq_immed:1; 2268 uint32_t rrq_enable:1; 2269 #endif 2270 } CONFIG_LINK; 2271 2272 /* Structure for MB Command PART_SLIM (08) 2273 * will be removed since SLI1 is no longer supported! 2274 */ 2275 typedef struct { 2276 #ifdef __BIG_ENDIAN_BITFIELD 2277 uint16_t offCiocb; 2278 uint16_t numCiocb; 2279 uint16_t offRiocb; 2280 uint16_t numRiocb; 2281 #else /* __LITTLE_ENDIAN_BITFIELD */ 2282 uint16_t numCiocb; 2283 uint16_t offCiocb; 2284 uint16_t numRiocb; 2285 uint16_t offRiocb; 2286 #endif 2287 } RING_DEF; 2288 2289 typedef struct { 2290 #ifdef __BIG_ENDIAN_BITFIELD 2291 uint32_t unused1:24; 2292 uint32_t numRing:8; 2293 #else /* __LITTLE_ENDIAN_BITFIELD */ 2294 uint32_t numRing:8; 2295 uint32_t unused1:24; 2296 #endif 2297 2298 RING_DEF ringdef[4]; 2299 uint32_t hbainit; 2300 } PART_SLIM_VAR; 2301 2302 /* Structure for MB Command CONFIG_RING (09) */ 2303 2304 typedef struct { 2305 #ifdef __BIG_ENDIAN_BITFIELD 2306 uint32_t unused2:6; 2307 uint32_t recvSeq:1; 2308 uint32_t recvNotify:1; 2309 uint32_t numMask:8; 2310 uint32_t profile:8; 2311 uint32_t unused1:4; 2312 uint32_t ring:4; 2313 #else /* __LITTLE_ENDIAN_BITFIELD */ 2314 uint32_t ring:4; 2315 uint32_t unused1:4; 2316 uint32_t profile:8; 2317 uint32_t numMask:8; 2318 uint32_t recvNotify:1; 2319 uint32_t recvSeq:1; 2320 uint32_t unused2:6; 2321 #endif 2322 2323 #ifdef __BIG_ENDIAN_BITFIELD 2324 uint16_t maxRespXchg; 2325 uint16_t maxOrigXchg; 2326 #else /* __LITTLE_ENDIAN_BITFIELD */ 2327 uint16_t maxOrigXchg; 2328 uint16_t maxRespXchg; 2329 #endif 2330 2331 RR_REG rrRegs[6]; 2332 } CONFIG_RING_VAR; 2333 2334 /* Structure for MB Command RESET_RING (10) */ 2335 2336 typedef struct { 2337 uint32_t ring_no; 2338 } RESET_RING_VAR; 2339 2340 /* Structure for MB Command READ_CONFIG (11) */ 2341 2342 typedef struct { 2343 #ifdef __BIG_ENDIAN_BITFIELD 2344 uint32_t cr:1; 2345 uint32_t ci:1; 2346 uint32_t cr_delay:6; 2347 uint32_t cr_count:8; 2348 uint32_t InitBBC:8; 2349 uint32_t MaxBBC:8; 2350 #else /* __LITTLE_ENDIAN_BITFIELD */ 2351 uint32_t MaxBBC:8; 2352 uint32_t InitBBC:8; 2353 uint32_t cr_count:8; 2354 uint32_t cr_delay:6; 2355 uint32_t ci:1; 2356 uint32_t cr:1; 2357 #endif 2358 2359 #ifdef __BIG_ENDIAN_BITFIELD 2360 uint32_t topology:8; 2361 uint32_t myDid:24; 2362 #else /* __LITTLE_ENDIAN_BITFIELD */ 2363 uint32_t myDid:24; 2364 uint32_t topology:8; 2365 #endif 2366 2367 /* Defines for topology (defined previously) */ 2368 #ifdef __BIG_ENDIAN_BITFIELD 2369 uint32_t AR:1; 2370 uint32_t IR:1; 2371 uint32_t rsvd1:29; 2372 uint32_t ack0:1; 2373 #else /* __LITTLE_ENDIAN_BITFIELD */ 2374 uint32_t ack0:1; 2375 uint32_t rsvd1:29; 2376 uint32_t IR:1; 2377 uint32_t AR:1; 2378 #endif 2379 2380 uint32_t edtov; 2381 uint32_t arbtov; 2382 uint32_t ratov; 2383 uint32_t rttov; 2384 uint32_t altov; 2385 uint32_t lmt; 2386 #define LMT_RESERVED 0x000 /* Not used */ 2387 #define LMT_1Gb 0x004 2388 #define LMT_2Gb 0x008 2389 #define LMT_4Gb 0x040 2390 #define LMT_8Gb 0x080 2391 #define LMT_10Gb 0x100 2392 #define LMT_16Gb 0x200 2393 #define LMT_32Gb 0x400 2394 uint32_t rsvd2; 2395 uint32_t rsvd3; 2396 uint32_t max_xri; 2397 uint32_t max_iocb; 2398 uint32_t max_rpi; 2399 uint32_t avail_xri; 2400 uint32_t avail_iocb; 2401 uint32_t avail_rpi; 2402 uint32_t max_vpi; 2403 uint32_t rsvd4; 2404 uint32_t rsvd5; 2405 uint32_t avail_vpi; 2406 } READ_CONFIG_VAR; 2407 2408 /* Structure for MB Command READ_RCONFIG (12) */ 2409 2410 typedef struct { 2411 #ifdef __BIG_ENDIAN_BITFIELD 2412 uint32_t rsvd2:7; 2413 uint32_t recvNotify:1; 2414 uint32_t numMask:8; 2415 uint32_t profile:8; 2416 uint32_t rsvd1:4; 2417 uint32_t ring:4; 2418 #else /* __LITTLE_ENDIAN_BITFIELD */ 2419 uint32_t ring:4; 2420 uint32_t rsvd1:4; 2421 uint32_t profile:8; 2422 uint32_t numMask:8; 2423 uint32_t recvNotify:1; 2424 uint32_t rsvd2:7; 2425 #endif 2426 2427 #ifdef __BIG_ENDIAN_BITFIELD 2428 uint16_t maxResp; 2429 uint16_t maxOrig; 2430 #else /* __LITTLE_ENDIAN_BITFIELD */ 2431 uint16_t maxOrig; 2432 uint16_t maxResp; 2433 #endif 2434 2435 RR_REG rrRegs[6]; 2436 2437 #ifdef __BIG_ENDIAN_BITFIELD 2438 uint16_t cmdRingOffset; 2439 uint16_t cmdEntryCnt; 2440 uint16_t rspRingOffset; 2441 uint16_t rspEntryCnt; 2442 uint16_t nextCmdOffset; 2443 uint16_t rsvd3; 2444 uint16_t nextRspOffset; 2445 uint16_t rsvd4; 2446 #else /* __LITTLE_ENDIAN_BITFIELD */ 2447 uint16_t cmdEntryCnt; 2448 uint16_t cmdRingOffset; 2449 uint16_t rspEntryCnt; 2450 uint16_t rspRingOffset; 2451 uint16_t rsvd3; 2452 uint16_t nextCmdOffset; 2453 uint16_t rsvd4; 2454 uint16_t nextRspOffset; 2455 #endif 2456 } READ_RCONF_VAR; 2457 2458 /* Structure for MB Command READ_SPARM (13) */ 2459 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2460 2461 typedef struct { 2462 uint32_t rsvd1; 2463 uint32_t rsvd2; 2464 union { 2465 struct ulp_bde sp; /* This BDE points to struct serv_parm 2466 structure */ 2467 struct ulp_bde64 sp64; 2468 } un; 2469 #ifdef __BIG_ENDIAN_BITFIELD 2470 uint16_t rsvd3; 2471 uint16_t vpi; 2472 #else /* __LITTLE_ENDIAN_BITFIELD */ 2473 uint16_t vpi; 2474 uint16_t rsvd3; 2475 #endif 2476 } READ_SPARM_VAR; 2477 2478 /* Structure for MB Command READ_STATUS (14) */ 2479 2480 typedef struct { 2481 #ifdef __BIG_ENDIAN_BITFIELD 2482 uint32_t rsvd1:31; 2483 uint32_t clrCounters:1; 2484 uint16_t activeXriCnt; 2485 uint16_t activeRpiCnt; 2486 #else /* __LITTLE_ENDIAN_BITFIELD */ 2487 uint32_t clrCounters:1; 2488 uint32_t rsvd1:31; 2489 uint16_t activeRpiCnt; 2490 uint16_t activeXriCnt; 2491 #endif 2492 2493 uint32_t xmitByteCnt; 2494 uint32_t rcvByteCnt; 2495 uint32_t xmitFrameCnt; 2496 uint32_t rcvFrameCnt; 2497 uint32_t xmitSeqCnt; 2498 uint32_t rcvSeqCnt; 2499 uint32_t totalOrigExchanges; 2500 uint32_t totalRespExchanges; 2501 uint32_t rcvPbsyCnt; 2502 uint32_t rcvFbsyCnt; 2503 } READ_STATUS_VAR; 2504 2505 /* Structure for MB Command READ_RPI (15) */ 2506 /* Structure for MB Command READ_RPI64 (0x8F) */ 2507 2508 typedef struct { 2509 #ifdef __BIG_ENDIAN_BITFIELD 2510 uint16_t nextRpi; 2511 uint16_t reqRpi; 2512 uint32_t rsvd2:8; 2513 uint32_t DID:24; 2514 #else /* __LITTLE_ENDIAN_BITFIELD */ 2515 uint16_t reqRpi; 2516 uint16_t nextRpi; 2517 uint32_t DID:24; 2518 uint32_t rsvd2:8; 2519 #endif 2520 2521 union { 2522 struct ulp_bde sp; 2523 struct ulp_bde64 sp64; 2524 } un; 2525 2526 } READ_RPI_VAR; 2527 2528 /* Structure for MB Command READ_XRI (16) */ 2529 2530 typedef struct { 2531 #ifdef __BIG_ENDIAN_BITFIELD 2532 uint16_t nextXri; 2533 uint16_t reqXri; 2534 uint16_t rsvd1; 2535 uint16_t rpi; 2536 uint32_t rsvd2:8; 2537 uint32_t DID:24; 2538 uint32_t rsvd3:8; 2539 uint32_t SID:24; 2540 uint32_t rsvd4; 2541 uint8_t seqId; 2542 uint8_t rsvd5; 2543 uint16_t seqCount; 2544 uint16_t oxId; 2545 uint16_t rxId; 2546 uint32_t rsvd6:30; 2547 uint32_t si:1; 2548 uint32_t exchOrig:1; 2549 #else /* __LITTLE_ENDIAN_BITFIELD */ 2550 uint16_t reqXri; 2551 uint16_t nextXri; 2552 uint16_t rpi; 2553 uint16_t rsvd1; 2554 uint32_t DID:24; 2555 uint32_t rsvd2:8; 2556 uint32_t SID:24; 2557 uint32_t rsvd3:8; 2558 uint32_t rsvd4; 2559 uint16_t seqCount; 2560 uint8_t rsvd5; 2561 uint8_t seqId; 2562 uint16_t rxId; 2563 uint16_t oxId; 2564 uint32_t exchOrig:1; 2565 uint32_t si:1; 2566 uint32_t rsvd6:30; 2567 #endif 2568 } READ_XRI_VAR; 2569 2570 /* Structure for MB Command READ_REV (17) */ 2571 2572 typedef struct { 2573 #ifdef __BIG_ENDIAN_BITFIELD 2574 uint32_t cv:1; 2575 uint32_t rr:1; 2576 uint32_t rsvd2:2; 2577 uint32_t v3req:1; 2578 uint32_t v3rsp:1; 2579 uint32_t rsvd1:25; 2580 uint32_t rv:1; 2581 #else /* __LITTLE_ENDIAN_BITFIELD */ 2582 uint32_t rv:1; 2583 uint32_t rsvd1:25; 2584 uint32_t v3rsp:1; 2585 uint32_t v3req:1; 2586 uint32_t rsvd2:2; 2587 uint32_t rr:1; 2588 uint32_t cv:1; 2589 #endif 2590 2591 uint32_t biuRev; 2592 uint32_t smRev; 2593 union { 2594 uint32_t smFwRev; 2595 struct { 2596 #ifdef __BIG_ENDIAN_BITFIELD 2597 uint8_t ProgType; 2598 uint8_t ProgId; 2599 uint16_t ProgVer:4; 2600 uint16_t ProgRev:4; 2601 uint16_t ProgFixLvl:2; 2602 uint16_t ProgDistType:2; 2603 uint16_t DistCnt:4; 2604 #else /* __LITTLE_ENDIAN_BITFIELD */ 2605 uint16_t DistCnt:4; 2606 uint16_t ProgDistType:2; 2607 uint16_t ProgFixLvl:2; 2608 uint16_t ProgRev:4; 2609 uint16_t ProgVer:4; 2610 uint8_t ProgId; 2611 uint8_t ProgType; 2612 #endif 2613 2614 } b; 2615 } un; 2616 uint32_t endecRev; 2617 #ifdef __BIG_ENDIAN_BITFIELD 2618 uint8_t feaLevelHigh; 2619 uint8_t feaLevelLow; 2620 uint8_t fcphHigh; 2621 uint8_t fcphLow; 2622 #else /* __LITTLE_ENDIAN_BITFIELD */ 2623 uint8_t fcphLow; 2624 uint8_t fcphHigh; 2625 uint8_t feaLevelLow; 2626 uint8_t feaLevelHigh; 2627 #endif 2628 2629 uint32_t postKernRev; 2630 uint32_t opFwRev; 2631 uint8_t opFwName[16]; 2632 uint32_t sli1FwRev; 2633 uint8_t sli1FwName[16]; 2634 uint32_t sli2FwRev; 2635 uint8_t sli2FwName[16]; 2636 uint32_t sli3Feat; 2637 uint32_t RandomData[6]; 2638 } READ_REV_VAR; 2639 2640 /* Structure for MB Command READ_LINK_STAT (18) */ 2641 2642 typedef struct { 2643 uint32_t word0; 2644 2645 #define lpfc_read_link_stat_rec_SHIFT 0 2646 #define lpfc_read_link_stat_rec_MASK 0x1 2647 #define lpfc_read_link_stat_rec_WORD word0 2648 2649 #define lpfc_read_link_stat_gec_SHIFT 1 2650 #define lpfc_read_link_stat_gec_MASK 0x1 2651 #define lpfc_read_link_stat_gec_WORD word0 2652 2653 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2654 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2655 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2656 2657 #define lpfc_read_link_stat_rsvd_SHIFT 24 2658 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2659 #define lpfc_read_link_stat_rsvd_WORD word0 2660 2661 #define lpfc_read_link_stat_gec2_SHIFT 29 2662 #define lpfc_read_link_stat_gec2_MASK 0x1 2663 #define lpfc_read_link_stat_gec2_WORD word0 2664 2665 #define lpfc_read_link_stat_clrc_SHIFT 30 2666 #define lpfc_read_link_stat_clrc_MASK 0x1 2667 #define lpfc_read_link_stat_clrc_WORD word0 2668 2669 #define lpfc_read_link_stat_clof_SHIFT 31 2670 #define lpfc_read_link_stat_clof_MASK 0x1 2671 #define lpfc_read_link_stat_clof_WORD word0 2672 2673 uint32_t linkFailureCnt; 2674 uint32_t lossSyncCnt; 2675 uint32_t lossSignalCnt; 2676 uint32_t primSeqErrCnt; 2677 uint32_t invalidXmitWord; 2678 uint32_t crcCnt; 2679 uint32_t primSeqTimeout; 2680 uint32_t elasticOverrun; 2681 uint32_t arbTimeout; 2682 uint32_t advRecBufCredit; 2683 uint32_t curRecBufCredit; 2684 uint32_t advTransBufCredit; 2685 uint32_t curTransBufCredit; 2686 uint32_t recEofCount; 2687 uint32_t recEofdtiCount; 2688 uint32_t recEofniCount; 2689 uint32_t recSofcount; 2690 uint32_t rsvd1; 2691 uint32_t rsvd2; 2692 uint32_t recDrpXriCount; 2693 uint32_t fecCorrBlkCount; 2694 uint32_t fecUncorrBlkCount; 2695 } READ_LNK_VAR; 2696 2697 /* Structure for MB Command REG_LOGIN (19) */ 2698 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2699 2700 typedef struct { 2701 #ifdef __BIG_ENDIAN_BITFIELD 2702 uint16_t rsvd1; 2703 uint16_t rpi; 2704 uint32_t rsvd2:8; 2705 uint32_t did:24; 2706 #else /* __LITTLE_ENDIAN_BITFIELD */ 2707 uint16_t rpi; 2708 uint16_t rsvd1; 2709 uint32_t did:24; 2710 uint32_t rsvd2:8; 2711 #endif 2712 2713 union { 2714 struct ulp_bde sp; 2715 struct ulp_bde64 sp64; 2716 } un; 2717 2718 #ifdef __BIG_ENDIAN_BITFIELD 2719 uint16_t rsvd6; 2720 uint16_t vpi; 2721 #else /* __LITTLE_ENDIAN_BITFIELD */ 2722 uint16_t vpi; 2723 uint16_t rsvd6; 2724 #endif 2725 2726 } REG_LOGIN_VAR; 2727 2728 /* Word 30 contents for REG_LOGIN */ 2729 typedef union { 2730 struct { 2731 #ifdef __BIG_ENDIAN_BITFIELD 2732 uint16_t rsvd1:12; 2733 uint16_t wd30_class:4; 2734 uint16_t xri; 2735 #else /* __LITTLE_ENDIAN_BITFIELD */ 2736 uint16_t xri; 2737 uint16_t wd30_class:4; 2738 uint16_t rsvd1:12; 2739 #endif 2740 } f; 2741 uint32_t word; 2742 } REG_WD30; 2743 2744 /* Structure for MB Command UNREG_LOGIN (20) */ 2745 2746 typedef struct { 2747 #ifdef __BIG_ENDIAN_BITFIELD 2748 uint16_t rsvd1; 2749 uint16_t rpi; 2750 uint32_t rsvd2; 2751 uint32_t rsvd3; 2752 uint32_t rsvd4; 2753 uint32_t rsvd5; 2754 uint16_t rsvd6; 2755 uint16_t vpi; 2756 #else /* __LITTLE_ENDIAN_BITFIELD */ 2757 uint16_t rpi; 2758 uint16_t rsvd1; 2759 uint32_t rsvd2; 2760 uint32_t rsvd3; 2761 uint32_t rsvd4; 2762 uint32_t rsvd5; 2763 uint16_t vpi; 2764 uint16_t rsvd6; 2765 #endif 2766 } UNREG_LOGIN_VAR; 2767 2768 /* Structure for MB Command REG_VPI (0x96) */ 2769 typedef struct { 2770 #ifdef __BIG_ENDIAN_BITFIELD 2771 uint32_t rsvd1; 2772 uint32_t rsvd2:7; 2773 uint32_t upd:1; 2774 uint32_t sid:24; 2775 uint32_t wwn[2]; 2776 uint32_t rsvd5; 2777 uint16_t vfi; 2778 uint16_t vpi; 2779 #else /* __LITTLE_ENDIAN */ 2780 uint32_t rsvd1; 2781 uint32_t sid:24; 2782 uint32_t upd:1; 2783 uint32_t rsvd2:7; 2784 uint32_t wwn[2]; 2785 uint32_t rsvd5; 2786 uint16_t vpi; 2787 uint16_t vfi; 2788 #endif 2789 } REG_VPI_VAR; 2790 2791 /* Structure for MB Command UNREG_VPI (0x97) */ 2792 typedef struct { 2793 uint32_t rsvd1; 2794 #ifdef __BIG_ENDIAN_BITFIELD 2795 uint16_t rsvd2; 2796 uint16_t sli4_vpi; 2797 #else /* __LITTLE_ENDIAN */ 2798 uint16_t sli4_vpi; 2799 uint16_t rsvd2; 2800 #endif 2801 uint32_t rsvd3; 2802 uint32_t rsvd4; 2803 uint32_t rsvd5; 2804 #ifdef __BIG_ENDIAN_BITFIELD 2805 uint16_t rsvd6; 2806 uint16_t vpi; 2807 #else /* __LITTLE_ENDIAN */ 2808 uint16_t vpi; 2809 uint16_t rsvd6; 2810 #endif 2811 } UNREG_VPI_VAR; 2812 2813 /* Structure for MB Command UNREG_D_ID (0x23) */ 2814 2815 typedef struct { 2816 uint32_t did; 2817 uint32_t rsvd2; 2818 uint32_t rsvd3; 2819 uint32_t rsvd4; 2820 uint32_t rsvd5; 2821 #ifdef __BIG_ENDIAN_BITFIELD 2822 uint16_t rsvd6; 2823 uint16_t vpi; 2824 #else 2825 uint16_t vpi; 2826 uint16_t rsvd6; 2827 #endif 2828 } UNREG_D_ID_VAR; 2829 2830 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 2831 struct lpfc_mbx_read_top { 2832 uint32_t eventTag; /* Event tag */ 2833 uint32_t word2; 2834 #define lpfc_mbx_read_top_fa_SHIFT 12 2835 #define lpfc_mbx_read_top_fa_MASK 0x00000001 2836 #define lpfc_mbx_read_top_fa_WORD word2 2837 #define lpfc_mbx_read_top_mm_SHIFT 11 2838 #define lpfc_mbx_read_top_mm_MASK 0x00000001 2839 #define lpfc_mbx_read_top_mm_WORD word2 2840 #define lpfc_mbx_read_top_pb_SHIFT 9 2841 #define lpfc_mbx_read_top_pb_MASK 0X00000001 2842 #define lpfc_mbx_read_top_pb_WORD word2 2843 #define lpfc_mbx_read_top_il_SHIFT 8 2844 #define lpfc_mbx_read_top_il_MASK 0x00000001 2845 #define lpfc_mbx_read_top_il_WORD word2 2846 #define lpfc_mbx_read_top_att_type_SHIFT 0 2847 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 2848 #define lpfc_mbx_read_top_att_type_WORD word2 2849 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 2850 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 2851 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 2852 uint32_t word3; 2853 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 2854 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 2855 #define lpfc_mbx_read_top_alpa_granted_WORD word3 2856 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 2857 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 2858 #define lpfc_mbx_read_top_lip_alps_WORD word3 2859 #define lpfc_mbx_read_top_lip_type_SHIFT 8 2860 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 2861 #define lpfc_mbx_read_top_lip_type_WORD word3 2862 #define lpfc_mbx_read_top_topology_SHIFT 0 2863 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 2864 #define lpfc_mbx_read_top_topology_WORD word3 2865 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2866 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2867 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2868 /* store the LILP AL_PA position map into */ 2869 struct ulp_bde64 lilpBde64; 2870 #define LPFC_ALPA_MAP_SIZE 128 2871 uint32_t word7; 2872 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 2873 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 2874 #define lpfc_mbx_read_top_ld_lu_WORD word7 2875 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 2876 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 2877 #define lpfc_mbx_read_top_ld_tf_WORD word7 2878 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 2879 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 2880 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 2881 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 2882 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 2883 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 2884 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 2885 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 2886 #define lpfc_mbx_read_top_ld_tx_WORD word7 2887 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 2888 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 2889 #define lpfc_mbx_read_top_ld_rx_WORD word7 2890 uint32_t word8; 2891 #define lpfc_mbx_read_top_lu_SHIFT 31 2892 #define lpfc_mbx_read_top_lu_MASK 0x00000001 2893 #define lpfc_mbx_read_top_lu_WORD word8 2894 #define lpfc_mbx_read_top_tf_SHIFT 30 2895 #define lpfc_mbx_read_top_tf_MASK 0x00000001 2896 #define lpfc_mbx_read_top_tf_WORD word8 2897 #define lpfc_mbx_read_top_link_spd_SHIFT 8 2898 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 2899 #define lpfc_mbx_read_top_link_spd_WORD word8 2900 #define lpfc_mbx_read_top_nl_port_SHIFT 4 2901 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 2902 #define lpfc_mbx_read_top_nl_port_WORD word8 2903 #define lpfc_mbx_read_top_tx_SHIFT 2 2904 #define lpfc_mbx_read_top_tx_MASK 0x00000003 2905 #define lpfc_mbx_read_top_tx_WORD word8 2906 #define lpfc_mbx_read_top_rx_SHIFT 0 2907 #define lpfc_mbx_read_top_rx_MASK 0x00000003 2908 #define lpfc_mbx_read_top_rx_WORD word8 2909 #define LPFC_LINK_SPEED_UNKNOWN 0x0 2910 #define LPFC_LINK_SPEED_1GHZ 0x04 2911 #define LPFC_LINK_SPEED_2GHZ 0x08 2912 #define LPFC_LINK_SPEED_4GHZ 0x10 2913 #define LPFC_LINK_SPEED_8GHZ 0x20 2914 #define LPFC_LINK_SPEED_10GHZ 0x40 2915 #define LPFC_LINK_SPEED_16GHZ 0x80 2916 #define LPFC_LINK_SPEED_32GHZ 0x90 2917 }; 2918 2919 /* Structure for MB Command CLEAR_LA (22) */ 2920 2921 typedef struct { 2922 uint32_t eventTag; /* Event tag */ 2923 uint32_t rsvd1; 2924 } CLEAR_LA_VAR; 2925 2926 /* Structure for MB Command DUMP */ 2927 2928 typedef struct { 2929 #ifdef __BIG_ENDIAN_BITFIELD 2930 uint32_t rsvd:25; 2931 uint32_t ra:1; 2932 uint32_t co:1; 2933 uint32_t cv:1; 2934 uint32_t type:4; 2935 uint32_t entry_index:16; 2936 uint32_t region_id:16; 2937 #else /* __LITTLE_ENDIAN_BITFIELD */ 2938 uint32_t type:4; 2939 uint32_t cv:1; 2940 uint32_t co:1; 2941 uint32_t ra:1; 2942 uint32_t rsvd:25; 2943 uint32_t region_id:16; 2944 uint32_t entry_index:16; 2945 #endif 2946 2947 uint32_t sli4_length; 2948 uint32_t word_cnt; 2949 uint32_t resp_offset; 2950 } DUMP_VAR; 2951 2952 #define DMP_MEM_REG 0x1 2953 #define DMP_NV_PARAMS 0x2 2954 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 2955 #define DMP_WELL_KNOWN 0x4 2956 2957 #define DMP_REGION_VPD 0xe 2958 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2959 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2960 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2961 2962 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2963 #define DMP_VPORT_REGION_SIZE 0x200 2964 #define DMP_MBOX_OFFSET_WORD 0x5 2965 2966 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2967 #define DMP_RGN23_SIZE 0x400 2968 2969 #define WAKE_UP_PARMS_REGION_ID 4 2970 #define WAKE_UP_PARMS_WORD_SIZE 15 2971 2972 struct vport_rec { 2973 uint8_t wwpn[8]; 2974 uint8_t wwnn[8]; 2975 }; 2976 2977 #define VPORT_INFO_SIG 0x32324752 2978 #define VPORT_INFO_REV_MASK 0xff 2979 #define VPORT_INFO_REV 0x1 2980 #define MAX_STATIC_VPORT_COUNT 16 2981 struct static_vport_info { 2982 uint32_t signature; 2983 uint32_t rev; 2984 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2985 uint32_t resvd[66]; 2986 }; 2987 2988 /* Option rom version structure */ 2989 struct prog_id { 2990 #ifdef __BIG_ENDIAN_BITFIELD 2991 uint8_t type; 2992 uint8_t id; 2993 uint32_t ver:4; /* Major Version */ 2994 uint32_t rev:4; /* Revision */ 2995 uint32_t lev:2; /* Level */ 2996 uint32_t dist:2; /* Dist Type */ 2997 uint32_t num:4; /* number after dist type */ 2998 #else /* __LITTLE_ENDIAN_BITFIELD */ 2999 uint32_t num:4; /* number after dist type */ 3000 uint32_t dist:2; /* Dist Type */ 3001 uint32_t lev:2; /* Level */ 3002 uint32_t rev:4; /* Revision */ 3003 uint32_t ver:4; /* Major Version */ 3004 uint8_t id; 3005 uint8_t type; 3006 #endif 3007 }; 3008 3009 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3010 3011 struct update_cfg_var { 3012 #ifdef __BIG_ENDIAN_BITFIELD 3013 uint32_t rsvd2:16; 3014 uint32_t type:8; 3015 uint32_t rsvd:1; 3016 uint32_t ra:1; 3017 uint32_t co:1; 3018 uint32_t cv:1; 3019 uint32_t req:4; 3020 uint32_t entry_length:16; 3021 uint32_t region_id:16; 3022 #else /* __LITTLE_ENDIAN_BITFIELD */ 3023 uint32_t req:4; 3024 uint32_t cv:1; 3025 uint32_t co:1; 3026 uint32_t ra:1; 3027 uint32_t rsvd:1; 3028 uint32_t type:8; 3029 uint32_t rsvd2:16; 3030 uint32_t region_id:16; 3031 uint32_t entry_length:16; 3032 #endif 3033 3034 uint32_t resp_info; 3035 uint32_t byte_cnt; 3036 uint32_t data_offset; 3037 }; 3038 3039 struct hbq_mask { 3040 #ifdef __BIG_ENDIAN_BITFIELD 3041 uint8_t tmatch; 3042 uint8_t tmask; 3043 uint8_t rctlmatch; 3044 uint8_t rctlmask; 3045 #else /* __LITTLE_ENDIAN */ 3046 uint8_t rctlmask; 3047 uint8_t rctlmatch; 3048 uint8_t tmask; 3049 uint8_t tmatch; 3050 #endif 3051 }; 3052 3053 3054 /* Structure for MB Command CONFIG_HBQ (7c) */ 3055 3056 struct config_hbq_var { 3057 #ifdef __BIG_ENDIAN_BITFIELD 3058 uint32_t rsvd1 :7; 3059 uint32_t recvNotify :1; /* Receive Notification */ 3060 uint32_t numMask :8; /* # Mask Entries */ 3061 uint32_t profile :8; /* Selection Profile */ 3062 uint32_t rsvd2 :8; 3063 #else /* __LITTLE_ENDIAN */ 3064 uint32_t rsvd2 :8; 3065 uint32_t profile :8; /* Selection Profile */ 3066 uint32_t numMask :8; /* # Mask Entries */ 3067 uint32_t recvNotify :1; /* Receive Notification */ 3068 uint32_t rsvd1 :7; 3069 #endif 3070 3071 #ifdef __BIG_ENDIAN_BITFIELD 3072 uint32_t hbqId :16; 3073 uint32_t rsvd3 :12; 3074 uint32_t ringMask :4; 3075 #else /* __LITTLE_ENDIAN */ 3076 uint32_t ringMask :4; 3077 uint32_t rsvd3 :12; 3078 uint32_t hbqId :16; 3079 #endif 3080 3081 #ifdef __BIG_ENDIAN_BITFIELD 3082 uint32_t entry_count :16; 3083 uint32_t rsvd4 :8; 3084 uint32_t headerLen :8; 3085 #else /* __LITTLE_ENDIAN */ 3086 uint32_t headerLen :8; 3087 uint32_t rsvd4 :8; 3088 uint32_t entry_count :16; 3089 #endif 3090 3091 uint32_t hbqaddrLow; 3092 uint32_t hbqaddrHigh; 3093 3094 #ifdef __BIG_ENDIAN_BITFIELD 3095 uint32_t rsvd5 :31; 3096 uint32_t logEntry :1; 3097 #else /* __LITTLE_ENDIAN */ 3098 uint32_t logEntry :1; 3099 uint32_t rsvd5 :31; 3100 #endif 3101 3102 uint32_t rsvd6; /* w7 */ 3103 uint32_t rsvd7; /* w8 */ 3104 uint32_t rsvd8; /* w9 */ 3105 3106 struct hbq_mask hbqMasks[6]; 3107 3108 3109 union { 3110 uint32_t allprofiles[12]; 3111 3112 struct { 3113 #ifdef __BIG_ENDIAN_BITFIELD 3114 uint32_t seqlenoff :16; 3115 uint32_t maxlen :16; 3116 #else /* __LITTLE_ENDIAN */ 3117 uint32_t maxlen :16; 3118 uint32_t seqlenoff :16; 3119 #endif 3120 #ifdef __BIG_ENDIAN_BITFIELD 3121 uint32_t rsvd1 :28; 3122 uint32_t seqlenbcnt :4; 3123 #else /* __LITTLE_ENDIAN */ 3124 uint32_t seqlenbcnt :4; 3125 uint32_t rsvd1 :28; 3126 #endif 3127 uint32_t rsvd[10]; 3128 } profile2; 3129 3130 struct { 3131 #ifdef __BIG_ENDIAN_BITFIELD 3132 uint32_t seqlenoff :16; 3133 uint32_t maxlen :16; 3134 #else /* __LITTLE_ENDIAN */ 3135 uint32_t maxlen :16; 3136 uint32_t seqlenoff :16; 3137 #endif 3138 #ifdef __BIG_ENDIAN_BITFIELD 3139 uint32_t cmdcodeoff :28; 3140 uint32_t rsvd1 :12; 3141 uint32_t seqlenbcnt :4; 3142 #else /* __LITTLE_ENDIAN */ 3143 uint32_t seqlenbcnt :4; 3144 uint32_t rsvd1 :12; 3145 uint32_t cmdcodeoff :28; 3146 #endif 3147 uint32_t cmdmatch[8]; 3148 3149 uint32_t rsvd[2]; 3150 } profile3; 3151 3152 struct { 3153 #ifdef __BIG_ENDIAN_BITFIELD 3154 uint32_t seqlenoff :16; 3155 uint32_t maxlen :16; 3156 #else /* __LITTLE_ENDIAN */ 3157 uint32_t maxlen :16; 3158 uint32_t seqlenoff :16; 3159 #endif 3160 #ifdef __BIG_ENDIAN_BITFIELD 3161 uint32_t cmdcodeoff :28; 3162 uint32_t rsvd1 :12; 3163 uint32_t seqlenbcnt :4; 3164 #else /* __LITTLE_ENDIAN */ 3165 uint32_t seqlenbcnt :4; 3166 uint32_t rsvd1 :12; 3167 uint32_t cmdcodeoff :28; 3168 #endif 3169 uint32_t cmdmatch[8]; 3170 3171 uint32_t rsvd[2]; 3172 } profile5; 3173 3174 } profiles; 3175 3176 }; 3177 3178 3179 3180 /* Structure for MB Command CONFIG_PORT (0x88) */ 3181 typedef struct { 3182 #ifdef __BIG_ENDIAN_BITFIELD 3183 uint32_t cBE : 1; 3184 uint32_t cET : 1; 3185 uint32_t cHpcb : 1; 3186 uint32_t cMA : 1; 3187 uint32_t sli_mode : 4; 3188 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3189 * config block */ 3190 #else /* __LITTLE_ENDIAN */ 3191 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3192 * config block */ 3193 uint32_t sli_mode : 4; 3194 uint32_t cMA : 1; 3195 uint32_t cHpcb : 1; 3196 uint32_t cET : 1; 3197 uint32_t cBE : 1; 3198 #endif 3199 3200 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3201 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3202 uint32_t hbainit[5]; 3203 #ifdef __BIG_ENDIAN_BITFIELD 3204 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3205 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3206 #else /* __LITTLE_ENDIAN */ 3207 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3208 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3209 #endif 3210 3211 #ifdef __BIG_ENDIAN_BITFIELD 3212 uint32_t rsvd1 : 19; /* Reserved */ 3213 uint32_t cdss : 1; /* Configure Data Security SLI */ 3214 uint32_t casabt : 1; /* Configure async abts status notice */ 3215 uint32_t rsvd2 : 2; /* Reserved */ 3216 uint32_t cbg : 1; /* Configure BlockGuard */ 3217 uint32_t cmv : 1; /* Configure Max VPIs */ 3218 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3219 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3220 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3221 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3222 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3223 uint32_t cmx : 1; /* Configure Max XRIs */ 3224 uint32_t cmr : 1; /* Configure Max RPIs */ 3225 #else /* __LITTLE_ENDIAN */ 3226 uint32_t cmr : 1; /* Configure Max RPIs */ 3227 uint32_t cmx : 1; /* Configure Max XRIs */ 3228 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3229 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3230 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3231 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3232 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3233 uint32_t cmv : 1; /* Configure Max VPIs */ 3234 uint32_t cbg : 1; /* Configure BlockGuard */ 3235 uint32_t rsvd2 : 2; /* Reserved */ 3236 uint32_t casabt : 1; /* Configure async abts status notice */ 3237 uint32_t cdss : 1; /* Configure Data Security SLI */ 3238 uint32_t rsvd1 : 19; /* Reserved */ 3239 #endif 3240 #ifdef __BIG_ENDIAN_BITFIELD 3241 uint32_t rsvd3 : 19; /* Reserved */ 3242 uint32_t gdss : 1; /* Configure Data Security SLI */ 3243 uint32_t gasabt : 1; /* Grant async abts status notice */ 3244 uint32_t rsvd4 : 2; /* Reserved */ 3245 uint32_t gbg : 1; /* Grant BlockGuard */ 3246 uint32_t gmv : 1; /* Grant Max VPIs */ 3247 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3248 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3249 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3250 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3251 uint32_t gerbm : 1; /* Grant ERBM Request */ 3252 uint32_t gmx : 1; /* Grant Max XRIs */ 3253 uint32_t gmr : 1; /* Grant Max RPIs */ 3254 #else /* __LITTLE_ENDIAN */ 3255 uint32_t gmr : 1; /* Grant Max RPIs */ 3256 uint32_t gmx : 1; /* Grant Max XRIs */ 3257 uint32_t gerbm : 1; /* Grant ERBM Request */ 3258 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3259 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3260 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3261 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3262 uint32_t gmv : 1; /* Grant Max VPIs */ 3263 uint32_t gbg : 1; /* Grant BlockGuard */ 3264 uint32_t rsvd4 : 2; /* Reserved */ 3265 uint32_t gasabt : 1; /* Grant async abts status notice */ 3266 uint32_t gdss : 1; /* Configure Data Security SLI */ 3267 uint32_t rsvd3 : 19; /* Reserved */ 3268 #endif 3269 3270 #ifdef __BIG_ENDIAN_BITFIELD 3271 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3272 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3273 #else /* __LITTLE_ENDIAN */ 3274 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3275 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3276 #endif 3277 3278 #ifdef __BIG_ENDIAN_BITFIELD 3279 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3280 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3281 #else /* __LITTLE_ENDIAN */ 3282 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3283 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3284 #endif 3285 3286 uint32_t rsvd6; /* Reserved */ 3287 3288 #ifdef __BIG_ENDIAN_BITFIELD 3289 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 3290 uint32_t fips_level : 4; /* FIPS Level */ 3291 uint32_t sec_err : 9; /* security crypto error */ 3292 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3293 #else /* __LITTLE_ENDIAN */ 3294 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3295 uint32_t sec_err : 9; /* security crypto error */ 3296 uint32_t fips_level : 4; /* FIPS Level */ 3297 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 3298 #endif 3299 3300 } CONFIG_PORT_VAR; 3301 3302 /* Structure for MB Command CONFIG_MSI (0x30) */ 3303 struct config_msi_var { 3304 #ifdef __BIG_ENDIAN_BITFIELD 3305 uint32_t dfltMsgNum:8; /* Default message number */ 3306 uint32_t rsvd1:11; /* Reserved */ 3307 uint32_t NID:5; /* Number of secondary attention IDs */ 3308 uint32_t rsvd2:5; /* Reserved */ 3309 uint32_t dfltPresent:1; /* Default message number present */ 3310 uint32_t addFlag:1; /* Add association flag */ 3311 uint32_t reportFlag:1; /* Report association flag */ 3312 #else /* __LITTLE_ENDIAN_BITFIELD */ 3313 uint32_t reportFlag:1; /* Report association flag */ 3314 uint32_t addFlag:1; /* Add association flag */ 3315 uint32_t dfltPresent:1; /* Default message number present */ 3316 uint32_t rsvd2:5; /* Reserved */ 3317 uint32_t NID:5; /* Number of secondary attention IDs */ 3318 uint32_t rsvd1:11; /* Reserved */ 3319 uint32_t dfltMsgNum:8; /* Default message number */ 3320 #endif 3321 uint32_t attentionConditions[2]; 3322 uint8_t attentionId[16]; 3323 uint8_t messageNumberByHA[64]; 3324 uint8_t messageNumberByID[16]; 3325 uint32_t autoClearHA[2]; 3326 #ifdef __BIG_ENDIAN_BITFIELD 3327 uint32_t rsvd3:16; 3328 uint32_t autoClearID:16; 3329 #else /* __LITTLE_ENDIAN_BITFIELD */ 3330 uint32_t autoClearID:16; 3331 uint32_t rsvd3:16; 3332 #endif 3333 uint32_t rsvd4; 3334 }; 3335 3336 /* SLI-2 Port Control Block */ 3337 3338 /* SLIM POINTER */ 3339 #define SLIMOFF 0x30 /* WORD */ 3340 3341 typedef struct _SLI2_RDSC { 3342 uint32_t cmdEntries; 3343 uint32_t cmdAddrLow; 3344 uint32_t cmdAddrHigh; 3345 3346 uint32_t rspEntries; 3347 uint32_t rspAddrLow; 3348 uint32_t rspAddrHigh; 3349 } SLI2_RDSC; 3350 3351 typedef struct _PCB { 3352 #ifdef __BIG_ENDIAN_BITFIELD 3353 uint32_t type:8; 3354 #define TYPE_NATIVE_SLI2 0x01 3355 uint32_t feature:8; 3356 #define FEATURE_INITIAL_SLI2 0x01 3357 uint32_t rsvd:12; 3358 uint32_t maxRing:4; 3359 #else /* __LITTLE_ENDIAN_BITFIELD */ 3360 uint32_t maxRing:4; 3361 uint32_t rsvd:12; 3362 uint32_t feature:8; 3363 #define FEATURE_INITIAL_SLI2 0x01 3364 uint32_t type:8; 3365 #define TYPE_NATIVE_SLI2 0x01 3366 #endif 3367 3368 uint32_t mailBoxSize; 3369 uint32_t mbAddrLow; 3370 uint32_t mbAddrHigh; 3371 3372 uint32_t hgpAddrLow; 3373 uint32_t hgpAddrHigh; 3374 3375 uint32_t pgpAddrLow; 3376 uint32_t pgpAddrHigh; 3377 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3378 } PCB_t; 3379 3380 /* NEW_FEATURE */ 3381 typedef struct { 3382 #ifdef __BIG_ENDIAN_BITFIELD 3383 uint32_t rsvd0:27; 3384 uint32_t discardFarp:1; 3385 uint32_t IPEnable:1; 3386 uint32_t nodeName:1; 3387 uint32_t portName:1; 3388 uint32_t filterEnable:1; 3389 #else /* __LITTLE_ENDIAN_BITFIELD */ 3390 uint32_t filterEnable:1; 3391 uint32_t portName:1; 3392 uint32_t nodeName:1; 3393 uint32_t IPEnable:1; 3394 uint32_t discardFarp:1; 3395 uint32_t rsvd:27; 3396 #endif 3397 3398 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3399 uint8_t nodename[8]; 3400 uint32_t rsvd1; 3401 uint32_t rsvd2; 3402 uint32_t rsvd3; 3403 uint32_t IPAddress; 3404 } CONFIG_FARP_VAR; 3405 3406 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3407 3408 typedef struct { 3409 #ifdef __BIG_ENDIAN_BITFIELD 3410 uint32_t rsvd:30; 3411 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3412 #else /* __LITTLE_ENDIAN */ 3413 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3414 uint32_t rsvd:30; 3415 #endif 3416 } ASYNCEVT_ENABLE_VAR; 3417 3418 /* Union of all Mailbox Command types */ 3419 #define MAILBOX_CMD_WSIZE 32 3420 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3421 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3422 #define MAILBOX_EXT_WSIZE 512 3423 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3424 #define MAILBOX_HBA_EXT_OFFSET 0x100 3425 /* max mbox xmit size is a page size for sysfs IO operations */ 3426 #define MAILBOX_SYSFS_MAX 4096 3427 3428 typedef union { 3429 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3430 * feature/max ring number 3431 */ 3432 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3433 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3434 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3435 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3436 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3437 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3438 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3439 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3440 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3441 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3442 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3443 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3444 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3445 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3446 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3447 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3448 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3449 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3450 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3451 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3452 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3453 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3454 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3455 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3456 * NEW_FEATURE 3457 */ 3458 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3459 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3460 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3461 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3462 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3463 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3464 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3465 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3466 * (READ_EVENT_LOG) 3467 */ 3468 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3469 } MAILVARIANTS; 3470 3471 /* 3472 * SLI-2 specific structures 3473 */ 3474 3475 struct lpfc_hgp { 3476 __le32 cmdPutInx; 3477 __le32 rspGetInx; 3478 }; 3479 3480 struct lpfc_pgp { 3481 __le32 cmdGetInx; 3482 __le32 rspPutInx; 3483 }; 3484 3485 struct sli2_desc { 3486 uint32_t unused1[16]; 3487 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3488 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3489 }; 3490 3491 struct sli3_desc { 3492 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3493 uint32_t reserved[8]; 3494 uint32_t hbq_put[16]; 3495 }; 3496 3497 struct sli3_pgp { 3498 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3499 uint32_t hbq_get[16]; 3500 }; 3501 3502 union sli_var { 3503 struct sli2_desc s2; 3504 struct sli3_desc s3; 3505 struct sli3_pgp s3_pgp; 3506 }; 3507 3508 typedef struct { 3509 #ifdef __BIG_ENDIAN_BITFIELD 3510 uint16_t mbxStatus; 3511 uint8_t mbxCommand; 3512 uint8_t mbxReserved:6; 3513 uint8_t mbxHc:1; 3514 uint8_t mbxOwner:1; /* Low order bit first word */ 3515 #else /* __LITTLE_ENDIAN_BITFIELD */ 3516 uint8_t mbxOwner:1; /* Low order bit first word */ 3517 uint8_t mbxHc:1; 3518 uint8_t mbxReserved:6; 3519 uint8_t mbxCommand; 3520 uint16_t mbxStatus; 3521 #endif 3522 3523 MAILVARIANTS un; 3524 union sli_var us; 3525 } MAILBOX_t; 3526 3527 /* 3528 * Begin Structure Definitions for IOCB Commands 3529 */ 3530 3531 typedef struct { 3532 #ifdef __BIG_ENDIAN_BITFIELD 3533 uint8_t statAction; 3534 uint8_t statRsn; 3535 uint8_t statBaExp; 3536 uint8_t statLocalError; 3537 #else /* __LITTLE_ENDIAN_BITFIELD */ 3538 uint8_t statLocalError; 3539 uint8_t statBaExp; 3540 uint8_t statRsn; 3541 uint8_t statAction; 3542 #endif 3543 /* statRsn P/F_RJT reason codes */ 3544 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3545 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3546 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3547 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3548 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3549 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3550 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3551 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3552 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3553 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3554 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3555 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3556 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3557 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3558 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3559 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3560 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3561 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3562 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3563 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3564 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3565 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3566 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3567 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3568 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3569 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3570 3571 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3572 #define IOERR_MISSING_CONTINUE 0x01 3573 #define IOERR_SEQUENCE_TIMEOUT 0x02 3574 #define IOERR_INTERNAL_ERROR 0x03 3575 #define IOERR_INVALID_RPI 0x04 3576 #define IOERR_NO_XRI 0x05 3577 #define IOERR_ILLEGAL_COMMAND 0x06 3578 #define IOERR_XCHG_DROPPED 0x07 3579 #define IOERR_ILLEGAL_FIELD 0x08 3580 #define IOERR_BAD_CONTINUE 0x09 3581 #define IOERR_TOO_MANY_BUFFERS 0x0A 3582 #define IOERR_RCV_BUFFER_WAITING 0x0B 3583 #define IOERR_NO_CONNECTION 0x0C 3584 #define IOERR_TX_DMA_FAILED 0x0D 3585 #define IOERR_RX_DMA_FAILED 0x0E 3586 #define IOERR_ILLEGAL_FRAME 0x0F 3587 #define IOERR_EXTRA_DATA 0x10 3588 #define IOERR_NO_RESOURCES 0x11 3589 #define IOERR_RESERVED 0x12 3590 #define IOERR_ILLEGAL_LENGTH 0x13 3591 #define IOERR_UNSUPPORTED_FEATURE 0x14 3592 #define IOERR_ABORT_IN_PROGRESS 0x15 3593 #define IOERR_ABORT_REQUESTED 0x16 3594 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3595 #define IOERR_LOOP_OPEN_FAILURE 0x18 3596 #define IOERR_RING_RESET 0x19 3597 #define IOERR_LINK_DOWN 0x1A 3598 #define IOERR_CORRUPTED_DATA 0x1B 3599 #define IOERR_CORRUPTED_RPI 0x1C 3600 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3601 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3602 #define IOERR_DUP_FRAME 0x1F 3603 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3604 #define IOERR_BAD_HOST_ADDRESS 0x21 3605 #define IOERR_RCV_HDRBUF_WAITING 0x22 3606 #define IOERR_MISSING_HDR_BUFFER 0x23 3607 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3608 #define IOERR_ABORTMULT_REQUESTED 0x25 3609 #define IOERR_BUFFER_SHORTAGE 0x28 3610 #define IOERR_DEFAULT 0x29 3611 #define IOERR_CNT 0x2A 3612 #define IOERR_SLER_FAILURE 0x46 3613 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3614 #define IOERR_SLER_REC_RJT_ERR 0x48 3615 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3616 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3617 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3618 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3619 #define IOERR_SLER_ABTS_ERR 0x4E 3620 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3621 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3622 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3623 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3624 #define IOERR_DRVR_MASK 0x100 3625 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3626 #define IOERR_SLI_BRESET 0x102 3627 #define IOERR_SLI_ABORTED 0x103 3628 #define IOERR_PARAM_MASK 0x1ff 3629 } PARM_ERR; 3630 3631 typedef union { 3632 struct { 3633 #ifdef __BIG_ENDIAN_BITFIELD 3634 uint8_t Rctl; /* R_CTL field */ 3635 uint8_t Type; /* TYPE field */ 3636 uint8_t Dfctl; /* DF_CTL field */ 3637 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3638 #else /* __LITTLE_ENDIAN_BITFIELD */ 3639 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3640 uint8_t Dfctl; /* DF_CTL field */ 3641 uint8_t Type; /* TYPE field */ 3642 uint8_t Rctl; /* R_CTL field */ 3643 #endif 3644 3645 #define BC 0x02 /* Broadcast Received - Fctl */ 3646 #define SI 0x04 /* Sequence Initiative */ 3647 #define LA 0x08 /* Ignore Link Attention state */ 3648 #define LS 0x80 /* Last Sequence */ 3649 } hcsw; 3650 uint32_t reserved; 3651 } WORD5; 3652 3653 /* IOCB Command template for a generic response */ 3654 typedef struct { 3655 uint32_t reserved[4]; 3656 PARM_ERR perr; 3657 } GENERIC_RSP; 3658 3659 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3660 typedef struct { 3661 struct ulp_bde xrsqbde[2]; 3662 uint32_t xrsqRo; /* Starting Relative Offset */ 3663 WORD5 w5; /* Header control/status word */ 3664 } XR_SEQ_FIELDS; 3665 3666 /* IOCB Command template for ELS_REQUEST */ 3667 typedef struct { 3668 struct ulp_bde elsReq; 3669 struct ulp_bde elsRsp; 3670 3671 #ifdef __BIG_ENDIAN_BITFIELD 3672 uint32_t word4Rsvd:7; 3673 uint32_t fl:1; 3674 uint32_t myID:24; 3675 uint32_t word5Rsvd:8; 3676 uint32_t remoteID:24; 3677 #else /* __LITTLE_ENDIAN_BITFIELD */ 3678 uint32_t myID:24; 3679 uint32_t fl:1; 3680 uint32_t word4Rsvd:7; 3681 uint32_t remoteID:24; 3682 uint32_t word5Rsvd:8; 3683 #endif 3684 } ELS_REQUEST; 3685 3686 /* IOCB Command template for RCV_ELS_REQ */ 3687 typedef struct { 3688 struct ulp_bde elsReq[2]; 3689 uint32_t parmRo; 3690 3691 #ifdef __BIG_ENDIAN_BITFIELD 3692 uint32_t word5Rsvd:8; 3693 uint32_t remoteID:24; 3694 #else /* __LITTLE_ENDIAN_BITFIELD */ 3695 uint32_t remoteID:24; 3696 uint32_t word5Rsvd:8; 3697 #endif 3698 } RCV_ELS_REQ; 3699 3700 /* IOCB Command template for ABORT / CLOSE_XRI */ 3701 typedef struct { 3702 uint32_t rsvd[3]; 3703 uint32_t abortType; 3704 #define ABORT_TYPE_ABTX 0x00000000 3705 #define ABORT_TYPE_ABTS 0x00000001 3706 uint32_t parm; 3707 #ifdef __BIG_ENDIAN_BITFIELD 3708 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3709 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3710 #else /* __LITTLE_ENDIAN_BITFIELD */ 3711 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3712 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3713 #endif 3714 } AC_XRI; 3715 3716 /* IOCB Command template for ABORT_MXRI64 */ 3717 typedef struct { 3718 uint32_t rsvd[3]; 3719 uint32_t abortType; 3720 uint32_t parm; 3721 uint32_t iotag32; 3722 } A_MXRI64; 3723 3724 /* IOCB Command template for GET_RPI */ 3725 typedef struct { 3726 uint32_t rsvd[4]; 3727 uint32_t parmRo; 3728 #ifdef __BIG_ENDIAN_BITFIELD 3729 uint32_t word5Rsvd:8; 3730 uint32_t remoteID:24; 3731 #else /* __LITTLE_ENDIAN_BITFIELD */ 3732 uint32_t remoteID:24; 3733 uint32_t word5Rsvd:8; 3734 #endif 3735 } GET_RPI; 3736 3737 /* IOCB Command template for all FCP Initiator commands */ 3738 typedef struct { 3739 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3740 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3741 uint32_t fcpi_parm; 3742 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3743 } FCPI_FIELDS; 3744 3745 /* IOCB Command template for all FCP Target commands */ 3746 typedef struct { 3747 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3748 uint32_t fcpt_Offset; 3749 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3750 } FCPT_FIELDS; 3751 3752 /* SLI-2 IOCB structure definitions */ 3753 3754 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3755 typedef struct { 3756 ULP_BDL bdl; 3757 uint32_t xrsqRo; /* Starting Relative Offset */ 3758 WORD5 w5; /* Header control/status word */ 3759 } XMT_SEQ_FIELDS64; 3760 3761 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 3762 #define xmit_els_remoteID xrsqRo 3763 3764 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3765 typedef struct { 3766 struct ulp_bde64 rcvBde; 3767 uint32_t rsvd1; 3768 uint32_t xrsqRo; /* Starting Relative Offset */ 3769 WORD5 w5; /* Header control/status word */ 3770 } RCV_SEQ_FIELDS64; 3771 3772 /* IOCB Command template for ELS_REQUEST64 */ 3773 typedef struct { 3774 ULP_BDL bdl; 3775 #ifdef __BIG_ENDIAN_BITFIELD 3776 uint32_t word4Rsvd:7; 3777 uint32_t fl:1; 3778 uint32_t myID:24; 3779 uint32_t word5Rsvd:8; 3780 uint32_t remoteID:24; 3781 #else /* __LITTLE_ENDIAN_BITFIELD */ 3782 uint32_t myID:24; 3783 uint32_t fl:1; 3784 uint32_t word4Rsvd:7; 3785 uint32_t remoteID:24; 3786 uint32_t word5Rsvd:8; 3787 #endif 3788 } ELS_REQUEST64; 3789 3790 /* IOCB Command template for GEN_REQUEST64 */ 3791 typedef struct { 3792 ULP_BDL bdl; 3793 uint32_t xrsqRo; /* Starting Relative Offset */ 3794 WORD5 w5; /* Header control/status word */ 3795 } GEN_REQUEST64; 3796 3797 /* IOCB Command template for RCV_ELS_REQ64 */ 3798 typedef struct { 3799 struct ulp_bde64 elsReq; 3800 uint32_t rcvd1; 3801 uint32_t parmRo; 3802 3803 #ifdef __BIG_ENDIAN_BITFIELD 3804 uint32_t word5Rsvd:8; 3805 uint32_t remoteID:24; 3806 #else /* __LITTLE_ENDIAN_BITFIELD */ 3807 uint32_t remoteID:24; 3808 uint32_t word5Rsvd:8; 3809 #endif 3810 } RCV_ELS_REQ64; 3811 3812 /* IOCB Command template for RCV_SEQ64 */ 3813 struct rcv_seq64 { 3814 struct ulp_bde64 elsReq; 3815 uint32_t hbq_1; 3816 uint32_t parmRo; 3817 #ifdef __BIG_ENDIAN_BITFIELD 3818 uint32_t rctl:8; 3819 uint32_t type:8; 3820 uint32_t dfctl:8; 3821 uint32_t ls:1; 3822 uint32_t fs:1; 3823 uint32_t rsvd2:3; 3824 uint32_t si:1; 3825 uint32_t bc:1; 3826 uint32_t rsvd3:1; 3827 #else /* __LITTLE_ENDIAN_BITFIELD */ 3828 uint32_t rsvd3:1; 3829 uint32_t bc:1; 3830 uint32_t si:1; 3831 uint32_t rsvd2:3; 3832 uint32_t fs:1; 3833 uint32_t ls:1; 3834 uint32_t dfctl:8; 3835 uint32_t type:8; 3836 uint32_t rctl:8; 3837 #endif 3838 }; 3839 3840 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3841 typedef struct { 3842 ULP_BDL bdl; 3843 uint32_t fcpi_parm; 3844 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3845 } FCPI_FIELDS64; 3846 3847 /* IOCB Command template for all 64 bit FCP Target commands */ 3848 typedef struct { 3849 ULP_BDL bdl; 3850 uint32_t fcpt_Offset; 3851 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3852 } FCPT_FIELDS64; 3853 3854 /* IOCB Command template for Async Status iocb commands */ 3855 typedef struct { 3856 uint32_t rsvd[4]; 3857 uint32_t param; 3858 #ifdef __BIG_ENDIAN_BITFIELD 3859 uint16_t evt_code; /* High order bits word 5 */ 3860 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3861 #else /* __LITTLE_ENDIAN_BITFIELD */ 3862 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3863 uint16_t evt_code; /* Low order bits word 5 */ 3864 #endif 3865 } ASYNCSTAT_FIELDS; 3866 #define ASYNC_TEMP_WARN 0x100 3867 #define ASYNC_TEMP_SAFE 0x101 3868 #define ASYNC_STATUS_CN 0x102 3869 3870 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3871 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3872 3873 struct rcv_sli3 { 3874 #ifdef __BIG_ENDIAN_BITFIELD 3875 uint16_t ox_id; 3876 uint16_t seq_cnt; 3877 3878 uint16_t vpi; 3879 uint16_t word9Rsvd; 3880 #else /* __LITTLE_ENDIAN */ 3881 uint16_t seq_cnt; 3882 uint16_t ox_id; 3883 3884 uint16_t word9Rsvd; 3885 uint16_t vpi; 3886 #endif 3887 uint32_t word10Rsvd; 3888 uint32_t acc_len; /* accumulated length */ 3889 struct ulp_bde64 bde2; 3890 }; 3891 3892 /* Structure used for a single HBQ entry */ 3893 struct lpfc_hbq_entry { 3894 struct ulp_bde64 bde; 3895 uint32_t buffer_tag; 3896 }; 3897 3898 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3899 typedef struct { 3900 struct lpfc_hbq_entry buff; 3901 uint32_t rsvd; 3902 uint32_t rsvd1; 3903 } QUE_XRI64_CX_FIELDS; 3904 3905 struct que_xri64cx_ext_fields { 3906 uint32_t iotag64_low; 3907 uint32_t iotag64_high; 3908 uint32_t ebde_count; 3909 uint32_t rsvd; 3910 struct lpfc_hbq_entry buff[5]; 3911 }; 3912 3913 struct sli3_bg_fields { 3914 uint32_t filler[6]; /* word 8-13 in IOCB */ 3915 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3916 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3917 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3918 #define BGS_BIDIR_BG_PROF_SHIFT 24 3919 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3920 #define BGS_BIDIR_ERR_COND_SHIFT 16 3921 #define BGS_BG_PROFILE_MASK 0x0000ff00 3922 #define BGS_BG_PROFILE_SHIFT 8 3923 #define BGS_INVALID_PROF_MASK 0x00000020 3924 #define BGS_INVALID_PROF_SHIFT 5 3925 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3926 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3927 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3928 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3929 #define BGS_REFTAG_ERR_MASK 0x00000004 3930 #define BGS_REFTAG_ERR_SHIFT 2 3931 #define BGS_APPTAG_ERR_MASK 0x00000002 3932 #define BGS_APPTAG_ERR_SHIFT 1 3933 #define BGS_GUARD_ERR_MASK 0x00000001 3934 #define BGS_GUARD_ERR_SHIFT 0 3935 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3936 }; 3937 3938 static inline uint32_t 3939 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3940 { 3941 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 3942 BGS_BIDIR_BG_PROF_SHIFT; 3943 } 3944 3945 static inline uint32_t 3946 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3947 { 3948 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3949 BGS_BIDIR_ERR_COND_SHIFT; 3950 } 3951 3952 static inline uint32_t 3953 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3954 { 3955 return (bgstat & BGS_BG_PROFILE_MASK) >> 3956 BGS_BG_PROFILE_SHIFT; 3957 } 3958 3959 static inline uint32_t 3960 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3961 { 3962 return (bgstat & BGS_INVALID_PROF_MASK) >> 3963 BGS_INVALID_PROF_SHIFT; 3964 } 3965 3966 static inline uint32_t 3967 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3968 { 3969 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 3970 BGS_UNINIT_DIF_BLOCK_SHIFT; 3971 } 3972 3973 static inline uint32_t 3974 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3975 { 3976 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3977 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3978 } 3979 3980 static inline uint32_t 3981 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3982 { 3983 return (bgstat & BGS_REFTAG_ERR_MASK) >> 3984 BGS_REFTAG_ERR_SHIFT; 3985 } 3986 3987 static inline uint32_t 3988 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3989 { 3990 return (bgstat & BGS_APPTAG_ERR_MASK) >> 3991 BGS_APPTAG_ERR_SHIFT; 3992 } 3993 3994 static inline uint32_t 3995 lpfc_bgs_get_guard_err(uint32_t bgstat) 3996 { 3997 return (bgstat & BGS_GUARD_ERR_MASK) >> 3998 BGS_GUARD_ERR_SHIFT; 3999 } 4000 4001 #define LPFC_EXT_DATA_BDE_COUNT 3 4002 struct fcp_irw_ext { 4003 uint32_t io_tag64_low; 4004 uint32_t io_tag64_high; 4005 #ifdef __BIG_ENDIAN_BITFIELD 4006 uint8_t reserved1; 4007 uint8_t reserved2; 4008 uint8_t reserved3; 4009 uint8_t ebde_count; 4010 #else /* __LITTLE_ENDIAN */ 4011 uint8_t ebde_count; 4012 uint8_t reserved3; 4013 uint8_t reserved2; 4014 uint8_t reserved1; 4015 #endif 4016 uint32_t reserved4; 4017 struct ulp_bde64 rbde; /* response bde */ 4018 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4019 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4020 }; 4021 4022 typedef struct _IOCB { /* IOCB structure */ 4023 union { 4024 GENERIC_RSP grsp; /* Generic response */ 4025 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4026 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4027 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4028 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4029 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4030 GET_RPI getrpi; /* GET_RPI template */ 4031 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4032 FCPT_FIELDS fcpt; /* FCP target template */ 4033 4034 /* SLI-2 structures */ 4035 4036 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4037 * bde_64s */ 4038 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4039 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4040 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4041 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4042 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4043 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4044 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4045 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4046 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4047 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4048 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4049 } un; 4050 union { 4051 struct { 4052 #ifdef __BIG_ENDIAN_BITFIELD 4053 uint16_t ulpContext; /* High order bits word 6 */ 4054 uint16_t ulpIoTag; /* Low order bits word 6 */ 4055 #else /* __LITTLE_ENDIAN_BITFIELD */ 4056 uint16_t ulpIoTag; /* Low order bits word 6 */ 4057 uint16_t ulpContext; /* High order bits word 6 */ 4058 #endif 4059 } t1; 4060 struct { 4061 #ifdef __BIG_ENDIAN_BITFIELD 4062 uint16_t ulpContext; /* High order bits word 6 */ 4063 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4064 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4065 #else /* __LITTLE_ENDIAN_BITFIELD */ 4066 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4067 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4068 uint16_t ulpContext; /* High order bits word 6 */ 4069 #endif 4070 } t2; 4071 } un1; 4072 #define ulpContext un1.t1.ulpContext 4073 #define ulpIoTag un1.t1.ulpIoTag 4074 #define ulpIoTag0 un1.t2.ulpIoTag0 4075 4076 #ifdef __BIG_ENDIAN_BITFIELD 4077 uint32_t ulpTimeout:8; 4078 uint32_t ulpXS:1; 4079 uint32_t ulpFCP2Rcvy:1; 4080 uint32_t ulpPU:2; 4081 uint32_t ulpIr:1; 4082 uint32_t ulpClass:3; 4083 uint32_t ulpCommand:8; 4084 uint32_t ulpStatus:4; 4085 uint32_t ulpBdeCount:2; 4086 uint32_t ulpLe:1; 4087 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4088 #else /* __LITTLE_ENDIAN_BITFIELD */ 4089 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4090 uint32_t ulpLe:1; 4091 uint32_t ulpBdeCount:2; 4092 uint32_t ulpStatus:4; 4093 uint32_t ulpCommand:8; 4094 uint32_t ulpClass:3; 4095 uint32_t ulpIr:1; 4096 uint32_t ulpPU:2; 4097 uint32_t ulpFCP2Rcvy:1; 4098 uint32_t ulpXS:1; 4099 uint32_t ulpTimeout:8; 4100 #endif 4101 4102 union { 4103 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4104 4105 /* words 8-31 used for que_xri_cx iocb */ 4106 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4107 struct fcp_irw_ext fcp_ext; 4108 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4109 4110 /* words 8-15 for BlockGuard */ 4111 struct sli3_bg_fields sli3_bg; 4112 } unsli3; 4113 4114 #define ulpCt_h ulpXS 4115 #define ulpCt_l ulpFCP2Rcvy 4116 4117 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4118 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4119 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4120 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4121 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4122 #define PARM_NPIV_DID 3 4123 #define CLASS1 0 /* Class 1 */ 4124 #define CLASS2 1 /* Class 2 */ 4125 #define CLASS3 2 /* Class 3 */ 4126 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4127 4128 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4129 #define IOSTAT_FCP_RSP_ERROR 0x1 4130 #define IOSTAT_REMOTE_STOP 0x2 4131 #define IOSTAT_LOCAL_REJECT 0x3 4132 #define IOSTAT_NPORT_RJT 0x4 4133 #define IOSTAT_FABRIC_RJT 0x5 4134 #define IOSTAT_NPORT_BSY 0x6 4135 #define IOSTAT_FABRIC_BSY 0x7 4136 #define IOSTAT_INTERMED_RSP 0x8 4137 #define IOSTAT_LS_RJT 0x9 4138 #define IOSTAT_BA_RJT 0xA 4139 #define IOSTAT_RSVD1 0xB 4140 #define IOSTAT_RSVD2 0xC 4141 #define IOSTAT_RSVD3 0xD 4142 #define IOSTAT_RSVD4 0xE 4143 #define IOSTAT_NEED_BUFFER 0xF 4144 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4145 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4146 #define IOSTAT_CNT 0x11 4147 4148 } IOCB_t; 4149 4150 4151 #define SLI1_SLIM_SIZE (4 * 1024) 4152 4153 /* Up to 498 IOCBs will fit into 16k 4154 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4155 */ 4156 #define SLI2_SLIM_SIZE (64 * 1024) 4157 4158 /* Maximum IOCBs that will fit in SLI2 slim */ 4159 #define MAX_SLI2_IOCB 498 4160 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4161 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4162 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4163 4164 /* HBQ entries are 4 words each = 4k */ 4165 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4166 lpfc_sli_hbq_count()) 4167 4168 struct lpfc_sli2_slim { 4169 MAILBOX_t mbx; 4170 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4171 PCB_t pcb; 4172 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4173 }; 4174 4175 /* 4176 * This function checks PCI device to allow special handling for LC HBAs. 4177 * 4178 * Parameters: 4179 * device : struct pci_dev 's device field 4180 * 4181 * return 1 => TRUE 4182 * 0 => FALSE 4183 */ 4184 static inline int 4185 lpfc_is_LC_HBA(unsigned short device) 4186 { 4187 if ((device == PCI_DEVICE_ID_TFLY) || 4188 (device == PCI_DEVICE_ID_PFLY) || 4189 (device == PCI_DEVICE_ID_LP101) || 4190 (device == PCI_DEVICE_ID_BMID) || 4191 (device == PCI_DEVICE_ID_BSMB) || 4192 (device == PCI_DEVICE_ID_ZMID) || 4193 (device == PCI_DEVICE_ID_ZSMB) || 4194 (device == PCI_DEVICE_ID_SAT_MID) || 4195 (device == PCI_DEVICE_ID_SAT_SMB) || 4196 (device == PCI_DEVICE_ID_RFLY)) 4197 return 1; 4198 else 4199 return 0; 4200 } 4201 4202 /* 4203 * Determine if an IOCB failed because of a link event or firmware reset. 4204 */ 4205 4206 static inline int 4207 lpfc_error_lost_link(IOCB_t *iocbp) 4208 { 4209 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 4210 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 4211 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 4212 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 4213 } 4214 4215 #define MENLO_TRANSPORT_TYPE 0xfe 4216 #define MENLO_CONTEXT 0 4217 #define MENLO_PU 3 4218 #define MENLO_TIMEOUT 30 4219 #define SETVAR_MLOMNT 0x103107 4220 #define SETVAR_MLORST 0x103007 4221 4222 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4223