1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2017-2021 Broadcom. All Rights Reserved. The term * 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. * 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 7 * EMULEX and SLI are trademarks of Emulex. * 8 * www.broadcom.com * 9 * * 10 * This program is free software; you can redistribute it and/or * 11 * modify it under the terms of version 2 of the GNU General * 12 * Public License as published by the Free Software Foundation. * 13 * This program is distributed in the hope that it will be useful. * 14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 18 * TO BE LEGALLY INVALID. See the GNU General Public License for * 19 * more details, a copy of which can be found in the file COPYING * 20 * included with this package. * 21 *******************************************************************/ 22 23 #define FDMI_DID 0xfffffaU 24 #define NameServer_DID 0xfffffcU 25 #define Fabric_Cntl_DID 0xfffffdU 26 #define Fabric_DID 0xfffffeU 27 #define Bcast_DID 0xffffffU 28 #define Mask_DID 0xffffffU 29 #define CT_DID_MASK 0xffff00U 30 #define Fabric_DID_MASK 0xfff000U 31 #define WELL_KNOWN_DID_MASK 0xfffff0U 32 33 #define PT2PT_LocalID 1 34 #define PT2PT_RemoteID 2 35 36 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 37 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 38 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 39 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 40 41 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 42 0 */ 43 44 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 45 46 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 47 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 48 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 uint32_t CmdRsp:16; 90 uint32_t Size:16; 91 } bits; 92 uint32_t word; 93 }; 94 95 /* FC4 Feature bits for RFF_ID */ 96 #define FC4_FEATURE_TARGET 0x1 97 #define FC4_FEATURE_INIT 0x2 98 #define FC4_FEATURE_NVME_DISC 0x4 99 100 struct lpfc_sli_ct_request { 101 /* Structure is in Big Endian format */ 102 union CtRevisionId RevisionId; 103 uint8_t FsType; 104 uint8_t FsSubType; 105 uint8_t Options; 106 uint8_t Rsrvd1; 107 union CtCommandResponse CommandResponse; 108 uint8_t Rsrvd2; 109 uint8_t ReasonCode; 110 uint8_t Explanation; 111 uint8_t VendorUnique; 112 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 113 114 union { 115 uint32_t PortID; 116 struct gid { 117 uint8_t PortType; /* for GID_PT requests */ 118 #define GID_PT_N_PORT 1 119 uint8_t DomainScope; 120 uint8_t AreaScope; 121 uint8_t Fc4Type; /* for GID_FT requests */ 122 } gid; 123 struct gid_ff { 124 uint8_t Flags; 125 uint8_t DomainScope; 126 uint8_t AreaScope; 127 uint8_t rsvd1; 128 uint8_t rsvd2; 129 uint8_t rsvd3; 130 uint8_t Fc4FBits; 131 uint8_t Fc4Type; 132 } gid_ff; 133 struct rft { 134 uint32_t PortId; /* For RFT_ID requests */ 135 136 #ifdef __BIG_ENDIAN_BITFIELD 137 uint32_t rsvd0:16; 138 uint32_t rsvd1:7; 139 uint32_t fcpReg:1; /* Type 8 */ 140 uint32_t rsvd2:2; 141 uint32_t ipReg:1; /* Type 5 */ 142 uint32_t rsvd3:5; 143 #else /* __LITTLE_ENDIAN_BITFIELD */ 144 uint32_t rsvd0:16; 145 uint32_t fcpReg:1; /* Type 8 */ 146 uint32_t rsvd1:7; 147 uint32_t rsvd3:5; 148 uint32_t ipReg:1; /* Type 5 */ 149 uint32_t rsvd2:2; 150 #endif 151 152 uint32_t rsvd[7]; 153 } rft; 154 struct rnn { 155 uint32_t PortId; /* For RNN_ID requests */ 156 uint8_t wwnn[8]; 157 } rnn; 158 struct rsnn { /* For RSNN_ID requests */ 159 uint8_t wwnn[8]; 160 uint8_t len; 161 uint8_t symbname[255]; 162 } rsnn; 163 struct da_id { /* For DA_ID requests */ 164 uint32_t port_id; 165 } da_id; 166 struct rspn { /* For RSPN_ID requests */ 167 uint32_t PortId; 168 uint8_t len; 169 uint8_t symbname[255]; 170 } rspn; 171 struct gff { 172 uint32_t PortId; 173 } gff; 174 struct gff_acc { 175 uint8_t fbits[128]; 176 } gff_acc; 177 struct gft { 178 uint32_t PortId; 179 } gft; 180 struct gft_acc { 181 uint32_t fc4_types[8]; 182 } gft_acc; 183 #define FCP_TYPE_FEATURE_OFFSET 7 184 struct rff { 185 uint32_t PortId; 186 uint8_t reserved[2]; 187 uint8_t fbits; 188 uint8_t type_code; /* type=8 for FCP */ 189 } rff; 190 } un; 191 }; 192 193 #define LPFC_MAX_CT_SIZE (60 * 4096) 194 195 #define SLI_CT_REVISION 1 196 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 197 sizeof(struct gid)) 198 #define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 199 sizeof(struct gid_ff)) 200 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 201 sizeof(struct gff)) 202 #define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 203 sizeof(struct gft)) 204 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 205 sizeof(struct rft)) 206 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 207 sizeof(struct rff)) 208 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 209 sizeof(struct rnn)) 210 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 211 sizeof(struct rsnn)) 212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 213 sizeof(struct da_id)) 214 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 215 sizeof(struct rspn)) 216 217 /* 218 * FsType Definitions 219 */ 220 221 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 222 #define SLI_CT_TIME_SERVICE 0xFB 223 #define SLI_CT_DIRECTORY_SERVICE 0xFC 224 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 225 226 /* 227 * Directory Service Subtypes 228 */ 229 230 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 231 232 /* 233 * Response Codes 234 */ 235 236 #define SLI_CT_RESPONSE_FS_RJT 0x8001 237 #define SLI_CT_RESPONSE_FS_ACC 0x8002 238 239 /* 240 * Reason Codes 241 */ 242 243 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 244 #define SLI_CT_INVALID_COMMAND 0x01 245 #define SLI_CT_INVALID_VERSION 0x02 246 #define SLI_CT_LOGICAL_ERROR 0x03 247 #define SLI_CT_INVALID_IU_SIZE 0x04 248 #define SLI_CT_LOGICAL_BUSY 0x05 249 #define SLI_CT_PROTOCOL_ERROR 0x07 250 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 251 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 252 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 253 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 254 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 255 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 256 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 257 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 258 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 259 #define SLI_CT_VENDOR_UNIQUE 0xff 260 261 /* 262 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 263 */ 264 265 #define SLI_CT_NO_PORT_ID 0x01 266 #define SLI_CT_NO_PORT_NAME 0x02 267 #define SLI_CT_NO_NODE_NAME 0x03 268 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 269 #define SLI_CT_NO_IP_ADDRESS 0x05 270 #define SLI_CT_NO_IPA 0x06 271 #define SLI_CT_NO_FC4_TYPES 0x07 272 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 273 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 274 #define SLI_CT_NO_PORT_TYPE 0x0A 275 #define SLI_CT_ACCESS_DENIED 0x10 276 #define SLI_CT_INVALID_PORT_ID 0x11 277 #define SLI_CT_DATABASE_EMPTY 0x12 278 #define SLI_CT_APP_ID_NOT_AVAILABLE 0x40 279 280 /* 281 * Name Server Command Codes 282 */ 283 284 #define SLI_CTNS_GA_NXT 0x0100 285 #define SLI_CTNS_GPN_ID 0x0112 286 #define SLI_CTNS_GNN_ID 0x0113 287 #define SLI_CTNS_GCS_ID 0x0114 288 #define SLI_CTNS_GFT_ID 0x0117 289 #define SLI_CTNS_GSPN_ID 0x0118 290 #define SLI_CTNS_GPT_ID 0x011A 291 #define SLI_CTNS_GFF_ID 0x011F 292 #define SLI_CTNS_GID_PN 0x0121 293 #define SLI_CTNS_GID_NN 0x0131 294 #define SLI_CTNS_GIP_NN 0x0135 295 #define SLI_CTNS_GIPA_NN 0x0136 296 #define SLI_CTNS_GSNN_NN 0x0139 297 #define SLI_CTNS_GNN_IP 0x0153 298 #define SLI_CTNS_GIPA_IP 0x0156 299 #define SLI_CTNS_GID_FT 0x0171 300 #define SLI_CTNS_GID_FF 0x01F1 301 #define SLI_CTNS_GID_PT 0x01A1 302 #define SLI_CTNS_RPN_ID 0x0212 303 #define SLI_CTNS_RNN_ID 0x0213 304 #define SLI_CTNS_RCS_ID 0x0214 305 #define SLI_CTNS_RFT_ID 0x0217 306 #define SLI_CTNS_RSPN_ID 0x0218 307 #define SLI_CTNS_RPT_ID 0x021A 308 #define SLI_CTNS_RFF_ID 0x021F 309 #define SLI_CTNS_RIP_NN 0x0235 310 #define SLI_CTNS_RIPA_NN 0x0236 311 #define SLI_CTNS_RSNN_NN 0x0239 312 #define SLI_CTNS_DA_ID 0x0300 313 314 /* 315 * Port Types 316 */ 317 318 #define SLI_CTPT_N_PORT 0x01 319 #define SLI_CTPT_NL_PORT 0x02 320 #define SLI_CTPT_FNL_PORT 0x03 321 #define SLI_CTPT_IP 0x04 322 #define SLI_CTPT_FCP 0x08 323 #define SLI_CTPT_NVME 0x28 324 #define SLI_CTPT_NX_PORT 0x7F 325 #define SLI_CTPT_F_PORT 0x81 326 #define SLI_CTPT_FL_PORT 0x82 327 #define SLI_CTPT_E_PORT 0x84 328 329 #define SLI_CT_LAST_ENTRY 0x80000000 330 331 /* Fibre Channel Service Parameter definitions */ 332 333 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 334 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 335 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 336 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 337 338 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 339 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 340 #define FC_PH3 0x20 /* FC-PH-3 version */ 341 342 #define FF_FRAME_SIZE 2048 343 344 struct lpfc_name { 345 union { 346 struct { 347 #ifdef __BIG_ENDIAN_BITFIELD 348 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 349 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 350 8:11 of IEEE ext */ 351 #else /* __LITTLE_ENDIAN_BITFIELD */ 352 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 353 8:11 of IEEE ext */ 354 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 355 #endif 356 357 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 358 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 359 #define NAME_FC_TYPE 0x3 /* FC native name type */ 360 #define NAME_IP_TYPE 0x4 /* IP address */ 361 #define NAME_CCITT_TYPE 0xC 362 #define NAME_CCITT_GR_TYPE 0xE 363 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 364 extended Lsb */ 365 uint8_t IEEE[6]; /* FC IEEE address */ 366 } s; 367 uint8_t wwn[8]; 368 uint64_t name; 369 } u; 370 }; 371 372 struct csp { 373 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 374 uint8_t fcphLow; 375 uint8_t bbCreditMsb; 376 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */ 377 378 /* 379 * Word 1 Bit 31 in common service parameter is overloaded. 380 * Word 1 Bit 31 in FLOGI request is multiple NPort request 381 * Word 1 Bit 31 in FLOGI response is clean address bit 382 */ 383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 384 /* 385 * Word 1 Bit 30 in common service parameter is overloaded. 386 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 387 * Word 1 Bit 30 in PLOGI request is random offset 388 */ 389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 390 /* 391 * Word 1 Bit 29 in common service parameter is overloaded. 392 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment 393 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level 394 */ 395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */ 396 #ifdef __BIG_ENDIAN_BITFIELD 397 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 398 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 399 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 400 uint16_t fPort:1; /* FC Word 1, bit 28 */ 401 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 402 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 403 uint16_t multicast:1; /* FC Word 1, bit 25 */ 404 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 405 406 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 407 uint16_t simplex:1; /* FC Word 1, bit 22 */ 408 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 409 uint16_t dhd:1; /* FC Word 1, bit 18 */ 410 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 411 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 412 #else /* __LITTLE_ENDIAN_BITFIELD */ 413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */ 414 uint16_t multicast:1; /* FC Word 1, bit 25 */ 415 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 416 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 417 uint16_t fPort:1; /* FC Word 1, bit 28 */ 418 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 419 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 420 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 421 422 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 423 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 424 uint16_t dhd:1; /* FC Word 1, bit 18 */ 425 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 426 uint16_t simplex:1; /* FC Word 1, bit 22 */ 427 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */ 428 #endif 429 430 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 431 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 432 union { 433 struct { 434 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 435 436 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 437 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 438 439 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 440 } nPort; 441 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 442 } w2; 443 444 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 445 }; 446 447 struct class_parms { 448 #ifdef __BIG_ENDIAN_BITFIELD 449 uint8_t classValid:1; /* FC Word 0, bit 31 */ 450 uint8_t intermix:1; /* FC Word 0, bit 30 */ 451 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 452 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 453 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 454 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 455 #else /* __LITTLE_ENDIAN_BITFIELD */ 456 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 457 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 458 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 459 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 460 uint8_t intermix:1; /* FC Word 0, bit 30 */ 461 uint8_t classValid:1; /* FC Word 0, bit 31 */ 462 463 #endif 464 465 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 466 467 #ifdef __BIG_ENDIAN_BITFIELD 468 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 469 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 470 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 471 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 472 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 473 #else /* __LITTLE_ENDIAN_BITFIELD */ 474 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 475 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 476 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 477 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 478 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 479 #endif 480 481 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 482 483 #ifdef __BIG_ENDIAN_BITFIELD 484 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 485 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 486 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 487 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 488 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 489 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 490 #else /* __LITTLE_ENDIAN_BITFIELD */ 491 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 492 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 493 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 494 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 495 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 496 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 497 #endif 498 499 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 500 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 501 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 502 503 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 504 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 505 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 506 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 507 508 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 509 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 510 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 511 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 512 }; 513 514 #define FAPWWN_KEY_VENDOR 0x42524344 /*valid vendor version fawwpn key*/ 515 516 struct serv_parm { /* Structure is in Big Endian format */ 517 struct csp cmn; 518 struct lpfc_name portName; 519 struct lpfc_name nodeName; 520 struct class_parms cls1; 521 struct class_parms cls2; 522 struct class_parms cls3; 523 struct class_parms cls4; 524 union { 525 uint8_t vendorVersion[16]; 526 struct { 527 uint32_t vid; 528 #define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */ 529 uint32_t flags; 530 #define LPFC_VV_SUPPRESS_RSP 1 531 } vv; 532 } un; 533 }; 534 535 /* 536 * Virtual Fabric Tagging Header 537 */ 538 struct fc_vft_header { 539 uint32_t word0; 540 #define fc_vft_hdr_r_ctl_SHIFT 24 541 #define fc_vft_hdr_r_ctl_MASK 0xFF 542 #define fc_vft_hdr_r_ctl_WORD word0 543 #define fc_vft_hdr_ver_SHIFT 22 544 #define fc_vft_hdr_ver_MASK 0x3 545 #define fc_vft_hdr_ver_WORD word0 546 #define fc_vft_hdr_type_SHIFT 18 547 #define fc_vft_hdr_type_MASK 0xF 548 #define fc_vft_hdr_type_WORD word0 549 #define fc_vft_hdr_e_SHIFT 16 550 #define fc_vft_hdr_e_MASK 0x1 551 #define fc_vft_hdr_e_WORD word0 552 #define fc_vft_hdr_priority_SHIFT 13 553 #define fc_vft_hdr_priority_MASK 0x7 554 #define fc_vft_hdr_priority_WORD word0 555 #define fc_vft_hdr_vf_id_SHIFT 1 556 #define fc_vft_hdr_vf_id_MASK 0xFFF 557 #define fc_vft_hdr_vf_id_WORD word0 558 uint32_t word1; 559 #define fc_vft_hdr_hopct_SHIFT 24 560 #define fc_vft_hdr_hopct_MASK 0xFF 561 #define fc_vft_hdr_hopct_WORD word1 562 }; 563 564 #include <uapi/scsi/fc/fc_els.h> 565 566 /* 567 * Extended Link Service LS_COMMAND codes (Payload Word 0) 568 */ 569 #ifdef __BIG_ENDIAN_BITFIELD 570 #define ELS_CMD_MASK 0xffff0000 571 #define ELS_RSP_MASK 0xff000000 572 #define ELS_CMD_LS_RJT 0x01000000 573 #define ELS_CMD_ACC 0x02000000 574 #define ELS_CMD_PLOGI 0x03000000 575 #define ELS_CMD_FLOGI 0x04000000 576 #define ELS_CMD_LOGO 0x05000000 577 #define ELS_CMD_ABTX 0x06000000 578 #define ELS_CMD_RCS 0x07000000 579 #define ELS_CMD_RES 0x08000000 580 #define ELS_CMD_RSS 0x09000000 581 #define ELS_CMD_RSI 0x0A000000 582 #define ELS_CMD_ESTS 0x0B000000 583 #define ELS_CMD_ESTC 0x0C000000 584 #define ELS_CMD_ADVC 0x0D000000 585 #define ELS_CMD_RTV 0x0E000000 586 #define ELS_CMD_RLS 0x0F000000 587 #define ELS_CMD_ECHO 0x10000000 588 #define ELS_CMD_TEST 0x11000000 589 #define ELS_CMD_RRQ 0x12000000 590 #define ELS_CMD_REC 0x13000000 591 #define ELS_CMD_RDP 0x18000000 592 #define ELS_CMD_RDF 0x19000000 593 #define ELS_CMD_PRLI 0x20100014 594 #define ELS_CMD_NVMEPRLI 0x20140018 595 #define ELS_CMD_PRLO 0x21100014 596 #define ELS_CMD_PRLO_ACC 0x02100014 597 #define ELS_CMD_PDISC 0x50000000 598 #define ELS_CMD_FDISC 0x51000000 599 #define ELS_CMD_ADISC 0x52000000 600 #define ELS_CMD_FARP 0x54000000 601 #define ELS_CMD_FARPR 0x55000000 602 #define ELS_CMD_RPL 0x57000000 603 #define ELS_CMD_FAN 0x60000000 604 #define ELS_CMD_RSCN 0x61040000 605 #define ELS_CMD_RSCN_XMT 0x61040008 606 #define ELS_CMD_SCR 0x62000000 607 #define ELS_CMD_RNID 0x78000000 608 #define ELS_CMD_LIRR 0x7A000000 609 #define ELS_CMD_LCB 0x81000000 610 #define ELS_CMD_FPIN 0x16000000 611 #define ELS_CMD_QFPA 0xB0000000 612 #define ELS_CMD_UVEM 0xB1000000 613 #else /* __LITTLE_ENDIAN_BITFIELD */ 614 #define ELS_CMD_MASK 0xffff 615 #define ELS_RSP_MASK 0xff 616 #define ELS_CMD_LS_RJT 0x01 617 #define ELS_CMD_ACC 0x02 618 #define ELS_CMD_PLOGI 0x03 619 #define ELS_CMD_FLOGI 0x04 620 #define ELS_CMD_LOGO 0x05 621 #define ELS_CMD_ABTX 0x06 622 #define ELS_CMD_RCS 0x07 623 #define ELS_CMD_RES 0x08 624 #define ELS_CMD_RSS 0x09 625 #define ELS_CMD_RSI 0x0A 626 #define ELS_CMD_ESTS 0x0B 627 #define ELS_CMD_ESTC 0x0C 628 #define ELS_CMD_ADVC 0x0D 629 #define ELS_CMD_RTV 0x0E 630 #define ELS_CMD_RLS 0x0F 631 #define ELS_CMD_ECHO 0x10 632 #define ELS_CMD_TEST 0x11 633 #define ELS_CMD_RRQ 0x12 634 #define ELS_CMD_REC 0x13 635 #define ELS_CMD_RDP 0x18 636 #define ELS_CMD_RDF 0x19 637 #define ELS_CMD_PRLI 0x14001020 638 #define ELS_CMD_NVMEPRLI 0x18001420 639 #define ELS_CMD_PRLO 0x14001021 640 #define ELS_CMD_PRLO_ACC 0x14001002 641 #define ELS_CMD_PDISC 0x50 642 #define ELS_CMD_FDISC 0x51 643 #define ELS_CMD_ADISC 0x52 644 #define ELS_CMD_FARP 0x54 645 #define ELS_CMD_FARPR 0x55 646 #define ELS_CMD_RPL 0x57 647 #define ELS_CMD_FAN 0x60 648 #define ELS_CMD_RSCN 0x0461 649 #define ELS_CMD_RSCN_XMT 0x08000461 650 #define ELS_CMD_SCR 0x62 651 #define ELS_CMD_RNID 0x78 652 #define ELS_CMD_LIRR 0x7A 653 #define ELS_CMD_LCB 0x81 654 #define ELS_CMD_FPIN ELS_FPIN 655 #define ELS_CMD_QFPA 0xB0 656 #define ELS_CMD_UVEM 0xB1 657 #endif 658 659 /* 660 * LS_RJT Payload Definition 661 */ 662 663 struct ls_rjt { /* Structure is in Big Endian format */ 664 union { 665 uint32_t lsRjtError; 666 struct { 667 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 668 669 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 670 /* LS_RJT reason codes */ 671 #define LSRJT_INVALID_CMD 0x01 672 #define LSRJT_LOGICAL_ERR 0x03 673 #define LSRJT_LOGICAL_BSY 0x05 674 #define LSRJT_PROTOCOL_ERR 0x07 675 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 676 #define LSRJT_CMD_UNSUPPORTED 0x0B 677 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 678 679 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 680 /* LS_RJT reason explanation */ 681 #define LSEXP_NOTHING_MORE 0x00 682 #define LSEXP_SPARM_OPTIONS 0x01 683 #define LSEXP_SPARM_ICTL 0x03 684 #define LSEXP_SPARM_RCTL 0x05 685 #define LSEXP_SPARM_RCV_SIZE 0x07 686 #define LSEXP_SPARM_CONCUR_SEQ 0x09 687 #define LSEXP_SPARM_CREDIT 0x0B 688 #define LSEXP_INVALID_PNAME 0x0D 689 #define LSEXP_INVALID_NNAME 0x0E 690 #define LSEXP_INVALID_CSP 0x0F 691 #define LSEXP_INVALID_ASSOC_HDR 0x11 692 #define LSEXP_ASSOC_HDR_REQ 0x13 693 #define LSEXP_INVALID_O_SID 0x15 694 #define LSEXP_INVALID_OX_RX 0x17 695 #define LSEXP_CMD_IN_PROGRESS 0x19 696 #define LSEXP_PORT_LOGIN_REQ 0x1E 697 #define LSEXP_INVALID_NPORT_ID 0x1F 698 #define LSEXP_INVALID_SEQ_ID 0x21 699 #define LSEXP_INVALID_XCHG 0x23 700 #define LSEXP_INACTIVE_XCHG 0x25 701 #define LSEXP_RQ_REQUIRED 0x27 702 #define LSEXP_OUT_OF_RESOURCE 0x29 703 #define LSEXP_CANT_GIVE_DATA 0x2A 704 #define LSEXP_REQ_UNSUPPORTED 0x2C 705 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 706 } b; 707 } un; 708 }; 709 710 /* 711 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 712 */ 713 714 typedef struct _LOGO { /* Structure is in Big Endian format */ 715 union { 716 uint32_t nPortId32; /* Access nPortId as a word */ 717 struct { 718 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 719 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 720 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 721 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 722 } b; 723 } un; 724 struct lpfc_name portName; /* N_port name field */ 725 } LOGO; 726 727 /* 728 * FCP Login (PRLI Request / ACC) Payload Definition 729 */ 730 731 #define PRLX_PAGE_LEN 0x10 732 #define TPRLO_PAGE_LEN 0x14 733 734 typedef struct _PRLI { /* Structure is in Big Endian format */ 735 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 736 737 #define PRLI_FCP_TYPE 0x08 738 #define PRLI_NVME_TYPE 0x28 739 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 740 741 #ifdef __BIG_ENDIAN_BITFIELD 742 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 743 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 744 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 745 746 /* ACC = imagePairEstablished */ 747 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 748 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 749 #else /* __LITTLE_ENDIAN_BITFIELD */ 750 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 751 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 752 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 753 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 754 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 755 /* ACC = imagePairEstablished */ 756 #endif 757 758 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 759 #define PRLI_NO_RESOURCES 0x2 760 #define PRLI_INIT_INCOMPLETE 0x3 761 #define PRLI_NO_SUCH_PA 0x4 762 #define PRLI_PREDEF_CONFIG 0x5 763 #define PRLI_PARTIAL_SUCCESS 0x6 764 #define PRLI_INVALID_PAGE_CNT 0x7 765 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 766 767 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 768 769 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 770 771 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 772 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 773 774 #ifdef __BIG_ENDIAN_BITFIELD 775 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 776 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 777 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 778 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 779 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 780 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 781 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 782 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 783 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 784 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 785 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 786 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 787 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 788 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 789 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 790 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 791 #else /* __LITTLE_ENDIAN_BITFIELD */ 792 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 793 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 794 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 795 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 796 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 797 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 798 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 799 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 800 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 801 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 802 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 803 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 804 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 805 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 806 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 807 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 808 #endif 809 } PRLI; 810 811 /* 812 * FCP Logout (PRLO Request / ACC) Payload Definition 813 */ 814 815 typedef struct _PRLO { /* Structure is in Big Endian format */ 816 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 817 818 #define PRLO_FCP_TYPE 0x08 819 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 820 821 #ifdef __BIG_ENDIAN_BITFIELD 822 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 823 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 824 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 825 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 826 #else /* __LITTLE_ENDIAN_BITFIELD */ 827 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 828 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 829 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 830 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 831 #endif 832 833 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 834 #define PRLO_NO_SUCH_IMAGE 0x4 835 #define PRLO_INVALID_PAGE_CNT 0x7 836 837 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 838 839 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 840 841 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 842 843 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 844 } PRLO; 845 846 typedef struct _ADISC { /* Structure is in Big Endian format */ 847 uint32_t hardAL_PA; 848 struct lpfc_name portName; 849 struct lpfc_name nodeName; 850 uint32_t DID; 851 } __packed ADISC; 852 853 typedef struct _FARP { /* Structure is in Big Endian format */ 854 uint32_t Mflags:8; 855 uint32_t Odid:24; 856 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 857 action */ 858 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 859 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 860 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 861 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 862 supported */ 863 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 864 supported */ 865 uint32_t Rflags:8; 866 uint32_t Rdid:24; 867 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 868 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 869 struct lpfc_name OportName; 870 struct lpfc_name OnodeName; 871 struct lpfc_name RportName; 872 struct lpfc_name RnodeName; 873 uint8_t Oipaddr[16]; 874 uint8_t Ripaddr[16]; 875 } FARP; 876 877 typedef struct _FAN { /* Structure is in Big Endian format */ 878 uint32_t Fdid; 879 struct lpfc_name FportName; 880 struct lpfc_name FnodeName; 881 } __packed FAN; 882 883 typedef struct _SCR { /* Structure is in Big Endian format */ 884 uint8_t resvd1; 885 uint8_t resvd2; 886 uint8_t resvd3; 887 uint8_t Function; 888 #define SCR_FUNC_FABRIC 0x01 889 #define SCR_FUNC_NPORT 0x02 890 #define SCR_FUNC_FULL 0x03 891 #define SCR_CLEAR 0xff 892 } SCR; 893 894 typedef struct _RNID_TOP_DISC { 895 struct lpfc_name portName; 896 uint8_t resvd[8]; 897 uint32_t unitType; 898 #define RNID_HBA 0x7 899 #define RNID_HOST 0xa 900 #define RNID_DRIVER 0xd 901 uint32_t physPort; 902 uint32_t attachedNodes; 903 uint16_t ipVersion; 904 #define RNID_IPV4 0x1 905 #define RNID_IPV6 0x2 906 uint16_t UDPport; 907 uint8_t ipAddr[16]; 908 uint16_t resvd1; 909 uint16_t flags; 910 #define RNID_TD_SUPPORT 0x1 911 #define RNID_LP_VALID 0x2 912 } RNID_TOP_DISC; 913 914 typedef struct _RNID { /* Structure is in Big Endian format */ 915 uint8_t Format; 916 #define RNID_TOPOLOGY_DISC 0xdf 917 uint8_t CommonLen; 918 uint8_t resvd1; 919 uint8_t SpecificLen; 920 struct lpfc_name portName; 921 struct lpfc_name nodeName; 922 union { 923 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 924 } un; 925 } __packed RNID; 926 927 struct RLS { /* Structure is in Big Endian format */ 928 uint32_t rls; 929 #define rls_rsvd_SHIFT 24 930 #define rls_rsvd_MASK 0x000000ff 931 #define rls_rsvd_WORD rls 932 #define rls_did_SHIFT 0 933 #define rls_did_MASK 0x00ffffff 934 #define rls_did_WORD rls 935 }; 936 937 struct RLS_RSP { /* Structure is in Big Endian format */ 938 uint32_t linkFailureCnt; 939 uint32_t lossSyncCnt; 940 uint32_t lossSignalCnt; 941 uint32_t primSeqErrCnt; 942 uint32_t invalidXmitWord; 943 uint32_t crcCnt; 944 }; 945 946 struct RRQ { /* Structure is in Big Endian format */ 947 uint32_t rrq; 948 #define rrq_rsvd_SHIFT 24 949 #define rrq_rsvd_MASK 0x000000ff 950 #define rrq_rsvd_WORD rrq 951 #define rrq_did_SHIFT 0 952 #define rrq_did_MASK 0x00ffffff 953 #define rrq_did_WORD rrq 954 uint32_t rrq_exchg; 955 #define rrq_oxid_SHIFT 16 956 #define rrq_oxid_MASK 0xffff 957 #define rrq_oxid_WORD rrq_exchg 958 #define rrq_rxid_SHIFT 0 959 #define rrq_rxid_MASK 0xffff 960 #define rrq_rxid_WORD rrq_exchg 961 }; 962 963 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 964 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 965 966 struct RTV_RSP { /* Structure is in Big Endian format */ 967 uint32_t ratov; 968 uint32_t edtov; 969 uint32_t qtov; 970 #define qtov_rsvd0_SHIFT 28 971 #define qtov_rsvd0_MASK 0x0000000f 972 #define qtov_rsvd0_WORD qtov /* reserved */ 973 #define qtov_edtovres_SHIFT 27 974 #define qtov_edtovres_MASK 0x00000001 975 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 976 #define qtov__rsvd1_SHIFT 19 977 #define qtov_rsvd1_MASK 0x0000003f 978 #define qtov_rsvd1_WORD qtov /* reserved */ 979 #define qtov_rttov_SHIFT 18 980 #define qtov_rttov_MASK 0x00000001 981 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 982 #define qtov_rsvd2_SHIFT 0 983 #define qtov_rsvd2_MASK 0x0003ffff 984 #define qtov_rsvd2_WORD qtov /* reserved */ 985 }; 986 987 988 typedef struct _RPL { /* Structure is in Big Endian format */ 989 uint32_t maxsize; 990 uint32_t index; 991 } RPL; 992 993 typedef struct _PORT_NUM_BLK { 994 uint32_t portNum; 995 uint32_t portID; 996 struct lpfc_name portName; 997 } PORT_NUM_BLK; 998 999 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 1000 uint32_t listLen; 1001 uint32_t index; 1002 PORT_NUM_BLK port_num_blk; 1003 } RPL_RSP; 1004 1005 /* This is used for RSCN command */ 1006 typedef struct _D_ID { /* Structure is in Big Endian format */ 1007 union { 1008 uint32_t word; 1009 struct { 1010 #ifdef __BIG_ENDIAN_BITFIELD 1011 uint8_t resv; 1012 uint8_t domain; 1013 uint8_t area; 1014 uint8_t id; 1015 #else /* __LITTLE_ENDIAN_BITFIELD */ 1016 uint8_t id; 1017 uint8_t area; 1018 uint8_t domain; 1019 uint8_t resv; 1020 #endif 1021 } b; 1022 } un; 1023 } D_ID; 1024 1025 #define RSCN_ADDRESS_FORMAT_PORT 0x0 1026 #define RSCN_ADDRESS_FORMAT_AREA 0x1 1027 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 1028 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 1029 #define RSCN_ADDRESS_FORMAT_MASK 0x3 1030 1031 /* 1032 * Structure to define all ELS Payload types 1033 */ 1034 1035 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 1036 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 1037 uint8_t elsByte1; 1038 uint8_t elsByte2; 1039 uint8_t elsByte3; 1040 union { 1041 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1042 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1043 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1044 PRLI prli; /* Payload for PRLI/ACC */ 1045 PRLO prlo; /* Payload for PRLO/ACC */ 1046 ADISC adisc; /* Payload for ADISC/ACC */ 1047 FARP farp; /* Payload for FARP/ACC */ 1048 FAN fan; /* Payload for FAN */ 1049 SCR scr; /* Payload for SCR/ACC */ 1050 RNID rnid; /* Payload for RNID */ 1051 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1052 } un; 1053 } ELS_PKT; 1054 1055 /* 1056 * Link Cable Beacon (LCB) ELS Frame 1057 */ 1058 1059 struct fc_lcb_request_frame { 1060 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1061 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1062 #define LPFC_LCB_ON 0x1 1063 #define LPFC_LCB_OFF 0x2 1064 uint8_t reserved[2]; 1065 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1066 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1067 #define LPFC_LCB_GREEN 0x1 1068 #define LPFC_LCB_AMBER 0x2 1069 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1070 #define LCB_CAPABILITY_DURATION 1 1071 #define BEACON_VERSION_V1 1 1072 #define BEACON_VERSION_V0 0 1073 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1074 }; 1075 1076 /* 1077 * Link Cable Beacon (LCB) ELS Response Frame 1078 */ 1079 struct fc_lcb_res_frame { 1080 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1081 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1082 uint8_t reserved[2]; 1083 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */ 1084 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1085 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1086 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1087 }; 1088 1089 /* 1090 * Read Diagnostic Parameters (RDP) ELS frame. 1091 */ 1092 #define SFF_PG0_IDENT_SFP 0x3 1093 1094 #define SFP_FLAG_PT_OPTICAL 0x0 1095 #define SFP_FLAG_PT_SWLASER 0x01 1096 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1097 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1098 #define SFP_FLAG_PT_MASK 0x0F 1099 #define SFP_FLAG_PT_SHIFT 0 1100 1101 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1102 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1103 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1104 1105 #define SFP_FLAG_IS_DESC_VALID 0x01 1106 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1107 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1108 1109 #define SFP_FLAG_CT_UNKNOWN 0x0 1110 #define SFP_FLAG_CT_SFP_PLUS 0x01 1111 #define SFP_FLAG_CT_MASK 0x3C 1112 #define SFP_FLAG_CT_SHIFT 6 1113 1114 struct fc_rdp_port_name_info { 1115 uint8_t wwnn[8]; 1116 uint8_t wwpn[8]; 1117 }; 1118 1119 1120 /* 1121 * Link Error Status Block Structure (FC-FS-3) for RDP 1122 * This similar to RPS ELS 1123 */ 1124 struct fc_link_status { 1125 uint32_t link_failure_cnt; 1126 uint32_t loss_of_synch_cnt; 1127 uint32_t loss_of_signal_cnt; 1128 uint32_t primitive_seq_proto_err; 1129 uint32_t invalid_trans_word; 1130 uint32_t invalid_crc_cnt; 1131 1132 }; 1133 1134 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1135 struct fc_rdp_port_name_desc { 1136 uint32_t tag; /* 0001 0003h */ 1137 uint32_t length; /* set to size of payload struct */ 1138 struct fc_rdp_port_name_info port_names; 1139 }; 1140 1141 1142 struct fc_rdp_fec_info { 1143 uint32_t CorrectedBlocks; 1144 uint32_t UncorrectableBlocks; 1145 }; 1146 1147 #define RDP_FEC_DESC_TAG 0x00010005 1148 struct fc_fec_rdp_desc { 1149 uint32_t tag; 1150 uint32_t length; 1151 struct fc_rdp_fec_info info; 1152 }; 1153 1154 struct fc_rdp_link_error_status_payload_info { 1155 struct fc_link_status link_status; /* 24 bytes */ 1156 uint32_t port_type; /* bits 31-30 only */ 1157 }; 1158 1159 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1160 struct fc_rdp_link_error_status_desc { 1161 uint32_t tag; /* 0001 0002h */ 1162 uint32_t length; /* set to size of payload struct */ 1163 struct fc_rdp_link_error_status_payload_info info; 1164 }; 1165 1166 #define VN_PT_PHY_UNKNOWN 0x00 1167 #define VN_PT_PHY_PF_PORT 0x01 1168 #define VN_PT_PHY_ETH_MAC 0x10 1169 #define VN_PT_PHY_SHIFT 30 1170 1171 #define RDP_PS_1GB 0x8000 1172 #define RDP_PS_2GB 0x4000 1173 #define RDP_PS_4GB 0x2000 1174 #define RDP_PS_10GB 0x1000 1175 #define RDP_PS_8GB 0x0800 1176 #define RDP_PS_16GB 0x0400 1177 #define RDP_PS_32GB 0x0200 1178 #define RDP_PS_64GB 0x0100 1179 #define RDP_PS_128GB 0x0080 1180 #define RDP_PS_256GB 0x0040 1181 1182 #define RDP_CAP_USER_CONFIGURED 0x0002 1183 #define RDP_CAP_UNKNOWN 0x0001 1184 #define RDP_PS_UNKNOWN 0x0002 1185 #define RDP_PS_NOT_ESTABLISHED 0x0001 1186 1187 struct fc_rdp_port_speed { 1188 uint16_t capabilities; 1189 uint16_t speed; 1190 }; 1191 1192 struct fc_rdp_port_speed_info { 1193 struct fc_rdp_port_speed port_speed; 1194 }; 1195 1196 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1197 struct fc_rdp_port_speed_desc { 1198 uint32_t tag; /* 00010001h */ 1199 uint32_t length; /* set to size of payload struct */ 1200 struct fc_rdp_port_speed_info info; 1201 }; 1202 1203 #define RDP_NPORT_ID_SIZE 4 1204 #define RDP_N_PORT_DESC_TAG 0x00000003 1205 struct fc_rdp_nport_desc { 1206 uint32_t tag; /* 0000 0003h, big endian */ 1207 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1208 uint32_t nport_id : 12; 1209 uint32_t reserved : 8; 1210 }; 1211 1212 1213 struct fc_rdp_link_service_info { 1214 uint32_t els_req; /* Request payload word 0 value.*/ 1215 }; 1216 1217 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1218 struct fc_rdp_link_service_desc { 1219 uint32_t tag; /* Descriptor tag 1 */ 1220 uint32_t length; /* set to size of payload struct. */ 1221 struct fc_rdp_link_service_info payload; 1222 /* must be ELS req Word 0(0x18) */ 1223 }; 1224 1225 struct fc_rdp_sfp_info { 1226 uint16_t temperature; 1227 uint16_t vcc; 1228 uint16_t tx_bias; 1229 uint16_t tx_power; 1230 uint16_t rx_power; 1231 uint16_t flags; 1232 }; 1233 1234 #define RDP_SFP_DESC_TAG 0x00010000 1235 struct fc_rdp_sfp_desc { 1236 uint32_t tag; 1237 uint32_t length; /* set to size of sfp_info struct */ 1238 struct fc_rdp_sfp_info sfp_info; 1239 }; 1240 1241 /* Buffer Credit Descriptor */ 1242 struct fc_rdp_bbc_info { 1243 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1244 uint32_t attached_port_bbc; 1245 uint32_t rtt; /* Round trip time */ 1246 }; 1247 #define RDP_BBC_DESC_TAG 0x00010006 1248 struct fc_rdp_bbc_desc { 1249 uint32_t tag; 1250 uint32_t length; 1251 struct fc_rdp_bbc_info bbc_info; 1252 }; 1253 1254 /* Optical Element Type Transgression Flags */ 1255 #define RDP_OET_LOW_WARNING 0x1 1256 #define RDP_OET_HIGH_WARNING 0x2 1257 #define RDP_OET_LOW_ALARM 0x4 1258 #define RDP_OET_HIGH_ALARM 0x8 1259 1260 #define RDP_OED_TEMPERATURE 0x1 1261 #define RDP_OED_VOLTAGE 0x2 1262 #define RDP_OED_TXBIAS 0x3 1263 #define RDP_OED_TXPOWER 0x4 1264 #define RDP_OED_RXPOWER 0x5 1265 1266 #define RDP_OED_TYPE_SHIFT 28 1267 /* Optical Element Data descriptor */ 1268 struct fc_rdp_oed_info { 1269 uint16_t hi_alarm; 1270 uint16_t lo_alarm; 1271 uint16_t hi_warning; 1272 uint16_t lo_warning; 1273 uint32_t function_flags; 1274 }; 1275 #define RDP_OED_DESC_TAG 0x00010007 1276 struct fc_rdp_oed_sfp_desc { 1277 uint32_t tag; 1278 uint32_t length; 1279 struct fc_rdp_oed_info oed_info; 1280 }; 1281 1282 /* Optical Product Data descriptor */ 1283 struct fc_rdp_opd_sfp_info { 1284 uint8_t vendor_name[16]; 1285 uint8_t model_number[16]; 1286 uint8_t serial_number[16]; 1287 uint8_t revision[4]; 1288 uint8_t date[8]; 1289 }; 1290 1291 #define RDP_OPD_DESC_TAG 0x00010008 1292 struct fc_rdp_opd_sfp_desc { 1293 uint32_t tag; 1294 uint32_t length; 1295 struct fc_rdp_opd_sfp_info opd_info; 1296 }; 1297 1298 struct fc_rdp_req_frame { 1299 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1300 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1301 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1302 }; 1303 1304 1305 struct fc_rdp_res_frame { 1306 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1307 uint32_t length; /* FC Word 1 */ 1308 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1309 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1310 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */ 1311 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */ 1312 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */ 1313 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */ 1314 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/ 1315 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/ 1316 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/ 1317 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/ 1318 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/ 1319 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/ 1320 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/ 1321 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/ 1322 }; 1323 1324 1325 /* UVEM */ 1326 1327 #define LPFC_UVEM_SIZE 60 1328 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16 1329 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20 1330 1331 #define VEM_ID_DESC_TAG 0x0001000A 1332 struct lpfc_vem_id_desc { 1333 uint32_t tag; 1334 uint32_t length; 1335 uint8_t vem_id[16]; 1336 }; 1337 1338 #define LPFC_QFPA_SIZE 4 1339 1340 #define INSTANTIATED_VE_DESC_TAG 0x0001000B 1341 struct instantiated_ve_desc { 1342 uint32_t tag; 1343 uint32_t length; 1344 uint8_t global_vem_id[16]; 1345 uint32_t word6; 1346 #define lpfc_instantiated_local_id_SHIFT 0 1347 #define lpfc_instantiated_local_id_MASK 0x000000ff 1348 #define lpfc_instantiated_local_id_WORD word6 1349 #define lpfc_instantiated_nport_id_SHIFT 8 1350 #define lpfc_instantiated_nport_id_MASK 0x00ffffff 1351 #define lpfc_instantiated_nport_id_WORD word6 1352 }; 1353 1354 #define DEINSTANTIATED_VE_DESC_TAG 0x0001000C 1355 struct deinstantiated_ve_desc { 1356 uint32_t tag; 1357 uint32_t length; 1358 uint8_t global_vem_id[16]; 1359 uint32_t word6; 1360 #define lpfc_deinstantiated_nport_id_SHIFT 0 1361 #define lpfc_deinstantiated_nport_id_MASK 0x000000ff 1362 #define lpfc_deinstantiated_nport_id_WORD word6 1363 #define lpfc_deinstantiated_local_id_SHIFT 24 1364 #define lpfc_deinstantiated_local_id_MASK 0x00ffffff 1365 #define lpfc_deinstantiated_local_id_WORD word6 1366 }; 1367 1368 /* Query Fabric Priority Allocation Response */ 1369 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12 1370 1371 struct priority_range_desc { 1372 uint32_t tag; 1373 uint32_t length; 1374 uint8_t lo_range; 1375 uint8_t hi_range; 1376 uint8_t qos_priority; 1377 uint8_t local_ve_id; 1378 }; 1379 1380 struct fc_qfpa_res { 1381 uint32_t reply_sequence; /* LS_ACC or LS_RJT */ 1382 uint32_t length; /* FC Word 1 */ 1383 struct priority_range_desc desc[1]; 1384 }; 1385 1386 /* Application Server command code */ 1387 /* VMID */ 1388 1389 #define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */ 1390 1391 #define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */ 1392 #define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */ 1393 #define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */ 1394 /* for Nport */ 1395 #define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */ 1396 /* for Nport */ 1397 #define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */ 1398 #define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */ 1399 /* Identifier */ 1400 #define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */ 1401 /* Identifier */ 1402 1403 struct entity_id_object { 1404 uint8_t entity_id_len; 1405 uint8_t entity_id[255]; /* VM UUID */ 1406 }; 1407 1408 struct app_id_object { 1409 uint32_t port_id; 1410 uint32_t app_id; 1411 struct entity_id_object obj; 1412 }; 1413 1414 struct lpfc_vmid_rapp_ident_list { 1415 uint32_t no_of_objects; 1416 struct entity_id_object obj[1]; 1417 }; 1418 1419 struct lpfc_vmid_dapp_ident_list { 1420 uint32_t no_of_objects; 1421 struct entity_id_object obj[1]; 1422 }; 1423 1424 #define GALLAPPIA_ID_LAST 0x80 1425 struct lpfc_vmid_gallapp_ident_list { 1426 uint8_t control; 1427 uint8_t reserved[3]; 1428 struct app_id_object app_id; 1429 }; 1430 1431 #define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1432 #define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4) 1433 #define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1434 #define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4) 1435 1436 /******** FDMI ********/ 1437 1438 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1439 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1440 1441 /* Definitions for HBA / Port attribute entries */ 1442 1443 /* Attribute Entry */ 1444 struct lpfc_fdmi_attr_entry { 1445 union { 1446 uint32_t AttrInt; 1447 uint8_t AttrTypes[32]; 1448 uint8_t AttrString[256]; 1449 struct lpfc_name AttrWWN; 1450 } un; 1451 }; 1452 1453 struct lpfc_fdmi_attr_def { /* Defined in TLV format */ 1454 /* Structure is in Big Endian format */ 1455 uint32_t AttrType:16; 1456 uint32_t AttrLen:16; 1457 /* Marks start of Value (ATTRIBUTE_ENTRY) */ 1458 struct lpfc_fdmi_attr_entry AttrValue; 1459 } __packed; 1460 1461 /* 1462 * HBA Attribute Block 1463 */ 1464 struct lpfc_fdmi_attr_block { 1465 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1466 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */ 1467 }; 1468 1469 /* 1470 * Port Entry 1471 */ 1472 struct lpfc_fdmi_port_entry { 1473 struct lpfc_name PortName; 1474 }; 1475 1476 /* 1477 * HBA Identifier 1478 */ 1479 struct lpfc_fdmi_hba_ident { 1480 struct lpfc_name PortName; 1481 }; 1482 1483 /* 1484 * Registered Port List Format 1485 */ 1486 struct lpfc_fdmi_reg_port_list { 1487 uint32_t EntryCnt; 1488 struct lpfc_fdmi_port_entry pe; 1489 } __packed; 1490 1491 /* 1492 * Register HBA(RHBA) 1493 */ 1494 struct lpfc_fdmi_reg_hba { 1495 struct lpfc_fdmi_hba_ident hi; 1496 struct lpfc_fdmi_reg_port_list rpl; 1497 }; 1498 1499 /******** MI MIB ********/ 1500 #define SLI_CT_MIB_Subtypes 0x11 1501 1502 /* 1503 * Register HBA Attributes (RHAT) 1504 */ 1505 struct lpfc_fdmi_reg_hbaattr { 1506 struct lpfc_name HBA_PortName; 1507 struct lpfc_fdmi_attr_block ab; 1508 }; 1509 1510 /* 1511 * Register Port Attributes (RPA) 1512 */ 1513 struct lpfc_fdmi_reg_portattr { 1514 struct lpfc_name PortName; 1515 struct lpfc_fdmi_attr_block ab; 1516 }; 1517 1518 /* 1519 * HBA MAnagement Operations Command Codes 1520 */ 1521 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1522 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1523 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1524 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1525 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1526 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1527 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1528 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1529 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1530 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1531 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1532 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1533 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1534 1535 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1536 1537 /* 1538 * HBA Attribute Types 1539 */ 1540 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1541 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1542 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1543 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1544 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1545 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1546 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1547 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1548 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1549 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1550 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1551 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1552 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1553 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1554 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1555 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1556 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1557 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1558 1559 /* Bit mask for all individual HBA attributes */ 1560 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1561 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1562 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1563 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1564 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1565 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1566 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1567 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1568 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1569 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1570 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1571 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1572 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1573 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1574 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1575 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1576 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1577 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1578 1579 /* Bit mask for FDMI-1 defined HBA attributes */ 1580 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1581 1582 /* Bit mask for FDMI-2 defined HBA attributes */ 1583 /* Skip vendor_info and bios_state */ 1584 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1585 1586 /* 1587 * Port Attribute Types 1588 */ 1589 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1590 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1591 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1592 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1593 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1594 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1595 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1596 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1597 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1598 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1599 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1600 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1601 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1602 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1603 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1604 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1605 #define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */ 1606 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1607 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1608 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1609 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1610 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1611 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1612 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1613 1614 /* Bit mask for all individual PORT attributes */ 1615 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1616 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1617 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1618 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1619 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1620 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1621 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1622 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1623 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1624 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1625 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1626 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1627 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1628 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1629 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1630 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1631 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1632 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1633 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1634 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1635 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1636 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1637 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1638 #define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */ 1639 1640 /* Bit mask for FDMI-1 defined PORT attributes */ 1641 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1642 1643 /* Bit mask for FDMI-2 defined PORT attributes */ 1644 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1645 1646 /* Bit mask for Smart SAN defined PORT attributes */ 1647 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1648 1649 /* Defines for PORT port state attribute */ 1650 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1651 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1652 1653 /* Defines for PORT port type attribute */ 1654 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1655 #define LPFC_FDMI_PORTTYPE_NPORT 1 1656 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1657 1658 /* 1659 * Begin HBA configuration parameters. 1660 * The PCI configuration register BAR assignments are: 1661 * BAR0, offset 0x10 - SLIM base memory address 1662 * BAR1, offset 0x14 - SLIM base memory high address 1663 * BAR2, offset 0x18 - REGISTER base memory address 1664 * BAR3, offset 0x1c - REGISTER base memory high address 1665 * BAR4, offset 0x20 - BIU I/O registers 1666 * BAR5, offset 0x24 - REGISTER base io high address 1667 */ 1668 1669 /* Number of rings currently used and available. */ 1670 #define MAX_SLI3_CONFIGURED_RINGS 3 1671 #define MAX_SLI3_RINGS 4 1672 1673 /* IOCB / Mailbox is owned by FireFly */ 1674 #define OWN_CHIP 1 1675 1676 /* IOCB / Mailbox is owned by Host */ 1677 #define OWN_HOST 0 1678 1679 /* Number of 4-byte words in an IOCB. */ 1680 #define IOCB_WORD_SZ 8 1681 1682 /* network headers for Dfctl field */ 1683 #define FC_NET_HDR 0x20 1684 1685 /* Start FireFly Register definitions */ 1686 #define PCI_VENDOR_ID_EMULEX 0x10df 1687 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1688 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1689 #define PCI_DEVICE_ID_BALIUS 0xe131 1690 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1691 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1692 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1693 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1694 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1695 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1696 #define PCI_DEVICE_ID_LANCER_G7_FC 0xf400 1697 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500 1698 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1699 #define PCI_DEVICE_ID_SAT_MID 0xf015 1700 #define PCI_DEVICE_ID_RFLY 0xf095 1701 #define PCI_DEVICE_ID_PFLY 0xf098 1702 #define PCI_DEVICE_ID_LP101 0xf0a1 1703 #define PCI_DEVICE_ID_TFLY 0xf0a5 1704 #define PCI_DEVICE_ID_BSMB 0xf0d1 1705 #define PCI_DEVICE_ID_BMID 0xf0d5 1706 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1707 #define PCI_DEVICE_ID_ZMID 0xf0e5 1708 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1709 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1710 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1711 #define PCI_DEVICE_ID_SAT 0xf100 1712 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1713 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1714 #define PCI_DEVICE_ID_FALCON 0xf180 1715 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1716 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1717 #define PCI_DEVICE_ID_CENTAUR 0xf900 1718 #define PCI_DEVICE_ID_PEGASUS 0xf980 1719 #define PCI_DEVICE_ID_THOR 0xfa00 1720 #define PCI_DEVICE_ID_VIPER 0xfb00 1721 #define PCI_DEVICE_ID_LP10000S 0xfc00 1722 #define PCI_DEVICE_ID_LP11000S 0xfc10 1723 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1724 #define PCI_DEVICE_ID_SAT_S 0xfc40 1725 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1726 #define PCI_DEVICE_ID_HELIOS 0xfd00 1727 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1728 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1729 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1730 #define PCI_DEVICE_ID_HORNET 0xfe05 1731 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1732 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1733 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1734 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1735 #define PCI_DEVICE_ID_TOMCAT 0x0714 1736 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1737 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1738 1739 #define JEDEC_ID_ADDRESS 0x0080001c 1740 #define FIREFLY_JEDEC_ID 0x1ACC 1741 #define SUPERFLY_JEDEC_ID 0x0020 1742 #define DRAGONFLY_JEDEC_ID 0x0021 1743 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1744 #define CENTAUR_2G_JEDEC_ID 0x0026 1745 #define CENTAUR_1G_JEDEC_ID 0x0028 1746 #define PEGASUS_ORION_JEDEC_ID 0x0036 1747 #define PEGASUS_JEDEC_ID 0x0038 1748 #define THOR_JEDEC_ID 0x0012 1749 #define HELIOS_JEDEC_ID 0x0364 1750 #define ZEPHYR_JEDEC_ID 0x0577 1751 #define VIPER_JEDEC_ID 0x4838 1752 #define SATURN_JEDEC_ID 0x1004 1753 #define HORNET_JDEC_ID 0x2057706D 1754 1755 #define JEDEC_ID_MASK 0x0FFFF000 1756 #define JEDEC_ID_SHIFT 12 1757 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1758 1759 typedef struct { /* FireFly BIU registers */ 1760 uint32_t hostAtt; /* See definitions for Host Attention 1761 register */ 1762 uint32_t chipAtt; /* See definitions for Chip Attention 1763 register */ 1764 uint32_t hostStatus; /* See definitions for Host Status register */ 1765 uint32_t hostControl; /* See definitions for Host Control register */ 1766 uint32_t buiConfig; /* See definitions for BIU configuration 1767 register */ 1768 } FF_REGS; 1769 1770 /* IO Register size in bytes */ 1771 #define FF_REG_AREA_SIZE 256 1772 1773 /* Host Attention Register */ 1774 1775 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1776 1777 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1778 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1779 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1780 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1781 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1782 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1783 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1784 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1785 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1786 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1787 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1788 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1789 #define HA_LATT 0x20000000 /* Bit 29 */ 1790 #define HA_MBATT 0x40000000 /* Bit 30 */ 1791 #define HA_ERATT 0x80000000 /* Bit 31 */ 1792 1793 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1794 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1795 #define HA_RXATT 0x00000008 /* Bit 3 */ 1796 #define HA_RXMASK 0x0000000f 1797 1798 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1799 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1800 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1801 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1802 1803 #define HA_R0_POS 3 1804 #define HA_R1_POS 7 1805 #define HA_R2_POS 11 1806 #define HA_R3_POS 15 1807 #define HA_LE_POS 29 1808 #define HA_MB_POS 30 1809 #define HA_ER_POS 31 1810 /* Chip Attention Register */ 1811 1812 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1813 1814 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1815 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1816 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1817 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1818 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1819 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1820 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1821 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1822 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1823 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1824 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1825 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1826 #define CA_MBATT 0x40000000 /* Bit 30 */ 1827 1828 /* Host Status Register */ 1829 1830 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1831 1832 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1833 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1834 #define HS_FFER8 0x01000000 /* Bit 24 */ 1835 #define HS_FFER7 0x02000000 /* Bit 25 */ 1836 #define HS_FFER6 0x04000000 /* Bit 26 */ 1837 #define HS_FFER5 0x08000000 /* Bit 27 */ 1838 #define HS_FFER4 0x10000000 /* Bit 28 */ 1839 #define HS_FFER3 0x20000000 /* Bit 29 */ 1840 #define HS_FFER2 0x40000000 /* Bit 30 */ 1841 #define HS_FFER1 0x80000000 /* Bit 31 */ 1842 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1843 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1844 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1845 /* Host Control Register */ 1846 1847 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1848 1849 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1850 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1851 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1852 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1853 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1854 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1855 #define HC_INITMB 0x04000000 /* Bit 26 */ 1856 #define HC_INITFF 0x08000000 /* Bit 27 */ 1857 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1858 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1859 1860 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1861 #define MSIX_DFLT_ID 0 1862 #define MSIX_RNG0_ID 0 1863 #define MSIX_RNG1_ID 1 1864 #define MSIX_RNG2_ID 2 1865 #define MSIX_RNG3_ID 3 1866 1867 #define MSIX_LINK_ID 4 1868 #define MSIX_MBOX_ID 5 1869 1870 #define MSIX_SPARE0_ID 6 1871 #define MSIX_SPARE1_ID 7 1872 1873 /* Mailbox Commands */ 1874 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1875 #define MBX_LOAD_SM 0x01 1876 #define MBX_READ_NV 0x02 1877 #define MBX_WRITE_NV 0x03 1878 #define MBX_RUN_BIU_DIAG 0x04 1879 #define MBX_INIT_LINK 0x05 1880 #define MBX_DOWN_LINK 0x06 1881 #define MBX_CONFIG_LINK 0x07 1882 #define MBX_CONFIG_RING 0x09 1883 #define MBX_RESET_RING 0x0A 1884 #define MBX_READ_CONFIG 0x0B 1885 #define MBX_READ_RCONFIG 0x0C 1886 #define MBX_READ_SPARM 0x0D 1887 #define MBX_READ_STATUS 0x0E 1888 #define MBX_READ_RPI 0x0F 1889 #define MBX_READ_XRI 0x10 1890 #define MBX_READ_REV 0x11 1891 #define MBX_READ_LNK_STAT 0x12 1892 #define MBX_REG_LOGIN 0x13 1893 #define MBX_UNREG_LOGIN 0x14 1894 #define MBX_CLEAR_LA 0x16 1895 #define MBX_DUMP_MEMORY 0x17 1896 #define MBX_DUMP_CONTEXT 0x18 1897 #define MBX_RUN_DIAGS 0x19 1898 #define MBX_RESTART 0x1A 1899 #define MBX_UPDATE_CFG 0x1B 1900 #define MBX_DOWN_LOAD 0x1C 1901 #define MBX_DEL_LD_ENTRY 0x1D 1902 #define MBX_RUN_PROGRAM 0x1E 1903 #define MBX_SET_MASK 0x20 1904 #define MBX_SET_VARIABLE 0x21 1905 #define MBX_UNREG_D_ID 0x23 1906 #define MBX_KILL_BOARD 0x24 1907 #define MBX_CONFIG_FARP 0x25 1908 #define MBX_BEACON 0x2A 1909 #define MBX_CONFIG_MSI 0x30 1910 #define MBX_HEARTBEAT 0x31 1911 #define MBX_WRITE_VPARMS 0x32 1912 #define MBX_ASYNCEVT_ENABLE 0x33 1913 #define MBX_READ_EVENT_LOG_STATUS 0x37 1914 #define MBX_READ_EVENT_LOG 0x38 1915 #define MBX_WRITE_EVENT_LOG 0x39 1916 1917 #define MBX_PORT_CAPABILITIES 0x3B 1918 #define MBX_PORT_IOV_CONTROL 0x3C 1919 1920 #define MBX_CONFIG_HBQ 0x7C 1921 #define MBX_LOAD_AREA 0x81 1922 #define MBX_RUN_BIU_DIAG64 0x84 1923 #define MBX_CONFIG_PORT 0x88 1924 #define MBX_READ_SPARM64 0x8D 1925 #define MBX_READ_RPI64 0x8F 1926 #define MBX_REG_LOGIN64 0x93 1927 #define MBX_READ_TOPOLOGY 0x95 1928 #define MBX_REG_VPI 0x96 1929 #define MBX_UNREG_VPI 0x97 1930 1931 #define MBX_WRITE_WWN 0x98 1932 #define MBX_SET_DEBUG 0x99 1933 #define MBX_LOAD_EXP_ROM 0x9C 1934 #define MBX_SLI4_CONFIG 0x9B 1935 #define MBX_SLI4_REQ_FTRS 0x9D 1936 #define MBX_MAX_CMDS 0x9E 1937 #define MBX_RESUME_RPI 0x9E 1938 #define MBX_SLI2_CMD_MASK 0x80 1939 #define MBX_REG_VFI 0x9F 1940 #define MBX_REG_FCFI 0xA0 1941 #define MBX_UNREG_VFI 0xA1 1942 #define MBX_UNREG_FCFI 0xA2 1943 #define MBX_INIT_VFI 0xA3 1944 #define MBX_INIT_VPI 0xA4 1945 #define MBX_ACCESS_VDATA 0xA5 1946 #define MBX_REG_FCFI_MRQ 0xAF 1947 1948 #define MBX_AUTH_PORT 0xF8 1949 #define MBX_SECURITY_MGMT 0xF9 1950 1951 /* IOCB Commands */ 1952 1953 #define CMD_RCV_SEQUENCE_CX 0x01 1954 #define CMD_XMIT_SEQUENCE_CR 0x02 1955 #define CMD_XMIT_SEQUENCE_CX 0x03 1956 #define CMD_XMIT_BCAST_CN 0x04 1957 #define CMD_XMIT_BCAST_CX 0x05 1958 #define CMD_QUE_RING_BUF_CN 0x06 1959 #define CMD_QUE_XRI_BUF_CX 0x07 1960 #define CMD_IOCB_CONTINUE_CN 0x08 1961 #define CMD_RET_XRI_BUF_CX 0x09 1962 #define CMD_ELS_REQUEST_CR 0x0A 1963 #define CMD_ELS_REQUEST_CX 0x0B 1964 #define CMD_RCV_ELS_REQ_CX 0x0D 1965 #define CMD_ABORT_XRI_CN 0x0E 1966 #define CMD_ABORT_XRI_CX 0x0F 1967 #define CMD_CLOSE_XRI_CN 0x10 1968 #define CMD_CLOSE_XRI_CX 0x11 1969 #define CMD_CREATE_XRI_CR 0x12 1970 #define CMD_CREATE_XRI_CX 0x13 1971 #define CMD_GET_RPI_CN 0x14 1972 #define CMD_XMIT_ELS_RSP_CX 0x15 1973 #define CMD_GET_RPI_CR 0x16 1974 #define CMD_XRI_ABORTED_CX 0x17 1975 #define CMD_FCP_IWRITE_CR 0x18 1976 #define CMD_FCP_IWRITE_CX 0x19 1977 #define CMD_FCP_IREAD_CR 0x1A 1978 #define CMD_FCP_IREAD_CX 0x1B 1979 #define CMD_FCP_ICMND_CR 0x1C 1980 #define CMD_FCP_ICMND_CX 0x1D 1981 #define CMD_FCP_TSEND_CX 0x1F 1982 #define CMD_FCP_TRECEIVE_CX 0x21 1983 #define CMD_FCP_TRSP_CX 0x23 1984 #define CMD_FCP_AUTO_TRSP_CX 0x29 1985 1986 #define CMD_ADAPTER_MSG 0x20 1987 #define CMD_ADAPTER_DUMP 0x22 1988 1989 /* SLI_2 IOCB Command Set */ 1990 1991 #define CMD_ASYNC_STATUS 0x7C 1992 #define CMD_RCV_SEQUENCE64_CX 0x81 1993 #define CMD_XMIT_SEQUENCE64_CR 0x82 1994 #define CMD_XMIT_SEQUENCE64_CX 0x83 1995 #define CMD_XMIT_BCAST64_CN 0x84 1996 #define CMD_XMIT_BCAST64_CX 0x85 1997 #define CMD_QUE_RING_BUF64_CN 0x86 1998 #define CMD_QUE_XRI_BUF64_CX 0x87 1999 #define CMD_IOCB_CONTINUE64_CN 0x88 2000 #define CMD_RET_XRI_BUF64_CX 0x89 2001 #define CMD_ELS_REQUEST64_CR 0x8A 2002 #define CMD_ELS_REQUEST64_CX 0x8B 2003 #define CMD_ABORT_MXRI64_CN 0x8C 2004 #define CMD_RCV_ELS_REQ64_CX 0x8D 2005 #define CMD_XMIT_ELS_RSP64_CX 0x95 2006 #define CMD_XMIT_BLS_RSP64_CX 0x97 2007 #define CMD_FCP_IWRITE64_CR 0x98 2008 #define CMD_FCP_IWRITE64_CX 0x99 2009 #define CMD_FCP_IREAD64_CR 0x9A 2010 #define CMD_FCP_IREAD64_CX 0x9B 2011 #define CMD_FCP_ICMND64_CR 0x9C 2012 #define CMD_FCP_ICMND64_CX 0x9D 2013 #define CMD_FCP_TSEND64_CX 0x9F 2014 #define CMD_FCP_TRECEIVE64_CX 0xA1 2015 #define CMD_FCP_TRSP64_CX 0xA3 2016 2017 #define CMD_QUE_XRI64_CX 0xB3 2018 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 2019 #define CMD_IOCB_RCV_ELS64_CX 0xB7 2020 #define CMD_IOCB_RET_XRI64_CX 0xB9 2021 #define CMD_IOCB_RCV_CONT64_CX 0xBB 2022 2023 #define CMD_GEN_REQUEST64_CR 0xC2 2024 #define CMD_GEN_REQUEST64_CX 0xC3 2025 2026 /* Unhandled SLI-3 Commands */ 2027 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 2028 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 2029 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 2030 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 2031 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 2032 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 2033 #define CMD_IOCB_RET_HBQE64_CN 0xCA 2034 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 2035 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 2036 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 2037 #define CMD_IOCB_LOGENTRY_CN 0x94 2038 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 2039 2040 /* Data Security SLI Commands */ 2041 #define DSSCMD_IWRITE64_CR 0xF8 2042 #define DSSCMD_IWRITE64_CX 0xF9 2043 #define DSSCMD_IREAD64_CR 0xFA 2044 #define DSSCMD_IREAD64_CX 0xFB 2045 2046 #define CMD_MAX_IOCB_CMD 0xFB 2047 #define CMD_IOCB_MASK 0xff 2048 2049 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 2050 iocb */ 2051 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 2052 /* 2053 * Define Status 2054 */ 2055 #define MBX_SUCCESS 0 2056 #define MBXERR_NUM_RINGS 1 2057 #define MBXERR_NUM_IOCBS 2 2058 #define MBXERR_IOCBS_EXCEEDED 3 2059 #define MBXERR_BAD_RING_NUMBER 4 2060 #define MBXERR_MASK_ENTRIES_RANGE 5 2061 #define MBXERR_MASKS_EXCEEDED 6 2062 #define MBXERR_BAD_PROFILE 7 2063 #define MBXERR_BAD_DEF_CLASS 8 2064 #define MBXERR_BAD_MAX_RESPONDER 9 2065 #define MBXERR_BAD_MAX_ORIGINATOR 10 2066 #define MBXERR_RPI_REGISTERED 11 2067 #define MBXERR_RPI_FULL 12 2068 #define MBXERR_NO_RESOURCES 13 2069 #define MBXERR_BAD_RCV_LENGTH 14 2070 #define MBXERR_DMA_ERROR 15 2071 #define MBXERR_ERROR 16 2072 #define MBXERR_LINK_DOWN 0x33 2073 #define MBXERR_SEC_NO_PERMISSION 0xF02 2074 #define MBX_NOT_FINISHED 255 2075 2076 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 2077 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 2078 2079 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 2080 2081 /* 2082 * return code Fail 2083 */ 2084 #define FAILURE 1 2085 2086 /* 2087 * Begin Structure Definitions for Mailbox Commands 2088 */ 2089 2090 typedef struct { 2091 #ifdef __BIG_ENDIAN_BITFIELD 2092 uint8_t tval; 2093 uint8_t tmask; 2094 uint8_t rval; 2095 uint8_t rmask; 2096 #else /* __LITTLE_ENDIAN_BITFIELD */ 2097 uint8_t rmask; 2098 uint8_t rval; 2099 uint8_t tmask; 2100 uint8_t tval; 2101 #endif 2102 } RR_REG; 2103 2104 struct ulp_bde { 2105 uint32_t bdeAddress; 2106 #ifdef __BIG_ENDIAN_BITFIELD 2107 uint32_t bdeReserved:4; 2108 uint32_t bdeAddrHigh:4; 2109 uint32_t bdeSize:24; 2110 #else /* __LITTLE_ENDIAN_BITFIELD */ 2111 uint32_t bdeSize:24; 2112 uint32_t bdeAddrHigh:4; 2113 uint32_t bdeReserved:4; 2114 #endif 2115 }; 2116 2117 typedef struct ULP_BDL { /* SLI-2 */ 2118 #ifdef __BIG_ENDIAN_BITFIELD 2119 uint32_t bdeFlags:8; /* BDL Flags */ 2120 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2121 #else /* __LITTLE_ENDIAN_BITFIELD */ 2122 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 2123 uint32_t bdeFlags:8; /* BDL Flags */ 2124 #endif 2125 2126 uint32_t addrLow; /* Address 0:31 */ 2127 uint32_t addrHigh; /* Address 32:63 */ 2128 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 2129 } ULP_BDL; 2130 2131 /* 2132 * BlockGuard Definitions 2133 */ 2134 2135 enum lpfc_protgrp_type { 2136 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 2137 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 2138 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 2139 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 2140 }; 2141 2142 /* PDE Descriptors */ 2143 #define LPFC_PDE5_DESCRIPTOR 0x85 2144 #define LPFC_PDE6_DESCRIPTOR 0x86 2145 #define LPFC_PDE7_DESCRIPTOR 0x87 2146 2147 /* BlockGuard Opcodes */ 2148 #define BG_OP_IN_NODIF_OUT_CRC 0x0 2149 #define BG_OP_IN_CRC_OUT_NODIF 0x1 2150 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 2151 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 2152 #define BG_OP_IN_CRC_OUT_CRC 0x4 2153 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 2154 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2155 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2156 #define BG_OP_RAW_MODE 0x8 2157 2158 struct lpfc_pde5 { 2159 uint32_t word0; 2160 #define pde5_type_SHIFT 24 2161 #define pde5_type_MASK 0x000000ff 2162 #define pde5_type_WORD word0 2163 #define pde5_rsvd0_SHIFT 0 2164 #define pde5_rsvd0_MASK 0x00ffffff 2165 #define pde5_rsvd0_WORD word0 2166 uint32_t reftag; /* Reference Tag Value */ 2167 uint32_t reftagtr; /* Reference Tag Translation Value */ 2168 }; 2169 2170 struct lpfc_pde6 { 2171 uint32_t word0; 2172 #define pde6_type_SHIFT 24 2173 #define pde6_type_MASK 0x000000ff 2174 #define pde6_type_WORD word0 2175 #define pde6_rsvd0_SHIFT 0 2176 #define pde6_rsvd0_MASK 0x00ffffff 2177 #define pde6_rsvd0_WORD word0 2178 uint32_t word1; 2179 #define pde6_rsvd1_SHIFT 26 2180 #define pde6_rsvd1_MASK 0x0000003f 2181 #define pde6_rsvd1_WORD word1 2182 #define pde6_na_SHIFT 25 2183 #define pde6_na_MASK 0x00000001 2184 #define pde6_na_WORD word1 2185 #define pde6_rsvd2_SHIFT 16 2186 #define pde6_rsvd2_MASK 0x000001FF 2187 #define pde6_rsvd2_WORD word1 2188 #define pde6_apptagtr_SHIFT 0 2189 #define pde6_apptagtr_MASK 0x0000ffff 2190 #define pde6_apptagtr_WORD word1 2191 uint32_t word2; 2192 #define pde6_optx_SHIFT 28 2193 #define pde6_optx_MASK 0x0000000f 2194 #define pde6_optx_WORD word2 2195 #define pde6_oprx_SHIFT 24 2196 #define pde6_oprx_MASK 0x0000000f 2197 #define pde6_oprx_WORD word2 2198 #define pde6_nr_SHIFT 23 2199 #define pde6_nr_MASK 0x00000001 2200 #define pde6_nr_WORD word2 2201 #define pde6_ce_SHIFT 22 2202 #define pde6_ce_MASK 0x00000001 2203 #define pde6_ce_WORD word2 2204 #define pde6_re_SHIFT 21 2205 #define pde6_re_MASK 0x00000001 2206 #define pde6_re_WORD word2 2207 #define pde6_ae_SHIFT 20 2208 #define pde6_ae_MASK 0x00000001 2209 #define pde6_ae_WORD word2 2210 #define pde6_ai_SHIFT 19 2211 #define pde6_ai_MASK 0x00000001 2212 #define pde6_ai_WORD word2 2213 #define pde6_bs_SHIFT 16 2214 #define pde6_bs_MASK 0x00000007 2215 #define pde6_bs_WORD word2 2216 #define pde6_apptagval_SHIFT 0 2217 #define pde6_apptagval_MASK 0x0000ffff 2218 #define pde6_apptagval_WORD word2 2219 }; 2220 2221 struct lpfc_pde7 { 2222 uint32_t word0; 2223 #define pde7_type_SHIFT 24 2224 #define pde7_type_MASK 0x000000ff 2225 #define pde7_type_WORD word0 2226 #define pde7_rsvd0_SHIFT 0 2227 #define pde7_rsvd0_MASK 0x00ffffff 2228 #define pde7_rsvd0_WORD word0 2229 uint32_t addrHigh; 2230 uint32_t addrLow; 2231 }; 2232 2233 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2234 2235 typedef struct { 2236 #ifdef __BIG_ENDIAN_BITFIELD 2237 uint32_t rsvd2:25; 2238 uint32_t acknowledgment:1; 2239 uint32_t version:1; 2240 uint32_t erase_or_prog:1; 2241 uint32_t update_flash:1; 2242 uint32_t update_ram:1; 2243 uint32_t method:1; 2244 uint32_t load_cmplt:1; 2245 #else /* __LITTLE_ENDIAN_BITFIELD */ 2246 uint32_t load_cmplt:1; 2247 uint32_t method:1; 2248 uint32_t update_ram:1; 2249 uint32_t update_flash:1; 2250 uint32_t erase_or_prog:1; 2251 uint32_t version:1; 2252 uint32_t acknowledgment:1; 2253 uint32_t rsvd2:25; 2254 #endif 2255 2256 uint32_t dl_to_adr_low; 2257 uint32_t dl_to_adr_high; 2258 uint32_t dl_len; 2259 union { 2260 uint32_t dl_from_mbx_offset; 2261 struct ulp_bde dl_from_bde; 2262 struct ulp_bde64 dl_from_bde64; 2263 } un; 2264 2265 } LOAD_SM_VAR; 2266 2267 /* Structure for MB Command READ_NVPARM (02) */ 2268 2269 typedef struct { 2270 uint32_t rsvd1[3]; /* Read as all one's */ 2271 uint32_t rsvd2; /* Read as all zero's */ 2272 uint32_t portname[2]; /* N_PORT name */ 2273 uint32_t nodename[2]; /* NODE name */ 2274 2275 #ifdef __BIG_ENDIAN_BITFIELD 2276 uint32_t pref_DID:24; 2277 uint32_t hardAL_PA:8; 2278 #else /* __LITTLE_ENDIAN_BITFIELD */ 2279 uint32_t hardAL_PA:8; 2280 uint32_t pref_DID:24; 2281 #endif 2282 2283 uint32_t rsvd3[21]; /* Read as all one's */ 2284 } READ_NV_VAR; 2285 2286 /* Structure for MB Command WRITE_NVPARMS (03) */ 2287 2288 typedef struct { 2289 uint32_t rsvd1[3]; /* Must be all one's */ 2290 uint32_t rsvd2; /* Must be all zero's */ 2291 uint32_t portname[2]; /* N_PORT name */ 2292 uint32_t nodename[2]; /* NODE name */ 2293 2294 #ifdef __BIG_ENDIAN_BITFIELD 2295 uint32_t pref_DID:24; 2296 uint32_t hardAL_PA:8; 2297 #else /* __LITTLE_ENDIAN_BITFIELD */ 2298 uint32_t hardAL_PA:8; 2299 uint32_t pref_DID:24; 2300 #endif 2301 2302 uint32_t rsvd3[21]; /* Must be all one's */ 2303 } WRITE_NV_VAR; 2304 2305 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2306 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2307 2308 typedef struct { 2309 uint32_t rsvd1; 2310 union { 2311 struct { 2312 struct ulp_bde xmit_bde; 2313 struct ulp_bde rcv_bde; 2314 } s1; 2315 struct { 2316 struct ulp_bde64 xmit_bde64; 2317 struct ulp_bde64 rcv_bde64; 2318 } s2; 2319 } un; 2320 } BIU_DIAG_VAR; 2321 2322 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2323 struct READ_EVENT_LOG_VAR { 2324 uint32_t word1; 2325 #define lpfc_event_log_SHIFT 29 2326 #define lpfc_event_log_MASK 0x00000001 2327 #define lpfc_event_log_WORD word1 2328 #define USE_MAILBOX_RESPONSE 1 2329 uint32_t offset; 2330 struct ulp_bde64 rcv_bde64; 2331 }; 2332 2333 /* Structure for MB Command INIT_LINK (05) */ 2334 2335 typedef struct { 2336 #ifdef __BIG_ENDIAN_BITFIELD 2337 uint32_t rsvd1:24; 2338 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2339 #else /* __LITTLE_ENDIAN_BITFIELD */ 2340 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2341 uint32_t rsvd1:24; 2342 #endif 2343 2344 #ifdef __BIG_ENDIAN_BITFIELD 2345 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2346 uint8_t rsvd2; 2347 uint16_t link_flags; 2348 #else /* __LITTLE_ENDIAN_BITFIELD */ 2349 uint16_t link_flags; 2350 uint8_t rsvd2; 2351 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2352 #endif 2353 2354 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2355 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2356 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2357 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2358 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2359 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2360 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2361 2362 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2363 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2364 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2365 2366 uint32_t link_speed; 2367 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2368 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2369 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2370 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2371 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2372 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2373 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2374 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2375 #define LINK_SPEED_64G 0x17 /* 64 Gigabaud */ 2376 #define LINK_SPEED_128G 0x1A /* 128 Gigabaud */ 2377 #define LINK_SPEED_256G 0x1D /* 256 Gigabaud */ 2378 2379 } INIT_LINK_VAR; 2380 2381 /* Structure for MB Command DOWN_LINK (06) */ 2382 2383 typedef struct { 2384 uint32_t rsvd1; 2385 } DOWN_LINK_VAR; 2386 2387 /* Structure for MB Command CONFIG_LINK (07) */ 2388 2389 typedef struct { 2390 #ifdef __BIG_ENDIAN_BITFIELD 2391 uint32_t cr:1; 2392 uint32_t ci:1; 2393 uint32_t cr_delay:6; 2394 uint32_t cr_count:8; 2395 uint32_t rsvd1:8; 2396 uint32_t MaxBBC:8; 2397 #else /* __LITTLE_ENDIAN_BITFIELD */ 2398 uint32_t MaxBBC:8; 2399 uint32_t rsvd1:8; 2400 uint32_t cr_count:8; 2401 uint32_t cr_delay:6; 2402 uint32_t ci:1; 2403 uint32_t cr:1; 2404 #endif 2405 2406 uint32_t myId; 2407 uint32_t rsvd2; 2408 uint32_t edtov; 2409 uint32_t arbtov; 2410 uint32_t ratov; 2411 uint32_t rttov; 2412 uint32_t altov; 2413 uint32_t crtov; 2414 2415 #ifdef __BIG_ENDIAN_BITFIELD 2416 uint32_t rsvd4:19; 2417 uint32_t cscn:1; 2418 uint32_t bbscn:4; 2419 uint32_t rsvd3:8; 2420 #else /* __LITTLE_ENDIAN_BITFIELD */ 2421 uint32_t rsvd3:8; 2422 uint32_t bbscn:4; 2423 uint32_t cscn:1; 2424 uint32_t rsvd4:19; 2425 #endif 2426 2427 #ifdef __BIG_ENDIAN_BITFIELD 2428 uint32_t rrq_enable:1; 2429 uint32_t rrq_immed:1; 2430 uint32_t rsvd5:29; 2431 uint32_t ack0_enable:1; 2432 #else /* __LITTLE_ENDIAN_BITFIELD */ 2433 uint32_t ack0_enable:1; 2434 uint32_t rsvd5:29; 2435 uint32_t rrq_immed:1; 2436 uint32_t rrq_enable:1; 2437 #endif 2438 } CONFIG_LINK; 2439 2440 /* Structure for MB Command PART_SLIM (08) 2441 * will be removed since SLI1 is no longer supported! 2442 */ 2443 typedef struct { 2444 #ifdef __BIG_ENDIAN_BITFIELD 2445 uint16_t offCiocb; 2446 uint16_t numCiocb; 2447 uint16_t offRiocb; 2448 uint16_t numRiocb; 2449 #else /* __LITTLE_ENDIAN_BITFIELD */ 2450 uint16_t numCiocb; 2451 uint16_t offCiocb; 2452 uint16_t numRiocb; 2453 uint16_t offRiocb; 2454 #endif 2455 } RING_DEF; 2456 2457 typedef struct { 2458 #ifdef __BIG_ENDIAN_BITFIELD 2459 uint32_t unused1:24; 2460 uint32_t numRing:8; 2461 #else /* __LITTLE_ENDIAN_BITFIELD */ 2462 uint32_t numRing:8; 2463 uint32_t unused1:24; 2464 #endif 2465 2466 RING_DEF ringdef[4]; 2467 uint32_t hbainit; 2468 } PART_SLIM_VAR; 2469 2470 /* Structure for MB Command CONFIG_RING (09) */ 2471 2472 typedef struct { 2473 #ifdef __BIG_ENDIAN_BITFIELD 2474 uint32_t unused2:6; 2475 uint32_t recvSeq:1; 2476 uint32_t recvNotify:1; 2477 uint32_t numMask:8; 2478 uint32_t profile:8; 2479 uint32_t unused1:4; 2480 uint32_t ring:4; 2481 #else /* __LITTLE_ENDIAN_BITFIELD */ 2482 uint32_t ring:4; 2483 uint32_t unused1:4; 2484 uint32_t profile:8; 2485 uint32_t numMask:8; 2486 uint32_t recvNotify:1; 2487 uint32_t recvSeq:1; 2488 uint32_t unused2:6; 2489 #endif 2490 2491 #ifdef __BIG_ENDIAN_BITFIELD 2492 uint16_t maxRespXchg; 2493 uint16_t maxOrigXchg; 2494 #else /* __LITTLE_ENDIAN_BITFIELD */ 2495 uint16_t maxOrigXchg; 2496 uint16_t maxRespXchg; 2497 #endif 2498 2499 RR_REG rrRegs[6]; 2500 } CONFIG_RING_VAR; 2501 2502 /* Structure for MB Command RESET_RING (10) */ 2503 2504 typedef struct { 2505 uint32_t ring_no; 2506 } RESET_RING_VAR; 2507 2508 /* Structure for MB Command READ_CONFIG (11) */ 2509 2510 typedef struct { 2511 #ifdef __BIG_ENDIAN_BITFIELD 2512 uint32_t cr:1; 2513 uint32_t ci:1; 2514 uint32_t cr_delay:6; 2515 uint32_t cr_count:8; 2516 uint32_t InitBBC:8; 2517 uint32_t MaxBBC:8; 2518 #else /* __LITTLE_ENDIAN_BITFIELD */ 2519 uint32_t MaxBBC:8; 2520 uint32_t InitBBC:8; 2521 uint32_t cr_count:8; 2522 uint32_t cr_delay:6; 2523 uint32_t ci:1; 2524 uint32_t cr:1; 2525 #endif 2526 2527 #ifdef __BIG_ENDIAN_BITFIELD 2528 uint32_t topology:8; 2529 uint32_t myDid:24; 2530 #else /* __LITTLE_ENDIAN_BITFIELD */ 2531 uint32_t myDid:24; 2532 uint32_t topology:8; 2533 #endif 2534 2535 /* Defines for topology (defined previously) */ 2536 #ifdef __BIG_ENDIAN_BITFIELD 2537 uint32_t AR:1; 2538 uint32_t IR:1; 2539 uint32_t rsvd1:29; 2540 uint32_t ack0:1; 2541 #else /* __LITTLE_ENDIAN_BITFIELD */ 2542 uint32_t ack0:1; 2543 uint32_t rsvd1:29; 2544 uint32_t IR:1; 2545 uint32_t AR:1; 2546 #endif 2547 2548 uint32_t edtov; 2549 uint32_t arbtov; 2550 uint32_t ratov; 2551 uint32_t rttov; 2552 uint32_t altov; 2553 uint32_t lmt; 2554 #define LMT_RESERVED 0x000 /* Not used */ 2555 #define LMT_1Gb 0x004 2556 #define LMT_2Gb 0x008 2557 #define LMT_4Gb 0x040 2558 #define LMT_8Gb 0x080 2559 #define LMT_10Gb 0x100 2560 #define LMT_16Gb 0x200 2561 #define LMT_32Gb 0x400 2562 #define LMT_64Gb 0x800 2563 #define LMT_128Gb 0x1000 2564 #define LMT_256Gb 0x2000 2565 uint32_t rsvd2; 2566 uint32_t rsvd3; 2567 uint32_t max_xri; 2568 uint32_t max_iocb; 2569 uint32_t max_rpi; 2570 uint32_t avail_xri; 2571 uint32_t avail_iocb; 2572 uint32_t avail_rpi; 2573 uint32_t max_vpi; 2574 uint32_t rsvd4; 2575 uint32_t rsvd5; 2576 uint32_t avail_vpi; 2577 } READ_CONFIG_VAR; 2578 2579 /* Structure for MB Command READ_RCONFIG (12) */ 2580 2581 typedef struct { 2582 #ifdef __BIG_ENDIAN_BITFIELD 2583 uint32_t rsvd2:7; 2584 uint32_t recvNotify:1; 2585 uint32_t numMask:8; 2586 uint32_t profile:8; 2587 uint32_t rsvd1:4; 2588 uint32_t ring:4; 2589 #else /* __LITTLE_ENDIAN_BITFIELD */ 2590 uint32_t ring:4; 2591 uint32_t rsvd1:4; 2592 uint32_t profile:8; 2593 uint32_t numMask:8; 2594 uint32_t recvNotify:1; 2595 uint32_t rsvd2:7; 2596 #endif 2597 2598 #ifdef __BIG_ENDIAN_BITFIELD 2599 uint16_t maxResp; 2600 uint16_t maxOrig; 2601 #else /* __LITTLE_ENDIAN_BITFIELD */ 2602 uint16_t maxOrig; 2603 uint16_t maxResp; 2604 #endif 2605 2606 RR_REG rrRegs[6]; 2607 2608 #ifdef __BIG_ENDIAN_BITFIELD 2609 uint16_t cmdRingOffset; 2610 uint16_t cmdEntryCnt; 2611 uint16_t rspRingOffset; 2612 uint16_t rspEntryCnt; 2613 uint16_t nextCmdOffset; 2614 uint16_t rsvd3; 2615 uint16_t nextRspOffset; 2616 uint16_t rsvd4; 2617 #else /* __LITTLE_ENDIAN_BITFIELD */ 2618 uint16_t cmdEntryCnt; 2619 uint16_t cmdRingOffset; 2620 uint16_t rspEntryCnt; 2621 uint16_t rspRingOffset; 2622 uint16_t rsvd3; 2623 uint16_t nextCmdOffset; 2624 uint16_t rsvd4; 2625 uint16_t nextRspOffset; 2626 #endif 2627 } READ_RCONF_VAR; 2628 2629 /* Structure for MB Command READ_SPARM (13) */ 2630 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2631 2632 typedef struct { 2633 uint32_t rsvd1; 2634 uint32_t rsvd2; 2635 union { 2636 struct ulp_bde sp; /* This BDE points to struct serv_parm 2637 structure */ 2638 struct ulp_bde64 sp64; 2639 } un; 2640 #ifdef __BIG_ENDIAN_BITFIELD 2641 uint16_t rsvd3; 2642 uint16_t vpi; 2643 #else /* __LITTLE_ENDIAN_BITFIELD */ 2644 uint16_t vpi; 2645 uint16_t rsvd3; 2646 #endif 2647 } READ_SPARM_VAR; 2648 2649 /* Structure for MB Command READ_STATUS (14) */ 2650 2651 typedef struct { 2652 #ifdef __BIG_ENDIAN_BITFIELD 2653 uint32_t rsvd1:31; 2654 uint32_t clrCounters:1; 2655 uint16_t activeXriCnt; 2656 uint16_t activeRpiCnt; 2657 #else /* __LITTLE_ENDIAN_BITFIELD */ 2658 uint32_t clrCounters:1; 2659 uint32_t rsvd1:31; 2660 uint16_t activeRpiCnt; 2661 uint16_t activeXriCnt; 2662 #endif 2663 2664 uint32_t xmitByteCnt; 2665 uint32_t rcvByteCnt; 2666 uint32_t xmitFrameCnt; 2667 uint32_t rcvFrameCnt; 2668 uint32_t xmitSeqCnt; 2669 uint32_t rcvSeqCnt; 2670 uint32_t totalOrigExchanges; 2671 uint32_t totalRespExchanges; 2672 uint32_t rcvPbsyCnt; 2673 uint32_t rcvFbsyCnt; 2674 } READ_STATUS_VAR; 2675 2676 /* Structure for MB Command READ_RPI (15) */ 2677 /* Structure for MB Command READ_RPI64 (0x8F) */ 2678 2679 typedef struct { 2680 #ifdef __BIG_ENDIAN_BITFIELD 2681 uint16_t nextRpi; 2682 uint16_t reqRpi; 2683 uint32_t rsvd2:8; 2684 uint32_t DID:24; 2685 #else /* __LITTLE_ENDIAN_BITFIELD */ 2686 uint16_t reqRpi; 2687 uint16_t nextRpi; 2688 uint32_t DID:24; 2689 uint32_t rsvd2:8; 2690 #endif 2691 2692 union { 2693 struct ulp_bde sp; 2694 struct ulp_bde64 sp64; 2695 } un; 2696 2697 } READ_RPI_VAR; 2698 2699 /* Structure for MB Command READ_XRI (16) */ 2700 2701 typedef struct { 2702 #ifdef __BIG_ENDIAN_BITFIELD 2703 uint16_t nextXri; 2704 uint16_t reqXri; 2705 uint16_t rsvd1; 2706 uint16_t rpi; 2707 uint32_t rsvd2:8; 2708 uint32_t DID:24; 2709 uint32_t rsvd3:8; 2710 uint32_t SID:24; 2711 uint32_t rsvd4; 2712 uint8_t seqId; 2713 uint8_t rsvd5; 2714 uint16_t seqCount; 2715 uint16_t oxId; 2716 uint16_t rxId; 2717 uint32_t rsvd6:30; 2718 uint32_t si:1; 2719 uint32_t exchOrig:1; 2720 #else /* __LITTLE_ENDIAN_BITFIELD */ 2721 uint16_t reqXri; 2722 uint16_t nextXri; 2723 uint16_t rpi; 2724 uint16_t rsvd1; 2725 uint32_t DID:24; 2726 uint32_t rsvd2:8; 2727 uint32_t SID:24; 2728 uint32_t rsvd3:8; 2729 uint32_t rsvd4; 2730 uint16_t seqCount; 2731 uint8_t rsvd5; 2732 uint8_t seqId; 2733 uint16_t rxId; 2734 uint16_t oxId; 2735 uint32_t exchOrig:1; 2736 uint32_t si:1; 2737 uint32_t rsvd6:30; 2738 #endif 2739 } READ_XRI_VAR; 2740 2741 /* Structure for MB Command READ_REV (17) */ 2742 2743 typedef struct { 2744 #ifdef __BIG_ENDIAN_BITFIELD 2745 uint32_t cv:1; 2746 uint32_t rr:1; 2747 uint32_t rsvd2:2; 2748 uint32_t v3req:1; 2749 uint32_t v3rsp:1; 2750 uint32_t rsvd1:25; 2751 uint32_t rv:1; 2752 #else /* __LITTLE_ENDIAN_BITFIELD */ 2753 uint32_t rv:1; 2754 uint32_t rsvd1:25; 2755 uint32_t v3rsp:1; 2756 uint32_t v3req:1; 2757 uint32_t rsvd2:2; 2758 uint32_t rr:1; 2759 uint32_t cv:1; 2760 #endif 2761 2762 uint32_t biuRev; 2763 uint32_t smRev; 2764 union { 2765 uint32_t smFwRev; 2766 struct { 2767 #ifdef __BIG_ENDIAN_BITFIELD 2768 uint8_t ProgType; 2769 uint8_t ProgId; 2770 uint16_t ProgVer:4; 2771 uint16_t ProgRev:4; 2772 uint16_t ProgFixLvl:2; 2773 uint16_t ProgDistType:2; 2774 uint16_t DistCnt:4; 2775 #else /* __LITTLE_ENDIAN_BITFIELD */ 2776 uint16_t DistCnt:4; 2777 uint16_t ProgDistType:2; 2778 uint16_t ProgFixLvl:2; 2779 uint16_t ProgRev:4; 2780 uint16_t ProgVer:4; 2781 uint8_t ProgId; 2782 uint8_t ProgType; 2783 #endif 2784 2785 } b; 2786 } un; 2787 uint32_t endecRev; 2788 #ifdef __BIG_ENDIAN_BITFIELD 2789 uint8_t feaLevelHigh; 2790 uint8_t feaLevelLow; 2791 uint8_t fcphHigh; 2792 uint8_t fcphLow; 2793 #else /* __LITTLE_ENDIAN_BITFIELD */ 2794 uint8_t fcphLow; 2795 uint8_t fcphHigh; 2796 uint8_t feaLevelLow; 2797 uint8_t feaLevelHigh; 2798 #endif 2799 2800 uint32_t postKernRev; 2801 uint32_t opFwRev; 2802 uint8_t opFwName[16]; 2803 uint32_t sli1FwRev; 2804 uint8_t sli1FwName[16]; 2805 uint32_t sli2FwRev; 2806 uint8_t sli2FwName[16]; 2807 uint32_t sli3Feat; 2808 uint32_t RandomData[6]; 2809 } READ_REV_VAR; 2810 2811 /* Structure for MB Command READ_LINK_STAT (18) */ 2812 2813 typedef struct { 2814 uint32_t word0; 2815 2816 #define lpfc_read_link_stat_rec_SHIFT 0 2817 #define lpfc_read_link_stat_rec_MASK 0x1 2818 #define lpfc_read_link_stat_rec_WORD word0 2819 2820 #define lpfc_read_link_stat_gec_SHIFT 1 2821 #define lpfc_read_link_stat_gec_MASK 0x1 2822 #define lpfc_read_link_stat_gec_WORD word0 2823 2824 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2825 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2826 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2827 2828 #define lpfc_read_link_stat_rsvd_SHIFT 24 2829 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2830 #define lpfc_read_link_stat_rsvd_WORD word0 2831 2832 #define lpfc_read_link_stat_gec2_SHIFT 29 2833 #define lpfc_read_link_stat_gec2_MASK 0x1 2834 #define lpfc_read_link_stat_gec2_WORD word0 2835 2836 #define lpfc_read_link_stat_clrc_SHIFT 30 2837 #define lpfc_read_link_stat_clrc_MASK 0x1 2838 #define lpfc_read_link_stat_clrc_WORD word0 2839 2840 #define lpfc_read_link_stat_clof_SHIFT 31 2841 #define lpfc_read_link_stat_clof_MASK 0x1 2842 #define lpfc_read_link_stat_clof_WORD word0 2843 2844 uint32_t linkFailureCnt; 2845 uint32_t lossSyncCnt; 2846 uint32_t lossSignalCnt; 2847 uint32_t primSeqErrCnt; 2848 uint32_t invalidXmitWord; 2849 uint32_t crcCnt; 2850 uint32_t primSeqTimeout; 2851 uint32_t elasticOverrun; 2852 uint32_t arbTimeout; 2853 uint32_t advRecBufCredit; 2854 uint32_t curRecBufCredit; 2855 uint32_t advTransBufCredit; 2856 uint32_t curTransBufCredit; 2857 uint32_t recEofCount; 2858 uint32_t recEofdtiCount; 2859 uint32_t recEofniCount; 2860 uint32_t recSofcount; 2861 uint32_t rsvd1; 2862 uint32_t rsvd2; 2863 uint32_t recDrpXriCount; 2864 uint32_t fecCorrBlkCount; 2865 uint32_t fecUncorrBlkCount; 2866 } READ_LNK_VAR; 2867 2868 /* Structure for MB Command REG_LOGIN (19) */ 2869 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2870 2871 typedef struct { 2872 #ifdef __BIG_ENDIAN_BITFIELD 2873 uint16_t rsvd1; 2874 uint16_t rpi; 2875 uint32_t rsvd2:8; 2876 uint32_t did:24; 2877 #else /* __LITTLE_ENDIAN_BITFIELD */ 2878 uint16_t rpi; 2879 uint16_t rsvd1; 2880 uint32_t did:24; 2881 uint32_t rsvd2:8; 2882 #endif 2883 2884 union { 2885 struct ulp_bde sp; 2886 struct ulp_bde64 sp64; 2887 } un; 2888 2889 #ifdef __BIG_ENDIAN_BITFIELD 2890 uint16_t rsvd6; 2891 uint16_t vpi; 2892 #else /* __LITTLE_ENDIAN_BITFIELD */ 2893 uint16_t vpi; 2894 uint16_t rsvd6; 2895 #endif 2896 2897 } REG_LOGIN_VAR; 2898 2899 /* Word 30 contents for REG_LOGIN */ 2900 typedef union { 2901 struct { 2902 #ifdef __BIG_ENDIAN_BITFIELD 2903 uint16_t rsvd1:12; 2904 uint16_t wd30_class:4; 2905 uint16_t xri; 2906 #else /* __LITTLE_ENDIAN_BITFIELD */ 2907 uint16_t xri; 2908 uint16_t wd30_class:4; 2909 uint16_t rsvd1:12; 2910 #endif 2911 } f; 2912 uint32_t word; 2913 } REG_WD30; 2914 2915 /* Structure for MB Command UNREG_LOGIN (20) */ 2916 2917 typedef struct { 2918 #ifdef __BIG_ENDIAN_BITFIELD 2919 uint16_t rsvd1; 2920 uint16_t rpi; 2921 uint32_t rsvd2; 2922 uint32_t rsvd3; 2923 uint32_t rsvd4; 2924 uint32_t rsvd5; 2925 uint16_t rsvd6; 2926 uint16_t vpi; 2927 #else /* __LITTLE_ENDIAN_BITFIELD */ 2928 uint16_t rpi; 2929 uint16_t rsvd1; 2930 uint32_t rsvd2; 2931 uint32_t rsvd3; 2932 uint32_t rsvd4; 2933 uint32_t rsvd5; 2934 uint16_t vpi; 2935 uint16_t rsvd6; 2936 #endif 2937 } UNREG_LOGIN_VAR; 2938 2939 /* Structure for MB Command REG_VPI (0x96) */ 2940 typedef struct { 2941 #ifdef __BIG_ENDIAN_BITFIELD 2942 uint32_t rsvd1; 2943 uint32_t rsvd2:7; 2944 uint32_t upd:1; 2945 uint32_t sid:24; 2946 uint32_t wwn[2]; 2947 uint32_t rsvd5; 2948 uint16_t vfi; 2949 uint16_t vpi; 2950 #else /* __LITTLE_ENDIAN */ 2951 uint32_t rsvd1; 2952 uint32_t sid:24; 2953 uint32_t upd:1; 2954 uint32_t rsvd2:7; 2955 uint32_t wwn[2]; 2956 uint32_t rsvd5; 2957 uint16_t vpi; 2958 uint16_t vfi; 2959 #endif 2960 } REG_VPI_VAR; 2961 2962 /* Structure for MB Command UNREG_VPI (0x97) */ 2963 typedef struct { 2964 uint32_t rsvd1; 2965 #ifdef __BIG_ENDIAN_BITFIELD 2966 uint16_t rsvd2; 2967 uint16_t sli4_vpi; 2968 #else /* __LITTLE_ENDIAN */ 2969 uint16_t sli4_vpi; 2970 uint16_t rsvd2; 2971 #endif 2972 uint32_t rsvd3; 2973 uint32_t rsvd4; 2974 uint32_t rsvd5; 2975 #ifdef __BIG_ENDIAN_BITFIELD 2976 uint16_t rsvd6; 2977 uint16_t vpi; 2978 #else /* __LITTLE_ENDIAN */ 2979 uint16_t vpi; 2980 uint16_t rsvd6; 2981 #endif 2982 } UNREG_VPI_VAR; 2983 2984 /* Structure for MB Command UNREG_D_ID (0x23) */ 2985 2986 typedef struct { 2987 uint32_t did; 2988 uint32_t rsvd2; 2989 uint32_t rsvd3; 2990 uint32_t rsvd4; 2991 uint32_t rsvd5; 2992 #ifdef __BIG_ENDIAN_BITFIELD 2993 uint16_t rsvd6; 2994 uint16_t vpi; 2995 #else 2996 uint16_t vpi; 2997 uint16_t rsvd6; 2998 #endif 2999 } UNREG_D_ID_VAR; 3000 3001 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 3002 struct lpfc_mbx_read_top { 3003 uint32_t eventTag; /* Event tag */ 3004 uint32_t word2; 3005 #define lpfc_mbx_read_top_fa_SHIFT 12 3006 #define lpfc_mbx_read_top_fa_MASK 0x00000001 3007 #define lpfc_mbx_read_top_fa_WORD word2 3008 #define lpfc_mbx_read_top_mm_SHIFT 11 3009 #define lpfc_mbx_read_top_mm_MASK 0x00000001 3010 #define lpfc_mbx_read_top_mm_WORD word2 3011 #define lpfc_mbx_read_top_pb_SHIFT 9 3012 #define lpfc_mbx_read_top_pb_MASK 0X00000001 3013 #define lpfc_mbx_read_top_pb_WORD word2 3014 #define lpfc_mbx_read_top_il_SHIFT 8 3015 #define lpfc_mbx_read_top_il_MASK 0x00000001 3016 #define lpfc_mbx_read_top_il_WORD word2 3017 #define lpfc_mbx_read_top_att_type_SHIFT 0 3018 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 3019 #define lpfc_mbx_read_top_att_type_WORD word2 3020 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 3021 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 3022 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 3023 #define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */ 3024 uint32_t word3; 3025 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 3026 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 3027 #define lpfc_mbx_read_top_alpa_granted_WORD word3 3028 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 3029 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 3030 #define lpfc_mbx_read_top_lip_alps_WORD word3 3031 #define lpfc_mbx_read_top_lip_type_SHIFT 8 3032 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 3033 #define lpfc_mbx_read_top_lip_type_WORD word3 3034 #define lpfc_mbx_read_top_topology_SHIFT 0 3035 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 3036 #define lpfc_mbx_read_top_topology_WORD word3 3037 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 3038 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 3039 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 3040 /* store the LILP AL_PA position map into */ 3041 struct ulp_bde64 lilpBde64; 3042 #define LPFC_ALPA_MAP_SIZE 128 3043 uint32_t word7; 3044 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 3045 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 3046 #define lpfc_mbx_read_top_ld_lu_WORD word7 3047 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 3048 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 3049 #define lpfc_mbx_read_top_ld_tf_WORD word7 3050 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 3051 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 3052 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 3053 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 3054 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 3055 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 3056 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 3057 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 3058 #define lpfc_mbx_read_top_ld_tx_WORD word7 3059 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 3060 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 3061 #define lpfc_mbx_read_top_ld_rx_WORD word7 3062 uint32_t word8; 3063 #define lpfc_mbx_read_top_lu_SHIFT 31 3064 #define lpfc_mbx_read_top_lu_MASK 0x00000001 3065 #define lpfc_mbx_read_top_lu_WORD word8 3066 #define lpfc_mbx_read_top_tf_SHIFT 30 3067 #define lpfc_mbx_read_top_tf_MASK 0x00000001 3068 #define lpfc_mbx_read_top_tf_WORD word8 3069 #define lpfc_mbx_read_top_link_spd_SHIFT 8 3070 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 3071 #define lpfc_mbx_read_top_link_spd_WORD word8 3072 #define lpfc_mbx_read_top_nl_port_SHIFT 4 3073 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 3074 #define lpfc_mbx_read_top_nl_port_WORD word8 3075 #define lpfc_mbx_read_top_tx_SHIFT 2 3076 #define lpfc_mbx_read_top_tx_MASK 0x00000003 3077 #define lpfc_mbx_read_top_tx_WORD word8 3078 #define lpfc_mbx_read_top_rx_SHIFT 0 3079 #define lpfc_mbx_read_top_rx_MASK 0x00000003 3080 #define lpfc_mbx_read_top_rx_WORD word8 3081 #define LPFC_LINK_SPEED_UNKNOWN 0x0 3082 #define LPFC_LINK_SPEED_1GHZ 0x04 3083 #define LPFC_LINK_SPEED_2GHZ 0x08 3084 #define LPFC_LINK_SPEED_4GHZ 0x10 3085 #define LPFC_LINK_SPEED_8GHZ 0x20 3086 #define LPFC_LINK_SPEED_10GHZ 0x40 3087 #define LPFC_LINK_SPEED_16GHZ 0x80 3088 #define LPFC_LINK_SPEED_32GHZ 0x90 3089 #define LPFC_LINK_SPEED_64GHZ 0xA0 3090 #define LPFC_LINK_SPEED_128GHZ 0xB0 3091 #define LPFC_LINK_SPEED_256GHZ 0xC0 3092 }; 3093 3094 /* Structure for MB Command CLEAR_LA (22) */ 3095 3096 typedef struct { 3097 uint32_t eventTag; /* Event tag */ 3098 uint32_t rsvd1; 3099 } CLEAR_LA_VAR; 3100 3101 /* Structure for MB Command DUMP */ 3102 3103 typedef struct { 3104 #ifdef __BIG_ENDIAN_BITFIELD 3105 uint32_t rsvd:25; 3106 uint32_t ra:1; 3107 uint32_t co:1; 3108 uint32_t cv:1; 3109 uint32_t type:4; 3110 uint32_t entry_index:16; 3111 uint32_t region_id:16; 3112 #else /* __LITTLE_ENDIAN_BITFIELD */ 3113 uint32_t type:4; 3114 uint32_t cv:1; 3115 uint32_t co:1; 3116 uint32_t ra:1; 3117 uint32_t rsvd:25; 3118 uint32_t region_id:16; 3119 uint32_t entry_index:16; 3120 #endif 3121 3122 uint32_t sli4_length; 3123 uint32_t word_cnt; 3124 uint32_t resp_offset; 3125 } DUMP_VAR; 3126 3127 #define DMP_MEM_REG 0x1 3128 #define DMP_NV_PARAMS 0x2 3129 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 3130 #define DMP_WELL_KNOWN 0x4 3131 3132 #define DMP_REGION_VPD 0xe 3133 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 3134 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 3135 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 3136 3137 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 3138 #define DMP_VPORT_REGION_SIZE 0x200 3139 #define DMP_MBOX_OFFSET_WORD 0x5 3140 3141 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 3142 #define DMP_RGN23_SIZE 0x400 3143 3144 #define WAKE_UP_PARMS_REGION_ID 4 3145 #define WAKE_UP_PARMS_WORD_SIZE 15 3146 3147 struct vport_rec { 3148 uint8_t wwpn[8]; 3149 uint8_t wwnn[8]; 3150 }; 3151 3152 #define VPORT_INFO_SIG 0x32324752 3153 #define VPORT_INFO_REV_MASK 0xff 3154 #define VPORT_INFO_REV 0x1 3155 #define MAX_STATIC_VPORT_COUNT 16 3156 struct static_vport_info { 3157 uint32_t signature; 3158 uint32_t rev; 3159 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 3160 uint32_t resvd[66]; 3161 }; 3162 3163 /* Option rom version structure */ 3164 struct prog_id { 3165 #ifdef __BIG_ENDIAN_BITFIELD 3166 uint8_t type; 3167 uint8_t id; 3168 uint32_t ver:4; /* Major Version */ 3169 uint32_t rev:4; /* Revision */ 3170 uint32_t lev:2; /* Level */ 3171 uint32_t dist:2; /* Dist Type */ 3172 uint32_t num:4; /* number after dist type */ 3173 #else /* __LITTLE_ENDIAN_BITFIELD */ 3174 uint32_t num:4; /* number after dist type */ 3175 uint32_t dist:2; /* Dist Type */ 3176 uint32_t lev:2; /* Level */ 3177 uint32_t rev:4; /* Revision */ 3178 uint32_t ver:4; /* Major Version */ 3179 uint8_t id; 3180 uint8_t type; 3181 #endif 3182 }; 3183 3184 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3185 3186 struct update_cfg_var { 3187 #ifdef __BIG_ENDIAN_BITFIELD 3188 uint32_t rsvd2:16; 3189 uint32_t type:8; 3190 uint32_t rsvd:1; 3191 uint32_t ra:1; 3192 uint32_t co:1; 3193 uint32_t cv:1; 3194 uint32_t req:4; 3195 uint32_t entry_length:16; 3196 uint32_t region_id:16; 3197 #else /* __LITTLE_ENDIAN_BITFIELD */ 3198 uint32_t req:4; 3199 uint32_t cv:1; 3200 uint32_t co:1; 3201 uint32_t ra:1; 3202 uint32_t rsvd:1; 3203 uint32_t type:8; 3204 uint32_t rsvd2:16; 3205 uint32_t region_id:16; 3206 uint32_t entry_length:16; 3207 #endif 3208 3209 uint32_t resp_info; 3210 uint32_t byte_cnt; 3211 uint32_t data_offset; 3212 }; 3213 3214 struct hbq_mask { 3215 #ifdef __BIG_ENDIAN_BITFIELD 3216 uint8_t tmatch; 3217 uint8_t tmask; 3218 uint8_t rctlmatch; 3219 uint8_t rctlmask; 3220 #else /* __LITTLE_ENDIAN */ 3221 uint8_t rctlmask; 3222 uint8_t rctlmatch; 3223 uint8_t tmask; 3224 uint8_t tmatch; 3225 #endif 3226 }; 3227 3228 3229 /* Structure for MB Command CONFIG_HBQ (7c) */ 3230 3231 struct config_hbq_var { 3232 #ifdef __BIG_ENDIAN_BITFIELD 3233 uint32_t rsvd1 :7; 3234 uint32_t recvNotify :1; /* Receive Notification */ 3235 uint32_t numMask :8; /* # Mask Entries */ 3236 uint32_t profile :8; /* Selection Profile */ 3237 uint32_t rsvd2 :8; 3238 #else /* __LITTLE_ENDIAN */ 3239 uint32_t rsvd2 :8; 3240 uint32_t profile :8; /* Selection Profile */ 3241 uint32_t numMask :8; /* # Mask Entries */ 3242 uint32_t recvNotify :1; /* Receive Notification */ 3243 uint32_t rsvd1 :7; 3244 #endif 3245 3246 #ifdef __BIG_ENDIAN_BITFIELD 3247 uint32_t hbqId :16; 3248 uint32_t rsvd3 :12; 3249 uint32_t ringMask :4; 3250 #else /* __LITTLE_ENDIAN */ 3251 uint32_t ringMask :4; 3252 uint32_t rsvd3 :12; 3253 uint32_t hbqId :16; 3254 #endif 3255 3256 #ifdef __BIG_ENDIAN_BITFIELD 3257 uint32_t entry_count :16; 3258 uint32_t rsvd4 :8; 3259 uint32_t headerLen :8; 3260 #else /* __LITTLE_ENDIAN */ 3261 uint32_t headerLen :8; 3262 uint32_t rsvd4 :8; 3263 uint32_t entry_count :16; 3264 #endif 3265 3266 uint32_t hbqaddrLow; 3267 uint32_t hbqaddrHigh; 3268 3269 #ifdef __BIG_ENDIAN_BITFIELD 3270 uint32_t rsvd5 :31; 3271 uint32_t logEntry :1; 3272 #else /* __LITTLE_ENDIAN */ 3273 uint32_t logEntry :1; 3274 uint32_t rsvd5 :31; 3275 #endif 3276 3277 uint32_t rsvd6; /* w7 */ 3278 uint32_t rsvd7; /* w8 */ 3279 uint32_t rsvd8; /* w9 */ 3280 3281 struct hbq_mask hbqMasks[6]; 3282 3283 3284 union { 3285 uint32_t allprofiles[12]; 3286 3287 struct { 3288 #ifdef __BIG_ENDIAN_BITFIELD 3289 uint32_t seqlenoff :16; 3290 uint32_t maxlen :16; 3291 #else /* __LITTLE_ENDIAN */ 3292 uint32_t maxlen :16; 3293 uint32_t seqlenoff :16; 3294 #endif 3295 #ifdef __BIG_ENDIAN_BITFIELD 3296 uint32_t rsvd1 :28; 3297 uint32_t seqlenbcnt :4; 3298 #else /* __LITTLE_ENDIAN */ 3299 uint32_t seqlenbcnt :4; 3300 uint32_t rsvd1 :28; 3301 #endif 3302 uint32_t rsvd[10]; 3303 } profile2; 3304 3305 struct { 3306 #ifdef __BIG_ENDIAN_BITFIELD 3307 uint32_t seqlenoff :16; 3308 uint32_t maxlen :16; 3309 #else /* __LITTLE_ENDIAN */ 3310 uint32_t maxlen :16; 3311 uint32_t seqlenoff :16; 3312 #endif 3313 #ifdef __BIG_ENDIAN_BITFIELD 3314 uint32_t cmdcodeoff :28; 3315 uint32_t rsvd1 :12; 3316 uint32_t seqlenbcnt :4; 3317 #else /* __LITTLE_ENDIAN */ 3318 uint32_t seqlenbcnt :4; 3319 uint32_t rsvd1 :12; 3320 uint32_t cmdcodeoff :28; 3321 #endif 3322 uint32_t cmdmatch[8]; 3323 3324 uint32_t rsvd[2]; 3325 } profile3; 3326 3327 struct { 3328 #ifdef __BIG_ENDIAN_BITFIELD 3329 uint32_t seqlenoff :16; 3330 uint32_t maxlen :16; 3331 #else /* __LITTLE_ENDIAN */ 3332 uint32_t maxlen :16; 3333 uint32_t seqlenoff :16; 3334 #endif 3335 #ifdef __BIG_ENDIAN_BITFIELD 3336 uint32_t cmdcodeoff :28; 3337 uint32_t rsvd1 :12; 3338 uint32_t seqlenbcnt :4; 3339 #else /* __LITTLE_ENDIAN */ 3340 uint32_t seqlenbcnt :4; 3341 uint32_t rsvd1 :12; 3342 uint32_t cmdcodeoff :28; 3343 #endif 3344 uint32_t cmdmatch[8]; 3345 3346 uint32_t rsvd[2]; 3347 } profile5; 3348 3349 } profiles; 3350 3351 }; 3352 3353 3354 3355 /* Structure for MB Command CONFIG_PORT (0x88) */ 3356 typedef struct { 3357 #ifdef __BIG_ENDIAN_BITFIELD 3358 uint32_t cBE : 1; 3359 uint32_t cET : 1; 3360 uint32_t cHpcb : 1; 3361 uint32_t cMA : 1; 3362 uint32_t sli_mode : 4; 3363 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3364 * config block */ 3365 #else /* __LITTLE_ENDIAN */ 3366 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3367 * config block */ 3368 uint32_t sli_mode : 4; 3369 uint32_t cMA : 1; 3370 uint32_t cHpcb : 1; 3371 uint32_t cET : 1; 3372 uint32_t cBE : 1; 3373 #endif 3374 3375 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3376 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3377 uint32_t hbainit[5]; 3378 #ifdef __BIG_ENDIAN_BITFIELD 3379 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3380 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3381 #else /* __LITTLE_ENDIAN */ 3382 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3383 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3384 #endif 3385 3386 #ifdef __BIG_ENDIAN_BITFIELD 3387 uint32_t rsvd1 : 20; /* Reserved */ 3388 uint32_t casabt : 1; /* Configure async abts status notice */ 3389 uint32_t rsvd2 : 2; /* Reserved */ 3390 uint32_t cbg : 1; /* Configure BlockGuard */ 3391 uint32_t cmv : 1; /* Configure Max VPIs */ 3392 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3393 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3394 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3395 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3396 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3397 uint32_t cmx : 1; /* Configure Max XRIs */ 3398 uint32_t cmr : 1; /* Configure Max RPIs */ 3399 #else /* __LITTLE_ENDIAN */ 3400 uint32_t cmr : 1; /* Configure Max RPIs */ 3401 uint32_t cmx : 1; /* Configure Max XRIs */ 3402 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3403 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3404 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3405 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3406 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3407 uint32_t cmv : 1; /* Configure Max VPIs */ 3408 uint32_t cbg : 1; /* Configure BlockGuard */ 3409 uint32_t rsvd2 : 2; /* Reserved */ 3410 uint32_t casabt : 1; /* Configure async abts status notice */ 3411 uint32_t rsvd1 : 20; /* Reserved */ 3412 #endif 3413 #ifdef __BIG_ENDIAN_BITFIELD 3414 uint32_t rsvd3 : 20; /* Reserved */ 3415 uint32_t gasabt : 1; /* Grant async abts status notice */ 3416 uint32_t rsvd4 : 2; /* Reserved */ 3417 uint32_t gbg : 1; /* Grant BlockGuard */ 3418 uint32_t gmv : 1; /* Grant Max VPIs */ 3419 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3420 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3421 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3422 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3423 uint32_t gerbm : 1; /* Grant ERBM Request */ 3424 uint32_t gmx : 1; /* Grant Max XRIs */ 3425 uint32_t gmr : 1; /* Grant Max RPIs */ 3426 #else /* __LITTLE_ENDIAN */ 3427 uint32_t gmr : 1; /* Grant Max RPIs */ 3428 uint32_t gmx : 1; /* Grant Max XRIs */ 3429 uint32_t gerbm : 1; /* Grant ERBM Request */ 3430 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3431 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3432 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3433 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3434 uint32_t gmv : 1; /* Grant Max VPIs */ 3435 uint32_t gbg : 1; /* Grant BlockGuard */ 3436 uint32_t rsvd4 : 2; /* Reserved */ 3437 uint32_t gasabt : 1; /* Grant async abts status notice */ 3438 uint32_t rsvd3 : 20; /* Reserved */ 3439 #endif 3440 3441 #ifdef __BIG_ENDIAN_BITFIELD 3442 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3443 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3444 #else /* __LITTLE_ENDIAN */ 3445 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3446 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3447 #endif 3448 3449 #ifdef __BIG_ENDIAN_BITFIELD 3450 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3451 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3452 #else /* __LITTLE_ENDIAN */ 3453 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3454 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3455 #endif 3456 3457 uint32_t rsvd6; /* Reserved */ 3458 3459 #ifdef __BIG_ENDIAN_BITFIELD 3460 uint32_t rsvd7 : 16; 3461 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3462 #else /* __LITTLE_ENDIAN */ 3463 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3464 uint32_t rsvd7 : 16; 3465 #endif 3466 3467 } CONFIG_PORT_VAR; 3468 3469 /* Structure for MB Command CONFIG_MSI (0x30) */ 3470 struct config_msi_var { 3471 #ifdef __BIG_ENDIAN_BITFIELD 3472 uint32_t dfltMsgNum:8; /* Default message number */ 3473 uint32_t rsvd1:11; /* Reserved */ 3474 uint32_t NID:5; /* Number of secondary attention IDs */ 3475 uint32_t rsvd2:5; /* Reserved */ 3476 uint32_t dfltPresent:1; /* Default message number present */ 3477 uint32_t addFlag:1; /* Add association flag */ 3478 uint32_t reportFlag:1; /* Report association flag */ 3479 #else /* __LITTLE_ENDIAN_BITFIELD */ 3480 uint32_t reportFlag:1; /* Report association flag */ 3481 uint32_t addFlag:1; /* Add association flag */ 3482 uint32_t dfltPresent:1; /* Default message number present */ 3483 uint32_t rsvd2:5; /* Reserved */ 3484 uint32_t NID:5; /* Number of secondary attention IDs */ 3485 uint32_t rsvd1:11; /* Reserved */ 3486 uint32_t dfltMsgNum:8; /* Default message number */ 3487 #endif 3488 uint32_t attentionConditions[2]; 3489 uint8_t attentionId[16]; 3490 uint8_t messageNumberByHA[64]; 3491 uint8_t messageNumberByID[16]; 3492 uint32_t autoClearHA[2]; 3493 #ifdef __BIG_ENDIAN_BITFIELD 3494 uint32_t rsvd3:16; 3495 uint32_t autoClearID:16; 3496 #else /* __LITTLE_ENDIAN_BITFIELD */ 3497 uint32_t autoClearID:16; 3498 uint32_t rsvd3:16; 3499 #endif 3500 uint32_t rsvd4; 3501 }; 3502 3503 /* SLI-2 Port Control Block */ 3504 3505 /* SLIM POINTER */ 3506 #define SLIMOFF 0x30 /* WORD */ 3507 3508 typedef struct _SLI2_RDSC { 3509 uint32_t cmdEntries; 3510 uint32_t cmdAddrLow; 3511 uint32_t cmdAddrHigh; 3512 3513 uint32_t rspEntries; 3514 uint32_t rspAddrLow; 3515 uint32_t rspAddrHigh; 3516 } SLI2_RDSC; 3517 3518 typedef struct _PCB { 3519 #ifdef __BIG_ENDIAN_BITFIELD 3520 uint32_t type:8; 3521 #define TYPE_NATIVE_SLI2 0x01 3522 uint32_t feature:8; 3523 #define FEATURE_INITIAL_SLI2 0x01 3524 uint32_t rsvd:12; 3525 uint32_t maxRing:4; 3526 #else /* __LITTLE_ENDIAN_BITFIELD */ 3527 uint32_t maxRing:4; 3528 uint32_t rsvd:12; 3529 uint32_t feature:8; 3530 #define FEATURE_INITIAL_SLI2 0x01 3531 uint32_t type:8; 3532 #define TYPE_NATIVE_SLI2 0x01 3533 #endif 3534 3535 uint32_t mailBoxSize; 3536 uint32_t mbAddrLow; 3537 uint32_t mbAddrHigh; 3538 3539 uint32_t hgpAddrLow; 3540 uint32_t hgpAddrHigh; 3541 3542 uint32_t pgpAddrLow; 3543 uint32_t pgpAddrHigh; 3544 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3545 } PCB_t; 3546 3547 /* NEW_FEATURE */ 3548 typedef struct { 3549 #ifdef __BIG_ENDIAN_BITFIELD 3550 uint32_t rsvd0:27; 3551 uint32_t discardFarp:1; 3552 uint32_t IPEnable:1; 3553 uint32_t nodeName:1; 3554 uint32_t portName:1; 3555 uint32_t filterEnable:1; 3556 #else /* __LITTLE_ENDIAN_BITFIELD */ 3557 uint32_t filterEnable:1; 3558 uint32_t portName:1; 3559 uint32_t nodeName:1; 3560 uint32_t IPEnable:1; 3561 uint32_t discardFarp:1; 3562 uint32_t rsvd:27; 3563 #endif 3564 3565 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3566 uint8_t nodename[8]; 3567 uint32_t rsvd1; 3568 uint32_t rsvd2; 3569 uint32_t rsvd3; 3570 uint32_t IPAddress; 3571 } CONFIG_FARP_VAR; 3572 3573 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3574 3575 typedef struct { 3576 #ifdef __BIG_ENDIAN_BITFIELD 3577 uint32_t rsvd:30; 3578 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3579 #else /* __LITTLE_ENDIAN */ 3580 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3581 uint32_t rsvd:30; 3582 #endif 3583 } ASYNCEVT_ENABLE_VAR; 3584 3585 /* Union of all Mailbox Command types */ 3586 #define MAILBOX_CMD_WSIZE 32 3587 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3588 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3589 #define MAILBOX_EXT_WSIZE 512 3590 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3591 #define MAILBOX_HBA_EXT_OFFSET 0x100 3592 /* max mbox xmit size is a page size for sysfs IO operations */ 3593 #define MAILBOX_SYSFS_MAX 4096 3594 3595 typedef union { 3596 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3597 * feature/max ring number 3598 */ 3599 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3600 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3601 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3602 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3603 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3604 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3605 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3606 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3607 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3608 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3609 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3610 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3611 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3612 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3613 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3614 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3615 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3616 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3617 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3618 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3619 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3620 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3621 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3622 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3623 * NEW_FEATURE 3624 */ 3625 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3626 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3627 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3628 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3629 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3630 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3631 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3632 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3633 * (READ_EVENT_LOG) 3634 */ 3635 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3636 } MAILVARIANTS; 3637 3638 /* 3639 * SLI-2 specific structures 3640 */ 3641 3642 struct lpfc_hgp { 3643 __le32 cmdPutInx; 3644 __le32 rspGetInx; 3645 }; 3646 3647 struct lpfc_pgp { 3648 __le32 cmdGetInx; 3649 __le32 rspPutInx; 3650 }; 3651 3652 struct sli2_desc { 3653 uint32_t unused1[16]; 3654 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3655 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3656 }; 3657 3658 struct sli3_desc { 3659 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3660 uint32_t reserved[8]; 3661 uint32_t hbq_put[16]; 3662 }; 3663 3664 struct sli3_pgp { 3665 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3666 uint32_t hbq_get[16]; 3667 }; 3668 3669 union sli_var { 3670 struct sli2_desc s2; 3671 struct sli3_desc s3; 3672 struct sli3_pgp s3_pgp; 3673 }; 3674 3675 typedef struct { 3676 #ifdef __BIG_ENDIAN_BITFIELD 3677 uint16_t mbxStatus; 3678 uint8_t mbxCommand; 3679 uint8_t mbxReserved:6; 3680 uint8_t mbxHc:1; 3681 uint8_t mbxOwner:1; /* Low order bit first word */ 3682 #else /* __LITTLE_ENDIAN_BITFIELD */ 3683 uint8_t mbxOwner:1; /* Low order bit first word */ 3684 uint8_t mbxHc:1; 3685 uint8_t mbxReserved:6; 3686 uint8_t mbxCommand; 3687 uint16_t mbxStatus; 3688 #endif 3689 3690 MAILVARIANTS un; 3691 union sli_var us; 3692 } MAILBOX_t; 3693 3694 /* 3695 * Begin Structure Definitions for IOCB Commands 3696 */ 3697 3698 typedef struct { 3699 #ifdef __BIG_ENDIAN_BITFIELD 3700 uint8_t statAction; 3701 uint8_t statRsn; 3702 uint8_t statBaExp; 3703 uint8_t statLocalError; 3704 #else /* __LITTLE_ENDIAN_BITFIELD */ 3705 uint8_t statLocalError; 3706 uint8_t statBaExp; 3707 uint8_t statRsn; 3708 uint8_t statAction; 3709 #endif 3710 /* statRsn P/F_RJT reason codes */ 3711 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3712 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3713 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3714 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3715 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3716 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3717 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3718 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3719 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3720 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3721 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3722 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3723 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3724 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3725 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3726 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3727 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3728 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3729 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3730 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3731 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3732 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3733 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3734 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3735 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3736 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3737 3738 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3739 #define IOERR_MISSING_CONTINUE 0x01 3740 #define IOERR_SEQUENCE_TIMEOUT 0x02 3741 #define IOERR_INTERNAL_ERROR 0x03 3742 #define IOERR_INVALID_RPI 0x04 3743 #define IOERR_NO_XRI 0x05 3744 #define IOERR_ILLEGAL_COMMAND 0x06 3745 #define IOERR_XCHG_DROPPED 0x07 3746 #define IOERR_ILLEGAL_FIELD 0x08 3747 #define IOERR_BAD_CONTINUE 0x09 3748 #define IOERR_TOO_MANY_BUFFERS 0x0A 3749 #define IOERR_RCV_BUFFER_WAITING 0x0B 3750 #define IOERR_NO_CONNECTION 0x0C 3751 #define IOERR_TX_DMA_FAILED 0x0D 3752 #define IOERR_RX_DMA_FAILED 0x0E 3753 #define IOERR_ILLEGAL_FRAME 0x0F 3754 #define IOERR_EXTRA_DATA 0x10 3755 #define IOERR_NO_RESOURCES 0x11 3756 #define IOERR_RESERVED 0x12 3757 #define IOERR_ILLEGAL_LENGTH 0x13 3758 #define IOERR_UNSUPPORTED_FEATURE 0x14 3759 #define IOERR_ABORT_IN_PROGRESS 0x15 3760 #define IOERR_ABORT_REQUESTED 0x16 3761 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3762 #define IOERR_LOOP_OPEN_FAILURE 0x18 3763 #define IOERR_RING_RESET 0x19 3764 #define IOERR_LINK_DOWN 0x1A 3765 #define IOERR_CORRUPTED_DATA 0x1B 3766 #define IOERR_CORRUPTED_RPI 0x1C 3767 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3768 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3769 #define IOERR_DUP_FRAME 0x1F 3770 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3771 #define IOERR_BAD_HOST_ADDRESS 0x21 3772 #define IOERR_RCV_HDRBUF_WAITING 0x22 3773 #define IOERR_MISSING_HDR_BUFFER 0x23 3774 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3775 #define IOERR_ABORTMULT_REQUESTED 0x25 3776 #define IOERR_BUFFER_SHORTAGE 0x28 3777 #define IOERR_DEFAULT 0x29 3778 #define IOERR_CNT 0x2A 3779 #define IOERR_SLER_FAILURE 0x46 3780 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3781 #define IOERR_SLER_REC_RJT_ERR 0x48 3782 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3783 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3784 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3785 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3786 #define IOERR_SLER_ABTS_ERR 0x4E 3787 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3788 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3789 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3790 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3791 #define IOERR_DRVR_MASK 0x100 3792 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3793 #define IOERR_SLI_BRESET 0x102 3794 #define IOERR_SLI_ABORTED 0x103 3795 #define IOERR_PARAM_MASK 0x1ff 3796 } PARM_ERR; 3797 3798 typedef union { 3799 struct { 3800 #ifdef __BIG_ENDIAN_BITFIELD 3801 uint8_t Rctl; /* R_CTL field */ 3802 uint8_t Type; /* TYPE field */ 3803 uint8_t Dfctl; /* DF_CTL field */ 3804 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3805 #else /* __LITTLE_ENDIAN_BITFIELD */ 3806 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3807 uint8_t Dfctl; /* DF_CTL field */ 3808 uint8_t Type; /* TYPE field */ 3809 uint8_t Rctl; /* R_CTL field */ 3810 #endif 3811 3812 #define BC 0x02 /* Broadcast Received - Fctl */ 3813 #define SI 0x04 /* Sequence Initiative */ 3814 #define LA 0x08 /* Ignore Link Attention state */ 3815 #define LS 0x80 /* Last Sequence */ 3816 } hcsw; 3817 uint32_t reserved; 3818 } WORD5; 3819 3820 /* IOCB Command template for a generic response */ 3821 typedef struct { 3822 uint32_t reserved[4]; 3823 PARM_ERR perr; 3824 } GENERIC_RSP; 3825 3826 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3827 typedef struct { 3828 struct ulp_bde xrsqbde[2]; 3829 uint32_t xrsqRo; /* Starting Relative Offset */ 3830 WORD5 w5; /* Header control/status word */ 3831 } XR_SEQ_FIELDS; 3832 3833 /* IOCB Command template for ELS_REQUEST */ 3834 typedef struct { 3835 struct ulp_bde elsReq; 3836 struct ulp_bde elsRsp; 3837 3838 #ifdef __BIG_ENDIAN_BITFIELD 3839 uint32_t word4Rsvd:7; 3840 uint32_t fl:1; 3841 uint32_t myID:24; 3842 uint32_t word5Rsvd:8; 3843 uint32_t remoteID:24; 3844 #else /* __LITTLE_ENDIAN_BITFIELD */ 3845 uint32_t myID:24; 3846 uint32_t fl:1; 3847 uint32_t word4Rsvd:7; 3848 uint32_t remoteID:24; 3849 uint32_t word5Rsvd:8; 3850 #endif 3851 } ELS_REQUEST; 3852 3853 /* IOCB Command template for RCV_ELS_REQ */ 3854 typedef struct { 3855 struct ulp_bde elsReq[2]; 3856 uint32_t parmRo; 3857 3858 #ifdef __BIG_ENDIAN_BITFIELD 3859 uint32_t word5Rsvd:8; 3860 uint32_t remoteID:24; 3861 #else /* __LITTLE_ENDIAN_BITFIELD */ 3862 uint32_t remoteID:24; 3863 uint32_t word5Rsvd:8; 3864 #endif 3865 } RCV_ELS_REQ; 3866 3867 /* IOCB Command template for ABORT / CLOSE_XRI */ 3868 typedef struct { 3869 uint32_t rsvd[3]; 3870 uint32_t abortType; 3871 #define ABORT_TYPE_ABTX 0x00000000 3872 #define ABORT_TYPE_ABTS 0x00000001 3873 uint32_t parm; 3874 #ifdef __BIG_ENDIAN_BITFIELD 3875 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3876 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3877 #else /* __LITTLE_ENDIAN_BITFIELD */ 3878 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3879 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3880 #endif 3881 } AC_XRI; 3882 3883 /* IOCB Command template for ABORT_MXRI64 */ 3884 typedef struct { 3885 uint32_t rsvd[3]; 3886 uint32_t abortType; 3887 uint32_t parm; 3888 uint32_t iotag32; 3889 } A_MXRI64; 3890 3891 /* IOCB Command template for GET_RPI */ 3892 typedef struct { 3893 uint32_t rsvd[4]; 3894 uint32_t parmRo; 3895 #ifdef __BIG_ENDIAN_BITFIELD 3896 uint32_t word5Rsvd:8; 3897 uint32_t remoteID:24; 3898 #else /* __LITTLE_ENDIAN_BITFIELD */ 3899 uint32_t remoteID:24; 3900 uint32_t word5Rsvd:8; 3901 #endif 3902 } GET_RPI; 3903 3904 /* IOCB Command template for all FCP Initiator commands */ 3905 typedef struct { 3906 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3907 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3908 uint32_t fcpi_parm; 3909 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3910 } FCPI_FIELDS; 3911 3912 /* IOCB Command template for all FCP Target commands */ 3913 typedef struct { 3914 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3915 uint32_t fcpt_Offset; 3916 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3917 } FCPT_FIELDS; 3918 3919 /* SLI-2 IOCB structure definitions */ 3920 3921 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3922 typedef struct { 3923 ULP_BDL bdl; 3924 uint32_t xrsqRo; /* Starting Relative Offset */ 3925 WORD5 w5; /* Header control/status word */ 3926 } XMT_SEQ_FIELDS64; 3927 3928 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 3929 #define xmit_els_remoteID xrsqRo 3930 3931 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3932 typedef struct { 3933 struct ulp_bde64 rcvBde; 3934 uint32_t rsvd1; 3935 uint32_t xrsqRo; /* Starting Relative Offset */ 3936 WORD5 w5; /* Header control/status word */ 3937 } RCV_SEQ_FIELDS64; 3938 3939 /* IOCB Command template for ELS_REQUEST64 */ 3940 typedef struct { 3941 ULP_BDL bdl; 3942 #ifdef __BIG_ENDIAN_BITFIELD 3943 uint32_t word4Rsvd:7; 3944 uint32_t fl:1; 3945 uint32_t myID:24; 3946 uint32_t word5Rsvd:8; 3947 uint32_t remoteID:24; 3948 #else /* __LITTLE_ENDIAN_BITFIELD */ 3949 uint32_t myID:24; 3950 uint32_t fl:1; 3951 uint32_t word4Rsvd:7; 3952 uint32_t remoteID:24; 3953 uint32_t word5Rsvd:8; 3954 #endif 3955 } ELS_REQUEST64; 3956 3957 /* IOCB Command template for GEN_REQUEST64 */ 3958 typedef struct { 3959 ULP_BDL bdl; 3960 uint32_t xrsqRo; /* Starting Relative Offset */ 3961 WORD5 w5; /* Header control/status word */ 3962 } GEN_REQUEST64; 3963 3964 /* IOCB Command template for RCV_ELS_REQ64 */ 3965 typedef struct { 3966 struct ulp_bde64 elsReq; 3967 uint32_t rcvd1; 3968 uint32_t parmRo; 3969 3970 #ifdef __BIG_ENDIAN_BITFIELD 3971 uint32_t word5Rsvd:8; 3972 uint32_t remoteID:24; 3973 #else /* __LITTLE_ENDIAN_BITFIELD */ 3974 uint32_t remoteID:24; 3975 uint32_t word5Rsvd:8; 3976 #endif 3977 } RCV_ELS_REQ64; 3978 3979 /* IOCB Command template for RCV_SEQ64 */ 3980 struct rcv_seq64 { 3981 struct ulp_bde64 elsReq; 3982 uint32_t hbq_1; 3983 uint32_t parmRo; 3984 #ifdef __BIG_ENDIAN_BITFIELD 3985 uint32_t rctl:8; 3986 uint32_t type:8; 3987 uint32_t dfctl:8; 3988 uint32_t ls:1; 3989 uint32_t fs:1; 3990 uint32_t rsvd2:3; 3991 uint32_t si:1; 3992 uint32_t bc:1; 3993 uint32_t rsvd3:1; 3994 #else /* __LITTLE_ENDIAN_BITFIELD */ 3995 uint32_t rsvd3:1; 3996 uint32_t bc:1; 3997 uint32_t si:1; 3998 uint32_t rsvd2:3; 3999 uint32_t fs:1; 4000 uint32_t ls:1; 4001 uint32_t dfctl:8; 4002 uint32_t type:8; 4003 uint32_t rctl:8; 4004 #endif 4005 }; 4006 4007 /* IOCB Command template for all 64 bit FCP Initiator commands */ 4008 typedef struct { 4009 ULP_BDL bdl; 4010 uint32_t fcpi_parm; 4011 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 4012 } FCPI_FIELDS64; 4013 4014 /* IOCB Command template for all 64 bit FCP Target commands */ 4015 typedef struct { 4016 ULP_BDL bdl; 4017 uint32_t fcpt_Offset; 4018 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 4019 } FCPT_FIELDS64; 4020 4021 /* IOCB Command template for Async Status iocb commands */ 4022 typedef struct { 4023 uint32_t rsvd[4]; 4024 uint32_t param; 4025 #ifdef __BIG_ENDIAN_BITFIELD 4026 uint16_t evt_code; /* High order bits word 5 */ 4027 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 4028 #else /* __LITTLE_ENDIAN_BITFIELD */ 4029 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 4030 uint16_t evt_code; /* Low order bits word 5 */ 4031 #endif 4032 } ASYNCSTAT_FIELDS; 4033 #define ASYNC_TEMP_WARN 0x100 4034 #define ASYNC_TEMP_SAFE 0x101 4035 #define ASYNC_STATUS_CN 0x102 4036 4037 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 4038 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 4039 4040 struct rcv_sli3 { 4041 #ifdef __BIG_ENDIAN_BITFIELD 4042 uint16_t ox_id; 4043 uint16_t seq_cnt; 4044 4045 uint16_t vpi; 4046 uint16_t word9Rsvd; 4047 #else /* __LITTLE_ENDIAN */ 4048 uint16_t seq_cnt; 4049 uint16_t ox_id; 4050 4051 uint16_t word9Rsvd; 4052 uint16_t vpi; 4053 #endif 4054 uint32_t word10Rsvd; 4055 uint32_t acc_len; /* accumulated length */ 4056 struct ulp_bde64 bde2; 4057 }; 4058 4059 /* Structure used for a single HBQ entry */ 4060 struct lpfc_hbq_entry { 4061 struct ulp_bde64 bde; 4062 uint32_t buffer_tag; 4063 }; 4064 4065 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 4066 typedef struct { 4067 struct lpfc_hbq_entry buff; 4068 uint32_t rsvd; 4069 uint32_t rsvd1; 4070 } QUE_XRI64_CX_FIELDS; 4071 4072 struct que_xri64cx_ext_fields { 4073 uint32_t iotag64_low; 4074 uint32_t iotag64_high; 4075 uint32_t ebde_count; 4076 uint32_t rsvd; 4077 struct lpfc_hbq_entry buff[5]; 4078 }; 4079 4080 struct sli3_bg_fields { 4081 uint32_t filler[6]; /* word 8-13 in IOCB */ 4082 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 4083 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 4084 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 4085 #define BGS_BIDIR_BG_PROF_SHIFT 24 4086 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 4087 #define BGS_BIDIR_ERR_COND_SHIFT 16 4088 #define BGS_BG_PROFILE_MASK 0x0000ff00 4089 #define BGS_BG_PROFILE_SHIFT 8 4090 #define BGS_INVALID_PROF_MASK 0x00000020 4091 #define BGS_INVALID_PROF_SHIFT 5 4092 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 4093 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 4094 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 4095 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 4096 #define BGS_REFTAG_ERR_MASK 0x00000004 4097 #define BGS_REFTAG_ERR_SHIFT 2 4098 #define BGS_APPTAG_ERR_MASK 0x00000002 4099 #define BGS_APPTAG_ERR_SHIFT 1 4100 #define BGS_GUARD_ERR_MASK 0x00000001 4101 #define BGS_GUARD_ERR_SHIFT 0 4102 uint32_t bgstat; /* word 15 - BlockGuard Status */ 4103 }; 4104 4105 static inline uint32_t 4106 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 4107 { 4108 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 4109 BGS_BIDIR_BG_PROF_SHIFT; 4110 } 4111 4112 static inline uint32_t 4113 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 4114 { 4115 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 4116 BGS_BIDIR_ERR_COND_SHIFT; 4117 } 4118 4119 static inline uint32_t 4120 lpfc_bgs_get_bg_prof(uint32_t bgstat) 4121 { 4122 return (bgstat & BGS_BG_PROFILE_MASK) >> 4123 BGS_BG_PROFILE_SHIFT; 4124 } 4125 4126 static inline uint32_t 4127 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 4128 { 4129 return (bgstat & BGS_INVALID_PROF_MASK) >> 4130 BGS_INVALID_PROF_SHIFT; 4131 } 4132 4133 static inline uint32_t 4134 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 4135 { 4136 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 4137 BGS_UNINIT_DIF_BLOCK_SHIFT; 4138 } 4139 4140 static inline uint32_t 4141 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 4142 { 4143 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 4144 BGS_HI_WATER_MARK_PRESENT_SHIFT; 4145 } 4146 4147 static inline uint32_t 4148 lpfc_bgs_get_reftag_err(uint32_t bgstat) 4149 { 4150 return (bgstat & BGS_REFTAG_ERR_MASK) >> 4151 BGS_REFTAG_ERR_SHIFT; 4152 } 4153 4154 static inline uint32_t 4155 lpfc_bgs_get_apptag_err(uint32_t bgstat) 4156 { 4157 return (bgstat & BGS_APPTAG_ERR_MASK) >> 4158 BGS_APPTAG_ERR_SHIFT; 4159 } 4160 4161 static inline uint32_t 4162 lpfc_bgs_get_guard_err(uint32_t bgstat) 4163 { 4164 return (bgstat & BGS_GUARD_ERR_MASK) >> 4165 BGS_GUARD_ERR_SHIFT; 4166 } 4167 4168 #define LPFC_EXT_DATA_BDE_COUNT 3 4169 struct fcp_irw_ext { 4170 uint32_t io_tag64_low; 4171 uint32_t io_tag64_high; 4172 #ifdef __BIG_ENDIAN_BITFIELD 4173 uint8_t reserved1; 4174 uint8_t reserved2; 4175 uint8_t reserved3; 4176 uint8_t ebde_count; 4177 #else /* __LITTLE_ENDIAN */ 4178 uint8_t ebde_count; 4179 uint8_t reserved3; 4180 uint8_t reserved2; 4181 uint8_t reserved1; 4182 #endif 4183 uint32_t reserved4; 4184 struct ulp_bde64 rbde; /* response bde */ 4185 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4186 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4187 }; 4188 4189 typedef struct _IOCB { /* IOCB structure */ 4190 union { 4191 GENERIC_RSP grsp; /* Generic response */ 4192 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4193 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4194 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4195 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4196 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4197 GET_RPI getrpi; /* GET_RPI template */ 4198 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4199 FCPT_FIELDS fcpt; /* FCP target template */ 4200 4201 /* SLI-2 structures */ 4202 4203 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4204 * bde_64s */ 4205 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4206 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4207 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4208 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4209 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4210 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4211 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4212 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4213 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4214 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4215 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4216 } un; 4217 union { 4218 struct { 4219 #ifdef __BIG_ENDIAN_BITFIELD 4220 uint16_t ulpContext; /* High order bits word 6 */ 4221 uint16_t ulpIoTag; /* Low order bits word 6 */ 4222 #else /* __LITTLE_ENDIAN_BITFIELD */ 4223 uint16_t ulpIoTag; /* Low order bits word 6 */ 4224 uint16_t ulpContext; /* High order bits word 6 */ 4225 #endif 4226 } t1; 4227 struct { 4228 #ifdef __BIG_ENDIAN_BITFIELD 4229 uint16_t ulpContext; /* High order bits word 6 */ 4230 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4231 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4232 #else /* __LITTLE_ENDIAN_BITFIELD */ 4233 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4234 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4235 uint16_t ulpContext; /* High order bits word 6 */ 4236 #endif 4237 } t2; 4238 } un1; 4239 #define ulpContext un1.t1.ulpContext 4240 #define ulpIoTag un1.t1.ulpIoTag 4241 #define ulpIoTag0 un1.t2.ulpIoTag0 4242 4243 #ifdef __BIG_ENDIAN_BITFIELD 4244 uint32_t ulpTimeout:8; 4245 uint32_t ulpXS:1; 4246 uint32_t ulpFCP2Rcvy:1; 4247 uint32_t ulpPU:2; 4248 uint32_t ulpIr:1; 4249 uint32_t ulpClass:3; 4250 uint32_t ulpCommand:8; 4251 uint32_t ulpStatus:4; 4252 uint32_t ulpBdeCount:2; 4253 uint32_t ulpLe:1; 4254 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4255 #else /* __LITTLE_ENDIAN_BITFIELD */ 4256 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4257 uint32_t ulpLe:1; 4258 uint32_t ulpBdeCount:2; 4259 uint32_t ulpStatus:4; 4260 uint32_t ulpCommand:8; 4261 uint32_t ulpClass:3; 4262 uint32_t ulpIr:1; 4263 uint32_t ulpPU:2; 4264 uint32_t ulpFCP2Rcvy:1; 4265 uint32_t ulpXS:1; 4266 uint32_t ulpTimeout:8; 4267 #endif 4268 4269 union { 4270 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4271 4272 /* words 8-31 used for que_xri_cx iocb */ 4273 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4274 struct fcp_irw_ext fcp_ext; 4275 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4276 4277 /* words 8-15 for BlockGuard */ 4278 struct sli3_bg_fields sli3_bg; 4279 } unsli3; 4280 4281 #define ulpCt_h ulpXS 4282 #define ulpCt_l ulpFCP2Rcvy 4283 4284 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4285 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4286 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4287 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4288 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4289 #define PARM_NPIV_DID 3 4290 #define CLASS1 0 /* Class 1 */ 4291 #define CLASS2 1 /* Class 2 */ 4292 #define CLASS3 2 /* Class 3 */ 4293 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4294 4295 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4296 #define IOSTAT_FCP_RSP_ERROR 0x1 4297 #define IOSTAT_REMOTE_STOP 0x2 4298 #define IOSTAT_LOCAL_REJECT 0x3 4299 #define IOSTAT_NPORT_RJT 0x4 4300 #define IOSTAT_FABRIC_RJT 0x5 4301 #define IOSTAT_NPORT_BSY 0x6 4302 #define IOSTAT_FABRIC_BSY 0x7 4303 #define IOSTAT_INTERMED_RSP 0x8 4304 #define IOSTAT_LS_RJT 0x9 4305 #define IOSTAT_BA_RJT 0xA 4306 #define IOSTAT_RSVD1 0xB 4307 #define IOSTAT_RSVD2 0xC 4308 #define IOSTAT_RSVD3 0xD 4309 #define IOSTAT_RSVD4 0xE 4310 #define IOSTAT_NEED_BUFFER 0xF 4311 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4312 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4313 #define IOSTAT_CNT 0x11 4314 4315 } IOCB_t; 4316 4317 4318 #define SLI1_SLIM_SIZE (4 * 1024) 4319 4320 /* Up to 498 IOCBs will fit into 16k 4321 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4322 */ 4323 #define SLI2_SLIM_SIZE (64 * 1024) 4324 4325 /* Maximum IOCBs that will fit in SLI2 slim */ 4326 #define MAX_SLI2_IOCB 498 4327 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4328 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4329 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4330 4331 /* HBQ entries are 4 words each = 4k */ 4332 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4333 lpfc_sli_hbq_count()) 4334 4335 struct lpfc_sli2_slim { 4336 MAILBOX_t mbx; 4337 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4338 PCB_t pcb; 4339 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4340 }; 4341 4342 /* 4343 * This function checks PCI device to allow special handling for LC HBAs. 4344 * 4345 * Parameters: 4346 * device : struct pci_dev 's device field 4347 * 4348 * return 1 => TRUE 4349 * 0 => FALSE 4350 */ 4351 static inline int 4352 lpfc_is_LC_HBA(unsigned short device) 4353 { 4354 if ((device == PCI_DEVICE_ID_TFLY) || 4355 (device == PCI_DEVICE_ID_PFLY) || 4356 (device == PCI_DEVICE_ID_LP101) || 4357 (device == PCI_DEVICE_ID_BMID) || 4358 (device == PCI_DEVICE_ID_BSMB) || 4359 (device == PCI_DEVICE_ID_ZMID) || 4360 (device == PCI_DEVICE_ID_ZSMB) || 4361 (device == PCI_DEVICE_ID_SAT_MID) || 4362 (device == PCI_DEVICE_ID_SAT_SMB) || 4363 (device == PCI_DEVICE_ID_RFLY)) 4364 return 1; 4365 else 4366 return 0; 4367 } 4368 4369 /* 4370 * Determine if an IOCB failed because of a link event or firmware reset. 4371 */ 4372 4373 static inline int 4374 lpfc_error_lost_link(IOCB_t *iocbp) 4375 { 4376 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 4377 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 4378 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 4379 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 4380 } 4381 4382 #define MENLO_TRANSPORT_TYPE 0xfe 4383 #define MENLO_CONTEXT 0 4384 #define MENLO_PU 3 4385 #define MENLO_TIMEOUT 30 4386 #define SETVAR_MLOMNT 0x103107 4387 #define SETVAR_MLORST 0x103007 4388 4389 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4390