1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2007 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 57 #define SLI2_IOCB_CMD_R3_ENTRIES 0 58 #define SLI2_IOCB_RSP_R3_ENTRIES 0 59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 61 62 #define SLI2_IOCB_CMD_SIZE 32 63 #define SLI2_IOCB_RSP_SIZE 32 64 #define SLI3_IOCB_CMD_SIZE 128 65 #define SLI3_IOCB_RSP_SIZE 64 66 67 68 /* Common Transport structures and definitions */ 69 70 union CtRevisionId { 71 /* Structure is in Big Endian format */ 72 struct { 73 uint32_t Revision:8; 74 uint32_t InId:24; 75 } bits; 76 uint32_t word; 77 }; 78 79 union CtCommandResponse { 80 /* Structure is in Big Endian format */ 81 struct { 82 uint32_t CmdRsp:16; 83 uint32_t Size:16; 84 } bits; 85 uint32_t word; 86 }; 87 88 #define FC4_FEATURE_INIT 0x2 89 #define FC4_FEATURE_TARGET 0x1 90 91 struct lpfc_sli_ct_request { 92 /* Structure is in Big Endian format */ 93 union CtRevisionId RevisionId; 94 uint8_t FsType; 95 uint8_t FsSubType; 96 uint8_t Options; 97 uint8_t Rsrvd1; 98 union CtCommandResponse CommandResponse; 99 uint8_t Rsrvd2; 100 uint8_t ReasonCode; 101 uint8_t Explanation; 102 uint8_t VendorUnique; 103 104 union { 105 uint32_t PortID; 106 struct gid { 107 uint8_t PortType; /* for GID_PT requests */ 108 uint8_t DomainScope; 109 uint8_t AreaScope; 110 uint8_t Fc4Type; /* for GID_FT requests */ 111 } gid; 112 struct rft { 113 uint32_t PortId; /* For RFT_ID requests */ 114 115 #ifdef __BIG_ENDIAN_BITFIELD 116 uint32_t rsvd0:16; 117 uint32_t rsvd1:7; 118 uint32_t fcpReg:1; /* Type 8 */ 119 uint32_t rsvd2:2; 120 uint32_t ipReg:1; /* Type 5 */ 121 uint32_t rsvd3:5; 122 #else /* __LITTLE_ENDIAN_BITFIELD */ 123 uint32_t rsvd0:16; 124 uint32_t fcpReg:1; /* Type 8 */ 125 uint32_t rsvd1:7; 126 uint32_t rsvd3:5; 127 uint32_t ipReg:1; /* Type 5 */ 128 uint32_t rsvd2:2; 129 #endif 130 131 uint32_t rsvd[7]; 132 } rft; 133 struct rnn { 134 uint32_t PortId; /* For RNN_ID requests */ 135 uint8_t wwnn[8]; 136 } rnn; 137 struct rsnn { /* For RSNN_ID requests */ 138 uint8_t wwnn[8]; 139 uint8_t len; 140 uint8_t symbname[255]; 141 } rsnn; 142 struct da_id { /* For DA_ID requests */ 143 uint32_t port_id; 144 } da_id; 145 struct rspn { /* For RSPN_ID requests */ 146 uint32_t PortId; 147 uint8_t len; 148 uint8_t symbname[255]; 149 } rspn; 150 struct gff { 151 uint32_t PortId; 152 } gff; 153 struct gff_acc { 154 uint8_t fbits[128]; 155 } gff_acc; 156 #define FCP_TYPE_FEATURE_OFFSET 7 157 struct rff { 158 uint32_t PortId; 159 uint8_t reserved[2]; 160 uint8_t fbits; 161 uint8_t type_code; /* type=8 for FCP */ 162 } rff; 163 } un; 164 }; 165 166 #define SLI_CT_REVISION 1 167 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 168 sizeof(struct gid)) 169 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 170 sizeof(struct gff)) 171 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 172 sizeof(struct rft)) 173 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 174 sizeof(struct rff)) 175 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 176 sizeof(struct rnn)) 177 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 178 sizeof(struct rsnn)) 179 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 180 sizeof(struct da_id)) 181 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 182 sizeof(struct rspn)) 183 184 /* 185 * FsType Definitions 186 */ 187 188 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 189 #define SLI_CT_TIME_SERVICE 0xFB 190 #define SLI_CT_DIRECTORY_SERVICE 0xFC 191 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 192 193 /* 194 * Directory Service Subtypes 195 */ 196 197 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 198 199 /* 200 * Response Codes 201 */ 202 203 #define SLI_CT_RESPONSE_FS_RJT 0x8001 204 #define SLI_CT_RESPONSE_FS_ACC 0x8002 205 206 /* 207 * Reason Codes 208 */ 209 210 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 211 #define SLI_CT_INVALID_COMMAND 0x01 212 #define SLI_CT_INVALID_VERSION 0x02 213 #define SLI_CT_LOGICAL_ERROR 0x03 214 #define SLI_CT_INVALID_IU_SIZE 0x04 215 #define SLI_CT_LOGICAL_BUSY 0x05 216 #define SLI_CT_PROTOCOL_ERROR 0x07 217 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 218 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 219 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 220 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 221 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 222 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 223 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 224 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 225 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 226 #define SLI_CT_VENDOR_UNIQUE 0xff 227 228 /* 229 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 230 */ 231 232 #define SLI_CT_NO_PORT_ID 0x01 233 #define SLI_CT_NO_PORT_NAME 0x02 234 #define SLI_CT_NO_NODE_NAME 0x03 235 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 236 #define SLI_CT_NO_IP_ADDRESS 0x05 237 #define SLI_CT_NO_IPA 0x06 238 #define SLI_CT_NO_FC4_TYPES 0x07 239 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 240 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 241 #define SLI_CT_NO_PORT_TYPE 0x0A 242 #define SLI_CT_ACCESS_DENIED 0x10 243 #define SLI_CT_INVALID_PORT_ID 0x11 244 #define SLI_CT_DATABASE_EMPTY 0x12 245 246 /* 247 * Name Server Command Codes 248 */ 249 250 #define SLI_CTNS_GA_NXT 0x0100 251 #define SLI_CTNS_GPN_ID 0x0112 252 #define SLI_CTNS_GNN_ID 0x0113 253 #define SLI_CTNS_GCS_ID 0x0114 254 #define SLI_CTNS_GFT_ID 0x0117 255 #define SLI_CTNS_GSPN_ID 0x0118 256 #define SLI_CTNS_GPT_ID 0x011A 257 #define SLI_CTNS_GFF_ID 0x011F 258 #define SLI_CTNS_GID_PN 0x0121 259 #define SLI_CTNS_GID_NN 0x0131 260 #define SLI_CTNS_GIP_NN 0x0135 261 #define SLI_CTNS_GIPA_NN 0x0136 262 #define SLI_CTNS_GSNN_NN 0x0139 263 #define SLI_CTNS_GNN_IP 0x0153 264 #define SLI_CTNS_GIPA_IP 0x0156 265 #define SLI_CTNS_GID_FT 0x0171 266 #define SLI_CTNS_GID_PT 0x01A1 267 #define SLI_CTNS_RPN_ID 0x0212 268 #define SLI_CTNS_RNN_ID 0x0213 269 #define SLI_CTNS_RCS_ID 0x0214 270 #define SLI_CTNS_RFT_ID 0x0217 271 #define SLI_CTNS_RSPN_ID 0x0218 272 #define SLI_CTNS_RPT_ID 0x021A 273 #define SLI_CTNS_RFF_ID 0x021F 274 #define SLI_CTNS_RIP_NN 0x0235 275 #define SLI_CTNS_RIPA_NN 0x0236 276 #define SLI_CTNS_RSNN_NN 0x0239 277 #define SLI_CTNS_DA_ID 0x0300 278 279 /* 280 * Port Types 281 */ 282 283 #define SLI_CTPT_N_PORT 0x01 284 #define SLI_CTPT_NL_PORT 0x02 285 #define SLI_CTPT_FNL_PORT 0x03 286 #define SLI_CTPT_IP 0x04 287 #define SLI_CTPT_FCP 0x08 288 #define SLI_CTPT_NX_PORT 0x7F 289 #define SLI_CTPT_F_PORT 0x81 290 #define SLI_CTPT_FL_PORT 0x82 291 #define SLI_CTPT_E_PORT 0x84 292 293 #define SLI_CT_LAST_ENTRY 0x80000000 294 295 /* Fibre Channel Service Parameter definitions */ 296 297 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 298 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 299 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 300 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 301 302 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 303 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 304 #define FC_PH3 0x20 /* FC-PH-3 version */ 305 306 #define FF_FRAME_SIZE 2048 307 308 struct lpfc_name { 309 union { 310 struct { 311 #ifdef __BIG_ENDIAN_BITFIELD 312 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 313 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 314 8:11 of IEEE ext */ 315 #else /* __LITTLE_ENDIAN_BITFIELD */ 316 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 317 8:11 of IEEE ext */ 318 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 319 #endif 320 321 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 322 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 323 #define NAME_FC_TYPE 0x3 /* FC native name type */ 324 #define NAME_IP_TYPE 0x4 /* IP address */ 325 #define NAME_CCITT_TYPE 0xC 326 #define NAME_CCITT_GR_TYPE 0xE 327 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 328 extended Lsb */ 329 uint8_t IEEE[6]; /* FC IEEE address */ 330 } s; 331 uint8_t wwn[8]; 332 } u; 333 }; 334 335 struct csp { 336 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 337 uint8_t fcphLow; 338 uint8_t bbCreditMsb; 339 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 340 341 #ifdef __BIG_ENDIAN_BITFIELD 342 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 343 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 344 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 345 uint16_t fPort:1; /* FC Word 1, bit 28 */ 346 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 347 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 348 uint16_t multicast:1; /* FC Word 1, bit 25 */ 349 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 350 351 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 352 uint16_t simplex:1; /* FC Word 1, bit 22 */ 353 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 354 uint16_t dhd:1; /* FC Word 1, bit 18 */ 355 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 356 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 357 #else /* __LITTLE_ENDIAN_BITFIELD */ 358 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 359 uint16_t multicast:1; /* FC Word 1, bit 25 */ 360 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 361 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 362 uint16_t fPort:1; /* FC Word 1, bit 28 */ 363 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 364 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 365 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 366 367 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 368 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 369 uint16_t dhd:1; /* FC Word 1, bit 18 */ 370 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 371 uint16_t simplex:1; /* FC Word 1, bit 22 */ 372 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 373 #endif 374 375 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 376 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 377 union { 378 struct { 379 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 380 381 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 382 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 383 384 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 385 } nPort; 386 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 387 } w2; 388 389 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 390 }; 391 392 struct class_parms { 393 #ifdef __BIG_ENDIAN_BITFIELD 394 uint8_t classValid:1; /* FC Word 0, bit 31 */ 395 uint8_t intermix:1; /* FC Word 0, bit 30 */ 396 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 397 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 398 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 399 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 400 #else /* __LITTLE_ENDIAN_BITFIELD */ 401 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 402 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 403 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 404 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 405 uint8_t intermix:1; /* FC Word 0, bit 30 */ 406 uint8_t classValid:1; /* FC Word 0, bit 31 */ 407 408 #endif 409 410 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 411 412 #ifdef __BIG_ENDIAN_BITFIELD 413 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 414 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 415 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 416 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 417 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 418 #else /* __LITTLE_ENDIAN_BITFIELD */ 419 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 420 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 421 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 422 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 423 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 424 #endif 425 426 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 427 428 #ifdef __BIG_ENDIAN_BITFIELD 429 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 430 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 431 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 432 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 433 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 434 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 435 #else /* __LITTLE_ENDIAN_BITFIELD */ 436 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 437 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 438 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 439 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 440 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 441 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 442 #endif 443 444 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 445 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 446 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 447 448 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 449 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 450 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 451 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 452 453 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 454 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 455 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 456 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 457 }; 458 459 struct serv_parm { /* Structure is in Big Endian format */ 460 struct csp cmn; 461 struct lpfc_name portName; 462 struct lpfc_name nodeName; 463 struct class_parms cls1; 464 struct class_parms cls2; 465 struct class_parms cls3; 466 struct class_parms cls4; 467 uint8_t vendorVersion[16]; 468 }; 469 470 /* 471 * Extended Link Service LS_COMMAND codes (Payload Word 0) 472 */ 473 #ifdef __BIG_ENDIAN_BITFIELD 474 #define ELS_CMD_MASK 0xffff0000 475 #define ELS_RSP_MASK 0xff000000 476 #define ELS_CMD_LS_RJT 0x01000000 477 #define ELS_CMD_ACC 0x02000000 478 #define ELS_CMD_PLOGI 0x03000000 479 #define ELS_CMD_FLOGI 0x04000000 480 #define ELS_CMD_LOGO 0x05000000 481 #define ELS_CMD_ABTX 0x06000000 482 #define ELS_CMD_RCS 0x07000000 483 #define ELS_CMD_RES 0x08000000 484 #define ELS_CMD_RSS 0x09000000 485 #define ELS_CMD_RSI 0x0A000000 486 #define ELS_CMD_ESTS 0x0B000000 487 #define ELS_CMD_ESTC 0x0C000000 488 #define ELS_CMD_ADVC 0x0D000000 489 #define ELS_CMD_RTV 0x0E000000 490 #define ELS_CMD_RLS 0x0F000000 491 #define ELS_CMD_ECHO 0x10000000 492 #define ELS_CMD_TEST 0x11000000 493 #define ELS_CMD_RRQ 0x12000000 494 #define ELS_CMD_PRLI 0x20100014 495 #define ELS_CMD_PRLO 0x21100014 496 #define ELS_CMD_PRLO_ACC 0x02100014 497 #define ELS_CMD_PDISC 0x50000000 498 #define ELS_CMD_FDISC 0x51000000 499 #define ELS_CMD_ADISC 0x52000000 500 #define ELS_CMD_FARP 0x54000000 501 #define ELS_CMD_FARPR 0x55000000 502 #define ELS_CMD_RPS 0x56000000 503 #define ELS_CMD_RPL 0x57000000 504 #define ELS_CMD_FAN 0x60000000 505 #define ELS_CMD_RSCN 0x61040000 506 #define ELS_CMD_SCR 0x62000000 507 #define ELS_CMD_RNID 0x78000000 508 #define ELS_CMD_LIRR 0x7A000000 509 #else /* __LITTLE_ENDIAN_BITFIELD */ 510 #define ELS_CMD_MASK 0xffff 511 #define ELS_RSP_MASK 0xff 512 #define ELS_CMD_LS_RJT 0x01 513 #define ELS_CMD_ACC 0x02 514 #define ELS_CMD_PLOGI 0x03 515 #define ELS_CMD_FLOGI 0x04 516 #define ELS_CMD_LOGO 0x05 517 #define ELS_CMD_ABTX 0x06 518 #define ELS_CMD_RCS 0x07 519 #define ELS_CMD_RES 0x08 520 #define ELS_CMD_RSS 0x09 521 #define ELS_CMD_RSI 0x0A 522 #define ELS_CMD_ESTS 0x0B 523 #define ELS_CMD_ESTC 0x0C 524 #define ELS_CMD_ADVC 0x0D 525 #define ELS_CMD_RTV 0x0E 526 #define ELS_CMD_RLS 0x0F 527 #define ELS_CMD_ECHO 0x10 528 #define ELS_CMD_TEST 0x11 529 #define ELS_CMD_RRQ 0x12 530 #define ELS_CMD_PRLI 0x14001020 531 #define ELS_CMD_PRLO 0x14001021 532 #define ELS_CMD_PRLO_ACC 0x14001002 533 #define ELS_CMD_PDISC 0x50 534 #define ELS_CMD_FDISC 0x51 535 #define ELS_CMD_ADISC 0x52 536 #define ELS_CMD_FARP 0x54 537 #define ELS_CMD_FARPR 0x55 538 #define ELS_CMD_RPS 0x56 539 #define ELS_CMD_RPL 0x57 540 #define ELS_CMD_FAN 0x60 541 #define ELS_CMD_RSCN 0x0461 542 #define ELS_CMD_SCR 0x62 543 #define ELS_CMD_RNID 0x78 544 #define ELS_CMD_LIRR 0x7A 545 #endif 546 547 /* 548 * LS_RJT Payload Definition 549 */ 550 551 struct ls_rjt { /* Structure is in Big Endian format */ 552 union { 553 uint32_t lsRjtError; 554 struct { 555 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 556 557 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 558 /* LS_RJT reason codes */ 559 #define LSRJT_INVALID_CMD 0x01 560 #define LSRJT_LOGICAL_ERR 0x03 561 #define LSRJT_LOGICAL_BSY 0x05 562 #define LSRJT_PROTOCOL_ERR 0x07 563 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 564 #define LSRJT_CMD_UNSUPPORTED 0x0B 565 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 566 567 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 568 /* LS_RJT reason explanation */ 569 #define LSEXP_NOTHING_MORE 0x00 570 #define LSEXP_SPARM_OPTIONS 0x01 571 #define LSEXP_SPARM_ICTL 0x03 572 #define LSEXP_SPARM_RCTL 0x05 573 #define LSEXP_SPARM_RCV_SIZE 0x07 574 #define LSEXP_SPARM_CONCUR_SEQ 0x09 575 #define LSEXP_SPARM_CREDIT 0x0B 576 #define LSEXP_INVALID_PNAME 0x0D 577 #define LSEXP_INVALID_NNAME 0x0E 578 #define LSEXP_INVALID_CSP 0x0F 579 #define LSEXP_INVALID_ASSOC_HDR 0x11 580 #define LSEXP_ASSOC_HDR_REQ 0x13 581 #define LSEXP_INVALID_O_SID 0x15 582 #define LSEXP_INVALID_OX_RX 0x17 583 #define LSEXP_CMD_IN_PROGRESS 0x19 584 #define LSEXP_INVALID_NPORT_ID 0x1F 585 #define LSEXP_INVALID_SEQ_ID 0x21 586 #define LSEXP_INVALID_XCHG 0x23 587 #define LSEXP_INACTIVE_XCHG 0x25 588 #define LSEXP_RQ_REQUIRED 0x27 589 #define LSEXP_OUT_OF_RESOURCE 0x29 590 #define LSEXP_CANT_GIVE_DATA 0x2A 591 #define LSEXP_REQ_UNSUPPORTED 0x2C 592 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 593 } b; 594 } un; 595 }; 596 597 /* 598 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 599 */ 600 601 typedef struct _LOGO { /* Structure is in Big Endian format */ 602 union { 603 uint32_t nPortId32; /* Access nPortId as a word */ 604 struct { 605 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 606 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 607 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 608 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 609 } b; 610 } un; 611 struct lpfc_name portName; /* N_port name field */ 612 } LOGO; 613 614 /* 615 * FCP Login (PRLI Request / ACC) Payload Definition 616 */ 617 618 #define PRLX_PAGE_LEN 0x10 619 #define TPRLO_PAGE_LEN 0x14 620 621 typedef struct _PRLI { /* Structure is in Big Endian format */ 622 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 623 624 #define PRLI_FCP_TYPE 0x08 625 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 626 627 #ifdef __BIG_ENDIAN_BITFIELD 628 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 629 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 630 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 631 632 /* ACC = imagePairEstablished */ 633 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 634 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 635 #else /* __LITTLE_ENDIAN_BITFIELD */ 636 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 637 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 638 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 639 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 640 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 641 /* ACC = imagePairEstablished */ 642 #endif 643 644 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 645 #define PRLI_NO_RESOURCES 0x2 646 #define PRLI_INIT_INCOMPLETE 0x3 647 #define PRLI_NO_SUCH_PA 0x4 648 #define PRLI_PREDEF_CONFIG 0x5 649 #define PRLI_PARTIAL_SUCCESS 0x6 650 #define PRLI_INVALID_PAGE_CNT 0x7 651 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 652 653 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 654 655 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 656 657 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 658 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 659 660 #ifdef __BIG_ENDIAN_BITFIELD 661 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 662 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 663 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 664 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 665 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 666 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 667 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 668 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 669 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 670 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 671 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 672 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 673 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 674 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 675 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 676 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 677 #else /* __LITTLE_ENDIAN_BITFIELD */ 678 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 679 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 680 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 681 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 682 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 683 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 684 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 685 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 686 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 687 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 688 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 689 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 690 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 691 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 692 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 693 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 694 #endif 695 } PRLI; 696 697 /* 698 * FCP Logout (PRLO Request / ACC) Payload Definition 699 */ 700 701 typedef struct _PRLO { /* Structure is in Big Endian format */ 702 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 703 704 #define PRLO_FCP_TYPE 0x08 705 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 706 707 #ifdef __BIG_ENDIAN_BITFIELD 708 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 709 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 710 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 711 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 712 #else /* __LITTLE_ENDIAN_BITFIELD */ 713 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 714 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 715 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 716 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 717 #endif 718 719 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 720 #define PRLO_NO_SUCH_IMAGE 0x4 721 #define PRLO_INVALID_PAGE_CNT 0x7 722 723 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 724 725 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 726 727 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 728 729 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 730 } PRLO; 731 732 typedef struct _ADISC { /* Structure is in Big Endian format */ 733 uint32_t hardAL_PA; 734 struct lpfc_name portName; 735 struct lpfc_name nodeName; 736 uint32_t DID; 737 } ADISC; 738 739 typedef struct _FARP { /* Structure is in Big Endian format */ 740 uint32_t Mflags:8; 741 uint32_t Odid:24; 742 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 743 action */ 744 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 745 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 746 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 747 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 748 supported */ 749 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 750 supported */ 751 uint32_t Rflags:8; 752 uint32_t Rdid:24; 753 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 754 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 755 struct lpfc_name OportName; 756 struct lpfc_name OnodeName; 757 struct lpfc_name RportName; 758 struct lpfc_name RnodeName; 759 uint8_t Oipaddr[16]; 760 uint8_t Ripaddr[16]; 761 } FARP; 762 763 typedef struct _FAN { /* Structure is in Big Endian format */ 764 uint32_t Fdid; 765 struct lpfc_name FportName; 766 struct lpfc_name FnodeName; 767 } FAN; 768 769 typedef struct _SCR { /* Structure is in Big Endian format */ 770 uint8_t resvd1; 771 uint8_t resvd2; 772 uint8_t resvd3; 773 uint8_t Function; 774 #define SCR_FUNC_FABRIC 0x01 775 #define SCR_FUNC_NPORT 0x02 776 #define SCR_FUNC_FULL 0x03 777 #define SCR_CLEAR 0xff 778 } SCR; 779 780 typedef struct _RNID_TOP_DISC { 781 struct lpfc_name portName; 782 uint8_t resvd[8]; 783 uint32_t unitType; 784 #define RNID_HBA 0x7 785 #define RNID_HOST 0xa 786 #define RNID_DRIVER 0xd 787 uint32_t physPort; 788 uint32_t attachedNodes; 789 uint16_t ipVersion; 790 #define RNID_IPV4 0x1 791 #define RNID_IPV6 0x2 792 uint16_t UDPport; 793 uint8_t ipAddr[16]; 794 uint16_t resvd1; 795 uint16_t flags; 796 #define RNID_TD_SUPPORT 0x1 797 #define RNID_LP_VALID 0x2 798 } RNID_TOP_DISC; 799 800 typedef struct _RNID { /* Structure is in Big Endian format */ 801 uint8_t Format; 802 #define RNID_TOPOLOGY_DISC 0xdf 803 uint8_t CommonLen; 804 uint8_t resvd1; 805 uint8_t SpecificLen; 806 struct lpfc_name portName; 807 struct lpfc_name nodeName; 808 union { 809 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 810 } un; 811 } RNID; 812 813 typedef struct _RPS { /* Structure is in Big Endian format */ 814 union { 815 uint32_t portNum; 816 struct lpfc_name portName; 817 } un; 818 } RPS; 819 820 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 821 uint16_t rsvd1; 822 uint16_t portStatus; 823 uint32_t linkFailureCnt; 824 uint32_t lossSyncCnt; 825 uint32_t lossSignalCnt; 826 uint32_t primSeqErrCnt; 827 uint32_t invalidXmitWord; 828 uint32_t crcCnt; 829 } RPS_RSP; 830 831 typedef struct _RPL { /* Structure is in Big Endian format */ 832 uint32_t maxsize; 833 uint32_t index; 834 } RPL; 835 836 typedef struct _PORT_NUM_BLK { 837 uint32_t portNum; 838 uint32_t portID; 839 struct lpfc_name portName; 840 } PORT_NUM_BLK; 841 842 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 843 uint32_t listLen; 844 uint32_t index; 845 PORT_NUM_BLK port_num_blk; 846 } RPL_RSP; 847 848 /* This is used for RSCN command */ 849 typedef struct _D_ID { /* Structure is in Big Endian format */ 850 union { 851 uint32_t word; 852 struct { 853 #ifdef __BIG_ENDIAN_BITFIELD 854 uint8_t resv; 855 uint8_t domain; 856 uint8_t area; 857 uint8_t id; 858 #else /* __LITTLE_ENDIAN_BITFIELD */ 859 uint8_t id; 860 uint8_t area; 861 uint8_t domain; 862 uint8_t resv; 863 #endif 864 } b; 865 } un; 866 } D_ID; 867 868 /* 869 * Structure to define all ELS Payload types 870 */ 871 872 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 873 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 874 uint8_t elsByte1; 875 uint8_t elsByte2; 876 uint8_t elsByte3; 877 union { 878 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 879 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 880 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 881 PRLI prli; /* Payload for PRLI/ACC */ 882 PRLO prlo; /* Payload for PRLO/ACC */ 883 ADISC adisc; /* Payload for ADISC/ACC */ 884 FARP farp; /* Payload for FARP/ACC */ 885 FAN fan; /* Payload for FAN */ 886 SCR scr; /* Payload for SCR/ACC */ 887 RNID rnid; /* Payload for RNID */ 888 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 889 } un; 890 } ELS_PKT; 891 892 /* 893 * FDMI 894 * HBA MAnagement Operations Command Codes 895 */ 896 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 897 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 898 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 899 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 900 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 901 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */ 902 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 903 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 904 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 905 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 906 907 /* 908 * Management Service Subtypes 909 */ 910 #define SLI_CT_FDMI_Subtypes 0x10 911 912 /* 913 * HBA Management Service Reject Code 914 */ 915 #define REJECT_CODE 0x9 /* Unable to perform command request */ 916 917 /* 918 * HBA Management Service Reject Reason Code 919 * Please refer to the Reason Codes above 920 */ 921 922 /* 923 * HBA Attribute Types 924 */ 925 #define NODE_NAME 0x1 926 #define MANUFACTURER 0x2 927 #define SERIAL_NUMBER 0x3 928 #define MODEL 0x4 929 #define MODEL_DESCRIPTION 0x5 930 #define HARDWARE_VERSION 0x6 931 #define DRIVER_VERSION 0x7 932 #define OPTION_ROM_VERSION 0x8 933 #define FIRMWARE_VERSION 0x9 934 #define OS_NAME_VERSION 0xa 935 #define MAX_CT_PAYLOAD_LEN 0xb 936 937 /* 938 * Port Attrubute Types 939 */ 940 #define SUPPORTED_FC4_TYPES 0x1 941 #define SUPPORTED_SPEED 0x2 942 #define PORT_SPEED 0x3 943 #define MAX_FRAME_SIZE 0x4 944 #define OS_DEVICE_NAME 0x5 945 #define HOST_NAME 0x6 946 947 union AttributesDef { 948 /* Structure is in Big Endian format */ 949 struct { 950 uint32_t AttrType:16; 951 uint32_t AttrLen:16; 952 } bits; 953 uint32_t word; 954 }; 955 956 957 /* 958 * HBA Attribute Entry (8 - 260 bytes) 959 */ 960 typedef struct { 961 union AttributesDef ad; 962 union { 963 uint32_t VendorSpecific; 964 uint8_t Manufacturer[64]; 965 uint8_t SerialNumber[64]; 966 uint8_t Model[256]; 967 uint8_t ModelDescription[256]; 968 uint8_t HardwareVersion[256]; 969 uint8_t DriverVersion[256]; 970 uint8_t OptionROMVersion[256]; 971 uint8_t FirmwareVersion[256]; 972 struct lpfc_name NodeName; 973 uint8_t SupportFC4Types[32]; 974 uint32_t SupportSpeed; 975 uint32_t PortSpeed; 976 uint32_t MaxFrameSize; 977 uint8_t OsDeviceName[256]; 978 uint8_t OsNameVersion[256]; 979 uint32_t MaxCTPayloadLen; 980 uint8_t HostName[256]; 981 } un; 982 } ATTRIBUTE_ENTRY; 983 984 /* 985 * HBA Attribute Block 986 */ 987 typedef struct { 988 uint32_t EntryCnt; /* Number of HBA attribute entries */ 989 ATTRIBUTE_ENTRY Entry; /* Variable-length array */ 990 } ATTRIBUTE_BLOCK; 991 992 /* 993 * Port Entry 994 */ 995 typedef struct { 996 struct lpfc_name PortName; 997 } PORT_ENTRY; 998 999 /* 1000 * HBA Identifier 1001 */ 1002 typedef struct { 1003 struct lpfc_name PortName; 1004 } HBA_IDENTIFIER; 1005 1006 /* 1007 * Registered Port List Format 1008 */ 1009 typedef struct { 1010 uint32_t EntryCnt; 1011 PORT_ENTRY pe; /* Variable-length array */ 1012 } REG_PORT_LIST; 1013 1014 /* 1015 * Register HBA(RHBA) 1016 */ 1017 typedef struct { 1018 HBA_IDENTIFIER hi; 1019 REG_PORT_LIST rpl; /* variable-length array */ 1020 /* ATTRIBUTE_BLOCK ab; */ 1021 } REG_HBA; 1022 1023 /* 1024 * Register HBA Attributes (RHAT) 1025 */ 1026 typedef struct { 1027 struct lpfc_name HBA_PortName; 1028 ATTRIBUTE_BLOCK ab; 1029 } REG_HBA_ATTRIBUTE; 1030 1031 /* 1032 * Register Port Attributes (RPA) 1033 */ 1034 typedef struct { 1035 struct lpfc_name PortName; 1036 ATTRIBUTE_BLOCK ab; 1037 } REG_PORT_ATTRIBUTE; 1038 1039 /* 1040 * Get Registered HBA List (GRHL) Accept Payload Format 1041 */ 1042 typedef struct { 1043 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */ 1044 struct lpfc_name HBA_PortName; /* Variable-length array */ 1045 } GRHL_ACC_PAYLOAD; 1046 1047 /* 1048 * Get Registered Port List (GRPL) Accept Payload Format 1049 */ 1050 typedef struct { 1051 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */ 1052 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */ 1053 } GRPL_ACC_PAYLOAD; 1054 1055 /* 1056 * Get Port Attributes (GPAT) Accept Payload Format 1057 */ 1058 1059 typedef struct { 1060 ATTRIBUTE_BLOCK pab; 1061 } GPAT_ACC_PAYLOAD; 1062 1063 1064 /* 1065 * Begin HBA configuration parameters. 1066 * The PCI configuration register BAR assignments are: 1067 * BAR0, offset 0x10 - SLIM base memory address 1068 * BAR1, offset 0x14 - SLIM base memory high address 1069 * BAR2, offset 0x18 - REGISTER base memory address 1070 * BAR3, offset 0x1c - REGISTER base memory high address 1071 * BAR4, offset 0x20 - BIU I/O registers 1072 * BAR5, offset 0x24 - REGISTER base io high address 1073 */ 1074 1075 /* Number of rings currently used and available. */ 1076 #define MAX_CONFIGURED_RINGS 3 1077 #define MAX_RINGS 4 1078 1079 /* IOCB / Mailbox is owned by FireFly */ 1080 #define OWN_CHIP 1 1081 1082 /* IOCB / Mailbox is owned by Host */ 1083 #define OWN_HOST 0 1084 1085 /* Number of 4-byte words in an IOCB. */ 1086 #define IOCB_WORD_SZ 8 1087 1088 /* defines for type field in fc header */ 1089 #define FC_ELS_DATA 0x1 1090 #define FC_LLC_SNAP 0x5 1091 #define FC_FCP_DATA 0x8 1092 #define FC_COMMON_TRANSPORT_ULP 0x20 1093 1094 /* defines for rctl field in fc header */ 1095 #define FC_DEV_DATA 0x0 1096 #define FC_UNSOL_CTL 0x2 1097 #define FC_SOL_CTL 0x3 1098 #define FC_UNSOL_DATA 0x4 1099 #define FC_FCP_CMND 0x6 1100 #define FC_ELS_REQ 0x22 1101 #define FC_ELS_RSP 0x23 1102 1103 /* network headers for Dfctl field */ 1104 #define FC_NET_HDR 0x20 1105 1106 /* Start FireFly Register definitions */ 1107 #define PCI_VENDOR_ID_EMULEX 0x10df 1108 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1109 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1110 #define PCI_DEVICE_ID_SAT_MID 0xf015 1111 #define PCI_DEVICE_ID_RFLY 0xf095 1112 #define PCI_DEVICE_ID_PFLY 0xf098 1113 #define PCI_DEVICE_ID_LP101 0xf0a1 1114 #define PCI_DEVICE_ID_TFLY 0xf0a5 1115 #define PCI_DEVICE_ID_BSMB 0xf0d1 1116 #define PCI_DEVICE_ID_BMID 0xf0d5 1117 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1118 #define PCI_DEVICE_ID_ZMID 0xf0e5 1119 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1120 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1121 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1122 #define PCI_DEVICE_ID_SAT 0xf100 1123 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1124 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1125 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1126 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1127 #define PCI_DEVICE_ID_CENTAUR 0xf900 1128 #define PCI_DEVICE_ID_PEGASUS 0xf980 1129 #define PCI_DEVICE_ID_THOR 0xfa00 1130 #define PCI_DEVICE_ID_VIPER 0xfb00 1131 #define PCI_DEVICE_ID_LP10000S 0xfc00 1132 #define PCI_DEVICE_ID_LP11000S 0xfc10 1133 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1134 #define PCI_DEVICE_ID_SAT_S 0xfc40 1135 #define PCI_DEVICE_ID_HELIOS 0xfd00 1136 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1137 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1138 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1139 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1140 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1141 1142 #define JEDEC_ID_ADDRESS 0x0080001c 1143 #define FIREFLY_JEDEC_ID 0x1ACC 1144 #define SUPERFLY_JEDEC_ID 0x0020 1145 #define DRAGONFLY_JEDEC_ID 0x0021 1146 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1147 #define CENTAUR_2G_JEDEC_ID 0x0026 1148 #define CENTAUR_1G_JEDEC_ID 0x0028 1149 #define PEGASUS_ORION_JEDEC_ID 0x0036 1150 #define PEGASUS_JEDEC_ID 0x0038 1151 #define THOR_JEDEC_ID 0x0012 1152 #define HELIOS_JEDEC_ID 0x0364 1153 #define ZEPHYR_JEDEC_ID 0x0577 1154 #define VIPER_JEDEC_ID 0x4838 1155 #define SATURN_JEDEC_ID 0x1004 1156 1157 #define JEDEC_ID_MASK 0x0FFFF000 1158 #define JEDEC_ID_SHIFT 12 1159 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1160 1161 typedef struct { /* FireFly BIU registers */ 1162 uint32_t hostAtt; /* See definitions for Host Attention 1163 register */ 1164 uint32_t chipAtt; /* See definitions for Chip Attention 1165 register */ 1166 uint32_t hostStatus; /* See definitions for Host Status register */ 1167 uint32_t hostControl; /* See definitions for Host Control register */ 1168 uint32_t buiConfig; /* See definitions for BIU configuration 1169 register */ 1170 } FF_REGS; 1171 1172 /* IO Register size in bytes */ 1173 #define FF_REG_AREA_SIZE 256 1174 1175 /* Host Attention Register */ 1176 1177 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1178 1179 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1180 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1181 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1182 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1183 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1184 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1185 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1186 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1187 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1188 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1189 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1190 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1191 #define HA_LATT 0x20000000 /* Bit 29 */ 1192 #define HA_MBATT 0x40000000 /* Bit 30 */ 1193 #define HA_ERATT 0x80000000 /* Bit 31 */ 1194 1195 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1196 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1197 #define HA_RXATT 0x00000008 /* Bit 3 */ 1198 #define HA_RXMASK 0x0000000f 1199 1200 /* Chip Attention Register */ 1201 1202 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1203 1204 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1205 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1206 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1207 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1208 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1209 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1210 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1211 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1212 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1213 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1214 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1215 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1216 #define CA_MBATT 0x40000000 /* Bit 30 */ 1217 1218 /* Host Status Register */ 1219 1220 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1221 1222 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1223 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1224 #define HS_FFER8 0x01000000 /* Bit 24 */ 1225 #define HS_FFER7 0x02000000 /* Bit 25 */ 1226 #define HS_FFER6 0x04000000 /* Bit 26 */ 1227 #define HS_FFER5 0x08000000 /* Bit 27 */ 1228 #define HS_FFER4 0x10000000 /* Bit 28 */ 1229 #define HS_FFER3 0x20000000 /* Bit 29 */ 1230 #define HS_FFER2 0x40000000 /* Bit 30 */ 1231 #define HS_FFER1 0x80000000 /* Bit 31 */ 1232 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1233 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1234 1235 /* Host Control Register */ 1236 1237 #define HC_REG_OFFSET 12 /* Word offset from register base address */ 1238 1239 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1240 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1241 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1242 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1243 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1244 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1245 #define HC_INITMB 0x04000000 /* Bit 26 */ 1246 #define HC_INITFF 0x08000000 /* Bit 27 */ 1247 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1248 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1249 1250 /* Mailbox Commands */ 1251 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1252 #define MBX_LOAD_SM 0x01 1253 #define MBX_READ_NV 0x02 1254 #define MBX_WRITE_NV 0x03 1255 #define MBX_RUN_BIU_DIAG 0x04 1256 #define MBX_INIT_LINK 0x05 1257 #define MBX_DOWN_LINK 0x06 1258 #define MBX_CONFIG_LINK 0x07 1259 #define MBX_CONFIG_RING 0x09 1260 #define MBX_RESET_RING 0x0A 1261 #define MBX_READ_CONFIG 0x0B 1262 #define MBX_READ_RCONFIG 0x0C 1263 #define MBX_READ_SPARM 0x0D 1264 #define MBX_READ_STATUS 0x0E 1265 #define MBX_READ_RPI 0x0F 1266 #define MBX_READ_XRI 0x10 1267 #define MBX_READ_REV 0x11 1268 #define MBX_READ_LNK_STAT 0x12 1269 #define MBX_REG_LOGIN 0x13 1270 #define MBX_UNREG_LOGIN 0x14 1271 #define MBX_READ_LA 0x15 1272 #define MBX_CLEAR_LA 0x16 1273 #define MBX_DUMP_MEMORY 0x17 1274 #define MBX_DUMP_CONTEXT 0x18 1275 #define MBX_RUN_DIAGS 0x19 1276 #define MBX_RESTART 0x1A 1277 #define MBX_UPDATE_CFG 0x1B 1278 #define MBX_DOWN_LOAD 0x1C 1279 #define MBX_DEL_LD_ENTRY 0x1D 1280 #define MBX_RUN_PROGRAM 0x1E 1281 #define MBX_SET_MASK 0x20 1282 #define MBX_SET_VARIABLE 0x21 1283 #define MBX_UNREG_D_ID 0x23 1284 #define MBX_KILL_BOARD 0x24 1285 #define MBX_CONFIG_FARP 0x25 1286 #define MBX_BEACON 0x2A 1287 #define MBX_HEARTBEAT 0x31 1288 #define MBX_WRITE_VPARMS 0x32 1289 #define MBX_ASYNCEVT_ENABLE 0x33 1290 1291 #define MBX_CONFIG_HBQ 0x7C 1292 #define MBX_LOAD_AREA 0x81 1293 #define MBX_RUN_BIU_DIAG64 0x84 1294 #define MBX_CONFIG_PORT 0x88 1295 #define MBX_READ_SPARM64 0x8D 1296 #define MBX_READ_RPI64 0x8F 1297 #define MBX_REG_LOGIN64 0x93 1298 #define MBX_READ_LA64 0x95 1299 #define MBX_REG_VPI 0x96 1300 #define MBX_UNREG_VPI 0x97 1301 #define MBX_REG_VNPID 0x96 1302 #define MBX_UNREG_VNPID 0x97 1303 1304 #define MBX_WRITE_WWN 0x98 1305 #define MBX_SET_DEBUG 0x99 1306 #define MBX_LOAD_EXP_ROM 0x9C 1307 1308 #define MBX_MAX_CMDS 0x9D 1309 #define MBX_SLI2_CMD_MASK 0x80 1310 1311 /* IOCB Commands */ 1312 1313 #define CMD_RCV_SEQUENCE_CX 0x01 1314 #define CMD_XMIT_SEQUENCE_CR 0x02 1315 #define CMD_XMIT_SEQUENCE_CX 0x03 1316 #define CMD_XMIT_BCAST_CN 0x04 1317 #define CMD_XMIT_BCAST_CX 0x05 1318 #define CMD_QUE_RING_BUF_CN 0x06 1319 #define CMD_QUE_XRI_BUF_CX 0x07 1320 #define CMD_IOCB_CONTINUE_CN 0x08 1321 #define CMD_RET_XRI_BUF_CX 0x09 1322 #define CMD_ELS_REQUEST_CR 0x0A 1323 #define CMD_ELS_REQUEST_CX 0x0B 1324 #define CMD_RCV_ELS_REQ_CX 0x0D 1325 #define CMD_ABORT_XRI_CN 0x0E 1326 #define CMD_ABORT_XRI_CX 0x0F 1327 #define CMD_CLOSE_XRI_CN 0x10 1328 #define CMD_CLOSE_XRI_CX 0x11 1329 #define CMD_CREATE_XRI_CR 0x12 1330 #define CMD_CREATE_XRI_CX 0x13 1331 #define CMD_GET_RPI_CN 0x14 1332 #define CMD_XMIT_ELS_RSP_CX 0x15 1333 #define CMD_GET_RPI_CR 0x16 1334 #define CMD_XRI_ABORTED_CX 0x17 1335 #define CMD_FCP_IWRITE_CR 0x18 1336 #define CMD_FCP_IWRITE_CX 0x19 1337 #define CMD_FCP_IREAD_CR 0x1A 1338 #define CMD_FCP_IREAD_CX 0x1B 1339 #define CMD_FCP_ICMND_CR 0x1C 1340 #define CMD_FCP_ICMND_CX 0x1D 1341 #define CMD_FCP_TSEND_CX 0x1F 1342 #define CMD_FCP_TRECEIVE_CX 0x21 1343 #define CMD_FCP_TRSP_CX 0x23 1344 #define CMD_FCP_AUTO_TRSP_CX 0x29 1345 1346 #define CMD_ADAPTER_MSG 0x20 1347 #define CMD_ADAPTER_DUMP 0x22 1348 1349 /* SLI_2 IOCB Command Set */ 1350 1351 #define CMD_ASYNC_STATUS 0x7C 1352 #define CMD_RCV_SEQUENCE64_CX 0x81 1353 #define CMD_XMIT_SEQUENCE64_CR 0x82 1354 #define CMD_XMIT_SEQUENCE64_CX 0x83 1355 #define CMD_XMIT_BCAST64_CN 0x84 1356 #define CMD_XMIT_BCAST64_CX 0x85 1357 #define CMD_QUE_RING_BUF64_CN 0x86 1358 #define CMD_QUE_XRI_BUF64_CX 0x87 1359 #define CMD_IOCB_CONTINUE64_CN 0x88 1360 #define CMD_RET_XRI_BUF64_CX 0x89 1361 #define CMD_ELS_REQUEST64_CR 0x8A 1362 #define CMD_ELS_REQUEST64_CX 0x8B 1363 #define CMD_ABORT_MXRI64_CN 0x8C 1364 #define CMD_RCV_ELS_REQ64_CX 0x8D 1365 #define CMD_XMIT_ELS_RSP64_CX 0x95 1366 #define CMD_FCP_IWRITE64_CR 0x98 1367 #define CMD_FCP_IWRITE64_CX 0x99 1368 #define CMD_FCP_IREAD64_CR 0x9A 1369 #define CMD_FCP_IREAD64_CX 0x9B 1370 #define CMD_FCP_ICMND64_CR 0x9C 1371 #define CMD_FCP_ICMND64_CX 0x9D 1372 #define CMD_FCP_TSEND64_CX 0x9F 1373 #define CMD_FCP_TRECEIVE64_CX 0xA1 1374 #define CMD_FCP_TRSP64_CX 0xA3 1375 1376 #define CMD_QUE_XRI64_CX 0xB3 1377 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1378 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1379 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1380 1381 #define CMD_GEN_REQUEST64_CR 0xC2 1382 #define CMD_GEN_REQUEST64_CX 0xC3 1383 1384 #define CMD_MAX_IOCB_CMD 0xE6 1385 #define CMD_IOCB_MASK 0xff 1386 1387 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1388 iocb */ 1389 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1390 /* 1391 * Define Status 1392 */ 1393 #define MBX_SUCCESS 0 1394 #define MBXERR_NUM_RINGS 1 1395 #define MBXERR_NUM_IOCBS 2 1396 #define MBXERR_IOCBS_EXCEEDED 3 1397 #define MBXERR_BAD_RING_NUMBER 4 1398 #define MBXERR_MASK_ENTRIES_RANGE 5 1399 #define MBXERR_MASKS_EXCEEDED 6 1400 #define MBXERR_BAD_PROFILE 7 1401 #define MBXERR_BAD_DEF_CLASS 8 1402 #define MBXERR_BAD_MAX_RESPONDER 9 1403 #define MBXERR_BAD_MAX_ORIGINATOR 10 1404 #define MBXERR_RPI_REGISTERED 11 1405 #define MBXERR_RPI_FULL 12 1406 #define MBXERR_NO_RESOURCES 13 1407 #define MBXERR_BAD_RCV_LENGTH 14 1408 #define MBXERR_DMA_ERROR 15 1409 #define MBXERR_ERROR 16 1410 #define MBX_NOT_FINISHED 255 1411 1412 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1413 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1414 1415 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1416 1417 /* 1418 * Begin Structure Definitions for Mailbox Commands 1419 */ 1420 1421 typedef struct { 1422 #ifdef __BIG_ENDIAN_BITFIELD 1423 uint8_t tval; 1424 uint8_t tmask; 1425 uint8_t rval; 1426 uint8_t rmask; 1427 #else /* __LITTLE_ENDIAN_BITFIELD */ 1428 uint8_t rmask; 1429 uint8_t rval; 1430 uint8_t tmask; 1431 uint8_t tval; 1432 #endif 1433 } RR_REG; 1434 1435 struct ulp_bde { 1436 uint32_t bdeAddress; 1437 #ifdef __BIG_ENDIAN_BITFIELD 1438 uint32_t bdeReserved:4; 1439 uint32_t bdeAddrHigh:4; 1440 uint32_t bdeSize:24; 1441 #else /* __LITTLE_ENDIAN_BITFIELD */ 1442 uint32_t bdeSize:24; 1443 uint32_t bdeAddrHigh:4; 1444 uint32_t bdeReserved:4; 1445 #endif 1446 }; 1447 1448 struct ulp_bde64 { /* SLI-2 */ 1449 union ULP_BDE_TUS { 1450 uint32_t w; 1451 struct { 1452 #ifdef __BIG_ENDIAN_BITFIELD 1453 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1454 VALUE !! */ 1455 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1456 #else /* __LITTLE_ENDIAN_BITFIELD */ 1457 uint32_t bdeSize:24; /* Size of buffer (in bytes) */ 1458 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED 1459 VALUE !! */ 1460 #endif 1461 1462 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 1463 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 1464 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 1465 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit 1466 buffer */ 1467 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit 1468 addr */ 1469 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 1470 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 1471 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 1472 } f; 1473 } tus; 1474 uint32_t addrLow; 1475 uint32_t addrHigh; 1476 }; 1477 #define BDE64_SIZE_WORD 0 1478 #define BPL64_SIZE_WORD 0x40 1479 1480 typedef struct ULP_BDL { /* SLI-2 */ 1481 #ifdef __BIG_ENDIAN_BITFIELD 1482 uint32_t bdeFlags:8; /* BDL Flags */ 1483 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1484 #else /* __LITTLE_ENDIAN_BITFIELD */ 1485 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1486 uint32_t bdeFlags:8; /* BDL Flags */ 1487 #endif 1488 1489 uint32_t addrLow; /* Address 0:31 */ 1490 uint32_t addrHigh; /* Address 32:63 */ 1491 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1492 } ULP_BDL; 1493 1494 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1495 1496 typedef struct { 1497 #ifdef __BIG_ENDIAN_BITFIELD 1498 uint32_t rsvd2:25; 1499 uint32_t acknowledgment:1; 1500 uint32_t version:1; 1501 uint32_t erase_or_prog:1; 1502 uint32_t update_flash:1; 1503 uint32_t update_ram:1; 1504 uint32_t method:1; 1505 uint32_t load_cmplt:1; 1506 #else /* __LITTLE_ENDIAN_BITFIELD */ 1507 uint32_t load_cmplt:1; 1508 uint32_t method:1; 1509 uint32_t update_ram:1; 1510 uint32_t update_flash:1; 1511 uint32_t erase_or_prog:1; 1512 uint32_t version:1; 1513 uint32_t acknowledgment:1; 1514 uint32_t rsvd2:25; 1515 #endif 1516 1517 uint32_t dl_to_adr_low; 1518 uint32_t dl_to_adr_high; 1519 uint32_t dl_len; 1520 union { 1521 uint32_t dl_from_mbx_offset; 1522 struct ulp_bde dl_from_bde; 1523 struct ulp_bde64 dl_from_bde64; 1524 } un; 1525 1526 } LOAD_SM_VAR; 1527 1528 /* Structure for MB Command READ_NVPARM (02) */ 1529 1530 typedef struct { 1531 uint32_t rsvd1[3]; /* Read as all one's */ 1532 uint32_t rsvd2; /* Read as all zero's */ 1533 uint32_t portname[2]; /* N_PORT name */ 1534 uint32_t nodename[2]; /* NODE name */ 1535 1536 #ifdef __BIG_ENDIAN_BITFIELD 1537 uint32_t pref_DID:24; 1538 uint32_t hardAL_PA:8; 1539 #else /* __LITTLE_ENDIAN_BITFIELD */ 1540 uint32_t hardAL_PA:8; 1541 uint32_t pref_DID:24; 1542 #endif 1543 1544 uint32_t rsvd3[21]; /* Read as all one's */ 1545 } READ_NV_VAR; 1546 1547 /* Structure for MB Command WRITE_NVPARMS (03) */ 1548 1549 typedef struct { 1550 uint32_t rsvd1[3]; /* Must be all one's */ 1551 uint32_t rsvd2; /* Must be all zero's */ 1552 uint32_t portname[2]; /* N_PORT name */ 1553 uint32_t nodename[2]; /* NODE name */ 1554 1555 #ifdef __BIG_ENDIAN_BITFIELD 1556 uint32_t pref_DID:24; 1557 uint32_t hardAL_PA:8; 1558 #else /* __LITTLE_ENDIAN_BITFIELD */ 1559 uint32_t hardAL_PA:8; 1560 uint32_t pref_DID:24; 1561 #endif 1562 1563 uint32_t rsvd3[21]; /* Must be all one's */ 1564 } WRITE_NV_VAR; 1565 1566 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1567 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1568 1569 typedef struct { 1570 uint32_t rsvd1; 1571 union { 1572 struct { 1573 struct ulp_bde xmit_bde; 1574 struct ulp_bde rcv_bde; 1575 } s1; 1576 struct { 1577 struct ulp_bde64 xmit_bde64; 1578 struct ulp_bde64 rcv_bde64; 1579 } s2; 1580 } un; 1581 } BIU_DIAG_VAR; 1582 1583 /* Structure for MB Command INIT_LINK (05) */ 1584 1585 typedef struct { 1586 #ifdef __BIG_ENDIAN_BITFIELD 1587 uint32_t rsvd1:24; 1588 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1589 #else /* __LITTLE_ENDIAN_BITFIELD */ 1590 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1591 uint32_t rsvd1:24; 1592 #endif 1593 1594 #ifdef __BIG_ENDIAN_BITFIELD 1595 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1596 uint8_t rsvd2; 1597 uint16_t link_flags; 1598 #else /* __LITTLE_ENDIAN_BITFIELD */ 1599 uint16_t link_flags; 1600 uint8_t rsvd2; 1601 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1602 #endif 1603 1604 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1605 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1606 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1607 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1608 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1609 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1610 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1611 1612 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1613 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1614 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1615 1616 uint32_t link_speed; 1617 #define LINK_SPEED_AUTO 0 /* Auto selection */ 1618 #define LINK_SPEED_1G 1 /* 1 Gigabaud */ 1619 #define LINK_SPEED_2G 2 /* 2 Gigabaud */ 1620 #define LINK_SPEED_4G 4 /* 4 Gigabaud */ 1621 #define LINK_SPEED_8G 8 /* 8 Gigabaud */ 1622 #define LINK_SPEED_10G 16 /* 10 Gigabaud */ 1623 1624 } INIT_LINK_VAR; 1625 1626 /* Structure for MB Command DOWN_LINK (06) */ 1627 1628 typedef struct { 1629 uint32_t rsvd1; 1630 } DOWN_LINK_VAR; 1631 1632 /* Structure for MB Command CONFIG_LINK (07) */ 1633 1634 typedef struct { 1635 #ifdef __BIG_ENDIAN_BITFIELD 1636 uint32_t cr:1; 1637 uint32_t ci:1; 1638 uint32_t cr_delay:6; 1639 uint32_t cr_count:8; 1640 uint32_t rsvd1:8; 1641 uint32_t MaxBBC:8; 1642 #else /* __LITTLE_ENDIAN_BITFIELD */ 1643 uint32_t MaxBBC:8; 1644 uint32_t rsvd1:8; 1645 uint32_t cr_count:8; 1646 uint32_t cr_delay:6; 1647 uint32_t ci:1; 1648 uint32_t cr:1; 1649 #endif 1650 1651 uint32_t myId; 1652 uint32_t rsvd2; 1653 uint32_t edtov; 1654 uint32_t arbtov; 1655 uint32_t ratov; 1656 uint32_t rttov; 1657 uint32_t altov; 1658 uint32_t crtov; 1659 uint32_t citov; 1660 #ifdef __BIG_ENDIAN_BITFIELD 1661 uint32_t rrq_enable:1; 1662 uint32_t rrq_immed:1; 1663 uint32_t rsvd4:29; 1664 uint32_t ack0_enable:1; 1665 #else /* __LITTLE_ENDIAN_BITFIELD */ 1666 uint32_t ack0_enable:1; 1667 uint32_t rsvd4:29; 1668 uint32_t rrq_immed:1; 1669 uint32_t rrq_enable:1; 1670 #endif 1671 } CONFIG_LINK; 1672 1673 /* Structure for MB Command PART_SLIM (08) 1674 * will be removed since SLI1 is no longer supported! 1675 */ 1676 typedef struct { 1677 #ifdef __BIG_ENDIAN_BITFIELD 1678 uint16_t offCiocb; 1679 uint16_t numCiocb; 1680 uint16_t offRiocb; 1681 uint16_t numRiocb; 1682 #else /* __LITTLE_ENDIAN_BITFIELD */ 1683 uint16_t numCiocb; 1684 uint16_t offCiocb; 1685 uint16_t numRiocb; 1686 uint16_t offRiocb; 1687 #endif 1688 } RING_DEF; 1689 1690 typedef struct { 1691 #ifdef __BIG_ENDIAN_BITFIELD 1692 uint32_t unused1:24; 1693 uint32_t numRing:8; 1694 #else /* __LITTLE_ENDIAN_BITFIELD */ 1695 uint32_t numRing:8; 1696 uint32_t unused1:24; 1697 #endif 1698 1699 RING_DEF ringdef[4]; 1700 uint32_t hbainit; 1701 } PART_SLIM_VAR; 1702 1703 /* Structure for MB Command CONFIG_RING (09) */ 1704 1705 typedef struct { 1706 #ifdef __BIG_ENDIAN_BITFIELD 1707 uint32_t unused2:6; 1708 uint32_t recvSeq:1; 1709 uint32_t recvNotify:1; 1710 uint32_t numMask:8; 1711 uint32_t profile:8; 1712 uint32_t unused1:4; 1713 uint32_t ring:4; 1714 #else /* __LITTLE_ENDIAN_BITFIELD */ 1715 uint32_t ring:4; 1716 uint32_t unused1:4; 1717 uint32_t profile:8; 1718 uint32_t numMask:8; 1719 uint32_t recvNotify:1; 1720 uint32_t recvSeq:1; 1721 uint32_t unused2:6; 1722 #endif 1723 1724 #ifdef __BIG_ENDIAN_BITFIELD 1725 uint16_t maxRespXchg; 1726 uint16_t maxOrigXchg; 1727 #else /* __LITTLE_ENDIAN_BITFIELD */ 1728 uint16_t maxOrigXchg; 1729 uint16_t maxRespXchg; 1730 #endif 1731 1732 RR_REG rrRegs[6]; 1733 } CONFIG_RING_VAR; 1734 1735 /* Structure for MB Command RESET_RING (10) */ 1736 1737 typedef struct { 1738 uint32_t ring_no; 1739 } RESET_RING_VAR; 1740 1741 /* Structure for MB Command READ_CONFIG (11) */ 1742 1743 typedef struct { 1744 #ifdef __BIG_ENDIAN_BITFIELD 1745 uint32_t cr:1; 1746 uint32_t ci:1; 1747 uint32_t cr_delay:6; 1748 uint32_t cr_count:8; 1749 uint32_t InitBBC:8; 1750 uint32_t MaxBBC:8; 1751 #else /* __LITTLE_ENDIAN_BITFIELD */ 1752 uint32_t MaxBBC:8; 1753 uint32_t InitBBC:8; 1754 uint32_t cr_count:8; 1755 uint32_t cr_delay:6; 1756 uint32_t ci:1; 1757 uint32_t cr:1; 1758 #endif 1759 1760 #ifdef __BIG_ENDIAN_BITFIELD 1761 uint32_t topology:8; 1762 uint32_t myDid:24; 1763 #else /* __LITTLE_ENDIAN_BITFIELD */ 1764 uint32_t myDid:24; 1765 uint32_t topology:8; 1766 #endif 1767 1768 /* Defines for topology (defined previously) */ 1769 #ifdef __BIG_ENDIAN_BITFIELD 1770 uint32_t AR:1; 1771 uint32_t IR:1; 1772 uint32_t rsvd1:29; 1773 uint32_t ack0:1; 1774 #else /* __LITTLE_ENDIAN_BITFIELD */ 1775 uint32_t ack0:1; 1776 uint32_t rsvd1:29; 1777 uint32_t IR:1; 1778 uint32_t AR:1; 1779 #endif 1780 1781 uint32_t edtov; 1782 uint32_t arbtov; 1783 uint32_t ratov; 1784 uint32_t rttov; 1785 uint32_t altov; 1786 uint32_t lmt; 1787 #define LMT_RESERVED 0x000 /* Not used */ 1788 #define LMT_1Gb 0x004 1789 #define LMT_2Gb 0x008 1790 #define LMT_4Gb 0x040 1791 #define LMT_8Gb 0x080 1792 #define LMT_10Gb 0x100 1793 uint32_t rsvd2; 1794 uint32_t rsvd3; 1795 uint32_t max_xri; 1796 uint32_t max_iocb; 1797 uint32_t max_rpi; 1798 uint32_t avail_xri; 1799 uint32_t avail_iocb; 1800 uint32_t avail_rpi; 1801 uint32_t max_vpi; 1802 uint32_t rsvd4; 1803 uint32_t rsvd5; 1804 uint32_t avail_vpi; 1805 } READ_CONFIG_VAR; 1806 1807 /* Structure for MB Command READ_RCONFIG (12) */ 1808 1809 typedef struct { 1810 #ifdef __BIG_ENDIAN_BITFIELD 1811 uint32_t rsvd2:7; 1812 uint32_t recvNotify:1; 1813 uint32_t numMask:8; 1814 uint32_t profile:8; 1815 uint32_t rsvd1:4; 1816 uint32_t ring:4; 1817 #else /* __LITTLE_ENDIAN_BITFIELD */ 1818 uint32_t ring:4; 1819 uint32_t rsvd1:4; 1820 uint32_t profile:8; 1821 uint32_t numMask:8; 1822 uint32_t recvNotify:1; 1823 uint32_t rsvd2:7; 1824 #endif 1825 1826 #ifdef __BIG_ENDIAN_BITFIELD 1827 uint16_t maxResp; 1828 uint16_t maxOrig; 1829 #else /* __LITTLE_ENDIAN_BITFIELD */ 1830 uint16_t maxOrig; 1831 uint16_t maxResp; 1832 #endif 1833 1834 RR_REG rrRegs[6]; 1835 1836 #ifdef __BIG_ENDIAN_BITFIELD 1837 uint16_t cmdRingOffset; 1838 uint16_t cmdEntryCnt; 1839 uint16_t rspRingOffset; 1840 uint16_t rspEntryCnt; 1841 uint16_t nextCmdOffset; 1842 uint16_t rsvd3; 1843 uint16_t nextRspOffset; 1844 uint16_t rsvd4; 1845 #else /* __LITTLE_ENDIAN_BITFIELD */ 1846 uint16_t cmdEntryCnt; 1847 uint16_t cmdRingOffset; 1848 uint16_t rspEntryCnt; 1849 uint16_t rspRingOffset; 1850 uint16_t rsvd3; 1851 uint16_t nextCmdOffset; 1852 uint16_t rsvd4; 1853 uint16_t nextRspOffset; 1854 #endif 1855 } READ_RCONF_VAR; 1856 1857 /* Structure for MB Command READ_SPARM (13) */ 1858 /* Structure for MB Command READ_SPARM64 (0x8D) */ 1859 1860 typedef struct { 1861 uint32_t rsvd1; 1862 uint32_t rsvd2; 1863 union { 1864 struct ulp_bde sp; /* This BDE points to struct serv_parm 1865 structure */ 1866 struct ulp_bde64 sp64; 1867 } un; 1868 #ifdef __BIG_ENDIAN_BITFIELD 1869 uint16_t rsvd3; 1870 uint16_t vpi; 1871 #else /* __LITTLE_ENDIAN_BITFIELD */ 1872 uint16_t vpi; 1873 uint16_t rsvd3; 1874 #endif 1875 } READ_SPARM_VAR; 1876 1877 /* Structure for MB Command READ_STATUS (14) */ 1878 1879 typedef struct { 1880 #ifdef __BIG_ENDIAN_BITFIELD 1881 uint32_t rsvd1:31; 1882 uint32_t clrCounters:1; 1883 uint16_t activeXriCnt; 1884 uint16_t activeRpiCnt; 1885 #else /* __LITTLE_ENDIAN_BITFIELD */ 1886 uint32_t clrCounters:1; 1887 uint32_t rsvd1:31; 1888 uint16_t activeRpiCnt; 1889 uint16_t activeXriCnt; 1890 #endif 1891 1892 uint32_t xmitByteCnt; 1893 uint32_t rcvByteCnt; 1894 uint32_t xmitFrameCnt; 1895 uint32_t rcvFrameCnt; 1896 uint32_t xmitSeqCnt; 1897 uint32_t rcvSeqCnt; 1898 uint32_t totalOrigExchanges; 1899 uint32_t totalRespExchanges; 1900 uint32_t rcvPbsyCnt; 1901 uint32_t rcvFbsyCnt; 1902 } READ_STATUS_VAR; 1903 1904 /* Structure for MB Command READ_RPI (15) */ 1905 /* Structure for MB Command READ_RPI64 (0x8F) */ 1906 1907 typedef struct { 1908 #ifdef __BIG_ENDIAN_BITFIELD 1909 uint16_t nextRpi; 1910 uint16_t reqRpi; 1911 uint32_t rsvd2:8; 1912 uint32_t DID:24; 1913 #else /* __LITTLE_ENDIAN_BITFIELD */ 1914 uint16_t reqRpi; 1915 uint16_t nextRpi; 1916 uint32_t DID:24; 1917 uint32_t rsvd2:8; 1918 #endif 1919 1920 union { 1921 struct ulp_bde sp; 1922 struct ulp_bde64 sp64; 1923 } un; 1924 1925 } READ_RPI_VAR; 1926 1927 /* Structure for MB Command READ_XRI (16) */ 1928 1929 typedef struct { 1930 #ifdef __BIG_ENDIAN_BITFIELD 1931 uint16_t nextXri; 1932 uint16_t reqXri; 1933 uint16_t rsvd1; 1934 uint16_t rpi; 1935 uint32_t rsvd2:8; 1936 uint32_t DID:24; 1937 uint32_t rsvd3:8; 1938 uint32_t SID:24; 1939 uint32_t rsvd4; 1940 uint8_t seqId; 1941 uint8_t rsvd5; 1942 uint16_t seqCount; 1943 uint16_t oxId; 1944 uint16_t rxId; 1945 uint32_t rsvd6:30; 1946 uint32_t si:1; 1947 uint32_t exchOrig:1; 1948 #else /* __LITTLE_ENDIAN_BITFIELD */ 1949 uint16_t reqXri; 1950 uint16_t nextXri; 1951 uint16_t rpi; 1952 uint16_t rsvd1; 1953 uint32_t DID:24; 1954 uint32_t rsvd2:8; 1955 uint32_t SID:24; 1956 uint32_t rsvd3:8; 1957 uint32_t rsvd4; 1958 uint16_t seqCount; 1959 uint8_t rsvd5; 1960 uint8_t seqId; 1961 uint16_t rxId; 1962 uint16_t oxId; 1963 uint32_t exchOrig:1; 1964 uint32_t si:1; 1965 uint32_t rsvd6:30; 1966 #endif 1967 } READ_XRI_VAR; 1968 1969 /* Structure for MB Command READ_REV (17) */ 1970 1971 typedef struct { 1972 #ifdef __BIG_ENDIAN_BITFIELD 1973 uint32_t cv:1; 1974 uint32_t rr:1; 1975 uint32_t rsvd2:2; 1976 uint32_t v3req:1; 1977 uint32_t v3rsp:1; 1978 uint32_t rsvd1:25; 1979 uint32_t rv:1; 1980 #else /* __LITTLE_ENDIAN_BITFIELD */ 1981 uint32_t rv:1; 1982 uint32_t rsvd1:25; 1983 uint32_t v3rsp:1; 1984 uint32_t v3req:1; 1985 uint32_t rsvd2:2; 1986 uint32_t rr:1; 1987 uint32_t cv:1; 1988 #endif 1989 1990 uint32_t biuRev; 1991 uint32_t smRev; 1992 union { 1993 uint32_t smFwRev; 1994 struct { 1995 #ifdef __BIG_ENDIAN_BITFIELD 1996 uint8_t ProgType; 1997 uint8_t ProgId; 1998 uint16_t ProgVer:4; 1999 uint16_t ProgRev:4; 2000 uint16_t ProgFixLvl:2; 2001 uint16_t ProgDistType:2; 2002 uint16_t DistCnt:4; 2003 #else /* __LITTLE_ENDIAN_BITFIELD */ 2004 uint16_t DistCnt:4; 2005 uint16_t ProgDistType:2; 2006 uint16_t ProgFixLvl:2; 2007 uint16_t ProgRev:4; 2008 uint16_t ProgVer:4; 2009 uint8_t ProgId; 2010 uint8_t ProgType; 2011 #endif 2012 2013 } b; 2014 } un; 2015 uint32_t endecRev; 2016 #ifdef __BIG_ENDIAN_BITFIELD 2017 uint8_t feaLevelHigh; 2018 uint8_t feaLevelLow; 2019 uint8_t fcphHigh; 2020 uint8_t fcphLow; 2021 #else /* __LITTLE_ENDIAN_BITFIELD */ 2022 uint8_t fcphLow; 2023 uint8_t fcphHigh; 2024 uint8_t feaLevelLow; 2025 uint8_t feaLevelHigh; 2026 #endif 2027 2028 uint32_t postKernRev; 2029 uint32_t opFwRev; 2030 uint8_t opFwName[16]; 2031 uint32_t sli1FwRev; 2032 uint8_t sli1FwName[16]; 2033 uint32_t sli2FwRev; 2034 uint8_t sli2FwName[16]; 2035 uint32_t sli3Feat; 2036 uint32_t RandomData[6]; 2037 } READ_REV_VAR; 2038 2039 /* Structure for MB Command READ_LINK_STAT (18) */ 2040 2041 typedef struct { 2042 uint32_t rsvd1; 2043 uint32_t linkFailureCnt; 2044 uint32_t lossSyncCnt; 2045 2046 uint32_t lossSignalCnt; 2047 uint32_t primSeqErrCnt; 2048 uint32_t invalidXmitWord; 2049 uint32_t crcCnt; 2050 uint32_t primSeqTimeout; 2051 uint32_t elasticOverrun; 2052 uint32_t arbTimeout; 2053 } READ_LNK_VAR; 2054 2055 /* Structure for MB Command REG_LOGIN (19) */ 2056 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2057 2058 typedef struct { 2059 #ifdef __BIG_ENDIAN_BITFIELD 2060 uint16_t rsvd1; 2061 uint16_t rpi; 2062 uint32_t rsvd2:8; 2063 uint32_t did:24; 2064 #else /* __LITTLE_ENDIAN_BITFIELD */ 2065 uint16_t rpi; 2066 uint16_t rsvd1; 2067 uint32_t did:24; 2068 uint32_t rsvd2:8; 2069 #endif 2070 2071 union { 2072 struct ulp_bde sp; 2073 struct ulp_bde64 sp64; 2074 } un; 2075 2076 #ifdef __BIG_ENDIAN_BITFIELD 2077 uint16_t rsvd6; 2078 uint16_t vpi; 2079 #else /* __LITTLE_ENDIAN_BITFIELD */ 2080 uint16_t vpi; 2081 uint16_t rsvd6; 2082 #endif 2083 2084 } REG_LOGIN_VAR; 2085 2086 /* Word 30 contents for REG_LOGIN */ 2087 typedef union { 2088 struct { 2089 #ifdef __BIG_ENDIAN_BITFIELD 2090 uint16_t rsvd1:12; 2091 uint16_t wd30_class:4; 2092 uint16_t xri; 2093 #else /* __LITTLE_ENDIAN_BITFIELD */ 2094 uint16_t xri; 2095 uint16_t wd30_class:4; 2096 uint16_t rsvd1:12; 2097 #endif 2098 } f; 2099 uint32_t word; 2100 } REG_WD30; 2101 2102 /* Structure for MB Command UNREG_LOGIN (20) */ 2103 2104 typedef struct { 2105 #ifdef __BIG_ENDIAN_BITFIELD 2106 uint16_t rsvd1; 2107 uint16_t rpi; 2108 uint32_t rsvd2; 2109 uint32_t rsvd3; 2110 uint32_t rsvd4; 2111 uint32_t rsvd5; 2112 uint16_t rsvd6; 2113 uint16_t vpi; 2114 #else /* __LITTLE_ENDIAN_BITFIELD */ 2115 uint16_t rpi; 2116 uint16_t rsvd1; 2117 uint32_t rsvd2; 2118 uint32_t rsvd3; 2119 uint32_t rsvd4; 2120 uint32_t rsvd5; 2121 uint16_t vpi; 2122 uint16_t rsvd6; 2123 #endif 2124 } UNREG_LOGIN_VAR; 2125 2126 /* Structure for MB Command REG_VPI (0x96) */ 2127 typedef struct { 2128 #ifdef __BIG_ENDIAN_BITFIELD 2129 uint32_t rsvd1; 2130 uint32_t rsvd2:8; 2131 uint32_t sid:24; 2132 uint32_t rsvd3; 2133 uint32_t rsvd4; 2134 uint32_t rsvd5; 2135 uint16_t rsvd6; 2136 uint16_t vpi; 2137 #else /* __LITTLE_ENDIAN */ 2138 uint32_t rsvd1; 2139 uint32_t sid:24; 2140 uint32_t rsvd2:8; 2141 uint32_t rsvd3; 2142 uint32_t rsvd4; 2143 uint32_t rsvd5; 2144 uint16_t vpi; 2145 uint16_t rsvd6; 2146 #endif 2147 } REG_VPI_VAR; 2148 2149 /* Structure for MB Command UNREG_VPI (0x97) */ 2150 typedef struct { 2151 uint32_t rsvd1; 2152 uint32_t rsvd2; 2153 uint32_t rsvd3; 2154 uint32_t rsvd4; 2155 uint32_t rsvd5; 2156 #ifdef __BIG_ENDIAN_BITFIELD 2157 uint16_t rsvd6; 2158 uint16_t vpi; 2159 #else /* __LITTLE_ENDIAN */ 2160 uint16_t vpi; 2161 uint16_t rsvd6; 2162 #endif 2163 } UNREG_VPI_VAR; 2164 2165 /* Structure for MB Command UNREG_D_ID (0x23) */ 2166 2167 typedef struct { 2168 uint32_t did; 2169 uint32_t rsvd2; 2170 uint32_t rsvd3; 2171 uint32_t rsvd4; 2172 uint32_t rsvd5; 2173 #ifdef __BIG_ENDIAN_BITFIELD 2174 uint16_t rsvd6; 2175 uint16_t vpi; 2176 #else 2177 uint16_t vpi; 2178 uint16_t rsvd6; 2179 #endif 2180 } UNREG_D_ID_VAR; 2181 2182 /* Structure for MB Command READ_LA (21) */ 2183 /* Structure for MB Command READ_LA64 (0x95) */ 2184 2185 typedef struct { 2186 uint32_t eventTag; /* Event tag */ 2187 #ifdef __BIG_ENDIAN_BITFIELD 2188 uint32_t rsvd1:22; 2189 uint32_t pb:1; 2190 uint32_t il:1; 2191 uint32_t attType:8; 2192 #else /* __LITTLE_ENDIAN_BITFIELD */ 2193 uint32_t attType:8; 2194 uint32_t il:1; 2195 uint32_t pb:1; 2196 uint32_t rsvd1:22; 2197 #endif 2198 2199 #define AT_RESERVED 0x00 /* Reserved - attType */ 2200 #define AT_LINK_UP 0x01 /* Link is up */ 2201 #define AT_LINK_DOWN 0x02 /* Link is down */ 2202 2203 #ifdef __BIG_ENDIAN_BITFIELD 2204 uint8_t granted_AL_PA; 2205 uint8_t lipAlPs; 2206 uint8_t lipType; 2207 uint8_t topology; 2208 #else /* __LITTLE_ENDIAN_BITFIELD */ 2209 uint8_t topology; 2210 uint8_t lipType; 2211 uint8_t lipAlPs; 2212 uint8_t granted_AL_PA; 2213 #endif 2214 2215 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2216 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2217 2218 union { 2219 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer 2220 to */ 2221 /* store the LILP AL_PA position map into */ 2222 struct ulp_bde64 lilpBde64; 2223 } un; 2224 2225 #ifdef __BIG_ENDIAN_BITFIELD 2226 uint32_t Dlu:1; 2227 uint32_t Dtf:1; 2228 uint32_t Drsvd2:14; 2229 uint32_t DlnkSpeed:8; 2230 uint32_t DnlPort:4; 2231 uint32_t Dtx:2; 2232 uint32_t Drx:2; 2233 #else /* __LITTLE_ENDIAN_BITFIELD */ 2234 uint32_t Drx:2; 2235 uint32_t Dtx:2; 2236 uint32_t DnlPort:4; 2237 uint32_t DlnkSpeed:8; 2238 uint32_t Drsvd2:14; 2239 uint32_t Dtf:1; 2240 uint32_t Dlu:1; 2241 #endif 2242 2243 #ifdef __BIG_ENDIAN_BITFIELD 2244 uint32_t Ulu:1; 2245 uint32_t Utf:1; 2246 uint32_t Ursvd2:14; 2247 uint32_t UlnkSpeed:8; 2248 uint32_t UnlPort:4; 2249 uint32_t Utx:2; 2250 uint32_t Urx:2; 2251 #else /* __LITTLE_ENDIAN_BITFIELD */ 2252 uint32_t Urx:2; 2253 uint32_t Utx:2; 2254 uint32_t UnlPort:4; 2255 uint32_t UlnkSpeed:8; 2256 uint32_t Ursvd2:14; 2257 uint32_t Utf:1; 2258 uint32_t Ulu:1; 2259 #endif 2260 2261 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */ 2262 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */ 2263 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */ 2264 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */ 2265 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */ 2266 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */ 2267 2268 } READ_LA_VAR; 2269 2270 /* Structure for MB Command CLEAR_LA (22) */ 2271 2272 typedef struct { 2273 uint32_t eventTag; /* Event tag */ 2274 uint32_t rsvd1; 2275 } CLEAR_LA_VAR; 2276 2277 /* Structure for MB Command DUMP */ 2278 2279 typedef struct { 2280 #ifdef __BIG_ENDIAN_BITFIELD 2281 uint32_t rsvd:25; 2282 uint32_t ra:1; 2283 uint32_t co:1; 2284 uint32_t cv:1; 2285 uint32_t type:4; 2286 uint32_t entry_index:16; 2287 uint32_t region_id:16; 2288 #else /* __LITTLE_ENDIAN_BITFIELD */ 2289 uint32_t type:4; 2290 uint32_t cv:1; 2291 uint32_t co:1; 2292 uint32_t ra:1; 2293 uint32_t rsvd:25; 2294 uint32_t region_id:16; 2295 uint32_t entry_index:16; 2296 #endif 2297 2298 uint32_t rsvd1; 2299 uint32_t word_cnt; 2300 uint32_t resp_offset; 2301 } DUMP_VAR; 2302 2303 #define DMP_MEM_REG 0x1 2304 #define DMP_NV_PARAMS 0x2 2305 2306 #define DMP_REGION_VPD 0xe 2307 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2308 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2309 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2310 2311 struct hbq_mask { 2312 #ifdef __BIG_ENDIAN_BITFIELD 2313 uint8_t tmatch; 2314 uint8_t tmask; 2315 uint8_t rctlmatch; 2316 uint8_t rctlmask; 2317 #else /* __LITTLE_ENDIAN */ 2318 uint8_t rctlmask; 2319 uint8_t rctlmatch; 2320 uint8_t tmask; 2321 uint8_t tmatch; 2322 #endif 2323 }; 2324 2325 2326 /* Structure for MB Command CONFIG_HBQ (7c) */ 2327 2328 struct config_hbq_var { 2329 #ifdef __BIG_ENDIAN_BITFIELD 2330 uint32_t rsvd1 :7; 2331 uint32_t recvNotify :1; /* Receive Notification */ 2332 uint32_t numMask :8; /* # Mask Entries */ 2333 uint32_t profile :8; /* Selection Profile */ 2334 uint32_t rsvd2 :8; 2335 #else /* __LITTLE_ENDIAN */ 2336 uint32_t rsvd2 :8; 2337 uint32_t profile :8; /* Selection Profile */ 2338 uint32_t numMask :8; /* # Mask Entries */ 2339 uint32_t recvNotify :1; /* Receive Notification */ 2340 uint32_t rsvd1 :7; 2341 #endif 2342 2343 #ifdef __BIG_ENDIAN_BITFIELD 2344 uint32_t hbqId :16; 2345 uint32_t rsvd3 :12; 2346 uint32_t ringMask :4; 2347 #else /* __LITTLE_ENDIAN */ 2348 uint32_t ringMask :4; 2349 uint32_t rsvd3 :12; 2350 uint32_t hbqId :16; 2351 #endif 2352 2353 #ifdef __BIG_ENDIAN_BITFIELD 2354 uint32_t entry_count :16; 2355 uint32_t rsvd4 :8; 2356 uint32_t headerLen :8; 2357 #else /* __LITTLE_ENDIAN */ 2358 uint32_t headerLen :8; 2359 uint32_t rsvd4 :8; 2360 uint32_t entry_count :16; 2361 #endif 2362 2363 uint32_t hbqaddrLow; 2364 uint32_t hbqaddrHigh; 2365 2366 #ifdef __BIG_ENDIAN_BITFIELD 2367 uint32_t rsvd5 :31; 2368 uint32_t logEntry :1; 2369 #else /* __LITTLE_ENDIAN */ 2370 uint32_t logEntry :1; 2371 uint32_t rsvd5 :31; 2372 #endif 2373 2374 uint32_t rsvd6; /* w7 */ 2375 uint32_t rsvd7; /* w8 */ 2376 uint32_t rsvd8; /* w9 */ 2377 2378 struct hbq_mask hbqMasks[6]; 2379 2380 2381 union { 2382 uint32_t allprofiles[12]; 2383 2384 struct { 2385 #ifdef __BIG_ENDIAN_BITFIELD 2386 uint32_t seqlenoff :16; 2387 uint32_t maxlen :16; 2388 #else /* __LITTLE_ENDIAN */ 2389 uint32_t maxlen :16; 2390 uint32_t seqlenoff :16; 2391 #endif 2392 #ifdef __BIG_ENDIAN_BITFIELD 2393 uint32_t rsvd1 :28; 2394 uint32_t seqlenbcnt :4; 2395 #else /* __LITTLE_ENDIAN */ 2396 uint32_t seqlenbcnt :4; 2397 uint32_t rsvd1 :28; 2398 #endif 2399 uint32_t rsvd[10]; 2400 } profile2; 2401 2402 struct { 2403 #ifdef __BIG_ENDIAN_BITFIELD 2404 uint32_t seqlenoff :16; 2405 uint32_t maxlen :16; 2406 #else /* __LITTLE_ENDIAN */ 2407 uint32_t maxlen :16; 2408 uint32_t seqlenoff :16; 2409 #endif 2410 #ifdef __BIG_ENDIAN_BITFIELD 2411 uint32_t cmdcodeoff :28; 2412 uint32_t rsvd1 :12; 2413 uint32_t seqlenbcnt :4; 2414 #else /* __LITTLE_ENDIAN */ 2415 uint32_t seqlenbcnt :4; 2416 uint32_t rsvd1 :12; 2417 uint32_t cmdcodeoff :28; 2418 #endif 2419 uint32_t cmdmatch[8]; 2420 2421 uint32_t rsvd[2]; 2422 } profile3; 2423 2424 struct { 2425 #ifdef __BIG_ENDIAN_BITFIELD 2426 uint32_t seqlenoff :16; 2427 uint32_t maxlen :16; 2428 #else /* __LITTLE_ENDIAN */ 2429 uint32_t maxlen :16; 2430 uint32_t seqlenoff :16; 2431 #endif 2432 #ifdef __BIG_ENDIAN_BITFIELD 2433 uint32_t cmdcodeoff :28; 2434 uint32_t rsvd1 :12; 2435 uint32_t seqlenbcnt :4; 2436 #else /* __LITTLE_ENDIAN */ 2437 uint32_t seqlenbcnt :4; 2438 uint32_t rsvd1 :12; 2439 uint32_t cmdcodeoff :28; 2440 #endif 2441 uint32_t cmdmatch[8]; 2442 2443 uint32_t rsvd[2]; 2444 } profile5; 2445 2446 } profiles; 2447 2448 }; 2449 2450 2451 2452 /* Structure for MB Command CONFIG_PORT (0x88) */ 2453 typedef struct { 2454 #ifdef __BIG_ENDIAN_BITFIELD 2455 uint32_t cBE : 1; 2456 uint32_t cET : 1; 2457 uint32_t cHpcb : 1; 2458 uint32_t cMA : 1; 2459 uint32_t sli_mode : 4; 2460 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2461 * config block */ 2462 #else /* __LITTLE_ENDIAN */ 2463 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2464 * config block */ 2465 uint32_t sli_mode : 4; 2466 uint32_t cMA : 1; 2467 uint32_t cHpcb : 1; 2468 uint32_t cET : 1; 2469 uint32_t cBE : 1; 2470 #endif 2471 2472 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2473 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2474 uint32_t hbainit[6]; 2475 2476 #ifdef __BIG_ENDIAN_BITFIELD 2477 uint32_t rsvd : 24; /* Reserved */ 2478 uint32_t cmv : 1; /* Configure Max VPIs */ 2479 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2480 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2481 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2482 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2483 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2484 uint32_t cmx : 1; /* Configure Max XRIs */ 2485 uint32_t cmr : 1; /* Configure Max RPIs */ 2486 #else /* __LITTLE_ENDIAN */ 2487 uint32_t cmr : 1; /* Configure Max RPIs */ 2488 uint32_t cmx : 1; /* Configure Max XRIs */ 2489 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2490 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2491 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2492 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2493 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2494 uint32_t cmv : 1; /* Configure Max VPIs */ 2495 uint32_t rsvd : 24; /* Reserved */ 2496 #endif 2497 #ifdef __BIG_ENDIAN_BITFIELD 2498 uint32_t rsvd2 : 24; /* Reserved */ 2499 uint32_t gmv : 1; /* Grant Max VPIs */ 2500 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2501 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2502 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2503 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2504 uint32_t gerbm : 1; /* Grant ERBM Request */ 2505 uint32_t gmx : 1; /* Grant Max XRIs */ 2506 uint32_t gmr : 1; /* Grant Max RPIs */ 2507 #else /* __LITTLE_ENDIAN */ 2508 uint32_t gmr : 1; /* Grant Max RPIs */ 2509 uint32_t gmx : 1; /* Grant Max XRIs */ 2510 uint32_t gerbm : 1; /* Grant ERBM Request */ 2511 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2512 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2513 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2514 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2515 uint32_t gmv : 1; /* Grant Max VPIs */ 2516 uint32_t rsvd2 : 24; /* Reserved */ 2517 #endif 2518 2519 #ifdef __BIG_ENDIAN_BITFIELD 2520 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2521 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2522 #else /* __LITTLE_ENDIAN */ 2523 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2524 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2525 #endif 2526 2527 #ifdef __BIG_ENDIAN_BITFIELD 2528 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2529 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */ 2530 #else /* __LITTLE_ENDIAN */ 2531 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */ 2532 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2533 #endif 2534 2535 uint32_t rsvd4; /* Reserved */ 2536 2537 #ifdef __BIG_ENDIAN_BITFIELD 2538 uint32_t rsvd5 : 16; /* Reserved */ 2539 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2540 #else /* __LITTLE_ENDIAN */ 2541 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2542 uint32_t rsvd5 : 16; /* Reserved */ 2543 #endif 2544 2545 } CONFIG_PORT_VAR; 2546 2547 /* SLI-2 Port Control Block */ 2548 2549 /* SLIM POINTER */ 2550 #define SLIMOFF 0x30 /* WORD */ 2551 2552 typedef struct _SLI2_RDSC { 2553 uint32_t cmdEntries; 2554 uint32_t cmdAddrLow; 2555 uint32_t cmdAddrHigh; 2556 2557 uint32_t rspEntries; 2558 uint32_t rspAddrLow; 2559 uint32_t rspAddrHigh; 2560 } SLI2_RDSC; 2561 2562 typedef struct _PCB { 2563 #ifdef __BIG_ENDIAN_BITFIELD 2564 uint32_t type:8; 2565 #define TYPE_NATIVE_SLI2 0x01; 2566 uint32_t feature:8; 2567 #define FEATURE_INITIAL_SLI2 0x01; 2568 uint32_t rsvd:12; 2569 uint32_t maxRing:4; 2570 #else /* __LITTLE_ENDIAN_BITFIELD */ 2571 uint32_t maxRing:4; 2572 uint32_t rsvd:12; 2573 uint32_t feature:8; 2574 #define FEATURE_INITIAL_SLI2 0x01; 2575 uint32_t type:8; 2576 #define TYPE_NATIVE_SLI2 0x01; 2577 #endif 2578 2579 uint32_t mailBoxSize; 2580 uint32_t mbAddrLow; 2581 uint32_t mbAddrHigh; 2582 2583 uint32_t hgpAddrLow; 2584 uint32_t hgpAddrHigh; 2585 2586 uint32_t pgpAddrLow; 2587 uint32_t pgpAddrHigh; 2588 SLI2_RDSC rdsc[MAX_RINGS]; 2589 } PCB_t; 2590 2591 /* NEW_FEATURE */ 2592 typedef struct { 2593 #ifdef __BIG_ENDIAN_BITFIELD 2594 uint32_t rsvd0:27; 2595 uint32_t discardFarp:1; 2596 uint32_t IPEnable:1; 2597 uint32_t nodeName:1; 2598 uint32_t portName:1; 2599 uint32_t filterEnable:1; 2600 #else /* __LITTLE_ENDIAN_BITFIELD */ 2601 uint32_t filterEnable:1; 2602 uint32_t portName:1; 2603 uint32_t nodeName:1; 2604 uint32_t IPEnable:1; 2605 uint32_t discardFarp:1; 2606 uint32_t rsvd:27; 2607 #endif 2608 2609 uint8_t portname[8]; /* Used to be struct lpfc_name */ 2610 uint8_t nodename[8]; 2611 uint32_t rsvd1; 2612 uint32_t rsvd2; 2613 uint32_t rsvd3; 2614 uint32_t IPAddress; 2615 } CONFIG_FARP_VAR; 2616 2617 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 2618 2619 typedef struct { 2620 #ifdef __BIG_ENDIAN_BITFIELD 2621 uint32_t rsvd:30; 2622 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2623 #else /* __LITTLE_ENDIAN */ 2624 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 2625 uint32_t rsvd:30; 2626 #endif 2627 } ASYNCEVT_ENABLE_VAR; 2628 2629 /* Union of all Mailbox Command types */ 2630 #define MAILBOX_CMD_WSIZE 32 2631 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 2632 2633 typedef union { 2634 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 2635 * feature/max ring number 2636 */ 2637 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 2638 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 2639 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 2640 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 2641 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 2642 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 2643 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 2644 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 2645 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 2646 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 2647 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 2648 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 2649 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 2650 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 2651 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 2652 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 2653 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 2654 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 2655 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 2656 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 2657 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */ 2658 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 2659 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 2660 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 2661 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 2662 * NEW_FEATURE 2663 */ 2664 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 2665 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 2666 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 2667 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 2668 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 2669 } MAILVARIANTS; 2670 2671 /* 2672 * SLI-2 specific structures 2673 */ 2674 2675 struct lpfc_hgp { 2676 __le32 cmdPutInx; 2677 __le32 rspGetInx; 2678 }; 2679 2680 struct lpfc_pgp { 2681 __le32 cmdGetInx; 2682 __le32 rspPutInx; 2683 }; 2684 2685 struct sli2_desc { 2686 uint32_t unused1[16]; 2687 struct lpfc_hgp host[MAX_RINGS]; 2688 struct lpfc_pgp port[MAX_RINGS]; 2689 }; 2690 2691 struct sli3_desc { 2692 struct lpfc_hgp host[MAX_RINGS]; 2693 uint32_t reserved[8]; 2694 uint32_t hbq_put[16]; 2695 }; 2696 2697 struct sli3_pgp { 2698 struct lpfc_pgp port[MAX_RINGS]; 2699 uint32_t hbq_get[16]; 2700 }; 2701 2702 typedef union { 2703 struct sli2_desc s2; 2704 struct sli3_desc s3; 2705 struct sli3_pgp s3_pgp; 2706 } SLI_VAR; 2707 2708 typedef struct { 2709 #ifdef __BIG_ENDIAN_BITFIELD 2710 uint16_t mbxStatus; 2711 uint8_t mbxCommand; 2712 uint8_t mbxReserved:6; 2713 uint8_t mbxHc:1; 2714 uint8_t mbxOwner:1; /* Low order bit first word */ 2715 #else /* __LITTLE_ENDIAN_BITFIELD */ 2716 uint8_t mbxOwner:1; /* Low order bit first word */ 2717 uint8_t mbxHc:1; 2718 uint8_t mbxReserved:6; 2719 uint8_t mbxCommand; 2720 uint16_t mbxStatus; 2721 #endif 2722 2723 MAILVARIANTS un; 2724 SLI_VAR us; 2725 } MAILBOX_t; 2726 2727 /* 2728 * Begin Structure Definitions for IOCB Commands 2729 */ 2730 2731 typedef struct { 2732 #ifdef __BIG_ENDIAN_BITFIELD 2733 uint8_t statAction; 2734 uint8_t statRsn; 2735 uint8_t statBaExp; 2736 uint8_t statLocalError; 2737 #else /* __LITTLE_ENDIAN_BITFIELD */ 2738 uint8_t statLocalError; 2739 uint8_t statBaExp; 2740 uint8_t statRsn; 2741 uint8_t statAction; 2742 #endif 2743 /* statRsn P/F_RJT reason codes */ 2744 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 2745 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 2746 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 2747 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 2748 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 2749 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 2750 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 2751 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 2752 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 2753 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 2754 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 2755 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 2756 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 2757 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 2758 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 2759 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 2760 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 2761 #define RJT_PROT_ERR 0x12 /* Protocol error */ 2762 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 2763 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 2764 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 2765 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 2766 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 2767 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 2768 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 2769 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 2770 2771 #define IOERR_SUCCESS 0x00 /* statLocalError */ 2772 #define IOERR_MISSING_CONTINUE 0x01 2773 #define IOERR_SEQUENCE_TIMEOUT 0x02 2774 #define IOERR_INTERNAL_ERROR 0x03 2775 #define IOERR_INVALID_RPI 0x04 2776 #define IOERR_NO_XRI 0x05 2777 #define IOERR_ILLEGAL_COMMAND 0x06 2778 #define IOERR_XCHG_DROPPED 0x07 2779 #define IOERR_ILLEGAL_FIELD 0x08 2780 #define IOERR_BAD_CONTINUE 0x09 2781 #define IOERR_TOO_MANY_BUFFERS 0x0A 2782 #define IOERR_RCV_BUFFER_WAITING 0x0B 2783 #define IOERR_NO_CONNECTION 0x0C 2784 #define IOERR_TX_DMA_FAILED 0x0D 2785 #define IOERR_RX_DMA_FAILED 0x0E 2786 #define IOERR_ILLEGAL_FRAME 0x0F 2787 #define IOERR_EXTRA_DATA 0x10 2788 #define IOERR_NO_RESOURCES 0x11 2789 #define IOERR_RESERVED 0x12 2790 #define IOERR_ILLEGAL_LENGTH 0x13 2791 #define IOERR_UNSUPPORTED_FEATURE 0x14 2792 #define IOERR_ABORT_IN_PROGRESS 0x15 2793 #define IOERR_ABORT_REQUESTED 0x16 2794 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 2795 #define IOERR_LOOP_OPEN_FAILURE 0x18 2796 #define IOERR_RING_RESET 0x19 2797 #define IOERR_LINK_DOWN 0x1A 2798 #define IOERR_CORRUPTED_DATA 0x1B 2799 #define IOERR_CORRUPTED_RPI 0x1C 2800 #define IOERR_OUT_OF_ORDER_DATA 0x1D 2801 #define IOERR_OUT_OF_ORDER_ACK 0x1E 2802 #define IOERR_DUP_FRAME 0x1F 2803 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 2804 #define IOERR_BAD_HOST_ADDRESS 0x21 2805 #define IOERR_RCV_HDRBUF_WAITING 0x22 2806 #define IOERR_MISSING_HDR_BUFFER 0x23 2807 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 2808 #define IOERR_ABORTMULT_REQUESTED 0x25 2809 #define IOERR_BUFFER_SHORTAGE 0x28 2810 #define IOERR_DEFAULT 0x29 2811 #define IOERR_CNT 0x2A 2812 2813 #define IOERR_DRVR_MASK 0x100 2814 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 2815 #define IOERR_SLI_BRESET 0x102 2816 #define IOERR_SLI_ABORTED 0x103 2817 } PARM_ERR; 2818 2819 typedef union { 2820 struct { 2821 #ifdef __BIG_ENDIAN_BITFIELD 2822 uint8_t Rctl; /* R_CTL field */ 2823 uint8_t Type; /* TYPE field */ 2824 uint8_t Dfctl; /* DF_CTL field */ 2825 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2826 #else /* __LITTLE_ENDIAN_BITFIELD */ 2827 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 2828 uint8_t Dfctl; /* DF_CTL field */ 2829 uint8_t Type; /* TYPE field */ 2830 uint8_t Rctl; /* R_CTL field */ 2831 #endif 2832 2833 #define BC 0x02 /* Broadcast Received - Fctl */ 2834 #define SI 0x04 /* Sequence Initiative */ 2835 #define LA 0x08 /* Ignore Link Attention state */ 2836 #define LS 0x80 /* Last Sequence */ 2837 } hcsw; 2838 uint32_t reserved; 2839 } WORD5; 2840 2841 /* IOCB Command template for a generic response */ 2842 typedef struct { 2843 uint32_t reserved[4]; 2844 PARM_ERR perr; 2845 } GENERIC_RSP; 2846 2847 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 2848 typedef struct { 2849 struct ulp_bde xrsqbde[2]; 2850 uint32_t xrsqRo; /* Starting Relative Offset */ 2851 WORD5 w5; /* Header control/status word */ 2852 } XR_SEQ_FIELDS; 2853 2854 /* IOCB Command template for ELS_REQUEST */ 2855 typedef struct { 2856 struct ulp_bde elsReq; 2857 struct ulp_bde elsRsp; 2858 2859 #ifdef __BIG_ENDIAN_BITFIELD 2860 uint32_t word4Rsvd:7; 2861 uint32_t fl:1; 2862 uint32_t myID:24; 2863 uint32_t word5Rsvd:8; 2864 uint32_t remoteID:24; 2865 #else /* __LITTLE_ENDIAN_BITFIELD */ 2866 uint32_t myID:24; 2867 uint32_t fl:1; 2868 uint32_t word4Rsvd:7; 2869 uint32_t remoteID:24; 2870 uint32_t word5Rsvd:8; 2871 #endif 2872 } ELS_REQUEST; 2873 2874 /* IOCB Command template for RCV_ELS_REQ */ 2875 typedef struct { 2876 struct ulp_bde elsReq[2]; 2877 uint32_t parmRo; 2878 2879 #ifdef __BIG_ENDIAN_BITFIELD 2880 uint32_t word5Rsvd:8; 2881 uint32_t remoteID:24; 2882 #else /* __LITTLE_ENDIAN_BITFIELD */ 2883 uint32_t remoteID:24; 2884 uint32_t word5Rsvd:8; 2885 #endif 2886 } RCV_ELS_REQ; 2887 2888 /* IOCB Command template for ABORT / CLOSE_XRI */ 2889 typedef struct { 2890 uint32_t rsvd[3]; 2891 uint32_t abortType; 2892 #define ABORT_TYPE_ABTX 0x00000000 2893 #define ABORT_TYPE_ABTS 0x00000001 2894 uint32_t parm; 2895 #ifdef __BIG_ENDIAN_BITFIELD 2896 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2897 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2898 #else /* __LITTLE_ENDIAN_BITFIELD */ 2899 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 2900 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 2901 #endif 2902 } AC_XRI; 2903 2904 /* IOCB Command template for ABORT_MXRI64 */ 2905 typedef struct { 2906 uint32_t rsvd[3]; 2907 uint32_t abortType; 2908 uint32_t parm; 2909 uint32_t iotag32; 2910 } A_MXRI64; 2911 2912 /* IOCB Command template for GET_RPI */ 2913 typedef struct { 2914 uint32_t rsvd[4]; 2915 uint32_t parmRo; 2916 #ifdef __BIG_ENDIAN_BITFIELD 2917 uint32_t word5Rsvd:8; 2918 uint32_t remoteID:24; 2919 #else /* __LITTLE_ENDIAN_BITFIELD */ 2920 uint32_t remoteID:24; 2921 uint32_t word5Rsvd:8; 2922 #endif 2923 } GET_RPI; 2924 2925 /* IOCB Command template for all FCP Initiator commands */ 2926 typedef struct { 2927 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 2928 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 2929 uint32_t fcpi_parm; 2930 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 2931 } FCPI_FIELDS; 2932 2933 /* IOCB Command template for all FCP Target commands */ 2934 typedef struct { 2935 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 2936 uint32_t fcpt_Offset; 2937 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 2938 } FCPT_FIELDS; 2939 2940 /* SLI-2 IOCB structure definitions */ 2941 2942 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 2943 typedef struct { 2944 ULP_BDL bdl; 2945 uint32_t xrsqRo; /* Starting Relative Offset */ 2946 WORD5 w5; /* Header control/status word */ 2947 } XMT_SEQ_FIELDS64; 2948 2949 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 2950 typedef struct { 2951 struct ulp_bde64 rcvBde; 2952 uint32_t rsvd1; 2953 uint32_t xrsqRo; /* Starting Relative Offset */ 2954 WORD5 w5; /* Header control/status word */ 2955 } RCV_SEQ_FIELDS64; 2956 2957 /* IOCB Command template for ELS_REQUEST64 */ 2958 typedef struct { 2959 ULP_BDL bdl; 2960 #ifdef __BIG_ENDIAN_BITFIELD 2961 uint32_t word4Rsvd:7; 2962 uint32_t fl:1; 2963 uint32_t myID:24; 2964 uint32_t word5Rsvd:8; 2965 uint32_t remoteID:24; 2966 #else /* __LITTLE_ENDIAN_BITFIELD */ 2967 uint32_t myID:24; 2968 uint32_t fl:1; 2969 uint32_t word4Rsvd:7; 2970 uint32_t remoteID:24; 2971 uint32_t word5Rsvd:8; 2972 #endif 2973 } ELS_REQUEST64; 2974 2975 /* IOCB Command template for GEN_REQUEST64 */ 2976 typedef struct { 2977 ULP_BDL bdl; 2978 uint32_t xrsqRo; /* Starting Relative Offset */ 2979 WORD5 w5; /* Header control/status word */ 2980 } GEN_REQUEST64; 2981 2982 /* IOCB Command template for RCV_ELS_REQ64 */ 2983 typedef struct { 2984 struct ulp_bde64 elsReq; 2985 uint32_t rcvd1; 2986 uint32_t parmRo; 2987 2988 #ifdef __BIG_ENDIAN_BITFIELD 2989 uint32_t word5Rsvd:8; 2990 uint32_t remoteID:24; 2991 #else /* __LITTLE_ENDIAN_BITFIELD */ 2992 uint32_t remoteID:24; 2993 uint32_t word5Rsvd:8; 2994 #endif 2995 } RCV_ELS_REQ64; 2996 2997 /* IOCB Command template for RCV_SEQ64 */ 2998 struct rcv_seq64 { 2999 struct ulp_bde64 elsReq; 3000 uint32_t hbq_1; 3001 uint32_t parmRo; 3002 #ifdef __BIG_ENDIAN_BITFIELD 3003 uint32_t rctl:8; 3004 uint32_t type:8; 3005 uint32_t dfctl:8; 3006 uint32_t ls:1; 3007 uint32_t fs:1; 3008 uint32_t rsvd2:3; 3009 uint32_t si:1; 3010 uint32_t bc:1; 3011 uint32_t rsvd3:1; 3012 #else /* __LITTLE_ENDIAN_BITFIELD */ 3013 uint32_t rsvd3:1; 3014 uint32_t bc:1; 3015 uint32_t si:1; 3016 uint32_t rsvd2:3; 3017 uint32_t fs:1; 3018 uint32_t ls:1; 3019 uint32_t dfctl:8; 3020 uint32_t type:8; 3021 uint32_t rctl:8; 3022 #endif 3023 }; 3024 3025 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3026 typedef struct { 3027 ULP_BDL bdl; 3028 uint32_t fcpi_parm; 3029 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3030 } FCPI_FIELDS64; 3031 3032 /* IOCB Command template for all 64 bit FCP Target commands */ 3033 typedef struct { 3034 ULP_BDL bdl; 3035 uint32_t fcpt_Offset; 3036 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3037 } FCPT_FIELDS64; 3038 3039 /* IOCB Command template for Async Status iocb commands */ 3040 typedef struct { 3041 uint32_t rsvd[4]; 3042 uint32_t param; 3043 #ifdef __BIG_ENDIAN_BITFIELD 3044 uint16_t evt_code; /* High order bits word 5 */ 3045 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3046 #else /* __LITTLE_ENDIAN_BITFIELD */ 3047 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3048 uint16_t evt_code; /* Low order bits word 5 */ 3049 #endif 3050 } ASYNCSTAT_FIELDS; 3051 #define ASYNC_TEMP_WARN 0x100 3052 #define ASYNC_TEMP_SAFE 0x101 3053 3054 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3055 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3056 3057 struct rcv_sli3 { 3058 uint32_t word8Rsvd; 3059 #ifdef __BIG_ENDIAN_BITFIELD 3060 uint16_t vpi; 3061 uint16_t word9Rsvd; 3062 #else /* __LITTLE_ENDIAN */ 3063 uint16_t word9Rsvd; 3064 uint16_t vpi; 3065 #endif 3066 uint32_t word10Rsvd; 3067 uint32_t acc_len; /* accumulated length */ 3068 struct ulp_bde64 bde2; 3069 }; 3070 3071 /* Structure used for a single HBQ entry */ 3072 struct lpfc_hbq_entry { 3073 struct ulp_bde64 bde; 3074 uint32_t buffer_tag; 3075 }; 3076 3077 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3078 typedef struct { 3079 struct lpfc_hbq_entry buff; 3080 uint32_t rsvd; 3081 uint32_t rsvd1; 3082 } QUE_XRI64_CX_FIELDS; 3083 3084 struct que_xri64cx_ext_fields { 3085 uint32_t iotag64_low; 3086 uint32_t iotag64_high; 3087 uint32_t ebde_count; 3088 uint32_t rsvd; 3089 struct lpfc_hbq_entry buff[5]; 3090 }; 3091 3092 typedef struct _IOCB { /* IOCB structure */ 3093 union { 3094 GENERIC_RSP grsp; /* Generic response */ 3095 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3096 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3097 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3098 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3099 A_MXRI64 amxri; /* abort multiple xri command overlay */ 3100 GET_RPI getrpi; /* GET_RPI template */ 3101 FCPI_FIELDS fcpi; /* FCP Initiator template */ 3102 FCPT_FIELDS fcpt; /* FCP target template */ 3103 3104 /* SLI-2 structures */ 3105 3106 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3107 * bde_64s */ 3108 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3109 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3110 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3111 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3112 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3113 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 3114 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 3115 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 3116 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3117 3118 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3119 } un; 3120 union { 3121 struct { 3122 #ifdef __BIG_ENDIAN_BITFIELD 3123 uint16_t ulpContext; /* High order bits word 6 */ 3124 uint16_t ulpIoTag; /* Low order bits word 6 */ 3125 #else /* __LITTLE_ENDIAN_BITFIELD */ 3126 uint16_t ulpIoTag; /* Low order bits word 6 */ 3127 uint16_t ulpContext; /* High order bits word 6 */ 3128 #endif 3129 } t1; 3130 struct { 3131 #ifdef __BIG_ENDIAN_BITFIELD 3132 uint16_t ulpContext; /* High order bits word 6 */ 3133 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3134 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3135 #else /* __LITTLE_ENDIAN_BITFIELD */ 3136 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3137 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3138 uint16_t ulpContext; /* High order bits word 6 */ 3139 #endif 3140 } t2; 3141 } un1; 3142 #define ulpContext un1.t1.ulpContext 3143 #define ulpIoTag un1.t1.ulpIoTag 3144 #define ulpIoTag0 un1.t2.ulpIoTag0 3145 3146 #ifdef __BIG_ENDIAN_BITFIELD 3147 uint32_t ulpTimeout:8; 3148 uint32_t ulpXS:1; 3149 uint32_t ulpFCP2Rcvy:1; 3150 uint32_t ulpPU:2; 3151 uint32_t ulpIr:1; 3152 uint32_t ulpClass:3; 3153 uint32_t ulpCommand:8; 3154 uint32_t ulpStatus:4; 3155 uint32_t ulpBdeCount:2; 3156 uint32_t ulpLe:1; 3157 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3158 #else /* __LITTLE_ENDIAN_BITFIELD */ 3159 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3160 uint32_t ulpLe:1; 3161 uint32_t ulpBdeCount:2; 3162 uint32_t ulpStatus:4; 3163 uint32_t ulpCommand:8; 3164 uint32_t ulpClass:3; 3165 uint32_t ulpIr:1; 3166 uint32_t ulpPU:2; 3167 uint32_t ulpFCP2Rcvy:1; 3168 uint32_t ulpXS:1; 3169 uint32_t ulpTimeout:8; 3170 #endif 3171 3172 union { 3173 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 3174 3175 /* words 8-31 used for que_xri_cx iocb */ 3176 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 3177 3178 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 3179 } unsli3; 3180 3181 #define ulpCt_h ulpXS 3182 #define ulpCt_l ulpFCP2Rcvy 3183 3184 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3185 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3186 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3187 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3188 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3189 #define PARM_NPIV_DID 3 3190 #define CLASS1 0 /* Class 1 */ 3191 #define CLASS2 1 /* Class 2 */ 3192 #define CLASS3 2 /* Class 3 */ 3193 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3194 3195 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3196 #define IOSTAT_FCP_RSP_ERROR 0x1 3197 #define IOSTAT_REMOTE_STOP 0x2 3198 #define IOSTAT_LOCAL_REJECT 0x3 3199 #define IOSTAT_NPORT_RJT 0x4 3200 #define IOSTAT_FABRIC_RJT 0x5 3201 #define IOSTAT_NPORT_BSY 0x6 3202 #define IOSTAT_FABRIC_BSY 0x7 3203 #define IOSTAT_INTERMED_RSP 0x8 3204 #define IOSTAT_LS_RJT 0x9 3205 #define IOSTAT_BA_RJT 0xA 3206 #define IOSTAT_RSVD1 0xB 3207 #define IOSTAT_RSVD2 0xC 3208 #define IOSTAT_RSVD3 0xD 3209 #define IOSTAT_RSVD4 0xE 3210 #define IOSTAT_NEED_BUFFER 0xF 3211 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3212 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3213 #define IOSTAT_CNT 0x11 3214 3215 } IOCB_t; 3216 3217 3218 #define SLI1_SLIM_SIZE (4 * 1024) 3219 3220 /* Up to 498 IOCBs will fit into 16k 3221 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3222 */ 3223 #define SLI2_SLIM_SIZE (64 * 1024) 3224 3225 /* Maximum IOCBs that will fit in SLI2 slim */ 3226 #define MAX_SLI2_IOCB 498 3227 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3228 (sizeof(MAILBOX_t) + sizeof(PCB_t))) 3229 3230 /* HBQ entries are 4 words each = 4k */ 3231 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3232 lpfc_sli_hbq_count()) 3233 3234 struct lpfc_sli2_slim { 3235 MAILBOX_t mbx; 3236 PCB_t pcb; 3237 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3238 }; 3239 3240 /* 3241 * This function checks PCI device to allow special handling for LC HBAs. 3242 * 3243 * Parameters: 3244 * device : struct pci_dev 's device field 3245 * 3246 * return 1 => TRUE 3247 * 0 => FALSE 3248 */ 3249 static inline int 3250 lpfc_is_LC_HBA(unsigned short device) 3251 { 3252 if ((device == PCI_DEVICE_ID_TFLY) || 3253 (device == PCI_DEVICE_ID_PFLY) || 3254 (device == PCI_DEVICE_ID_LP101) || 3255 (device == PCI_DEVICE_ID_BMID) || 3256 (device == PCI_DEVICE_ID_BSMB) || 3257 (device == PCI_DEVICE_ID_ZMID) || 3258 (device == PCI_DEVICE_ID_ZSMB) || 3259 (device == PCI_DEVICE_ID_SAT_MID) || 3260 (device == PCI_DEVICE_ID_SAT_SMB) || 3261 (device == PCI_DEVICE_ID_RFLY)) 3262 return 1; 3263 else 3264 return 0; 3265 } 3266 3267 /* 3268 * Determine if an IOCB failed because of a link event or firmware reset. 3269 */ 3270 3271 static inline int 3272 lpfc_error_lost_link(IOCB_t *iocbp) 3273 { 3274 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3275 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3276 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3277 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3278 } 3279