1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2015 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 #define LPFC_FCP_OAS_RING 3 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 uint32_t CmdRsp:16; 90 uint32_t Size:16; 91 } bits; 92 uint32_t word; 93 }; 94 95 #define FC4_FEATURE_INIT 0x2 96 #define FC4_FEATURE_TARGET 0x1 97 98 struct lpfc_sli_ct_request { 99 /* Structure is in Big Endian format */ 100 union CtRevisionId RevisionId; 101 uint8_t FsType; 102 uint8_t FsSubType; 103 uint8_t Options; 104 uint8_t Rsrvd1; 105 union CtCommandResponse CommandResponse; 106 uint8_t Rsrvd2; 107 uint8_t ReasonCode; 108 uint8_t Explanation; 109 uint8_t VendorUnique; 110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 111 112 union { 113 uint32_t PortID; 114 struct gid { 115 uint8_t PortType; /* for GID_PT requests */ 116 uint8_t DomainScope; 117 uint8_t AreaScope; 118 uint8_t Fc4Type; /* for GID_FT requests */ 119 } gid; 120 struct rft { 121 uint32_t PortId; /* For RFT_ID requests */ 122 123 #ifdef __BIG_ENDIAN_BITFIELD 124 uint32_t rsvd0:16; 125 uint32_t rsvd1:7; 126 uint32_t fcpReg:1; /* Type 8 */ 127 uint32_t rsvd2:2; 128 uint32_t ipReg:1; /* Type 5 */ 129 uint32_t rsvd3:5; 130 #else /* __LITTLE_ENDIAN_BITFIELD */ 131 uint32_t rsvd0:16; 132 uint32_t fcpReg:1; /* Type 8 */ 133 uint32_t rsvd1:7; 134 uint32_t rsvd3:5; 135 uint32_t ipReg:1; /* Type 5 */ 136 uint32_t rsvd2:2; 137 #endif 138 139 uint32_t rsvd[7]; 140 } rft; 141 struct rnn { 142 uint32_t PortId; /* For RNN_ID requests */ 143 uint8_t wwnn[8]; 144 } rnn; 145 struct rsnn { /* For RSNN_ID requests */ 146 uint8_t wwnn[8]; 147 uint8_t len; 148 uint8_t symbname[255]; 149 } rsnn; 150 struct da_id { /* For DA_ID requests */ 151 uint32_t port_id; 152 } da_id; 153 struct rspn { /* For RSPN_ID requests */ 154 uint32_t PortId; 155 uint8_t len; 156 uint8_t symbname[255]; 157 } rspn; 158 struct gff { 159 uint32_t PortId; 160 } gff; 161 struct gff_acc { 162 uint8_t fbits[128]; 163 } gff_acc; 164 #define FCP_TYPE_FEATURE_OFFSET 7 165 struct rff { 166 uint32_t PortId; 167 uint8_t reserved[2]; 168 uint8_t fbits; 169 uint8_t type_code; /* type=8 for FCP */ 170 } rff; 171 } un; 172 }; 173 174 #define LPFC_MAX_CT_SIZE (60 * 4096) 175 176 #define SLI_CT_REVISION 1 177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 178 sizeof(struct gid)) 179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 180 sizeof(struct gff)) 181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 182 sizeof(struct rft)) 183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 184 sizeof(struct rff)) 185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 186 sizeof(struct rnn)) 187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 188 sizeof(struct rsnn)) 189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 190 sizeof(struct da_id)) 191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 192 sizeof(struct rspn)) 193 194 /* 195 * FsType Definitions 196 */ 197 198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 199 #define SLI_CT_TIME_SERVICE 0xFB 200 #define SLI_CT_DIRECTORY_SERVICE 0xFC 201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 202 203 /* 204 * Directory Service Subtypes 205 */ 206 207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 208 209 /* 210 * Response Codes 211 */ 212 213 #define SLI_CT_RESPONSE_FS_RJT 0x8001 214 #define SLI_CT_RESPONSE_FS_ACC 0x8002 215 216 /* 217 * Reason Codes 218 */ 219 220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 221 #define SLI_CT_INVALID_COMMAND 0x01 222 #define SLI_CT_INVALID_VERSION 0x02 223 #define SLI_CT_LOGICAL_ERROR 0x03 224 #define SLI_CT_INVALID_IU_SIZE 0x04 225 #define SLI_CT_LOGICAL_BUSY 0x05 226 #define SLI_CT_PROTOCOL_ERROR 0x07 227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 236 #define SLI_CT_VENDOR_UNIQUE 0xff 237 238 /* 239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 240 */ 241 242 #define SLI_CT_NO_PORT_ID 0x01 243 #define SLI_CT_NO_PORT_NAME 0x02 244 #define SLI_CT_NO_NODE_NAME 0x03 245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 246 #define SLI_CT_NO_IP_ADDRESS 0x05 247 #define SLI_CT_NO_IPA 0x06 248 #define SLI_CT_NO_FC4_TYPES 0x07 249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 251 #define SLI_CT_NO_PORT_TYPE 0x0A 252 #define SLI_CT_ACCESS_DENIED 0x10 253 #define SLI_CT_INVALID_PORT_ID 0x11 254 #define SLI_CT_DATABASE_EMPTY 0x12 255 256 /* 257 * Name Server Command Codes 258 */ 259 260 #define SLI_CTNS_GA_NXT 0x0100 261 #define SLI_CTNS_GPN_ID 0x0112 262 #define SLI_CTNS_GNN_ID 0x0113 263 #define SLI_CTNS_GCS_ID 0x0114 264 #define SLI_CTNS_GFT_ID 0x0117 265 #define SLI_CTNS_GSPN_ID 0x0118 266 #define SLI_CTNS_GPT_ID 0x011A 267 #define SLI_CTNS_GFF_ID 0x011F 268 #define SLI_CTNS_GID_PN 0x0121 269 #define SLI_CTNS_GID_NN 0x0131 270 #define SLI_CTNS_GIP_NN 0x0135 271 #define SLI_CTNS_GIPA_NN 0x0136 272 #define SLI_CTNS_GSNN_NN 0x0139 273 #define SLI_CTNS_GNN_IP 0x0153 274 #define SLI_CTNS_GIPA_IP 0x0156 275 #define SLI_CTNS_GID_FT 0x0171 276 #define SLI_CTNS_GID_PT 0x01A1 277 #define SLI_CTNS_RPN_ID 0x0212 278 #define SLI_CTNS_RNN_ID 0x0213 279 #define SLI_CTNS_RCS_ID 0x0214 280 #define SLI_CTNS_RFT_ID 0x0217 281 #define SLI_CTNS_RSPN_ID 0x0218 282 #define SLI_CTNS_RPT_ID 0x021A 283 #define SLI_CTNS_RFF_ID 0x021F 284 #define SLI_CTNS_RIP_NN 0x0235 285 #define SLI_CTNS_RIPA_NN 0x0236 286 #define SLI_CTNS_RSNN_NN 0x0239 287 #define SLI_CTNS_DA_ID 0x0300 288 289 /* 290 * Port Types 291 */ 292 293 #define SLI_CTPT_N_PORT 0x01 294 #define SLI_CTPT_NL_PORT 0x02 295 #define SLI_CTPT_FNL_PORT 0x03 296 #define SLI_CTPT_IP 0x04 297 #define SLI_CTPT_FCP 0x08 298 #define SLI_CTPT_NX_PORT 0x7F 299 #define SLI_CTPT_F_PORT 0x81 300 #define SLI_CTPT_FL_PORT 0x82 301 #define SLI_CTPT_E_PORT 0x84 302 303 #define SLI_CT_LAST_ENTRY 0x80000000 304 305 /* Fibre Channel Service Parameter definitions */ 306 307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 311 312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 314 #define FC_PH3 0x20 /* FC-PH-3 version */ 315 316 #define FF_FRAME_SIZE 2048 317 318 struct lpfc_name { 319 union { 320 struct { 321 #ifdef __BIG_ENDIAN_BITFIELD 322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 324 8:11 of IEEE ext */ 325 #else /* __LITTLE_ENDIAN_BITFIELD */ 326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 327 8:11 of IEEE ext */ 328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 329 #endif 330 331 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 333 #define NAME_FC_TYPE 0x3 /* FC native name type */ 334 #define NAME_IP_TYPE 0x4 /* IP address */ 335 #define NAME_CCITT_TYPE 0xC 336 #define NAME_CCITT_GR_TYPE 0xE 337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 338 extended Lsb */ 339 uint8_t IEEE[6]; /* FC IEEE address */ 340 } s; 341 uint8_t wwn[8]; 342 } u; 343 }; 344 345 struct csp { 346 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 347 uint8_t fcphLow; 348 uint8_t bbCreditMsb; 349 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 350 351 /* 352 * Word 1 Bit 31 in common service parameter is overloaded. 353 * Word 1 Bit 31 in FLOGI request is multiple NPort request 354 * Word 1 Bit 31 in FLOGI response is clean address bit 355 */ 356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 357 /* 358 * Word 1 Bit 30 in common service parameter is overloaded. 359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 360 * Word 1 Bit 30 in PLOGI request is random offset 361 */ 362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 363 #ifdef __BIG_ENDIAN_BITFIELD 364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 365 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 367 uint16_t fPort:1; /* FC Word 1, bit 28 */ 368 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 370 uint16_t multicast:1; /* FC Word 1, bit 25 */ 371 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 372 373 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 374 uint16_t simplex:1; /* FC Word 1, bit 22 */ 375 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 376 uint16_t dhd:1; /* FC Word 1, bit 18 */ 377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 379 #else /* __LITTLE_ENDIAN_BITFIELD */ 380 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 381 uint16_t multicast:1; /* FC Word 1, bit 25 */ 382 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 383 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 384 uint16_t fPort:1; /* FC Word 1, bit 28 */ 385 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 386 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 387 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 388 389 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 390 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 391 uint16_t dhd:1; /* FC Word 1, bit 18 */ 392 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 393 uint16_t simplex:1; /* FC Word 1, bit 22 */ 394 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 395 #endif 396 397 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 398 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 399 union { 400 struct { 401 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 402 403 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 404 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 405 406 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 407 } nPort; 408 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 409 } w2; 410 411 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 412 }; 413 414 struct class_parms { 415 #ifdef __BIG_ENDIAN_BITFIELD 416 uint8_t classValid:1; /* FC Word 0, bit 31 */ 417 uint8_t intermix:1; /* FC Word 0, bit 30 */ 418 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 419 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 420 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 421 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 422 #else /* __LITTLE_ENDIAN_BITFIELD */ 423 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 424 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 426 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 427 uint8_t intermix:1; /* FC Word 0, bit 30 */ 428 uint8_t classValid:1; /* FC Word 0, bit 31 */ 429 430 #endif 431 432 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 433 434 #ifdef __BIG_ENDIAN_BITFIELD 435 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 436 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 437 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 438 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 439 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 440 #else /* __LITTLE_ENDIAN_BITFIELD */ 441 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 442 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 444 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 445 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 446 #endif 447 448 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 449 450 #ifdef __BIG_ENDIAN_BITFIELD 451 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 452 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 453 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 454 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 455 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 456 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 457 #else /* __LITTLE_ENDIAN_BITFIELD */ 458 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 459 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 461 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 462 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 463 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 464 #endif 465 466 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 467 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 468 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 469 470 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 471 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 472 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 473 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 474 475 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 476 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 477 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 478 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 479 }; 480 481 struct serv_parm { /* Structure is in Big Endian format */ 482 struct csp cmn; 483 struct lpfc_name portName; 484 struct lpfc_name nodeName; 485 struct class_parms cls1; 486 struct class_parms cls2; 487 struct class_parms cls3; 488 struct class_parms cls4; 489 uint8_t vendorVersion[16]; 490 }; 491 492 /* 493 * Virtual Fabric Tagging Header 494 */ 495 struct fc_vft_header { 496 uint32_t word0; 497 #define fc_vft_hdr_r_ctl_SHIFT 24 498 #define fc_vft_hdr_r_ctl_MASK 0xFF 499 #define fc_vft_hdr_r_ctl_WORD word0 500 #define fc_vft_hdr_ver_SHIFT 22 501 #define fc_vft_hdr_ver_MASK 0x3 502 #define fc_vft_hdr_ver_WORD word0 503 #define fc_vft_hdr_type_SHIFT 18 504 #define fc_vft_hdr_type_MASK 0xF 505 #define fc_vft_hdr_type_WORD word0 506 #define fc_vft_hdr_e_SHIFT 16 507 #define fc_vft_hdr_e_MASK 0x1 508 #define fc_vft_hdr_e_WORD word0 509 #define fc_vft_hdr_priority_SHIFT 13 510 #define fc_vft_hdr_priority_MASK 0x7 511 #define fc_vft_hdr_priority_WORD word0 512 #define fc_vft_hdr_vf_id_SHIFT 1 513 #define fc_vft_hdr_vf_id_MASK 0xFFF 514 #define fc_vft_hdr_vf_id_WORD word0 515 uint32_t word1; 516 #define fc_vft_hdr_hopct_SHIFT 24 517 #define fc_vft_hdr_hopct_MASK 0xFF 518 #define fc_vft_hdr_hopct_WORD word1 519 }; 520 521 /* 522 * Extended Link Service LS_COMMAND codes (Payload Word 0) 523 */ 524 #ifdef __BIG_ENDIAN_BITFIELD 525 #define ELS_CMD_MASK 0xffff0000 526 #define ELS_RSP_MASK 0xff000000 527 #define ELS_CMD_LS_RJT 0x01000000 528 #define ELS_CMD_ACC 0x02000000 529 #define ELS_CMD_PLOGI 0x03000000 530 #define ELS_CMD_FLOGI 0x04000000 531 #define ELS_CMD_LOGO 0x05000000 532 #define ELS_CMD_ABTX 0x06000000 533 #define ELS_CMD_RCS 0x07000000 534 #define ELS_CMD_RES 0x08000000 535 #define ELS_CMD_RSS 0x09000000 536 #define ELS_CMD_RSI 0x0A000000 537 #define ELS_CMD_ESTS 0x0B000000 538 #define ELS_CMD_ESTC 0x0C000000 539 #define ELS_CMD_ADVC 0x0D000000 540 #define ELS_CMD_RTV 0x0E000000 541 #define ELS_CMD_RLS 0x0F000000 542 #define ELS_CMD_ECHO 0x10000000 543 #define ELS_CMD_TEST 0x11000000 544 #define ELS_CMD_RRQ 0x12000000 545 #define ELS_CMD_REC 0x13000000 546 #define ELS_CMD_PRLI 0x20100014 547 #define ELS_CMD_PRLO 0x21100014 548 #define ELS_CMD_PRLO_ACC 0x02100014 549 #define ELS_CMD_PDISC 0x50000000 550 #define ELS_CMD_FDISC 0x51000000 551 #define ELS_CMD_ADISC 0x52000000 552 #define ELS_CMD_FARP 0x54000000 553 #define ELS_CMD_FARPR 0x55000000 554 #define ELS_CMD_RPS 0x56000000 555 #define ELS_CMD_RPL 0x57000000 556 #define ELS_CMD_FAN 0x60000000 557 #define ELS_CMD_RSCN 0x61040000 558 #define ELS_CMD_SCR 0x62000000 559 #define ELS_CMD_RNID 0x78000000 560 #define ELS_CMD_LIRR 0x7A000000 561 #else /* __LITTLE_ENDIAN_BITFIELD */ 562 #define ELS_CMD_MASK 0xffff 563 #define ELS_RSP_MASK 0xff 564 #define ELS_CMD_LS_RJT 0x01 565 #define ELS_CMD_ACC 0x02 566 #define ELS_CMD_PLOGI 0x03 567 #define ELS_CMD_FLOGI 0x04 568 #define ELS_CMD_LOGO 0x05 569 #define ELS_CMD_ABTX 0x06 570 #define ELS_CMD_RCS 0x07 571 #define ELS_CMD_RES 0x08 572 #define ELS_CMD_RSS 0x09 573 #define ELS_CMD_RSI 0x0A 574 #define ELS_CMD_ESTS 0x0B 575 #define ELS_CMD_ESTC 0x0C 576 #define ELS_CMD_ADVC 0x0D 577 #define ELS_CMD_RTV 0x0E 578 #define ELS_CMD_RLS 0x0F 579 #define ELS_CMD_ECHO 0x10 580 #define ELS_CMD_TEST 0x11 581 #define ELS_CMD_RRQ 0x12 582 #define ELS_CMD_REC 0x13 583 #define ELS_CMD_PRLI 0x14001020 584 #define ELS_CMD_PRLO 0x14001021 585 #define ELS_CMD_PRLO_ACC 0x14001002 586 #define ELS_CMD_PDISC 0x50 587 #define ELS_CMD_FDISC 0x51 588 #define ELS_CMD_ADISC 0x52 589 #define ELS_CMD_FARP 0x54 590 #define ELS_CMD_FARPR 0x55 591 #define ELS_CMD_RPS 0x56 592 #define ELS_CMD_RPL 0x57 593 #define ELS_CMD_FAN 0x60 594 #define ELS_CMD_RSCN 0x0461 595 #define ELS_CMD_SCR 0x62 596 #define ELS_CMD_RNID 0x78 597 #define ELS_CMD_LIRR 0x7A 598 #endif 599 600 /* 601 * LS_RJT Payload Definition 602 */ 603 604 struct ls_rjt { /* Structure is in Big Endian format */ 605 union { 606 uint32_t lsRjtError; 607 struct { 608 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 609 610 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 611 /* LS_RJT reason codes */ 612 #define LSRJT_INVALID_CMD 0x01 613 #define LSRJT_LOGICAL_ERR 0x03 614 #define LSRJT_LOGICAL_BSY 0x05 615 #define LSRJT_PROTOCOL_ERR 0x07 616 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 617 #define LSRJT_CMD_UNSUPPORTED 0x0B 618 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 619 620 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 621 /* LS_RJT reason explanation */ 622 #define LSEXP_NOTHING_MORE 0x00 623 #define LSEXP_SPARM_OPTIONS 0x01 624 #define LSEXP_SPARM_ICTL 0x03 625 #define LSEXP_SPARM_RCTL 0x05 626 #define LSEXP_SPARM_RCV_SIZE 0x07 627 #define LSEXP_SPARM_CONCUR_SEQ 0x09 628 #define LSEXP_SPARM_CREDIT 0x0B 629 #define LSEXP_INVALID_PNAME 0x0D 630 #define LSEXP_INVALID_NNAME 0x0E 631 #define LSEXP_INVALID_CSP 0x0F 632 #define LSEXP_INVALID_ASSOC_HDR 0x11 633 #define LSEXP_ASSOC_HDR_REQ 0x13 634 #define LSEXP_INVALID_O_SID 0x15 635 #define LSEXP_INVALID_OX_RX 0x17 636 #define LSEXP_CMD_IN_PROGRESS 0x19 637 #define LSEXP_PORT_LOGIN_REQ 0x1E 638 #define LSEXP_INVALID_NPORT_ID 0x1F 639 #define LSEXP_INVALID_SEQ_ID 0x21 640 #define LSEXP_INVALID_XCHG 0x23 641 #define LSEXP_INACTIVE_XCHG 0x25 642 #define LSEXP_RQ_REQUIRED 0x27 643 #define LSEXP_OUT_OF_RESOURCE 0x29 644 #define LSEXP_CANT_GIVE_DATA 0x2A 645 #define LSEXP_REQ_UNSUPPORTED 0x2C 646 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 647 } b; 648 } un; 649 }; 650 651 /* 652 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 653 */ 654 655 typedef struct _LOGO { /* Structure is in Big Endian format */ 656 union { 657 uint32_t nPortId32; /* Access nPortId as a word */ 658 struct { 659 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 660 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 661 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 662 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 663 } b; 664 } un; 665 struct lpfc_name portName; /* N_port name field */ 666 } LOGO; 667 668 /* 669 * FCP Login (PRLI Request / ACC) Payload Definition 670 */ 671 672 #define PRLX_PAGE_LEN 0x10 673 #define TPRLO_PAGE_LEN 0x14 674 675 typedef struct _PRLI { /* Structure is in Big Endian format */ 676 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 677 678 #define PRLI_FCP_TYPE 0x08 679 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 680 681 #ifdef __BIG_ENDIAN_BITFIELD 682 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 683 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 684 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 685 686 /* ACC = imagePairEstablished */ 687 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 688 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 689 #else /* __LITTLE_ENDIAN_BITFIELD */ 690 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 691 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 692 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 693 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 694 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 695 /* ACC = imagePairEstablished */ 696 #endif 697 698 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 699 #define PRLI_NO_RESOURCES 0x2 700 #define PRLI_INIT_INCOMPLETE 0x3 701 #define PRLI_NO_SUCH_PA 0x4 702 #define PRLI_PREDEF_CONFIG 0x5 703 #define PRLI_PARTIAL_SUCCESS 0x6 704 #define PRLI_INVALID_PAGE_CNT 0x7 705 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 706 707 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 708 709 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 710 711 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 712 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 713 714 #ifdef __BIG_ENDIAN_BITFIELD 715 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 716 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 717 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 718 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 719 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 720 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 721 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 722 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 723 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 724 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 725 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 726 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 727 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 728 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 729 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 730 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 731 #else /* __LITTLE_ENDIAN_BITFIELD */ 732 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 733 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 734 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 735 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 736 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 737 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 738 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 739 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 740 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 741 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 742 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 743 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 744 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 745 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 746 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 747 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 748 #endif 749 } PRLI; 750 751 /* 752 * FCP Logout (PRLO Request / ACC) Payload Definition 753 */ 754 755 typedef struct _PRLO { /* Structure is in Big Endian format */ 756 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 757 758 #define PRLO_FCP_TYPE 0x08 759 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 760 761 #ifdef __BIG_ENDIAN_BITFIELD 762 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 763 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 764 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 765 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 766 #else /* __LITTLE_ENDIAN_BITFIELD */ 767 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 768 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 769 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 770 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 771 #endif 772 773 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 774 #define PRLO_NO_SUCH_IMAGE 0x4 775 #define PRLO_INVALID_PAGE_CNT 0x7 776 777 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 778 779 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 780 781 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 782 783 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 784 } PRLO; 785 786 typedef struct _ADISC { /* Structure is in Big Endian format */ 787 uint32_t hardAL_PA; 788 struct lpfc_name portName; 789 struct lpfc_name nodeName; 790 uint32_t DID; 791 } ADISC; 792 793 typedef struct _FARP { /* Structure is in Big Endian format */ 794 uint32_t Mflags:8; 795 uint32_t Odid:24; 796 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 797 action */ 798 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 799 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 800 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 801 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 802 supported */ 803 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 804 supported */ 805 uint32_t Rflags:8; 806 uint32_t Rdid:24; 807 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 808 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 809 struct lpfc_name OportName; 810 struct lpfc_name OnodeName; 811 struct lpfc_name RportName; 812 struct lpfc_name RnodeName; 813 uint8_t Oipaddr[16]; 814 uint8_t Ripaddr[16]; 815 } FARP; 816 817 typedef struct _FAN { /* Structure is in Big Endian format */ 818 uint32_t Fdid; 819 struct lpfc_name FportName; 820 struct lpfc_name FnodeName; 821 } FAN; 822 823 typedef struct _SCR { /* Structure is in Big Endian format */ 824 uint8_t resvd1; 825 uint8_t resvd2; 826 uint8_t resvd3; 827 uint8_t Function; 828 #define SCR_FUNC_FABRIC 0x01 829 #define SCR_FUNC_NPORT 0x02 830 #define SCR_FUNC_FULL 0x03 831 #define SCR_CLEAR 0xff 832 } SCR; 833 834 typedef struct _RNID_TOP_DISC { 835 struct lpfc_name portName; 836 uint8_t resvd[8]; 837 uint32_t unitType; 838 #define RNID_HBA 0x7 839 #define RNID_HOST 0xa 840 #define RNID_DRIVER 0xd 841 uint32_t physPort; 842 uint32_t attachedNodes; 843 uint16_t ipVersion; 844 #define RNID_IPV4 0x1 845 #define RNID_IPV6 0x2 846 uint16_t UDPport; 847 uint8_t ipAddr[16]; 848 uint16_t resvd1; 849 uint16_t flags; 850 #define RNID_TD_SUPPORT 0x1 851 #define RNID_LP_VALID 0x2 852 } RNID_TOP_DISC; 853 854 typedef struct _RNID { /* Structure is in Big Endian format */ 855 uint8_t Format; 856 #define RNID_TOPOLOGY_DISC 0xdf 857 uint8_t CommonLen; 858 uint8_t resvd1; 859 uint8_t SpecificLen; 860 struct lpfc_name portName; 861 struct lpfc_name nodeName; 862 union { 863 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 864 } un; 865 } RNID; 866 867 typedef struct _RPS { /* Structure is in Big Endian format */ 868 union { 869 uint32_t portNum; 870 struct lpfc_name portName; 871 } un; 872 } RPS; 873 874 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 875 uint16_t rsvd1; 876 uint16_t portStatus; 877 uint32_t linkFailureCnt; 878 uint32_t lossSyncCnt; 879 uint32_t lossSignalCnt; 880 uint32_t primSeqErrCnt; 881 uint32_t invalidXmitWord; 882 uint32_t crcCnt; 883 } RPS_RSP; 884 885 struct RLS { /* Structure is in Big Endian format */ 886 uint32_t rls; 887 #define rls_rsvd_SHIFT 24 888 #define rls_rsvd_MASK 0x000000ff 889 #define rls_rsvd_WORD rls 890 #define rls_did_SHIFT 0 891 #define rls_did_MASK 0x00ffffff 892 #define rls_did_WORD rls 893 }; 894 895 struct RLS_RSP { /* Structure is in Big Endian format */ 896 uint32_t linkFailureCnt; 897 uint32_t lossSyncCnt; 898 uint32_t lossSignalCnt; 899 uint32_t primSeqErrCnt; 900 uint32_t invalidXmitWord; 901 uint32_t crcCnt; 902 }; 903 904 struct RRQ { /* Structure is in Big Endian format */ 905 uint32_t rrq; 906 #define rrq_rsvd_SHIFT 24 907 #define rrq_rsvd_MASK 0x000000ff 908 #define rrq_rsvd_WORD rrq 909 #define rrq_did_SHIFT 0 910 #define rrq_did_MASK 0x00ffffff 911 #define rrq_did_WORD rrq 912 uint32_t rrq_exchg; 913 #define rrq_oxid_SHIFT 16 914 #define rrq_oxid_MASK 0xffff 915 #define rrq_oxid_WORD rrq_exchg 916 #define rrq_rxid_SHIFT 0 917 #define rrq_rxid_MASK 0xffff 918 #define rrq_rxid_WORD rrq_exchg 919 }; 920 921 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 922 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 923 924 struct RTV_RSP { /* Structure is in Big Endian format */ 925 uint32_t ratov; 926 uint32_t edtov; 927 uint32_t qtov; 928 #define qtov_rsvd0_SHIFT 28 929 #define qtov_rsvd0_MASK 0x0000000f 930 #define qtov_rsvd0_WORD qtov /* reserved */ 931 #define qtov_edtovres_SHIFT 27 932 #define qtov_edtovres_MASK 0x00000001 933 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 934 #define qtov__rsvd1_SHIFT 19 935 #define qtov_rsvd1_MASK 0x0000003f 936 #define qtov_rsvd1_WORD qtov /* reserved */ 937 #define qtov_rttov_SHIFT 18 938 #define qtov_rttov_MASK 0x00000001 939 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 940 #define qtov_rsvd2_SHIFT 0 941 #define qtov_rsvd2_MASK 0x0003ffff 942 #define qtov_rsvd2_WORD qtov /* reserved */ 943 }; 944 945 946 typedef struct _RPL { /* Structure is in Big Endian format */ 947 uint32_t maxsize; 948 uint32_t index; 949 } RPL; 950 951 typedef struct _PORT_NUM_BLK { 952 uint32_t portNum; 953 uint32_t portID; 954 struct lpfc_name portName; 955 } PORT_NUM_BLK; 956 957 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 958 uint32_t listLen; 959 uint32_t index; 960 PORT_NUM_BLK port_num_blk; 961 } RPL_RSP; 962 963 /* This is used for RSCN command */ 964 typedef struct _D_ID { /* Structure is in Big Endian format */ 965 union { 966 uint32_t word; 967 struct { 968 #ifdef __BIG_ENDIAN_BITFIELD 969 uint8_t resv; 970 uint8_t domain; 971 uint8_t area; 972 uint8_t id; 973 #else /* __LITTLE_ENDIAN_BITFIELD */ 974 uint8_t id; 975 uint8_t area; 976 uint8_t domain; 977 uint8_t resv; 978 #endif 979 } b; 980 } un; 981 } D_ID; 982 983 #define RSCN_ADDRESS_FORMAT_PORT 0x0 984 #define RSCN_ADDRESS_FORMAT_AREA 0x1 985 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 986 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 987 #define RSCN_ADDRESS_FORMAT_MASK 0x3 988 989 /* 990 * Structure to define all ELS Payload types 991 */ 992 993 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 994 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 995 uint8_t elsByte1; 996 uint8_t elsByte2; 997 uint8_t elsByte3; 998 union { 999 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1000 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1001 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1002 PRLI prli; /* Payload for PRLI/ACC */ 1003 PRLO prlo; /* Payload for PRLO/ACC */ 1004 ADISC adisc; /* Payload for ADISC/ACC */ 1005 FARP farp; /* Payload for FARP/ACC */ 1006 FAN fan; /* Payload for FAN */ 1007 SCR scr; /* Payload for SCR/ACC */ 1008 RNID rnid; /* Payload for RNID */ 1009 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1010 } un; 1011 } ELS_PKT; 1012 1013 /******** FDMI ********/ 1014 1015 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1016 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1017 1018 /* 1019 * Registered Port List Format 1020 */ 1021 struct lpfc_fdmi_reg_port_list { 1022 uint32_t EntryCnt; 1023 uint32_t pe; /* Variable-length array */ 1024 }; 1025 1026 1027 /* Definitions for HBA / Port attribute entries */ 1028 1029 struct lpfc_fdmi_attr_def { /* Defined in TLV format */ 1030 /* Structure is in Big Endian format */ 1031 uint32_t AttrType:16; 1032 uint32_t AttrLen:16; 1033 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */ 1034 }; 1035 1036 1037 /* Attribute Entry */ 1038 struct lpfc_fdmi_attr_entry { 1039 union { 1040 uint32_t VendorSpecific; 1041 uint32_t SupportClass; 1042 uint32_t SupportSpeed; 1043 uint32_t PortSpeed; 1044 uint32_t MaxFrameSize; 1045 uint32_t MaxCTPayloadLen; 1046 uint32_t PortState; 1047 uint32_t PortId; 1048 struct lpfc_name NodeName; 1049 struct lpfc_name PortName; 1050 struct lpfc_name FabricName; 1051 uint8_t FC4Types[32]; 1052 uint8_t Manufacturer[64]; 1053 uint8_t SerialNumber[64]; 1054 uint8_t Model[256]; 1055 uint8_t ModelDescription[256]; 1056 uint8_t HardwareVersion[256]; 1057 uint8_t DriverVersion[256]; 1058 uint8_t OptionROMVersion[256]; 1059 uint8_t FirmwareVersion[256]; 1060 uint8_t OsHostName[256]; 1061 uint8_t NodeSymName[256]; 1062 uint8_t OsDeviceName[256]; 1063 uint8_t OsNameVersion[256]; 1064 uint8_t HostName[256]; 1065 } un; 1066 }; 1067 1068 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry) 1069 1070 /* 1071 * HBA Attribute Block 1072 */ 1073 struct lpfc_fdmi_attr_block { 1074 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1075 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */ 1076 }; 1077 1078 /* 1079 * Port Entry 1080 */ 1081 struct lpfc_fdmi_port_entry { 1082 struct lpfc_name PortName; 1083 }; 1084 1085 /* 1086 * HBA Identifier 1087 */ 1088 struct lpfc_fdmi_hba_ident { 1089 struct lpfc_name PortName; 1090 }; 1091 1092 /* 1093 * Register HBA(RHBA) 1094 */ 1095 struct lpfc_fdmi_reg_hba { 1096 struct lpfc_fdmi_hba_ident hi; 1097 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */ 1098 /* struct lpfc_fdmi_attr_block ab; */ 1099 }; 1100 1101 /* 1102 * Register HBA Attributes (RHAT) 1103 */ 1104 struct lpfc_fdmi_reg_hbaattr { 1105 struct lpfc_name HBA_PortName; 1106 struct lpfc_fdmi_attr_block ab; 1107 }; 1108 1109 /* 1110 * Register Port Attributes (RPA) 1111 */ 1112 struct lpfc_fdmi_reg_portattr { 1113 struct lpfc_name PortName; 1114 struct lpfc_fdmi_attr_block ab; 1115 }; 1116 1117 /* 1118 * HBA MAnagement Operations Command Codes 1119 */ 1120 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1121 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1122 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1123 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1124 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1125 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1126 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1127 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1128 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1129 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1130 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1131 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1132 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1133 1134 /* 1135 * HBA Attribute Types 1136 */ 1137 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1138 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1139 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1140 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1141 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1142 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1143 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1144 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1145 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1146 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1147 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1148 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1149 1150 /* 1151 * Port Attrubute Types 1152 */ 1153 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1154 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1155 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1156 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1157 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1158 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1159 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1160 #define RPRT_PORTNAME 0x8 /* 8 byte WWNN */ 1161 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1162 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1163 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1164 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWNN */ 1165 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1166 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1167 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1168 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1169 1170 /* 1171 * Begin HBA configuration parameters. 1172 * The PCI configuration register BAR assignments are: 1173 * BAR0, offset 0x10 - SLIM base memory address 1174 * BAR1, offset 0x14 - SLIM base memory high address 1175 * BAR2, offset 0x18 - REGISTER base memory address 1176 * BAR3, offset 0x1c - REGISTER base memory high address 1177 * BAR4, offset 0x20 - BIU I/O registers 1178 * BAR5, offset 0x24 - REGISTER base io high address 1179 */ 1180 1181 /* Number of rings currently used and available. */ 1182 #define MAX_SLI3_CONFIGURED_RINGS 3 1183 #define MAX_SLI3_RINGS 4 1184 1185 /* IOCB / Mailbox is owned by FireFly */ 1186 #define OWN_CHIP 1 1187 1188 /* IOCB / Mailbox is owned by Host */ 1189 #define OWN_HOST 0 1190 1191 /* Number of 4-byte words in an IOCB. */ 1192 #define IOCB_WORD_SZ 8 1193 1194 /* network headers for Dfctl field */ 1195 #define FC_NET_HDR 0x20 1196 1197 /* Start FireFly Register definitions */ 1198 #define PCI_VENDOR_ID_EMULEX 0x10df 1199 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1200 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1201 #define PCI_DEVICE_ID_BALIUS 0xe131 1202 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1203 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1204 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1205 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1206 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1207 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1208 #define PCI_DEVICE_ID_SAT_MID 0xf015 1209 #define PCI_DEVICE_ID_RFLY 0xf095 1210 #define PCI_DEVICE_ID_PFLY 0xf098 1211 #define PCI_DEVICE_ID_LP101 0xf0a1 1212 #define PCI_DEVICE_ID_TFLY 0xf0a5 1213 #define PCI_DEVICE_ID_BSMB 0xf0d1 1214 #define PCI_DEVICE_ID_BMID 0xf0d5 1215 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1216 #define PCI_DEVICE_ID_ZMID 0xf0e5 1217 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1218 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1219 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1220 #define PCI_DEVICE_ID_SAT 0xf100 1221 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1222 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1223 #define PCI_DEVICE_ID_FALCON 0xf180 1224 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1225 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1226 #define PCI_DEVICE_ID_CENTAUR 0xf900 1227 #define PCI_DEVICE_ID_PEGASUS 0xf980 1228 #define PCI_DEVICE_ID_THOR 0xfa00 1229 #define PCI_DEVICE_ID_VIPER 0xfb00 1230 #define PCI_DEVICE_ID_LP10000S 0xfc00 1231 #define PCI_DEVICE_ID_LP11000S 0xfc10 1232 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1233 #define PCI_DEVICE_ID_SAT_S 0xfc40 1234 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1235 #define PCI_DEVICE_ID_HELIOS 0xfd00 1236 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1237 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1238 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1239 #define PCI_DEVICE_ID_HORNET 0xfe05 1240 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1241 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1242 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1243 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1244 #define PCI_DEVICE_ID_TOMCAT 0x0714 1245 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1246 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1247 1248 #define JEDEC_ID_ADDRESS 0x0080001c 1249 #define FIREFLY_JEDEC_ID 0x1ACC 1250 #define SUPERFLY_JEDEC_ID 0x0020 1251 #define DRAGONFLY_JEDEC_ID 0x0021 1252 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1253 #define CENTAUR_2G_JEDEC_ID 0x0026 1254 #define CENTAUR_1G_JEDEC_ID 0x0028 1255 #define PEGASUS_ORION_JEDEC_ID 0x0036 1256 #define PEGASUS_JEDEC_ID 0x0038 1257 #define THOR_JEDEC_ID 0x0012 1258 #define HELIOS_JEDEC_ID 0x0364 1259 #define ZEPHYR_JEDEC_ID 0x0577 1260 #define VIPER_JEDEC_ID 0x4838 1261 #define SATURN_JEDEC_ID 0x1004 1262 #define HORNET_JDEC_ID 0x2057706D 1263 1264 #define JEDEC_ID_MASK 0x0FFFF000 1265 #define JEDEC_ID_SHIFT 12 1266 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1267 1268 typedef struct { /* FireFly BIU registers */ 1269 uint32_t hostAtt; /* See definitions for Host Attention 1270 register */ 1271 uint32_t chipAtt; /* See definitions for Chip Attention 1272 register */ 1273 uint32_t hostStatus; /* See definitions for Host Status register */ 1274 uint32_t hostControl; /* See definitions for Host Control register */ 1275 uint32_t buiConfig; /* See definitions for BIU configuration 1276 register */ 1277 } FF_REGS; 1278 1279 /* IO Register size in bytes */ 1280 #define FF_REG_AREA_SIZE 256 1281 1282 /* Host Attention Register */ 1283 1284 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1285 1286 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1287 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1288 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1289 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1290 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1291 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1292 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1293 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1294 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1295 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1296 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1297 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1298 #define HA_LATT 0x20000000 /* Bit 29 */ 1299 #define HA_MBATT 0x40000000 /* Bit 30 */ 1300 #define HA_ERATT 0x80000000 /* Bit 31 */ 1301 1302 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1303 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1304 #define HA_RXATT 0x00000008 /* Bit 3 */ 1305 #define HA_RXMASK 0x0000000f 1306 1307 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1308 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1309 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1310 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1311 1312 #define HA_R0_POS 3 1313 #define HA_R1_POS 7 1314 #define HA_R2_POS 11 1315 #define HA_R3_POS 15 1316 #define HA_LE_POS 29 1317 #define HA_MB_POS 30 1318 #define HA_ER_POS 31 1319 /* Chip Attention Register */ 1320 1321 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1322 1323 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1324 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1325 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1326 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1327 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1328 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1329 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1330 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1331 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1332 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1333 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1334 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1335 #define CA_MBATT 0x40000000 /* Bit 30 */ 1336 1337 /* Host Status Register */ 1338 1339 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1340 1341 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1342 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1343 #define HS_FFER8 0x01000000 /* Bit 24 */ 1344 #define HS_FFER7 0x02000000 /* Bit 25 */ 1345 #define HS_FFER6 0x04000000 /* Bit 26 */ 1346 #define HS_FFER5 0x08000000 /* Bit 27 */ 1347 #define HS_FFER4 0x10000000 /* Bit 28 */ 1348 #define HS_FFER3 0x20000000 /* Bit 29 */ 1349 #define HS_FFER2 0x40000000 /* Bit 30 */ 1350 #define HS_FFER1 0x80000000 /* Bit 31 */ 1351 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1352 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1353 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1354 /* Host Control Register */ 1355 1356 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1357 1358 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1359 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1360 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1361 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1362 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1363 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1364 #define HC_INITMB 0x04000000 /* Bit 26 */ 1365 #define HC_INITFF 0x08000000 /* Bit 27 */ 1366 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1367 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1368 1369 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1370 #define MSIX_DFLT_ID 0 1371 #define MSIX_RNG0_ID 0 1372 #define MSIX_RNG1_ID 1 1373 #define MSIX_RNG2_ID 2 1374 #define MSIX_RNG3_ID 3 1375 1376 #define MSIX_LINK_ID 4 1377 #define MSIX_MBOX_ID 5 1378 1379 #define MSIX_SPARE0_ID 6 1380 #define MSIX_SPARE1_ID 7 1381 1382 /* Mailbox Commands */ 1383 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1384 #define MBX_LOAD_SM 0x01 1385 #define MBX_READ_NV 0x02 1386 #define MBX_WRITE_NV 0x03 1387 #define MBX_RUN_BIU_DIAG 0x04 1388 #define MBX_INIT_LINK 0x05 1389 #define MBX_DOWN_LINK 0x06 1390 #define MBX_CONFIG_LINK 0x07 1391 #define MBX_CONFIG_RING 0x09 1392 #define MBX_RESET_RING 0x0A 1393 #define MBX_READ_CONFIG 0x0B 1394 #define MBX_READ_RCONFIG 0x0C 1395 #define MBX_READ_SPARM 0x0D 1396 #define MBX_READ_STATUS 0x0E 1397 #define MBX_READ_RPI 0x0F 1398 #define MBX_READ_XRI 0x10 1399 #define MBX_READ_REV 0x11 1400 #define MBX_READ_LNK_STAT 0x12 1401 #define MBX_REG_LOGIN 0x13 1402 #define MBX_UNREG_LOGIN 0x14 1403 #define MBX_CLEAR_LA 0x16 1404 #define MBX_DUMP_MEMORY 0x17 1405 #define MBX_DUMP_CONTEXT 0x18 1406 #define MBX_RUN_DIAGS 0x19 1407 #define MBX_RESTART 0x1A 1408 #define MBX_UPDATE_CFG 0x1B 1409 #define MBX_DOWN_LOAD 0x1C 1410 #define MBX_DEL_LD_ENTRY 0x1D 1411 #define MBX_RUN_PROGRAM 0x1E 1412 #define MBX_SET_MASK 0x20 1413 #define MBX_SET_VARIABLE 0x21 1414 #define MBX_UNREG_D_ID 0x23 1415 #define MBX_KILL_BOARD 0x24 1416 #define MBX_CONFIG_FARP 0x25 1417 #define MBX_BEACON 0x2A 1418 #define MBX_CONFIG_MSI 0x30 1419 #define MBX_HEARTBEAT 0x31 1420 #define MBX_WRITE_VPARMS 0x32 1421 #define MBX_ASYNCEVT_ENABLE 0x33 1422 #define MBX_READ_EVENT_LOG_STATUS 0x37 1423 #define MBX_READ_EVENT_LOG 0x38 1424 #define MBX_WRITE_EVENT_LOG 0x39 1425 1426 #define MBX_PORT_CAPABILITIES 0x3B 1427 #define MBX_PORT_IOV_CONTROL 0x3C 1428 1429 #define MBX_CONFIG_HBQ 0x7C 1430 #define MBX_LOAD_AREA 0x81 1431 #define MBX_RUN_BIU_DIAG64 0x84 1432 #define MBX_CONFIG_PORT 0x88 1433 #define MBX_READ_SPARM64 0x8D 1434 #define MBX_READ_RPI64 0x8F 1435 #define MBX_REG_LOGIN64 0x93 1436 #define MBX_READ_TOPOLOGY 0x95 1437 #define MBX_REG_VPI 0x96 1438 #define MBX_UNREG_VPI 0x97 1439 1440 #define MBX_WRITE_WWN 0x98 1441 #define MBX_SET_DEBUG 0x99 1442 #define MBX_LOAD_EXP_ROM 0x9C 1443 #define MBX_SLI4_CONFIG 0x9B 1444 #define MBX_SLI4_REQ_FTRS 0x9D 1445 #define MBX_MAX_CMDS 0x9E 1446 #define MBX_RESUME_RPI 0x9E 1447 #define MBX_SLI2_CMD_MASK 0x80 1448 #define MBX_REG_VFI 0x9F 1449 #define MBX_REG_FCFI 0xA0 1450 #define MBX_UNREG_VFI 0xA1 1451 #define MBX_UNREG_FCFI 0xA2 1452 #define MBX_INIT_VFI 0xA3 1453 #define MBX_INIT_VPI 0xA4 1454 #define MBX_ACCESS_VDATA 0xA5 1455 1456 #define MBX_AUTH_PORT 0xF8 1457 #define MBX_SECURITY_MGMT 0xF9 1458 1459 /* IOCB Commands */ 1460 1461 #define CMD_RCV_SEQUENCE_CX 0x01 1462 #define CMD_XMIT_SEQUENCE_CR 0x02 1463 #define CMD_XMIT_SEQUENCE_CX 0x03 1464 #define CMD_XMIT_BCAST_CN 0x04 1465 #define CMD_XMIT_BCAST_CX 0x05 1466 #define CMD_QUE_RING_BUF_CN 0x06 1467 #define CMD_QUE_XRI_BUF_CX 0x07 1468 #define CMD_IOCB_CONTINUE_CN 0x08 1469 #define CMD_RET_XRI_BUF_CX 0x09 1470 #define CMD_ELS_REQUEST_CR 0x0A 1471 #define CMD_ELS_REQUEST_CX 0x0B 1472 #define CMD_RCV_ELS_REQ_CX 0x0D 1473 #define CMD_ABORT_XRI_CN 0x0E 1474 #define CMD_ABORT_XRI_CX 0x0F 1475 #define CMD_CLOSE_XRI_CN 0x10 1476 #define CMD_CLOSE_XRI_CX 0x11 1477 #define CMD_CREATE_XRI_CR 0x12 1478 #define CMD_CREATE_XRI_CX 0x13 1479 #define CMD_GET_RPI_CN 0x14 1480 #define CMD_XMIT_ELS_RSP_CX 0x15 1481 #define CMD_GET_RPI_CR 0x16 1482 #define CMD_XRI_ABORTED_CX 0x17 1483 #define CMD_FCP_IWRITE_CR 0x18 1484 #define CMD_FCP_IWRITE_CX 0x19 1485 #define CMD_FCP_IREAD_CR 0x1A 1486 #define CMD_FCP_IREAD_CX 0x1B 1487 #define CMD_FCP_ICMND_CR 0x1C 1488 #define CMD_FCP_ICMND_CX 0x1D 1489 #define CMD_FCP_TSEND_CX 0x1F 1490 #define CMD_FCP_TRECEIVE_CX 0x21 1491 #define CMD_FCP_TRSP_CX 0x23 1492 #define CMD_FCP_AUTO_TRSP_CX 0x29 1493 1494 #define CMD_ADAPTER_MSG 0x20 1495 #define CMD_ADAPTER_DUMP 0x22 1496 1497 /* SLI_2 IOCB Command Set */ 1498 1499 #define CMD_ASYNC_STATUS 0x7C 1500 #define CMD_RCV_SEQUENCE64_CX 0x81 1501 #define CMD_XMIT_SEQUENCE64_CR 0x82 1502 #define CMD_XMIT_SEQUENCE64_CX 0x83 1503 #define CMD_XMIT_BCAST64_CN 0x84 1504 #define CMD_XMIT_BCAST64_CX 0x85 1505 #define CMD_QUE_RING_BUF64_CN 0x86 1506 #define CMD_QUE_XRI_BUF64_CX 0x87 1507 #define CMD_IOCB_CONTINUE64_CN 0x88 1508 #define CMD_RET_XRI_BUF64_CX 0x89 1509 #define CMD_ELS_REQUEST64_CR 0x8A 1510 #define CMD_ELS_REQUEST64_CX 0x8B 1511 #define CMD_ABORT_MXRI64_CN 0x8C 1512 #define CMD_RCV_ELS_REQ64_CX 0x8D 1513 #define CMD_XMIT_ELS_RSP64_CX 0x95 1514 #define CMD_XMIT_BLS_RSP64_CX 0x97 1515 #define CMD_FCP_IWRITE64_CR 0x98 1516 #define CMD_FCP_IWRITE64_CX 0x99 1517 #define CMD_FCP_IREAD64_CR 0x9A 1518 #define CMD_FCP_IREAD64_CX 0x9B 1519 #define CMD_FCP_ICMND64_CR 0x9C 1520 #define CMD_FCP_ICMND64_CX 0x9D 1521 #define CMD_FCP_TSEND64_CX 0x9F 1522 #define CMD_FCP_TRECEIVE64_CX 0xA1 1523 #define CMD_FCP_TRSP64_CX 0xA3 1524 1525 #define CMD_QUE_XRI64_CX 0xB3 1526 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1527 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1528 #define CMD_IOCB_RET_XRI64_CX 0xB9 1529 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1530 1531 #define CMD_GEN_REQUEST64_CR 0xC2 1532 #define CMD_GEN_REQUEST64_CX 0xC3 1533 1534 /* Unhandled SLI-3 Commands */ 1535 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1536 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1537 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1538 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1539 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1540 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1541 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1542 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1543 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1544 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1545 #define CMD_IOCB_LOGENTRY_CN 0x94 1546 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1547 1548 /* Data Security SLI Commands */ 1549 #define DSSCMD_IWRITE64_CR 0xF8 1550 #define DSSCMD_IWRITE64_CX 0xF9 1551 #define DSSCMD_IREAD64_CR 0xFA 1552 #define DSSCMD_IREAD64_CX 0xFB 1553 1554 #define CMD_MAX_IOCB_CMD 0xFB 1555 #define CMD_IOCB_MASK 0xff 1556 1557 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1558 iocb */ 1559 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1560 /* 1561 * Define Status 1562 */ 1563 #define MBX_SUCCESS 0 1564 #define MBXERR_NUM_RINGS 1 1565 #define MBXERR_NUM_IOCBS 2 1566 #define MBXERR_IOCBS_EXCEEDED 3 1567 #define MBXERR_BAD_RING_NUMBER 4 1568 #define MBXERR_MASK_ENTRIES_RANGE 5 1569 #define MBXERR_MASKS_EXCEEDED 6 1570 #define MBXERR_BAD_PROFILE 7 1571 #define MBXERR_BAD_DEF_CLASS 8 1572 #define MBXERR_BAD_MAX_RESPONDER 9 1573 #define MBXERR_BAD_MAX_ORIGINATOR 10 1574 #define MBXERR_RPI_REGISTERED 11 1575 #define MBXERR_RPI_FULL 12 1576 #define MBXERR_NO_RESOURCES 13 1577 #define MBXERR_BAD_RCV_LENGTH 14 1578 #define MBXERR_DMA_ERROR 15 1579 #define MBXERR_ERROR 16 1580 #define MBXERR_LINK_DOWN 0x33 1581 #define MBXERR_SEC_NO_PERMISSION 0xF02 1582 #define MBX_NOT_FINISHED 255 1583 1584 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1585 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1586 1587 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1588 1589 /* 1590 * Begin Structure Definitions for Mailbox Commands 1591 */ 1592 1593 typedef struct { 1594 #ifdef __BIG_ENDIAN_BITFIELD 1595 uint8_t tval; 1596 uint8_t tmask; 1597 uint8_t rval; 1598 uint8_t rmask; 1599 #else /* __LITTLE_ENDIAN_BITFIELD */ 1600 uint8_t rmask; 1601 uint8_t rval; 1602 uint8_t tmask; 1603 uint8_t tval; 1604 #endif 1605 } RR_REG; 1606 1607 struct ulp_bde { 1608 uint32_t bdeAddress; 1609 #ifdef __BIG_ENDIAN_BITFIELD 1610 uint32_t bdeReserved:4; 1611 uint32_t bdeAddrHigh:4; 1612 uint32_t bdeSize:24; 1613 #else /* __LITTLE_ENDIAN_BITFIELD */ 1614 uint32_t bdeSize:24; 1615 uint32_t bdeAddrHigh:4; 1616 uint32_t bdeReserved:4; 1617 #endif 1618 }; 1619 1620 typedef struct ULP_BDL { /* SLI-2 */ 1621 #ifdef __BIG_ENDIAN_BITFIELD 1622 uint32_t bdeFlags:8; /* BDL Flags */ 1623 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1624 #else /* __LITTLE_ENDIAN_BITFIELD */ 1625 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1626 uint32_t bdeFlags:8; /* BDL Flags */ 1627 #endif 1628 1629 uint32_t addrLow; /* Address 0:31 */ 1630 uint32_t addrHigh; /* Address 32:63 */ 1631 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1632 } ULP_BDL; 1633 1634 /* 1635 * BlockGuard Definitions 1636 */ 1637 1638 enum lpfc_protgrp_type { 1639 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1640 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1641 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1642 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1643 }; 1644 1645 /* PDE Descriptors */ 1646 #define LPFC_PDE5_DESCRIPTOR 0x85 1647 #define LPFC_PDE6_DESCRIPTOR 0x86 1648 #define LPFC_PDE7_DESCRIPTOR 0x87 1649 1650 /* BlockGuard Opcodes */ 1651 #define BG_OP_IN_NODIF_OUT_CRC 0x0 1652 #define BG_OP_IN_CRC_OUT_NODIF 0x1 1653 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 1654 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 1655 #define BG_OP_IN_CRC_OUT_CRC 0x4 1656 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 1657 #define BG_OP_IN_CRC_OUT_CSUM 0x6 1658 #define BG_OP_IN_CSUM_OUT_CRC 0x7 1659 #define BG_OP_RAW_MODE 0x8 1660 1661 struct lpfc_pde5 { 1662 uint32_t word0; 1663 #define pde5_type_SHIFT 24 1664 #define pde5_type_MASK 0x000000ff 1665 #define pde5_type_WORD word0 1666 #define pde5_rsvd0_SHIFT 0 1667 #define pde5_rsvd0_MASK 0x00ffffff 1668 #define pde5_rsvd0_WORD word0 1669 uint32_t reftag; /* Reference Tag Value */ 1670 uint32_t reftagtr; /* Reference Tag Translation Value */ 1671 }; 1672 1673 struct lpfc_pde6 { 1674 uint32_t word0; 1675 #define pde6_type_SHIFT 24 1676 #define pde6_type_MASK 0x000000ff 1677 #define pde6_type_WORD word0 1678 #define pde6_rsvd0_SHIFT 0 1679 #define pde6_rsvd0_MASK 0x00ffffff 1680 #define pde6_rsvd0_WORD word0 1681 uint32_t word1; 1682 #define pde6_rsvd1_SHIFT 26 1683 #define pde6_rsvd1_MASK 0x0000003f 1684 #define pde6_rsvd1_WORD word1 1685 #define pde6_na_SHIFT 25 1686 #define pde6_na_MASK 0x00000001 1687 #define pde6_na_WORD word1 1688 #define pde6_rsvd2_SHIFT 16 1689 #define pde6_rsvd2_MASK 0x000001FF 1690 #define pde6_rsvd2_WORD word1 1691 #define pde6_apptagtr_SHIFT 0 1692 #define pde6_apptagtr_MASK 0x0000ffff 1693 #define pde6_apptagtr_WORD word1 1694 uint32_t word2; 1695 #define pde6_optx_SHIFT 28 1696 #define pde6_optx_MASK 0x0000000f 1697 #define pde6_optx_WORD word2 1698 #define pde6_oprx_SHIFT 24 1699 #define pde6_oprx_MASK 0x0000000f 1700 #define pde6_oprx_WORD word2 1701 #define pde6_nr_SHIFT 23 1702 #define pde6_nr_MASK 0x00000001 1703 #define pde6_nr_WORD word2 1704 #define pde6_ce_SHIFT 22 1705 #define pde6_ce_MASK 0x00000001 1706 #define pde6_ce_WORD word2 1707 #define pde6_re_SHIFT 21 1708 #define pde6_re_MASK 0x00000001 1709 #define pde6_re_WORD word2 1710 #define pde6_ae_SHIFT 20 1711 #define pde6_ae_MASK 0x00000001 1712 #define pde6_ae_WORD word2 1713 #define pde6_ai_SHIFT 19 1714 #define pde6_ai_MASK 0x00000001 1715 #define pde6_ai_WORD word2 1716 #define pde6_bs_SHIFT 16 1717 #define pde6_bs_MASK 0x00000007 1718 #define pde6_bs_WORD word2 1719 #define pde6_apptagval_SHIFT 0 1720 #define pde6_apptagval_MASK 0x0000ffff 1721 #define pde6_apptagval_WORD word2 1722 }; 1723 1724 struct lpfc_pde7 { 1725 uint32_t word0; 1726 #define pde7_type_SHIFT 24 1727 #define pde7_type_MASK 0x000000ff 1728 #define pde7_type_WORD word0 1729 #define pde7_rsvd0_SHIFT 0 1730 #define pde7_rsvd0_MASK 0x00ffffff 1731 #define pde7_rsvd0_WORD word0 1732 uint32_t addrHigh; 1733 uint32_t addrLow; 1734 }; 1735 1736 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 1737 1738 typedef struct { 1739 #ifdef __BIG_ENDIAN_BITFIELD 1740 uint32_t rsvd2:25; 1741 uint32_t acknowledgment:1; 1742 uint32_t version:1; 1743 uint32_t erase_or_prog:1; 1744 uint32_t update_flash:1; 1745 uint32_t update_ram:1; 1746 uint32_t method:1; 1747 uint32_t load_cmplt:1; 1748 #else /* __LITTLE_ENDIAN_BITFIELD */ 1749 uint32_t load_cmplt:1; 1750 uint32_t method:1; 1751 uint32_t update_ram:1; 1752 uint32_t update_flash:1; 1753 uint32_t erase_or_prog:1; 1754 uint32_t version:1; 1755 uint32_t acknowledgment:1; 1756 uint32_t rsvd2:25; 1757 #endif 1758 1759 uint32_t dl_to_adr_low; 1760 uint32_t dl_to_adr_high; 1761 uint32_t dl_len; 1762 union { 1763 uint32_t dl_from_mbx_offset; 1764 struct ulp_bde dl_from_bde; 1765 struct ulp_bde64 dl_from_bde64; 1766 } un; 1767 1768 } LOAD_SM_VAR; 1769 1770 /* Structure for MB Command READ_NVPARM (02) */ 1771 1772 typedef struct { 1773 uint32_t rsvd1[3]; /* Read as all one's */ 1774 uint32_t rsvd2; /* Read as all zero's */ 1775 uint32_t portname[2]; /* N_PORT name */ 1776 uint32_t nodename[2]; /* NODE name */ 1777 1778 #ifdef __BIG_ENDIAN_BITFIELD 1779 uint32_t pref_DID:24; 1780 uint32_t hardAL_PA:8; 1781 #else /* __LITTLE_ENDIAN_BITFIELD */ 1782 uint32_t hardAL_PA:8; 1783 uint32_t pref_DID:24; 1784 #endif 1785 1786 uint32_t rsvd3[21]; /* Read as all one's */ 1787 } READ_NV_VAR; 1788 1789 /* Structure for MB Command WRITE_NVPARMS (03) */ 1790 1791 typedef struct { 1792 uint32_t rsvd1[3]; /* Must be all one's */ 1793 uint32_t rsvd2; /* Must be all zero's */ 1794 uint32_t portname[2]; /* N_PORT name */ 1795 uint32_t nodename[2]; /* NODE name */ 1796 1797 #ifdef __BIG_ENDIAN_BITFIELD 1798 uint32_t pref_DID:24; 1799 uint32_t hardAL_PA:8; 1800 #else /* __LITTLE_ENDIAN_BITFIELD */ 1801 uint32_t hardAL_PA:8; 1802 uint32_t pref_DID:24; 1803 #endif 1804 1805 uint32_t rsvd3[21]; /* Must be all one's */ 1806 } WRITE_NV_VAR; 1807 1808 /* Structure for MB Command RUN_BIU_DIAG (04) */ 1809 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 1810 1811 typedef struct { 1812 uint32_t rsvd1; 1813 union { 1814 struct { 1815 struct ulp_bde xmit_bde; 1816 struct ulp_bde rcv_bde; 1817 } s1; 1818 struct { 1819 struct ulp_bde64 xmit_bde64; 1820 struct ulp_bde64 rcv_bde64; 1821 } s2; 1822 } un; 1823 } BIU_DIAG_VAR; 1824 1825 /* Structure for MB command READ_EVENT_LOG (0x38) */ 1826 struct READ_EVENT_LOG_VAR { 1827 uint32_t word1; 1828 #define lpfc_event_log_SHIFT 29 1829 #define lpfc_event_log_MASK 0x00000001 1830 #define lpfc_event_log_WORD word1 1831 #define USE_MAILBOX_RESPONSE 1 1832 uint32_t offset; 1833 struct ulp_bde64 rcv_bde64; 1834 }; 1835 1836 /* Structure for MB Command INIT_LINK (05) */ 1837 1838 typedef struct { 1839 #ifdef __BIG_ENDIAN_BITFIELD 1840 uint32_t rsvd1:24; 1841 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1842 #else /* __LITTLE_ENDIAN_BITFIELD */ 1843 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 1844 uint32_t rsvd1:24; 1845 #endif 1846 1847 #ifdef __BIG_ENDIAN_BITFIELD 1848 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1849 uint8_t rsvd2; 1850 uint16_t link_flags; 1851 #else /* __LITTLE_ENDIAN_BITFIELD */ 1852 uint16_t link_flags; 1853 uint8_t rsvd2; 1854 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 1855 #endif 1856 1857 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 1858 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 1859 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 1860 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 1861 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 1862 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 1863 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 1864 1865 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 1866 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 1867 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 1868 1869 uint32_t link_speed; 1870 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 1871 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 1872 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 1873 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 1874 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 1875 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 1876 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 1877 1878 } INIT_LINK_VAR; 1879 1880 /* Structure for MB Command DOWN_LINK (06) */ 1881 1882 typedef struct { 1883 uint32_t rsvd1; 1884 } DOWN_LINK_VAR; 1885 1886 /* Structure for MB Command CONFIG_LINK (07) */ 1887 1888 typedef struct { 1889 #ifdef __BIG_ENDIAN_BITFIELD 1890 uint32_t cr:1; 1891 uint32_t ci:1; 1892 uint32_t cr_delay:6; 1893 uint32_t cr_count:8; 1894 uint32_t rsvd1:8; 1895 uint32_t MaxBBC:8; 1896 #else /* __LITTLE_ENDIAN_BITFIELD */ 1897 uint32_t MaxBBC:8; 1898 uint32_t rsvd1:8; 1899 uint32_t cr_count:8; 1900 uint32_t cr_delay:6; 1901 uint32_t ci:1; 1902 uint32_t cr:1; 1903 #endif 1904 1905 uint32_t myId; 1906 uint32_t rsvd2; 1907 uint32_t edtov; 1908 uint32_t arbtov; 1909 uint32_t ratov; 1910 uint32_t rttov; 1911 uint32_t altov; 1912 uint32_t crtov; 1913 uint32_t citov; 1914 #ifdef __BIG_ENDIAN_BITFIELD 1915 uint32_t rrq_enable:1; 1916 uint32_t rrq_immed:1; 1917 uint32_t rsvd4:29; 1918 uint32_t ack0_enable:1; 1919 #else /* __LITTLE_ENDIAN_BITFIELD */ 1920 uint32_t ack0_enable:1; 1921 uint32_t rsvd4:29; 1922 uint32_t rrq_immed:1; 1923 uint32_t rrq_enable:1; 1924 #endif 1925 } CONFIG_LINK; 1926 1927 /* Structure for MB Command PART_SLIM (08) 1928 * will be removed since SLI1 is no longer supported! 1929 */ 1930 typedef struct { 1931 #ifdef __BIG_ENDIAN_BITFIELD 1932 uint16_t offCiocb; 1933 uint16_t numCiocb; 1934 uint16_t offRiocb; 1935 uint16_t numRiocb; 1936 #else /* __LITTLE_ENDIAN_BITFIELD */ 1937 uint16_t numCiocb; 1938 uint16_t offCiocb; 1939 uint16_t numRiocb; 1940 uint16_t offRiocb; 1941 #endif 1942 } RING_DEF; 1943 1944 typedef struct { 1945 #ifdef __BIG_ENDIAN_BITFIELD 1946 uint32_t unused1:24; 1947 uint32_t numRing:8; 1948 #else /* __LITTLE_ENDIAN_BITFIELD */ 1949 uint32_t numRing:8; 1950 uint32_t unused1:24; 1951 #endif 1952 1953 RING_DEF ringdef[4]; 1954 uint32_t hbainit; 1955 } PART_SLIM_VAR; 1956 1957 /* Structure for MB Command CONFIG_RING (09) */ 1958 1959 typedef struct { 1960 #ifdef __BIG_ENDIAN_BITFIELD 1961 uint32_t unused2:6; 1962 uint32_t recvSeq:1; 1963 uint32_t recvNotify:1; 1964 uint32_t numMask:8; 1965 uint32_t profile:8; 1966 uint32_t unused1:4; 1967 uint32_t ring:4; 1968 #else /* __LITTLE_ENDIAN_BITFIELD */ 1969 uint32_t ring:4; 1970 uint32_t unused1:4; 1971 uint32_t profile:8; 1972 uint32_t numMask:8; 1973 uint32_t recvNotify:1; 1974 uint32_t recvSeq:1; 1975 uint32_t unused2:6; 1976 #endif 1977 1978 #ifdef __BIG_ENDIAN_BITFIELD 1979 uint16_t maxRespXchg; 1980 uint16_t maxOrigXchg; 1981 #else /* __LITTLE_ENDIAN_BITFIELD */ 1982 uint16_t maxOrigXchg; 1983 uint16_t maxRespXchg; 1984 #endif 1985 1986 RR_REG rrRegs[6]; 1987 } CONFIG_RING_VAR; 1988 1989 /* Structure for MB Command RESET_RING (10) */ 1990 1991 typedef struct { 1992 uint32_t ring_no; 1993 } RESET_RING_VAR; 1994 1995 /* Structure for MB Command READ_CONFIG (11) */ 1996 1997 typedef struct { 1998 #ifdef __BIG_ENDIAN_BITFIELD 1999 uint32_t cr:1; 2000 uint32_t ci:1; 2001 uint32_t cr_delay:6; 2002 uint32_t cr_count:8; 2003 uint32_t InitBBC:8; 2004 uint32_t MaxBBC:8; 2005 #else /* __LITTLE_ENDIAN_BITFIELD */ 2006 uint32_t MaxBBC:8; 2007 uint32_t InitBBC:8; 2008 uint32_t cr_count:8; 2009 uint32_t cr_delay:6; 2010 uint32_t ci:1; 2011 uint32_t cr:1; 2012 #endif 2013 2014 #ifdef __BIG_ENDIAN_BITFIELD 2015 uint32_t topology:8; 2016 uint32_t myDid:24; 2017 #else /* __LITTLE_ENDIAN_BITFIELD */ 2018 uint32_t myDid:24; 2019 uint32_t topology:8; 2020 #endif 2021 2022 /* Defines for topology (defined previously) */ 2023 #ifdef __BIG_ENDIAN_BITFIELD 2024 uint32_t AR:1; 2025 uint32_t IR:1; 2026 uint32_t rsvd1:29; 2027 uint32_t ack0:1; 2028 #else /* __LITTLE_ENDIAN_BITFIELD */ 2029 uint32_t ack0:1; 2030 uint32_t rsvd1:29; 2031 uint32_t IR:1; 2032 uint32_t AR:1; 2033 #endif 2034 2035 uint32_t edtov; 2036 uint32_t arbtov; 2037 uint32_t ratov; 2038 uint32_t rttov; 2039 uint32_t altov; 2040 uint32_t lmt; 2041 #define LMT_RESERVED 0x000 /* Not used */ 2042 #define LMT_1Gb 0x004 2043 #define LMT_2Gb 0x008 2044 #define LMT_4Gb 0x040 2045 #define LMT_8Gb 0x080 2046 #define LMT_10Gb 0x100 2047 #define LMT_16Gb 0x200 2048 uint32_t rsvd2; 2049 uint32_t rsvd3; 2050 uint32_t max_xri; 2051 uint32_t max_iocb; 2052 uint32_t max_rpi; 2053 uint32_t avail_xri; 2054 uint32_t avail_iocb; 2055 uint32_t avail_rpi; 2056 uint32_t max_vpi; 2057 uint32_t rsvd4; 2058 uint32_t rsvd5; 2059 uint32_t avail_vpi; 2060 } READ_CONFIG_VAR; 2061 2062 /* Structure for MB Command READ_RCONFIG (12) */ 2063 2064 typedef struct { 2065 #ifdef __BIG_ENDIAN_BITFIELD 2066 uint32_t rsvd2:7; 2067 uint32_t recvNotify:1; 2068 uint32_t numMask:8; 2069 uint32_t profile:8; 2070 uint32_t rsvd1:4; 2071 uint32_t ring:4; 2072 #else /* __LITTLE_ENDIAN_BITFIELD */ 2073 uint32_t ring:4; 2074 uint32_t rsvd1:4; 2075 uint32_t profile:8; 2076 uint32_t numMask:8; 2077 uint32_t recvNotify:1; 2078 uint32_t rsvd2:7; 2079 #endif 2080 2081 #ifdef __BIG_ENDIAN_BITFIELD 2082 uint16_t maxResp; 2083 uint16_t maxOrig; 2084 #else /* __LITTLE_ENDIAN_BITFIELD */ 2085 uint16_t maxOrig; 2086 uint16_t maxResp; 2087 #endif 2088 2089 RR_REG rrRegs[6]; 2090 2091 #ifdef __BIG_ENDIAN_BITFIELD 2092 uint16_t cmdRingOffset; 2093 uint16_t cmdEntryCnt; 2094 uint16_t rspRingOffset; 2095 uint16_t rspEntryCnt; 2096 uint16_t nextCmdOffset; 2097 uint16_t rsvd3; 2098 uint16_t nextRspOffset; 2099 uint16_t rsvd4; 2100 #else /* __LITTLE_ENDIAN_BITFIELD */ 2101 uint16_t cmdEntryCnt; 2102 uint16_t cmdRingOffset; 2103 uint16_t rspEntryCnt; 2104 uint16_t rspRingOffset; 2105 uint16_t rsvd3; 2106 uint16_t nextCmdOffset; 2107 uint16_t rsvd4; 2108 uint16_t nextRspOffset; 2109 #endif 2110 } READ_RCONF_VAR; 2111 2112 /* Structure for MB Command READ_SPARM (13) */ 2113 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2114 2115 typedef struct { 2116 uint32_t rsvd1; 2117 uint32_t rsvd2; 2118 union { 2119 struct ulp_bde sp; /* This BDE points to struct serv_parm 2120 structure */ 2121 struct ulp_bde64 sp64; 2122 } un; 2123 #ifdef __BIG_ENDIAN_BITFIELD 2124 uint16_t rsvd3; 2125 uint16_t vpi; 2126 #else /* __LITTLE_ENDIAN_BITFIELD */ 2127 uint16_t vpi; 2128 uint16_t rsvd3; 2129 #endif 2130 } READ_SPARM_VAR; 2131 2132 /* Structure for MB Command READ_STATUS (14) */ 2133 2134 typedef struct { 2135 #ifdef __BIG_ENDIAN_BITFIELD 2136 uint32_t rsvd1:31; 2137 uint32_t clrCounters:1; 2138 uint16_t activeXriCnt; 2139 uint16_t activeRpiCnt; 2140 #else /* __LITTLE_ENDIAN_BITFIELD */ 2141 uint32_t clrCounters:1; 2142 uint32_t rsvd1:31; 2143 uint16_t activeRpiCnt; 2144 uint16_t activeXriCnt; 2145 #endif 2146 2147 uint32_t xmitByteCnt; 2148 uint32_t rcvByteCnt; 2149 uint32_t xmitFrameCnt; 2150 uint32_t rcvFrameCnt; 2151 uint32_t xmitSeqCnt; 2152 uint32_t rcvSeqCnt; 2153 uint32_t totalOrigExchanges; 2154 uint32_t totalRespExchanges; 2155 uint32_t rcvPbsyCnt; 2156 uint32_t rcvFbsyCnt; 2157 } READ_STATUS_VAR; 2158 2159 /* Structure for MB Command READ_RPI (15) */ 2160 /* Structure for MB Command READ_RPI64 (0x8F) */ 2161 2162 typedef struct { 2163 #ifdef __BIG_ENDIAN_BITFIELD 2164 uint16_t nextRpi; 2165 uint16_t reqRpi; 2166 uint32_t rsvd2:8; 2167 uint32_t DID:24; 2168 #else /* __LITTLE_ENDIAN_BITFIELD */ 2169 uint16_t reqRpi; 2170 uint16_t nextRpi; 2171 uint32_t DID:24; 2172 uint32_t rsvd2:8; 2173 #endif 2174 2175 union { 2176 struct ulp_bde sp; 2177 struct ulp_bde64 sp64; 2178 } un; 2179 2180 } READ_RPI_VAR; 2181 2182 /* Structure for MB Command READ_XRI (16) */ 2183 2184 typedef struct { 2185 #ifdef __BIG_ENDIAN_BITFIELD 2186 uint16_t nextXri; 2187 uint16_t reqXri; 2188 uint16_t rsvd1; 2189 uint16_t rpi; 2190 uint32_t rsvd2:8; 2191 uint32_t DID:24; 2192 uint32_t rsvd3:8; 2193 uint32_t SID:24; 2194 uint32_t rsvd4; 2195 uint8_t seqId; 2196 uint8_t rsvd5; 2197 uint16_t seqCount; 2198 uint16_t oxId; 2199 uint16_t rxId; 2200 uint32_t rsvd6:30; 2201 uint32_t si:1; 2202 uint32_t exchOrig:1; 2203 #else /* __LITTLE_ENDIAN_BITFIELD */ 2204 uint16_t reqXri; 2205 uint16_t nextXri; 2206 uint16_t rpi; 2207 uint16_t rsvd1; 2208 uint32_t DID:24; 2209 uint32_t rsvd2:8; 2210 uint32_t SID:24; 2211 uint32_t rsvd3:8; 2212 uint32_t rsvd4; 2213 uint16_t seqCount; 2214 uint8_t rsvd5; 2215 uint8_t seqId; 2216 uint16_t rxId; 2217 uint16_t oxId; 2218 uint32_t exchOrig:1; 2219 uint32_t si:1; 2220 uint32_t rsvd6:30; 2221 #endif 2222 } READ_XRI_VAR; 2223 2224 /* Structure for MB Command READ_REV (17) */ 2225 2226 typedef struct { 2227 #ifdef __BIG_ENDIAN_BITFIELD 2228 uint32_t cv:1; 2229 uint32_t rr:1; 2230 uint32_t rsvd2:2; 2231 uint32_t v3req:1; 2232 uint32_t v3rsp:1; 2233 uint32_t rsvd1:25; 2234 uint32_t rv:1; 2235 #else /* __LITTLE_ENDIAN_BITFIELD */ 2236 uint32_t rv:1; 2237 uint32_t rsvd1:25; 2238 uint32_t v3rsp:1; 2239 uint32_t v3req:1; 2240 uint32_t rsvd2:2; 2241 uint32_t rr:1; 2242 uint32_t cv:1; 2243 #endif 2244 2245 uint32_t biuRev; 2246 uint32_t smRev; 2247 union { 2248 uint32_t smFwRev; 2249 struct { 2250 #ifdef __BIG_ENDIAN_BITFIELD 2251 uint8_t ProgType; 2252 uint8_t ProgId; 2253 uint16_t ProgVer:4; 2254 uint16_t ProgRev:4; 2255 uint16_t ProgFixLvl:2; 2256 uint16_t ProgDistType:2; 2257 uint16_t DistCnt:4; 2258 #else /* __LITTLE_ENDIAN_BITFIELD */ 2259 uint16_t DistCnt:4; 2260 uint16_t ProgDistType:2; 2261 uint16_t ProgFixLvl:2; 2262 uint16_t ProgRev:4; 2263 uint16_t ProgVer:4; 2264 uint8_t ProgId; 2265 uint8_t ProgType; 2266 #endif 2267 2268 } b; 2269 } un; 2270 uint32_t endecRev; 2271 #ifdef __BIG_ENDIAN_BITFIELD 2272 uint8_t feaLevelHigh; 2273 uint8_t feaLevelLow; 2274 uint8_t fcphHigh; 2275 uint8_t fcphLow; 2276 #else /* __LITTLE_ENDIAN_BITFIELD */ 2277 uint8_t fcphLow; 2278 uint8_t fcphHigh; 2279 uint8_t feaLevelLow; 2280 uint8_t feaLevelHigh; 2281 #endif 2282 2283 uint32_t postKernRev; 2284 uint32_t opFwRev; 2285 uint8_t opFwName[16]; 2286 uint32_t sli1FwRev; 2287 uint8_t sli1FwName[16]; 2288 uint32_t sli2FwRev; 2289 uint8_t sli2FwName[16]; 2290 uint32_t sli3Feat; 2291 uint32_t RandomData[6]; 2292 } READ_REV_VAR; 2293 2294 /* Structure for MB Command READ_LINK_STAT (18) */ 2295 2296 typedef struct { 2297 uint32_t rsvd1; 2298 uint32_t linkFailureCnt; 2299 uint32_t lossSyncCnt; 2300 2301 uint32_t lossSignalCnt; 2302 uint32_t primSeqErrCnt; 2303 uint32_t invalidXmitWord; 2304 uint32_t crcCnt; 2305 uint32_t primSeqTimeout; 2306 uint32_t elasticOverrun; 2307 uint32_t arbTimeout; 2308 } READ_LNK_VAR; 2309 2310 /* Structure for MB Command REG_LOGIN (19) */ 2311 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2312 2313 typedef struct { 2314 #ifdef __BIG_ENDIAN_BITFIELD 2315 uint16_t rsvd1; 2316 uint16_t rpi; 2317 uint32_t rsvd2:8; 2318 uint32_t did:24; 2319 #else /* __LITTLE_ENDIAN_BITFIELD */ 2320 uint16_t rpi; 2321 uint16_t rsvd1; 2322 uint32_t did:24; 2323 uint32_t rsvd2:8; 2324 #endif 2325 2326 union { 2327 struct ulp_bde sp; 2328 struct ulp_bde64 sp64; 2329 } un; 2330 2331 #ifdef __BIG_ENDIAN_BITFIELD 2332 uint16_t rsvd6; 2333 uint16_t vpi; 2334 #else /* __LITTLE_ENDIAN_BITFIELD */ 2335 uint16_t vpi; 2336 uint16_t rsvd6; 2337 #endif 2338 2339 } REG_LOGIN_VAR; 2340 2341 /* Word 30 contents for REG_LOGIN */ 2342 typedef union { 2343 struct { 2344 #ifdef __BIG_ENDIAN_BITFIELD 2345 uint16_t rsvd1:12; 2346 uint16_t wd30_class:4; 2347 uint16_t xri; 2348 #else /* __LITTLE_ENDIAN_BITFIELD */ 2349 uint16_t xri; 2350 uint16_t wd30_class:4; 2351 uint16_t rsvd1:12; 2352 #endif 2353 } f; 2354 uint32_t word; 2355 } REG_WD30; 2356 2357 /* Structure for MB Command UNREG_LOGIN (20) */ 2358 2359 typedef struct { 2360 #ifdef __BIG_ENDIAN_BITFIELD 2361 uint16_t rsvd1; 2362 uint16_t rpi; 2363 uint32_t rsvd2; 2364 uint32_t rsvd3; 2365 uint32_t rsvd4; 2366 uint32_t rsvd5; 2367 uint16_t rsvd6; 2368 uint16_t vpi; 2369 #else /* __LITTLE_ENDIAN_BITFIELD */ 2370 uint16_t rpi; 2371 uint16_t rsvd1; 2372 uint32_t rsvd2; 2373 uint32_t rsvd3; 2374 uint32_t rsvd4; 2375 uint32_t rsvd5; 2376 uint16_t vpi; 2377 uint16_t rsvd6; 2378 #endif 2379 } UNREG_LOGIN_VAR; 2380 2381 /* Structure for MB Command REG_VPI (0x96) */ 2382 typedef struct { 2383 #ifdef __BIG_ENDIAN_BITFIELD 2384 uint32_t rsvd1; 2385 uint32_t rsvd2:7; 2386 uint32_t upd:1; 2387 uint32_t sid:24; 2388 uint32_t wwn[2]; 2389 uint32_t rsvd5; 2390 uint16_t vfi; 2391 uint16_t vpi; 2392 #else /* __LITTLE_ENDIAN */ 2393 uint32_t rsvd1; 2394 uint32_t sid:24; 2395 uint32_t upd:1; 2396 uint32_t rsvd2:7; 2397 uint32_t wwn[2]; 2398 uint32_t rsvd5; 2399 uint16_t vpi; 2400 uint16_t vfi; 2401 #endif 2402 } REG_VPI_VAR; 2403 2404 /* Structure for MB Command UNREG_VPI (0x97) */ 2405 typedef struct { 2406 uint32_t rsvd1; 2407 #ifdef __BIG_ENDIAN_BITFIELD 2408 uint16_t rsvd2; 2409 uint16_t sli4_vpi; 2410 #else /* __LITTLE_ENDIAN */ 2411 uint16_t sli4_vpi; 2412 uint16_t rsvd2; 2413 #endif 2414 uint32_t rsvd3; 2415 uint32_t rsvd4; 2416 uint32_t rsvd5; 2417 #ifdef __BIG_ENDIAN_BITFIELD 2418 uint16_t rsvd6; 2419 uint16_t vpi; 2420 #else /* __LITTLE_ENDIAN */ 2421 uint16_t vpi; 2422 uint16_t rsvd6; 2423 #endif 2424 } UNREG_VPI_VAR; 2425 2426 /* Structure for MB Command UNREG_D_ID (0x23) */ 2427 2428 typedef struct { 2429 uint32_t did; 2430 uint32_t rsvd2; 2431 uint32_t rsvd3; 2432 uint32_t rsvd4; 2433 uint32_t rsvd5; 2434 #ifdef __BIG_ENDIAN_BITFIELD 2435 uint16_t rsvd6; 2436 uint16_t vpi; 2437 #else 2438 uint16_t vpi; 2439 uint16_t rsvd6; 2440 #endif 2441 } UNREG_D_ID_VAR; 2442 2443 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 2444 struct lpfc_mbx_read_top { 2445 uint32_t eventTag; /* Event tag */ 2446 uint32_t word2; 2447 #define lpfc_mbx_read_top_fa_SHIFT 12 2448 #define lpfc_mbx_read_top_fa_MASK 0x00000001 2449 #define lpfc_mbx_read_top_fa_WORD word2 2450 #define lpfc_mbx_read_top_mm_SHIFT 11 2451 #define lpfc_mbx_read_top_mm_MASK 0x00000001 2452 #define lpfc_mbx_read_top_mm_WORD word2 2453 #define lpfc_mbx_read_top_pb_SHIFT 9 2454 #define lpfc_mbx_read_top_pb_MASK 0X00000001 2455 #define lpfc_mbx_read_top_pb_WORD word2 2456 #define lpfc_mbx_read_top_il_SHIFT 8 2457 #define lpfc_mbx_read_top_il_MASK 0x00000001 2458 #define lpfc_mbx_read_top_il_WORD word2 2459 #define lpfc_mbx_read_top_att_type_SHIFT 0 2460 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 2461 #define lpfc_mbx_read_top_att_type_WORD word2 2462 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 2463 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 2464 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 2465 uint32_t word3; 2466 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 2467 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 2468 #define lpfc_mbx_read_top_alpa_granted_WORD word3 2469 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 2470 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 2471 #define lpfc_mbx_read_top_lip_alps_WORD word3 2472 #define lpfc_mbx_read_top_lip_type_SHIFT 8 2473 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 2474 #define lpfc_mbx_read_top_lip_type_WORD word3 2475 #define lpfc_mbx_read_top_topology_SHIFT 0 2476 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 2477 #define lpfc_mbx_read_top_topology_WORD word3 2478 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2479 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2480 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2481 /* store the LILP AL_PA position map into */ 2482 struct ulp_bde64 lilpBde64; 2483 #define LPFC_ALPA_MAP_SIZE 128 2484 uint32_t word7; 2485 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 2486 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 2487 #define lpfc_mbx_read_top_ld_lu_WORD word7 2488 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 2489 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 2490 #define lpfc_mbx_read_top_ld_tf_WORD word7 2491 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 2492 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 2493 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 2494 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 2495 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 2496 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 2497 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 2498 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 2499 #define lpfc_mbx_read_top_ld_tx_WORD word7 2500 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 2501 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 2502 #define lpfc_mbx_read_top_ld_rx_WORD word7 2503 uint32_t word8; 2504 #define lpfc_mbx_read_top_lu_SHIFT 31 2505 #define lpfc_mbx_read_top_lu_MASK 0x00000001 2506 #define lpfc_mbx_read_top_lu_WORD word8 2507 #define lpfc_mbx_read_top_tf_SHIFT 30 2508 #define lpfc_mbx_read_top_tf_MASK 0x00000001 2509 #define lpfc_mbx_read_top_tf_WORD word8 2510 #define lpfc_mbx_read_top_link_spd_SHIFT 8 2511 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 2512 #define lpfc_mbx_read_top_link_spd_WORD word8 2513 #define lpfc_mbx_read_top_nl_port_SHIFT 4 2514 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 2515 #define lpfc_mbx_read_top_nl_port_WORD word8 2516 #define lpfc_mbx_read_top_tx_SHIFT 2 2517 #define lpfc_mbx_read_top_tx_MASK 0x00000003 2518 #define lpfc_mbx_read_top_tx_WORD word8 2519 #define lpfc_mbx_read_top_rx_SHIFT 0 2520 #define lpfc_mbx_read_top_rx_MASK 0x00000003 2521 #define lpfc_mbx_read_top_rx_WORD word8 2522 #define LPFC_LINK_SPEED_UNKNOWN 0x0 2523 #define LPFC_LINK_SPEED_1GHZ 0x04 2524 #define LPFC_LINK_SPEED_2GHZ 0x08 2525 #define LPFC_LINK_SPEED_4GHZ 0x10 2526 #define LPFC_LINK_SPEED_8GHZ 0x20 2527 #define LPFC_LINK_SPEED_10GHZ 0x40 2528 #define LPFC_LINK_SPEED_16GHZ 0x80 2529 }; 2530 2531 /* Structure for MB Command CLEAR_LA (22) */ 2532 2533 typedef struct { 2534 uint32_t eventTag; /* Event tag */ 2535 uint32_t rsvd1; 2536 } CLEAR_LA_VAR; 2537 2538 /* Structure for MB Command DUMP */ 2539 2540 typedef struct { 2541 #ifdef __BIG_ENDIAN_BITFIELD 2542 uint32_t rsvd:25; 2543 uint32_t ra:1; 2544 uint32_t co:1; 2545 uint32_t cv:1; 2546 uint32_t type:4; 2547 uint32_t entry_index:16; 2548 uint32_t region_id:16; 2549 #else /* __LITTLE_ENDIAN_BITFIELD */ 2550 uint32_t type:4; 2551 uint32_t cv:1; 2552 uint32_t co:1; 2553 uint32_t ra:1; 2554 uint32_t rsvd:25; 2555 uint32_t region_id:16; 2556 uint32_t entry_index:16; 2557 #endif 2558 2559 uint32_t sli4_length; 2560 uint32_t word_cnt; 2561 uint32_t resp_offset; 2562 } DUMP_VAR; 2563 2564 #define DMP_MEM_REG 0x1 2565 #define DMP_NV_PARAMS 0x2 2566 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 2567 #define DMP_WELL_KNOWN 0x4 2568 2569 #define DMP_REGION_VPD 0xe 2570 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2571 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2572 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2573 2574 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2575 #define DMP_VPORT_REGION_SIZE 0x200 2576 #define DMP_MBOX_OFFSET_WORD 0x5 2577 2578 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2579 #define DMP_RGN23_SIZE 0x400 2580 2581 #define WAKE_UP_PARMS_REGION_ID 4 2582 #define WAKE_UP_PARMS_WORD_SIZE 15 2583 2584 struct vport_rec { 2585 uint8_t wwpn[8]; 2586 uint8_t wwnn[8]; 2587 }; 2588 2589 #define VPORT_INFO_SIG 0x32324752 2590 #define VPORT_INFO_REV_MASK 0xff 2591 #define VPORT_INFO_REV 0x1 2592 #define MAX_STATIC_VPORT_COUNT 16 2593 struct static_vport_info { 2594 uint32_t signature; 2595 uint32_t rev; 2596 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2597 uint32_t resvd[66]; 2598 }; 2599 2600 /* Option rom version structure */ 2601 struct prog_id { 2602 #ifdef __BIG_ENDIAN_BITFIELD 2603 uint8_t type; 2604 uint8_t id; 2605 uint32_t ver:4; /* Major Version */ 2606 uint32_t rev:4; /* Revision */ 2607 uint32_t lev:2; /* Level */ 2608 uint32_t dist:2; /* Dist Type */ 2609 uint32_t num:4; /* number after dist type */ 2610 #else /* __LITTLE_ENDIAN_BITFIELD */ 2611 uint32_t num:4; /* number after dist type */ 2612 uint32_t dist:2; /* Dist Type */ 2613 uint32_t lev:2; /* Level */ 2614 uint32_t rev:4; /* Revision */ 2615 uint32_t ver:4; /* Major Version */ 2616 uint8_t id; 2617 uint8_t type; 2618 #endif 2619 }; 2620 2621 /* Structure for MB Command UPDATE_CFG (0x1B) */ 2622 2623 struct update_cfg_var { 2624 #ifdef __BIG_ENDIAN_BITFIELD 2625 uint32_t rsvd2:16; 2626 uint32_t type:8; 2627 uint32_t rsvd:1; 2628 uint32_t ra:1; 2629 uint32_t co:1; 2630 uint32_t cv:1; 2631 uint32_t req:4; 2632 uint32_t entry_length:16; 2633 uint32_t region_id:16; 2634 #else /* __LITTLE_ENDIAN_BITFIELD */ 2635 uint32_t req:4; 2636 uint32_t cv:1; 2637 uint32_t co:1; 2638 uint32_t ra:1; 2639 uint32_t rsvd:1; 2640 uint32_t type:8; 2641 uint32_t rsvd2:16; 2642 uint32_t region_id:16; 2643 uint32_t entry_length:16; 2644 #endif 2645 2646 uint32_t resp_info; 2647 uint32_t byte_cnt; 2648 uint32_t data_offset; 2649 }; 2650 2651 struct hbq_mask { 2652 #ifdef __BIG_ENDIAN_BITFIELD 2653 uint8_t tmatch; 2654 uint8_t tmask; 2655 uint8_t rctlmatch; 2656 uint8_t rctlmask; 2657 #else /* __LITTLE_ENDIAN */ 2658 uint8_t rctlmask; 2659 uint8_t rctlmatch; 2660 uint8_t tmask; 2661 uint8_t tmatch; 2662 #endif 2663 }; 2664 2665 2666 /* Structure for MB Command CONFIG_HBQ (7c) */ 2667 2668 struct config_hbq_var { 2669 #ifdef __BIG_ENDIAN_BITFIELD 2670 uint32_t rsvd1 :7; 2671 uint32_t recvNotify :1; /* Receive Notification */ 2672 uint32_t numMask :8; /* # Mask Entries */ 2673 uint32_t profile :8; /* Selection Profile */ 2674 uint32_t rsvd2 :8; 2675 #else /* __LITTLE_ENDIAN */ 2676 uint32_t rsvd2 :8; 2677 uint32_t profile :8; /* Selection Profile */ 2678 uint32_t numMask :8; /* # Mask Entries */ 2679 uint32_t recvNotify :1; /* Receive Notification */ 2680 uint32_t rsvd1 :7; 2681 #endif 2682 2683 #ifdef __BIG_ENDIAN_BITFIELD 2684 uint32_t hbqId :16; 2685 uint32_t rsvd3 :12; 2686 uint32_t ringMask :4; 2687 #else /* __LITTLE_ENDIAN */ 2688 uint32_t ringMask :4; 2689 uint32_t rsvd3 :12; 2690 uint32_t hbqId :16; 2691 #endif 2692 2693 #ifdef __BIG_ENDIAN_BITFIELD 2694 uint32_t entry_count :16; 2695 uint32_t rsvd4 :8; 2696 uint32_t headerLen :8; 2697 #else /* __LITTLE_ENDIAN */ 2698 uint32_t headerLen :8; 2699 uint32_t rsvd4 :8; 2700 uint32_t entry_count :16; 2701 #endif 2702 2703 uint32_t hbqaddrLow; 2704 uint32_t hbqaddrHigh; 2705 2706 #ifdef __BIG_ENDIAN_BITFIELD 2707 uint32_t rsvd5 :31; 2708 uint32_t logEntry :1; 2709 #else /* __LITTLE_ENDIAN */ 2710 uint32_t logEntry :1; 2711 uint32_t rsvd5 :31; 2712 #endif 2713 2714 uint32_t rsvd6; /* w7 */ 2715 uint32_t rsvd7; /* w8 */ 2716 uint32_t rsvd8; /* w9 */ 2717 2718 struct hbq_mask hbqMasks[6]; 2719 2720 2721 union { 2722 uint32_t allprofiles[12]; 2723 2724 struct { 2725 #ifdef __BIG_ENDIAN_BITFIELD 2726 uint32_t seqlenoff :16; 2727 uint32_t maxlen :16; 2728 #else /* __LITTLE_ENDIAN */ 2729 uint32_t maxlen :16; 2730 uint32_t seqlenoff :16; 2731 #endif 2732 #ifdef __BIG_ENDIAN_BITFIELD 2733 uint32_t rsvd1 :28; 2734 uint32_t seqlenbcnt :4; 2735 #else /* __LITTLE_ENDIAN */ 2736 uint32_t seqlenbcnt :4; 2737 uint32_t rsvd1 :28; 2738 #endif 2739 uint32_t rsvd[10]; 2740 } profile2; 2741 2742 struct { 2743 #ifdef __BIG_ENDIAN_BITFIELD 2744 uint32_t seqlenoff :16; 2745 uint32_t maxlen :16; 2746 #else /* __LITTLE_ENDIAN */ 2747 uint32_t maxlen :16; 2748 uint32_t seqlenoff :16; 2749 #endif 2750 #ifdef __BIG_ENDIAN_BITFIELD 2751 uint32_t cmdcodeoff :28; 2752 uint32_t rsvd1 :12; 2753 uint32_t seqlenbcnt :4; 2754 #else /* __LITTLE_ENDIAN */ 2755 uint32_t seqlenbcnt :4; 2756 uint32_t rsvd1 :12; 2757 uint32_t cmdcodeoff :28; 2758 #endif 2759 uint32_t cmdmatch[8]; 2760 2761 uint32_t rsvd[2]; 2762 } profile3; 2763 2764 struct { 2765 #ifdef __BIG_ENDIAN_BITFIELD 2766 uint32_t seqlenoff :16; 2767 uint32_t maxlen :16; 2768 #else /* __LITTLE_ENDIAN */ 2769 uint32_t maxlen :16; 2770 uint32_t seqlenoff :16; 2771 #endif 2772 #ifdef __BIG_ENDIAN_BITFIELD 2773 uint32_t cmdcodeoff :28; 2774 uint32_t rsvd1 :12; 2775 uint32_t seqlenbcnt :4; 2776 #else /* __LITTLE_ENDIAN */ 2777 uint32_t seqlenbcnt :4; 2778 uint32_t rsvd1 :12; 2779 uint32_t cmdcodeoff :28; 2780 #endif 2781 uint32_t cmdmatch[8]; 2782 2783 uint32_t rsvd[2]; 2784 } profile5; 2785 2786 } profiles; 2787 2788 }; 2789 2790 2791 2792 /* Structure for MB Command CONFIG_PORT (0x88) */ 2793 typedef struct { 2794 #ifdef __BIG_ENDIAN_BITFIELD 2795 uint32_t cBE : 1; 2796 uint32_t cET : 1; 2797 uint32_t cHpcb : 1; 2798 uint32_t cMA : 1; 2799 uint32_t sli_mode : 4; 2800 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2801 * config block */ 2802 #else /* __LITTLE_ENDIAN */ 2803 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 2804 * config block */ 2805 uint32_t sli_mode : 4; 2806 uint32_t cMA : 1; 2807 uint32_t cHpcb : 1; 2808 uint32_t cET : 1; 2809 uint32_t cBE : 1; 2810 #endif 2811 2812 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 2813 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 2814 uint32_t hbainit[5]; 2815 #ifdef __BIG_ENDIAN_BITFIELD 2816 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2817 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2818 #else /* __LITTLE_ENDIAN */ 2819 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 2820 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 2821 #endif 2822 2823 #ifdef __BIG_ENDIAN_BITFIELD 2824 uint32_t rsvd1 : 19; /* Reserved */ 2825 uint32_t cdss : 1; /* Configure Data Security SLI */ 2826 uint32_t casabt : 1; /* Configure async abts status notice */ 2827 uint32_t rsvd2 : 2; /* Reserved */ 2828 uint32_t cbg : 1; /* Configure BlockGuard */ 2829 uint32_t cmv : 1; /* Configure Max VPIs */ 2830 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2831 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2832 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2833 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2834 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2835 uint32_t cmx : 1; /* Configure Max XRIs */ 2836 uint32_t cmr : 1; /* Configure Max RPIs */ 2837 #else /* __LITTLE_ENDIAN */ 2838 uint32_t cmr : 1; /* Configure Max RPIs */ 2839 uint32_t cmx : 1; /* Configure Max XRIs */ 2840 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 2841 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 2842 uint32_t chbs : 1; /* Cofigure Host Backing store */ 2843 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 2844 uint32_t ccrp : 1; /* Config Command Ring Polling */ 2845 uint32_t cmv : 1; /* Configure Max VPIs */ 2846 uint32_t cbg : 1; /* Configure BlockGuard */ 2847 uint32_t rsvd2 : 2; /* Reserved */ 2848 uint32_t casabt : 1; /* Configure async abts status notice */ 2849 uint32_t cdss : 1; /* Configure Data Security SLI */ 2850 uint32_t rsvd1 : 19; /* Reserved */ 2851 #endif 2852 #ifdef __BIG_ENDIAN_BITFIELD 2853 uint32_t rsvd3 : 19; /* Reserved */ 2854 uint32_t gdss : 1; /* Configure Data Security SLI */ 2855 uint32_t gasabt : 1; /* Grant async abts status notice */ 2856 uint32_t rsvd4 : 2; /* Reserved */ 2857 uint32_t gbg : 1; /* Grant BlockGuard */ 2858 uint32_t gmv : 1; /* Grant Max VPIs */ 2859 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2860 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2861 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2862 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2863 uint32_t gerbm : 1; /* Grant ERBM Request */ 2864 uint32_t gmx : 1; /* Grant Max XRIs */ 2865 uint32_t gmr : 1; /* Grant Max RPIs */ 2866 #else /* __LITTLE_ENDIAN */ 2867 uint32_t gmr : 1; /* Grant Max RPIs */ 2868 uint32_t gmx : 1; /* Grant Max XRIs */ 2869 uint32_t gerbm : 1; /* Grant ERBM Request */ 2870 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 2871 uint32_t ghbs : 1; /* Grant Host Backing Store */ 2872 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 2873 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 2874 uint32_t gmv : 1; /* Grant Max VPIs */ 2875 uint32_t gbg : 1; /* Grant BlockGuard */ 2876 uint32_t rsvd4 : 2; /* Reserved */ 2877 uint32_t gasabt : 1; /* Grant async abts status notice */ 2878 uint32_t gdss : 1; /* Configure Data Security SLI */ 2879 uint32_t rsvd3 : 19; /* Reserved */ 2880 #endif 2881 2882 #ifdef __BIG_ENDIAN_BITFIELD 2883 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2884 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2885 #else /* __LITTLE_ENDIAN */ 2886 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 2887 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 2888 #endif 2889 2890 #ifdef __BIG_ENDIAN_BITFIELD 2891 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2892 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2893 #else /* __LITTLE_ENDIAN */ 2894 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 2895 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 2896 #endif 2897 2898 uint32_t rsvd6; /* Reserved */ 2899 2900 #ifdef __BIG_ENDIAN_BITFIELD 2901 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2902 uint32_t fips_level : 4; /* FIPS Level */ 2903 uint32_t sec_err : 9; /* security crypto error */ 2904 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2905 #else /* __LITTLE_ENDIAN */ 2906 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 2907 uint32_t sec_err : 9; /* security crypto error */ 2908 uint32_t fips_level : 4; /* FIPS Level */ 2909 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 2910 #endif 2911 2912 } CONFIG_PORT_VAR; 2913 2914 /* Structure for MB Command CONFIG_MSI (0x30) */ 2915 struct config_msi_var { 2916 #ifdef __BIG_ENDIAN_BITFIELD 2917 uint32_t dfltMsgNum:8; /* Default message number */ 2918 uint32_t rsvd1:11; /* Reserved */ 2919 uint32_t NID:5; /* Number of secondary attention IDs */ 2920 uint32_t rsvd2:5; /* Reserved */ 2921 uint32_t dfltPresent:1; /* Default message number present */ 2922 uint32_t addFlag:1; /* Add association flag */ 2923 uint32_t reportFlag:1; /* Report association flag */ 2924 #else /* __LITTLE_ENDIAN_BITFIELD */ 2925 uint32_t reportFlag:1; /* Report association flag */ 2926 uint32_t addFlag:1; /* Add association flag */ 2927 uint32_t dfltPresent:1; /* Default message number present */ 2928 uint32_t rsvd2:5; /* Reserved */ 2929 uint32_t NID:5; /* Number of secondary attention IDs */ 2930 uint32_t rsvd1:11; /* Reserved */ 2931 uint32_t dfltMsgNum:8; /* Default message number */ 2932 #endif 2933 uint32_t attentionConditions[2]; 2934 uint8_t attentionId[16]; 2935 uint8_t messageNumberByHA[64]; 2936 uint8_t messageNumberByID[16]; 2937 uint32_t autoClearHA[2]; 2938 #ifdef __BIG_ENDIAN_BITFIELD 2939 uint32_t rsvd3:16; 2940 uint32_t autoClearID:16; 2941 #else /* __LITTLE_ENDIAN_BITFIELD */ 2942 uint32_t autoClearID:16; 2943 uint32_t rsvd3:16; 2944 #endif 2945 uint32_t rsvd4; 2946 }; 2947 2948 /* SLI-2 Port Control Block */ 2949 2950 /* SLIM POINTER */ 2951 #define SLIMOFF 0x30 /* WORD */ 2952 2953 typedef struct _SLI2_RDSC { 2954 uint32_t cmdEntries; 2955 uint32_t cmdAddrLow; 2956 uint32_t cmdAddrHigh; 2957 2958 uint32_t rspEntries; 2959 uint32_t rspAddrLow; 2960 uint32_t rspAddrHigh; 2961 } SLI2_RDSC; 2962 2963 typedef struct _PCB { 2964 #ifdef __BIG_ENDIAN_BITFIELD 2965 uint32_t type:8; 2966 #define TYPE_NATIVE_SLI2 0x01 2967 uint32_t feature:8; 2968 #define FEATURE_INITIAL_SLI2 0x01 2969 uint32_t rsvd:12; 2970 uint32_t maxRing:4; 2971 #else /* __LITTLE_ENDIAN_BITFIELD */ 2972 uint32_t maxRing:4; 2973 uint32_t rsvd:12; 2974 uint32_t feature:8; 2975 #define FEATURE_INITIAL_SLI2 0x01 2976 uint32_t type:8; 2977 #define TYPE_NATIVE_SLI2 0x01 2978 #endif 2979 2980 uint32_t mailBoxSize; 2981 uint32_t mbAddrLow; 2982 uint32_t mbAddrHigh; 2983 2984 uint32_t hgpAddrLow; 2985 uint32_t hgpAddrHigh; 2986 2987 uint32_t pgpAddrLow; 2988 uint32_t pgpAddrHigh; 2989 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 2990 } PCB_t; 2991 2992 /* NEW_FEATURE */ 2993 typedef struct { 2994 #ifdef __BIG_ENDIAN_BITFIELD 2995 uint32_t rsvd0:27; 2996 uint32_t discardFarp:1; 2997 uint32_t IPEnable:1; 2998 uint32_t nodeName:1; 2999 uint32_t portName:1; 3000 uint32_t filterEnable:1; 3001 #else /* __LITTLE_ENDIAN_BITFIELD */ 3002 uint32_t filterEnable:1; 3003 uint32_t portName:1; 3004 uint32_t nodeName:1; 3005 uint32_t IPEnable:1; 3006 uint32_t discardFarp:1; 3007 uint32_t rsvd:27; 3008 #endif 3009 3010 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3011 uint8_t nodename[8]; 3012 uint32_t rsvd1; 3013 uint32_t rsvd2; 3014 uint32_t rsvd3; 3015 uint32_t IPAddress; 3016 } CONFIG_FARP_VAR; 3017 3018 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3019 3020 typedef struct { 3021 #ifdef __BIG_ENDIAN_BITFIELD 3022 uint32_t rsvd:30; 3023 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3024 #else /* __LITTLE_ENDIAN */ 3025 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3026 uint32_t rsvd:30; 3027 #endif 3028 } ASYNCEVT_ENABLE_VAR; 3029 3030 /* Union of all Mailbox Command types */ 3031 #define MAILBOX_CMD_WSIZE 32 3032 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3033 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3034 #define MAILBOX_EXT_WSIZE 512 3035 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3036 #define MAILBOX_HBA_EXT_OFFSET 0x100 3037 /* max mbox xmit size is a page size for sysfs IO operations */ 3038 #define MAILBOX_SYSFS_MAX 4096 3039 3040 typedef union { 3041 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3042 * feature/max ring number 3043 */ 3044 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3045 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3046 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3047 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3048 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3049 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3050 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3051 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3052 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3053 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3054 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3055 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3056 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3057 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3058 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3059 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3060 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3061 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3062 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3063 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3064 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3065 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3066 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3067 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3068 * NEW_FEATURE 3069 */ 3070 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3071 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3072 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3073 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3074 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3075 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3076 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3077 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3078 * (READ_EVENT_LOG) 3079 */ 3080 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3081 } MAILVARIANTS; 3082 3083 /* 3084 * SLI-2 specific structures 3085 */ 3086 3087 struct lpfc_hgp { 3088 __le32 cmdPutInx; 3089 __le32 rspGetInx; 3090 }; 3091 3092 struct lpfc_pgp { 3093 __le32 cmdGetInx; 3094 __le32 rspPutInx; 3095 }; 3096 3097 struct sli2_desc { 3098 uint32_t unused1[16]; 3099 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3100 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3101 }; 3102 3103 struct sli3_desc { 3104 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3105 uint32_t reserved[8]; 3106 uint32_t hbq_put[16]; 3107 }; 3108 3109 struct sli3_pgp { 3110 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3111 uint32_t hbq_get[16]; 3112 }; 3113 3114 union sli_var { 3115 struct sli2_desc s2; 3116 struct sli3_desc s3; 3117 struct sli3_pgp s3_pgp; 3118 }; 3119 3120 typedef struct { 3121 #ifdef __BIG_ENDIAN_BITFIELD 3122 uint16_t mbxStatus; 3123 uint8_t mbxCommand; 3124 uint8_t mbxReserved:6; 3125 uint8_t mbxHc:1; 3126 uint8_t mbxOwner:1; /* Low order bit first word */ 3127 #else /* __LITTLE_ENDIAN_BITFIELD */ 3128 uint8_t mbxOwner:1; /* Low order bit first word */ 3129 uint8_t mbxHc:1; 3130 uint8_t mbxReserved:6; 3131 uint8_t mbxCommand; 3132 uint16_t mbxStatus; 3133 #endif 3134 3135 MAILVARIANTS un; 3136 union sli_var us; 3137 } MAILBOX_t; 3138 3139 /* 3140 * Begin Structure Definitions for IOCB Commands 3141 */ 3142 3143 typedef struct { 3144 #ifdef __BIG_ENDIAN_BITFIELD 3145 uint8_t statAction; 3146 uint8_t statRsn; 3147 uint8_t statBaExp; 3148 uint8_t statLocalError; 3149 #else /* __LITTLE_ENDIAN_BITFIELD */ 3150 uint8_t statLocalError; 3151 uint8_t statBaExp; 3152 uint8_t statRsn; 3153 uint8_t statAction; 3154 #endif 3155 /* statRsn P/F_RJT reason codes */ 3156 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3157 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3158 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3159 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3160 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3161 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3162 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3163 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3164 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3165 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3166 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3167 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3168 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3169 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3170 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3171 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3172 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3173 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3174 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3175 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3176 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3177 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3178 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3179 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3180 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3181 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3182 3183 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3184 #define IOERR_MISSING_CONTINUE 0x01 3185 #define IOERR_SEQUENCE_TIMEOUT 0x02 3186 #define IOERR_INTERNAL_ERROR 0x03 3187 #define IOERR_INVALID_RPI 0x04 3188 #define IOERR_NO_XRI 0x05 3189 #define IOERR_ILLEGAL_COMMAND 0x06 3190 #define IOERR_XCHG_DROPPED 0x07 3191 #define IOERR_ILLEGAL_FIELD 0x08 3192 #define IOERR_BAD_CONTINUE 0x09 3193 #define IOERR_TOO_MANY_BUFFERS 0x0A 3194 #define IOERR_RCV_BUFFER_WAITING 0x0B 3195 #define IOERR_NO_CONNECTION 0x0C 3196 #define IOERR_TX_DMA_FAILED 0x0D 3197 #define IOERR_RX_DMA_FAILED 0x0E 3198 #define IOERR_ILLEGAL_FRAME 0x0F 3199 #define IOERR_EXTRA_DATA 0x10 3200 #define IOERR_NO_RESOURCES 0x11 3201 #define IOERR_RESERVED 0x12 3202 #define IOERR_ILLEGAL_LENGTH 0x13 3203 #define IOERR_UNSUPPORTED_FEATURE 0x14 3204 #define IOERR_ABORT_IN_PROGRESS 0x15 3205 #define IOERR_ABORT_REQUESTED 0x16 3206 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3207 #define IOERR_LOOP_OPEN_FAILURE 0x18 3208 #define IOERR_RING_RESET 0x19 3209 #define IOERR_LINK_DOWN 0x1A 3210 #define IOERR_CORRUPTED_DATA 0x1B 3211 #define IOERR_CORRUPTED_RPI 0x1C 3212 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3213 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3214 #define IOERR_DUP_FRAME 0x1F 3215 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3216 #define IOERR_BAD_HOST_ADDRESS 0x21 3217 #define IOERR_RCV_HDRBUF_WAITING 0x22 3218 #define IOERR_MISSING_HDR_BUFFER 0x23 3219 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3220 #define IOERR_ABORTMULT_REQUESTED 0x25 3221 #define IOERR_BUFFER_SHORTAGE 0x28 3222 #define IOERR_DEFAULT 0x29 3223 #define IOERR_CNT 0x2A 3224 #define IOERR_SLER_FAILURE 0x46 3225 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3226 #define IOERR_SLER_REC_RJT_ERR 0x48 3227 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3228 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3229 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3230 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3231 #define IOERR_SLER_ABTS_ERR 0x4E 3232 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3233 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3234 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3235 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3236 #define IOERR_DRVR_MASK 0x100 3237 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3238 #define IOERR_SLI_BRESET 0x102 3239 #define IOERR_SLI_ABORTED 0x103 3240 #define IOERR_PARAM_MASK 0x1ff 3241 } PARM_ERR; 3242 3243 typedef union { 3244 struct { 3245 #ifdef __BIG_ENDIAN_BITFIELD 3246 uint8_t Rctl; /* R_CTL field */ 3247 uint8_t Type; /* TYPE field */ 3248 uint8_t Dfctl; /* DF_CTL field */ 3249 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3250 #else /* __LITTLE_ENDIAN_BITFIELD */ 3251 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3252 uint8_t Dfctl; /* DF_CTL field */ 3253 uint8_t Type; /* TYPE field */ 3254 uint8_t Rctl; /* R_CTL field */ 3255 #endif 3256 3257 #define BC 0x02 /* Broadcast Received - Fctl */ 3258 #define SI 0x04 /* Sequence Initiative */ 3259 #define LA 0x08 /* Ignore Link Attention state */ 3260 #define LS 0x80 /* Last Sequence */ 3261 } hcsw; 3262 uint32_t reserved; 3263 } WORD5; 3264 3265 /* IOCB Command template for a generic response */ 3266 typedef struct { 3267 uint32_t reserved[4]; 3268 PARM_ERR perr; 3269 } GENERIC_RSP; 3270 3271 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3272 typedef struct { 3273 struct ulp_bde xrsqbde[2]; 3274 uint32_t xrsqRo; /* Starting Relative Offset */ 3275 WORD5 w5; /* Header control/status word */ 3276 } XR_SEQ_FIELDS; 3277 3278 /* IOCB Command template for ELS_REQUEST */ 3279 typedef struct { 3280 struct ulp_bde elsReq; 3281 struct ulp_bde elsRsp; 3282 3283 #ifdef __BIG_ENDIAN_BITFIELD 3284 uint32_t word4Rsvd:7; 3285 uint32_t fl:1; 3286 uint32_t myID:24; 3287 uint32_t word5Rsvd:8; 3288 uint32_t remoteID:24; 3289 #else /* __LITTLE_ENDIAN_BITFIELD */ 3290 uint32_t myID:24; 3291 uint32_t fl:1; 3292 uint32_t word4Rsvd:7; 3293 uint32_t remoteID:24; 3294 uint32_t word5Rsvd:8; 3295 #endif 3296 } ELS_REQUEST; 3297 3298 /* IOCB Command template for RCV_ELS_REQ */ 3299 typedef struct { 3300 struct ulp_bde elsReq[2]; 3301 uint32_t parmRo; 3302 3303 #ifdef __BIG_ENDIAN_BITFIELD 3304 uint32_t word5Rsvd:8; 3305 uint32_t remoteID:24; 3306 #else /* __LITTLE_ENDIAN_BITFIELD */ 3307 uint32_t remoteID:24; 3308 uint32_t word5Rsvd:8; 3309 #endif 3310 } RCV_ELS_REQ; 3311 3312 /* IOCB Command template for ABORT / CLOSE_XRI */ 3313 typedef struct { 3314 uint32_t rsvd[3]; 3315 uint32_t abortType; 3316 #define ABORT_TYPE_ABTX 0x00000000 3317 #define ABORT_TYPE_ABTS 0x00000001 3318 uint32_t parm; 3319 #ifdef __BIG_ENDIAN_BITFIELD 3320 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3321 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3322 #else /* __LITTLE_ENDIAN_BITFIELD */ 3323 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3324 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3325 #endif 3326 } AC_XRI; 3327 3328 /* IOCB Command template for ABORT_MXRI64 */ 3329 typedef struct { 3330 uint32_t rsvd[3]; 3331 uint32_t abortType; 3332 uint32_t parm; 3333 uint32_t iotag32; 3334 } A_MXRI64; 3335 3336 /* IOCB Command template for GET_RPI */ 3337 typedef struct { 3338 uint32_t rsvd[4]; 3339 uint32_t parmRo; 3340 #ifdef __BIG_ENDIAN_BITFIELD 3341 uint32_t word5Rsvd:8; 3342 uint32_t remoteID:24; 3343 #else /* __LITTLE_ENDIAN_BITFIELD */ 3344 uint32_t remoteID:24; 3345 uint32_t word5Rsvd:8; 3346 #endif 3347 } GET_RPI; 3348 3349 /* IOCB Command template for all FCP Initiator commands */ 3350 typedef struct { 3351 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3352 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3353 uint32_t fcpi_parm; 3354 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3355 } FCPI_FIELDS; 3356 3357 /* IOCB Command template for all FCP Target commands */ 3358 typedef struct { 3359 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3360 uint32_t fcpt_Offset; 3361 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3362 } FCPT_FIELDS; 3363 3364 /* SLI-2 IOCB structure definitions */ 3365 3366 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3367 typedef struct { 3368 ULP_BDL bdl; 3369 uint32_t xrsqRo; /* Starting Relative Offset */ 3370 WORD5 w5; /* Header control/status word */ 3371 } XMT_SEQ_FIELDS64; 3372 3373 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 3374 #define xmit_els_remoteID xrsqRo 3375 3376 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3377 typedef struct { 3378 struct ulp_bde64 rcvBde; 3379 uint32_t rsvd1; 3380 uint32_t xrsqRo; /* Starting Relative Offset */ 3381 WORD5 w5; /* Header control/status word */ 3382 } RCV_SEQ_FIELDS64; 3383 3384 /* IOCB Command template for ELS_REQUEST64 */ 3385 typedef struct { 3386 ULP_BDL bdl; 3387 #ifdef __BIG_ENDIAN_BITFIELD 3388 uint32_t word4Rsvd:7; 3389 uint32_t fl:1; 3390 uint32_t myID:24; 3391 uint32_t word5Rsvd:8; 3392 uint32_t remoteID:24; 3393 #else /* __LITTLE_ENDIAN_BITFIELD */ 3394 uint32_t myID:24; 3395 uint32_t fl:1; 3396 uint32_t word4Rsvd:7; 3397 uint32_t remoteID:24; 3398 uint32_t word5Rsvd:8; 3399 #endif 3400 } ELS_REQUEST64; 3401 3402 /* IOCB Command template for GEN_REQUEST64 */ 3403 typedef struct { 3404 ULP_BDL bdl; 3405 uint32_t xrsqRo; /* Starting Relative Offset */ 3406 WORD5 w5; /* Header control/status word */ 3407 } GEN_REQUEST64; 3408 3409 /* IOCB Command template for RCV_ELS_REQ64 */ 3410 typedef struct { 3411 struct ulp_bde64 elsReq; 3412 uint32_t rcvd1; 3413 uint32_t parmRo; 3414 3415 #ifdef __BIG_ENDIAN_BITFIELD 3416 uint32_t word5Rsvd:8; 3417 uint32_t remoteID:24; 3418 #else /* __LITTLE_ENDIAN_BITFIELD */ 3419 uint32_t remoteID:24; 3420 uint32_t word5Rsvd:8; 3421 #endif 3422 } RCV_ELS_REQ64; 3423 3424 /* IOCB Command template for RCV_SEQ64 */ 3425 struct rcv_seq64 { 3426 struct ulp_bde64 elsReq; 3427 uint32_t hbq_1; 3428 uint32_t parmRo; 3429 #ifdef __BIG_ENDIAN_BITFIELD 3430 uint32_t rctl:8; 3431 uint32_t type:8; 3432 uint32_t dfctl:8; 3433 uint32_t ls:1; 3434 uint32_t fs:1; 3435 uint32_t rsvd2:3; 3436 uint32_t si:1; 3437 uint32_t bc:1; 3438 uint32_t rsvd3:1; 3439 #else /* __LITTLE_ENDIAN_BITFIELD */ 3440 uint32_t rsvd3:1; 3441 uint32_t bc:1; 3442 uint32_t si:1; 3443 uint32_t rsvd2:3; 3444 uint32_t fs:1; 3445 uint32_t ls:1; 3446 uint32_t dfctl:8; 3447 uint32_t type:8; 3448 uint32_t rctl:8; 3449 #endif 3450 }; 3451 3452 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3453 typedef struct { 3454 ULP_BDL bdl; 3455 uint32_t fcpi_parm; 3456 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3457 } FCPI_FIELDS64; 3458 3459 /* IOCB Command template for all 64 bit FCP Target commands */ 3460 typedef struct { 3461 ULP_BDL bdl; 3462 uint32_t fcpt_Offset; 3463 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3464 } FCPT_FIELDS64; 3465 3466 /* IOCB Command template for Async Status iocb commands */ 3467 typedef struct { 3468 uint32_t rsvd[4]; 3469 uint32_t param; 3470 #ifdef __BIG_ENDIAN_BITFIELD 3471 uint16_t evt_code; /* High order bits word 5 */ 3472 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3473 #else /* __LITTLE_ENDIAN_BITFIELD */ 3474 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3475 uint16_t evt_code; /* Low order bits word 5 */ 3476 #endif 3477 } ASYNCSTAT_FIELDS; 3478 #define ASYNC_TEMP_WARN 0x100 3479 #define ASYNC_TEMP_SAFE 0x101 3480 #define ASYNC_STATUS_CN 0x102 3481 3482 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3483 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3484 3485 struct rcv_sli3 { 3486 #ifdef __BIG_ENDIAN_BITFIELD 3487 uint16_t ox_id; 3488 uint16_t seq_cnt; 3489 3490 uint16_t vpi; 3491 uint16_t word9Rsvd; 3492 #else /* __LITTLE_ENDIAN */ 3493 uint16_t seq_cnt; 3494 uint16_t ox_id; 3495 3496 uint16_t word9Rsvd; 3497 uint16_t vpi; 3498 #endif 3499 uint32_t word10Rsvd; 3500 uint32_t acc_len; /* accumulated length */ 3501 struct ulp_bde64 bde2; 3502 }; 3503 3504 /* Structure used for a single HBQ entry */ 3505 struct lpfc_hbq_entry { 3506 struct ulp_bde64 bde; 3507 uint32_t buffer_tag; 3508 }; 3509 3510 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3511 typedef struct { 3512 struct lpfc_hbq_entry buff; 3513 uint32_t rsvd; 3514 uint32_t rsvd1; 3515 } QUE_XRI64_CX_FIELDS; 3516 3517 struct que_xri64cx_ext_fields { 3518 uint32_t iotag64_low; 3519 uint32_t iotag64_high; 3520 uint32_t ebde_count; 3521 uint32_t rsvd; 3522 struct lpfc_hbq_entry buff[5]; 3523 }; 3524 3525 struct sli3_bg_fields { 3526 uint32_t filler[6]; /* word 8-13 in IOCB */ 3527 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3528 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3529 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3530 #define BGS_BIDIR_BG_PROF_SHIFT 24 3531 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3532 #define BGS_BIDIR_ERR_COND_SHIFT 16 3533 #define BGS_BG_PROFILE_MASK 0x0000ff00 3534 #define BGS_BG_PROFILE_SHIFT 8 3535 #define BGS_INVALID_PROF_MASK 0x00000020 3536 #define BGS_INVALID_PROF_SHIFT 5 3537 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3538 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3539 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3540 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3541 #define BGS_REFTAG_ERR_MASK 0x00000004 3542 #define BGS_REFTAG_ERR_SHIFT 2 3543 #define BGS_APPTAG_ERR_MASK 0x00000002 3544 #define BGS_APPTAG_ERR_SHIFT 1 3545 #define BGS_GUARD_ERR_MASK 0x00000001 3546 #define BGS_GUARD_ERR_SHIFT 0 3547 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3548 }; 3549 3550 static inline uint32_t 3551 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3552 { 3553 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 3554 BGS_BIDIR_BG_PROF_SHIFT; 3555 } 3556 3557 static inline uint32_t 3558 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3559 { 3560 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3561 BGS_BIDIR_ERR_COND_SHIFT; 3562 } 3563 3564 static inline uint32_t 3565 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3566 { 3567 return (bgstat & BGS_BG_PROFILE_MASK) >> 3568 BGS_BG_PROFILE_SHIFT; 3569 } 3570 3571 static inline uint32_t 3572 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3573 { 3574 return (bgstat & BGS_INVALID_PROF_MASK) >> 3575 BGS_INVALID_PROF_SHIFT; 3576 } 3577 3578 static inline uint32_t 3579 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3580 { 3581 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 3582 BGS_UNINIT_DIF_BLOCK_SHIFT; 3583 } 3584 3585 static inline uint32_t 3586 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3587 { 3588 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3589 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3590 } 3591 3592 static inline uint32_t 3593 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3594 { 3595 return (bgstat & BGS_REFTAG_ERR_MASK) >> 3596 BGS_REFTAG_ERR_SHIFT; 3597 } 3598 3599 static inline uint32_t 3600 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3601 { 3602 return (bgstat & BGS_APPTAG_ERR_MASK) >> 3603 BGS_APPTAG_ERR_SHIFT; 3604 } 3605 3606 static inline uint32_t 3607 lpfc_bgs_get_guard_err(uint32_t bgstat) 3608 { 3609 return (bgstat & BGS_GUARD_ERR_MASK) >> 3610 BGS_GUARD_ERR_SHIFT; 3611 } 3612 3613 #define LPFC_EXT_DATA_BDE_COUNT 3 3614 struct fcp_irw_ext { 3615 uint32_t io_tag64_low; 3616 uint32_t io_tag64_high; 3617 #ifdef __BIG_ENDIAN_BITFIELD 3618 uint8_t reserved1; 3619 uint8_t reserved2; 3620 uint8_t reserved3; 3621 uint8_t ebde_count; 3622 #else /* __LITTLE_ENDIAN */ 3623 uint8_t ebde_count; 3624 uint8_t reserved3; 3625 uint8_t reserved2; 3626 uint8_t reserved1; 3627 #endif 3628 uint32_t reserved4; 3629 struct ulp_bde64 rbde; /* response bde */ 3630 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 3631 uint8_t icd[32]; /* immediate command data (32 bytes) */ 3632 }; 3633 3634 typedef struct _IOCB { /* IOCB structure */ 3635 union { 3636 GENERIC_RSP grsp; /* Generic response */ 3637 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 3638 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 3639 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 3640 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 3641 A_MXRI64 amxri; /* abort multiple xri command overlay */ 3642 GET_RPI getrpi; /* GET_RPI template */ 3643 FCPI_FIELDS fcpi; /* FCP Initiator template */ 3644 FCPT_FIELDS fcpt; /* FCP target template */ 3645 3646 /* SLI-2 structures */ 3647 3648 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 3649 * bde_64s */ 3650 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 3651 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 3652 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 3653 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 3654 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 3655 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 3656 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 3657 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 3658 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 3659 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 3660 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 3661 } un; 3662 union { 3663 struct { 3664 #ifdef __BIG_ENDIAN_BITFIELD 3665 uint16_t ulpContext; /* High order bits word 6 */ 3666 uint16_t ulpIoTag; /* Low order bits word 6 */ 3667 #else /* __LITTLE_ENDIAN_BITFIELD */ 3668 uint16_t ulpIoTag; /* Low order bits word 6 */ 3669 uint16_t ulpContext; /* High order bits word 6 */ 3670 #endif 3671 } t1; 3672 struct { 3673 #ifdef __BIG_ENDIAN_BITFIELD 3674 uint16_t ulpContext; /* High order bits word 6 */ 3675 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3676 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3677 #else /* __LITTLE_ENDIAN_BITFIELD */ 3678 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 3679 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 3680 uint16_t ulpContext; /* High order bits word 6 */ 3681 #endif 3682 } t2; 3683 } un1; 3684 #define ulpContext un1.t1.ulpContext 3685 #define ulpIoTag un1.t1.ulpIoTag 3686 #define ulpIoTag0 un1.t2.ulpIoTag0 3687 3688 #ifdef __BIG_ENDIAN_BITFIELD 3689 uint32_t ulpTimeout:8; 3690 uint32_t ulpXS:1; 3691 uint32_t ulpFCP2Rcvy:1; 3692 uint32_t ulpPU:2; 3693 uint32_t ulpIr:1; 3694 uint32_t ulpClass:3; 3695 uint32_t ulpCommand:8; 3696 uint32_t ulpStatus:4; 3697 uint32_t ulpBdeCount:2; 3698 uint32_t ulpLe:1; 3699 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3700 #else /* __LITTLE_ENDIAN_BITFIELD */ 3701 uint32_t ulpOwner:1; /* Low order bit word 7 */ 3702 uint32_t ulpLe:1; 3703 uint32_t ulpBdeCount:2; 3704 uint32_t ulpStatus:4; 3705 uint32_t ulpCommand:8; 3706 uint32_t ulpClass:3; 3707 uint32_t ulpIr:1; 3708 uint32_t ulpPU:2; 3709 uint32_t ulpFCP2Rcvy:1; 3710 uint32_t ulpXS:1; 3711 uint32_t ulpTimeout:8; 3712 #endif 3713 3714 union { 3715 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 3716 3717 /* words 8-31 used for que_xri_cx iocb */ 3718 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 3719 struct fcp_irw_ext fcp_ext; 3720 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 3721 3722 /* words 8-15 for BlockGuard */ 3723 struct sli3_bg_fields sli3_bg; 3724 } unsli3; 3725 3726 #define ulpCt_h ulpXS 3727 #define ulpCt_l ulpFCP2Rcvy 3728 3729 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 3730 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 3731 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 3732 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 3733 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 3734 #define PARM_NPIV_DID 3 3735 #define CLASS1 0 /* Class 1 */ 3736 #define CLASS2 1 /* Class 2 */ 3737 #define CLASS3 2 /* Class 3 */ 3738 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 3739 3740 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 3741 #define IOSTAT_FCP_RSP_ERROR 0x1 3742 #define IOSTAT_REMOTE_STOP 0x2 3743 #define IOSTAT_LOCAL_REJECT 0x3 3744 #define IOSTAT_NPORT_RJT 0x4 3745 #define IOSTAT_FABRIC_RJT 0x5 3746 #define IOSTAT_NPORT_BSY 0x6 3747 #define IOSTAT_FABRIC_BSY 0x7 3748 #define IOSTAT_INTERMED_RSP 0x8 3749 #define IOSTAT_LS_RJT 0x9 3750 #define IOSTAT_BA_RJT 0xA 3751 #define IOSTAT_RSVD1 0xB 3752 #define IOSTAT_RSVD2 0xC 3753 #define IOSTAT_RSVD3 0xD 3754 #define IOSTAT_RSVD4 0xE 3755 #define IOSTAT_NEED_BUFFER 0xF 3756 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 3757 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 3758 #define IOSTAT_CNT 0x11 3759 3760 } IOCB_t; 3761 3762 3763 #define SLI1_SLIM_SIZE (4 * 1024) 3764 3765 /* Up to 498 IOCBs will fit into 16k 3766 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 3767 */ 3768 #define SLI2_SLIM_SIZE (64 * 1024) 3769 3770 /* Maximum IOCBs that will fit in SLI2 slim */ 3771 #define MAX_SLI2_IOCB 498 3772 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 3773 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 3774 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 3775 3776 /* HBQ entries are 4 words each = 4k */ 3777 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 3778 lpfc_sli_hbq_count()) 3779 3780 struct lpfc_sli2_slim { 3781 MAILBOX_t mbx; 3782 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 3783 PCB_t pcb; 3784 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 3785 }; 3786 3787 /* 3788 * This function checks PCI device to allow special handling for LC HBAs. 3789 * 3790 * Parameters: 3791 * device : struct pci_dev 's device field 3792 * 3793 * return 1 => TRUE 3794 * 0 => FALSE 3795 */ 3796 static inline int 3797 lpfc_is_LC_HBA(unsigned short device) 3798 { 3799 if ((device == PCI_DEVICE_ID_TFLY) || 3800 (device == PCI_DEVICE_ID_PFLY) || 3801 (device == PCI_DEVICE_ID_LP101) || 3802 (device == PCI_DEVICE_ID_BMID) || 3803 (device == PCI_DEVICE_ID_BSMB) || 3804 (device == PCI_DEVICE_ID_ZMID) || 3805 (device == PCI_DEVICE_ID_ZSMB) || 3806 (device == PCI_DEVICE_ID_SAT_MID) || 3807 (device == PCI_DEVICE_ID_SAT_SMB) || 3808 (device == PCI_DEVICE_ID_RFLY)) 3809 return 1; 3810 else 3811 return 0; 3812 } 3813 3814 /* 3815 * Determine if an IOCB failed because of a link event or firmware reset. 3816 */ 3817 3818 static inline int 3819 lpfc_error_lost_link(IOCB_t *iocbp) 3820 { 3821 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 3822 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 3823 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 3824 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 3825 } 3826 3827 #define MENLO_TRANSPORT_TYPE 0xfe 3828 #define MENLO_CONTEXT 0 3829 #define MENLO_PU 3 3830 #define MENLO_TIMEOUT 30 3831 #define SETVAR_MLOMNT 0x103107 3832 #define SETVAR_MLORST 0x103007 3833 3834 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 3835