1 /******************************************************************* 2 * This file is part of the Emulex Linux Device Driver for * 3 * Fibre Channel Host Bus Adapters. * 4 * Copyright (C) 2004-2016 Emulex. All rights reserved. * 5 * EMULEX and SLI are trademarks of Emulex. * 6 * www.emulex.com * 7 * * 8 * This program is free software; you can redistribute it and/or * 9 * modify it under the terms of version 2 of the GNU General * 10 * Public License as published by the Free Software Foundation. * 11 * This program is distributed in the hope that it will be useful. * 12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * 13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * 14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * 15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * 16 * TO BE LEGALLY INVALID. See the GNU General Public License for * 17 * more details, a copy of which can be found in the file COPYING * 18 * included with this package. * 19 *******************************************************************/ 20 21 #define FDMI_DID 0xfffffaU 22 #define NameServer_DID 0xfffffcU 23 #define SCR_DID 0xfffffdU 24 #define Fabric_DID 0xfffffeU 25 #define Bcast_DID 0xffffffU 26 #define Mask_DID 0xffffffU 27 #define CT_DID_MASK 0xffff00U 28 #define Fabric_DID_MASK 0xfff000U 29 #define WELL_KNOWN_DID_MASK 0xfffff0U 30 31 #define PT2PT_LocalID 1 32 #define PT2PT_RemoteID 2 33 34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */ 35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */ 36 #define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */ 37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */ 38 39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING 40 0 */ 41 42 #define FCELSSIZE 1024 /* maximum ELS transfer size */ 43 44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */ 45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */ 46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */ 47 #define LPFC_FCP_NEXT_RING 3 48 #define LPFC_FCP_OAS_RING 3 49 50 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */ 51 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */ 52 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */ 53 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */ 54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */ 55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */ 56 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */ 57 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */ 58 #define SLI2_IOCB_CMD_R3_ENTRIES 0 59 #define SLI2_IOCB_RSP_R3_ENTRIES 0 60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24 61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32 62 63 #define SLI2_IOCB_CMD_SIZE 32 64 #define SLI2_IOCB_RSP_SIZE 32 65 #define SLI3_IOCB_CMD_SIZE 128 66 #define SLI3_IOCB_RSP_SIZE 64 67 68 #define LPFC_UNREG_ALL_RPIS_VPORT 0xffff 69 #define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff 70 71 /* vendor ID used in SCSI netlink calls */ 72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX) 73 74 #define FW_REV_STR_SIZE 32 75 /* Common Transport structures and definitions */ 76 77 union CtRevisionId { 78 /* Structure is in Big Endian format */ 79 struct { 80 uint32_t Revision:8; 81 uint32_t InId:24; 82 } bits; 83 uint32_t word; 84 }; 85 86 union CtCommandResponse { 87 /* Structure is in Big Endian format */ 88 struct { 89 uint32_t CmdRsp:16; 90 uint32_t Size:16; 91 } bits; 92 uint32_t word; 93 }; 94 95 #define FC4_FEATURE_INIT 0x2 96 #define FC4_FEATURE_TARGET 0x1 97 98 struct lpfc_sli_ct_request { 99 /* Structure is in Big Endian format */ 100 union CtRevisionId RevisionId; 101 uint8_t FsType; 102 uint8_t FsSubType; 103 uint8_t Options; 104 uint8_t Rsrvd1; 105 union CtCommandResponse CommandResponse; 106 uint8_t Rsrvd2; 107 uint8_t ReasonCode; 108 uint8_t Explanation; 109 uint8_t VendorUnique; 110 #define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */ 111 112 union { 113 uint32_t PortID; 114 struct gid { 115 uint8_t PortType; /* for GID_PT requests */ 116 uint8_t DomainScope; 117 uint8_t AreaScope; 118 uint8_t Fc4Type; /* for GID_FT requests */ 119 } gid; 120 struct rft { 121 uint32_t PortId; /* For RFT_ID requests */ 122 123 #ifdef __BIG_ENDIAN_BITFIELD 124 uint32_t rsvd0:16; 125 uint32_t rsvd1:7; 126 uint32_t fcpReg:1; /* Type 8 */ 127 uint32_t rsvd2:2; 128 uint32_t ipReg:1; /* Type 5 */ 129 uint32_t rsvd3:5; 130 #else /* __LITTLE_ENDIAN_BITFIELD */ 131 uint32_t rsvd0:16; 132 uint32_t fcpReg:1; /* Type 8 */ 133 uint32_t rsvd1:7; 134 uint32_t rsvd3:5; 135 uint32_t ipReg:1; /* Type 5 */ 136 uint32_t rsvd2:2; 137 #endif 138 139 uint32_t rsvd[7]; 140 } rft; 141 struct rnn { 142 uint32_t PortId; /* For RNN_ID requests */ 143 uint8_t wwnn[8]; 144 } rnn; 145 struct rsnn { /* For RSNN_ID requests */ 146 uint8_t wwnn[8]; 147 uint8_t len; 148 uint8_t symbname[255]; 149 } rsnn; 150 struct da_id { /* For DA_ID requests */ 151 uint32_t port_id; 152 } da_id; 153 struct rspn { /* For RSPN_ID requests */ 154 uint32_t PortId; 155 uint8_t len; 156 uint8_t symbname[255]; 157 } rspn; 158 struct gff { 159 uint32_t PortId; 160 } gff; 161 struct gff_acc { 162 uint8_t fbits[128]; 163 } gff_acc; 164 #define FCP_TYPE_FEATURE_OFFSET 7 165 struct rff { 166 uint32_t PortId; 167 uint8_t reserved[2]; 168 uint8_t fbits; 169 uint8_t type_code; /* type=8 for FCP */ 170 } rff; 171 } un; 172 }; 173 174 #define LPFC_MAX_CT_SIZE (60 * 4096) 175 176 #define SLI_CT_REVISION 1 177 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 178 sizeof(struct gid)) 179 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 180 sizeof(struct gff)) 181 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 182 sizeof(struct rft)) 183 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 184 sizeof(struct rff)) 185 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 186 sizeof(struct rnn)) 187 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 188 sizeof(struct rsnn)) 189 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 190 sizeof(struct da_id)) 191 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \ 192 sizeof(struct rspn)) 193 194 /* 195 * FsType Definitions 196 */ 197 198 #define SLI_CT_MANAGEMENT_SERVICE 0xFA 199 #define SLI_CT_TIME_SERVICE 0xFB 200 #define SLI_CT_DIRECTORY_SERVICE 0xFC 201 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD 202 203 /* 204 * Directory Service Subtypes 205 */ 206 207 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02 208 209 /* 210 * Response Codes 211 */ 212 213 #define SLI_CT_RESPONSE_FS_RJT 0x8001 214 #define SLI_CT_RESPONSE_FS_ACC 0x8002 215 216 /* 217 * Reason Codes 218 */ 219 220 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0 221 #define SLI_CT_INVALID_COMMAND 0x01 222 #define SLI_CT_INVALID_VERSION 0x02 223 #define SLI_CT_LOGICAL_ERROR 0x03 224 #define SLI_CT_INVALID_IU_SIZE 0x04 225 #define SLI_CT_LOGICAL_BUSY 0x05 226 #define SLI_CT_PROTOCOL_ERROR 0x07 227 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09 228 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b 229 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10 230 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11 231 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12 232 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13 233 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20 234 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21 235 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22 236 #define SLI_CT_VENDOR_UNIQUE 0xff 237 238 /* 239 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations 240 */ 241 242 #define SLI_CT_NO_PORT_ID 0x01 243 #define SLI_CT_NO_PORT_NAME 0x02 244 #define SLI_CT_NO_NODE_NAME 0x03 245 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04 246 #define SLI_CT_NO_IP_ADDRESS 0x05 247 #define SLI_CT_NO_IPA 0x06 248 #define SLI_CT_NO_FC4_TYPES 0x07 249 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08 250 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09 251 #define SLI_CT_NO_PORT_TYPE 0x0A 252 #define SLI_CT_ACCESS_DENIED 0x10 253 #define SLI_CT_INVALID_PORT_ID 0x11 254 #define SLI_CT_DATABASE_EMPTY 0x12 255 256 /* 257 * Name Server Command Codes 258 */ 259 260 #define SLI_CTNS_GA_NXT 0x0100 261 #define SLI_CTNS_GPN_ID 0x0112 262 #define SLI_CTNS_GNN_ID 0x0113 263 #define SLI_CTNS_GCS_ID 0x0114 264 #define SLI_CTNS_GFT_ID 0x0117 265 #define SLI_CTNS_GSPN_ID 0x0118 266 #define SLI_CTNS_GPT_ID 0x011A 267 #define SLI_CTNS_GFF_ID 0x011F 268 #define SLI_CTNS_GID_PN 0x0121 269 #define SLI_CTNS_GID_NN 0x0131 270 #define SLI_CTNS_GIP_NN 0x0135 271 #define SLI_CTNS_GIPA_NN 0x0136 272 #define SLI_CTNS_GSNN_NN 0x0139 273 #define SLI_CTNS_GNN_IP 0x0153 274 #define SLI_CTNS_GIPA_IP 0x0156 275 #define SLI_CTNS_GID_FT 0x0171 276 #define SLI_CTNS_GID_PT 0x01A1 277 #define SLI_CTNS_RPN_ID 0x0212 278 #define SLI_CTNS_RNN_ID 0x0213 279 #define SLI_CTNS_RCS_ID 0x0214 280 #define SLI_CTNS_RFT_ID 0x0217 281 #define SLI_CTNS_RSPN_ID 0x0218 282 #define SLI_CTNS_RPT_ID 0x021A 283 #define SLI_CTNS_RFF_ID 0x021F 284 #define SLI_CTNS_RIP_NN 0x0235 285 #define SLI_CTNS_RIPA_NN 0x0236 286 #define SLI_CTNS_RSNN_NN 0x0239 287 #define SLI_CTNS_DA_ID 0x0300 288 289 /* 290 * Port Types 291 */ 292 293 #define SLI_CTPT_N_PORT 0x01 294 #define SLI_CTPT_NL_PORT 0x02 295 #define SLI_CTPT_FNL_PORT 0x03 296 #define SLI_CTPT_IP 0x04 297 #define SLI_CTPT_FCP 0x08 298 #define SLI_CTPT_NX_PORT 0x7F 299 #define SLI_CTPT_F_PORT 0x81 300 #define SLI_CTPT_FL_PORT 0x82 301 #define SLI_CTPT_E_PORT 0x84 302 303 #define SLI_CT_LAST_ENTRY 0x80000000 304 305 /* Fibre Channel Service Parameter definitions */ 306 307 #define FC_PH_4_0 6 /* FC-PH version 4.0 */ 308 #define FC_PH_4_1 7 /* FC-PH version 4.1 */ 309 #define FC_PH_4_2 8 /* FC-PH version 4.2 */ 310 #define FC_PH_4_3 9 /* FC-PH version 4.3 */ 311 312 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */ 313 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */ 314 #define FC_PH3 0x20 /* FC-PH-3 version */ 315 316 #define FF_FRAME_SIZE 2048 317 318 struct lpfc_name { 319 union { 320 struct { 321 #ifdef __BIG_ENDIAN_BITFIELD 322 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 324 8:11 of IEEE ext */ 325 #else /* __LITTLE_ENDIAN_BITFIELD */ 326 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit 327 8:11 of IEEE ext */ 328 uint8_t nameType:4; /* FC Word 0, bit 28:31 */ 329 #endif 330 331 #define NAME_IEEE 0x1 /* IEEE name - nameType */ 332 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */ 333 #define NAME_FC_TYPE 0x3 /* FC native name type */ 334 #define NAME_IP_TYPE 0x4 /* IP address */ 335 #define NAME_CCITT_TYPE 0xC 336 #define NAME_CCITT_GR_TYPE 0xE 337 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE 338 extended Lsb */ 339 uint8_t IEEE[6]; /* FC IEEE address */ 340 } s; 341 uint8_t wwn[8]; 342 } u; 343 }; 344 345 struct csp { 346 uint8_t fcphHigh; /* FC Word 0, byte 0 */ 347 uint8_t fcphLow; 348 uint8_t bbCreditMsb; 349 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */ 350 351 /* 352 * Word 1 Bit 31 in common service parameter is overloaded. 353 * Word 1 Bit 31 in FLOGI request is multiple NPort request 354 * Word 1 Bit 31 in FLOGI response is clean address bit 355 */ 356 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */ 357 /* 358 * Word 1 Bit 30 in common service parameter is overloaded. 359 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics 360 * Word 1 Bit 30 in PLOGI request is random offset 361 */ 362 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */ 363 #ifdef __BIG_ENDIAN_BITFIELD 364 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 365 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 366 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 367 uint16_t fPort:1; /* FC Word 1, bit 28 */ 368 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 369 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 370 uint16_t multicast:1; /* FC Word 1, bit 25 */ 371 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 372 373 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 374 uint16_t simplex:1; /* FC Word 1, bit 22 */ 375 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 376 uint16_t dhd:1; /* FC Word 1, bit 18 */ 377 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 378 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 379 #else /* __LITTLE_ENDIAN_BITFIELD */ 380 uint16_t broadcast:1; /* FC Word 1, bit 24 */ 381 uint16_t multicast:1; /* FC Word 1, bit 25 */ 382 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */ 383 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */ 384 uint16_t fPort:1; /* FC Word 1, bit 28 */ 385 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */ 386 uint16_t randomOffset:1; /* FC Word 1, bit 30 */ 387 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */ 388 389 uint16_t payloadlength:1; /* FC Word 1, bit 16 */ 390 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */ 391 uint16_t dhd:1; /* FC Word 1, bit 18 */ 392 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */ 393 uint16_t simplex:1; /* FC Word 1, bit 22 */ 394 uint16_t huntgroup:1; /* FC Word 1, bit 23 */ 395 #endif 396 397 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */ 398 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */ 399 union { 400 struct { 401 uint8_t word2Reserved1; /* FC Word 2 byte 0 */ 402 403 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */ 404 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */ 405 406 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */ 407 } nPort; 408 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */ 409 } w2; 410 411 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */ 412 }; 413 414 struct class_parms { 415 #ifdef __BIG_ENDIAN_BITFIELD 416 uint8_t classValid:1; /* FC Word 0, bit 31 */ 417 uint8_t intermix:1; /* FC Word 0, bit 30 */ 418 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 419 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 420 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 421 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 422 #else /* __LITTLE_ENDIAN_BITFIELD */ 423 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */ 424 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */ 425 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */ 426 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */ 427 uint8_t intermix:1; /* FC Word 0, bit 30 */ 428 uint8_t classValid:1; /* FC Word 0, bit 31 */ 429 430 #endif 431 432 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */ 433 434 #ifdef __BIG_ENDIAN_BITFIELD 435 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 436 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 437 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 438 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 439 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 440 #else /* __LITTLE_ENDIAN_BITFIELD */ 441 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */ 442 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */ 443 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */ 444 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */ 445 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */ 446 #endif 447 448 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */ 449 450 #ifdef __BIG_ENDIAN_BITFIELD 451 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 452 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 453 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 454 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 455 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 456 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 457 #else /* __LITTLE_ENDIAN_BITFIELD */ 458 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */ 459 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */ 460 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */ 461 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */ 462 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */ 463 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */ 464 #endif 465 466 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */ 467 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */ 468 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */ 469 470 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */ 471 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */ 472 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */ 473 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */ 474 475 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */ 476 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */ 477 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */ 478 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */ 479 }; 480 481 struct serv_parm { /* Structure is in Big Endian format */ 482 struct csp cmn; 483 struct lpfc_name portName; 484 struct lpfc_name nodeName; 485 struct class_parms cls1; 486 struct class_parms cls2; 487 struct class_parms cls3; 488 struct class_parms cls4; 489 uint8_t vendorVersion[16]; 490 }; 491 492 /* 493 * Virtual Fabric Tagging Header 494 */ 495 struct fc_vft_header { 496 uint32_t word0; 497 #define fc_vft_hdr_r_ctl_SHIFT 24 498 #define fc_vft_hdr_r_ctl_MASK 0xFF 499 #define fc_vft_hdr_r_ctl_WORD word0 500 #define fc_vft_hdr_ver_SHIFT 22 501 #define fc_vft_hdr_ver_MASK 0x3 502 #define fc_vft_hdr_ver_WORD word0 503 #define fc_vft_hdr_type_SHIFT 18 504 #define fc_vft_hdr_type_MASK 0xF 505 #define fc_vft_hdr_type_WORD word0 506 #define fc_vft_hdr_e_SHIFT 16 507 #define fc_vft_hdr_e_MASK 0x1 508 #define fc_vft_hdr_e_WORD word0 509 #define fc_vft_hdr_priority_SHIFT 13 510 #define fc_vft_hdr_priority_MASK 0x7 511 #define fc_vft_hdr_priority_WORD word0 512 #define fc_vft_hdr_vf_id_SHIFT 1 513 #define fc_vft_hdr_vf_id_MASK 0xFFF 514 #define fc_vft_hdr_vf_id_WORD word0 515 uint32_t word1; 516 #define fc_vft_hdr_hopct_SHIFT 24 517 #define fc_vft_hdr_hopct_MASK 0xFF 518 #define fc_vft_hdr_hopct_WORD word1 519 }; 520 521 /* 522 * Extended Link Service LS_COMMAND codes (Payload Word 0) 523 */ 524 #ifdef __BIG_ENDIAN_BITFIELD 525 #define ELS_CMD_MASK 0xffff0000 526 #define ELS_RSP_MASK 0xff000000 527 #define ELS_CMD_LS_RJT 0x01000000 528 #define ELS_CMD_ACC 0x02000000 529 #define ELS_CMD_PLOGI 0x03000000 530 #define ELS_CMD_FLOGI 0x04000000 531 #define ELS_CMD_LOGO 0x05000000 532 #define ELS_CMD_ABTX 0x06000000 533 #define ELS_CMD_RCS 0x07000000 534 #define ELS_CMD_RES 0x08000000 535 #define ELS_CMD_RSS 0x09000000 536 #define ELS_CMD_RSI 0x0A000000 537 #define ELS_CMD_ESTS 0x0B000000 538 #define ELS_CMD_ESTC 0x0C000000 539 #define ELS_CMD_ADVC 0x0D000000 540 #define ELS_CMD_RTV 0x0E000000 541 #define ELS_CMD_RLS 0x0F000000 542 #define ELS_CMD_ECHO 0x10000000 543 #define ELS_CMD_TEST 0x11000000 544 #define ELS_CMD_RRQ 0x12000000 545 #define ELS_CMD_REC 0x13000000 546 #define ELS_CMD_RDP 0x18000000 547 #define ELS_CMD_PRLI 0x20100014 548 #define ELS_CMD_PRLO 0x21100014 549 #define ELS_CMD_PRLO_ACC 0x02100014 550 #define ELS_CMD_PDISC 0x50000000 551 #define ELS_CMD_FDISC 0x51000000 552 #define ELS_CMD_ADISC 0x52000000 553 #define ELS_CMD_FARP 0x54000000 554 #define ELS_CMD_FARPR 0x55000000 555 #define ELS_CMD_RPS 0x56000000 556 #define ELS_CMD_RPL 0x57000000 557 #define ELS_CMD_FAN 0x60000000 558 #define ELS_CMD_RSCN 0x61040000 559 #define ELS_CMD_SCR 0x62000000 560 #define ELS_CMD_RNID 0x78000000 561 #define ELS_CMD_LIRR 0x7A000000 562 #define ELS_CMD_LCB 0x81000000 563 #else /* __LITTLE_ENDIAN_BITFIELD */ 564 #define ELS_CMD_MASK 0xffff 565 #define ELS_RSP_MASK 0xff 566 #define ELS_CMD_LS_RJT 0x01 567 #define ELS_CMD_ACC 0x02 568 #define ELS_CMD_PLOGI 0x03 569 #define ELS_CMD_FLOGI 0x04 570 #define ELS_CMD_LOGO 0x05 571 #define ELS_CMD_ABTX 0x06 572 #define ELS_CMD_RCS 0x07 573 #define ELS_CMD_RES 0x08 574 #define ELS_CMD_RSS 0x09 575 #define ELS_CMD_RSI 0x0A 576 #define ELS_CMD_ESTS 0x0B 577 #define ELS_CMD_ESTC 0x0C 578 #define ELS_CMD_ADVC 0x0D 579 #define ELS_CMD_RTV 0x0E 580 #define ELS_CMD_RLS 0x0F 581 #define ELS_CMD_ECHO 0x10 582 #define ELS_CMD_TEST 0x11 583 #define ELS_CMD_RRQ 0x12 584 #define ELS_CMD_REC 0x13 585 #define ELS_CMD_RDP 0x18 586 #define ELS_CMD_PRLI 0x14001020 587 #define ELS_CMD_PRLO 0x14001021 588 #define ELS_CMD_PRLO_ACC 0x14001002 589 #define ELS_CMD_PDISC 0x50 590 #define ELS_CMD_FDISC 0x51 591 #define ELS_CMD_ADISC 0x52 592 #define ELS_CMD_FARP 0x54 593 #define ELS_CMD_FARPR 0x55 594 #define ELS_CMD_RPS 0x56 595 #define ELS_CMD_RPL 0x57 596 #define ELS_CMD_FAN 0x60 597 #define ELS_CMD_RSCN 0x0461 598 #define ELS_CMD_SCR 0x62 599 #define ELS_CMD_RNID 0x78 600 #define ELS_CMD_LIRR 0x7A 601 #define ELS_CMD_LCB 0x81 602 #endif 603 604 /* 605 * LS_RJT Payload Definition 606 */ 607 608 struct ls_rjt { /* Structure is in Big Endian format */ 609 union { 610 uint32_t lsRjtError; 611 struct { 612 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */ 613 614 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */ 615 /* LS_RJT reason codes */ 616 #define LSRJT_INVALID_CMD 0x01 617 #define LSRJT_LOGICAL_ERR 0x03 618 #define LSRJT_LOGICAL_BSY 0x05 619 #define LSRJT_PROTOCOL_ERR 0x07 620 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */ 621 #define LSRJT_CMD_UNSUPPORTED 0x0B 622 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */ 623 624 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */ 625 /* LS_RJT reason explanation */ 626 #define LSEXP_NOTHING_MORE 0x00 627 #define LSEXP_SPARM_OPTIONS 0x01 628 #define LSEXP_SPARM_ICTL 0x03 629 #define LSEXP_SPARM_RCTL 0x05 630 #define LSEXP_SPARM_RCV_SIZE 0x07 631 #define LSEXP_SPARM_CONCUR_SEQ 0x09 632 #define LSEXP_SPARM_CREDIT 0x0B 633 #define LSEXP_INVALID_PNAME 0x0D 634 #define LSEXP_INVALID_NNAME 0x0E 635 #define LSEXP_INVALID_CSP 0x0F 636 #define LSEXP_INVALID_ASSOC_HDR 0x11 637 #define LSEXP_ASSOC_HDR_REQ 0x13 638 #define LSEXP_INVALID_O_SID 0x15 639 #define LSEXP_INVALID_OX_RX 0x17 640 #define LSEXP_CMD_IN_PROGRESS 0x19 641 #define LSEXP_PORT_LOGIN_REQ 0x1E 642 #define LSEXP_INVALID_NPORT_ID 0x1F 643 #define LSEXP_INVALID_SEQ_ID 0x21 644 #define LSEXP_INVALID_XCHG 0x23 645 #define LSEXP_INACTIVE_XCHG 0x25 646 #define LSEXP_RQ_REQUIRED 0x27 647 #define LSEXP_OUT_OF_RESOURCE 0x29 648 #define LSEXP_CANT_GIVE_DATA 0x2A 649 #define LSEXP_REQ_UNSUPPORTED 0x2C 650 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */ 651 } b; 652 } un; 653 }; 654 655 /* 656 * N_Port Login (FLOGO/PLOGO Request) Payload Definition 657 */ 658 659 typedef struct _LOGO { /* Structure is in Big Endian format */ 660 union { 661 uint32_t nPortId32; /* Access nPortId as a word */ 662 struct { 663 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */ 664 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */ 665 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */ 666 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */ 667 } b; 668 } un; 669 struct lpfc_name portName; /* N_port name field */ 670 } LOGO; 671 672 /* 673 * FCP Login (PRLI Request / ACC) Payload Definition 674 */ 675 676 #define PRLX_PAGE_LEN 0x10 677 #define TPRLO_PAGE_LEN 0x14 678 679 typedef struct _PRLI { /* Structure is in Big Endian format */ 680 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */ 681 682 #define PRLI_FCP_TYPE 0x08 683 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 684 685 #ifdef __BIG_ENDIAN_BITFIELD 686 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 687 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 688 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 689 690 /* ACC = imagePairEstablished */ 691 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 692 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 693 #else /* __LITTLE_ENDIAN_BITFIELD */ 694 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 695 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */ 696 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */ 697 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 698 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 699 /* ACC = imagePairEstablished */ 700 #endif 701 702 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */ 703 #define PRLI_NO_RESOURCES 0x2 704 #define PRLI_INIT_INCOMPLETE 0x3 705 #define PRLI_NO_SUCH_PA 0x4 706 #define PRLI_PREDEF_CONFIG 0x5 707 #define PRLI_PARTIAL_SUCCESS 0x6 708 #define PRLI_INVALID_PAGE_CNT 0x7 709 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 710 711 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 712 713 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 714 715 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */ 716 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */ 717 718 #ifdef __BIG_ENDIAN_BITFIELD 719 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 720 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 721 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 722 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 723 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 724 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 725 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 726 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 727 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 728 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 729 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 730 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 731 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 732 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 733 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 734 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 735 #else /* __LITTLE_ENDIAN_BITFIELD */ 736 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */ 737 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */ 738 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */ 739 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */ 740 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */ 741 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */ 742 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */ 743 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */ 744 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */ 745 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */ 746 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */ 747 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */ 748 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */ 749 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */ 750 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */ 751 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */ 752 #endif 753 } PRLI; 754 755 /* 756 * FCP Logout (PRLO Request / ACC) Payload Definition 757 */ 758 759 typedef struct _PRLO { /* Structure is in Big Endian format */ 760 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */ 761 762 #define PRLO_FCP_TYPE 0x08 763 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */ 764 765 #ifdef __BIG_ENDIAN_BITFIELD 766 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 767 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 768 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 769 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 770 #else /* __LITTLE_ENDIAN_BITFIELD */ 771 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */ 772 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */ 773 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */ 774 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */ 775 #endif 776 777 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */ 778 #define PRLO_NO_SUCH_IMAGE 0x4 779 #define PRLO_INVALID_PAGE_CNT 0x7 780 781 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */ 782 783 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */ 784 785 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */ 786 787 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */ 788 } PRLO; 789 790 typedef struct _ADISC { /* Structure is in Big Endian format */ 791 uint32_t hardAL_PA; 792 struct lpfc_name portName; 793 struct lpfc_name nodeName; 794 uint32_t DID; 795 } ADISC; 796 797 typedef struct _FARP { /* Structure is in Big Endian format */ 798 uint32_t Mflags:8; 799 uint32_t Odid:24; 800 #define FARP_NO_ACTION 0 /* FARP information enclosed, no 801 action */ 802 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */ 803 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */ 804 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */ 805 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not 806 supported */ 807 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not 808 supported */ 809 uint32_t Rflags:8; 810 uint32_t Rdid:24; 811 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */ 812 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */ 813 struct lpfc_name OportName; 814 struct lpfc_name OnodeName; 815 struct lpfc_name RportName; 816 struct lpfc_name RnodeName; 817 uint8_t Oipaddr[16]; 818 uint8_t Ripaddr[16]; 819 } FARP; 820 821 typedef struct _FAN { /* Structure is in Big Endian format */ 822 uint32_t Fdid; 823 struct lpfc_name FportName; 824 struct lpfc_name FnodeName; 825 } FAN; 826 827 typedef struct _SCR { /* Structure is in Big Endian format */ 828 uint8_t resvd1; 829 uint8_t resvd2; 830 uint8_t resvd3; 831 uint8_t Function; 832 #define SCR_FUNC_FABRIC 0x01 833 #define SCR_FUNC_NPORT 0x02 834 #define SCR_FUNC_FULL 0x03 835 #define SCR_CLEAR 0xff 836 } SCR; 837 838 typedef struct _RNID_TOP_DISC { 839 struct lpfc_name portName; 840 uint8_t resvd[8]; 841 uint32_t unitType; 842 #define RNID_HBA 0x7 843 #define RNID_HOST 0xa 844 #define RNID_DRIVER 0xd 845 uint32_t physPort; 846 uint32_t attachedNodes; 847 uint16_t ipVersion; 848 #define RNID_IPV4 0x1 849 #define RNID_IPV6 0x2 850 uint16_t UDPport; 851 uint8_t ipAddr[16]; 852 uint16_t resvd1; 853 uint16_t flags; 854 #define RNID_TD_SUPPORT 0x1 855 #define RNID_LP_VALID 0x2 856 } RNID_TOP_DISC; 857 858 typedef struct _RNID { /* Structure is in Big Endian format */ 859 uint8_t Format; 860 #define RNID_TOPOLOGY_DISC 0xdf 861 uint8_t CommonLen; 862 uint8_t resvd1; 863 uint8_t SpecificLen; 864 struct lpfc_name portName; 865 struct lpfc_name nodeName; 866 union { 867 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */ 868 } un; 869 } RNID; 870 871 typedef struct _RPS { /* Structure is in Big Endian format */ 872 union { 873 uint32_t portNum; 874 struct lpfc_name portName; 875 } un; 876 } RPS; 877 878 typedef struct _RPS_RSP { /* Structure is in Big Endian format */ 879 uint16_t rsvd1; 880 uint16_t portStatus; 881 uint32_t linkFailureCnt; 882 uint32_t lossSyncCnt; 883 uint32_t lossSignalCnt; 884 uint32_t primSeqErrCnt; 885 uint32_t invalidXmitWord; 886 uint32_t crcCnt; 887 } RPS_RSP; 888 889 struct RLS { /* Structure is in Big Endian format */ 890 uint32_t rls; 891 #define rls_rsvd_SHIFT 24 892 #define rls_rsvd_MASK 0x000000ff 893 #define rls_rsvd_WORD rls 894 #define rls_did_SHIFT 0 895 #define rls_did_MASK 0x00ffffff 896 #define rls_did_WORD rls 897 }; 898 899 struct RLS_RSP { /* Structure is in Big Endian format */ 900 uint32_t linkFailureCnt; 901 uint32_t lossSyncCnt; 902 uint32_t lossSignalCnt; 903 uint32_t primSeqErrCnt; 904 uint32_t invalidXmitWord; 905 uint32_t crcCnt; 906 }; 907 908 struct RRQ { /* Structure is in Big Endian format */ 909 uint32_t rrq; 910 #define rrq_rsvd_SHIFT 24 911 #define rrq_rsvd_MASK 0x000000ff 912 #define rrq_rsvd_WORD rrq 913 #define rrq_did_SHIFT 0 914 #define rrq_did_MASK 0x00ffffff 915 #define rrq_did_WORD rrq 916 uint32_t rrq_exchg; 917 #define rrq_oxid_SHIFT 16 918 #define rrq_oxid_MASK 0xffff 919 #define rrq_oxid_WORD rrq_exchg 920 #define rrq_rxid_SHIFT 0 921 #define rrq_rxid_MASK 0xffff 922 #define rrq_rxid_WORD rrq_exchg 923 }; 924 925 #define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */ 926 #define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/ 927 928 struct RTV_RSP { /* Structure is in Big Endian format */ 929 uint32_t ratov; 930 uint32_t edtov; 931 uint32_t qtov; 932 #define qtov_rsvd0_SHIFT 28 933 #define qtov_rsvd0_MASK 0x0000000f 934 #define qtov_rsvd0_WORD qtov /* reserved */ 935 #define qtov_edtovres_SHIFT 27 936 #define qtov_edtovres_MASK 0x00000001 937 #define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */ 938 #define qtov__rsvd1_SHIFT 19 939 #define qtov_rsvd1_MASK 0x0000003f 940 #define qtov_rsvd1_WORD qtov /* reserved */ 941 #define qtov_rttov_SHIFT 18 942 #define qtov_rttov_MASK 0x00000001 943 #define qtov_rttov_WORD qtov /* R_T_TOV value */ 944 #define qtov_rsvd2_SHIFT 0 945 #define qtov_rsvd2_MASK 0x0003ffff 946 #define qtov_rsvd2_WORD qtov /* reserved */ 947 }; 948 949 950 typedef struct _RPL { /* Structure is in Big Endian format */ 951 uint32_t maxsize; 952 uint32_t index; 953 } RPL; 954 955 typedef struct _PORT_NUM_BLK { 956 uint32_t portNum; 957 uint32_t portID; 958 struct lpfc_name portName; 959 } PORT_NUM_BLK; 960 961 typedef struct _RPL_RSP { /* Structure is in Big Endian format */ 962 uint32_t listLen; 963 uint32_t index; 964 PORT_NUM_BLK port_num_blk; 965 } RPL_RSP; 966 967 /* This is used for RSCN command */ 968 typedef struct _D_ID { /* Structure is in Big Endian format */ 969 union { 970 uint32_t word; 971 struct { 972 #ifdef __BIG_ENDIAN_BITFIELD 973 uint8_t resv; 974 uint8_t domain; 975 uint8_t area; 976 uint8_t id; 977 #else /* __LITTLE_ENDIAN_BITFIELD */ 978 uint8_t id; 979 uint8_t area; 980 uint8_t domain; 981 uint8_t resv; 982 #endif 983 } b; 984 } un; 985 } D_ID; 986 987 #define RSCN_ADDRESS_FORMAT_PORT 0x0 988 #define RSCN_ADDRESS_FORMAT_AREA 0x1 989 #define RSCN_ADDRESS_FORMAT_DOMAIN 0x2 990 #define RSCN_ADDRESS_FORMAT_FABRIC 0x3 991 #define RSCN_ADDRESS_FORMAT_MASK 0x3 992 993 /* 994 * Structure to define all ELS Payload types 995 */ 996 997 typedef struct _ELS_PKT { /* Structure is in Big Endian format */ 998 uint8_t elsCode; /* FC Word 0, bit 24:31 */ 999 uint8_t elsByte1; 1000 uint8_t elsByte2; 1001 uint8_t elsByte3; 1002 union { 1003 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */ 1004 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */ 1005 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */ 1006 PRLI prli; /* Payload for PRLI/ACC */ 1007 PRLO prlo; /* Payload for PRLO/ACC */ 1008 ADISC adisc; /* Payload for ADISC/ACC */ 1009 FARP farp; /* Payload for FARP/ACC */ 1010 FAN fan; /* Payload for FAN */ 1011 SCR scr; /* Payload for SCR/ACC */ 1012 RNID rnid; /* Payload for RNID */ 1013 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */ 1014 } un; 1015 } ELS_PKT; 1016 1017 /* 1018 * Link Cable Beacon (LCB) ELS Frame 1019 */ 1020 1021 struct fc_lcb_request_frame { 1022 uint32_t lcb_command; /* ELS command opcode (0x81) */ 1023 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1024 #define LPFC_LCB_ON 0x1 1025 #define LPFC_LCB_OFF 0x2 1026 uint8_t reserved[3]; 1027 1028 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1029 #define LPFC_LCB_GREEN 0x1 1030 #define LPFC_LCB_AMBER 0x2 1031 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1032 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1033 }; 1034 1035 /* 1036 * Link Cable Beacon (LCB) ELS Response Frame 1037 */ 1038 struct fc_lcb_res_frame { 1039 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */ 1040 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */ 1041 uint8_t reserved[3]; 1042 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */ 1043 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */ 1044 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */ 1045 }; 1046 1047 /* 1048 * Read Diagnostic Parameters (RDP) ELS frame. 1049 */ 1050 #define SFF_PG0_IDENT_SFP 0x3 1051 1052 #define SFP_FLAG_PT_OPTICAL 0x0 1053 #define SFP_FLAG_PT_SWLASER 0x01 1054 #define SFP_FLAG_PT_LWLASER_LC1310 0x02 1055 #define SFP_FLAG_PT_LWLASER_LL1550 0x03 1056 #define SFP_FLAG_PT_MASK 0x0F 1057 #define SFP_FLAG_PT_SHIFT 0 1058 1059 #define SFP_FLAG_IS_OPTICAL_PORT 0x01 1060 #define SFP_FLAG_IS_OPTICAL_MASK 0x010 1061 #define SFP_FLAG_IS_OPTICAL_SHIFT 4 1062 1063 #define SFP_FLAG_IS_DESC_VALID 0x01 1064 #define SFP_FLAG_IS_DESC_VALID_MASK 0x020 1065 #define SFP_FLAG_IS_DESC_VALID_SHIFT 5 1066 1067 #define SFP_FLAG_CT_UNKNOWN 0x0 1068 #define SFP_FLAG_CT_SFP_PLUS 0x01 1069 #define SFP_FLAG_CT_MASK 0x3C 1070 #define SFP_FLAG_CT_SHIFT 6 1071 1072 struct fc_rdp_port_name_info { 1073 uint8_t wwnn[8]; 1074 uint8_t wwpn[8]; 1075 }; 1076 1077 1078 /* 1079 * Link Error Status Block Structure (FC-FS-3) for RDP 1080 * This similar to RPS ELS 1081 */ 1082 struct fc_link_status { 1083 uint32_t link_failure_cnt; 1084 uint32_t loss_of_synch_cnt; 1085 uint32_t loss_of_signal_cnt; 1086 uint32_t primitive_seq_proto_err; 1087 uint32_t invalid_trans_word; 1088 uint32_t invalid_crc_cnt; 1089 1090 }; 1091 1092 #define RDP_PORT_NAMES_DESC_TAG 0x00010003 1093 struct fc_rdp_port_name_desc { 1094 uint32_t tag; /* 0001 0003h */ 1095 uint32_t length; /* set to size of payload struct */ 1096 struct fc_rdp_port_name_info port_names; 1097 }; 1098 1099 1100 struct fc_rdp_fec_info { 1101 uint32_t CorrectedBlocks; 1102 uint32_t UncorrectableBlocks; 1103 }; 1104 1105 #define RDP_FEC_DESC_TAG 0x00010005 1106 struct fc_fec_rdp_desc { 1107 uint32_t tag; 1108 uint32_t length; 1109 struct fc_rdp_fec_info info; 1110 }; 1111 1112 struct fc_rdp_link_error_status_payload_info { 1113 struct fc_link_status link_status; /* 24 bytes */ 1114 uint32_t port_type; /* bits 31-30 only */ 1115 }; 1116 1117 #define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002 1118 struct fc_rdp_link_error_status_desc { 1119 uint32_t tag; /* 0001 0002h */ 1120 uint32_t length; /* set to size of payload struct */ 1121 struct fc_rdp_link_error_status_payload_info info; 1122 }; 1123 1124 #define VN_PT_PHY_UNKNOWN 0x00 1125 #define VN_PT_PHY_PF_PORT 0x01 1126 #define VN_PT_PHY_ETH_MAC 0x10 1127 #define VN_PT_PHY_SHIFT 30 1128 1129 #define RDP_PS_1GB 0x8000 1130 #define RDP_PS_2GB 0x4000 1131 #define RDP_PS_4GB 0x2000 1132 #define RDP_PS_10GB 0x1000 1133 #define RDP_PS_8GB 0x0800 1134 #define RDP_PS_16GB 0x0400 1135 #define RDP_PS_32GB 0x0200 1136 1137 #define RDP_CAP_USER_CONFIGURED 0x0002 1138 #define RDP_CAP_UNKNOWN 0x0001 1139 #define RDP_PS_UNKNOWN 0x0002 1140 #define RDP_PS_NOT_ESTABLISHED 0x0001 1141 1142 struct fc_rdp_port_speed { 1143 uint16_t capabilities; 1144 uint16_t speed; 1145 }; 1146 1147 struct fc_rdp_port_speed_info { 1148 struct fc_rdp_port_speed port_speed; 1149 }; 1150 1151 #define RDP_PORT_SPEED_DESC_TAG 0x00010001 1152 struct fc_rdp_port_speed_desc { 1153 uint32_t tag; /* 00010001h */ 1154 uint32_t length; /* set to size of payload struct */ 1155 struct fc_rdp_port_speed_info info; 1156 }; 1157 1158 #define RDP_NPORT_ID_SIZE 4 1159 #define RDP_N_PORT_DESC_TAG 0x00000003 1160 struct fc_rdp_nport_desc { 1161 uint32_t tag; /* 0000 0003h, big endian */ 1162 uint32_t length; /* size of RDP_N_PORT_ID struct */ 1163 uint32_t nport_id : 12; 1164 uint32_t reserved : 8; 1165 }; 1166 1167 1168 struct fc_rdp_link_service_info { 1169 uint32_t els_req; /* Request payload word 0 value.*/ 1170 }; 1171 1172 #define RDP_LINK_SERVICE_DESC_TAG 0x00000001 1173 struct fc_rdp_link_service_desc { 1174 uint32_t tag; /* Descriptor tag 1 */ 1175 uint32_t length; /* set to size of payload struct. */ 1176 struct fc_rdp_link_service_info payload; 1177 /* must be ELS req Word 0(0x18) */ 1178 }; 1179 1180 struct fc_rdp_sfp_info { 1181 uint16_t temperature; 1182 uint16_t vcc; 1183 uint16_t tx_bias; 1184 uint16_t tx_power; 1185 uint16_t rx_power; 1186 uint16_t flags; 1187 }; 1188 1189 #define RDP_SFP_DESC_TAG 0x00010000 1190 struct fc_rdp_sfp_desc { 1191 uint32_t tag; 1192 uint32_t length; /* set to size of sfp_info struct */ 1193 struct fc_rdp_sfp_info sfp_info; 1194 }; 1195 1196 /* Buffer Credit Descriptor */ 1197 struct fc_rdp_bbc_info { 1198 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */ 1199 uint32_t attached_port_bbc; 1200 uint32_t rtt; /* Round trip time */ 1201 }; 1202 #define RDP_BBC_DESC_TAG 0x00010006 1203 struct fc_rdp_bbc_desc { 1204 uint32_t tag; 1205 uint32_t length; 1206 struct fc_rdp_bbc_info bbc_info; 1207 }; 1208 1209 /* Optical Element Type Transgression Flags */ 1210 #define RDP_OET_LOW_WARNING 0x1 1211 #define RDP_OET_HIGH_WARNING 0x2 1212 #define RDP_OET_LOW_ALARM 0x4 1213 #define RDP_OET_HIGH_ALARM 0x8 1214 1215 #define RDP_OED_TEMPERATURE 0x1 1216 #define RDP_OED_VOLTAGE 0x2 1217 #define RDP_OED_TXBIAS 0x3 1218 #define RDP_OED_TXPOWER 0x4 1219 #define RDP_OED_RXPOWER 0x5 1220 1221 #define RDP_OED_TYPE_SHIFT 28 1222 /* Optical Element Data descriptor */ 1223 struct fc_rdp_oed_info { 1224 uint16_t hi_alarm; 1225 uint16_t lo_alarm; 1226 uint16_t hi_warning; 1227 uint16_t lo_warning; 1228 uint32_t function_flags; 1229 }; 1230 #define RDP_OED_DESC_TAG 0x00010007 1231 struct fc_rdp_oed_sfp_desc { 1232 uint32_t tag; 1233 uint32_t length; 1234 struct fc_rdp_oed_info oed_info; 1235 }; 1236 1237 /* Optical Product Data descriptor */ 1238 struct fc_rdp_opd_sfp_info { 1239 uint8_t vendor_name[16]; 1240 uint8_t model_number[16]; 1241 uint8_t serial_number[16]; 1242 uint8_t reserved[2]; 1243 uint8_t revision[2]; 1244 uint8_t date[8]; 1245 }; 1246 1247 #define RDP_OPD_DESC_TAG 0x00010008 1248 struct fc_rdp_opd_sfp_desc { 1249 uint32_t tag; 1250 uint32_t length; 1251 struct fc_rdp_opd_sfp_info opd_info; 1252 }; 1253 1254 struct fc_rdp_req_frame { 1255 uint32_t rdp_command; /* ELS command opcode (0x18)*/ 1256 uint32_t rdp_des_length; /* RDP Payload Word 1 */ 1257 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */ 1258 }; 1259 1260 1261 struct fc_rdp_res_frame { 1262 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */ 1263 uint32_t length; /* FC Word 1 */ 1264 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */ 1265 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */ 1266 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10-12 */ 1267 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13-21 */ 1268 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22-27 */ 1269 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28-33 */ 1270 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 34-38*/ 1271 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 39-43*/ 1272 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 44-48*/ 1273 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 49-53*/ 1274 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 54-58*/ 1275 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 59-63*/ 1276 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 64-80*/ 1277 struct fc_fec_rdp_desc fec_desc; /* FC word 81-84*/ 1278 }; 1279 1280 1281 #define RDP_DESC_PAYLOAD_SIZE (sizeof(struct fc_rdp_link_service_desc) \ 1282 + sizeof(struct fc_rdp_sfp_desc) \ 1283 + sizeof(struct fc_rdp_port_speed_desc) \ 1284 + sizeof(struct fc_rdp_link_error_status_desc) \ 1285 + (sizeof(struct fc_rdp_port_name_desc) * 2) \ 1286 + sizeof(struct fc_rdp_bbc_desc) \ 1287 + (sizeof(struct fc_rdp_oed_sfp_desc) * 5) \ 1288 + sizeof(struct fc_rdp_opd_sfp_desc)) 1289 1290 1291 /******** FDMI ********/ 1292 1293 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */ 1294 #define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */ 1295 1296 /* 1297 * Registered Port List Format 1298 */ 1299 struct lpfc_fdmi_reg_port_list { 1300 uint32_t EntryCnt; 1301 uint32_t pe; /* Variable-length array */ 1302 }; 1303 1304 1305 /* Definitions for HBA / Port attribute entries */ 1306 1307 struct lpfc_fdmi_attr_def { /* Defined in TLV format */ 1308 /* Structure is in Big Endian format */ 1309 uint32_t AttrType:16; 1310 uint32_t AttrLen:16; 1311 uint32_t AttrValue; /* Marks start of Value (ATTRIBUTE_ENTRY) */ 1312 }; 1313 1314 1315 /* Attribute Entry */ 1316 struct lpfc_fdmi_attr_entry { 1317 union { 1318 uint32_t AttrInt; 1319 uint8_t AttrTypes[32]; 1320 uint8_t AttrString[256]; 1321 struct lpfc_name AttrWWN; 1322 } un; 1323 }; 1324 1325 #define LPFC_FDMI_MAX_AE_SIZE sizeof(struct lpfc_fdmi_attr_entry) 1326 1327 /* 1328 * HBA Attribute Block 1329 */ 1330 struct lpfc_fdmi_attr_block { 1331 uint32_t EntryCnt; /* Number of HBA attribute entries */ 1332 struct lpfc_fdmi_attr_entry Entry; /* Variable-length array */ 1333 }; 1334 1335 /* 1336 * Port Entry 1337 */ 1338 struct lpfc_fdmi_port_entry { 1339 struct lpfc_name PortName; 1340 }; 1341 1342 /* 1343 * HBA Identifier 1344 */ 1345 struct lpfc_fdmi_hba_ident { 1346 struct lpfc_name PortName; 1347 }; 1348 1349 /* 1350 * Register HBA(RHBA) 1351 */ 1352 struct lpfc_fdmi_reg_hba { 1353 struct lpfc_fdmi_hba_ident hi; 1354 struct lpfc_fdmi_reg_port_list rpl; /* variable-length array */ 1355 /* struct lpfc_fdmi_attr_block ab; */ 1356 }; 1357 1358 /* 1359 * Register HBA Attributes (RHAT) 1360 */ 1361 struct lpfc_fdmi_reg_hbaattr { 1362 struct lpfc_name HBA_PortName; 1363 struct lpfc_fdmi_attr_block ab; 1364 }; 1365 1366 /* 1367 * Register Port Attributes (RPA) 1368 */ 1369 struct lpfc_fdmi_reg_portattr { 1370 struct lpfc_name PortName; 1371 struct lpfc_fdmi_attr_block ab; 1372 }; 1373 1374 /* 1375 * HBA MAnagement Operations Command Codes 1376 */ 1377 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */ 1378 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */ 1379 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */ 1380 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */ 1381 #define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */ 1382 #define SLI_MGMT_RHBA 0x200 /* Register HBA */ 1383 #define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */ 1384 #define SLI_MGMT_RPRT 0x210 /* Register Port */ 1385 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */ 1386 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */ 1387 #define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */ 1388 #define SLI_MGMT_DPRT 0x310 /* De-register Port */ 1389 #define SLI_MGMT_DPA 0x311 /* De-register Port attributes */ 1390 1391 #define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */ 1392 1393 /* 1394 * HBA Attribute Types 1395 */ 1396 #define RHBA_NODENAME 0x1 /* 8 byte WWNN */ 1397 #define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */ 1398 #define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */ 1399 #define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */ 1400 #define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */ 1401 #define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */ 1402 #define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */ 1403 #define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */ 1404 #define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */ 1405 #define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */ 1406 #define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */ 1407 #define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */ 1408 #define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */ 1409 #define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */ 1410 #define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */ 1411 #define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */ 1412 #define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */ 1413 #define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */ 1414 1415 /* Bit mask for all individual HBA attributes */ 1416 #define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001 1417 #define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002 1418 #define LPFC_FDMI_HBA_ATTR_sn 0x00000004 1419 #define LPFC_FDMI_HBA_ATTR_model 0x00000008 1420 #define LPFC_FDMI_HBA_ATTR_description 0x00000010 1421 #define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020 1422 #define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040 1423 #define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080 1424 #define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100 1425 #define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200 1426 #define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400 1427 #define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800 1428 #define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */ 1429 #define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000 1430 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000 1431 #define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000 1432 #define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */ 1433 #define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000 1434 1435 /* Bit mask for FDMI-1 defined HBA attributes */ 1436 #define LPFC_FDMI1_HBA_ATTR 0x000007ff 1437 1438 /* Bit mask for FDMI-2 defined HBA attributes */ 1439 /* Skip vendor_info and bios_state */ 1440 #define LPFC_FDMI2_HBA_ATTR 0x0002efff 1441 1442 /* 1443 * Port Attrubute Types 1444 */ 1445 #define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */ 1446 #define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */ 1447 #define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */ 1448 #define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */ 1449 #define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */ 1450 #define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */ 1451 #define RPRT_NODENAME 0x7 /* 8 byte WWNN */ 1452 #define RPRT_PORTNAME 0x8 /* 8 byte WWPN */ 1453 #define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */ 1454 #define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */ 1455 #define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */ 1456 #define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */ 1457 #define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */ 1458 #define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */ 1459 #define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */ 1460 #define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */ 1461 #define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */ 1462 #define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */ 1463 #define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */ 1464 #define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */ 1465 #define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */ 1466 #define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */ 1467 #define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */ 1468 1469 /* Bit mask for all individual PORT attributes */ 1470 #define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001 1471 #define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002 1472 #define LPFC_FDMI_PORT_ATTR_speed 0x00000004 1473 #define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008 1474 #define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010 1475 #define LPFC_FDMI_PORT_ATTR_host_name 0x00000020 1476 #define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040 1477 #define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080 1478 #define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100 1479 #define LPFC_FDMI_PORT_ATTR_port_type 0x00000200 1480 #define LPFC_FDMI_PORT_ATTR_class 0x00000400 1481 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800 1482 #define LPFC_FDMI_PORT_ATTR_port_state 0x00001000 1483 #define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000 1484 #define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000 1485 #define LPFC_FDMI_PORT_ATTR_nportid 0x00008000 1486 #define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */ 1487 #define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */ 1488 #define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */ 1489 #define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */ 1490 #define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */ 1491 #define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */ 1492 #define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */ 1493 1494 /* Bit mask for FDMI-1 defined PORT attributes */ 1495 #define LPFC_FDMI1_PORT_ATTR 0x0000003f 1496 1497 /* Bit mask for FDMI-2 defined PORT attributes */ 1498 #define LPFC_FDMI2_PORT_ATTR 0x0000ffff 1499 1500 /* Bit mask for Smart SAN defined PORT attributes */ 1501 #define LPFC_FDMI2_SMART_ATTR 0x007fffff 1502 1503 /* Defines for PORT port state attribute */ 1504 #define LPFC_FDMI_PORTSTATE_UNKNOWN 1 1505 #define LPFC_FDMI_PORTSTATE_ONLINE 2 1506 1507 /* Defines for PORT port type attribute */ 1508 #define LPFC_FDMI_PORTTYPE_UNKNOWN 0 1509 #define LPFC_FDMI_PORTTYPE_NPORT 1 1510 #define LPFC_FDMI_PORTTYPE_NLPORT 2 1511 1512 /* 1513 * Begin HBA configuration parameters. 1514 * The PCI configuration register BAR assignments are: 1515 * BAR0, offset 0x10 - SLIM base memory address 1516 * BAR1, offset 0x14 - SLIM base memory high address 1517 * BAR2, offset 0x18 - REGISTER base memory address 1518 * BAR3, offset 0x1c - REGISTER base memory high address 1519 * BAR4, offset 0x20 - BIU I/O registers 1520 * BAR5, offset 0x24 - REGISTER base io high address 1521 */ 1522 1523 /* Number of rings currently used and available. */ 1524 #define MAX_SLI3_CONFIGURED_RINGS 3 1525 #define MAX_SLI3_RINGS 4 1526 1527 /* IOCB / Mailbox is owned by FireFly */ 1528 #define OWN_CHIP 1 1529 1530 /* IOCB / Mailbox is owned by Host */ 1531 #define OWN_HOST 0 1532 1533 /* Number of 4-byte words in an IOCB. */ 1534 #define IOCB_WORD_SZ 8 1535 1536 /* network headers for Dfctl field */ 1537 #define FC_NET_HDR 0x20 1538 1539 /* Start FireFly Register definitions */ 1540 #define PCI_VENDOR_ID_EMULEX 0x10df 1541 #define PCI_DEVICE_ID_FIREFLY 0x1ae5 1542 #define PCI_DEVICE_ID_PROTEUS_VF 0xe100 1543 #define PCI_DEVICE_ID_BALIUS 0xe131 1544 #define PCI_DEVICE_ID_PROTEUS_PF 0xe180 1545 #define PCI_DEVICE_ID_LANCER_FC 0xe200 1546 #define PCI_DEVICE_ID_LANCER_FC_VF 0xe208 1547 #define PCI_DEVICE_ID_LANCER_FCOE 0xe260 1548 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268 1549 #define PCI_DEVICE_ID_LANCER_G6_FC 0xe300 1550 #define PCI_DEVICE_ID_SAT_SMB 0xf011 1551 #define PCI_DEVICE_ID_SAT_MID 0xf015 1552 #define PCI_DEVICE_ID_RFLY 0xf095 1553 #define PCI_DEVICE_ID_PFLY 0xf098 1554 #define PCI_DEVICE_ID_LP101 0xf0a1 1555 #define PCI_DEVICE_ID_TFLY 0xf0a5 1556 #define PCI_DEVICE_ID_BSMB 0xf0d1 1557 #define PCI_DEVICE_ID_BMID 0xf0d5 1558 #define PCI_DEVICE_ID_ZSMB 0xf0e1 1559 #define PCI_DEVICE_ID_ZMID 0xf0e5 1560 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5 1561 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6 1562 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7 1563 #define PCI_DEVICE_ID_SAT 0xf100 1564 #define PCI_DEVICE_ID_SAT_SCSP 0xf111 1565 #define PCI_DEVICE_ID_SAT_DCSP 0xf112 1566 #define PCI_DEVICE_ID_FALCON 0xf180 1567 #define PCI_DEVICE_ID_SUPERFLY 0xf700 1568 #define PCI_DEVICE_ID_DRAGONFLY 0xf800 1569 #define PCI_DEVICE_ID_CENTAUR 0xf900 1570 #define PCI_DEVICE_ID_PEGASUS 0xf980 1571 #define PCI_DEVICE_ID_THOR 0xfa00 1572 #define PCI_DEVICE_ID_VIPER 0xfb00 1573 #define PCI_DEVICE_ID_LP10000S 0xfc00 1574 #define PCI_DEVICE_ID_LP11000S 0xfc10 1575 #define PCI_DEVICE_ID_LPE11000S 0xfc20 1576 #define PCI_DEVICE_ID_SAT_S 0xfc40 1577 #define PCI_DEVICE_ID_PROTEUS_S 0xfc50 1578 #define PCI_DEVICE_ID_HELIOS 0xfd00 1579 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11 1580 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12 1581 #define PCI_DEVICE_ID_ZEPHYR 0xfe00 1582 #define PCI_DEVICE_ID_HORNET 0xfe05 1583 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11 1584 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12 1585 #define PCI_VENDOR_ID_SERVERENGINE 0x19a2 1586 #define PCI_DEVICE_ID_TIGERSHARK 0x0704 1587 #define PCI_DEVICE_ID_TOMCAT 0x0714 1588 #define PCI_DEVICE_ID_SKYHAWK 0x0724 1589 #define PCI_DEVICE_ID_SKYHAWK_VF 0x072c 1590 1591 #define JEDEC_ID_ADDRESS 0x0080001c 1592 #define FIREFLY_JEDEC_ID 0x1ACC 1593 #define SUPERFLY_JEDEC_ID 0x0020 1594 #define DRAGONFLY_JEDEC_ID 0x0021 1595 #define DRAGONFLY_V2_JEDEC_ID 0x0025 1596 #define CENTAUR_2G_JEDEC_ID 0x0026 1597 #define CENTAUR_1G_JEDEC_ID 0x0028 1598 #define PEGASUS_ORION_JEDEC_ID 0x0036 1599 #define PEGASUS_JEDEC_ID 0x0038 1600 #define THOR_JEDEC_ID 0x0012 1601 #define HELIOS_JEDEC_ID 0x0364 1602 #define ZEPHYR_JEDEC_ID 0x0577 1603 #define VIPER_JEDEC_ID 0x4838 1604 #define SATURN_JEDEC_ID 0x1004 1605 #define HORNET_JDEC_ID 0x2057706D 1606 1607 #define JEDEC_ID_MASK 0x0FFFF000 1608 #define JEDEC_ID_SHIFT 12 1609 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT) 1610 1611 typedef struct { /* FireFly BIU registers */ 1612 uint32_t hostAtt; /* See definitions for Host Attention 1613 register */ 1614 uint32_t chipAtt; /* See definitions for Chip Attention 1615 register */ 1616 uint32_t hostStatus; /* See definitions for Host Status register */ 1617 uint32_t hostControl; /* See definitions for Host Control register */ 1618 uint32_t buiConfig; /* See definitions for BIU configuration 1619 register */ 1620 } FF_REGS; 1621 1622 /* IO Register size in bytes */ 1623 #define FF_REG_AREA_SIZE 256 1624 1625 /* Host Attention Register */ 1626 1627 #define HA_REG_OFFSET 0 /* Byte offset from register base address */ 1628 1629 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */ 1630 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */ 1631 #define HA_R0ATT 0x00000008 /* Bit 3 */ 1632 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */ 1633 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */ 1634 #define HA_R1ATT 0x00000080 /* Bit 7 */ 1635 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */ 1636 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */ 1637 #define HA_R2ATT 0x00000800 /* Bit 11 */ 1638 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */ 1639 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */ 1640 #define HA_R3ATT 0x00008000 /* Bit 15 */ 1641 #define HA_LATT 0x20000000 /* Bit 29 */ 1642 #define HA_MBATT 0x40000000 /* Bit 30 */ 1643 #define HA_ERATT 0x80000000 /* Bit 31 */ 1644 1645 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */ 1646 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */ 1647 #define HA_RXATT 0x00000008 /* Bit 3 */ 1648 #define HA_RXMASK 0x0000000f 1649 1650 #define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT) 1651 #define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT) 1652 #define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT) 1653 #define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT) 1654 1655 #define HA_R0_POS 3 1656 #define HA_R1_POS 7 1657 #define HA_R2_POS 11 1658 #define HA_R3_POS 15 1659 #define HA_LE_POS 29 1660 #define HA_MB_POS 30 1661 #define HA_ER_POS 31 1662 /* Chip Attention Register */ 1663 1664 #define CA_REG_OFFSET 4 /* Byte offset from register base address */ 1665 1666 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */ 1667 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */ 1668 #define CA_R0ATT 0x00000008 /* Bit 3 */ 1669 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */ 1670 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */ 1671 #define CA_R1ATT 0x00000080 /* Bit 7 */ 1672 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */ 1673 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */ 1674 #define CA_R2ATT 0x00000800 /* Bit 11 */ 1675 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */ 1676 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */ 1677 #define CA_R3ATT 0x00008000 /* Bit 15 */ 1678 #define CA_MBATT 0x40000000 /* Bit 30 */ 1679 1680 /* Host Status Register */ 1681 1682 #define HS_REG_OFFSET 8 /* Byte offset from register base address */ 1683 1684 #define HS_MBRDY 0x00400000 /* Bit 22 */ 1685 #define HS_FFRDY 0x00800000 /* Bit 23 */ 1686 #define HS_FFER8 0x01000000 /* Bit 24 */ 1687 #define HS_FFER7 0x02000000 /* Bit 25 */ 1688 #define HS_FFER6 0x04000000 /* Bit 26 */ 1689 #define HS_FFER5 0x08000000 /* Bit 27 */ 1690 #define HS_FFER4 0x10000000 /* Bit 28 */ 1691 #define HS_FFER3 0x20000000 /* Bit 29 */ 1692 #define HS_FFER2 0x40000000 /* Bit 30 */ 1693 #define HS_FFER1 0x80000000 /* Bit 31 */ 1694 #define HS_CRIT_TEMP 0x00000100 /* Bit 8 */ 1695 #define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */ 1696 #define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */ 1697 /* Host Control Register */ 1698 1699 #define HC_REG_OFFSET 12 /* Byte offset from register base address */ 1700 1701 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */ 1702 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */ 1703 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */ 1704 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */ 1705 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */ 1706 #define HC_INITHBI 0x02000000 /* Bit 25 */ 1707 #define HC_INITMB 0x04000000 /* Bit 26 */ 1708 #define HC_INITFF 0x08000000 /* Bit 27 */ 1709 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */ 1710 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */ 1711 1712 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */ 1713 #define MSIX_DFLT_ID 0 1714 #define MSIX_RNG0_ID 0 1715 #define MSIX_RNG1_ID 1 1716 #define MSIX_RNG2_ID 2 1717 #define MSIX_RNG3_ID 3 1718 1719 #define MSIX_LINK_ID 4 1720 #define MSIX_MBOX_ID 5 1721 1722 #define MSIX_SPARE0_ID 6 1723 #define MSIX_SPARE1_ID 7 1724 1725 /* Mailbox Commands */ 1726 #define MBX_SHUTDOWN 0x00 /* terminate testing */ 1727 #define MBX_LOAD_SM 0x01 1728 #define MBX_READ_NV 0x02 1729 #define MBX_WRITE_NV 0x03 1730 #define MBX_RUN_BIU_DIAG 0x04 1731 #define MBX_INIT_LINK 0x05 1732 #define MBX_DOWN_LINK 0x06 1733 #define MBX_CONFIG_LINK 0x07 1734 #define MBX_CONFIG_RING 0x09 1735 #define MBX_RESET_RING 0x0A 1736 #define MBX_READ_CONFIG 0x0B 1737 #define MBX_READ_RCONFIG 0x0C 1738 #define MBX_READ_SPARM 0x0D 1739 #define MBX_READ_STATUS 0x0E 1740 #define MBX_READ_RPI 0x0F 1741 #define MBX_READ_XRI 0x10 1742 #define MBX_READ_REV 0x11 1743 #define MBX_READ_LNK_STAT 0x12 1744 #define MBX_REG_LOGIN 0x13 1745 #define MBX_UNREG_LOGIN 0x14 1746 #define MBX_CLEAR_LA 0x16 1747 #define MBX_DUMP_MEMORY 0x17 1748 #define MBX_DUMP_CONTEXT 0x18 1749 #define MBX_RUN_DIAGS 0x19 1750 #define MBX_RESTART 0x1A 1751 #define MBX_UPDATE_CFG 0x1B 1752 #define MBX_DOWN_LOAD 0x1C 1753 #define MBX_DEL_LD_ENTRY 0x1D 1754 #define MBX_RUN_PROGRAM 0x1E 1755 #define MBX_SET_MASK 0x20 1756 #define MBX_SET_VARIABLE 0x21 1757 #define MBX_UNREG_D_ID 0x23 1758 #define MBX_KILL_BOARD 0x24 1759 #define MBX_CONFIG_FARP 0x25 1760 #define MBX_BEACON 0x2A 1761 #define MBX_CONFIG_MSI 0x30 1762 #define MBX_HEARTBEAT 0x31 1763 #define MBX_WRITE_VPARMS 0x32 1764 #define MBX_ASYNCEVT_ENABLE 0x33 1765 #define MBX_READ_EVENT_LOG_STATUS 0x37 1766 #define MBX_READ_EVENT_LOG 0x38 1767 #define MBX_WRITE_EVENT_LOG 0x39 1768 1769 #define MBX_PORT_CAPABILITIES 0x3B 1770 #define MBX_PORT_IOV_CONTROL 0x3C 1771 1772 #define MBX_CONFIG_HBQ 0x7C 1773 #define MBX_LOAD_AREA 0x81 1774 #define MBX_RUN_BIU_DIAG64 0x84 1775 #define MBX_CONFIG_PORT 0x88 1776 #define MBX_READ_SPARM64 0x8D 1777 #define MBX_READ_RPI64 0x8F 1778 #define MBX_REG_LOGIN64 0x93 1779 #define MBX_READ_TOPOLOGY 0x95 1780 #define MBX_REG_VPI 0x96 1781 #define MBX_UNREG_VPI 0x97 1782 1783 #define MBX_WRITE_WWN 0x98 1784 #define MBX_SET_DEBUG 0x99 1785 #define MBX_LOAD_EXP_ROM 0x9C 1786 #define MBX_SLI4_CONFIG 0x9B 1787 #define MBX_SLI4_REQ_FTRS 0x9D 1788 #define MBX_MAX_CMDS 0x9E 1789 #define MBX_RESUME_RPI 0x9E 1790 #define MBX_SLI2_CMD_MASK 0x80 1791 #define MBX_REG_VFI 0x9F 1792 #define MBX_REG_FCFI 0xA0 1793 #define MBX_UNREG_VFI 0xA1 1794 #define MBX_UNREG_FCFI 0xA2 1795 #define MBX_INIT_VFI 0xA3 1796 #define MBX_INIT_VPI 0xA4 1797 #define MBX_ACCESS_VDATA 0xA5 1798 1799 #define MBX_AUTH_PORT 0xF8 1800 #define MBX_SECURITY_MGMT 0xF9 1801 1802 /* IOCB Commands */ 1803 1804 #define CMD_RCV_SEQUENCE_CX 0x01 1805 #define CMD_XMIT_SEQUENCE_CR 0x02 1806 #define CMD_XMIT_SEQUENCE_CX 0x03 1807 #define CMD_XMIT_BCAST_CN 0x04 1808 #define CMD_XMIT_BCAST_CX 0x05 1809 #define CMD_QUE_RING_BUF_CN 0x06 1810 #define CMD_QUE_XRI_BUF_CX 0x07 1811 #define CMD_IOCB_CONTINUE_CN 0x08 1812 #define CMD_RET_XRI_BUF_CX 0x09 1813 #define CMD_ELS_REQUEST_CR 0x0A 1814 #define CMD_ELS_REQUEST_CX 0x0B 1815 #define CMD_RCV_ELS_REQ_CX 0x0D 1816 #define CMD_ABORT_XRI_CN 0x0E 1817 #define CMD_ABORT_XRI_CX 0x0F 1818 #define CMD_CLOSE_XRI_CN 0x10 1819 #define CMD_CLOSE_XRI_CX 0x11 1820 #define CMD_CREATE_XRI_CR 0x12 1821 #define CMD_CREATE_XRI_CX 0x13 1822 #define CMD_GET_RPI_CN 0x14 1823 #define CMD_XMIT_ELS_RSP_CX 0x15 1824 #define CMD_GET_RPI_CR 0x16 1825 #define CMD_XRI_ABORTED_CX 0x17 1826 #define CMD_FCP_IWRITE_CR 0x18 1827 #define CMD_FCP_IWRITE_CX 0x19 1828 #define CMD_FCP_IREAD_CR 0x1A 1829 #define CMD_FCP_IREAD_CX 0x1B 1830 #define CMD_FCP_ICMND_CR 0x1C 1831 #define CMD_FCP_ICMND_CX 0x1D 1832 #define CMD_FCP_TSEND_CX 0x1F 1833 #define CMD_FCP_TRECEIVE_CX 0x21 1834 #define CMD_FCP_TRSP_CX 0x23 1835 #define CMD_FCP_AUTO_TRSP_CX 0x29 1836 1837 #define CMD_ADAPTER_MSG 0x20 1838 #define CMD_ADAPTER_DUMP 0x22 1839 1840 /* SLI_2 IOCB Command Set */ 1841 1842 #define CMD_ASYNC_STATUS 0x7C 1843 #define CMD_RCV_SEQUENCE64_CX 0x81 1844 #define CMD_XMIT_SEQUENCE64_CR 0x82 1845 #define CMD_XMIT_SEQUENCE64_CX 0x83 1846 #define CMD_XMIT_BCAST64_CN 0x84 1847 #define CMD_XMIT_BCAST64_CX 0x85 1848 #define CMD_QUE_RING_BUF64_CN 0x86 1849 #define CMD_QUE_XRI_BUF64_CX 0x87 1850 #define CMD_IOCB_CONTINUE64_CN 0x88 1851 #define CMD_RET_XRI_BUF64_CX 0x89 1852 #define CMD_ELS_REQUEST64_CR 0x8A 1853 #define CMD_ELS_REQUEST64_CX 0x8B 1854 #define CMD_ABORT_MXRI64_CN 0x8C 1855 #define CMD_RCV_ELS_REQ64_CX 0x8D 1856 #define CMD_XMIT_ELS_RSP64_CX 0x95 1857 #define CMD_XMIT_BLS_RSP64_CX 0x97 1858 #define CMD_FCP_IWRITE64_CR 0x98 1859 #define CMD_FCP_IWRITE64_CX 0x99 1860 #define CMD_FCP_IREAD64_CR 0x9A 1861 #define CMD_FCP_IREAD64_CX 0x9B 1862 #define CMD_FCP_ICMND64_CR 0x9C 1863 #define CMD_FCP_ICMND64_CX 0x9D 1864 #define CMD_FCP_TSEND64_CX 0x9F 1865 #define CMD_FCP_TRECEIVE64_CX 0xA1 1866 #define CMD_FCP_TRSP64_CX 0xA3 1867 1868 #define CMD_QUE_XRI64_CX 0xB3 1869 #define CMD_IOCB_RCV_SEQ64_CX 0xB5 1870 #define CMD_IOCB_RCV_ELS64_CX 0xB7 1871 #define CMD_IOCB_RET_XRI64_CX 0xB9 1872 #define CMD_IOCB_RCV_CONT64_CX 0xBB 1873 1874 #define CMD_GEN_REQUEST64_CR 0xC2 1875 #define CMD_GEN_REQUEST64_CX 0xC3 1876 1877 /* Unhandled SLI-3 Commands */ 1878 #define CMD_IOCB_XMIT_MSEQ64_CR 0xB0 1879 #define CMD_IOCB_XMIT_MSEQ64_CX 0xB1 1880 #define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1 1881 #define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD 1882 #define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6 1883 #define CMD_IOCB_ABORT_EXTENDED_CN 0xBA 1884 #define CMD_IOCB_RET_HBQE64_CN 0xCA 1885 #define CMD_IOCB_FCP_IBIDIR64_CR 0xAC 1886 #define CMD_IOCB_FCP_IBIDIR64_CX 0xAD 1887 #define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF 1888 #define CMD_IOCB_LOGENTRY_CN 0x94 1889 #define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96 1890 1891 /* Data Security SLI Commands */ 1892 #define DSSCMD_IWRITE64_CR 0xF8 1893 #define DSSCMD_IWRITE64_CX 0xF9 1894 #define DSSCMD_IREAD64_CR 0xFA 1895 #define DSSCMD_IREAD64_CX 0xFB 1896 1897 #define CMD_MAX_IOCB_CMD 0xFB 1898 #define CMD_IOCB_MASK 0xff 1899 1900 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG 1901 iocb */ 1902 #define LPFC_MAX_ADPTMSG 32 /* max msg data */ 1903 /* 1904 * Define Status 1905 */ 1906 #define MBX_SUCCESS 0 1907 #define MBXERR_NUM_RINGS 1 1908 #define MBXERR_NUM_IOCBS 2 1909 #define MBXERR_IOCBS_EXCEEDED 3 1910 #define MBXERR_BAD_RING_NUMBER 4 1911 #define MBXERR_MASK_ENTRIES_RANGE 5 1912 #define MBXERR_MASKS_EXCEEDED 6 1913 #define MBXERR_BAD_PROFILE 7 1914 #define MBXERR_BAD_DEF_CLASS 8 1915 #define MBXERR_BAD_MAX_RESPONDER 9 1916 #define MBXERR_BAD_MAX_ORIGINATOR 10 1917 #define MBXERR_RPI_REGISTERED 11 1918 #define MBXERR_RPI_FULL 12 1919 #define MBXERR_NO_RESOURCES 13 1920 #define MBXERR_BAD_RCV_LENGTH 14 1921 #define MBXERR_DMA_ERROR 15 1922 #define MBXERR_ERROR 16 1923 #define MBXERR_LINK_DOWN 0x33 1924 #define MBXERR_SEC_NO_PERMISSION 0xF02 1925 #define MBX_NOT_FINISHED 255 1926 1927 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */ 1928 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */ 1929 1930 #define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */ 1931 1932 /* 1933 * return code Fail 1934 */ 1935 #define FAILURE 1 1936 1937 /* 1938 * Begin Structure Definitions for Mailbox Commands 1939 */ 1940 1941 typedef struct { 1942 #ifdef __BIG_ENDIAN_BITFIELD 1943 uint8_t tval; 1944 uint8_t tmask; 1945 uint8_t rval; 1946 uint8_t rmask; 1947 #else /* __LITTLE_ENDIAN_BITFIELD */ 1948 uint8_t rmask; 1949 uint8_t rval; 1950 uint8_t tmask; 1951 uint8_t tval; 1952 #endif 1953 } RR_REG; 1954 1955 struct ulp_bde { 1956 uint32_t bdeAddress; 1957 #ifdef __BIG_ENDIAN_BITFIELD 1958 uint32_t bdeReserved:4; 1959 uint32_t bdeAddrHigh:4; 1960 uint32_t bdeSize:24; 1961 #else /* __LITTLE_ENDIAN_BITFIELD */ 1962 uint32_t bdeSize:24; 1963 uint32_t bdeAddrHigh:4; 1964 uint32_t bdeReserved:4; 1965 #endif 1966 }; 1967 1968 typedef struct ULP_BDL { /* SLI-2 */ 1969 #ifdef __BIG_ENDIAN_BITFIELD 1970 uint32_t bdeFlags:8; /* BDL Flags */ 1971 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1972 #else /* __LITTLE_ENDIAN_BITFIELD */ 1973 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */ 1974 uint32_t bdeFlags:8; /* BDL Flags */ 1975 #endif 1976 1977 uint32_t addrLow; /* Address 0:31 */ 1978 uint32_t addrHigh; /* Address 32:63 */ 1979 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */ 1980 } ULP_BDL; 1981 1982 /* 1983 * BlockGuard Definitions 1984 */ 1985 1986 enum lpfc_protgrp_type { 1987 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */ 1988 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */ 1989 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */ 1990 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */ 1991 }; 1992 1993 /* PDE Descriptors */ 1994 #define LPFC_PDE5_DESCRIPTOR 0x85 1995 #define LPFC_PDE6_DESCRIPTOR 0x86 1996 #define LPFC_PDE7_DESCRIPTOR 0x87 1997 1998 /* BlockGuard Opcodes */ 1999 #define BG_OP_IN_NODIF_OUT_CRC 0x0 2000 #define BG_OP_IN_CRC_OUT_NODIF 0x1 2001 #define BG_OP_IN_NODIF_OUT_CSUM 0x2 2002 #define BG_OP_IN_CSUM_OUT_NODIF 0x3 2003 #define BG_OP_IN_CRC_OUT_CRC 0x4 2004 #define BG_OP_IN_CSUM_OUT_CSUM 0x5 2005 #define BG_OP_IN_CRC_OUT_CSUM 0x6 2006 #define BG_OP_IN_CSUM_OUT_CRC 0x7 2007 #define BG_OP_RAW_MODE 0x8 2008 2009 struct lpfc_pde5 { 2010 uint32_t word0; 2011 #define pde5_type_SHIFT 24 2012 #define pde5_type_MASK 0x000000ff 2013 #define pde5_type_WORD word0 2014 #define pde5_rsvd0_SHIFT 0 2015 #define pde5_rsvd0_MASK 0x00ffffff 2016 #define pde5_rsvd0_WORD word0 2017 uint32_t reftag; /* Reference Tag Value */ 2018 uint32_t reftagtr; /* Reference Tag Translation Value */ 2019 }; 2020 2021 struct lpfc_pde6 { 2022 uint32_t word0; 2023 #define pde6_type_SHIFT 24 2024 #define pde6_type_MASK 0x000000ff 2025 #define pde6_type_WORD word0 2026 #define pde6_rsvd0_SHIFT 0 2027 #define pde6_rsvd0_MASK 0x00ffffff 2028 #define pde6_rsvd0_WORD word0 2029 uint32_t word1; 2030 #define pde6_rsvd1_SHIFT 26 2031 #define pde6_rsvd1_MASK 0x0000003f 2032 #define pde6_rsvd1_WORD word1 2033 #define pde6_na_SHIFT 25 2034 #define pde6_na_MASK 0x00000001 2035 #define pde6_na_WORD word1 2036 #define pde6_rsvd2_SHIFT 16 2037 #define pde6_rsvd2_MASK 0x000001FF 2038 #define pde6_rsvd2_WORD word1 2039 #define pde6_apptagtr_SHIFT 0 2040 #define pde6_apptagtr_MASK 0x0000ffff 2041 #define pde6_apptagtr_WORD word1 2042 uint32_t word2; 2043 #define pde6_optx_SHIFT 28 2044 #define pde6_optx_MASK 0x0000000f 2045 #define pde6_optx_WORD word2 2046 #define pde6_oprx_SHIFT 24 2047 #define pde6_oprx_MASK 0x0000000f 2048 #define pde6_oprx_WORD word2 2049 #define pde6_nr_SHIFT 23 2050 #define pde6_nr_MASK 0x00000001 2051 #define pde6_nr_WORD word2 2052 #define pde6_ce_SHIFT 22 2053 #define pde6_ce_MASK 0x00000001 2054 #define pde6_ce_WORD word2 2055 #define pde6_re_SHIFT 21 2056 #define pde6_re_MASK 0x00000001 2057 #define pde6_re_WORD word2 2058 #define pde6_ae_SHIFT 20 2059 #define pde6_ae_MASK 0x00000001 2060 #define pde6_ae_WORD word2 2061 #define pde6_ai_SHIFT 19 2062 #define pde6_ai_MASK 0x00000001 2063 #define pde6_ai_WORD word2 2064 #define pde6_bs_SHIFT 16 2065 #define pde6_bs_MASK 0x00000007 2066 #define pde6_bs_WORD word2 2067 #define pde6_apptagval_SHIFT 0 2068 #define pde6_apptagval_MASK 0x0000ffff 2069 #define pde6_apptagval_WORD word2 2070 }; 2071 2072 struct lpfc_pde7 { 2073 uint32_t word0; 2074 #define pde7_type_SHIFT 24 2075 #define pde7_type_MASK 0x000000ff 2076 #define pde7_type_WORD word0 2077 #define pde7_rsvd0_SHIFT 0 2078 #define pde7_rsvd0_MASK 0x00ffffff 2079 #define pde7_rsvd0_WORD word0 2080 uint32_t addrHigh; 2081 uint32_t addrLow; 2082 }; 2083 2084 /* Structure for MB Command LOAD_SM and DOWN_LOAD */ 2085 2086 typedef struct { 2087 #ifdef __BIG_ENDIAN_BITFIELD 2088 uint32_t rsvd2:25; 2089 uint32_t acknowledgment:1; 2090 uint32_t version:1; 2091 uint32_t erase_or_prog:1; 2092 uint32_t update_flash:1; 2093 uint32_t update_ram:1; 2094 uint32_t method:1; 2095 uint32_t load_cmplt:1; 2096 #else /* __LITTLE_ENDIAN_BITFIELD */ 2097 uint32_t load_cmplt:1; 2098 uint32_t method:1; 2099 uint32_t update_ram:1; 2100 uint32_t update_flash:1; 2101 uint32_t erase_or_prog:1; 2102 uint32_t version:1; 2103 uint32_t acknowledgment:1; 2104 uint32_t rsvd2:25; 2105 #endif 2106 2107 uint32_t dl_to_adr_low; 2108 uint32_t dl_to_adr_high; 2109 uint32_t dl_len; 2110 union { 2111 uint32_t dl_from_mbx_offset; 2112 struct ulp_bde dl_from_bde; 2113 struct ulp_bde64 dl_from_bde64; 2114 } un; 2115 2116 } LOAD_SM_VAR; 2117 2118 /* Structure for MB Command READ_NVPARM (02) */ 2119 2120 typedef struct { 2121 uint32_t rsvd1[3]; /* Read as all one's */ 2122 uint32_t rsvd2; /* Read as all zero's */ 2123 uint32_t portname[2]; /* N_PORT name */ 2124 uint32_t nodename[2]; /* NODE name */ 2125 2126 #ifdef __BIG_ENDIAN_BITFIELD 2127 uint32_t pref_DID:24; 2128 uint32_t hardAL_PA:8; 2129 #else /* __LITTLE_ENDIAN_BITFIELD */ 2130 uint32_t hardAL_PA:8; 2131 uint32_t pref_DID:24; 2132 #endif 2133 2134 uint32_t rsvd3[21]; /* Read as all one's */ 2135 } READ_NV_VAR; 2136 2137 /* Structure for MB Command WRITE_NVPARMS (03) */ 2138 2139 typedef struct { 2140 uint32_t rsvd1[3]; /* Must be all one's */ 2141 uint32_t rsvd2; /* Must be all zero's */ 2142 uint32_t portname[2]; /* N_PORT name */ 2143 uint32_t nodename[2]; /* NODE name */ 2144 2145 #ifdef __BIG_ENDIAN_BITFIELD 2146 uint32_t pref_DID:24; 2147 uint32_t hardAL_PA:8; 2148 #else /* __LITTLE_ENDIAN_BITFIELD */ 2149 uint32_t hardAL_PA:8; 2150 uint32_t pref_DID:24; 2151 #endif 2152 2153 uint32_t rsvd3[21]; /* Must be all one's */ 2154 } WRITE_NV_VAR; 2155 2156 /* Structure for MB Command RUN_BIU_DIAG (04) */ 2157 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */ 2158 2159 typedef struct { 2160 uint32_t rsvd1; 2161 union { 2162 struct { 2163 struct ulp_bde xmit_bde; 2164 struct ulp_bde rcv_bde; 2165 } s1; 2166 struct { 2167 struct ulp_bde64 xmit_bde64; 2168 struct ulp_bde64 rcv_bde64; 2169 } s2; 2170 } un; 2171 } BIU_DIAG_VAR; 2172 2173 /* Structure for MB command READ_EVENT_LOG (0x38) */ 2174 struct READ_EVENT_LOG_VAR { 2175 uint32_t word1; 2176 #define lpfc_event_log_SHIFT 29 2177 #define lpfc_event_log_MASK 0x00000001 2178 #define lpfc_event_log_WORD word1 2179 #define USE_MAILBOX_RESPONSE 1 2180 uint32_t offset; 2181 struct ulp_bde64 rcv_bde64; 2182 }; 2183 2184 /* Structure for MB Command INIT_LINK (05) */ 2185 2186 typedef struct { 2187 #ifdef __BIG_ENDIAN_BITFIELD 2188 uint32_t rsvd1:24; 2189 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2190 #else /* __LITTLE_ENDIAN_BITFIELD */ 2191 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */ 2192 uint32_t rsvd1:24; 2193 #endif 2194 2195 #ifdef __BIG_ENDIAN_BITFIELD 2196 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2197 uint8_t rsvd2; 2198 uint16_t link_flags; 2199 #else /* __LITTLE_ENDIAN_BITFIELD */ 2200 uint16_t link_flags; 2201 uint8_t rsvd2; 2202 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */ 2203 #endif 2204 2205 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */ 2206 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */ 2207 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */ 2208 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */ 2209 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */ 2210 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */ 2211 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */ 2212 2213 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */ 2214 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */ 2215 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */ 2216 2217 uint32_t link_speed; 2218 #define LINK_SPEED_AUTO 0x0 /* Auto selection */ 2219 #define LINK_SPEED_1G 0x1 /* 1 Gigabaud */ 2220 #define LINK_SPEED_2G 0x2 /* 2 Gigabaud */ 2221 #define LINK_SPEED_4G 0x4 /* 4 Gigabaud */ 2222 #define LINK_SPEED_8G 0x8 /* 8 Gigabaud */ 2223 #define LINK_SPEED_10G 0x10 /* 10 Gigabaud */ 2224 #define LINK_SPEED_16G 0x11 /* 16 Gigabaud */ 2225 #define LINK_SPEED_32G 0x14 /* 32 Gigabaud */ 2226 2227 } INIT_LINK_VAR; 2228 2229 /* Structure for MB Command DOWN_LINK (06) */ 2230 2231 typedef struct { 2232 uint32_t rsvd1; 2233 } DOWN_LINK_VAR; 2234 2235 /* Structure for MB Command CONFIG_LINK (07) */ 2236 2237 typedef struct { 2238 #ifdef __BIG_ENDIAN_BITFIELD 2239 uint32_t cr:1; 2240 uint32_t ci:1; 2241 uint32_t cr_delay:6; 2242 uint32_t cr_count:8; 2243 uint32_t rsvd1:8; 2244 uint32_t MaxBBC:8; 2245 #else /* __LITTLE_ENDIAN_BITFIELD */ 2246 uint32_t MaxBBC:8; 2247 uint32_t rsvd1:8; 2248 uint32_t cr_count:8; 2249 uint32_t cr_delay:6; 2250 uint32_t ci:1; 2251 uint32_t cr:1; 2252 #endif 2253 2254 uint32_t myId; 2255 uint32_t rsvd2; 2256 uint32_t edtov; 2257 uint32_t arbtov; 2258 uint32_t ratov; 2259 uint32_t rttov; 2260 uint32_t altov; 2261 uint32_t crtov; 2262 uint32_t citov; 2263 #ifdef __BIG_ENDIAN_BITFIELD 2264 uint32_t rrq_enable:1; 2265 uint32_t rrq_immed:1; 2266 uint32_t rsvd4:29; 2267 uint32_t ack0_enable:1; 2268 #else /* __LITTLE_ENDIAN_BITFIELD */ 2269 uint32_t ack0_enable:1; 2270 uint32_t rsvd4:29; 2271 uint32_t rrq_immed:1; 2272 uint32_t rrq_enable:1; 2273 #endif 2274 } CONFIG_LINK; 2275 2276 /* Structure for MB Command PART_SLIM (08) 2277 * will be removed since SLI1 is no longer supported! 2278 */ 2279 typedef struct { 2280 #ifdef __BIG_ENDIAN_BITFIELD 2281 uint16_t offCiocb; 2282 uint16_t numCiocb; 2283 uint16_t offRiocb; 2284 uint16_t numRiocb; 2285 #else /* __LITTLE_ENDIAN_BITFIELD */ 2286 uint16_t numCiocb; 2287 uint16_t offCiocb; 2288 uint16_t numRiocb; 2289 uint16_t offRiocb; 2290 #endif 2291 } RING_DEF; 2292 2293 typedef struct { 2294 #ifdef __BIG_ENDIAN_BITFIELD 2295 uint32_t unused1:24; 2296 uint32_t numRing:8; 2297 #else /* __LITTLE_ENDIAN_BITFIELD */ 2298 uint32_t numRing:8; 2299 uint32_t unused1:24; 2300 #endif 2301 2302 RING_DEF ringdef[4]; 2303 uint32_t hbainit; 2304 } PART_SLIM_VAR; 2305 2306 /* Structure for MB Command CONFIG_RING (09) */ 2307 2308 typedef struct { 2309 #ifdef __BIG_ENDIAN_BITFIELD 2310 uint32_t unused2:6; 2311 uint32_t recvSeq:1; 2312 uint32_t recvNotify:1; 2313 uint32_t numMask:8; 2314 uint32_t profile:8; 2315 uint32_t unused1:4; 2316 uint32_t ring:4; 2317 #else /* __LITTLE_ENDIAN_BITFIELD */ 2318 uint32_t ring:4; 2319 uint32_t unused1:4; 2320 uint32_t profile:8; 2321 uint32_t numMask:8; 2322 uint32_t recvNotify:1; 2323 uint32_t recvSeq:1; 2324 uint32_t unused2:6; 2325 #endif 2326 2327 #ifdef __BIG_ENDIAN_BITFIELD 2328 uint16_t maxRespXchg; 2329 uint16_t maxOrigXchg; 2330 #else /* __LITTLE_ENDIAN_BITFIELD */ 2331 uint16_t maxOrigXchg; 2332 uint16_t maxRespXchg; 2333 #endif 2334 2335 RR_REG rrRegs[6]; 2336 } CONFIG_RING_VAR; 2337 2338 /* Structure for MB Command RESET_RING (10) */ 2339 2340 typedef struct { 2341 uint32_t ring_no; 2342 } RESET_RING_VAR; 2343 2344 /* Structure for MB Command READ_CONFIG (11) */ 2345 2346 typedef struct { 2347 #ifdef __BIG_ENDIAN_BITFIELD 2348 uint32_t cr:1; 2349 uint32_t ci:1; 2350 uint32_t cr_delay:6; 2351 uint32_t cr_count:8; 2352 uint32_t InitBBC:8; 2353 uint32_t MaxBBC:8; 2354 #else /* __LITTLE_ENDIAN_BITFIELD */ 2355 uint32_t MaxBBC:8; 2356 uint32_t InitBBC:8; 2357 uint32_t cr_count:8; 2358 uint32_t cr_delay:6; 2359 uint32_t ci:1; 2360 uint32_t cr:1; 2361 #endif 2362 2363 #ifdef __BIG_ENDIAN_BITFIELD 2364 uint32_t topology:8; 2365 uint32_t myDid:24; 2366 #else /* __LITTLE_ENDIAN_BITFIELD */ 2367 uint32_t myDid:24; 2368 uint32_t topology:8; 2369 #endif 2370 2371 /* Defines for topology (defined previously) */ 2372 #ifdef __BIG_ENDIAN_BITFIELD 2373 uint32_t AR:1; 2374 uint32_t IR:1; 2375 uint32_t rsvd1:29; 2376 uint32_t ack0:1; 2377 #else /* __LITTLE_ENDIAN_BITFIELD */ 2378 uint32_t ack0:1; 2379 uint32_t rsvd1:29; 2380 uint32_t IR:1; 2381 uint32_t AR:1; 2382 #endif 2383 2384 uint32_t edtov; 2385 uint32_t arbtov; 2386 uint32_t ratov; 2387 uint32_t rttov; 2388 uint32_t altov; 2389 uint32_t lmt; 2390 #define LMT_RESERVED 0x000 /* Not used */ 2391 #define LMT_1Gb 0x004 2392 #define LMT_2Gb 0x008 2393 #define LMT_4Gb 0x040 2394 #define LMT_8Gb 0x080 2395 #define LMT_10Gb 0x100 2396 #define LMT_16Gb 0x200 2397 #define LMT_32Gb 0x400 2398 uint32_t rsvd2; 2399 uint32_t rsvd3; 2400 uint32_t max_xri; 2401 uint32_t max_iocb; 2402 uint32_t max_rpi; 2403 uint32_t avail_xri; 2404 uint32_t avail_iocb; 2405 uint32_t avail_rpi; 2406 uint32_t max_vpi; 2407 uint32_t rsvd4; 2408 uint32_t rsvd5; 2409 uint32_t avail_vpi; 2410 } READ_CONFIG_VAR; 2411 2412 /* Structure for MB Command READ_RCONFIG (12) */ 2413 2414 typedef struct { 2415 #ifdef __BIG_ENDIAN_BITFIELD 2416 uint32_t rsvd2:7; 2417 uint32_t recvNotify:1; 2418 uint32_t numMask:8; 2419 uint32_t profile:8; 2420 uint32_t rsvd1:4; 2421 uint32_t ring:4; 2422 #else /* __LITTLE_ENDIAN_BITFIELD */ 2423 uint32_t ring:4; 2424 uint32_t rsvd1:4; 2425 uint32_t profile:8; 2426 uint32_t numMask:8; 2427 uint32_t recvNotify:1; 2428 uint32_t rsvd2:7; 2429 #endif 2430 2431 #ifdef __BIG_ENDIAN_BITFIELD 2432 uint16_t maxResp; 2433 uint16_t maxOrig; 2434 #else /* __LITTLE_ENDIAN_BITFIELD */ 2435 uint16_t maxOrig; 2436 uint16_t maxResp; 2437 #endif 2438 2439 RR_REG rrRegs[6]; 2440 2441 #ifdef __BIG_ENDIAN_BITFIELD 2442 uint16_t cmdRingOffset; 2443 uint16_t cmdEntryCnt; 2444 uint16_t rspRingOffset; 2445 uint16_t rspEntryCnt; 2446 uint16_t nextCmdOffset; 2447 uint16_t rsvd3; 2448 uint16_t nextRspOffset; 2449 uint16_t rsvd4; 2450 #else /* __LITTLE_ENDIAN_BITFIELD */ 2451 uint16_t cmdEntryCnt; 2452 uint16_t cmdRingOffset; 2453 uint16_t rspEntryCnt; 2454 uint16_t rspRingOffset; 2455 uint16_t rsvd3; 2456 uint16_t nextCmdOffset; 2457 uint16_t rsvd4; 2458 uint16_t nextRspOffset; 2459 #endif 2460 } READ_RCONF_VAR; 2461 2462 /* Structure for MB Command READ_SPARM (13) */ 2463 /* Structure for MB Command READ_SPARM64 (0x8D) */ 2464 2465 typedef struct { 2466 uint32_t rsvd1; 2467 uint32_t rsvd2; 2468 union { 2469 struct ulp_bde sp; /* This BDE points to struct serv_parm 2470 structure */ 2471 struct ulp_bde64 sp64; 2472 } un; 2473 #ifdef __BIG_ENDIAN_BITFIELD 2474 uint16_t rsvd3; 2475 uint16_t vpi; 2476 #else /* __LITTLE_ENDIAN_BITFIELD */ 2477 uint16_t vpi; 2478 uint16_t rsvd3; 2479 #endif 2480 } READ_SPARM_VAR; 2481 2482 /* Structure for MB Command READ_STATUS (14) */ 2483 2484 typedef struct { 2485 #ifdef __BIG_ENDIAN_BITFIELD 2486 uint32_t rsvd1:31; 2487 uint32_t clrCounters:1; 2488 uint16_t activeXriCnt; 2489 uint16_t activeRpiCnt; 2490 #else /* __LITTLE_ENDIAN_BITFIELD */ 2491 uint32_t clrCounters:1; 2492 uint32_t rsvd1:31; 2493 uint16_t activeRpiCnt; 2494 uint16_t activeXriCnt; 2495 #endif 2496 2497 uint32_t xmitByteCnt; 2498 uint32_t rcvByteCnt; 2499 uint32_t xmitFrameCnt; 2500 uint32_t rcvFrameCnt; 2501 uint32_t xmitSeqCnt; 2502 uint32_t rcvSeqCnt; 2503 uint32_t totalOrigExchanges; 2504 uint32_t totalRespExchanges; 2505 uint32_t rcvPbsyCnt; 2506 uint32_t rcvFbsyCnt; 2507 } READ_STATUS_VAR; 2508 2509 /* Structure for MB Command READ_RPI (15) */ 2510 /* Structure for MB Command READ_RPI64 (0x8F) */ 2511 2512 typedef struct { 2513 #ifdef __BIG_ENDIAN_BITFIELD 2514 uint16_t nextRpi; 2515 uint16_t reqRpi; 2516 uint32_t rsvd2:8; 2517 uint32_t DID:24; 2518 #else /* __LITTLE_ENDIAN_BITFIELD */ 2519 uint16_t reqRpi; 2520 uint16_t nextRpi; 2521 uint32_t DID:24; 2522 uint32_t rsvd2:8; 2523 #endif 2524 2525 union { 2526 struct ulp_bde sp; 2527 struct ulp_bde64 sp64; 2528 } un; 2529 2530 } READ_RPI_VAR; 2531 2532 /* Structure for MB Command READ_XRI (16) */ 2533 2534 typedef struct { 2535 #ifdef __BIG_ENDIAN_BITFIELD 2536 uint16_t nextXri; 2537 uint16_t reqXri; 2538 uint16_t rsvd1; 2539 uint16_t rpi; 2540 uint32_t rsvd2:8; 2541 uint32_t DID:24; 2542 uint32_t rsvd3:8; 2543 uint32_t SID:24; 2544 uint32_t rsvd4; 2545 uint8_t seqId; 2546 uint8_t rsvd5; 2547 uint16_t seqCount; 2548 uint16_t oxId; 2549 uint16_t rxId; 2550 uint32_t rsvd6:30; 2551 uint32_t si:1; 2552 uint32_t exchOrig:1; 2553 #else /* __LITTLE_ENDIAN_BITFIELD */ 2554 uint16_t reqXri; 2555 uint16_t nextXri; 2556 uint16_t rpi; 2557 uint16_t rsvd1; 2558 uint32_t DID:24; 2559 uint32_t rsvd2:8; 2560 uint32_t SID:24; 2561 uint32_t rsvd3:8; 2562 uint32_t rsvd4; 2563 uint16_t seqCount; 2564 uint8_t rsvd5; 2565 uint8_t seqId; 2566 uint16_t rxId; 2567 uint16_t oxId; 2568 uint32_t exchOrig:1; 2569 uint32_t si:1; 2570 uint32_t rsvd6:30; 2571 #endif 2572 } READ_XRI_VAR; 2573 2574 /* Structure for MB Command READ_REV (17) */ 2575 2576 typedef struct { 2577 #ifdef __BIG_ENDIAN_BITFIELD 2578 uint32_t cv:1; 2579 uint32_t rr:1; 2580 uint32_t rsvd2:2; 2581 uint32_t v3req:1; 2582 uint32_t v3rsp:1; 2583 uint32_t rsvd1:25; 2584 uint32_t rv:1; 2585 #else /* __LITTLE_ENDIAN_BITFIELD */ 2586 uint32_t rv:1; 2587 uint32_t rsvd1:25; 2588 uint32_t v3rsp:1; 2589 uint32_t v3req:1; 2590 uint32_t rsvd2:2; 2591 uint32_t rr:1; 2592 uint32_t cv:1; 2593 #endif 2594 2595 uint32_t biuRev; 2596 uint32_t smRev; 2597 union { 2598 uint32_t smFwRev; 2599 struct { 2600 #ifdef __BIG_ENDIAN_BITFIELD 2601 uint8_t ProgType; 2602 uint8_t ProgId; 2603 uint16_t ProgVer:4; 2604 uint16_t ProgRev:4; 2605 uint16_t ProgFixLvl:2; 2606 uint16_t ProgDistType:2; 2607 uint16_t DistCnt:4; 2608 #else /* __LITTLE_ENDIAN_BITFIELD */ 2609 uint16_t DistCnt:4; 2610 uint16_t ProgDistType:2; 2611 uint16_t ProgFixLvl:2; 2612 uint16_t ProgRev:4; 2613 uint16_t ProgVer:4; 2614 uint8_t ProgId; 2615 uint8_t ProgType; 2616 #endif 2617 2618 } b; 2619 } un; 2620 uint32_t endecRev; 2621 #ifdef __BIG_ENDIAN_BITFIELD 2622 uint8_t feaLevelHigh; 2623 uint8_t feaLevelLow; 2624 uint8_t fcphHigh; 2625 uint8_t fcphLow; 2626 #else /* __LITTLE_ENDIAN_BITFIELD */ 2627 uint8_t fcphLow; 2628 uint8_t fcphHigh; 2629 uint8_t feaLevelLow; 2630 uint8_t feaLevelHigh; 2631 #endif 2632 2633 uint32_t postKernRev; 2634 uint32_t opFwRev; 2635 uint8_t opFwName[16]; 2636 uint32_t sli1FwRev; 2637 uint8_t sli1FwName[16]; 2638 uint32_t sli2FwRev; 2639 uint8_t sli2FwName[16]; 2640 uint32_t sli3Feat; 2641 uint32_t RandomData[6]; 2642 } READ_REV_VAR; 2643 2644 /* Structure for MB Command READ_LINK_STAT (18) */ 2645 2646 typedef struct { 2647 uint32_t word0; 2648 2649 #define lpfc_read_link_stat_rec_SHIFT 0 2650 #define lpfc_read_link_stat_rec_MASK 0x1 2651 #define lpfc_read_link_stat_rec_WORD word0 2652 2653 #define lpfc_read_link_stat_gec_SHIFT 1 2654 #define lpfc_read_link_stat_gec_MASK 0x1 2655 #define lpfc_read_link_stat_gec_WORD word0 2656 2657 #define lpfc_read_link_stat_w02oftow23of_SHIFT 2 2658 #define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF 2659 #define lpfc_read_link_stat_w02oftow23of_WORD word0 2660 2661 #define lpfc_read_link_stat_rsvd_SHIFT 24 2662 #define lpfc_read_link_stat_rsvd_MASK 0x1F 2663 #define lpfc_read_link_stat_rsvd_WORD word0 2664 2665 #define lpfc_read_link_stat_gec2_SHIFT 29 2666 #define lpfc_read_link_stat_gec2_MASK 0x1 2667 #define lpfc_read_link_stat_gec2_WORD word0 2668 2669 #define lpfc_read_link_stat_clrc_SHIFT 30 2670 #define lpfc_read_link_stat_clrc_MASK 0x1 2671 #define lpfc_read_link_stat_clrc_WORD word0 2672 2673 #define lpfc_read_link_stat_clof_SHIFT 31 2674 #define lpfc_read_link_stat_clof_MASK 0x1 2675 #define lpfc_read_link_stat_clof_WORD word0 2676 2677 uint32_t linkFailureCnt; 2678 uint32_t lossSyncCnt; 2679 uint32_t lossSignalCnt; 2680 uint32_t primSeqErrCnt; 2681 uint32_t invalidXmitWord; 2682 uint32_t crcCnt; 2683 uint32_t primSeqTimeout; 2684 uint32_t elasticOverrun; 2685 uint32_t arbTimeout; 2686 uint32_t advRecBufCredit; 2687 uint32_t curRecBufCredit; 2688 uint32_t advTransBufCredit; 2689 uint32_t curTransBufCredit; 2690 uint32_t recEofCount; 2691 uint32_t recEofdtiCount; 2692 uint32_t recEofniCount; 2693 uint32_t recSofcount; 2694 uint32_t rsvd1; 2695 uint32_t rsvd2; 2696 uint32_t recDrpXriCount; 2697 uint32_t fecCorrBlkCount; 2698 uint32_t fecUncorrBlkCount; 2699 } READ_LNK_VAR; 2700 2701 /* Structure for MB Command REG_LOGIN (19) */ 2702 /* Structure for MB Command REG_LOGIN64 (0x93) */ 2703 2704 typedef struct { 2705 #ifdef __BIG_ENDIAN_BITFIELD 2706 uint16_t rsvd1; 2707 uint16_t rpi; 2708 uint32_t rsvd2:8; 2709 uint32_t did:24; 2710 #else /* __LITTLE_ENDIAN_BITFIELD */ 2711 uint16_t rpi; 2712 uint16_t rsvd1; 2713 uint32_t did:24; 2714 uint32_t rsvd2:8; 2715 #endif 2716 2717 union { 2718 struct ulp_bde sp; 2719 struct ulp_bde64 sp64; 2720 } un; 2721 2722 #ifdef __BIG_ENDIAN_BITFIELD 2723 uint16_t rsvd6; 2724 uint16_t vpi; 2725 #else /* __LITTLE_ENDIAN_BITFIELD */ 2726 uint16_t vpi; 2727 uint16_t rsvd6; 2728 #endif 2729 2730 } REG_LOGIN_VAR; 2731 2732 /* Word 30 contents for REG_LOGIN */ 2733 typedef union { 2734 struct { 2735 #ifdef __BIG_ENDIAN_BITFIELD 2736 uint16_t rsvd1:12; 2737 uint16_t wd30_class:4; 2738 uint16_t xri; 2739 #else /* __LITTLE_ENDIAN_BITFIELD */ 2740 uint16_t xri; 2741 uint16_t wd30_class:4; 2742 uint16_t rsvd1:12; 2743 #endif 2744 } f; 2745 uint32_t word; 2746 } REG_WD30; 2747 2748 /* Structure for MB Command UNREG_LOGIN (20) */ 2749 2750 typedef struct { 2751 #ifdef __BIG_ENDIAN_BITFIELD 2752 uint16_t rsvd1; 2753 uint16_t rpi; 2754 uint32_t rsvd2; 2755 uint32_t rsvd3; 2756 uint32_t rsvd4; 2757 uint32_t rsvd5; 2758 uint16_t rsvd6; 2759 uint16_t vpi; 2760 #else /* __LITTLE_ENDIAN_BITFIELD */ 2761 uint16_t rpi; 2762 uint16_t rsvd1; 2763 uint32_t rsvd2; 2764 uint32_t rsvd3; 2765 uint32_t rsvd4; 2766 uint32_t rsvd5; 2767 uint16_t vpi; 2768 uint16_t rsvd6; 2769 #endif 2770 } UNREG_LOGIN_VAR; 2771 2772 /* Structure for MB Command REG_VPI (0x96) */ 2773 typedef struct { 2774 #ifdef __BIG_ENDIAN_BITFIELD 2775 uint32_t rsvd1; 2776 uint32_t rsvd2:7; 2777 uint32_t upd:1; 2778 uint32_t sid:24; 2779 uint32_t wwn[2]; 2780 uint32_t rsvd5; 2781 uint16_t vfi; 2782 uint16_t vpi; 2783 #else /* __LITTLE_ENDIAN */ 2784 uint32_t rsvd1; 2785 uint32_t sid:24; 2786 uint32_t upd:1; 2787 uint32_t rsvd2:7; 2788 uint32_t wwn[2]; 2789 uint32_t rsvd5; 2790 uint16_t vpi; 2791 uint16_t vfi; 2792 #endif 2793 } REG_VPI_VAR; 2794 2795 /* Structure for MB Command UNREG_VPI (0x97) */ 2796 typedef struct { 2797 uint32_t rsvd1; 2798 #ifdef __BIG_ENDIAN_BITFIELD 2799 uint16_t rsvd2; 2800 uint16_t sli4_vpi; 2801 #else /* __LITTLE_ENDIAN */ 2802 uint16_t sli4_vpi; 2803 uint16_t rsvd2; 2804 #endif 2805 uint32_t rsvd3; 2806 uint32_t rsvd4; 2807 uint32_t rsvd5; 2808 #ifdef __BIG_ENDIAN_BITFIELD 2809 uint16_t rsvd6; 2810 uint16_t vpi; 2811 #else /* __LITTLE_ENDIAN */ 2812 uint16_t vpi; 2813 uint16_t rsvd6; 2814 #endif 2815 } UNREG_VPI_VAR; 2816 2817 /* Structure for MB Command UNREG_D_ID (0x23) */ 2818 2819 typedef struct { 2820 uint32_t did; 2821 uint32_t rsvd2; 2822 uint32_t rsvd3; 2823 uint32_t rsvd4; 2824 uint32_t rsvd5; 2825 #ifdef __BIG_ENDIAN_BITFIELD 2826 uint16_t rsvd6; 2827 uint16_t vpi; 2828 #else 2829 uint16_t vpi; 2830 uint16_t rsvd6; 2831 #endif 2832 } UNREG_D_ID_VAR; 2833 2834 /* Structure for MB Command READ_TOPOLOGY (0x95) */ 2835 struct lpfc_mbx_read_top { 2836 uint32_t eventTag; /* Event tag */ 2837 uint32_t word2; 2838 #define lpfc_mbx_read_top_fa_SHIFT 12 2839 #define lpfc_mbx_read_top_fa_MASK 0x00000001 2840 #define lpfc_mbx_read_top_fa_WORD word2 2841 #define lpfc_mbx_read_top_mm_SHIFT 11 2842 #define lpfc_mbx_read_top_mm_MASK 0x00000001 2843 #define lpfc_mbx_read_top_mm_WORD word2 2844 #define lpfc_mbx_read_top_pb_SHIFT 9 2845 #define lpfc_mbx_read_top_pb_MASK 0X00000001 2846 #define lpfc_mbx_read_top_pb_WORD word2 2847 #define lpfc_mbx_read_top_il_SHIFT 8 2848 #define lpfc_mbx_read_top_il_MASK 0x00000001 2849 #define lpfc_mbx_read_top_il_WORD word2 2850 #define lpfc_mbx_read_top_att_type_SHIFT 0 2851 #define lpfc_mbx_read_top_att_type_MASK 0x000000FF 2852 #define lpfc_mbx_read_top_att_type_WORD word2 2853 #define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */ 2854 #define LPFC_ATT_LINK_UP 0x01 /* Link is up */ 2855 #define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */ 2856 uint32_t word3; 2857 #define lpfc_mbx_read_top_alpa_granted_SHIFT 24 2858 #define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF 2859 #define lpfc_mbx_read_top_alpa_granted_WORD word3 2860 #define lpfc_mbx_read_top_lip_alps_SHIFT 16 2861 #define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF 2862 #define lpfc_mbx_read_top_lip_alps_WORD word3 2863 #define lpfc_mbx_read_top_lip_type_SHIFT 8 2864 #define lpfc_mbx_read_top_lip_type_MASK 0x000000FF 2865 #define lpfc_mbx_read_top_lip_type_WORD word3 2866 #define lpfc_mbx_read_top_topology_SHIFT 0 2867 #define lpfc_mbx_read_top_topology_MASK 0x000000FF 2868 #define lpfc_mbx_read_top_topology_WORD word3 2869 #define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */ 2870 #define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */ 2871 #define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */ 2872 /* store the LILP AL_PA position map into */ 2873 struct ulp_bde64 lilpBde64; 2874 #define LPFC_ALPA_MAP_SIZE 128 2875 uint32_t word7; 2876 #define lpfc_mbx_read_top_ld_lu_SHIFT 31 2877 #define lpfc_mbx_read_top_ld_lu_MASK 0x00000001 2878 #define lpfc_mbx_read_top_ld_lu_WORD word7 2879 #define lpfc_mbx_read_top_ld_tf_SHIFT 30 2880 #define lpfc_mbx_read_top_ld_tf_MASK 0x00000001 2881 #define lpfc_mbx_read_top_ld_tf_WORD word7 2882 #define lpfc_mbx_read_top_ld_link_spd_SHIFT 8 2883 #define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF 2884 #define lpfc_mbx_read_top_ld_link_spd_WORD word7 2885 #define lpfc_mbx_read_top_ld_nl_port_SHIFT 4 2886 #define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F 2887 #define lpfc_mbx_read_top_ld_nl_port_WORD word7 2888 #define lpfc_mbx_read_top_ld_tx_SHIFT 2 2889 #define lpfc_mbx_read_top_ld_tx_MASK 0x00000003 2890 #define lpfc_mbx_read_top_ld_tx_WORD word7 2891 #define lpfc_mbx_read_top_ld_rx_SHIFT 0 2892 #define lpfc_mbx_read_top_ld_rx_MASK 0x00000003 2893 #define lpfc_mbx_read_top_ld_rx_WORD word7 2894 uint32_t word8; 2895 #define lpfc_mbx_read_top_lu_SHIFT 31 2896 #define lpfc_mbx_read_top_lu_MASK 0x00000001 2897 #define lpfc_mbx_read_top_lu_WORD word8 2898 #define lpfc_mbx_read_top_tf_SHIFT 30 2899 #define lpfc_mbx_read_top_tf_MASK 0x00000001 2900 #define lpfc_mbx_read_top_tf_WORD word8 2901 #define lpfc_mbx_read_top_link_spd_SHIFT 8 2902 #define lpfc_mbx_read_top_link_spd_MASK 0x000000FF 2903 #define lpfc_mbx_read_top_link_spd_WORD word8 2904 #define lpfc_mbx_read_top_nl_port_SHIFT 4 2905 #define lpfc_mbx_read_top_nl_port_MASK 0x0000000F 2906 #define lpfc_mbx_read_top_nl_port_WORD word8 2907 #define lpfc_mbx_read_top_tx_SHIFT 2 2908 #define lpfc_mbx_read_top_tx_MASK 0x00000003 2909 #define lpfc_mbx_read_top_tx_WORD word8 2910 #define lpfc_mbx_read_top_rx_SHIFT 0 2911 #define lpfc_mbx_read_top_rx_MASK 0x00000003 2912 #define lpfc_mbx_read_top_rx_WORD word8 2913 #define LPFC_LINK_SPEED_UNKNOWN 0x0 2914 #define LPFC_LINK_SPEED_1GHZ 0x04 2915 #define LPFC_LINK_SPEED_2GHZ 0x08 2916 #define LPFC_LINK_SPEED_4GHZ 0x10 2917 #define LPFC_LINK_SPEED_8GHZ 0x20 2918 #define LPFC_LINK_SPEED_10GHZ 0x40 2919 #define LPFC_LINK_SPEED_16GHZ 0x80 2920 #define LPFC_LINK_SPEED_32GHZ 0x90 2921 }; 2922 2923 /* Structure for MB Command CLEAR_LA (22) */ 2924 2925 typedef struct { 2926 uint32_t eventTag; /* Event tag */ 2927 uint32_t rsvd1; 2928 } CLEAR_LA_VAR; 2929 2930 /* Structure for MB Command DUMP */ 2931 2932 typedef struct { 2933 #ifdef __BIG_ENDIAN_BITFIELD 2934 uint32_t rsvd:25; 2935 uint32_t ra:1; 2936 uint32_t co:1; 2937 uint32_t cv:1; 2938 uint32_t type:4; 2939 uint32_t entry_index:16; 2940 uint32_t region_id:16; 2941 #else /* __LITTLE_ENDIAN_BITFIELD */ 2942 uint32_t type:4; 2943 uint32_t cv:1; 2944 uint32_t co:1; 2945 uint32_t ra:1; 2946 uint32_t rsvd:25; 2947 uint32_t region_id:16; 2948 uint32_t entry_index:16; 2949 #endif 2950 2951 uint32_t sli4_length; 2952 uint32_t word_cnt; 2953 uint32_t resp_offset; 2954 } DUMP_VAR; 2955 2956 #define DMP_MEM_REG 0x1 2957 #define DMP_NV_PARAMS 0x2 2958 #define DMP_LMSD 0x3 /* Link Module Serial Data */ 2959 #define DMP_WELL_KNOWN 0x4 2960 2961 #define DMP_REGION_VPD 0xe 2962 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */ 2963 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */ 2964 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */ 2965 2966 #define DMP_REGION_VPORT 0x16 /* VPort info region */ 2967 #define DMP_VPORT_REGION_SIZE 0x200 2968 #define DMP_MBOX_OFFSET_WORD 0x5 2969 2970 #define DMP_REGION_23 0x17 /* fcoe param and port state region */ 2971 #define DMP_RGN23_SIZE 0x400 2972 2973 #define WAKE_UP_PARMS_REGION_ID 4 2974 #define WAKE_UP_PARMS_WORD_SIZE 15 2975 2976 struct vport_rec { 2977 uint8_t wwpn[8]; 2978 uint8_t wwnn[8]; 2979 }; 2980 2981 #define VPORT_INFO_SIG 0x32324752 2982 #define VPORT_INFO_REV_MASK 0xff 2983 #define VPORT_INFO_REV 0x1 2984 #define MAX_STATIC_VPORT_COUNT 16 2985 struct static_vport_info { 2986 uint32_t signature; 2987 uint32_t rev; 2988 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT]; 2989 uint32_t resvd[66]; 2990 }; 2991 2992 /* Option rom version structure */ 2993 struct prog_id { 2994 #ifdef __BIG_ENDIAN_BITFIELD 2995 uint8_t type; 2996 uint8_t id; 2997 uint32_t ver:4; /* Major Version */ 2998 uint32_t rev:4; /* Revision */ 2999 uint32_t lev:2; /* Level */ 3000 uint32_t dist:2; /* Dist Type */ 3001 uint32_t num:4; /* number after dist type */ 3002 #else /* __LITTLE_ENDIAN_BITFIELD */ 3003 uint32_t num:4; /* number after dist type */ 3004 uint32_t dist:2; /* Dist Type */ 3005 uint32_t lev:2; /* Level */ 3006 uint32_t rev:4; /* Revision */ 3007 uint32_t ver:4; /* Major Version */ 3008 uint8_t id; 3009 uint8_t type; 3010 #endif 3011 }; 3012 3013 /* Structure for MB Command UPDATE_CFG (0x1B) */ 3014 3015 struct update_cfg_var { 3016 #ifdef __BIG_ENDIAN_BITFIELD 3017 uint32_t rsvd2:16; 3018 uint32_t type:8; 3019 uint32_t rsvd:1; 3020 uint32_t ra:1; 3021 uint32_t co:1; 3022 uint32_t cv:1; 3023 uint32_t req:4; 3024 uint32_t entry_length:16; 3025 uint32_t region_id:16; 3026 #else /* __LITTLE_ENDIAN_BITFIELD */ 3027 uint32_t req:4; 3028 uint32_t cv:1; 3029 uint32_t co:1; 3030 uint32_t ra:1; 3031 uint32_t rsvd:1; 3032 uint32_t type:8; 3033 uint32_t rsvd2:16; 3034 uint32_t region_id:16; 3035 uint32_t entry_length:16; 3036 #endif 3037 3038 uint32_t resp_info; 3039 uint32_t byte_cnt; 3040 uint32_t data_offset; 3041 }; 3042 3043 struct hbq_mask { 3044 #ifdef __BIG_ENDIAN_BITFIELD 3045 uint8_t tmatch; 3046 uint8_t tmask; 3047 uint8_t rctlmatch; 3048 uint8_t rctlmask; 3049 #else /* __LITTLE_ENDIAN */ 3050 uint8_t rctlmask; 3051 uint8_t rctlmatch; 3052 uint8_t tmask; 3053 uint8_t tmatch; 3054 #endif 3055 }; 3056 3057 3058 /* Structure for MB Command CONFIG_HBQ (7c) */ 3059 3060 struct config_hbq_var { 3061 #ifdef __BIG_ENDIAN_BITFIELD 3062 uint32_t rsvd1 :7; 3063 uint32_t recvNotify :1; /* Receive Notification */ 3064 uint32_t numMask :8; /* # Mask Entries */ 3065 uint32_t profile :8; /* Selection Profile */ 3066 uint32_t rsvd2 :8; 3067 #else /* __LITTLE_ENDIAN */ 3068 uint32_t rsvd2 :8; 3069 uint32_t profile :8; /* Selection Profile */ 3070 uint32_t numMask :8; /* # Mask Entries */ 3071 uint32_t recvNotify :1; /* Receive Notification */ 3072 uint32_t rsvd1 :7; 3073 #endif 3074 3075 #ifdef __BIG_ENDIAN_BITFIELD 3076 uint32_t hbqId :16; 3077 uint32_t rsvd3 :12; 3078 uint32_t ringMask :4; 3079 #else /* __LITTLE_ENDIAN */ 3080 uint32_t ringMask :4; 3081 uint32_t rsvd3 :12; 3082 uint32_t hbqId :16; 3083 #endif 3084 3085 #ifdef __BIG_ENDIAN_BITFIELD 3086 uint32_t entry_count :16; 3087 uint32_t rsvd4 :8; 3088 uint32_t headerLen :8; 3089 #else /* __LITTLE_ENDIAN */ 3090 uint32_t headerLen :8; 3091 uint32_t rsvd4 :8; 3092 uint32_t entry_count :16; 3093 #endif 3094 3095 uint32_t hbqaddrLow; 3096 uint32_t hbqaddrHigh; 3097 3098 #ifdef __BIG_ENDIAN_BITFIELD 3099 uint32_t rsvd5 :31; 3100 uint32_t logEntry :1; 3101 #else /* __LITTLE_ENDIAN */ 3102 uint32_t logEntry :1; 3103 uint32_t rsvd5 :31; 3104 #endif 3105 3106 uint32_t rsvd6; /* w7 */ 3107 uint32_t rsvd7; /* w8 */ 3108 uint32_t rsvd8; /* w9 */ 3109 3110 struct hbq_mask hbqMasks[6]; 3111 3112 3113 union { 3114 uint32_t allprofiles[12]; 3115 3116 struct { 3117 #ifdef __BIG_ENDIAN_BITFIELD 3118 uint32_t seqlenoff :16; 3119 uint32_t maxlen :16; 3120 #else /* __LITTLE_ENDIAN */ 3121 uint32_t maxlen :16; 3122 uint32_t seqlenoff :16; 3123 #endif 3124 #ifdef __BIG_ENDIAN_BITFIELD 3125 uint32_t rsvd1 :28; 3126 uint32_t seqlenbcnt :4; 3127 #else /* __LITTLE_ENDIAN */ 3128 uint32_t seqlenbcnt :4; 3129 uint32_t rsvd1 :28; 3130 #endif 3131 uint32_t rsvd[10]; 3132 } profile2; 3133 3134 struct { 3135 #ifdef __BIG_ENDIAN_BITFIELD 3136 uint32_t seqlenoff :16; 3137 uint32_t maxlen :16; 3138 #else /* __LITTLE_ENDIAN */ 3139 uint32_t maxlen :16; 3140 uint32_t seqlenoff :16; 3141 #endif 3142 #ifdef __BIG_ENDIAN_BITFIELD 3143 uint32_t cmdcodeoff :28; 3144 uint32_t rsvd1 :12; 3145 uint32_t seqlenbcnt :4; 3146 #else /* __LITTLE_ENDIAN */ 3147 uint32_t seqlenbcnt :4; 3148 uint32_t rsvd1 :12; 3149 uint32_t cmdcodeoff :28; 3150 #endif 3151 uint32_t cmdmatch[8]; 3152 3153 uint32_t rsvd[2]; 3154 } profile3; 3155 3156 struct { 3157 #ifdef __BIG_ENDIAN_BITFIELD 3158 uint32_t seqlenoff :16; 3159 uint32_t maxlen :16; 3160 #else /* __LITTLE_ENDIAN */ 3161 uint32_t maxlen :16; 3162 uint32_t seqlenoff :16; 3163 #endif 3164 #ifdef __BIG_ENDIAN_BITFIELD 3165 uint32_t cmdcodeoff :28; 3166 uint32_t rsvd1 :12; 3167 uint32_t seqlenbcnt :4; 3168 #else /* __LITTLE_ENDIAN */ 3169 uint32_t seqlenbcnt :4; 3170 uint32_t rsvd1 :12; 3171 uint32_t cmdcodeoff :28; 3172 #endif 3173 uint32_t cmdmatch[8]; 3174 3175 uint32_t rsvd[2]; 3176 } profile5; 3177 3178 } profiles; 3179 3180 }; 3181 3182 3183 3184 /* Structure for MB Command CONFIG_PORT (0x88) */ 3185 typedef struct { 3186 #ifdef __BIG_ENDIAN_BITFIELD 3187 uint32_t cBE : 1; 3188 uint32_t cET : 1; 3189 uint32_t cHpcb : 1; 3190 uint32_t cMA : 1; 3191 uint32_t sli_mode : 4; 3192 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3193 * config block */ 3194 #else /* __LITTLE_ENDIAN */ 3195 uint32_t pcbLen : 24; /* bit 23:0 of memory based port 3196 * config block */ 3197 uint32_t sli_mode : 4; 3198 uint32_t cMA : 1; 3199 uint32_t cHpcb : 1; 3200 uint32_t cET : 1; 3201 uint32_t cBE : 1; 3202 #endif 3203 3204 uint32_t pcbLow; /* bit 31:0 of memory based port config block */ 3205 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */ 3206 uint32_t hbainit[5]; 3207 #ifdef __BIG_ENDIAN_BITFIELD 3208 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3209 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3210 #else /* __LITTLE_ENDIAN */ 3211 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */ 3212 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */ 3213 #endif 3214 3215 #ifdef __BIG_ENDIAN_BITFIELD 3216 uint32_t rsvd1 : 19; /* Reserved */ 3217 uint32_t cdss : 1; /* Configure Data Security SLI */ 3218 uint32_t casabt : 1; /* Configure async abts status notice */ 3219 uint32_t rsvd2 : 2; /* Reserved */ 3220 uint32_t cbg : 1; /* Configure BlockGuard */ 3221 uint32_t cmv : 1; /* Configure Max VPIs */ 3222 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3223 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3224 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3225 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3226 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3227 uint32_t cmx : 1; /* Configure Max XRIs */ 3228 uint32_t cmr : 1; /* Configure Max RPIs */ 3229 #else /* __LITTLE_ENDIAN */ 3230 uint32_t cmr : 1; /* Configure Max RPIs */ 3231 uint32_t cmx : 1; /* Configure Max XRIs */ 3232 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */ 3233 uint32_t cinb : 1; /* Enable Interrupt Notification Block */ 3234 uint32_t chbs : 1; /* Cofigure Host Backing store */ 3235 uint32_t csah : 1; /* Configure Synchronous Abort Handling */ 3236 uint32_t ccrp : 1; /* Config Command Ring Polling */ 3237 uint32_t cmv : 1; /* Configure Max VPIs */ 3238 uint32_t cbg : 1; /* Configure BlockGuard */ 3239 uint32_t rsvd2 : 2; /* Reserved */ 3240 uint32_t casabt : 1; /* Configure async abts status notice */ 3241 uint32_t cdss : 1; /* Configure Data Security SLI */ 3242 uint32_t rsvd1 : 19; /* Reserved */ 3243 #endif 3244 #ifdef __BIG_ENDIAN_BITFIELD 3245 uint32_t rsvd3 : 19; /* Reserved */ 3246 uint32_t gdss : 1; /* Configure Data Security SLI */ 3247 uint32_t gasabt : 1; /* Grant async abts status notice */ 3248 uint32_t rsvd4 : 2; /* Reserved */ 3249 uint32_t gbg : 1; /* Grant BlockGuard */ 3250 uint32_t gmv : 1; /* Grant Max VPIs */ 3251 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3252 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3253 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3254 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3255 uint32_t gerbm : 1; /* Grant ERBM Request */ 3256 uint32_t gmx : 1; /* Grant Max XRIs */ 3257 uint32_t gmr : 1; /* Grant Max RPIs */ 3258 #else /* __LITTLE_ENDIAN */ 3259 uint32_t gmr : 1; /* Grant Max RPIs */ 3260 uint32_t gmx : 1; /* Grant Max XRIs */ 3261 uint32_t gerbm : 1; /* Grant ERBM Request */ 3262 uint32_t ginb : 1; /* Grant Interrupt Notification Block */ 3263 uint32_t ghbs : 1; /* Grant Host Backing Store */ 3264 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */ 3265 uint32_t gcrp : 1; /* Grant Command Ring Polling */ 3266 uint32_t gmv : 1; /* Grant Max VPIs */ 3267 uint32_t gbg : 1; /* Grant BlockGuard */ 3268 uint32_t rsvd4 : 2; /* Reserved */ 3269 uint32_t gasabt : 1; /* Grant async abts status notice */ 3270 uint32_t gdss : 1; /* Configure Data Security SLI */ 3271 uint32_t rsvd3 : 19; /* Reserved */ 3272 #endif 3273 3274 #ifdef __BIG_ENDIAN_BITFIELD 3275 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3276 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3277 #else /* __LITTLE_ENDIAN */ 3278 uint32_t max_xri : 16; /* Max XRIs Port should configure */ 3279 uint32_t max_rpi : 16; /* Max RPIs Port should configure */ 3280 #endif 3281 3282 #ifdef __BIG_ENDIAN_BITFIELD 3283 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3284 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3285 #else /* __LITTLE_ENDIAN */ 3286 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */ 3287 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */ 3288 #endif 3289 3290 uint32_t rsvd6; /* Reserved */ 3291 3292 #ifdef __BIG_ENDIAN_BITFIELD 3293 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 3294 uint32_t fips_level : 4; /* FIPS Level */ 3295 uint32_t sec_err : 9; /* security crypto error */ 3296 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3297 #else /* __LITTLE_ENDIAN */ 3298 uint32_t max_vpi : 16; /* Max number of virt N-Ports */ 3299 uint32_t sec_err : 9; /* security crypto error */ 3300 uint32_t fips_level : 4; /* FIPS Level */ 3301 uint32_t fips_rev : 3; /* FIPS Spec Revision */ 3302 #endif 3303 3304 } CONFIG_PORT_VAR; 3305 3306 /* Structure for MB Command CONFIG_MSI (0x30) */ 3307 struct config_msi_var { 3308 #ifdef __BIG_ENDIAN_BITFIELD 3309 uint32_t dfltMsgNum:8; /* Default message number */ 3310 uint32_t rsvd1:11; /* Reserved */ 3311 uint32_t NID:5; /* Number of secondary attention IDs */ 3312 uint32_t rsvd2:5; /* Reserved */ 3313 uint32_t dfltPresent:1; /* Default message number present */ 3314 uint32_t addFlag:1; /* Add association flag */ 3315 uint32_t reportFlag:1; /* Report association flag */ 3316 #else /* __LITTLE_ENDIAN_BITFIELD */ 3317 uint32_t reportFlag:1; /* Report association flag */ 3318 uint32_t addFlag:1; /* Add association flag */ 3319 uint32_t dfltPresent:1; /* Default message number present */ 3320 uint32_t rsvd2:5; /* Reserved */ 3321 uint32_t NID:5; /* Number of secondary attention IDs */ 3322 uint32_t rsvd1:11; /* Reserved */ 3323 uint32_t dfltMsgNum:8; /* Default message number */ 3324 #endif 3325 uint32_t attentionConditions[2]; 3326 uint8_t attentionId[16]; 3327 uint8_t messageNumberByHA[64]; 3328 uint8_t messageNumberByID[16]; 3329 uint32_t autoClearHA[2]; 3330 #ifdef __BIG_ENDIAN_BITFIELD 3331 uint32_t rsvd3:16; 3332 uint32_t autoClearID:16; 3333 #else /* __LITTLE_ENDIAN_BITFIELD */ 3334 uint32_t autoClearID:16; 3335 uint32_t rsvd3:16; 3336 #endif 3337 uint32_t rsvd4; 3338 }; 3339 3340 /* SLI-2 Port Control Block */ 3341 3342 /* SLIM POINTER */ 3343 #define SLIMOFF 0x30 /* WORD */ 3344 3345 typedef struct _SLI2_RDSC { 3346 uint32_t cmdEntries; 3347 uint32_t cmdAddrLow; 3348 uint32_t cmdAddrHigh; 3349 3350 uint32_t rspEntries; 3351 uint32_t rspAddrLow; 3352 uint32_t rspAddrHigh; 3353 } SLI2_RDSC; 3354 3355 typedef struct _PCB { 3356 #ifdef __BIG_ENDIAN_BITFIELD 3357 uint32_t type:8; 3358 #define TYPE_NATIVE_SLI2 0x01 3359 uint32_t feature:8; 3360 #define FEATURE_INITIAL_SLI2 0x01 3361 uint32_t rsvd:12; 3362 uint32_t maxRing:4; 3363 #else /* __LITTLE_ENDIAN_BITFIELD */ 3364 uint32_t maxRing:4; 3365 uint32_t rsvd:12; 3366 uint32_t feature:8; 3367 #define FEATURE_INITIAL_SLI2 0x01 3368 uint32_t type:8; 3369 #define TYPE_NATIVE_SLI2 0x01 3370 #endif 3371 3372 uint32_t mailBoxSize; 3373 uint32_t mbAddrLow; 3374 uint32_t mbAddrHigh; 3375 3376 uint32_t hgpAddrLow; 3377 uint32_t hgpAddrHigh; 3378 3379 uint32_t pgpAddrLow; 3380 uint32_t pgpAddrHigh; 3381 SLI2_RDSC rdsc[MAX_SLI3_RINGS]; 3382 } PCB_t; 3383 3384 /* NEW_FEATURE */ 3385 typedef struct { 3386 #ifdef __BIG_ENDIAN_BITFIELD 3387 uint32_t rsvd0:27; 3388 uint32_t discardFarp:1; 3389 uint32_t IPEnable:1; 3390 uint32_t nodeName:1; 3391 uint32_t portName:1; 3392 uint32_t filterEnable:1; 3393 #else /* __LITTLE_ENDIAN_BITFIELD */ 3394 uint32_t filterEnable:1; 3395 uint32_t portName:1; 3396 uint32_t nodeName:1; 3397 uint32_t IPEnable:1; 3398 uint32_t discardFarp:1; 3399 uint32_t rsvd:27; 3400 #endif 3401 3402 uint8_t portname[8]; /* Used to be struct lpfc_name */ 3403 uint8_t nodename[8]; 3404 uint32_t rsvd1; 3405 uint32_t rsvd2; 3406 uint32_t rsvd3; 3407 uint32_t IPAddress; 3408 } CONFIG_FARP_VAR; 3409 3410 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */ 3411 3412 typedef struct { 3413 #ifdef __BIG_ENDIAN_BITFIELD 3414 uint32_t rsvd:30; 3415 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3416 #else /* __LITTLE_ENDIAN */ 3417 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/ 3418 uint32_t rsvd:30; 3419 #endif 3420 } ASYNCEVT_ENABLE_VAR; 3421 3422 /* Union of all Mailbox Command types */ 3423 #define MAILBOX_CMD_WSIZE 32 3424 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t)) 3425 /* ext_wsize times 4 bytes should not be greater than max xmit size */ 3426 #define MAILBOX_EXT_WSIZE 512 3427 #define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t)) 3428 #define MAILBOX_HBA_EXT_OFFSET 0x100 3429 /* max mbox xmit size is a page size for sysfs IO operations */ 3430 #define MAILBOX_SYSFS_MAX 4096 3431 3432 typedef union { 3433 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/ 3434 * feature/max ring number 3435 */ 3436 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */ 3437 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */ 3438 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */ 3439 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */ 3440 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */ 3441 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */ 3442 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */ 3443 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */ 3444 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */ 3445 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */ 3446 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */ 3447 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */ 3448 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */ 3449 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */ 3450 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */ 3451 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */ 3452 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */ 3453 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */ 3454 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */ 3455 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */ 3456 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */ 3457 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */ 3458 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */ 3459 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP) 3460 * NEW_FEATURE 3461 */ 3462 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */ 3463 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/ 3464 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */ 3465 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */ 3466 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */ 3467 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */ 3468 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */ 3469 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38 3470 * (READ_EVENT_LOG) 3471 */ 3472 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */ 3473 } MAILVARIANTS; 3474 3475 /* 3476 * SLI-2 specific structures 3477 */ 3478 3479 struct lpfc_hgp { 3480 __le32 cmdPutInx; 3481 __le32 rspGetInx; 3482 }; 3483 3484 struct lpfc_pgp { 3485 __le32 cmdGetInx; 3486 __le32 rspPutInx; 3487 }; 3488 3489 struct sli2_desc { 3490 uint32_t unused1[16]; 3491 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3492 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3493 }; 3494 3495 struct sli3_desc { 3496 struct lpfc_hgp host[MAX_SLI3_RINGS]; 3497 uint32_t reserved[8]; 3498 uint32_t hbq_put[16]; 3499 }; 3500 3501 struct sli3_pgp { 3502 struct lpfc_pgp port[MAX_SLI3_RINGS]; 3503 uint32_t hbq_get[16]; 3504 }; 3505 3506 union sli_var { 3507 struct sli2_desc s2; 3508 struct sli3_desc s3; 3509 struct sli3_pgp s3_pgp; 3510 }; 3511 3512 typedef struct { 3513 #ifdef __BIG_ENDIAN_BITFIELD 3514 uint16_t mbxStatus; 3515 uint8_t mbxCommand; 3516 uint8_t mbxReserved:6; 3517 uint8_t mbxHc:1; 3518 uint8_t mbxOwner:1; /* Low order bit first word */ 3519 #else /* __LITTLE_ENDIAN_BITFIELD */ 3520 uint8_t mbxOwner:1; /* Low order bit first word */ 3521 uint8_t mbxHc:1; 3522 uint8_t mbxReserved:6; 3523 uint8_t mbxCommand; 3524 uint16_t mbxStatus; 3525 #endif 3526 3527 MAILVARIANTS un; 3528 union sli_var us; 3529 } MAILBOX_t; 3530 3531 /* 3532 * Begin Structure Definitions for IOCB Commands 3533 */ 3534 3535 typedef struct { 3536 #ifdef __BIG_ENDIAN_BITFIELD 3537 uint8_t statAction; 3538 uint8_t statRsn; 3539 uint8_t statBaExp; 3540 uint8_t statLocalError; 3541 #else /* __LITTLE_ENDIAN_BITFIELD */ 3542 uint8_t statLocalError; 3543 uint8_t statBaExp; 3544 uint8_t statRsn; 3545 uint8_t statAction; 3546 #endif 3547 /* statRsn P/F_RJT reason codes */ 3548 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */ 3549 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */ 3550 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */ 3551 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */ 3552 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */ 3553 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */ 3554 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */ 3555 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */ 3556 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */ 3557 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */ 3558 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */ 3559 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */ 3560 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */ 3561 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */ 3562 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */ 3563 #define RJT_BAD_PARM 0x10 /* Param. field invalid */ 3564 #define RJT_XCHG_ERR 0x11 /* Exchange error */ 3565 #define RJT_PROT_ERR 0x12 /* Protocol error */ 3566 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */ 3567 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */ 3568 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */ 3569 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */ 3570 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */ 3571 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */ 3572 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */ 3573 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */ 3574 3575 #define IOERR_SUCCESS 0x00 /* statLocalError */ 3576 #define IOERR_MISSING_CONTINUE 0x01 3577 #define IOERR_SEQUENCE_TIMEOUT 0x02 3578 #define IOERR_INTERNAL_ERROR 0x03 3579 #define IOERR_INVALID_RPI 0x04 3580 #define IOERR_NO_XRI 0x05 3581 #define IOERR_ILLEGAL_COMMAND 0x06 3582 #define IOERR_XCHG_DROPPED 0x07 3583 #define IOERR_ILLEGAL_FIELD 0x08 3584 #define IOERR_BAD_CONTINUE 0x09 3585 #define IOERR_TOO_MANY_BUFFERS 0x0A 3586 #define IOERR_RCV_BUFFER_WAITING 0x0B 3587 #define IOERR_NO_CONNECTION 0x0C 3588 #define IOERR_TX_DMA_FAILED 0x0D 3589 #define IOERR_RX_DMA_FAILED 0x0E 3590 #define IOERR_ILLEGAL_FRAME 0x0F 3591 #define IOERR_EXTRA_DATA 0x10 3592 #define IOERR_NO_RESOURCES 0x11 3593 #define IOERR_RESERVED 0x12 3594 #define IOERR_ILLEGAL_LENGTH 0x13 3595 #define IOERR_UNSUPPORTED_FEATURE 0x14 3596 #define IOERR_ABORT_IN_PROGRESS 0x15 3597 #define IOERR_ABORT_REQUESTED 0x16 3598 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17 3599 #define IOERR_LOOP_OPEN_FAILURE 0x18 3600 #define IOERR_RING_RESET 0x19 3601 #define IOERR_LINK_DOWN 0x1A 3602 #define IOERR_CORRUPTED_DATA 0x1B 3603 #define IOERR_CORRUPTED_RPI 0x1C 3604 #define IOERR_OUT_OF_ORDER_DATA 0x1D 3605 #define IOERR_OUT_OF_ORDER_ACK 0x1E 3606 #define IOERR_DUP_FRAME 0x1F 3607 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */ 3608 #define IOERR_BAD_HOST_ADDRESS 0x21 3609 #define IOERR_RCV_HDRBUF_WAITING 0x22 3610 #define IOERR_MISSING_HDR_BUFFER 0x23 3611 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24 3612 #define IOERR_ABORTMULT_REQUESTED 0x25 3613 #define IOERR_BUFFER_SHORTAGE 0x28 3614 #define IOERR_DEFAULT 0x29 3615 #define IOERR_CNT 0x2A 3616 #define IOERR_SLER_FAILURE 0x46 3617 #define IOERR_SLER_CMD_RCV_FAILURE 0x47 3618 #define IOERR_SLER_REC_RJT_ERR 0x48 3619 #define IOERR_SLER_REC_SRR_RETRY_ERR 0x49 3620 #define IOERR_SLER_SRR_RJT_ERR 0x4A 3621 #define IOERR_SLER_RRQ_RJT_ERR 0x4C 3622 #define IOERR_SLER_RRQ_RETRY_ERR 0x4D 3623 #define IOERR_SLER_ABTS_ERR 0x4E 3624 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0 3625 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1 3626 #define IOERR_ELXSEC_CRYPTO_ERROR 0xF2 3627 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3 3628 #define IOERR_DRVR_MASK 0x100 3629 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */ 3630 #define IOERR_SLI_BRESET 0x102 3631 #define IOERR_SLI_ABORTED 0x103 3632 #define IOERR_PARAM_MASK 0x1ff 3633 } PARM_ERR; 3634 3635 typedef union { 3636 struct { 3637 #ifdef __BIG_ENDIAN_BITFIELD 3638 uint8_t Rctl; /* R_CTL field */ 3639 uint8_t Type; /* TYPE field */ 3640 uint8_t Dfctl; /* DF_CTL field */ 3641 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3642 #else /* __LITTLE_ENDIAN_BITFIELD */ 3643 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */ 3644 uint8_t Dfctl; /* DF_CTL field */ 3645 uint8_t Type; /* TYPE field */ 3646 uint8_t Rctl; /* R_CTL field */ 3647 #endif 3648 3649 #define BC 0x02 /* Broadcast Received - Fctl */ 3650 #define SI 0x04 /* Sequence Initiative */ 3651 #define LA 0x08 /* Ignore Link Attention state */ 3652 #define LS 0x80 /* Last Sequence */ 3653 } hcsw; 3654 uint32_t reserved; 3655 } WORD5; 3656 3657 /* IOCB Command template for a generic response */ 3658 typedef struct { 3659 uint32_t reserved[4]; 3660 PARM_ERR perr; 3661 } GENERIC_RSP; 3662 3663 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */ 3664 typedef struct { 3665 struct ulp_bde xrsqbde[2]; 3666 uint32_t xrsqRo; /* Starting Relative Offset */ 3667 WORD5 w5; /* Header control/status word */ 3668 } XR_SEQ_FIELDS; 3669 3670 /* IOCB Command template for ELS_REQUEST */ 3671 typedef struct { 3672 struct ulp_bde elsReq; 3673 struct ulp_bde elsRsp; 3674 3675 #ifdef __BIG_ENDIAN_BITFIELD 3676 uint32_t word4Rsvd:7; 3677 uint32_t fl:1; 3678 uint32_t myID:24; 3679 uint32_t word5Rsvd:8; 3680 uint32_t remoteID:24; 3681 #else /* __LITTLE_ENDIAN_BITFIELD */ 3682 uint32_t myID:24; 3683 uint32_t fl:1; 3684 uint32_t word4Rsvd:7; 3685 uint32_t remoteID:24; 3686 uint32_t word5Rsvd:8; 3687 #endif 3688 } ELS_REQUEST; 3689 3690 /* IOCB Command template for RCV_ELS_REQ */ 3691 typedef struct { 3692 struct ulp_bde elsReq[2]; 3693 uint32_t parmRo; 3694 3695 #ifdef __BIG_ENDIAN_BITFIELD 3696 uint32_t word5Rsvd:8; 3697 uint32_t remoteID:24; 3698 #else /* __LITTLE_ENDIAN_BITFIELD */ 3699 uint32_t remoteID:24; 3700 uint32_t word5Rsvd:8; 3701 #endif 3702 } RCV_ELS_REQ; 3703 3704 /* IOCB Command template for ABORT / CLOSE_XRI */ 3705 typedef struct { 3706 uint32_t rsvd[3]; 3707 uint32_t abortType; 3708 #define ABORT_TYPE_ABTX 0x00000000 3709 #define ABORT_TYPE_ABTS 0x00000001 3710 uint32_t parm; 3711 #ifdef __BIG_ENDIAN_BITFIELD 3712 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3713 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3714 #else /* __LITTLE_ENDIAN_BITFIELD */ 3715 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */ 3716 uint16_t abortContextTag; /* ulpContext from command to abort/close */ 3717 #endif 3718 } AC_XRI; 3719 3720 /* IOCB Command template for ABORT_MXRI64 */ 3721 typedef struct { 3722 uint32_t rsvd[3]; 3723 uint32_t abortType; 3724 uint32_t parm; 3725 uint32_t iotag32; 3726 } A_MXRI64; 3727 3728 /* IOCB Command template for GET_RPI */ 3729 typedef struct { 3730 uint32_t rsvd[4]; 3731 uint32_t parmRo; 3732 #ifdef __BIG_ENDIAN_BITFIELD 3733 uint32_t word5Rsvd:8; 3734 uint32_t remoteID:24; 3735 #else /* __LITTLE_ENDIAN_BITFIELD */ 3736 uint32_t remoteID:24; 3737 uint32_t word5Rsvd:8; 3738 #endif 3739 } GET_RPI; 3740 3741 /* IOCB Command template for all FCP Initiator commands */ 3742 typedef struct { 3743 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */ 3744 struct ulp_bde fcpi_rsp; /* Rcv buffer */ 3745 uint32_t fcpi_parm; 3746 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3747 } FCPI_FIELDS; 3748 3749 /* IOCB Command template for all FCP Target commands */ 3750 typedef struct { 3751 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */ 3752 uint32_t fcpt_Offset; 3753 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3754 } FCPT_FIELDS; 3755 3756 /* SLI-2 IOCB structure definitions */ 3757 3758 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */ 3759 typedef struct { 3760 ULP_BDL bdl; 3761 uint32_t xrsqRo; /* Starting Relative Offset */ 3762 WORD5 w5; /* Header control/status word */ 3763 } XMT_SEQ_FIELDS64; 3764 3765 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */ 3766 #define xmit_els_remoteID xrsqRo 3767 3768 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */ 3769 typedef struct { 3770 struct ulp_bde64 rcvBde; 3771 uint32_t rsvd1; 3772 uint32_t xrsqRo; /* Starting Relative Offset */ 3773 WORD5 w5; /* Header control/status word */ 3774 } RCV_SEQ_FIELDS64; 3775 3776 /* IOCB Command template for ELS_REQUEST64 */ 3777 typedef struct { 3778 ULP_BDL bdl; 3779 #ifdef __BIG_ENDIAN_BITFIELD 3780 uint32_t word4Rsvd:7; 3781 uint32_t fl:1; 3782 uint32_t myID:24; 3783 uint32_t word5Rsvd:8; 3784 uint32_t remoteID:24; 3785 #else /* __LITTLE_ENDIAN_BITFIELD */ 3786 uint32_t myID:24; 3787 uint32_t fl:1; 3788 uint32_t word4Rsvd:7; 3789 uint32_t remoteID:24; 3790 uint32_t word5Rsvd:8; 3791 #endif 3792 } ELS_REQUEST64; 3793 3794 /* IOCB Command template for GEN_REQUEST64 */ 3795 typedef struct { 3796 ULP_BDL bdl; 3797 uint32_t xrsqRo; /* Starting Relative Offset */ 3798 WORD5 w5; /* Header control/status word */ 3799 } GEN_REQUEST64; 3800 3801 /* IOCB Command template for RCV_ELS_REQ64 */ 3802 typedef struct { 3803 struct ulp_bde64 elsReq; 3804 uint32_t rcvd1; 3805 uint32_t parmRo; 3806 3807 #ifdef __BIG_ENDIAN_BITFIELD 3808 uint32_t word5Rsvd:8; 3809 uint32_t remoteID:24; 3810 #else /* __LITTLE_ENDIAN_BITFIELD */ 3811 uint32_t remoteID:24; 3812 uint32_t word5Rsvd:8; 3813 #endif 3814 } RCV_ELS_REQ64; 3815 3816 /* IOCB Command template for RCV_SEQ64 */ 3817 struct rcv_seq64 { 3818 struct ulp_bde64 elsReq; 3819 uint32_t hbq_1; 3820 uint32_t parmRo; 3821 #ifdef __BIG_ENDIAN_BITFIELD 3822 uint32_t rctl:8; 3823 uint32_t type:8; 3824 uint32_t dfctl:8; 3825 uint32_t ls:1; 3826 uint32_t fs:1; 3827 uint32_t rsvd2:3; 3828 uint32_t si:1; 3829 uint32_t bc:1; 3830 uint32_t rsvd3:1; 3831 #else /* __LITTLE_ENDIAN_BITFIELD */ 3832 uint32_t rsvd3:1; 3833 uint32_t bc:1; 3834 uint32_t si:1; 3835 uint32_t rsvd2:3; 3836 uint32_t fs:1; 3837 uint32_t ls:1; 3838 uint32_t dfctl:8; 3839 uint32_t type:8; 3840 uint32_t rctl:8; 3841 #endif 3842 }; 3843 3844 /* IOCB Command template for all 64 bit FCP Initiator commands */ 3845 typedef struct { 3846 ULP_BDL bdl; 3847 uint32_t fcpi_parm; 3848 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */ 3849 } FCPI_FIELDS64; 3850 3851 /* IOCB Command template for all 64 bit FCP Target commands */ 3852 typedef struct { 3853 ULP_BDL bdl; 3854 uint32_t fcpt_Offset; 3855 uint32_t fcpt_Length; /* transfer ready for IWRITE */ 3856 } FCPT_FIELDS64; 3857 3858 /* IOCB Command template for Async Status iocb commands */ 3859 typedef struct { 3860 uint32_t rsvd[4]; 3861 uint32_t param; 3862 #ifdef __BIG_ENDIAN_BITFIELD 3863 uint16_t evt_code; /* High order bits word 5 */ 3864 uint16_t sub_ctxt_tag; /* Low order bits word 5 */ 3865 #else /* __LITTLE_ENDIAN_BITFIELD */ 3866 uint16_t sub_ctxt_tag; /* High order bits word 5 */ 3867 uint16_t evt_code; /* Low order bits word 5 */ 3868 #endif 3869 } ASYNCSTAT_FIELDS; 3870 #define ASYNC_TEMP_WARN 0x100 3871 #define ASYNC_TEMP_SAFE 0x101 3872 #define ASYNC_STATUS_CN 0x102 3873 3874 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7) 3875 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */ 3876 3877 struct rcv_sli3 { 3878 #ifdef __BIG_ENDIAN_BITFIELD 3879 uint16_t ox_id; 3880 uint16_t seq_cnt; 3881 3882 uint16_t vpi; 3883 uint16_t word9Rsvd; 3884 #else /* __LITTLE_ENDIAN */ 3885 uint16_t seq_cnt; 3886 uint16_t ox_id; 3887 3888 uint16_t word9Rsvd; 3889 uint16_t vpi; 3890 #endif 3891 uint32_t word10Rsvd; 3892 uint32_t acc_len; /* accumulated length */ 3893 struct ulp_bde64 bde2; 3894 }; 3895 3896 /* Structure used for a single HBQ entry */ 3897 struct lpfc_hbq_entry { 3898 struct ulp_bde64 bde; 3899 uint32_t buffer_tag; 3900 }; 3901 3902 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */ 3903 typedef struct { 3904 struct lpfc_hbq_entry buff; 3905 uint32_t rsvd; 3906 uint32_t rsvd1; 3907 } QUE_XRI64_CX_FIELDS; 3908 3909 struct que_xri64cx_ext_fields { 3910 uint32_t iotag64_low; 3911 uint32_t iotag64_high; 3912 uint32_t ebde_count; 3913 uint32_t rsvd; 3914 struct lpfc_hbq_entry buff[5]; 3915 }; 3916 3917 struct sli3_bg_fields { 3918 uint32_t filler[6]; /* word 8-13 in IOCB */ 3919 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */ 3920 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */ 3921 #define BGS_BIDIR_BG_PROF_MASK 0xff000000 3922 #define BGS_BIDIR_BG_PROF_SHIFT 24 3923 #define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000 3924 #define BGS_BIDIR_ERR_COND_SHIFT 16 3925 #define BGS_BG_PROFILE_MASK 0x0000ff00 3926 #define BGS_BG_PROFILE_SHIFT 8 3927 #define BGS_INVALID_PROF_MASK 0x00000020 3928 #define BGS_INVALID_PROF_SHIFT 5 3929 #define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010 3930 #define BGS_UNINIT_DIF_BLOCK_SHIFT 4 3931 #define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008 3932 #define BGS_HI_WATER_MARK_PRESENT_SHIFT 3 3933 #define BGS_REFTAG_ERR_MASK 0x00000004 3934 #define BGS_REFTAG_ERR_SHIFT 2 3935 #define BGS_APPTAG_ERR_MASK 0x00000002 3936 #define BGS_APPTAG_ERR_SHIFT 1 3937 #define BGS_GUARD_ERR_MASK 0x00000001 3938 #define BGS_GUARD_ERR_SHIFT 0 3939 uint32_t bgstat; /* word 15 - BlockGuard Status */ 3940 }; 3941 3942 static inline uint32_t 3943 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat) 3944 { 3945 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >> 3946 BGS_BIDIR_BG_PROF_SHIFT; 3947 } 3948 3949 static inline uint32_t 3950 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat) 3951 { 3952 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >> 3953 BGS_BIDIR_ERR_COND_SHIFT; 3954 } 3955 3956 static inline uint32_t 3957 lpfc_bgs_get_bg_prof(uint32_t bgstat) 3958 { 3959 return (bgstat & BGS_BG_PROFILE_MASK) >> 3960 BGS_BG_PROFILE_SHIFT; 3961 } 3962 3963 static inline uint32_t 3964 lpfc_bgs_get_invalid_prof(uint32_t bgstat) 3965 { 3966 return (bgstat & BGS_INVALID_PROF_MASK) >> 3967 BGS_INVALID_PROF_SHIFT; 3968 } 3969 3970 static inline uint32_t 3971 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat) 3972 { 3973 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >> 3974 BGS_UNINIT_DIF_BLOCK_SHIFT; 3975 } 3976 3977 static inline uint32_t 3978 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat) 3979 { 3980 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >> 3981 BGS_HI_WATER_MARK_PRESENT_SHIFT; 3982 } 3983 3984 static inline uint32_t 3985 lpfc_bgs_get_reftag_err(uint32_t bgstat) 3986 { 3987 return (bgstat & BGS_REFTAG_ERR_MASK) >> 3988 BGS_REFTAG_ERR_SHIFT; 3989 } 3990 3991 static inline uint32_t 3992 lpfc_bgs_get_apptag_err(uint32_t bgstat) 3993 { 3994 return (bgstat & BGS_APPTAG_ERR_MASK) >> 3995 BGS_APPTAG_ERR_SHIFT; 3996 } 3997 3998 static inline uint32_t 3999 lpfc_bgs_get_guard_err(uint32_t bgstat) 4000 { 4001 return (bgstat & BGS_GUARD_ERR_MASK) >> 4002 BGS_GUARD_ERR_SHIFT; 4003 } 4004 4005 #define LPFC_EXT_DATA_BDE_COUNT 3 4006 struct fcp_irw_ext { 4007 uint32_t io_tag64_low; 4008 uint32_t io_tag64_high; 4009 #ifdef __BIG_ENDIAN_BITFIELD 4010 uint8_t reserved1; 4011 uint8_t reserved2; 4012 uint8_t reserved3; 4013 uint8_t ebde_count; 4014 #else /* __LITTLE_ENDIAN */ 4015 uint8_t ebde_count; 4016 uint8_t reserved3; 4017 uint8_t reserved2; 4018 uint8_t reserved1; 4019 #endif 4020 uint32_t reserved4; 4021 struct ulp_bde64 rbde; /* response bde */ 4022 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */ 4023 uint8_t icd[32]; /* immediate command data (32 bytes) */ 4024 }; 4025 4026 typedef struct _IOCB { /* IOCB structure */ 4027 union { 4028 GENERIC_RSP grsp; /* Generic response */ 4029 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */ 4030 struct ulp_bde cont[3]; /* up to 3 continuation bdes */ 4031 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */ 4032 AC_XRI acxri; /* ABORT / CLOSE_XRI template */ 4033 A_MXRI64 amxri; /* abort multiple xri command overlay */ 4034 GET_RPI getrpi; /* GET_RPI template */ 4035 FCPI_FIELDS fcpi; /* FCP Initiator template */ 4036 FCPT_FIELDS fcpt; /* FCP target template */ 4037 4038 /* SLI-2 structures */ 4039 4040 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation 4041 * bde_64s */ 4042 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */ 4043 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */ 4044 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */ 4045 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */ 4046 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */ 4047 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */ 4048 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */ 4049 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */ 4050 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */ 4051 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */ 4052 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */ 4053 } un; 4054 union { 4055 struct { 4056 #ifdef __BIG_ENDIAN_BITFIELD 4057 uint16_t ulpContext; /* High order bits word 6 */ 4058 uint16_t ulpIoTag; /* Low order bits word 6 */ 4059 #else /* __LITTLE_ENDIAN_BITFIELD */ 4060 uint16_t ulpIoTag; /* Low order bits word 6 */ 4061 uint16_t ulpContext; /* High order bits word 6 */ 4062 #endif 4063 } t1; 4064 struct { 4065 #ifdef __BIG_ENDIAN_BITFIELD 4066 uint16_t ulpContext; /* High order bits word 6 */ 4067 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4068 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4069 #else /* __LITTLE_ENDIAN_BITFIELD */ 4070 uint16_t ulpIoTag0:14; /* Low order bits word 6 */ 4071 uint16_t ulpIoTag1:2; /* Low order bits word 6 */ 4072 uint16_t ulpContext; /* High order bits word 6 */ 4073 #endif 4074 } t2; 4075 } un1; 4076 #define ulpContext un1.t1.ulpContext 4077 #define ulpIoTag un1.t1.ulpIoTag 4078 #define ulpIoTag0 un1.t2.ulpIoTag0 4079 4080 #ifdef __BIG_ENDIAN_BITFIELD 4081 uint32_t ulpTimeout:8; 4082 uint32_t ulpXS:1; 4083 uint32_t ulpFCP2Rcvy:1; 4084 uint32_t ulpPU:2; 4085 uint32_t ulpIr:1; 4086 uint32_t ulpClass:3; 4087 uint32_t ulpCommand:8; 4088 uint32_t ulpStatus:4; 4089 uint32_t ulpBdeCount:2; 4090 uint32_t ulpLe:1; 4091 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4092 #else /* __LITTLE_ENDIAN_BITFIELD */ 4093 uint32_t ulpOwner:1; /* Low order bit word 7 */ 4094 uint32_t ulpLe:1; 4095 uint32_t ulpBdeCount:2; 4096 uint32_t ulpStatus:4; 4097 uint32_t ulpCommand:8; 4098 uint32_t ulpClass:3; 4099 uint32_t ulpIr:1; 4100 uint32_t ulpPU:2; 4101 uint32_t ulpFCP2Rcvy:1; 4102 uint32_t ulpXS:1; 4103 uint32_t ulpTimeout:8; 4104 #endif 4105 4106 union { 4107 struct rcv_sli3 rcvsli3; /* words 8 - 15 */ 4108 4109 /* words 8-31 used for que_xri_cx iocb */ 4110 struct que_xri64cx_ext_fields que_xri64cx_ext_words; 4111 struct fcp_irw_ext fcp_ext; 4112 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */ 4113 4114 /* words 8-15 for BlockGuard */ 4115 struct sli3_bg_fields sli3_bg; 4116 } unsli3; 4117 4118 #define ulpCt_h ulpXS 4119 #define ulpCt_l ulpFCP2Rcvy 4120 4121 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */ 4122 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */ 4123 #define PARM_UNUSED 0 /* PU field (Word 4) not used */ 4124 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */ 4125 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */ 4126 #define PARM_NPIV_DID 3 4127 #define CLASS1 0 /* Class 1 */ 4128 #define CLASS2 1 /* Class 2 */ 4129 #define CLASS3 2 /* Class 3 */ 4130 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */ 4131 4132 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */ 4133 #define IOSTAT_FCP_RSP_ERROR 0x1 4134 #define IOSTAT_REMOTE_STOP 0x2 4135 #define IOSTAT_LOCAL_REJECT 0x3 4136 #define IOSTAT_NPORT_RJT 0x4 4137 #define IOSTAT_FABRIC_RJT 0x5 4138 #define IOSTAT_NPORT_BSY 0x6 4139 #define IOSTAT_FABRIC_BSY 0x7 4140 #define IOSTAT_INTERMED_RSP 0x8 4141 #define IOSTAT_LS_RJT 0x9 4142 #define IOSTAT_BA_RJT 0xA 4143 #define IOSTAT_RSVD1 0xB 4144 #define IOSTAT_RSVD2 0xC 4145 #define IOSTAT_RSVD3 0xD 4146 #define IOSTAT_RSVD4 0xE 4147 #define IOSTAT_NEED_BUFFER 0xF 4148 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */ 4149 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */ 4150 #define IOSTAT_CNT 0x11 4151 4152 } IOCB_t; 4153 4154 4155 #define SLI1_SLIM_SIZE (4 * 1024) 4156 4157 /* Up to 498 IOCBs will fit into 16k 4158 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384 4159 */ 4160 #define SLI2_SLIM_SIZE (64 * 1024) 4161 4162 /* Maximum IOCBs that will fit in SLI2 slim */ 4163 #define MAX_SLI2_IOCB 498 4164 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \ 4165 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \ 4166 sizeof(uint32_t) * MAILBOX_EXT_WSIZE)) 4167 4168 /* HBQ entries are 4 words each = 4k */ 4169 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \ 4170 lpfc_sli_hbq_count()) 4171 4172 struct lpfc_sli2_slim { 4173 MAILBOX_t mbx; 4174 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE]; 4175 PCB_t pcb; 4176 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE]; 4177 }; 4178 4179 /* 4180 * This function checks PCI device to allow special handling for LC HBAs. 4181 * 4182 * Parameters: 4183 * device : struct pci_dev 's device field 4184 * 4185 * return 1 => TRUE 4186 * 0 => FALSE 4187 */ 4188 static inline int 4189 lpfc_is_LC_HBA(unsigned short device) 4190 { 4191 if ((device == PCI_DEVICE_ID_TFLY) || 4192 (device == PCI_DEVICE_ID_PFLY) || 4193 (device == PCI_DEVICE_ID_LP101) || 4194 (device == PCI_DEVICE_ID_BMID) || 4195 (device == PCI_DEVICE_ID_BSMB) || 4196 (device == PCI_DEVICE_ID_ZMID) || 4197 (device == PCI_DEVICE_ID_ZSMB) || 4198 (device == PCI_DEVICE_ID_SAT_MID) || 4199 (device == PCI_DEVICE_ID_SAT_SMB) || 4200 (device == PCI_DEVICE_ID_RFLY)) 4201 return 1; 4202 else 4203 return 0; 4204 } 4205 4206 /* 4207 * Determine if an IOCB failed because of a link event or firmware reset. 4208 */ 4209 4210 static inline int 4211 lpfc_error_lost_link(IOCB_t *iocbp) 4212 { 4213 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT && 4214 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED || 4215 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN || 4216 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN)); 4217 } 4218 4219 #define MENLO_TRANSPORT_TYPE 0xfe 4220 #define MENLO_CONTEXT 0 4221 #define MENLO_PU 3 4222 #define MENLO_TIMEOUT 30 4223 #define SETVAR_MLOMNT 0x103107 4224 #define SETVAR_MLORST 0x103007 4225 4226 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */ 4227