1 /*****************************************************************************/ 2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */ 3 /* */ 4 /* Written By: Keith Mitchell, IBM Corporation */ 5 /* Jack Hammer, Adaptec, Inc. */ 6 /* David Jeffery, Adaptec, Inc. */ 7 /* */ 8 /* Copyright (C) 2000 IBM Corporation */ 9 /* Copyright (C) 2002,2003 Adaptec, Inc. */ 10 /* */ 11 /* This program is free software; you can redistribute it and/or modify */ 12 /* it under the terms of the GNU General Public License as published by */ 13 /* the Free Software Foundation; either version 2 of the License, or */ 14 /* (at your option) any later version. */ 15 /* */ 16 /* This program is distributed in the hope that it will be useful, */ 17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */ 18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ 19 /* GNU General Public License for more details. */ 20 /* */ 21 /* NO WARRANTY */ 22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ 23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ 24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ 25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ 26 /* solely responsible for determining the appropriateness of using and */ 27 /* distributing the Program and assumes all risks associated with its */ 28 /* exercise of rights under this Agreement, including but not limited to */ 29 /* the risks and costs of program errors, damage to or loss of data, */ 30 /* programs or equipment, and unavailability or interruption of operations. */ 31 /* */ 32 /* DISCLAIMER OF LIABILITY */ 33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ 34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ 35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ 36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ 37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ 38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ 39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ 40 /* */ 41 /* You should have received a copy of the GNU General Public License */ 42 /* along with this program; if not, write to the Free Software */ 43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ 44 /* */ 45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */ 46 /* ipslinux@adaptec.com */ 47 /* */ 48 /* For system support issues, contact your local IBM Customer support. */ 49 /* Directions to find IBM Customer Support for each country can be found at: */ 50 /* http://www.ibm.com/planetwide/ */ 51 /* */ 52 /*****************************************************************************/ 53 54 /*****************************************************************************/ 55 /* Change Log */ 56 /* */ 57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */ 58 /* 0.99.03 - Make interrupt routine handle all completed request on the */ 59 /* adapter not just the first one */ 60 /* - Make sure passthru commands get woken up if we run out of */ 61 /* SCBs */ 62 /* - Send all of the commands on the queue at once rather than */ 63 /* one at a time since the card will support it. */ 64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */ 65 /* the interface to the utilities to change */ 66 /* - Fix error recovery code */ 67 /* 0.99.05 - Fix an oops when we get certain passthru commands */ 68 /* 1.00.00 - Initial Public Release */ 69 /* Functionally equivalent to 0.99.05 */ 70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */ 71 /* - Change version to 3.60 to coincide with release numbering. */ 72 /* 3.60.01 - Remove bogus error check in passthru routine */ 73 /* 3.60.02 - Make DCDB direction based on lookup table */ 74 /* - Only allow one DCDB command to a SCSI ID at a time */ 75 /* 4.00.00 - Add support for ServeRAID 4 */ 76 /* 4.00.01 - Add support for First Failure Data Capture */ 77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */ 78 /* 4.00.03 - Add alternative passthru interface */ 79 /* - Add ability to flash BIOS */ 80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */ 81 /* 4.00.05 - Remove wish_block from init routine */ 82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */ 83 /* 2.3.18 and later */ 84 /* - Sync with other changes from the 2.3 kernels */ 85 /* 4.00.06 - Fix timeout with initial FFDC command */ 86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */ 87 /* 4.10.00 - Add support for ServeRAID 4M/4L */ 88 /* 4.10.13 - Fix for dynamic unload and proc file system */ 89 /* 4.20.03 - Rename version to coincide with new release schedules */ 90 /* Performance fixes */ 91 /* Fix truncation of /proc files with cat */ 92 /* Merge in changes through kernel 2.4.0test1ac21 */ 93 /* 4.20.13 - Fix some failure cases / reset code */ 94 /* - Hook into the reboot_notifier to flush the controller cache */ 95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */ 96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */ 97 /* - Add IPSSEND Flash Support */ 98 /* - Set Sense Data for Unknown SCSI Command */ 99 /* - Use Slot Number from NVRAM Page 5 */ 100 /* - Restore caller's DCDB Structure */ 101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/ 102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */ 103 /* - Don't release HA Lock in ips_next() until SC taken off queue */ 104 /* - Unregister SCSI device in ips_release() */ 105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */ 106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */ 107 /* Code Clean-Up for 2.4.x kernel */ 108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */ 109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */ 110 /* - Don't Issue Internal FFDC Command if there are Active Commands */ 111 /* - Close Window for getting too many IOCTL's active */ 112 /* 4.80.00 - Make ia64 Safe */ 113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */ 114 /* - Adjustments to Device Queue Depth */ 115 /* 4.80.14 - Take all semaphores off stack */ 116 /* - Clean Up New_IOCTL path */ 117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */ 118 /* - 5 second delay needed after resetting an i960 adapter */ 119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */ 120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */ 121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */ 122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */ 123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */ 124 /* 4.90.11 - Don't actually RESET unless it's physically required */ 125 /* - Remove unused compile options */ 126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */ 127 /* - Get rid on IOCTL_NEW_COMMAND code */ 128 /* - Add Extended DCDB Commands for Tape Support in 5I */ 129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */ 130 /* 5.10.15 - remove unused code (sem, macros, etc.) */ 131 /* 5.30.00 - use __devexit_p() */ 132 /* 6.00.00 - Add 6x Adapters and Battery Flash */ 133 /* 6.10.00 - Remove 1G Addressing Limitations */ 134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */ 135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */ 136 /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */ 137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */ 138 /* - Fix sort order of 7k */ 139 /* - Remove 3 unused "inline" functions */ 140 /* 7.12.xx - Use STATIC functions wherever possible */ 141 /* - Clean up deprecated MODULE_PARM calls */ 142 /* 7.12.05 - Remove Version Matching per IBM request */ 143 /*****************************************************************************/ 144 145 /* 146 * Conditional Compilation directives for this driver: 147 * 148 * IPS_DEBUG - Turn on debugging info 149 * 150 * Parameters: 151 * 152 * debug:<number> - Set debug level to <number> 153 * NOTE: only works when IPS_DEBUG compile directive is used. 154 * 1 - Normal debug messages 155 * 2 - Verbose debug messages 156 * 11 - Method trace (non interrupt) 157 * 12 - Method trace (includes interrupt) 158 * 159 * noi2o - Don't use I2O Queues (ServeRAID 4 only) 160 * nommap - Don't use memory mapped I/O 161 * ioctlsize - Initial size of the IOCTL buffer 162 */ 163 164 #include <asm/io.h> 165 #include <asm/byteorder.h> 166 #include <asm/page.h> 167 #include <linux/stddef.h> 168 #include <linux/string.h> 169 #include <linux/errno.h> 170 #include <linux/kernel.h> 171 #include <linux/ioport.h> 172 #include <linux/slab.h> 173 #include <linux/delay.h> 174 #include <linux/pci.h> 175 #include <linux/proc_fs.h> 176 #include <linux/reboot.h> 177 #include <linux/interrupt.h> 178 179 #include <linux/blkdev.h> 180 #include <linux/types.h> 181 #include <linux/dma-mapping.h> 182 183 #include <scsi/sg.h> 184 #include "scsi.h" 185 #include <scsi/scsi_host.h> 186 187 #include "ips.h" 188 189 #include <linux/module.h> 190 191 #include <linux/stat.h> 192 193 #include <linux/spinlock.h> 194 #include <linux/init.h> 195 196 #include <linux/smp.h> 197 198 #ifdef MODULE 199 static char *ips = NULL; 200 module_param(ips, charp, 0); 201 #endif 202 203 /* 204 * DRIVER_VER 205 */ 206 #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING 207 #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " " 208 209 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__) 210 #warning "This driver has only been tested on the x86/ia64/x86_64 platforms" 211 #endif 212 213 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \ 214 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \ 215 PCI_DMA_BIDIRECTIONAL : \ 216 scb->scsi_cmd->sc_data_direction) 217 218 #ifdef IPS_DEBUG 219 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n"); 220 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n"); 221 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v); 222 #else 223 #define METHOD_TRACE(s, i) 224 #define DEBUG(i, s) 225 #define DEBUG_VAR(i, s, v...) 226 #endif 227 228 /* 229 * Function prototypes 230 */ 231 static int ips_detect(struct scsi_host_template *); 232 static int ips_release(struct Scsi_Host *); 233 static int ips_eh_abort(struct scsi_cmnd *); 234 static int ips_eh_reset(struct scsi_cmnd *); 235 static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *); 236 static const char *ips_info(struct Scsi_Host *); 237 static irqreturn_t do_ipsintr(int, void *); 238 static int ips_hainit(ips_ha_t *); 239 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *); 240 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int); 241 static int ips_send_cmd(ips_ha_t *, ips_scb_t *); 242 static int ips_online(ips_ha_t *, ips_scb_t *); 243 static int ips_inquiry(ips_ha_t *, ips_scb_t *); 244 static int ips_rdcap(ips_ha_t *, ips_scb_t *); 245 static int ips_msense(ips_ha_t *, ips_scb_t *); 246 static int ips_reqsen(ips_ha_t *, ips_scb_t *); 247 static int ips_deallocatescbs(ips_ha_t *, int); 248 static int ips_allocatescbs(ips_ha_t *); 249 static int ips_reset_copperhead(ips_ha_t *); 250 static int ips_reset_copperhead_memio(ips_ha_t *); 251 static int ips_reset_morpheus(ips_ha_t *); 252 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *); 253 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *); 254 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *); 255 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *); 256 static int ips_isintr_copperhead(ips_ha_t *); 257 static int ips_isintr_copperhead_memio(ips_ha_t *); 258 static int ips_isintr_morpheus(ips_ha_t *); 259 static int ips_wait(ips_ha_t *, int, int); 260 static int ips_write_driver_status(ips_ha_t *, int); 261 static int ips_read_adapter_status(ips_ha_t *, int); 262 static int ips_read_subsystem_parameters(ips_ha_t *, int); 263 static int ips_read_config(ips_ha_t *, int); 264 static int ips_clear_adapter(ips_ha_t *, int); 265 static int ips_readwrite_page5(ips_ha_t *, int, int); 266 static int ips_init_copperhead(ips_ha_t *); 267 static int ips_init_copperhead_memio(ips_ha_t *); 268 static int ips_init_morpheus(ips_ha_t *); 269 static int ips_isinit_copperhead(ips_ha_t *); 270 static int ips_isinit_copperhead_memio(ips_ha_t *); 271 static int ips_isinit_morpheus(ips_ha_t *); 272 static int ips_erase_bios(ips_ha_t *); 273 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); 274 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); 275 static int ips_erase_bios_memio(ips_ha_t *); 276 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 277 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 278 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 279 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 280 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 281 static void ips_free_flash_copperhead(ips_ha_t * ha); 282 static void ips_get_bios_version(ips_ha_t *, int); 283 static void ips_identify_controller(ips_ha_t *); 284 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *); 285 static void ips_enable_int_copperhead(ips_ha_t *); 286 static void ips_enable_int_copperhead_memio(ips_ha_t *); 287 static void ips_enable_int_morpheus(ips_ha_t *); 288 static int ips_intr_copperhead(ips_ha_t *); 289 static int ips_intr_morpheus(ips_ha_t *); 290 static void ips_next(ips_ha_t *, int); 291 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *); 292 static void ipsintr_done(ips_ha_t *, struct ips_scb *); 293 static void ips_done(ips_ha_t *, ips_scb_t *); 294 static void ips_free(ips_ha_t *); 295 static void ips_init_scb(ips_ha_t *, ips_scb_t *); 296 static void ips_freescb(ips_ha_t *, ips_scb_t *); 297 static void ips_setup_funclist(ips_ha_t *); 298 static void ips_statinit(ips_ha_t *); 299 static void ips_statinit_memio(ips_ha_t *); 300 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t); 301 static void ips_ffdc_reset(ips_ha_t *, int); 302 static void ips_ffdc_time(ips_ha_t *); 303 static uint32_t ips_statupd_copperhead(ips_ha_t *); 304 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); 305 static uint32_t ips_statupd_morpheus(ips_ha_t *); 306 static ips_scb_t *ips_getscb(ips_ha_t *); 307 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *); 308 static void ips_putq_wait_tail(ips_wait_queue_t *, struct scsi_cmnd *); 309 static void ips_putq_copp_tail(ips_copp_queue_t *, 310 ips_copp_wait_item_t *); 311 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *); 312 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *); 313 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *); 314 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *, 315 struct scsi_cmnd *); 316 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *, 317 ips_copp_wait_item_t *); 318 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *); 319 320 static int ips_is_passthru(struct scsi_cmnd *); 321 static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int); 322 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 323 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *); 324 static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data, 325 unsigned int count); 326 static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data, 327 unsigned int count); 328 329 static int ips_write_info(struct Scsi_Host *, char *, int); 330 static int ips_show_info(struct seq_file *, struct Scsi_Host *); 331 static int ips_host_info(ips_ha_t *, struct seq_file *); 332 static int ips_abort_init(ips_ha_t * ha, int index); 333 static int ips_init_phase2(int index); 334 335 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr); 336 static int ips_register_scsi(int index); 337 338 static int ips_poll_for_flush_complete(ips_ha_t * ha); 339 static void ips_flush_and_reset(ips_ha_t *ha); 340 341 /* 342 * global variables 343 */ 344 static const char ips_name[] = "ips"; 345 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */ 346 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */ 347 static unsigned int ips_next_controller; 348 static unsigned int ips_num_controllers; 349 static unsigned int ips_released_controllers; 350 static int ips_hotplug; 351 static int ips_cmd_timeout = 60; 352 static int ips_reset_timeout = 60 * 5; 353 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */ 354 static int ips_force_i2o = 1; /* Always use I2O command delivery */ 355 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */ 356 static int ips_cd_boot; /* Booting from Manager CD */ 357 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */ 358 static dma_addr_t ips_flashbusaddr; 359 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */ 360 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ 361 static struct scsi_host_template ips_driver_template = { 362 .detect = ips_detect, 363 .release = ips_release, 364 .info = ips_info, 365 .queuecommand = ips_queue, 366 .eh_abort_handler = ips_eh_abort, 367 .eh_host_reset_handler = ips_eh_reset, 368 .proc_name = "ips", 369 .show_info = ips_show_info, 370 .write_info = ips_write_info, 371 .slave_configure = ips_slave_configure, 372 .bios_param = ips_biosparam, 373 .this_id = -1, 374 .sg_tablesize = IPS_MAX_SG, 375 .cmd_per_lun = 3, 376 .use_clustering = ENABLE_CLUSTERING, 377 }; 378 379 380 /* This table describes all ServeRAID Adapters */ 381 static struct pci_device_id ips_pci_table[] = { 382 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 383 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 384 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 385 { 0, } 386 }; 387 388 MODULE_DEVICE_TABLE( pci, ips_pci_table ); 389 390 static char ips_hot_plug_name[] = "ips"; 391 392 static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); 393 static void ips_remove_device(struct pci_dev *pci_dev); 394 395 static struct pci_driver ips_pci_driver = { 396 .name = ips_hot_plug_name, 397 .id_table = ips_pci_table, 398 .probe = ips_insert_device, 399 .remove = ips_remove_device, 400 }; 401 402 403 /* 404 * Necessary forward function protoypes 405 */ 406 static int ips_halt(struct notifier_block *nb, ulong event, void *buf); 407 408 #define MAX_ADAPTER_NAME 15 409 410 static char ips_adapter_name[][30] = { 411 "ServeRAID", 412 "ServeRAID II", 413 "ServeRAID on motherboard", 414 "ServeRAID on motherboard", 415 "ServeRAID 3H", 416 "ServeRAID 3L", 417 "ServeRAID 4H", 418 "ServeRAID 4M", 419 "ServeRAID 4L", 420 "ServeRAID 4Mx", 421 "ServeRAID 4Lx", 422 "ServeRAID 5i", 423 "ServeRAID 5i", 424 "ServeRAID 6M", 425 "ServeRAID 6i", 426 "ServeRAID 7t", 427 "ServeRAID 7k", 428 "ServeRAID 7M" 429 }; 430 431 static struct notifier_block ips_notifier = { 432 ips_halt, NULL, 0 433 }; 434 435 /* 436 * Direction table 437 */ 438 static char ips_command_direction[] = { 439 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, 440 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, 441 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 442 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT, 444 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 445 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN, 446 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 447 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK, 448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 449 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, 450 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 451 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, 452 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE, 453 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, 454 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 456 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 457 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 472 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE, 473 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT, 474 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE, 475 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, 476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT, 486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 487 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK 490 }; 491 492 493 /****************************************************************************/ 494 /* */ 495 /* Routine Name: ips_setup */ 496 /* */ 497 /* Routine Description: */ 498 /* */ 499 /* setup parameters to the driver */ 500 /* */ 501 /****************************************************************************/ 502 static int 503 ips_setup(char *ips_str) 504 { 505 506 int i; 507 char *key; 508 char *value; 509 IPS_OPTION options[] = { 510 {"noi2o", &ips_force_i2o, 0}, 511 {"nommap", &ips_force_memio, 0}, 512 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE}, 513 {"cdboot", &ips_cd_boot, 0}, 514 {"maxcmds", &MaxLiteCmds, 32}, 515 }; 516 517 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */ 518 /* Search for value */ 519 while ((key = strsep(&ips_str, ",."))) { 520 if (!*key) 521 continue; 522 value = strchr(key, ':'); 523 if (value) 524 *value++ = '\0'; 525 /* 526 * We now have key/value pairs. 527 * Update the variables 528 */ 529 for (i = 0; i < ARRAY_SIZE(options); i++) { 530 if (strnicmp 531 (key, options[i].option_name, 532 strlen(options[i].option_name)) == 0) { 533 if (value) 534 *options[i].option_flag = 535 simple_strtoul(value, NULL, 0); 536 else 537 *options[i].option_flag = 538 options[i].option_value; 539 break; 540 } 541 } 542 } 543 544 return (1); 545 } 546 547 __setup("ips=", ips_setup); 548 549 /****************************************************************************/ 550 /* */ 551 /* Routine Name: ips_detect */ 552 /* */ 553 /* Routine Description: */ 554 /* */ 555 /* Detect and initialize the driver */ 556 /* */ 557 /* NOTE: this routine is called under the io_request_lock spinlock */ 558 /* */ 559 /****************************************************************************/ 560 static int 561 ips_detect(struct scsi_host_template * SHT) 562 { 563 int i; 564 565 METHOD_TRACE("ips_detect", 1); 566 567 #ifdef MODULE 568 if (ips) 569 ips_setup(ips); 570 #endif 571 572 for (i = 0; i < ips_num_controllers; i++) { 573 if (ips_register_scsi(i)) 574 ips_free(ips_ha[i]); 575 ips_released_controllers++; 576 } 577 ips_hotplug = 1; 578 return (ips_num_controllers); 579 } 580 581 /****************************************************************************/ 582 /* configure the function pointers to use the functions that will work */ 583 /* with the found version of the adapter */ 584 /****************************************************************************/ 585 static void 586 ips_setup_funclist(ips_ha_t * ha) 587 { 588 589 /* 590 * Setup Functions 591 */ 592 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { 593 /* morpheus / marco / sebring */ 594 ha->func.isintr = ips_isintr_morpheus; 595 ha->func.isinit = ips_isinit_morpheus; 596 ha->func.issue = ips_issue_i2o_memio; 597 ha->func.init = ips_init_morpheus; 598 ha->func.statupd = ips_statupd_morpheus; 599 ha->func.reset = ips_reset_morpheus; 600 ha->func.intr = ips_intr_morpheus; 601 ha->func.enableint = ips_enable_int_morpheus; 602 } else if (IPS_USE_MEMIO(ha)) { 603 /* copperhead w/MEMIO */ 604 ha->func.isintr = ips_isintr_copperhead_memio; 605 ha->func.isinit = ips_isinit_copperhead_memio; 606 ha->func.init = ips_init_copperhead_memio; 607 ha->func.statupd = ips_statupd_copperhead_memio; 608 ha->func.statinit = ips_statinit_memio; 609 ha->func.reset = ips_reset_copperhead_memio; 610 ha->func.intr = ips_intr_copperhead; 611 ha->func.erasebios = ips_erase_bios_memio; 612 ha->func.programbios = ips_program_bios_memio; 613 ha->func.verifybios = ips_verify_bios_memio; 614 ha->func.enableint = ips_enable_int_copperhead_memio; 615 if (IPS_USE_I2O_DELIVER(ha)) 616 ha->func.issue = ips_issue_i2o_memio; 617 else 618 ha->func.issue = ips_issue_copperhead_memio; 619 } else { 620 /* copperhead */ 621 ha->func.isintr = ips_isintr_copperhead; 622 ha->func.isinit = ips_isinit_copperhead; 623 ha->func.init = ips_init_copperhead; 624 ha->func.statupd = ips_statupd_copperhead; 625 ha->func.statinit = ips_statinit; 626 ha->func.reset = ips_reset_copperhead; 627 ha->func.intr = ips_intr_copperhead; 628 ha->func.erasebios = ips_erase_bios; 629 ha->func.programbios = ips_program_bios; 630 ha->func.verifybios = ips_verify_bios; 631 ha->func.enableint = ips_enable_int_copperhead; 632 633 if (IPS_USE_I2O_DELIVER(ha)) 634 ha->func.issue = ips_issue_i2o; 635 else 636 ha->func.issue = ips_issue_copperhead; 637 } 638 } 639 640 /****************************************************************************/ 641 /* */ 642 /* Routine Name: ips_release */ 643 /* */ 644 /* Routine Description: */ 645 /* */ 646 /* Remove a driver */ 647 /* */ 648 /****************************************************************************/ 649 static int 650 ips_release(struct Scsi_Host *sh) 651 { 652 ips_scb_t *scb; 653 ips_ha_t *ha; 654 int i; 655 656 METHOD_TRACE("ips_release", 1); 657 658 scsi_remove_host(sh); 659 660 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ; 661 662 if (i == IPS_MAX_ADAPTERS) { 663 printk(KERN_WARNING 664 "(%s) release, invalid Scsi_Host pointer.\n", ips_name); 665 BUG(); 666 return (FALSE); 667 } 668 669 ha = IPS_HA(sh); 670 671 if (!ha) 672 return (FALSE); 673 674 /* flush the cache on the controller */ 675 scb = &ha->scbs[ha->max_cmds - 1]; 676 677 ips_init_scb(ha, scb); 678 679 scb->timeout = ips_cmd_timeout; 680 scb->cdb[0] = IPS_CMD_FLUSH; 681 682 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 683 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 684 scb->cmd.flush_cache.state = IPS_NORM_STATE; 685 scb->cmd.flush_cache.reserved = 0; 686 scb->cmd.flush_cache.reserved2 = 0; 687 scb->cmd.flush_cache.reserved3 = 0; 688 scb->cmd.flush_cache.reserved4 = 0; 689 690 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 691 692 /* send command */ 693 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE) 694 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n"); 695 696 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n"); 697 698 ips_sh[i] = NULL; 699 ips_ha[i] = NULL; 700 701 /* free extra memory */ 702 ips_free(ha); 703 704 /* free IRQ */ 705 free_irq(ha->pcidev->irq, ha); 706 707 scsi_host_put(sh); 708 709 ips_released_controllers++; 710 711 return (FALSE); 712 } 713 714 /****************************************************************************/ 715 /* */ 716 /* Routine Name: ips_halt */ 717 /* */ 718 /* Routine Description: */ 719 /* */ 720 /* Perform cleanup when the system reboots */ 721 /* */ 722 /****************************************************************************/ 723 static int 724 ips_halt(struct notifier_block *nb, ulong event, void *buf) 725 { 726 ips_scb_t *scb; 727 ips_ha_t *ha; 728 int i; 729 730 if ((event != SYS_RESTART) && (event != SYS_HALT) && 731 (event != SYS_POWER_OFF)) 732 return (NOTIFY_DONE); 733 734 for (i = 0; i < ips_next_controller; i++) { 735 ha = (ips_ha_t *) ips_ha[i]; 736 737 if (!ha) 738 continue; 739 740 if (!ha->active) 741 continue; 742 743 /* flush the cache on the controller */ 744 scb = &ha->scbs[ha->max_cmds - 1]; 745 746 ips_init_scb(ha, scb); 747 748 scb->timeout = ips_cmd_timeout; 749 scb->cdb[0] = IPS_CMD_FLUSH; 750 751 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 752 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 753 scb->cmd.flush_cache.state = IPS_NORM_STATE; 754 scb->cmd.flush_cache.reserved = 0; 755 scb->cmd.flush_cache.reserved2 = 0; 756 scb->cmd.flush_cache.reserved3 = 0; 757 scb->cmd.flush_cache.reserved4 = 0; 758 759 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 760 761 /* send command */ 762 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == 763 IPS_FAILURE) 764 IPS_PRINTK(KERN_WARNING, ha->pcidev, 765 "Incomplete Flush.\n"); 766 else 767 IPS_PRINTK(KERN_WARNING, ha->pcidev, 768 "Flushing Complete.\n"); 769 } 770 771 return (NOTIFY_OK); 772 } 773 774 /****************************************************************************/ 775 /* */ 776 /* Routine Name: ips_eh_abort */ 777 /* */ 778 /* Routine Description: */ 779 /* */ 780 /* Abort a command (using the new error code stuff) */ 781 /* Note: this routine is called under the io_request_lock */ 782 /****************************************************************************/ 783 int ips_eh_abort(struct scsi_cmnd *SC) 784 { 785 ips_ha_t *ha; 786 ips_copp_wait_item_t *item; 787 int ret; 788 struct Scsi_Host *host; 789 790 METHOD_TRACE("ips_eh_abort", 1); 791 792 if (!SC) 793 return (FAILED); 794 795 host = SC->device->host; 796 ha = (ips_ha_t *) SC->device->host->hostdata; 797 798 if (!ha) 799 return (FAILED); 800 801 if (!ha->active) 802 return (FAILED); 803 804 spin_lock(host->host_lock); 805 806 /* See if the command is on the copp queue */ 807 item = ha->copp_waitlist.head; 808 while ((item) && (item->scsi_cmd != SC)) 809 item = item->next; 810 811 if (item) { 812 /* Found it */ 813 ips_removeq_copp(&ha->copp_waitlist, item); 814 ret = (SUCCESS); 815 816 /* See if the command is on the wait queue */ 817 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 818 /* command not sent yet */ 819 ret = (SUCCESS); 820 } else { 821 /* command must have already been sent */ 822 ret = (FAILED); 823 } 824 825 spin_unlock(host->host_lock); 826 return ret; 827 } 828 829 /****************************************************************************/ 830 /* */ 831 /* Routine Name: ips_eh_reset */ 832 /* */ 833 /* Routine Description: */ 834 /* */ 835 /* Reset the controller (with new eh error code) */ 836 /* */ 837 /* NOTE: this routine is called under the io_request_lock spinlock */ 838 /* */ 839 /****************************************************************************/ 840 static int __ips_eh_reset(struct scsi_cmnd *SC) 841 { 842 int ret; 843 int i; 844 ips_ha_t *ha; 845 ips_scb_t *scb; 846 ips_copp_wait_item_t *item; 847 848 METHOD_TRACE("ips_eh_reset", 1); 849 850 #ifdef NO_IPS_RESET 851 return (FAILED); 852 #else 853 854 if (!SC) { 855 DEBUG(1, "Reset called with NULL scsi command"); 856 857 return (FAILED); 858 } 859 860 ha = (ips_ha_t *) SC->device->host->hostdata; 861 862 if (!ha) { 863 DEBUG(1, "Reset called with NULL ha struct"); 864 865 return (FAILED); 866 } 867 868 if (!ha->active) 869 return (FAILED); 870 871 /* See if the command is on the copp queue */ 872 item = ha->copp_waitlist.head; 873 while ((item) && (item->scsi_cmd != SC)) 874 item = item->next; 875 876 if (item) { 877 /* Found it */ 878 ips_removeq_copp(&ha->copp_waitlist, item); 879 return (SUCCESS); 880 } 881 882 /* See if the command is on the wait queue */ 883 if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 884 /* command not sent yet */ 885 return (SUCCESS); 886 } 887 888 /* An explanation for the casual observer: */ 889 /* Part of the function of a RAID controller is automatic error */ 890 /* detection and recovery. As such, the only problem that physically */ 891 /* resetting an adapter will ever fix is when, for some reason, */ 892 /* the driver is not successfully communicating with the adapter. */ 893 /* Therefore, we will attempt to flush this adapter. If that succeeds, */ 894 /* then there's no real purpose in a physical reset. This will complete */ 895 /* much faster and avoids any problems that might be caused by a */ 896 /* physical reset ( such as having to fail all the outstanding I/O's ). */ 897 898 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */ 899 scb = &ha->scbs[ha->max_cmds - 1]; 900 901 ips_init_scb(ha, scb); 902 903 scb->timeout = ips_cmd_timeout; 904 scb->cdb[0] = IPS_CMD_FLUSH; 905 906 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 907 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 908 scb->cmd.flush_cache.state = IPS_NORM_STATE; 909 scb->cmd.flush_cache.reserved = 0; 910 scb->cmd.flush_cache.reserved2 = 0; 911 scb->cmd.flush_cache.reserved3 = 0; 912 scb->cmd.flush_cache.reserved4 = 0; 913 914 /* Attempt the flush command */ 915 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL); 916 if (ret == IPS_SUCCESS) { 917 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 918 "Reset Request - Flushed Cache\n"); 919 return (SUCCESS); 920 } 921 } 922 923 /* Either we can't communicate with the adapter or it's an IOCTL request */ 924 /* from a utility. A physical reset is needed at this point. */ 925 926 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */ 927 928 /* 929 * command must have already been sent 930 * reset the controller 931 */ 932 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n"); 933 ret = (*ha->func.reset) (ha); 934 935 if (!ret) { 936 struct scsi_cmnd *scsi_cmd; 937 938 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 939 "Controller reset failed - controller now offline.\n"); 940 941 /* Now fail all of the active commands */ 942 DEBUG_VAR(1, "(%s%d) Failing active commands", 943 ips_name, ha->host_num); 944 945 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 946 scb->scsi_cmd->result = DID_ERROR << 16; 947 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 948 ips_freescb(ha, scb); 949 } 950 951 /* Now fail all of the pending commands */ 952 DEBUG_VAR(1, "(%s%d) Failing pending commands", 953 ips_name, ha->host_num); 954 955 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 956 scsi_cmd->result = DID_ERROR; 957 scsi_cmd->scsi_done(scsi_cmd); 958 } 959 960 ha->active = FALSE; 961 return (FAILED); 962 } 963 964 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) { 965 struct scsi_cmnd *scsi_cmd; 966 967 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 968 "Controller reset failed - controller now offline.\n"); 969 970 /* Now fail all of the active commands */ 971 DEBUG_VAR(1, "(%s%d) Failing active commands", 972 ips_name, ha->host_num); 973 974 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 975 scb->scsi_cmd->result = DID_ERROR << 16; 976 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 977 ips_freescb(ha, scb); 978 } 979 980 /* Now fail all of the pending commands */ 981 DEBUG_VAR(1, "(%s%d) Failing pending commands", 982 ips_name, ha->host_num); 983 984 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 985 scsi_cmd->result = DID_ERROR << 16; 986 scsi_cmd->scsi_done(scsi_cmd); 987 } 988 989 ha->active = FALSE; 990 return (FAILED); 991 } 992 993 /* FFDC */ 994 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) { 995 struct timeval tv; 996 997 do_gettimeofday(&tv); 998 ha->last_ffdc = tv.tv_sec; 999 ha->reset_count++; 1000 ips_ffdc_reset(ha, IPS_INTR_IORL); 1001 } 1002 1003 /* Now fail all of the active commands */ 1004 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num); 1005 1006 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 1007 scb->scsi_cmd->result = DID_RESET << 16; 1008 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 1009 ips_freescb(ha, scb); 1010 } 1011 1012 /* Reset DCDB active command bits */ 1013 for (i = 1; i < ha->nbus; i++) 1014 ha->dcdb_active[i - 1] = 0; 1015 1016 /* Reset the number of active IOCTLs */ 1017 ha->num_ioctl = 0; 1018 1019 ips_next(ha, IPS_INTR_IORL); 1020 1021 return (SUCCESS); 1022 #endif /* NO_IPS_RESET */ 1023 1024 } 1025 1026 static int ips_eh_reset(struct scsi_cmnd *SC) 1027 { 1028 int rc; 1029 1030 spin_lock_irq(SC->device->host->host_lock); 1031 rc = __ips_eh_reset(SC); 1032 spin_unlock_irq(SC->device->host->host_lock); 1033 1034 return rc; 1035 } 1036 1037 /****************************************************************************/ 1038 /* */ 1039 /* Routine Name: ips_queue */ 1040 /* */ 1041 /* Routine Description: */ 1042 /* */ 1043 /* Send a command to the controller */ 1044 /* */ 1045 /* NOTE: */ 1046 /* Linux obtains io_request_lock before calling this function */ 1047 /* */ 1048 /****************************************************************************/ 1049 static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *)) 1050 { 1051 ips_ha_t *ha; 1052 ips_passthru_t *pt; 1053 1054 METHOD_TRACE("ips_queue", 1); 1055 1056 ha = (ips_ha_t *) SC->device->host->hostdata; 1057 1058 if (!ha) 1059 return (1); 1060 1061 if (!ha->active) 1062 return (DID_ERROR); 1063 1064 if (ips_is_passthru(SC)) { 1065 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) { 1066 SC->result = DID_BUS_BUSY << 16; 1067 done(SC); 1068 1069 return (0); 1070 } 1071 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) { 1072 SC->result = DID_BUS_BUSY << 16; 1073 done(SC); 1074 1075 return (0); 1076 } 1077 1078 SC->scsi_done = done; 1079 1080 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)", 1081 ips_name, 1082 ha->host_num, 1083 SC->cmnd[0], 1084 SC->device->channel, SC->device->id, SC->device->lun); 1085 1086 /* Check for command to initiator IDs */ 1087 if ((scmd_channel(SC) > 0) 1088 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) { 1089 SC->result = DID_NO_CONNECT << 16; 1090 done(SC); 1091 1092 return (0); 1093 } 1094 1095 if (ips_is_passthru(SC)) { 1096 1097 ips_copp_wait_item_t *scratch; 1098 1099 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */ 1100 /* There can never be any system activity ( network or disk ), but check */ 1101 /* anyway just as a good practice. */ 1102 pt = (ips_passthru_t *) scsi_sglist(SC); 1103 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) && 1104 (pt->CoppCP.cmd.reset.adapter_flag == 1)) { 1105 if (ha->scb_activelist.count != 0) { 1106 SC->result = DID_BUS_BUSY << 16; 1107 done(SC); 1108 return (0); 1109 } 1110 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */ 1111 __ips_eh_reset(SC); 1112 SC->result = DID_OK << 16; 1113 SC->scsi_done(SC); 1114 return (0); 1115 } 1116 1117 /* allocate space for the scribble */ 1118 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC); 1119 1120 if (!scratch) { 1121 SC->result = DID_ERROR << 16; 1122 done(SC); 1123 1124 return (0); 1125 } 1126 1127 scratch->scsi_cmd = SC; 1128 scratch->next = NULL; 1129 1130 ips_putq_copp_tail(&ha->copp_waitlist, scratch); 1131 } else { 1132 ips_putq_wait_tail(&ha->scb_waitlist, SC); 1133 } 1134 1135 ips_next(ha, IPS_INTR_IORL); 1136 1137 return (0); 1138 } 1139 1140 static DEF_SCSI_QCMD(ips_queue) 1141 1142 /****************************************************************************/ 1143 /* */ 1144 /* Routine Name: ips_biosparam */ 1145 /* */ 1146 /* Routine Description: */ 1147 /* */ 1148 /* Set bios geometry for the controller */ 1149 /* */ 1150 /****************************************************************************/ 1151 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, 1152 sector_t capacity, int geom[]) 1153 { 1154 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata; 1155 int heads; 1156 int sectors; 1157 int cylinders; 1158 1159 METHOD_TRACE("ips_biosparam", 1); 1160 1161 if (!ha) 1162 /* ?!?! host adater info invalid */ 1163 return (0); 1164 1165 if (!ha->active) 1166 return (0); 1167 1168 if (!ips_read_adapter_status(ha, IPS_INTR_ON)) 1169 /* ?!?! Enquiry command failed */ 1170 return (0); 1171 1172 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) { 1173 heads = IPS_NORM_HEADS; 1174 sectors = IPS_NORM_SECTORS; 1175 } else { 1176 heads = IPS_COMP_HEADS; 1177 sectors = IPS_COMP_SECTORS; 1178 } 1179 1180 cylinders = (unsigned long) capacity / (heads * sectors); 1181 1182 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d", 1183 heads, sectors, cylinders); 1184 1185 geom[0] = heads; 1186 geom[1] = sectors; 1187 geom[2] = cylinders; 1188 1189 return (0); 1190 } 1191 1192 /****************************************************************************/ 1193 /* */ 1194 /* Routine Name: ips_slave_configure */ 1195 /* */ 1196 /* Routine Description: */ 1197 /* */ 1198 /* Set queue depths on devices once scan is complete */ 1199 /* */ 1200 /****************************************************************************/ 1201 static int 1202 ips_slave_configure(struct scsi_device * SDptr) 1203 { 1204 ips_ha_t *ha; 1205 int min; 1206 1207 ha = IPS_HA(SDptr->host); 1208 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) { 1209 min = ha->max_cmds / 2; 1210 if (ha->enq->ucLogDriveCount <= 2) 1211 min = ha->max_cmds - 1; 1212 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min); 1213 } 1214 1215 SDptr->skip_ms_page_8 = 1; 1216 SDptr->skip_ms_page_3f = 1; 1217 return 0; 1218 } 1219 1220 /****************************************************************************/ 1221 /* */ 1222 /* Routine Name: do_ipsintr */ 1223 /* */ 1224 /* Routine Description: */ 1225 /* */ 1226 /* Wrapper for the interrupt handler */ 1227 /* */ 1228 /****************************************************************************/ 1229 static irqreturn_t 1230 do_ipsintr(int irq, void *dev_id) 1231 { 1232 ips_ha_t *ha; 1233 struct Scsi_Host *host; 1234 int irqstatus; 1235 1236 METHOD_TRACE("do_ipsintr", 2); 1237 1238 ha = (ips_ha_t *) dev_id; 1239 if (!ha) 1240 return IRQ_NONE; 1241 host = ips_sh[ha->host_num]; 1242 /* interrupt during initialization */ 1243 if (!host) { 1244 (*ha->func.intr) (ha); 1245 return IRQ_HANDLED; 1246 } 1247 1248 spin_lock(host->host_lock); 1249 1250 if (!ha->active) { 1251 spin_unlock(host->host_lock); 1252 return IRQ_HANDLED; 1253 } 1254 1255 irqstatus = (*ha->func.intr) (ha); 1256 1257 spin_unlock(host->host_lock); 1258 1259 /* start the next command */ 1260 ips_next(ha, IPS_INTR_ON); 1261 return IRQ_RETVAL(irqstatus); 1262 } 1263 1264 /****************************************************************************/ 1265 /* */ 1266 /* Routine Name: ips_intr_copperhead */ 1267 /* */ 1268 /* Routine Description: */ 1269 /* */ 1270 /* Polling interrupt handler */ 1271 /* */ 1272 /* ASSUMES interrupts are disabled */ 1273 /* */ 1274 /****************************************************************************/ 1275 int 1276 ips_intr_copperhead(ips_ha_t * ha) 1277 { 1278 ips_stat_t *sp; 1279 ips_scb_t *scb; 1280 IPS_STATUS cstatus; 1281 int intrstatus; 1282 1283 METHOD_TRACE("ips_intr", 2); 1284 1285 if (!ha) 1286 return 0; 1287 1288 if (!ha->active) 1289 return 0; 1290 1291 intrstatus = (*ha->func.isintr) (ha); 1292 1293 if (!intrstatus) { 1294 /* 1295 * Unexpected/Shared interrupt 1296 */ 1297 1298 return 0; 1299 } 1300 1301 while (TRUE) { 1302 sp = &ha->sp; 1303 1304 intrstatus = (*ha->func.isintr) (ha); 1305 1306 if (!intrstatus) 1307 break; 1308 else 1309 cstatus.value = (*ha->func.statupd) (ha); 1310 1311 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1312 /* Spurious Interrupt ? */ 1313 continue; 1314 } 1315 1316 ips_chkstatus(ha, &cstatus); 1317 scb = (ips_scb_t *) sp->scb_addr; 1318 1319 /* 1320 * use the callback function to finish things up 1321 * NOTE: interrupts are OFF for this 1322 */ 1323 (*scb->callback) (ha, scb); 1324 } /* end while */ 1325 return 1; 1326 } 1327 1328 /****************************************************************************/ 1329 /* */ 1330 /* Routine Name: ips_intr_morpheus */ 1331 /* */ 1332 /* Routine Description: */ 1333 /* */ 1334 /* Polling interrupt handler */ 1335 /* */ 1336 /* ASSUMES interrupts are disabled */ 1337 /* */ 1338 /****************************************************************************/ 1339 int 1340 ips_intr_morpheus(ips_ha_t * ha) 1341 { 1342 ips_stat_t *sp; 1343 ips_scb_t *scb; 1344 IPS_STATUS cstatus; 1345 int intrstatus; 1346 1347 METHOD_TRACE("ips_intr_morpheus", 2); 1348 1349 if (!ha) 1350 return 0; 1351 1352 if (!ha->active) 1353 return 0; 1354 1355 intrstatus = (*ha->func.isintr) (ha); 1356 1357 if (!intrstatus) { 1358 /* 1359 * Unexpected/Shared interrupt 1360 */ 1361 1362 return 0; 1363 } 1364 1365 while (TRUE) { 1366 sp = &ha->sp; 1367 1368 intrstatus = (*ha->func.isintr) (ha); 1369 1370 if (!intrstatus) 1371 break; 1372 else 1373 cstatus.value = (*ha->func.statupd) (ha); 1374 1375 if (cstatus.value == 0xffffffff) 1376 /* No more to process */ 1377 break; 1378 1379 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1380 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1381 "Spurious interrupt; no ccb.\n"); 1382 1383 continue; 1384 } 1385 1386 ips_chkstatus(ha, &cstatus); 1387 scb = (ips_scb_t *) sp->scb_addr; 1388 1389 /* 1390 * use the callback function to finish things up 1391 * NOTE: interrupts are OFF for this 1392 */ 1393 (*scb->callback) (ha, scb); 1394 } /* end while */ 1395 return 1; 1396 } 1397 1398 /****************************************************************************/ 1399 /* */ 1400 /* Routine Name: ips_info */ 1401 /* */ 1402 /* Routine Description: */ 1403 /* */ 1404 /* Return info about the driver */ 1405 /* */ 1406 /****************************************************************************/ 1407 static const char * 1408 ips_info(struct Scsi_Host *SH) 1409 { 1410 static char buffer[256]; 1411 char *bp; 1412 ips_ha_t *ha; 1413 1414 METHOD_TRACE("ips_info", 1); 1415 1416 ha = IPS_HA(SH); 1417 1418 if (!ha) 1419 return (NULL); 1420 1421 bp = &buffer[0]; 1422 memset(bp, 0, sizeof (buffer)); 1423 1424 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ", 1425 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT); 1426 1427 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) { 1428 strcat(bp, " <"); 1429 strcat(bp, ips_adapter_name[ha->ad_type - 1]); 1430 strcat(bp, ">"); 1431 } 1432 1433 return (bp); 1434 } 1435 1436 static int 1437 ips_write_info(struct Scsi_Host *host, char *buffer, int length) 1438 { 1439 int i; 1440 ips_ha_t *ha = NULL; 1441 1442 /* Find our host structure */ 1443 for (i = 0; i < ips_next_controller; i++) { 1444 if (ips_sh[i]) { 1445 if (ips_sh[i] == host) { 1446 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1447 break; 1448 } 1449 } 1450 } 1451 1452 if (!ha) 1453 return (-EINVAL); 1454 1455 return 0; 1456 } 1457 1458 static int 1459 ips_show_info(struct seq_file *m, struct Scsi_Host *host) 1460 { 1461 int i; 1462 ips_ha_t *ha = NULL; 1463 1464 /* Find our host structure */ 1465 for (i = 0; i < ips_next_controller; i++) { 1466 if (ips_sh[i]) { 1467 if (ips_sh[i] == host) { 1468 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1469 break; 1470 } 1471 } 1472 } 1473 1474 if (!ha) 1475 return (-EINVAL); 1476 1477 return ips_host_info(ha, m); 1478 } 1479 1480 /*--------------------------------------------------------------------------*/ 1481 /* Helper Functions */ 1482 /*--------------------------------------------------------------------------*/ 1483 1484 /****************************************************************************/ 1485 /* */ 1486 /* Routine Name: ips_is_passthru */ 1487 /* */ 1488 /* Routine Description: */ 1489 /* */ 1490 /* Determine if the specified SCSI command is really a passthru command */ 1491 /* */ 1492 /****************************************************************************/ 1493 static int ips_is_passthru(struct scsi_cmnd *SC) 1494 { 1495 unsigned long flags; 1496 1497 METHOD_TRACE("ips_is_passthru", 1); 1498 1499 if (!SC) 1500 return (0); 1501 1502 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) && 1503 (SC->device->channel == 0) && 1504 (SC->device->id == IPS_ADAPTER_ID) && 1505 (SC->device->lun == 0) && scsi_sglist(SC)) { 1506 struct scatterlist *sg = scsi_sglist(SC); 1507 char *buffer; 1508 1509 /* kmap_atomic() ensures addressability of the user buffer.*/ 1510 /* local_irq_save() protects the KM_IRQ0 address slot. */ 1511 local_irq_save(flags); 1512 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 1513 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' && 1514 buffer[2] == 'P' && buffer[3] == 'P') { 1515 kunmap_atomic(buffer - sg->offset); 1516 local_irq_restore(flags); 1517 return 1; 1518 } 1519 kunmap_atomic(buffer - sg->offset); 1520 local_irq_restore(flags); 1521 } 1522 return 0; 1523 } 1524 1525 /****************************************************************************/ 1526 /* */ 1527 /* Routine Name: ips_alloc_passthru_buffer */ 1528 /* */ 1529 /* Routine Description: */ 1530 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */ 1531 /* is too small or doesn't exist */ 1532 /****************************************************************************/ 1533 static int 1534 ips_alloc_passthru_buffer(ips_ha_t * ha, int length) 1535 { 1536 void *bigger_buf; 1537 dma_addr_t dma_busaddr; 1538 1539 if (ha->ioctl_data && length <= ha->ioctl_len) 1540 return 0; 1541 /* there is no buffer or it's not big enough, allocate a new one */ 1542 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr); 1543 if (bigger_buf) { 1544 /* free the old memory */ 1545 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data, 1546 ha->ioctl_busaddr); 1547 /* use the new memory */ 1548 ha->ioctl_data = (char *) bigger_buf; 1549 ha->ioctl_len = length; 1550 ha->ioctl_busaddr = dma_busaddr; 1551 } else { 1552 return -1; 1553 } 1554 return 0; 1555 } 1556 1557 /****************************************************************************/ 1558 /* */ 1559 /* Routine Name: ips_make_passthru */ 1560 /* */ 1561 /* Routine Description: */ 1562 /* */ 1563 /* Make a passthru command out of the info in the Scsi block */ 1564 /* */ 1565 /****************************************************************************/ 1566 static int 1567 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) 1568 { 1569 ips_passthru_t *pt; 1570 int length = 0; 1571 int i, ret; 1572 struct scatterlist *sg = scsi_sglist(SC); 1573 1574 METHOD_TRACE("ips_make_passthru", 1); 1575 1576 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i) 1577 length += sg->length; 1578 1579 if (length < sizeof (ips_passthru_t)) { 1580 /* wrong size */ 1581 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size", 1582 ips_name, ha->host_num); 1583 return (IPS_FAILURE); 1584 } 1585 if (ips_alloc_passthru_buffer(ha, length)) { 1586 /* allocation failure! If ha->ioctl_data exists, use it to return 1587 some error codes. Return a failed command to the scsi layer. */ 1588 if (ha->ioctl_data) { 1589 pt = (ips_passthru_t *) ha->ioctl_data; 1590 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t)); 1591 pt->BasicStatus = 0x0B; 1592 pt->ExtendedStatus = 0x00; 1593 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t)); 1594 } 1595 return IPS_FAILURE; 1596 } 1597 ha->ioctl_datasize = length; 1598 1599 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize); 1600 pt = (ips_passthru_t *) ha->ioctl_data; 1601 1602 /* 1603 * Some notes about the passthru interface used 1604 * 1605 * IF the scsi op_code == 0x0d then we assume 1606 * that the data came along with/goes with the 1607 * packet we received from the sg driver. In this 1608 * case the CmdBSize field of the pt structure is 1609 * used for the size of the buffer. 1610 */ 1611 1612 switch (pt->CoppCmd) { 1613 case IPS_NUMCTRLS: 1614 memcpy(ha->ioctl_data + sizeof (ips_passthru_t), 1615 &ips_num_controllers, sizeof (int)); 1616 ips_scmd_buf_write(SC, ha->ioctl_data, 1617 sizeof (ips_passthru_t) + sizeof (int)); 1618 SC->result = DID_OK << 16; 1619 1620 return (IPS_SUCCESS_IMM); 1621 1622 case IPS_COPPUSRCMD: 1623 case IPS_COPPIOCCMD: 1624 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) { 1625 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) { 1626 /* wrong size */ 1627 DEBUG_VAR(1, 1628 "(%s%d) Passthru structure wrong size", 1629 ips_name, ha->host_num); 1630 1631 return (IPS_FAILURE); 1632 } 1633 1634 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && 1635 pt->CoppCP.cmd.flashfw.op_code == 1636 IPS_CMD_RW_BIOSFW) { 1637 ret = ips_flash_copperhead(ha, pt, scb); 1638 ips_scmd_buf_write(SC, ha->ioctl_data, 1639 sizeof (ips_passthru_t)); 1640 return ret; 1641 } 1642 if (ips_usrcmd(ha, pt, scb)) 1643 return (IPS_SUCCESS); 1644 else 1645 return (IPS_FAILURE); 1646 } 1647 1648 break; 1649 1650 } /* end switch */ 1651 1652 return (IPS_FAILURE); 1653 } 1654 1655 /****************************************************************************/ 1656 /* Routine Name: ips_flash_copperhead */ 1657 /* Routine Description: */ 1658 /* Flash the BIOS/FW on a Copperhead style controller */ 1659 /****************************************************************************/ 1660 static int 1661 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1662 { 1663 int datasize; 1664 1665 /* Trombone is the only copperhead that can do packet flash, but only 1666 * for firmware. No one said it had to make sense. */ 1667 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) { 1668 if (ips_usrcmd(ha, pt, scb)) 1669 return IPS_SUCCESS; 1670 else 1671 return IPS_FAILURE; 1672 } 1673 pt->BasicStatus = 0x0B; 1674 pt->ExtendedStatus = 0; 1675 scb->scsi_cmd->result = DID_OK << 16; 1676 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */ 1677 /* avoid allocating a huge buffer per adapter ( which can fail ). */ 1678 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1679 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1680 pt->BasicStatus = 0; 1681 return ips_flash_bios(ha, pt, scb); 1682 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) { 1683 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){ 1684 ha->flash_data = ips_FlashData; 1685 ha->flash_busaddr = ips_flashbusaddr; 1686 ha->flash_len = PAGE_SIZE << 7; 1687 ha->flash_datasize = 0; 1688 } else if (!ha->flash_data) { 1689 datasize = pt->CoppCP.cmd.flashfw.total_packets * 1690 pt->CoppCP.cmd.flashfw.count; 1691 ha->flash_data = pci_alloc_consistent(ha->pcidev, 1692 datasize, 1693 &ha->flash_busaddr); 1694 if (!ha->flash_data){ 1695 printk(KERN_WARNING "Unable to allocate a flash buffer\n"); 1696 return IPS_FAILURE; 1697 } 1698 ha->flash_datasize = 0; 1699 ha->flash_len = datasize; 1700 } else 1701 return IPS_FAILURE; 1702 } else { 1703 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize > 1704 ha->flash_len) { 1705 ips_free_flash_copperhead(ha); 1706 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1707 "failed size sanity check\n"); 1708 return IPS_FAILURE; 1709 } 1710 } 1711 if (!ha->flash_data) 1712 return IPS_FAILURE; 1713 pt->BasicStatus = 0; 1714 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1, 1715 pt->CoppCP.cmd.flashfw.count); 1716 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count; 1717 if (pt->CoppCP.cmd.flashfw.packet_num == 1718 pt->CoppCP.cmd.flashfw.total_packets - 1) { 1719 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE) 1720 return ips_flash_bios(ha, pt, scb); 1721 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) 1722 return ips_flash_firmware(ha, pt, scb); 1723 } 1724 return IPS_SUCCESS_IMM; 1725 } 1726 1727 /****************************************************************************/ 1728 /* Routine Name: ips_flash_bios */ 1729 /* Routine Description: */ 1730 /* flashes the bios of a copperhead adapter */ 1731 /****************************************************************************/ 1732 static int 1733 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1734 { 1735 1736 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1737 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) { 1738 if ((!ha->func.programbios) || (!ha->func.erasebios) || 1739 (!ha->func.verifybios)) 1740 goto error; 1741 if ((*ha->func.erasebios) (ha)) { 1742 DEBUG_VAR(1, 1743 "(%s%d) flash bios failed - unable to erase flash", 1744 ips_name, ha->host_num); 1745 goto error; 1746 } else 1747 if ((*ha->func.programbios) (ha, 1748 ha->flash_data + 1749 IPS_BIOS_HEADER, 1750 ha->flash_datasize - 1751 IPS_BIOS_HEADER, 0)) { 1752 DEBUG_VAR(1, 1753 "(%s%d) flash bios failed - unable to flash", 1754 ips_name, ha->host_num); 1755 goto error; 1756 } else 1757 if ((*ha->func.verifybios) (ha, 1758 ha->flash_data + 1759 IPS_BIOS_HEADER, 1760 ha->flash_datasize - 1761 IPS_BIOS_HEADER, 0)) { 1762 DEBUG_VAR(1, 1763 "(%s%d) flash bios failed - unable to verify flash", 1764 ips_name, ha->host_num); 1765 goto error; 1766 } 1767 ips_free_flash_copperhead(ha); 1768 return IPS_SUCCESS_IMM; 1769 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1770 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1771 if (!ha->func.erasebios) 1772 goto error; 1773 if ((*ha->func.erasebios) (ha)) { 1774 DEBUG_VAR(1, 1775 "(%s%d) flash bios failed - unable to erase flash", 1776 ips_name, ha->host_num); 1777 goto error; 1778 } 1779 return IPS_SUCCESS_IMM; 1780 } 1781 error: 1782 pt->BasicStatus = 0x0B; 1783 pt->ExtendedStatus = 0x00; 1784 ips_free_flash_copperhead(ha); 1785 return IPS_FAILURE; 1786 } 1787 1788 /****************************************************************************/ 1789 /* */ 1790 /* Routine Name: ips_fill_scb_sg_single */ 1791 /* */ 1792 /* Routine Description: */ 1793 /* Fill in a single scb sg_list element from an address */ 1794 /* return a -1 if a breakup occurred */ 1795 /****************************************************************************/ 1796 static int 1797 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr, 1798 ips_scb_t * scb, int indx, unsigned int e_len) 1799 { 1800 1801 int ret_val = 0; 1802 1803 if ((scb->data_len + e_len) > ha->max_xfer) { 1804 e_len = ha->max_xfer - scb->data_len; 1805 scb->breakup = indx; 1806 ++scb->sg_break; 1807 ret_val = -1; 1808 } else { 1809 scb->breakup = 0; 1810 scb->sg_break = 0; 1811 } 1812 if (IPS_USE_ENH_SGLIST(ha)) { 1813 scb->sg_list.enh_list[indx].address_lo = 1814 cpu_to_le32(pci_dma_lo32(busaddr)); 1815 scb->sg_list.enh_list[indx].address_hi = 1816 cpu_to_le32(pci_dma_hi32(busaddr)); 1817 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len); 1818 } else { 1819 scb->sg_list.std_list[indx].address = 1820 cpu_to_le32(pci_dma_lo32(busaddr)); 1821 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len); 1822 } 1823 1824 ++scb->sg_len; 1825 scb->data_len += e_len; 1826 return ret_val; 1827 } 1828 1829 /****************************************************************************/ 1830 /* Routine Name: ips_flash_firmware */ 1831 /* Routine Description: */ 1832 /* flashes the firmware of a copperhead adapter */ 1833 /****************************************************************************/ 1834 static int 1835 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1836 { 1837 IPS_SG_LIST sg_list; 1838 uint32_t cmd_busaddr; 1839 1840 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE && 1841 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) { 1842 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND)); 1843 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD; 1844 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize); 1845 } else { 1846 pt->BasicStatus = 0x0B; 1847 pt->ExtendedStatus = 0x00; 1848 ips_free_flash_copperhead(ha); 1849 return IPS_FAILURE; 1850 } 1851 /* Save the S/G list pointer so it doesn't get clobbered */ 1852 sg_list.list = scb->sg_list.list; 1853 cmd_busaddr = scb->scb_busaddr; 1854 /* copy in the CP */ 1855 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1856 /* FIX stuff that might be wrong */ 1857 scb->sg_list.list = sg_list.list; 1858 scb->scb_busaddr = cmd_busaddr; 1859 scb->bus = scb->scsi_cmd->device->channel; 1860 scb->target_id = scb->scsi_cmd->device->id; 1861 scb->lun = scb->scsi_cmd->device->lun; 1862 scb->sg_len = 0; 1863 scb->data_len = 0; 1864 scb->flags = 0; 1865 scb->op_code = 0; 1866 scb->callback = ipsintr_done; 1867 scb->timeout = ips_cmd_timeout; 1868 1869 scb->data_len = ha->flash_datasize; 1870 scb->data_busaddr = 1871 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len, 1872 IPS_DMA_DIR(scb)); 1873 scb->flags |= IPS_SCB_MAP_SINGLE; 1874 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 1875 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr); 1876 if (pt->TimeOut) 1877 scb->timeout = pt->TimeOut; 1878 scb->scsi_cmd->result = DID_OK << 16; 1879 return IPS_SUCCESS; 1880 } 1881 1882 /****************************************************************************/ 1883 /* Routine Name: ips_free_flash_copperhead */ 1884 /* Routine Description: */ 1885 /* release the memory resources used to hold the flash image */ 1886 /****************************************************************************/ 1887 static void 1888 ips_free_flash_copperhead(ips_ha_t * ha) 1889 { 1890 if (ha->flash_data == ips_FlashData) 1891 test_and_clear_bit(0, &ips_FlashDataInUse); 1892 else if (ha->flash_data) 1893 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data, 1894 ha->flash_busaddr); 1895 ha->flash_data = NULL; 1896 } 1897 1898 /****************************************************************************/ 1899 /* */ 1900 /* Routine Name: ips_usrcmd */ 1901 /* */ 1902 /* Routine Description: */ 1903 /* */ 1904 /* Process a user command and make it ready to send */ 1905 /* */ 1906 /****************************************************************************/ 1907 static int 1908 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1909 { 1910 IPS_SG_LIST sg_list; 1911 uint32_t cmd_busaddr; 1912 1913 METHOD_TRACE("ips_usrcmd", 1); 1914 1915 if ((!scb) || (!pt) || (!ha)) 1916 return (0); 1917 1918 /* Save the S/G list pointer so it doesn't get clobbered */ 1919 sg_list.list = scb->sg_list.list; 1920 cmd_busaddr = scb->scb_busaddr; 1921 /* copy in the CP */ 1922 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1923 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE)); 1924 1925 /* FIX stuff that might be wrong */ 1926 scb->sg_list.list = sg_list.list; 1927 scb->scb_busaddr = cmd_busaddr; 1928 scb->bus = scb->scsi_cmd->device->channel; 1929 scb->target_id = scb->scsi_cmd->device->id; 1930 scb->lun = scb->scsi_cmd->device->lun; 1931 scb->sg_len = 0; 1932 scb->data_len = 0; 1933 scb->flags = 0; 1934 scb->op_code = 0; 1935 scb->callback = ipsintr_done; 1936 scb->timeout = ips_cmd_timeout; 1937 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 1938 1939 /* we don't support DCDB/READ/WRITE Scatter Gather */ 1940 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) || 1941 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) || 1942 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG)) 1943 return (0); 1944 1945 if (pt->CmdBSize) { 1946 scb->data_len = pt->CmdBSize; 1947 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t); 1948 } else { 1949 scb->data_busaddr = 0L; 1950 } 1951 1952 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 1953 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 1954 (unsigned long) &scb-> 1955 dcdb - 1956 (unsigned long) scb); 1957 1958 if (pt->CmdBSize) { 1959 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 1960 scb->dcdb.buffer_pointer = 1961 cpu_to_le32(scb->data_busaddr); 1962 else 1963 scb->cmd.basic_io.sg_addr = 1964 cpu_to_le32(scb->data_busaddr); 1965 } 1966 1967 /* set timeouts */ 1968 if (pt->TimeOut) { 1969 scb->timeout = pt->TimeOut; 1970 1971 if (pt->TimeOut <= 10) 1972 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; 1973 else if (pt->TimeOut <= 60) 1974 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; 1975 else 1976 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; 1977 } 1978 1979 /* assume success */ 1980 scb->scsi_cmd->result = DID_OK << 16; 1981 1982 /* success */ 1983 return (1); 1984 } 1985 1986 /****************************************************************************/ 1987 /* */ 1988 /* Routine Name: ips_cleanup_passthru */ 1989 /* */ 1990 /* Routine Description: */ 1991 /* */ 1992 /* Cleanup after a passthru command */ 1993 /* */ 1994 /****************************************************************************/ 1995 static void 1996 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) 1997 { 1998 ips_passthru_t *pt; 1999 2000 METHOD_TRACE("ips_cleanup_passthru", 1); 2001 2002 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) { 2003 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru", 2004 ips_name, ha->host_num); 2005 2006 return; 2007 } 2008 pt = (ips_passthru_t *) ha->ioctl_data; 2009 2010 /* Copy data back to the user */ 2011 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */ 2012 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE)); 2013 2014 pt->BasicStatus = scb->basic_status; 2015 pt->ExtendedStatus = scb->extended_status; 2016 pt->AdapterType = ha->ad_type; 2017 2018 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && 2019 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || 2020 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) 2021 ips_free_flash_copperhead(ha); 2022 2023 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize); 2024 } 2025 2026 /****************************************************************************/ 2027 /* */ 2028 /* Routine Name: ips_host_info */ 2029 /* */ 2030 /* Routine Description: */ 2031 /* */ 2032 /* The passthru interface for the driver */ 2033 /* */ 2034 /****************************************************************************/ 2035 static int 2036 ips_host_info(ips_ha_t *ha, struct seq_file *m) 2037 { 2038 METHOD_TRACE("ips_host_info", 1); 2039 2040 seq_printf(m, "\nIBM ServeRAID General Information:\n\n"); 2041 2042 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) && 2043 (le16_to_cpu(ha->nvram->adapter_type) != 0)) 2044 seq_printf(m, "\tController Type : %s\n", 2045 ips_adapter_name[ha->ad_type - 1]); 2046 else 2047 seq_printf(m, 2048 "\tController Type : Unknown\n"); 2049 2050 if (ha->io_addr) 2051 seq_printf(m, 2052 "\tIO region : 0x%x (%d bytes)\n", 2053 ha->io_addr, ha->io_len); 2054 2055 if (ha->mem_addr) { 2056 seq_printf(m, 2057 "\tMemory region : 0x%x (%d bytes)\n", 2058 ha->mem_addr, ha->mem_len); 2059 seq_printf(m, 2060 "\tShared memory address : 0x%lx\n", 2061 (unsigned long)ha->mem_ptr); 2062 } 2063 2064 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq); 2065 2066 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ 2067 /* That keeps everything happy for "text" operations on the proc file. */ 2068 2069 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { 2070 if (ha->nvram->bios_low[3] == 0) { 2071 seq_printf(m, 2072 "\tBIOS Version : %c%c%c%c%c%c%c\n", 2073 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2074 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2075 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2076 ha->nvram->bios_low[2]); 2077 2078 } else { 2079 seq_printf(m, 2080 "\tBIOS Version : %c%c%c%c%c%c%c%c\n", 2081 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2082 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2083 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2084 ha->nvram->bios_low[2], ha->nvram->bios_low[3]); 2085 } 2086 2087 } 2088 2089 if (ha->enq->CodeBlkVersion[7] == 0) { 2090 seq_printf(m, 2091 "\tFirmware Version : %c%c%c%c%c%c%c\n", 2092 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2093 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2094 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2095 ha->enq->CodeBlkVersion[6]); 2096 } else { 2097 seq_printf(m, 2098 "\tFirmware Version : %c%c%c%c%c%c%c%c\n", 2099 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2100 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2101 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2102 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]); 2103 } 2104 2105 if (ha->enq->BootBlkVersion[7] == 0) { 2106 seq_printf(m, 2107 "\tBoot Block Version : %c%c%c%c%c%c%c\n", 2108 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2109 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2110 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2111 ha->enq->BootBlkVersion[6]); 2112 } else { 2113 seq_printf(m, 2114 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n", 2115 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2116 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2117 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2118 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]); 2119 } 2120 2121 seq_printf(m, "\tDriver Version : %s%s\n", 2122 IPS_VERSION_HIGH, IPS_VERSION_LOW); 2123 2124 seq_printf(m, "\tDriver Build : %d\n", 2125 IPS_BUILD_IDENT); 2126 2127 seq_printf(m, "\tMax Physical Devices : %d\n", 2128 ha->enq->ucMaxPhysicalDevices); 2129 seq_printf(m, "\tMax Active Commands : %d\n", 2130 ha->max_cmds); 2131 seq_printf(m, "\tCurrent Queued Commands : %d\n", 2132 ha->scb_waitlist.count); 2133 seq_printf(m, "\tCurrent Active Commands : %d\n", 2134 ha->scb_activelist.count - ha->num_ioctl); 2135 seq_printf(m, "\tCurrent Queued PT Commands : %d\n", 2136 ha->copp_waitlist.count); 2137 seq_printf(m, "\tCurrent Active PT Commands : %d\n", 2138 ha->num_ioctl); 2139 2140 seq_printf(m, "\n"); 2141 2142 return 0; 2143 } 2144 2145 /****************************************************************************/ 2146 /* */ 2147 /* Routine Name: ips_identify_controller */ 2148 /* */ 2149 /* Routine Description: */ 2150 /* */ 2151 /* Identify this controller */ 2152 /* */ 2153 /****************************************************************************/ 2154 static void 2155 ips_identify_controller(ips_ha_t * ha) 2156 { 2157 METHOD_TRACE("ips_identify_controller", 1); 2158 2159 switch (ha->pcidev->device) { 2160 case IPS_DEVICEID_COPPERHEAD: 2161 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) { 2162 ha->ad_type = IPS_ADTYPE_SERVERAID; 2163 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) { 2164 ha->ad_type = IPS_ADTYPE_SERVERAID2; 2165 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) { 2166 ha->ad_type = IPS_ADTYPE_NAVAJO; 2167 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2) 2168 && (ha->slot_num == 0)) { 2169 ha->ad_type = IPS_ADTYPE_KIOWA; 2170 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) && 2171 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) { 2172 if (ha->enq->ucMaxPhysicalDevices == 15) 2173 ha->ad_type = IPS_ADTYPE_SERVERAID3L; 2174 else 2175 ha->ad_type = IPS_ADTYPE_SERVERAID3; 2176 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) && 2177 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) { 2178 ha->ad_type = IPS_ADTYPE_SERVERAID4H; 2179 } 2180 break; 2181 2182 case IPS_DEVICEID_MORPHEUS: 2183 switch (ha->pcidev->subsystem_device) { 2184 case IPS_SUBDEVICEID_4L: 2185 ha->ad_type = IPS_ADTYPE_SERVERAID4L; 2186 break; 2187 2188 case IPS_SUBDEVICEID_4M: 2189 ha->ad_type = IPS_ADTYPE_SERVERAID4M; 2190 break; 2191 2192 case IPS_SUBDEVICEID_4MX: 2193 ha->ad_type = IPS_ADTYPE_SERVERAID4MX; 2194 break; 2195 2196 case IPS_SUBDEVICEID_4LX: 2197 ha->ad_type = IPS_ADTYPE_SERVERAID4LX; 2198 break; 2199 2200 case IPS_SUBDEVICEID_5I2: 2201 ha->ad_type = IPS_ADTYPE_SERVERAID5I2; 2202 break; 2203 2204 case IPS_SUBDEVICEID_5I1: 2205 ha->ad_type = IPS_ADTYPE_SERVERAID5I1; 2206 break; 2207 } 2208 2209 break; 2210 2211 case IPS_DEVICEID_MARCO: 2212 switch (ha->pcidev->subsystem_device) { 2213 case IPS_SUBDEVICEID_6M: 2214 ha->ad_type = IPS_ADTYPE_SERVERAID6M; 2215 break; 2216 case IPS_SUBDEVICEID_6I: 2217 ha->ad_type = IPS_ADTYPE_SERVERAID6I; 2218 break; 2219 case IPS_SUBDEVICEID_7k: 2220 ha->ad_type = IPS_ADTYPE_SERVERAID7k; 2221 break; 2222 case IPS_SUBDEVICEID_7M: 2223 ha->ad_type = IPS_ADTYPE_SERVERAID7M; 2224 break; 2225 } 2226 break; 2227 } 2228 } 2229 2230 /****************************************************************************/ 2231 /* */ 2232 /* Routine Name: ips_get_bios_version */ 2233 /* */ 2234 /* Routine Description: */ 2235 /* */ 2236 /* Get the BIOS revision number */ 2237 /* */ 2238 /****************************************************************************/ 2239 static void 2240 ips_get_bios_version(ips_ha_t * ha, int intr) 2241 { 2242 ips_scb_t *scb; 2243 int ret; 2244 uint8_t major; 2245 uint8_t minor; 2246 uint8_t subminor; 2247 uint8_t *buffer; 2248 char hexDigits[] = 2249 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 2250 'D', 'E', 'F' }; 2251 2252 METHOD_TRACE("ips_get_bios_version", 1); 2253 2254 major = 0; 2255 minor = 0; 2256 2257 strncpy(ha->bios_version, " ?", 8); 2258 2259 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) { 2260 if (IPS_USE_MEMIO(ha)) { 2261 /* Memory Mapped I/O */ 2262 2263 /* test 1st byte */ 2264 writel(0, ha->mem_ptr + IPS_REG_FLAP); 2265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2266 udelay(25); /* 25 us */ 2267 2268 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 2269 return; 2270 2271 writel(1, ha->mem_ptr + IPS_REG_FLAP); 2272 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2273 udelay(25); /* 25 us */ 2274 2275 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 2276 return; 2277 2278 /* Get Major version */ 2279 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); 2280 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2281 udelay(25); /* 25 us */ 2282 2283 major = readb(ha->mem_ptr + IPS_REG_FLDP); 2284 2285 /* Get Minor version */ 2286 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); 2287 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2288 udelay(25); /* 25 us */ 2289 minor = readb(ha->mem_ptr + IPS_REG_FLDP); 2290 2291 /* Get SubMinor version */ 2292 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); 2293 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2294 udelay(25); /* 25 us */ 2295 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); 2296 2297 } else { 2298 /* Programmed I/O */ 2299 2300 /* test 1st byte */ 2301 outl(0, ha->io_addr + IPS_REG_FLAP); 2302 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2303 udelay(25); /* 25 us */ 2304 2305 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 2306 return; 2307 2308 outl(1, ha->io_addr + IPS_REG_FLAP); 2309 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2310 udelay(25); /* 25 us */ 2311 2312 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 2313 return; 2314 2315 /* Get Major version */ 2316 outl(0x1FF, ha->io_addr + IPS_REG_FLAP); 2317 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2318 udelay(25); /* 25 us */ 2319 2320 major = inb(ha->io_addr + IPS_REG_FLDP); 2321 2322 /* Get Minor version */ 2323 outl(0x1FE, ha->io_addr + IPS_REG_FLAP); 2324 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2325 udelay(25); /* 25 us */ 2326 2327 minor = inb(ha->io_addr + IPS_REG_FLDP); 2328 2329 /* Get SubMinor version */ 2330 outl(0x1FD, ha->io_addr + IPS_REG_FLAP); 2331 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2332 udelay(25); /* 25 us */ 2333 2334 subminor = inb(ha->io_addr + IPS_REG_FLDP); 2335 2336 } 2337 } else { 2338 /* Morpheus Family - Send Command to the card */ 2339 2340 buffer = ha->ioctl_data; 2341 2342 memset(buffer, 0, 0x1000); 2343 2344 scb = &ha->scbs[ha->max_cmds - 1]; 2345 2346 ips_init_scb(ha, scb); 2347 2348 scb->timeout = ips_cmd_timeout; 2349 scb->cdb[0] = IPS_CMD_RW_BIOSFW; 2350 2351 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW; 2352 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 2353 scb->cmd.flashfw.type = 1; 2354 scb->cmd.flashfw.direction = 0; 2355 scb->cmd.flashfw.count = cpu_to_le32(0x800); 2356 scb->cmd.flashfw.total_packets = 1; 2357 scb->cmd.flashfw.packet_num = 0; 2358 scb->data_len = 0x1000; 2359 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr; 2360 2361 /* issue the command */ 2362 if (((ret = 2363 ips_send_wait(ha, scb, ips_cmd_timeout, 2364 intr)) == IPS_FAILURE) 2365 || (ret == IPS_SUCCESS_IMM) 2366 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 2367 /* Error occurred */ 2368 2369 return; 2370 } 2371 2372 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) { 2373 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */ 2374 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */ 2375 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */ 2376 } else { 2377 return; 2378 } 2379 } 2380 2381 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4]; 2382 ha->bios_version[1] = '.'; 2383 ha->bios_version[2] = hexDigits[major & 0x0F]; 2384 ha->bios_version[3] = hexDigits[subminor]; 2385 ha->bios_version[4] = '.'; 2386 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4]; 2387 ha->bios_version[6] = hexDigits[minor & 0x0F]; 2388 ha->bios_version[7] = 0; 2389 } 2390 2391 /****************************************************************************/ 2392 /* */ 2393 /* Routine Name: ips_hainit */ 2394 /* */ 2395 /* Routine Description: */ 2396 /* */ 2397 /* Initialize the controller */ 2398 /* */ 2399 /* NOTE: Assumes to be called from with a lock */ 2400 /* */ 2401 /****************************************************************************/ 2402 static int 2403 ips_hainit(ips_ha_t * ha) 2404 { 2405 int i; 2406 struct timeval tv; 2407 2408 METHOD_TRACE("ips_hainit", 1); 2409 2410 if (!ha) 2411 return (0); 2412 2413 if (ha->func.statinit) 2414 (*ha->func.statinit) (ha); 2415 2416 if (ha->func.enableint) 2417 (*ha->func.enableint) (ha); 2418 2419 /* Send FFDC */ 2420 ha->reset_count = 1; 2421 do_gettimeofday(&tv); 2422 ha->last_ffdc = tv.tv_sec; 2423 ips_ffdc_reset(ha, IPS_INTR_IORL); 2424 2425 if (!ips_read_config(ha, IPS_INTR_IORL)) { 2426 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2427 "unable to read config from controller.\n"); 2428 2429 return (0); 2430 } 2431 /* end if */ 2432 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) { 2433 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2434 "unable to read controller status.\n"); 2435 2436 return (0); 2437 } 2438 2439 /* Identify this controller */ 2440 ips_identify_controller(ha); 2441 2442 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) { 2443 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2444 "unable to read subsystem parameters.\n"); 2445 2446 return (0); 2447 } 2448 2449 /* write nvram user page 5 */ 2450 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) { 2451 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2452 "unable to write driver info to controller.\n"); 2453 2454 return (0); 2455 } 2456 2457 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */ 2458 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1)) 2459 ips_clear_adapter(ha, IPS_INTR_IORL); 2460 2461 /* set limits on SID, LUN, BUS */ 2462 ha->ntargets = IPS_MAX_TARGETS + 1; 2463 ha->nlun = 1; 2464 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1; 2465 2466 switch (ha->conf->logical_drive[0].ucStripeSize) { 2467 case 4: 2468 ha->max_xfer = 0x10000; 2469 break; 2470 2471 case 5: 2472 ha->max_xfer = 0x20000; 2473 break; 2474 2475 case 6: 2476 ha->max_xfer = 0x40000; 2477 break; 2478 2479 case 7: 2480 default: 2481 ha->max_xfer = 0x80000; 2482 break; 2483 } 2484 2485 /* setup max concurrent commands */ 2486 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) { 2487 /* Use the new method */ 2488 ha->max_cmds = ha->enq->ucConcurrentCmdCount; 2489 } else { 2490 /* use the old method */ 2491 switch (ha->conf->logical_drive[0].ucStripeSize) { 2492 case 4: 2493 ha->max_cmds = 32; 2494 break; 2495 2496 case 5: 2497 ha->max_cmds = 16; 2498 break; 2499 2500 case 6: 2501 ha->max_cmds = 8; 2502 break; 2503 2504 case 7: 2505 default: 2506 ha->max_cmds = 4; 2507 break; 2508 } 2509 } 2510 2511 /* Limit the Active Commands on a Lite Adapter */ 2512 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) || 2513 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) || 2514 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) { 2515 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds)) 2516 ha->max_cmds = MaxLiteCmds; 2517 } 2518 2519 /* set controller IDs */ 2520 ha->ha_id[0] = IPS_ADAPTER_ID; 2521 for (i = 1; i < ha->nbus; i++) { 2522 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f; 2523 ha->dcdb_active[i - 1] = 0; 2524 } 2525 2526 return (1); 2527 } 2528 2529 /****************************************************************************/ 2530 /* */ 2531 /* Routine Name: ips_next */ 2532 /* */ 2533 /* Routine Description: */ 2534 /* */ 2535 /* Take the next command off the queue and send it to the controller */ 2536 /* */ 2537 /****************************************************************************/ 2538 static void 2539 ips_next(ips_ha_t * ha, int intr) 2540 { 2541 ips_scb_t *scb; 2542 struct scsi_cmnd *SC; 2543 struct scsi_cmnd *p; 2544 struct scsi_cmnd *q; 2545 ips_copp_wait_item_t *item; 2546 int ret; 2547 struct Scsi_Host *host; 2548 METHOD_TRACE("ips_next", 1); 2549 2550 if (!ha) 2551 return; 2552 host = ips_sh[ha->host_num]; 2553 /* 2554 * Block access to the queue function so 2555 * this command won't time out 2556 */ 2557 if (intr == IPS_INTR_ON) 2558 spin_lock(host->host_lock); 2559 2560 if ((ha->subsys->param[3] & 0x300000) 2561 && (ha->scb_activelist.count == 0)) { 2562 struct timeval tv; 2563 2564 do_gettimeofday(&tv); 2565 2566 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) { 2567 ha->last_ffdc = tv.tv_sec; 2568 ips_ffdc_time(ha); 2569 } 2570 } 2571 2572 /* 2573 * Send passthru commands 2574 * These have priority over normal I/O 2575 * but shouldn't affect performance too much 2576 * since we limit the number that can be active 2577 * on the card at any one time 2578 */ 2579 while ((ha->num_ioctl < IPS_MAX_IOCTL) && 2580 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) { 2581 2582 item = ips_removeq_copp_head(&ha->copp_waitlist); 2583 ha->num_ioctl++; 2584 if (intr == IPS_INTR_ON) 2585 spin_unlock(host->host_lock); 2586 scb->scsi_cmd = item->scsi_cmd; 2587 kfree(item); 2588 2589 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr); 2590 2591 if (intr == IPS_INTR_ON) 2592 spin_lock(host->host_lock); 2593 switch (ret) { 2594 case IPS_FAILURE: 2595 if (scb->scsi_cmd) { 2596 scb->scsi_cmd->result = DID_ERROR << 16; 2597 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2598 } 2599 2600 ips_freescb(ha, scb); 2601 break; 2602 case IPS_SUCCESS_IMM: 2603 if (scb->scsi_cmd) { 2604 scb->scsi_cmd->result = DID_OK << 16; 2605 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2606 } 2607 2608 ips_freescb(ha, scb); 2609 break; 2610 default: 2611 break; 2612 } /* end case */ 2613 2614 if (ret != IPS_SUCCESS) { 2615 ha->num_ioctl--; 2616 continue; 2617 } 2618 2619 ret = ips_send_cmd(ha, scb); 2620 2621 if (ret == IPS_SUCCESS) 2622 ips_putq_scb_head(&ha->scb_activelist, scb); 2623 else 2624 ha->num_ioctl--; 2625 2626 switch (ret) { 2627 case IPS_FAILURE: 2628 if (scb->scsi_cmd) { 2629 scb->scsi_cmd->result = DID_ERROR << 16; 2630 } 2631 2632 ips_freescb(ha, scb); 2633 break; 2634 case IPS_SUCCESS_IMM: 2635 ips_freescb(ha, scb); 2636 break; 2637 default: 2638 break; 2639 } /* end case */ 2640 2641 } 2642 2643 /* 2644 * Send "Normal" I/O commands 2645 */ 2646 2647 p = ha->scb_waitlist.head; 2648 while ((p) && (scb = ips_getscb(ha))) { 2649 if ((scmd_channel(p) > 0) 2650 && (ha-> 2651 dcdb_active[scmd_channel(p) - 2652 1] & (1 << scmd_id(p)))) { 2653 ips_freescb(ha, scb); 2654 p = (struct scsi_cmnd *) p->host_scribble; 2655 continue; 2656 } 2657 2658 q = p; 2659 SC = ips_removeq_wait(&ha->scb_waitlist, q); 2660 2661 if (intr == IPS_INTR_ON) 2662 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */ 2663 2664 SC->result = DID_OK; 2665 SC->host_scribble = NULL; 2666 2667 scb->target_id = SC->device->id; 2668 scb->lun = SC->device->lun; 2669 scb->bus = SC->device->channel; 2670 scb->scsi_cmd = SC; 2671 scb->breakup = 0; 2672 scb->data_len = 0; 2673 scb->callback = ipsintr_done; 2674 scb->timeout = ips_cmd_timeout; 2675 memset(&scb->cmd, 0, 16); 2676 2677 /* copy in the CDB */ 2678 memcpy(scb->cdb, SC->cmnd, SC->cmd_len); 2679 2680 scb->sg_count = scsi_dma_map(SC); 2681 BUG_ON(scb->sg_count < 0); 2682 if (scb->sg_count) { 2683 struct scatterlist *sg; 2684 int i; 2685 2686 scb->flags |= IPS_SCB_MAP_SG; 2687 2688 scsi_for_each_sg(SC, sg, scb->sg_count, i) { 2689 if (ips_fill_scb_sg_single 2690 (ha, sg_dma_address(sg), scb, i, 2691 sg_dma_len(sg)) < 0) 2692 break; 2693 } 2694 scb->dcdb.transfer_length = scb->data_len; 2695 } else { 2696 scb->data_busaddr = 0L; 2697 scb->sg_len = 0; 2698 scb->data_len = 0; 2699 scb->dcdb.transfer_length = 0; 2700 } 2701 2702 scb->dcdb.cmd_attribute = 2703 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 2704 2705 /* Allow a WRITE BUFFER Command to Have no Data */ 2706 /* This is Used by Tape Flash Utilites */ 2707 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && 2708 (scb->data_len == 0)) 2709 scb->dcdb.cmd_attribute = 0; 2710 2711 if (!(scb->dcdb.cmd_attribute & 0x3)) 2712 scb->dcdb.transfer_length = 0; 2713 2714 if (scb->data_len >= IPS_MAX_XFER) { 2715 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 2716 scb->dcdb.transfer_length = 0; 2717 } 2718 if (intr == IPS_INTR_ON) 2719 spin_lock(host->host_lock); 2720 2721 ret = ips_send_cmd(ha, scb); 2722 2723 switch (ret) { 2724 case IPS_SUCCESS: 2725 ips_putq_scb_head(&ha->scb_activelist, scb); 2726 break; 2727 case IPS_FAILURE: 2728 if (scb->scsi_cmd) { 2729 scb->scsi_cmd->result = DID_ERROR << 16; 2730 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2731 } 2732 2733 if (scb->bus) 2734 ha->dcdb_active[scb->bus - 1] &= 2735 ~(1 << scb->target_id); 2736 2737 ips_freescb(ha, scb); 2738 break; 2739 case IPS_SUCCESS_IMM: 2740 if (scb->scsi_cmd) 2741 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2742 2743 if (scb->bus) 2744 ha->dcdb_active[scb->bus - 1] &= 2745 ~(1 << scb->target_id); 2746 2747 ips_freescb(ha, scb); 2748 break; 2749 default: 2750 break; 2751 } /* end case */ 2752 2753 p = (struct scsi_cmnd *) p->host_scribble; 2754 2755 } /* end while */ 2756 2757 if (intr == IPS_INTR_ON) 2758 spin_unlock(host->host_lock); 2759 } 2760 2761 /****************************************************************************/ 2762 /* */ 2763 /* Routine Name: ips_putq_scb_head */ 2764 /* */ 2765 /* Routine Description: */ 2766 /* */ 2767 /* Add an item to the head of the queue */ 2768 /* */ 2769 /* ASSUMED to be called from within the HA lock */ 2770 /* */ 2771 /****************************************************************************/ 2772 static void 2773 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item) 2774 { 2775 METHOD_TRACE("ips_putq_scb_head", 1); 2776 2777 if (!item) 2778 return; 2779 2780 item->q_next = queue->head; 2781 queue->head = item; 2782 2783 if (!queue->tail) 2784 queue->tail = item; 2785 2786 queue->count++; 2787 } 2788 2789 /****************************************************************************/ 2790 /* */ 2791 /* Routine Name: ips_removeq_scb_head */ 2792 /* */ 2793 /* Routine Description: */ 2794 /* */ 2795 /* Remove the head of the queue */ 2796 /* */ 2797 /* ASSUMED to be called from within the HA lock */ 2798 /* */ 2799 /****************************************************************************/ 2800 static ips_scb_t * 2801 ips_removeq_scb_head(ips_scb_queue_t * queue) 2802 { 2803 ips_scb_t *item; 2804 2805 METHOD_TRACE("ips_removeq_scb_head", 1); 2806 2807 item = queue->head; 2808 2809 if (!item) { 2810 return (NULL); 2811 } 2812 2813 queue->head = item->q_next; 2814 item->q_next = NULL; 2815 2816 if (queue->tail == item) 2817 queue->tail = NULL; 2818 2819 queue->count--; 2820 2821 return (item); 2822 } 2823 2824 /****************************************************************************/ 2825 /* */ 2826 /* Routine Name: ips_removeq_scb */ 2827 /* */ 2828 /* Routine Description: */ 2829 /* */ 2830 /* Remove an item from a queue */ 2831 /* */ 2832 /* ASSUMED to be called from within the HA lock */ 2833 /* */ 2834 /****************************************************************************/ 2835 static ips_scb_t * 2836 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item) 2837 { 2838 ips_scb_t *p; 2839 2840 METHOD_TRACE("ips_removeq_scb", 1); 2841 2842 if (!item) 2843 return (NULL); 2844 2845 if (item == queue->head) { 2846 return (ips_removeq_scb_head(queue)); 2847 } 2848 2849 p = queue->head; 2850 2851 while ((p) && (item != p->q_next)) 2852 p = p->q_next; 2853 2854 if (p) { 2855 /* found a match */ 2856 p->q_next = item->q_next; 2857 2858 if (!item->q_next) 2859 queue->tail = p; 2860 2861 item->q_next = NULL; 2862 queue->count--; 2863 2864 return (item); 2865 } 2866 2867 return (NULL); 2868 } 2869 2870 /****************************************************************************/ 2871 /* */ 2872 /* Routine Name: ips_putq_wait_tail */ 2873 /* */ 2874 /* Routine Description: */ 2875 /* */ 2876 /* Add an item to the tail of the queue */ 2877 /* */ 2878 /* ASSUMED to be called from within the HA lock */ 2879 /* */ 2880 /****************************************************************************/ 2881 static void ips_putq_wait_tail(ips_wait_queue_t *queue, struct scsi_cmnd *item) 2882 { 2883 METHOD_TRACE("ips_putq_wait_tail", 1); 2884 2885 if (!item) 2886 return; 2887 2888 item->host_scribble = NULL; 2889 2890 if (queue->tail) 2891 queue->tail->host_scribble = (char *) item; 2892 2893 queue->tail = item; 2894 2895 if (!queue->head) 2896 queue->head = item; 2897 2898 queue->count++; 2899 } 2900 2901 /****************************************************************************/ 2902 /* */ 2903 /* Routine Name: ips_removeq_wait_head */ 2904 /* */ 2905 /* Routine Description: */ 2906 /* */ 2907 /* Remove the head of the queue */ 2908 /* */ 2909 /* ASSUMED to be called from within the HA lock */ 2910 /* */ 2911 /****************************************************************************/ 2912 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *queue) 2913 { 2914 struct scsi_cmnd *item; 2915 2916 METHOD_TRACE("ips_removeq_wait_head", 1); 2917 2918 item = queue->head; 2919 2920 if (!item) { 2921 return (NULL); 2922 } 2923 2924 queue->head = (struct scsi_cmnd *) item->host_scribble; 2925 item->host_scribble = NULL; 2926 2927 if (queue->tail == item) 2928 queue->tail = NULL; 2929 2930 queue->count--; 2931 2932 return (item); 2933 } 2934 2935 /****************************************************************************/ 2936 /* */ 2937 /* Routine Name: ips_removeq_wait */ 2938 /* */ 2939 /* Routine Description: */ 2940 /* */ 2941 /* Remove an item from a queue */ 2942 /* */ 2943 /* ASSUMED to be called from within the HA lock */ 2944 /* */ 2945 /****************************************************************************/ 2946 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *queue, 2947 struct scsi_cmnd *item) 2948 { 2949 struct scsi_cmnd *p; 2950 2951 METHOD_TRACE("ips_removeq_wait", 1); 2952 2953 if (!item) 2954 return (NULL); 2955 2956 if (item == queue->head) { 2957 return (ips_removeq_wait_head(queue)); 2958 } 2959 2960 p = queue->head; 2961 2962 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble)) 2963 p = (struct scsi_cmnd *) p->host_scribble; 2964 2965 if (p) { 2966 /* found a match */ 2967 p->host_scribble = item->host_scribble; 2968 2969 if (!item->host_scribble) 2970 queue->tail = p; 2971 2972 item->host_scribble = NULL; 2973 queue->count--; 2974 2975 return (item); 2976 } 2977 2978 return (NULL); 2979 } 2980 2981 /****************************************************************************/ 2982 /* */ 2983 /* Routine Name: ips_putq_copp_tail */ 2984 /* */ 2985 /* Routine Description: */ 2986 /* */ 2987 /* Add an item to the tail of the queue */ 2988 /* */ 2989 /* ASSUMED to be called from within the HA lock */ 2990 /* */ 2991 /****************************************************************************/ 2992 static void 2993 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 2994 { 2995 METHOD_TRACE("ips_putq_copp_tail", 1); 2996 2997 if (!item) 2998 return; 2999 3000 item->next = NULL; 3001 3002 if (queue->tail) 3003 queue->tail->next = item; 3004 3005 queue->tail = item; 3006 3007 if (!queue->head) 3008 queue->head = item; 3009 3010 queue->count++; 3011 } 3012 3013 /****************************************************************************/ 3014 /* */ 3015 /* Routine Name: ips_removeq_copp_head */ 3016 /* */ 3017 /* Routine Description: */ 3018 /* */ 3019 /* Remove the head of the queue */ 3020 /* */ 3021 /* ASSUMED to be called from within the HA lock */ 3022 /* */ 3023 /****************************************************************************/ 3024 static ips_copp_wait_item_t * 3025 ips_removeq_copp_head(ips_copp_queue_t * queue) 3026 { 3027 ips_copp_wait_item_t *item; 3028 3029 METHOD_TRACE("ips_removeq_copp_head", 1); 3030 3031 item = queue->head; 3032 3033 if (!item) { 3034 return (NULL); 3035 } 3036 3037 queue->head = item->next; 3038 item->next = NULL; 3039 3040 if (queue->tail == item) 3041 queue->tail = NULL; 3042 3043 queue->count--; 3044 3045 return (item); 3046 } 3047 3048 /****************************************************************************/ 3049 /* */ 3050 /* Routine Name: ips_removeq_copp */ 3051 /* */ 3052 /* Routine Description: */ 3053 /* */ 3054 /* Remove an item from a queue */ 3055 /* */ 3056 /* ASSUMED to be called from within the HA lock */ 3057 /* */ 3058 /****************************************************************************/ 3059 static ips_copp_wait_item_t * 3060 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 3061 { 3062 ips_copp_wait_item_t *p; 3063 3064 METHOD_TRACE("ips_removeq_copp", 1); 3065 3066 if (!item) 3067 return (NULL); 3068 3069 if (item == queue->head) { 3070 return (ips_removeq_copp_head(queue)); 3071 } 3072 3073 p = queue->head; 3074 3075 while ((p) && (item != p->next)) 3076 p = p->next; 3077 3078 if (p) { 3079 /* found a match */ 3080 p->next = item->next; 3081 3082 if (!item->next) 3083 queue->tail = p; 3084 3085 item->next = NULL; 3086 queue->count--; 3087 3088 return (item); 3089 } 3090 3091 return (NULL); 3092 } 3093 3094 /****************************************************************************/ 3095 /* */ 3096 /* Routine Name: ipsintr_blocking */ 3097 /* */ 3098 /* Routine Description: */ 3099 /* */ 3100 /* Finalize an interrupt for internal commands */ 3101 /* */ 3102 /****************************************************************************/ 3103 static void 3104 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb) 3105 { 3106 METHOD_TRACE("ipsintr_blocking", 2); 3107 3108 ips_freescb(ha, scb); 3109 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) { 3110 ha->waitflag = FALSE; 3111 3112 return; 3113 } 3114 } 3115 3116 /****************************************************************************/ 3117 /* */ 3118 /* Routine Name: ipsintr_done */ 3119 /* */ 3120 /* Routine Description: */ 3121 /* */ 3122 /* Finalize an interrupt for non-internal commands */ 3123 /* */ 3124 /****************************************************************************/ 3125 static void 3126 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb) 3127 { 3128 METHOD_TRACE("ipsintr_done", 2); 3129 3130 if (!scb) { 3131 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3132 "Spurious interrupt; scb NULL.\n"); 3133 3134 return; 3135 } 3136 3137 if (scb->scsi_cmd == NULL) { 3138 /* unexpected interrupt */ 3139 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3140 "Spurious interrupt; scsi_cmd not set.\n"); 3141 3142 return; 3143 } 3144 3145 ips_done(ha, scb); 3146 } 3147 3148 /****************************************************************************/ 3149 /* */ 3150 /* Routine Name: ips_done */ 3151 /* */ 3152 /* Routine Description: */ 3153 /* */ 3154 /* Do housekeeping on completed commands */ 3155 /* ASSUMED to be called form within the request lock */ 3156 /****************************************************************************/ 3157 static void 3158 ips_done(ips_ha_t * ha, ips_scb_t * scb) 3159 { 3160 int ret; 3161 3162 METHOD_TRACE("ips_done", 1); 3163 3164 if (!scb) 3165 return; 3166 3167 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) { 3168 ips_cleanup_passthru(ha, scb); 3169 ha->num_ioctl--; 3170 } else { 3171 /* 3172 * Check to see if this command had too much 3173 * data and had to be broke up. If so, queue 3174 * the rest of the data and continue. 3175 */ 3176 if ((scb->breakup) || (scb->sg_break)) { 3177 struct scatterlist *sg; 3178 int i, sg_dma_index, ips_sg_index = 0; 3179 3180 /* we had a data breakup */ 3181 scb->data_len = 0; 3182 3183 sg = scsi_sglist(scb->scsi_cmd); 3184 3185 /* Spin forward to last dma chunk */ 3186 sg_dma_index = scb->breakup; 3187 for (i = 0; i < scb->breakup; i++) 3188 sg = sg_next(sg); 3189 3190 /* Take care of possible partial on last chunk */ 3191 ips_fill_scb_sg_single(ha, 3192 sg_dma_address(sg), 3193 scb, ips_sg_index++, 3194 sg_dma_len(sg)); 3195 3196 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd); 3197 sg_dma_index++, sg = sg_next(sg)) { 3198 if (ips_fill_scb_sg_single 3199 (ha, 3200 sg_dma_address(sg), 3201 scb, ips_sg_index++, 3202 sg_dma_len(sg)) < 0) 3203 break; 3204 } 3205 3206 scb->dcdb.transfer_length = scb->data_len; 3207 scb->dcdb.cmd_attribute |= 3208 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 3209 3210 if (!(scb->dcdb.cmd_attribute & 0x3)) 3211 scb->dcdb.transfer_length = 0; 3212 3213 if (scb->data_len >= IPS_MAX_XFER) { 3214 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 3215 scb->dcdb.transfer_length = 0; 3216 } 3217 3218 ret = ips_send_cmd(ha, scb); 3219 3220 switch (ret) { 3221 case IPS_FAILURE: 3222 if (scb->scsi_cmd) { 3223 scb->scsi_cmd->result = DID_ERROR << 16; 3224 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3225 } 3226 3227 ips_freescb(ha, scb); 3228 break; 3229 case IPS_SUCCESS_IMM: 3230 if (scb->scsi_cmd) { 3231 scb->scsi_cmd->result = DID_ERROR << 16; 3232 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3233 } 3234 3235 ips_freescb(ha, scb); 3236 break; 3237 default: 3238 break; 3239 } /* end case */ 3240 3241 return; 3242 } 3243 } /* end if passthru */ 3244 3245 if (scb->bus) { 3246 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id); 3247 } 3248 3249 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3250 3251 ips_freescb(ha, scb); 3252 } 3253 3254 /****************************************************************************/ 3255 /* */ 3256 /* Routine Name: ips_map_status */ 3257 /* */ 3258 /* Routine Description: */ 3259 /* */ 3260 /* Map Controller Error codes to Linux Error Codes */ 3261 /* */ 3262 /****************************************************************************/ 3263 static int 3264 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp) 3265 { 3266 int errcode; 3267 int device_error; 3268 uint32_t transfer_len; 3269 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3270 IPS_SCSI_INQ_DATA inquiryData; 3271 3272 METHOD_TRACE("ips_map_status", 1); 3273 3274 if (scb->bus) { 3275 DEBUG_VAR(2, 3276 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x", 3277 ips_name, ha->host_num, 3278 scb->scsi_cmd->device->channel, 3279 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun, 3280 scb->basic_status, scb->extended_status, 3281 scb->extended_status == 3282 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0, 3283 scb->extended_status == 3284 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0, 3285 scb->extended_status == 3286 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0); 3287 } 3288 3289 /* default driver error */ 3290 errcode = DID_ERROR; 3291 device_error = 0; 3292 3293 switch (scb->basic_status & IPS_GSC_STATUS_MASK) { 3294 case IPS_CMD_TIMEOUT: 3295 errcode = DID_TIME_OUT; 3296 break; 3297 3298 case IPS_INVAL_OPCO: 3299 case IPS_INVAL_CMD_BLK: 3300 case IPS_INVAL_PARM_BLK: 3301 case IPS_LD_ERROR: 3302 case IPS_CMD_CMPLT_WERROR: 3303 break; 3304 3305 case IPS_PHYS_DRV_ERROR: 3306 switch (scb->extended_status) { 3307 case IPS_ERR_SEL_TO: 3308 if (scb->bus) 3309 errcode = DID_NO_CONNECT; 3310 3311 break; 3312 3313 case IPS_ERR_OU_RUN: 3314 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) || 3315 (scb->cmd.dcdb.op_code == 3316 IPS_CMD_EXTENDED_DCDB_SG)) { 3317 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3318 transfer_len = tapeDCDB->transfer_length; 3319 } else { 3320 transfer_len = 3321 (uint32_t) scb->dcdb.transfer_length; 3322 } 3323 3324 if ((scb->bus) && (transfer_len < scb->data_len)) { 3325 /* Underrun - set default to no error */ 3326 errcode = DID_OK; 3327 3328 /* Restrict access to physical DASD */ 3329 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3330 ips_scmd_buf_read(scb->scsi_cmd, 3331 &inquiryData, sizeof (inquiryData)); 3332 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { 3333 errcode = DID_TIME_OUT; 3334 break; 3335 } 3336 } 3337 } else 3338 errcode = DID_ERROR; 3339 3340 break; 3341 3342 case IPS_ERR_RECOVERY: 3343 /* don't fail recovered errors */ 3344 if (scb->bus) 3345 errcode = DID_OK; 3346 3347 break; 3348 3349 case IPS_ERR_HOST_RESET: 3350 case IPS_ERR_DEV_RESET: 3351 errcode = DID_RESET; 3352 break; 3353 3354 case IPS_ERR_CKCOND: 3355 if (scb->bus) { 3356 if ((scb->cmd.dcdb.op_code == 3357 IPS_CMD_EXTENDED_DCDB) 3358 || (scb->cmd.dcdb.op_code == 3359 IPS_CMD_EXTENDED_DCDB_SG)) { 3360 tapeDCDB = 3361 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3362 memcpy(scb->scsi_cmd->sense_buffer, 3363 tapeDCDB->sense_info, 3364 SCSI_SENSE_BUFFERSIZE); 3365 } else { 3366 memcpy(scb->scsi_cmd->sense_buffer, 3367 scb->dcdb.sense_info, 3368 SCSI_SENSE_BUFFERSIZE); 3369 } 3370 device_error = 2; /* check condition */ 3371 } 3372 3373 errcode = DID_OK; 3374 3375 break; 3376 3377 default: 3378 errcode = DID_ERROR; 3379 break; 3380 3381 } /* end switch */ 3382 } /* end switch */ 3383 3384 scb->scsi_cmd->result = device_error | (errcode << 16); 3385 3386 return (1); 3387 } 3388 3389 /****************************************************************************/ 3390 /* */ 3391 /* Routine Name: ips_send_wait */ 3392 /* */ 3393 /* Routine Description: */ 3394 /* */ 3395 /* Send a command to the controller and wait for it to return */ 3396 /* */ 3397 /* The FFDC Time Stamp use this function for the callback, but doesn't */ 3398 /* actually need to wait. */ 3399 /****************************************************************************/ 3400 static int 3401 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) 3402 { 3403 int ret; 3404 3405 METHOD_TRACE("ips_send_wait", 1); 3406 3407 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */ 3408 ha->waitflag = TRUE; 3409 ha->cmd_in_progress = scb->cdb[0]; 3410 } 3411 scb->callback = ipsintr_blocking; 3412 ret = ips_send_cmd(ha, scb); 3413 3414 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)) 3415 return (ret); 3416 3417 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */ 3418 ret = ips_wait(ha, timeout, intr); 3419 3420 return (ret); 3421 } 3422 3423 /****************************************************************************/ 3424 /* */ 3425 /* Routine Name: ips_scmd_buf_write */ 3426 /* */ 3427 /* Routine Description: */ 3428 /* Write data to struct scsi_cmnd request_buffer at proper offsets */ 3429 /****************************************************************************/ 3430 static void 3431 ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count) 3432 { 3433 unsigned long flags; 3434 3435 local_irq_save(flags); 3436 scsi_sg_copy_from_buffer(scmd, data, count); 3437 local_irq_restore(flags); 3438 } 3439 3440 /****************************************************************************/ 3441 /* */ 3442 /* Routine Name: ips_scmd_buf_read */ 3443 /* */ 3444 /* Routine Description: */ 3445 /* Copy data from a struct scsi_cmnd to a new, linear buffer */ 3446 /****************************************************************************/ 3447 static void 3448 ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count) 3449 { 3450 unsigned long flags; 3451 3452 local_irq_save(flags); 3453 scsi_sg_copy_to_buffer(scmd, data, count); 3454 local_irq_restore(flags); 3455 } 3456 3457 /****************************************************************************/ 3458 /* */ 3459 /* Routine Name: ips_send_cmd */ 3460 /* */ 3461 /* Routine Description: */ 3462 /* */ 3463 /* Map SCSI commands to ServeRAID commands for logical drives */ 3464 /* */ 3465 /****************************************************************************/ 3466 static int 3467 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb) 3468 { 3469 int ret; 3470 char *sp; 3471 int device_error; 3472 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3473 int TimeOut; 3474 3475 METHOD_TRACE("ips_send_cmd", 1); 3476 3477 ret = IPS_SUCCESS; 3478 3479 if (!scb->scsi_cmd) { 3480 /* internal command */ 3481 3482 if (scb->bus > 0) { 3483 /* Controller commands can't be issued */ 3484 /* to real devices -- fail them */ 3485 if ((ha->waitflag == TRUE) && 3486 (ha->cmd_in_progress == scb->cdb[0])) { 3487 ha->waitflag = FALSE; 3488 } 3489 3490 return (1); 3491 } 3492 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) { 3493 /* command to logical bus -- interpret */ 3494 ret = IPS_SUCCESS_IMM; 3495 3496 switch (scb->scsi_cmd->cmnd[0]) { 3497 case ALLOW_MEDIUM_REMOVAL: 3498 case REZERO_UNIT: 3499 case ERASE: 3500 case WRITE_FILEMARKS: 3501 case SPACE: 3502 scb->scsi_cmd->result = DID_ERROR << 16; 3503 break; 3504 3505 case START_STOP: 3506 scb->scsi_cmd->result = DID_OK << 16; 3507 3508 case TEST_UNIT_READY: 3509 case INQUIRY: 3510 if (scb->target_id == IPS_ADAPTER_ID) { 3511 /* 3512 * Either we have a TUR 3513 * or we have a SCSI inquiry 3514 */ 3515 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY) 3516 scb->scsi_cmd->result = DID_OK << 16; 3517 3518 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3519 IPS_SCSI_INQ_DATA inquiry; 3520 3521 memset(&inquiry, 0, 3522 sizeof (IPS_SCSI_INQ_DATA)); 3523 3524 inquiry.DeviceType = 3525 IPS_SCSI_INQ_TYPE_PROCESSOR; 3526 inquiry.DeviceTypeQualifier = 3527 IPS_SCSI_INQ_LU_CONNECTED; 3528 inquiry.Version = IPS_SCSI_INQ_REV2; 3529 inquiry.ResponseDataFormat = 3530 IPS_SCSI_INQ_RD_REV2; 3531 inquiry.AdditionalLength = 31; 3532 inquiry.Flags[0] = 3533 IPS_SCSI_INQ_Address16; 3534 inquiry.Flags[1] = 3535 IPS_SCSI_INQ_WBus16 | 3536 IPS_SCSI_INQ_Sync; 3537 strncpy(inquiry.VendorId, "IBM ", 3538 8); 3539 strncpy(inquiry.ProductId, 3540 "SERVERAID ", 16); 3541 strncpy(inquiry.ProductRevisionLevel, 3542 "1.00", 4); 3543 3544 ips_scmd_buf_write(scb->scsi_cmd, 3545 &inquiry, 3546 sizeof (inquiry)); 3547 3548 scb->scsi_cmd->result = DID_OK << 16; 3549 } 3550 } else { 3551 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3552 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3553 scb->cmd.logical_info.reserved = 0; 3554 scb->cmd.logical_info.reserved2 = 0; 3555 scb->data_len = sizeof (IPS_LD_INFO); 3556 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3557 scb->flags = 0; 3558 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3559 ret = IPS_SUCCESS; 3560 } 3561 3562 break; 3563 3564 case REQUEST_SENSE: 3565 ips_reqsen(ha, scb); 3566 scb->scsi_cmd->result = DID_OK << 16; 3567 break; 3568 3569 case READ_6: 3570 case WRITE_6: 3571 if (!scb->sg_len) { 3572 scb->cmd.basic_io.op_code = 3573 (scb->scsi_cmd->cmnd[0] == 3574 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE; 3575 scb->cmd.basic_io.enhanced_sg = 0; 3576 scb->cmd.basic_io.sg_addr = 3577 cpu_to_le32(scb->data_busaddr); 3578 } else { 3579 scb->cmd.basic_io.op_code = 3580 (scb->scsi_cmd->cmnd[0] == 3581 READ_6) ? IPS_CMD_READ_SG : 3582 IPS_CMD_WRITE_SG; 3583 scb->cmd.basic_io.enhanced_sg = 3584 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3585 scb->cmd.basic_io.sg_addr = 3586 cpu_to_le32(scb->sg_busaddr); 3587 } 3588 3589 scb->cmd.basic_io.segment_4G = 0; 3590 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3591 scb->cmd.basic_io.log_drv = scb->target_id; 3592 scb->cmd.basic_io.sg_count = scb->sg_len; 3593 3594 if (scb->cmd.basic_io.lba) 3595 le32_add_cpu(&scb->cmd.basic_io.lba, 3596 le16_to_cpu(scb->cmd.basic_io. 3597 sector_count)); 3598 else 3599 scb->cmd.basic_io.lba = 3600 (((scb->scsi_cmd-> 3601 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd-> 3602 cmnd[2] << 8) | 3603 (scb->scsi_cmd->cmnd[3])); 3604 3605 scb->cmd.basic_io.sector_count = 3606 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3607 3608 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0) 3609 scb->cmd.basic_io.sector_count = 3610 cpu_to_le16(256); 3611 3612 ret = IPS_SUCCESS; 3613 break; 3614 3615 case READ_10: 3616 case WRITE_10: 3617 if (!scb->sg_len) { 3618 scb->cmd.basic_io.op_code = 3619 (scb->scsi_cmd->cmnd[0] == 3620 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE; 3621 scb->cmd.basic_io.enhanced_sg = 0; 3622 scb->cmd.basic_io.sg_addr = 3623 cpu_to_le32(scb->data_busaddr); 3624 } else { 3625 scb->cmd.basic_io.op_code = 3626 (scb->scsi_cmd->cmnd[0] == 3627 READ_10) ? IPS_CMD_READ_SG : 3628 IPS_CMD_WRITE_SG; 3629 scb->cmd.basic_io.enhanced_sg = 3630 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3631 scb->cmd.basic_io.sg_addr = 3632 cpu_to_le32(scb->sg_busaddr); 3633 } 3634 3635 scb->cmd.basic_io.segment_4G = 0; 3636 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3637 scb->cmd.basic_io.log_drv = scb->target_id; 3638 scb->cmd.basic_io.sg_count = scb->sg_len; 3639 3640 if (scb->cmd.basic_io.lba) 3641 le32_add_cpu(&scb->cmd.basic_io.lba, 3642 le16_to_cpu(scb->cmd.basic_io. 3643 sector_count)); 3644 else 3645 scb->cmd.basic_io.lba = 3646 ((scb->scsi_cmd->cmnd[2] << 24) | (scb-> 3647 scsi_cmd-> 3648 cmnd[3] 3649 << 16) | 3650 (scb->scsi_cmd->cmnd[4] << 8) | scb-> 3651 scsi_cmd->cmnd[5]); 3652 3653 scb->cmd.basic_io.sector_count = 3654 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3655 3656 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) { 3657 /* 3658 * This is a null condition 3659 * we don't have to do anything 3660 * so just return 3661 */ 3662 scb->scsi_cmd->result = DID_OK << 16; 3663 } else 3664 ret = IPS_SUCCESS; 3665 3666 break; 3667 3668 case RESERVE: 3669 case RELEASE: 3670 scb->scsi_cmd->result = DID_OK << 16; 3671 break; 3672 3673 case MODE_SENSE: 3674 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 3675 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3676 scb->cmd.basic_io.segment_4G = 0; 3677 scb->cmd.basic_io.enhanced_sg = 0; 3678 scb->data_len = sizeof (*ha->enq); 3679 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 3680 ret = IPS_SUCCESS; 3681 break; 3682 3683 case READ_CAPACITY: 3684 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3685 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3686 scb->cmd.logical_info.reserved = 0; 3687 scb->cmd.logical_info.reserved2 = 0; 3688 scb->cmd.logical_info.reserved3 = 0; 3689 scb->data_len = sizeof (IPS_LD_INFO); 3690 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3691 scb->flags = 0; 3692 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3693 ret = IPS_SUCCESS; 3694 break; 3695 3696 case SEND_DIAGNOSTIC: 3697 case REASSIGN_BLOCKS: 3698 case FORMAT_UNIT: 3699 case SEEK_10: 3700 case VERIFY: 3701 case READ_DEFECT_DATA: 3702 case READ_BUFFER: 3703 case WRITE_BUFFER: 3704 scb->scsi_cmd->result = DID_OK << 16; 3705 break; 3706 3707 default: 3708 /* Set the Return Info to appear like the Command was */ 3709 /* attempted, a Check Condition occurred, and Sense */ 3710 /* Data indicating an Invalid CDB OpCode is returned. */ 3711 sp = (char *) scb->scsi_cmd->sense_buffer; 3712 3713 sp[0] = 0x70; /* Error Code */ 3714 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ 3715 sp[7] = 0x0A; /* Additional Sense Length */ 3716 sp[12] = 0x20; /* ASC = Invalid OpCode */ 3717 sp[13] = 0x00; /* ASCQ */ 3718 3719 device_error = 2; /* Indicate Check Condition */ 3720 scb->scsi_cmd->result = device_error | (DID_OK << 16); 3721 break; 3722 } /* end switch */ 3723 } 3724 /* end if */ 3725 if (ret == IPS_SUCCESS_IMM) 3726 return (ret); 3727 3728 /* setup DCDB */ 3729 if (scb->bus > 0) { 3730 3731 /* If we already know the Device is Not there, no need to attempt a Command */ 3732 /* This also protects an NT FailOver Controller from getting CDB's sent to it */ 3733 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) { 3734 scb->scsi_cmd->result = DID_NO_CONNECT << 16; 3735 return (IPS_SUCCESS_IMM); 3736 } 3737 3738 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id); 3739 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb); 3740 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 3741 (unsigned long) &scb-> 3742 dcdb - 3743 (unsigned long) scb); 3744 scb->cmd.dcdb.reserved = 0; 3745 scb->cmd.dcdb.reserved2 = 0; 3746 scb->cmd.dcdb.reserved3 = 0; 3747 scb->cmd.dcdb.segment_4G = 0; 3748 scb->cmd.dcdb.enhanced_sg = 0; 3749 3750 TimeOut = scb->scsi_cmd->request->timeout; 3751 3752 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */ 3753 if (!scb->sg_len) { 3754 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB; 3755 } else { 3756 scb->cmd.dcdb.op_code = 3757 IPS_CMD_EXTENDED_DCDB_SG; 3758 scb->cmd.dcdb.enhanced_sg = 3759 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3760 } 3761 3762 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */ 3763 tapeDCDB->device_address = 3764 ((scb->bus - 1) << 4) | scb->target_id; 3765 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED; 3766 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */ 3767 3768 if (TimeOut) { 3769 if (TimeOut < (10 * HZ)) 3770 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 3771 else if (TimeOut < (60 * HZ)) 3772 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 3773 else if (TimeOut < (1200 * HZ)) 3774 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 3775 } 3776 3777 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len; 3778 tapeDCDB->reserved_for_LUN = 0; 3779 tapeDCDB->transfer_length = scb->data_len; 3780 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG) 3781 tapeDCDB->buffer_pointer = 3782 cpu_to_le32(scb->sg_busaddr); 3783 else 3784 tapeDCDB->buffer_pointer = 3785 cpu_to_le32(scb->data_busaddr); 3786 tapeDCDB->sg_count = scb->sg_len; 3787 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info); 3788 tapeDCDB->scsi_status = 0; 3789 tapeDCDB->reserved = 0; 3790 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd, 3791 scb->scsi_cmd->cmd_len); 3792 } else { 3793 if (!scb->sg_len) { 3794 scb->cmd.dcdb.op_code = IPS_CMD_DCDB; 3795 } else { 3796 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG; 3797 scb->cmd.dcdb.enhanced_sg = 3798 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3799 } 3800 3801 scb->dcdb.device_address = 3802 ((scb->bus - 1) << 4) | scb->target_id; 3803 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED; 3804 3805 if (TimeOut) { 3806 if (TimeOut < (10 * HZ)) 3807 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 3808 else if (TimeOut < (60 * HZ)) 3809 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 3810 else if (TimeOut < (1200 * HZ)) 3811 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 3812 } 3813 3814 scb->dcdb.transfer_length = scb->data_len; 3815 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K) 3816 scb->dcdb.transfer_length = 0; 3817 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG) 3818 scb->dcdb.buffer_pointer = 3819 cpu_to_le32(scb->sg_busaddr); 3820 else 3821 scb->dcdb.buffer_pointer = 3822 cpu_to_le32(scb->data_busaddr); 3823 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len; 3824 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info); 3825 scb->dcdb.sg_count = scb->sg_len; 3826 scb->dcdb.reserved = 0; 3827 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd, 3828 scb->scsi_cmd->cmd_len); 3829 scb->dcdb.scsi_status = 0; 3830 scb->dcdb.reserved2[0] = 0; 3831 scb->dcdb.reserved2[1] = 0; 3832 scb->dcdb.reserved2[2] = 0; 3833 } 3834 } 3835 3836 return ((*ha->func.issue) (ha, scb)); 3837 } 3838 3839 /****************************************************************************/ 3840 /* */ 3841 /* Routine Name: ips_chk_status */ 3842 /* */ 3843 /* Routine Description: */ 3844 /* */ 3845 /* Check the status of commands to logical drives */ 3846 /* Assumed to be called with the HA lock */ 3847 /****************************************************************************/ 3848 static void 3849 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus) 3850 { 3851 ips_scb_t *scb; 3852 ips_stat_t *sp; 3853 uint8_t basic_status; 3854 uint8_t ext_status; 3855 int errcode; 3856 IPS_SCSI_INQ_DATA inquiryData; 3857 3858 METHOD_TRACE("ips_chkstatus", 1); 3859 3860 scb = &ha->scbs[pstatus->fields.command_id]; 3861 scb->basic_status = basic_status = 3862 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK; 3863 scb->extended_status = ext_status = pstatus->fields.extended_status; 3864 3865 sp = &ha->sp; 3866 sp->residue_len = 0; 3867 sp->scb_addr = (void *) scb; 3868 3869 /* Remove the item from the active queue */ 3870 ips_removeq_scb(&ha->scb_activelist, scb); 3871 3872 if (!scb->scsi_cmd) 3873 /* internal commands are handled in do_ipsintr */ 3874 return; 3875 3876 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)", 3877 ips_name, 3878 ha->host_num, 3879 scb->cdb[0], 3880 scb->cmd.basic_io.command_id, 3881 scb->bus, scb->target_id, scb->lun); 3882 3883 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) 3884 /* passthru - just returns the raw result */ 3885 return; 3886 3887 errcode = DID_OK; 3888 3889 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) || 3890 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) { 3891 3892 if (scb->bus == 0) { 3893 if ((basic_status & IPS_GSC_STATUS_MASK) == 3894 IPS_CMD_RECOVERED_ERROR) { 3895 DEBUG_VAR(1, 3896 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 3897 ips_name, ha->host_num, 3898 scb->cmd.basic_io.op_code, 3899 basic_status, ext_status); 3900 } 3901 3902 switch (scb->scsi_cmd->cmnd[0]) { 3903 case ALLOW_MEDIUM_REMOVAL: 3904 case REZERO_UNIT: 3905 case ERASE: 3906 case WRITE_FILEMARKS: 3907 case SPACE: 3908 errcode = DID_ERROR; 3909 break; 3910 3911 case START_STOP: 3912 break; 3913 3914 case TEST_UNIT_READY: 3915 if (!ips_online(ha, scb)) { 3916 errcode = DID_TIME_OUT; 3917 } 3918 break; 3919 3920 case INQUIRY: 3921 if (ips_online(ha, scb)) { 3922 ips_inquiry(ha, scb); 3923 } else { 3924 errcode = DID_TIME_OUT; 3925 } 3926 break; 3927 3928 case REQUEST_SENSE: 3929 ips_reqsen(ha, scb); 3930 break; 3931 3932 case READ_6: 3933 case WRITE_6: 3934 case READ_10: 3935 case WRITE_10: 3936 case RESERVE: 3937 case RELEASE: 3938 break; 3939 3940 case MODE_SENSE: 3941 if (!ips_online(ha, scb) 3942 || !ips_msense(ha, scb)) { 3943 errcode = DID_ERROR; 3944 } 3945 break; 3946 3947 case READ_CAPACITY: 3948 if (ips_online(ha, scb)) 3949 ips_rdcap(ha, scb); 3950 else { 3951 errcode = DID_TIME_OUT; 3952 } 3953 break; 3954 3955 case SEND_DIAGNOSTIC: 3956 case REASSIGN_BLOCKS: 3957 break; 3958 3959 case FORMAT_UNIT: 3960 errcode = DID_ERROR; 3961 break; 3962 3963 case SEEK_10: 3964 case VERIFY: 3965 case READ_DEFECT_DATA: 3966 case READ_BUFFER: 3967 case WRITE_BUFFER: 3968 break; 3969 3970 default: 3971 errcode = DID_ERROR; 3972 } /* end switch */ 3973 3974 scb->scsi_cmd->result = errcode << 16; 3975 } else { /* bus == 0 */ 3976 /* restrict access to physical drives */ 3977 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3978 ips_scmd_buf_read(scb->scsi_cmd, 3979 &inquiryData, sizeof (inquiryData)); 3980 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) 3981 scb->scsi_cmd->result = DID_TIME_OUT << 16; 3982 } 3983 } /* else */ 3984 } else { /* recovered error / success */ 3985 if (scb->bus == 0) { 3986 DEBUG_VAR(1, 3987 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 3988 ips_name, ha->host_num, 3989 scb->cmd.basic_io.op_code, basic_status, 3990 ext_status); 3991 } 3992 3993 ips_map_status(ha, scb, sp); 3994 } /* else */ 3995 } 3996 3997 /****************************************************************************/ 3998 /* */ 3999 /* Routine Name: ips_online */ 4000 /* */ 4001 /* Routine Description: */ 4002 /* */ 4003 /* Determine if a logical drive is online */ 4004 /* */ 4005 /****************************************************************************/ 4006 static int 4007 ips_online(ips_ha_t * ha, ips_scb_t * scb) 4008 { 4009 METHOD_TRACE("ips_online", 1); 4010 4011 if (scb->target_id >= IPS_MAX_LD) 4012 return (0); 4013 4014 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) { 4015 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO)); 4016 return (0); 4017 } 4018 4019 if (ha->logical_drive_info->drive_info[scb->target_id].state != 4020 IPS_LD_OFFLINE 4021 && ha->logical_drive_info->drive_info[scb->target_id].state != 4022 IPS_LD_FREE 4023 && ha->logical_drive_info->drive_info[scb->target_id].state != 4024 IPS_LD_CRS 4025 && ha->logical_drive_info->drive_info[scb->target_id].state != 4026 IPS_LD_SYS) 4027 return (1); 4028 else 4029 return (0); 4030 } 4031 4032 /****************************************************************************/ 4033 /* */ 4034 /* Routine Name: ips_inquiry */ 4035 /* */ 4036 /* Routine Description: */ 4037 /* */ 4038 /* Simulate an inquiry command to a logical drive */ 4039 /* */ 4040 /****************************************************************************/ 4041 static int 4042 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb) 4043 { 4044 IPS_SCSI_INQ_DATA inquiry; 4045 4046 METHOD_TRACE("ips_inquiry", 1); 4047 4048 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA)); 4049 4050 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD; 4051 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED; 4052 inquiry.Version = IPS_SCSI_INQ_REV2; 4053 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2; 4054 inquiry.AdditionalLength = 31; 4055 inquiry.Flags[0] = IPS_SCSI_INQ_Address16; 4056 inquiry.Flags[1] = 4057 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue; 4058 strncpy(inquiry.VendorId, "IBM ", 8); 4059 strncpy(inquiry.ProductId, "SERVERAID ", 16); 4060 strncpy(inquiry.ProductRevisionLevel, "1.00", 4); 4061 4062 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry)); 4063 4064 return (1); 4065 } 4066 4067 /****************************************************************************/ 4068 /* */ 4069 /* Routine Name: ips_rdcap */ 4070 /* */ 4071 /* Routine Description: */ 4072 /* */ 4073 /* Simulate a read capacity command to a logical drive */ 4074 /* */ 4075 /****************************************************************************/ 4076 static int 4077 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb) 4078 { 4079 IPS_SCSI_CAPACITY cap; 4080 4081 METHOD_TRACE("ips_rdcap", 1); 4082 4083 if (scsi_bufflen(scb->scsi_cmd) < 8) 4084 return (0); 4085 4086 cap.lba = 4087 cpu_to_be32(le32_to_cpu 4088 (ha->logical_drive_info-> 4089 drive_info[scb->target_id].sector_count) - 1); 4090 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); 4091 4092 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap)); 4093 4094 return (1); 4095 } 4096 4097 /****************************************************************************/ 4098 /* */ 4099 /* Routine Name: ips_msense */ 4100 /* */ 4101 /* Routine Description: */ 4102 /* */ 4103 /* Simulate a mode sense command to a logical drive */ 4104 /* */ 4105 /****************************************************************************/ 4106 static int 4107 ips_msense(ips_ha_t * ha, ips_scb_t * scb) 4108 { 4109 uint16_t heads; 4110 uint16_t sectors; 4111 uint32_t cylinders; 4112 IPS_SCSI_MODE_PAGE_DATA mdata; 4113 4114 METHOD_TRACE("ips_msense", 1); 4115 4116 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 && 4117 (ha->enq->ucMiscFlag & 0x8) == 0) { 4118 heads = IPS_NORM_HEADS; 4119 sectors = IPS_NORM_SECTORS; 4120 } else { 4121 heads = IPS_COMP_HEADS; 4122 sectors = IPS_COMP_SECTORS; 4123 } 4124 4125 cylinders = 4126 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) - 4127 1) / (heads * sectors); 4128 4129 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA)); 4130 4131 mdata.hdr.BlockDescLength = 8; 4132 4133 switch (scb->scsi_cmd->cmnd[2] & 0x3f) { 4134 case 0x03: /* page 3 */ 4135 mdata.pdata.pg3.PageCode = 3; 4136 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3); 4137 mdata.hdr.DataLength = 4138 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength; 4139 mdata.pdata.pg3.TracksPerZone = 0; 4140 mdata.pdata.pg3.AltSectorsPerZone = 0; 4141 mdata.pdata.pg3.AltTracksPerZone = 0; 4142 mdata.pdata.pg3.AltTracksPerVolume = 0; 4143 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors); 4144 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE); 4145 mdata.pdata.pg3.Interleave = cpu_to_be16(1); 4146 mdata.pdata.pg3.TrackSkew = 0; 4147 mdata.pdata.pg3.CylinderSkew = 0; 4148 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector; 4149 break; 4150 4151 case 0x4: 4152 mdata.pdata.pg4.PageCode = 4; 4153 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4); 4154 mdata.hdr.DataLength = 4155 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength; 4156 mdata.pdata.pg4.CylindersHigh = 4157 cpu_to_be16((cylinders >> 8) & 0xFFFF); 4158 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF); 4159 mdata.pdata.pg4.Heads = heads; 4160 mdata.pdata.pg4.WritePrecompHigh = 0; 4161 mdata.pdata.pg4.WritePrecompLow = 0; 4162 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0; 4163 mdata.pdata.pg4.ReducedWriteCurrentLow = 0; 4164 mdata.pdata.pg4.StepRate = cpu_to_be16(1); 4165 mdata.pdata.pg4.LandingZoneHigh = 0; 4166 mdata.pdata.pg4.LandingZoneLow = 0; 4167 mdata.pdata.pg4.flags = 0; 4168 mdata.pdata.pg4.RotationalOffset = 0; 4169 mdata.pdata.pg4.MediumRotationRate = 0; 4170 break; 4171 case 0x8: 4172 mdata.pdata.pg8.PageCode = 8; 4173 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8); 4174 mdata.hdr.DataLength = 4175 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength; 4176 /* everything else is left set to 0 */ 4177 break; 4178 4179 default: 4180 return (0); 4181 } /* end switch */ 4182 4183 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata)); 4184 4185 return (1); 4186 } 4187 4188 /****************************************************************************/ 4189 /* */ 4190 /* Routine Name: ips_reqsen */ 4191 /* */ 4192 /* Routine Description: */ 4193 /* */ 4194 /* Simulate a request sense command to a logical drive */ 4195 /* */ 4196 /****************************************************************************/ 4197 static int 4198 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb) 4199 { 4200 IPS_SCSI_REQSEN reqsen; 4201 4202 METHOD_TRACE("ips_reqsen", 1); 4203 4204 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN)); 4205 4206 reqsen.ResponseCode = 4207 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR; 4208 reqsen.AdditionalLength = 10; 4209 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE; 4210 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE; 4211 4212 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen)); 4213 4214 return (1); 4215 } 4216 4217 /****************************************************************************/ 4218 /* */ 4219 /* Routine Name: ips_free */ 4220 /* */ 4221 /* Routine Description: */ 4222 /* */ 4223 /* Free any allocated space for this controller */ 4224 /* */ 4225 /****************************************************************************/ 4226 static void 4227 ips_free(ips_ha_t * ha) 4228 { 4229 4230 METHOD_TRACE("ips_free", 1); 4231 4232 if (ha) { 4233 if (ha->enq) { 4234 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ), 4235 ha->enq, ha->enq_busaddr); 4236 ha->enq = NULL; 4237 } 4238 4239 kfree(ha->conf); 4240 ha->conf = NULL; 4241 4242 if (ha->adapt) { 4243 pci_free_consistent(ha->pcidev, 4244 sizeof (IPS_ADAPTER) + 4245 sizeof (IPS_IO_CMD), ha->adapt, 4246 ha->adapt->hw_status_start); 4247 ha->adapt = NULL; 4248 } 4249 4250 if (ha->logical_drive_info) { 4251 pci_free_consistent(ha->pcidev, 4252 sizeof (IPS_LD_INFO), 4253 ha->logical_drive_info, 4254 ha->logical_drive_info_dma_addr); 4255 ha->logical_drive_info = NULL; 4256 } 4257 4258 kfree(ha->nvram); 4259 ha->nvram = NULL; 4260 4261 kfree(ha->subsys); 4262 ha->subsys = NULL; 4263 4264 if (ha->ioctl_data) { 4265 pci_free_consistent(ha->pcidev, ha->ioctl_len, 4266 ha->ioctl_data, ha->ioctl_busaddr); 4267 ha->ioctl_data = NULL; 4268 ha->ioctl_datasize = 0; 4269 ha->ioctl_len = 0; 4270 } 4271 ips_deallocatescbs(ha, ha->max_cmds); 4272 4273 /* free memory mapped (if applicable) */ 4274 if (ha->mem_ptr) { 4275 iounmap(ha->ioremap_ptr); 4276 ha->ioremap_ptr = NULL; 4277 ha->mem_ptr = NULL; 4278 } 4279 4280 ha->mem_addr = 0; 4281 4282 } 4283 } 4284 4285 /****************************************************************************/ 4286 /* */ 4287 /* Routine Name: ips_deallocatescbs */ 4288 /* */ 4289 /* Routine Description: */ 4290 /* */ 4291 /* Free the command blocks */ 4292 /* */ 4293 /****************************************************************************/ 4294 static int 4295 ips_deallocatescbs(ips_ha_t * ha, int cmds) 4296 { 4297 if (ha->scbs) { 4298 pci_free_consistent(ha->pcidev, 4299 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds, 4300 ha->scbs->sg_list.list, 4301 ha->scbs->sg_busaddr); 4302 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds, 4303 ha->scbs, ha->scbs->scb_busaddr); 4304 ha->scbs = NULL; 4305 } /* end if */ 4306 return 1; 4307 } 4308 4309 /****************************************************************************/ 4310 /* */ 4311 /* Routine Name: ips_allocatescbs */ 4312 /* */ 4313 /* Routine Description: */ 4314 /* */ 4315 /* Allocate the command blocks */ 4316 /* */ 4317 /****************************************************************************/ 4318 static int 4319 ips_allocatescbs(ips_ha_t * ha) 4320 { 4321 ips_scb_t *scb_p; 4322 IPS_SG_LIST ips_sg; 4323 int i; 4324 dma_addr_t command_dma, sg_dma; 4325 4326 METHOD_TRACE("ips_allocatescbs", 1); 4327 4328 /* Allocate memory for the SCBs */ 4329 ha->scbs = 4330 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t), 4331 &command_dma); 4332 if (ha->scbs == NULL) 4333 return 0; 4334 ips_sg.list = 4335 pci_alloc_consistent(ha->pcidev, 4336 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * 4337 ha->max_cmds, &sg_dma); 4338 if (ips_sg.list == NULL) { 4339 pci_free_consistent(ha->pcidev, 4340 ha->max_cmds * sizeof (ips_scb_t), ha->scbs, 4341 command_dma); 4342 return 0; 4343 } 4344 4345 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t)); 4346 4347 for (i = 0; i < ha->max_cmds; i++) { 4348 scb_p = &ha->scbs[i]; 4349 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i; 4350 /* set up S/G list */ 4351 if (IPS_USE_ENH_SGLIST(ha)) { 4352 scb_p->sg_list.enh_list = 4353 ips_sg.enh_list + i * IPS_MAX_SG; 4354 scb_p->sg_busaddr = 4355 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4356 } else { 4357 scb_p->sg_list.std_list = 4358 ips_sg.std_list + i * IPS_MAX_SG; 4359 scb_p->sg_busaddr = 4360 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4361 } 4362 4363 /* add to the free list */ 4364 if (i < ha->max_cmds - 1) { 4365 scb_p->q_next = ha->scb_freelist; 4366 ha->scb_freelist = scb_p; 4367 } 4368 } 4369 4370 /* success */ 4371 return (1); 4372 } 4373 4374 /****************************************************************************/ 4375 /* */ 4376 /* Routine Name: ips_init_scb */ 4377 /* */ 4378 /* Routine Description: */ 4379 /* */ 4380 /* Initialize a CCB to default values */ 4381 /* */ 4382 /****************************************************************************/ 4383 static void 4384 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb) 4385 { 4386 IPS_SG_LIST sg_list; 4387 uint32_t cmd_busaddr, sg_busaddr; 4388 METHOD_TRACE("ips_init_scb", 1); 4389 4390 if (scb == NULL) 4391 return; 4392 4393 sg_list.list = scb->sg_list.list; 4394 cmd_busaddr = scb->scb_busaddr; 4395 sg_busaddr = scb->sg_busaddr; 4396 /* zero fill */ 4397 memset(scb, 0, sizeof (ips_scb_t)); 4398 memset(ha->dummy, 0, sizeof (IPS_IO_CMD)); 4399 4400 /* Initialize dummy command bucket */ 4401 ha->dummy->op_code = 0xFF; 4402 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start 4403 + sizeof (IPS_ADAPTER)); 4404 ha->dummy->command_id = IPS_MAX_CMDS; 4405 4406 /* set bus address of scb */ 4407 scb->scb_busaddr = cmd_busaddr; 4408 scb->sg_busaddr = sg_busaddr; 4409 scb->sg_list.list = sg_list.list; 4410 4411 /* Neptune Fix */ 4412 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); 4413 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start 4414 + sizeof (IPS_ADAPTER)); 4415 } 4416 4417 /****************************************************************************/ 4418 /* */ 4419 /* Routine Name: ips_get_scb */ 4420 /* */ 4421 /* Routine Description: */ 4422 /* */ 4423 /* Initialize a CCB to default values */ 4424 /* */ 4425 /* ASSUMED to be called from within a lock */ 4426 /* */ 4427 /****************************************************************************/ 4428 static ips_scb_t * 4429 ips_getscb(ips_ha_t * ha) 4430 { 4431 ips_scb_t *scb; 4432 4433 METHOD_TRACE("ips_getscb", 1); 4434 4435 if ((scb = ha->scb_freelist) == NULL) { 4436 4437 return (NULL); 4438 } 4439 4440 ha->scb_freelist = scb->q_next; 4441 scb->flags = 0; 4442 scb->q_next = NULL; 4443 4444 ips_init_scb(ha, scb); 4445 4446 return (scb); 4447 } 4448 4449 /****************************************************************************/ 4450 /* */ 4451 /* Routine Name: ips_free_scb */ 4452 /* */ 4453 /* Routine Description: */ 4454 /* */ 4455 /* Return an unused CCB back to the free list */ 4456 /* */ 4457 /* ASSUMED to be called from within a lock */ 4458 /* */ 4459 /****************************************************************************/ 4460 static void 4461 ips_freescb(ips_ha_t * ha, ips_scb_t * scb) 4462 { 4463 4464 METHOD_TRACE("ips_freescb", 1); 4465 if (scb->flags & IPS_SCB_MAP_SG) 4466 scsi_dma_unmap(scb->scsi_cmd); 4467 else if (scb->flags & IPS_SCB_MAP_SINGLE) 4468 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len, 4469 IPS_DMA_DIR(scb)); 4470 4471 /* check to make sure this is not our "special" scb */ 4472 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) { 4473 scb->q_next = ha->scb_freelist; 4474 ha->scb_freelist = scb; 4475 } 4476 } 4477 4478 /****************************************************************************/ 4479 /* */ 4480 /* Routine Name: ips_isinit_copperhead */ 4481 /* */ 4482 /* Routine Description: */ 4483 /* */ 4484 /* Is controller initialized ? */ 4485 /* */ 4486 /****************************************************************************/ 4487 static int 4488 ips_isinit_copperhead(ips_ha_t * ha) 4489 { 4490 uint8_t scpr; 4491 uint8_t isr; 4492 4493 METHOD_TRACE("ips_isinit_copperhead", 1); 4494 4495 isr = inb(ha->io_addr + IPS_REG_HISR); 4496 scpr = inb(ha->io_addr + IPS_REG_SCPR); 4497 4498 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4499 return (0); 4500 else 4501 return (1); 4502 } 4503 4504 /****************************************************************************/ 4505 /* */ 4506 /* Routine Name: ips_isinit_copperhead_memio */ 4507 /* */ 4508 /* Routine Description: */ 4509 /* */ 4510 /* Is controller initialized ? */ 4511 /* */ 4512 /****************************************************************************/ 4513 static int 4514 ips_isinit_copperhead_memio(ips_ha_t * ha) 4515 { 4516 uint8_t isr = 0; 4517 uint8_t scpr; 4518 4519 METHOD_TRACE("ips_is_init_copperhead_memio", 1); 4520 4521 isr = readb(ha->mem_ptr + IPS_REG_HISR); 4522 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); 4523 4524 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4525 return (0); 4526 else 4527 return (1); 4528 } 4529 4530 /****************************************************************************/ 4531 /* */ 4532 /* Routine Name: ips_isinit_morpheus */ 4533 /* */ 4534 /* Routine Description: */ 4535 /* */ 4536 /* Is controller initialized ? */ 4537 /* */ 4538 /****************************************************************************/ 4539 static int 4540 ips_isinit_morpheus(ips_ha_t * ha) 4541 { 4542 uint32_t post; 4543 uint32_t bits; 4544 4545 METHOD_TRACE("ips_is_init_morpheus", 1); 4546 4547 if (ips_isintr_morpheus(ha)) 4548 ips_flush_and_reset(ha); 4549 4550 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4551 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4552 4553 if (post == 0) 4554 return (0); 4555 else if (bits & 0x3) 4556 return (0); 4557 else 4558 return (1); 4559 } 4560 4561 /****************************************************************************/ 4562 /* */ 4563 /* Routine Name: ips_flush_and_reset */ 4564 /* */ 4565 /* Routine Description: */ 4566 /* */ 4567 /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */ 4568 /* state ( was trying to INIT and an interrupt was already pending ) ... */ 4569 /* */ 4570 /****************************************************************************/ 4571 static void 4572 ips_flush_and_reset(ips_ha_t *ha) 4573 { 4574 ips_scb_t *scb; 4575 int ret; 4576 int time; 4577 int done; 4578 dma_addr_t command_dma; 4579 4580 /* Create a usuable SCB */ 4581 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma); 4582 if (scb) { 4583 memset(scb, 0, sizeof(ips_scb_t)); 4584 ips_init_scb(ha, scb); 4585 scb->scb_busaddr = command_dma; 4586 4587 scb->timeout = ips_cmd_timeout; 4588 scb->cdb[0] = IPS_CMD_FLUSH; 4589 4590 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 4591 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */ 4592 scb->cmd.flush_cache.state = IPS_NORM_STATE; 4593 scb->cmd.flush_cache.reserved = 0; 4594 scb->cmd.flush_cache.reserved2 = 0; 4595 scb->cmd.flush_cache.reserved3 = 0; 4596 scb->cmd.flush_cache.reserved4 = 0; 4597 4598 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */ 4599 4600 if (ret == IPS_SUCCESS) { 4601 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ 4602 done = 0; 4603 4604 while ((time > 0) && (!done)) { 4605 done = ips_poll_for_flush_complete(ha); 4606 /* This may look evil, but it's only done during extremely rare start-up conditions ! */ 4607 udelay(1000); 4608 time--; 4609 } 4610 } 4611 } 4612 4613 /* Now RESET and INIT the adapter */ 4614 (*ha->func.reset) (ha); 4615 4616 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma); 4617 return; 4618 } 4619 4620 /****************************************************************************/ 4621 /* */ 4622 /* Routine Name: ips_poll_for_flush_complete */ 4623 /* */ 4624 /* Routine Description: */ 4625 /* */ 4626 /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */ 4627 /* All other responses are just taken off the queue and ignored */ 4628 /* */ 4629 /****************************************************************************/ 4630 static int 4631 ips_poll_for_flush_complete(ips_ha_t * ha) 4632 { 4633 IPS_STATUS cstatus; 4634 4635 while (TRUE) { 4636 cstatus.value = (*ha->func.statupd) (ha); 4637 4638 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ 4639 break; 4640 4641 /* Success is when we see the Flush Command ID */ 4642 if (cstatus.fields.command_id == IPS_MAX_CMDS) 4643 return 1; 4644 } 4645 4646 return 0; 4647 } 4648 4649 /****************************************************************************/ 4650 /* */ 4651 /* Routine Name: ips_enable_int_copperhead */ 4652 /* */ 4653 /* Routine Description: */ 4654 /* Turn on interrupts */ 4655 /* */ 4656 /****************************************************************************/ 4657 static void 4658 ips_enable_int_copperhead(ips_ha_t * ha) 4659 { 4660 METHOD_TRACE("ips_enable_int_copperhead", 1); 4661 4662 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI); 4663 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4664 } 4665 4666 /****************************************************************************/ 4667 /* */ 4668 /* Routine Name: ips_enable_int_copperhead_memio */ 4669 /* */ 4670 /* Routine Description: */ 4671 /* Turn on interrupts */ 4672 /* */ 4673 /****************************************************************************/ 4674 static void 4675 ips_enable_int_copperhead_memio(ips_ha_t * ha) 4676 { 4677 METHOD_TRACE("ips_enable_int_copperhead_memio", 1); 4678 4679 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4680 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4681 } 4682 4683 /****************************************************************************/ 4684 /* */ 4685 /* Routine Name: ips_enable_int_morpheus */ 4686 /* */ 4687 /* Routine Description: */ 4688 /* Turn on interrupts */ 4689 /* */ 4690 /****************************************************************************/ 4691 static void 4692 ips_enable_int_morpheus(ips_ha_t * ha) 4693 { 4694 uint32_t Oimr; 4695 4696 METHOD_TRACE("ips_enable_int_morpheus", 1); 4697 4698 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4699 Oimr &= ~0x08; 4700 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4701 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ 4702 } 4703 4704 /****************************************************************************/ 4705 /* */ 4706 /* Routine Name: ips_init_copperhead */ 4707 /* */ 4708 /* Routine Description: */ 4709 /* */ 4710 /* Initialize a copperhead controller */ 4711 /* */ 4712 /****************************************************************************/ 4713 static int 4714 ips_init_copperhead(ips_ha_t * ha) 4715 { 4716 uint8_t Isr; 4717 uint8_t Cbsp; 4718 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4719 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; 4720 int i, j; 4721 4722 METHOD_TRACE("ips_init_copperhead", 1); 4723 4724 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4725 for (j = 0; j < 45; j++) { 4726 Isr = inb(ha->io_addr + IPS_REG_HISR); 4727 if (Isr & IPS_BIT_GHI) 4728 break; 4729 4730 /* Delay for 1 Second */ 4731 MDELAY(IPS_ONE_SEC); 4732 } 4733 4734 if (j >= 45) 4735 /* error occurred */ 4736 return (0); 4737 4738 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 4739 outb(Isr, ha->io_addr + IPS_REG_HISR); 4740 } 4741 4742 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 4743 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4744 "reset controller fails (post status %x %x).\n", 4745 PostByte[0], PostByte[1]); 4746 4747 return (0); 4748 } 4749 4750 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 4751 for (j = 0; j < 240; j++) { 4752 Isr = inb(ha->io_addr + IPS_REG_HISR); 4753 if (Isr & IPS_BIT_GHI) 4754 break; 4755 4756 /* Delay for 1 Second */ 4757 MDELAY(IPS_ONE_SEC); 4758 } 4759 4760 if (j >= 240) 4761 /* error occurred */ 4762 return (0); 4763 4764 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 4765 outb(Isr, ha->io_addr + IPS_REG_HISR); 4766 } 4767 4768 for (i = 0; i < 240; i++) { 4769 Cbsp = inb(ha->io_addr + IPS_REG_CBSP); 4770 4771 if ((Cbsp & IPS_BIT_OP) == 0) 4772 break; 4773 4774 /* Delay for 1 Second */ 4775 MDELAY(IPS_ONE_SEC); 4776 } 4777 4778 if (i >= 240) 4779 /* reset failed */ 4780 return (0); 4781 4782 /* setup CCCR */ 4783 outl(0x1010, ha->io_addr + IPS_REG_CCCR); 4784 4785 /* Enable busmastering */ 4786 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); 4787 4788 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 4789 /* fix for anaconda64 */ 4790 outl(0, ha->io_addr + IPS_REG_NDAE); 4791 4792 /* Enable interrupts */ 4793 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR); 4794 4795 return (1); 4796 } 4797 4798 /****************************************************************************/ 4799 /* */ 4800 /* Routine Name: ips_init_copperhead_memio */ 4801 /* */ 4802 /* Routine Description: */ 4803 /* */ 4804 /* Initialize a copperhead controller with memory mapped I/O */ 4805 /* */ 4806 /****************************************************************************/ 4807 static int 4808 ips_init_copperhead_memio(ips_ha_t * ha) 4809 { 4810 uint8_t Isr = 0; 4811 uint8_t Cbsp; 4812 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4813 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; 4814 int i, j; 4815 4816 METHOD_TRACE("ips_init_copperhead_memio", 1); 4817 4818 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4819 for (j = 0; j < 45; j++) { 4820 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 4821 if (Isr & IPS_BIT_GHI) 4822 break; 4823 4824 /* Delay for 1 Second */ 4825 MDELAY(IPS_ONE_SEC); 4826 } 4827 4828 if (j >= 45) 4829 /* error occurred */ 4830 return (0); 4831 4832 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 4833 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 4834 } 4835 4836 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 4837 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4838 "reset controller fails (post status %x %x).\n", 4839 PostByte[0], PostByte[1]); 4840 4841 return (0); 4842 } 4843 4844 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 4845 for (j = 0; j < 240; j++) { 4846 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 4847 if (Isr & IPS_BIT_GHI) 4848 break; 4849 4850 /* Delay for 1 Second */ 4851 MDELAY(IPS_ONE_SEC); 4852 } 4853 4854 if (j >= 240) 4855 /* error occurred */ 4856 return (0); 4857 4858 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 4859 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 4860 } 4861 4862 for (i = 0; i < 240; i++) { 4863 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); 4864 4865 if ((Cbsp & IPS_BIT_OP) == 0) 4866 break; 4867 4868 /* Delay for 1 Second */ 4869 MDELAY(IPS_ONE_SEC); 4870 } 4871 4872 if (i >= 240) 4873 /* error occurred */ 4874 return (0); 4875 4876 /* setup CCCR */ 4877 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); 4878 4879 /* Enable busmastering */ 4880 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); 4881 4882 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 4883 /* fix for anaconda64 */ 4884 writel(0, ha->mem_ptr + IPS_REG_NDAE); 4885 4886 /* Enable interrupts */ 4887 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4888 4889 /* if we get here then everything went OK */ 4890 return (1); 4891 } 4892 4893 /****************************************************************************/ 4894 /* */ 4895 /* Routine Name: ips_init_morpheus */ 4896 /* */ 4897 /* Routine Description: */ 4898 /* */ 4899 /* Initialize a morpheus controller */ 4900 /* */ 4901 /****************************************************************************/ 4902 static int 4903 ips_init_morpheus(ips_ha_t * ha) 4904 { 4905 uint32_t Post; 4906 uint32_t Config; 4907 uint32_t Isr; 4908 uint32_t Oimr; 4909 int i; 4910 4911 METHOD_TRACE("ips_init_morpheus", 1); 4912 4913 /* Wait up to 45 secs for Post */ 4914 for (i = 0; i < 45; i++) { 4915 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4916 4917 if (Isr & IPS_BIT_I960_MSG0I) 4918 break; 4919 4920 /* Delay for 1 Second */ 4921 MDELAY(IPS_ONE_SEC); 4922 } 4923 4924 if (i >= 45) { 4925 /* error occurred */ 4926 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4927 "timeout waiting for post.\n"); 4928 4929 return (0); 4930 } 4931 4932 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4933 4934 if (Post == 0x4F00) { /* If Flashing the Battery PIC */ 4935 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4936 "Flashing Battery PIC, Please wait ...\n"); 4937 4938 /* Clear the interrupt bit */ 4939 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 4940 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4941 4942 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */ 4943 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4944 if (Post != 0x4F00) 4945 break; 4946 /* Delay for 1 Second */ 4947 MDELAY(IPS_ONE_SEC); 4948 } 4949 4950 if (i >= 120) { 4951 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4952 "timeout waiting for Battery PIC Flash\n"); 4953 return (0); 4954 } 4955 4956 } 4957 4958 /* Clear the interrupt bit */ 4959 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 4960 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4961 4962 if (Post < (IPS_GOOD_POST_STATUS << 8)) { 4963 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4964 "reset controller fails (post status %x).\n", Post); 4965 4966 return (0); 4967 } 4968 4969 /* Wait up to 240 secs for config bytes */ 4970 for (i = 0; i < 240; i++) { 4971 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4972 4973 if (Isr & IPS_BIT_I960_MSG1I) 4974 break; 4975 4976 /* Delay for 1 Second */ 4977 MDELAY(IPS_ONE_SEC); 4978 } 4979 4980 if (i >= 240) { 4981 /* error occurred */ 4982 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4983 "timeout waiting for config.\n"); 4984 4985 return (0); 4986 } 4987 4988 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 4989 4990 /* Clear interrupt bit */ 4991 Isr = (uint32_t) IPS_BIT_I960_MSG1I; 4992 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4993 4994 /* Turn on the interrupts */ 4995 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4996 Oimr &= ~0x8; 4997 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4998 4999 /* if we get here then everything went OK */ 5000 5001 /* Since we did a RESET, an EraseStripeLock may be needed */ 5002 if (Post == 0xEF10) { 5003 if ((Config == 0x000F) || (Config == 0x0009)) 5004 ha->requires_esl = 1; 5005 } 5006 5007 return (1); 5008 } 5009 5010 /****************************************************************************/ 5011 /* */ 5012 /* Routine Name: ips_reset_copperhead */ 5013 /* */ 5014 /* Routine Description: */ 5015 /* */ 5016 /* Reset the controller */ 5017 /* */ 5018 /****************************************************************************/ 5019 static int 5020 ips_reset_copperhead(ips_ha_t * ha) 5021 { 5022 int reset_counter; 5023 5024 METHOD_TRACE("ips_reset_copperhead", 1); 5025 5026 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", 5027 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq); 5028 5029 reset_counter = 0; 5030 5031 while (reset_counter < 2) { 5032 reset_counter++; 5033 5034 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR); 5035 5036 /* Delay for 1 Second */ 5037 MDELAY(IPS_ONE_SEC); 5038 5039 outb(0, ha->io_addr + IPS_REG_SCPR); 5040 5041 /* Delay for 1 Second */ 5042 MDELAY(IPS_ONE_SEC); 5043 5044 if ((*ha->func.init) (ha)) 5045 break; 5046 else if (reset_counter >= 2) { 5047 5048 return (0); 5049 } 5050 } 5051 5052 return (1); 5053 } 5054 5055 /****************************************************************************/ 5056 /* */ 5057 /* Routine Name: ips_reset_copperhead_memio */ 5058 /* */ 5059 /* Routine Description: */ 5060 /* */ 5061 /* Reset the controller */ 5062 /* */ 5063 /****************************************************************************/ 5064 static int 5065 ips_reset_copperhead_memio(ips_ha_t * ha) 5066 { 5067 int reset_counter; 5068 5069 METHOD_TRACE("ips_reset_copperhead_memio", 1); 5070 5071 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", 5072 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); 5073 5074 reset_counter = 0; 5075 5076 while (reset_counter < 2) { 5077 reset_counter++; 5078 5079 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); 5080 5081 /* Delay for 1 Second */ 5082 MDELAY(IPS_ONE_SEC); 5083 5084 writeb(0, ha->mem_ptr + IPS_REG_SCPR); 5085 5086 /* Delay for 1 Second */ 5087 MDELAY(IPS_ONE_SEC); 5088 5089 if ((*ha->func.init) (ha)) 5090 break; 5091 else if (reset_counter >= 2) { 5092 5093 return (0); 5094 } 5095 } 5096 5097 return (1); 5098 } 5099 5100 /****************************************************************************/ 5101 /* */ 5102 /* Routine Name: ips_reset_morpheus */ 5103 /* */ 5104 /* Routine Description: */ 5105 /* */ 5106 /* Reset the controller */ 5107 /* */ 5108 /****************************************************************************/ 5109 static int 5110 ips_reset_morpheus(ips_ha_t * ha) 5111 { 5112 int reset_counter; 5113 uint8_t junk; 5114 5115 METHOD_TRACE("ips_reset_morpheus", 1); 5116 5117 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", 5118 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); 5119 5120 reset_counter = 0; 5121 5122 while (reset_counter < 2) { 5123 reset_counter++; 5124 5125 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); 5126 5127 /* Delay for 5 Seconds */ 5128 MDELAY(5 * IPS_ONE_SEC); 5129 5130 /* Do a PCI config read to wait for adapter */ 5131 pci_read_config_byte(ha->pcidev, 4, &junk); 5132 5133 if ((*ha->func.init) (ha)) 5134 break; 5135 else if (reset_counter >= 2) { 5136 5137 return (0); 5138 } 5139 } 5140 5141 return (1); 5142 } 5143 5144 /****************************************************************************/ 5145 /* */ 5146 /* Routine Name: ips_statinit */ 5147 /* */ 5148 /* Routine Description: */ 5149 /* */ 5150 /* Initialize the status queues on the controller */ 5151 /* */ 5152 /****************************************************************************/ 5153 static void 5154 ips_statinit(ips_ha_t * ha) 5155 { 5156 uint32_t phys_status_start; 5157 5158 METHOD_TRACE("ips_statinit", 1); 5159 5160 ha->adapt->p_status_start = ha->adapt->status; 5161 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5162 ha->adapt->p_status_tail = ha->adapt->status; 5163 5164 phys_status_start = ha->adapt->hw_status_start; 5165 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR); 5166 outl(phys_status_start + IPS_STATUS_Q_SIZE, 5167 ha->io_addr + IPS_REG_SQER); 5168 outl(phys_status_start + IPS_STATUS_SIZE, 5169 ha->io_addr + IPS_REG_SQHR); 5170 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR); 5171 5172 ha->adapt->hw_status_tail = phys_status_start; 5173 } 5174 5175 /****************************************************************************/ 5176 /* */ 5177 /* Routine Name: ips_statinit_memio */ 5178 /* */ 5179 /* Routine Description: */ 5180 /* */ 5181 /* Initialize the status queues on the controller */ 5182 /* */ 5183 /****************************************************************************/ 5184 static void 5185 ips_statinit_memio(ips_ha_t * ha) 5186 { 5187 uint32_t phys_status_start; 5188 5189 METHOD_TRACE("ips_statinit_memio", 1); 5190 5191 ha->adapt->p_status_start = ha->adapt->status; 5192 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5193 ha->adapt->p_status_tail = ha->adapt->status; 5194 5195 phys_status_start = ha->adapt->hw_status_start; 5196 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); 5197 writel(phys_status_start + IPS_STATUS_Q_SIZE, 5198 ha->mem_ptr + IPS_REG_SQER); 5199 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); 5200 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); 5201 5202 ha->adapt->hw_status_tail = phys_status_start; 5203 } 5204 5205 /****************************************************************************/ 5206 /* */ 5207 /* Routine Name: ips_statupd_copperhead */ 5208 /* */ 5209 /* Routine Description: */ 5210 /* */ 5211 /* Remove an element from the status queue */ 5212 /* */ 5213 /****************************************************************************/ 5214 static uint32_t 5215 ips_statupd_copperhead(ips_ha_t * ha) 5216 { 5217 METHOD_TRACE("ips_statupd_copperhead", 1); 5218 5219 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5220 ha->adapt->p_status_tail++; 5221 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5222 } else { 5223 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5224 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5225 } 5226 5227 outl(ha->adapt->hw_status_tail, 5228 ha->io_addr + IPS_REG_SQTR); 5229 5230 return (ha->adapt->p_status_tail->value); 5231 } 5232 5233 /****************************************************************************/ 5234 /* */ 5235 /* Routine Name: ips_statupd_copperhead_memio */ 5236 /* */ 5237 /* Routine Description: */ 5238 /* */ 5239 /* Remove an element from the status queue */ 5240 /* */ 5241 /****************************************************************************/ 5242 static uint32_t 5243 ips_statupd_copperhead_memio(ips_ha_t * ha) 5244 { 5245 METHOD_TRACE("ips_statupd_copperhead_memio", 1); 5246 5247 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5248 ha->adapt->p_status_tail++; 5249 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5250 } else { 5251 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5252 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5253 } 5254 5255 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); 5256 5257 return (ha->adapt->p_status_tail->value); 5258 } 5259 5260 /****************************************************************************/ 5261 /* */ 5262 /* Routine Name: ips_statupd_morpheus */ 5263 /* */ 5264 /* Routine Description: */ 5265 /* */ 5266 /* Remove an element from the status queue */ 5267 /* */ 5268 /****************************************************************************/ 5269 static uint32_t 5270 ips_statupd_morpheus(ips_ha_t * ha) 5271 { 5272 uint32_t val; 5273 5274 METHOD_TRACE("ips_statupd_morpheus", 1); 5275 5276 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); 5277 5278 return (val); 5279 } 5280 5281 /****************************************************************************/ 5282 /* */ 5283 /* Routine Name: ips_issue_copperhead */ 5284 /* */ 5285 /* Routine Description: */ 5286 /* */ 5287 /* Send a command down to the controller */ 5288 /* */ 5289 /****************************************************************************/ 5290 static int 5291 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb) 5292 { 5293 uint32_t TimeOut; 5294 uint32_t val; 5295 5296 METHOD_TRACE("ips_issue_copperhead", 1); 5297 5298 if (scb->scsi_cmd) { 5299 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5300 ips_name, 5301 ha->host_num, 5302 scb->cdb[0], 5303 scb->cmd.basic_io.command_id, 5304 scb->bus, scb->target_id, scb->lun); 5305 } else { 5306 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d", 5307 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5308 } 5309 5310 TimeOut = 0; 5311 5312 while ((val = 5313 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) { 5314 udelay(1000); 5315 5316 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5317 if (!(val & IPS_BIT_START_STOP)) 5318 break; 5319 5320 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5321 "ips_issue val [0x%x].\n", val); 5322 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5323 "ips_issue semaphore chk timeout.\n"); 5324 5325 return (IPS_FAILURE); 5326 } /* end if */ 5327 } /* end while */ 5328 5329 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR); 5330 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR); 5331 5332 return (IPS_SUCCESS); 5333 } 5334 5335 /****************************************************************************/ 5336 /* */ 5337 /* Routine Name: ips_issue_copperhead_memio */ 5338 /* */ 5339 /* Routine Description: */ 5340 /* */ 5341 /* Send a command down to the controller */ 5342 /* */ 5343 /****************************************************************************/ 5344 static int 5345 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb) 5346 { 5347 uint32_t TimeOut; 5348 uint32_t val; 5349 5350 METHOD_TRACE("ips_issue_copperhead_memio", 1); 5351 5352 if (scb->scsi_cmd) { 5353 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5354 ips_name, 5355 ha->host_num, 5356 scb->cdb[0], 5357 scb->cmd.basic_io.command_id, 5358 scb->bus, scb->target_id, scb->lun); 5359 } else { 5360 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5361 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5362 } 5363 5364 TimeOut = 0; 5365 5366 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { 5367 udelay(1000); 5368 5369 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5370 if (!(val & IPS_BIT_START_STOP)) 5371 break; 5372 5373 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5374 "ips_issue val [0x%x].\n", val); 5375 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5376 "ips_issue semaphore chk timeout.\n"); 5377 5378 return (IPS_FAILURE); 5379 } /* end if */ 5380 } /* end while */ 5381 5382 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); 5383 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); 5384 5385 return (IPS_SUCCESS); 5386 } 5387 5388 /****************************************************************************/ 5389 /* */ 5390 /* Routine Name: ips_issue_i2o */ 5391 /* */ 5392 /* Routine Description: */ 5393 /* */ 5394 /* Send a command down to the controller */ 5395 /* */ 5396 /****************************************************************************/ 5397 static int 5398 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb) 5399 { 5400 5401 METHOD_TRACE("ips_issue_i2o", 1); 5402 5403 if (scb->scsi_cmd) { 5404 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5405 ips_name, 5406 ha->host_num, 5407 scb->cdb[0], 5408 scb->cmd.basic_io.command_id, 5409 scb->bus, scb->target_id, scb->lun); 5410 } else { 5411 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5412 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5413 } 5414 5415 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ); 5416 5417 return (IPS_SUCCESS); 5418 } 5419 5420 /****************************************************************************/ 5421 /* */ 5422 /* Routine Name: ips_issue_i2o_memio */ 5423 /* */ 5424 /* Routine Description: */ 5425 /* */ 5426 /* Send a command down to the controller */ 5427 /* */ 5428 /****************************************************************************/ 5429 static int 5430 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb) 5431 { 5432 5433 METHOD_TRACE("ips_issue_i2o_memio", 1); 5434 5435 if (scb->scsi_cmd) { 5436 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5437 ips_name, 5438 ha->host_num, 5439 scb->cdb[0], 5440 scb->cmd.basic_io.command_id, 5441 scb->bus, scb->target_id, scb->lun); 5442 } else { 5443 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5444 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5445 } 5446 5447 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); 5448 5449 return (IPS_SUCCESS); 5450 } 5451 5452 /****************************************************************************/ 5453 /* */ 5454 /* Routine Name: ips_isintr_copperhead */ 5455 /* */ 5456 /* Routine Description: */ 5457 /* */ 5458 /* Test to see if an interrupt is for us */ 5459 /* */ 5460 /****************************************************************************/ 5461 static int 5462 ips_isintr_copperhead(ips_ha_t * ha) 5463 { 5464 uint8_t Isr; 5465 5466 METHOD_TRACE("ips_isintr_copperhead", 2); 5467 5468 Isr = inb(ha->io_addr + IPS_REG_HISR); 5469 5470 if (Isr == 0xFF) 5471 /* ?!?! Nothing really there */ 5472 return (0); 5473 5474 if (Isr & IPS_BIT_SCE) 5475 return (1); 5476 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5477 /* status queue overflow or GHI */ 5478 /* just clear the interrupt */ 5479 outb(Isr, ha->io_addr + IPS_REG_HISR); 5480 } 5481 5482 return (0); 5483 } 5484 5485 /****************************************************************************/ 5486 /* */ 5487 /* Routine Name: ips_isintr_copperhead_memio */ 5488 /* */ 5489 /* Routine Description: */ 5490 /* */ 5491 /* Test to see if an interrupt is for us */ 5492 /* */ 5493 /****************************************************************************/ 5494 static int 5495 ips_isintr_copperhead_memio(ips_ha_t * ha) 5496 { 5497 uint8_t Isr; 5498 5499 METHOD_TRACE("ips_isintr_memio", 2); 5500 5501 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 5502 5503 if (Isr == 0xFF) 5504 /* ?!?! Nothing really there */ 5505 return (0); 5506 5507 if (Isr & IPS_BIT_SCE) 5508 return (1); 5509 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5510 /* status queue overflow or GHI */ 5511 /* just clear the interrupt */ 5512 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 5513 } 5514 5515 return (0); 5516 } 5517 5518 /****************************************************************************/ 5519 /* */ 5520 /* Routine Name: ips_isintr_morpheus */ 5521 /* */ 5522 /* Routine Description: */ 5523 /* */ 5524 /* Test to see if an interrupt is for us */ 5525 /* */ 5526 /****************************************************************************/ 5527 static int 5528 ips_isintr_morpheus(ips_ha_t * ha) 5529 { 5530 uint32_t Isr; 5531 5532 METHOD_TRACE("ips_isintr_morpheus", 2); 5533 5534 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 5535 5536 if (Isr & IPS_BIT_I2O_OPQI) 5537 return (1); 5538 else 5539 return (0); 5540 } 5541 5542 /****************************************************************************/ 5543 /* */ 5544 /* Routine Name: ips_wait */ 5545 /* */ 5546 /* Routine Description: */ 5547 /* */ 5548 /* Wait for a command to complete */ 5549 /* */ 5550 /****************************************************************************/ 5551 static int 5552 ips_wait(ips_ha_t * ha, int time, int intr) 5553 { 5554 int ret; 5555 int done; 5556 5557 METHOD_TRACE("ips_wait", 1); 5558 5559 ret = IPS_FAILURE; 5560 done = FALSE; 5561 5562 time *= IPS_ONE_SEC; /* convert seconds */ 5563 5564 while ((time > 0) && (!done)) { 5565 if (intr == IPS_INTR_ON) { 5566 if (ha->waitflag == FALSE) { 5567 ret = IPS_SUCCESS; 5568 done = TRUE; 5569 break; 5570 } 5571 } else if (intr == IPS_INTR_IORL) { 5572 if (ha->waitflag == FALSE) { 5573 /* 5574 * controller generated an interrupt to 5575 * acknowledge completion of the command 5576 * and ips_intr() has serviced the interrupt. 5577 */ 5578 ret = IPS_SUCCESS; 5579 done = TRUE; 5580 break; 5581 } 5582 5583 /* 5584 * NOTE: we already have the io_request_lock so 5585 * even if we get an interrupt it won't get serviced 5586 * until after we finish. 5587 */ 5588 5589 (*ha->func.intr) (ha); 5590 } 5591 5592 /* This looks like a very evil loop, but it only does this during start-up */ 5593 udelay(1000); 5594 time--; 5595 } 5596 5597 return (ret); 5598 } 5599 5600 /****************************************************************************/ 5601 /* */ 5602 /* Routine Name: ips_write_driver_status */ 5603 /* */ 5604 /* Routine Description: */ 5605 /* */ 5606 /* Write OS/Driver version to Page 5 of the nvram on the controller */ 5607 /* */ 5608 /****************************************************************************/ 5609 static int 5610 ips_write_driver_status(ips_ha_t * ha, int intr) 5611 { 5612 METHOD_TRACE("ips_write_driver_status", 1); 5613 5614 if (!ips_readwrite_page5(ha, FALSE, intr)) { 5615 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5616 "unable to read NVRAM page 5.\n"); 5617 5618 return (0); 5619 } 5620 5621 /* check to make sure the page has a valid */ 5622 /* signature */ 5623 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) { 5624 DEBUG_VAR(1, 5625 "(%s%d) NVRAM page 5 has an invalid signature: %X.", 5626 ips_name, ha->host_num, ha->nvram->signature); 5627 ha->nvram->signature = IPS_NVRAM_P5_SIG; 5628 } 5629 5630 DEBUG_VAR(2, 5631 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.", 5632 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type), 5633 ha->nvram->adapter_slot, ha->nvram->bios_high[0], 5634 ha->nvram->bios_high[1], ha->nvram->bios_high[2], 5635 ha->nvram->bios_high[3], ha->nvram->bios_low[0], 5636 ha->nvram->bios_low[1], ha->nvram->bios_low[2], 5637 ha->nvram->bios_low[3]); 5638 5639 ips_get_bios_version(ha, intr); 5640 5641 /* change values (as needed) */ 5642 ha->nvram->operating_system = IPS_OS_LINUX; 5643 ha->nvram->adapter_type = ha->ad_type; 5644 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4); 5645 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4); 5646 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4); 5647 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4); 5648 5649 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */ 5650 5651 /* now update the page */ 5652 if (!ips_readwrite_page5(ha, TRUE, intr)) { 5653 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5654 "unable to write NVRAM page 5.\n"); 5655 5656 return (0); 5657 } 5658 5659 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */ 5660 ha->slot_num = ha->nvram->adapter_slot; 5661 5662 return (1); 5663 } 5664 5665 /****************************************************************************/ 5666 /* */ 5667 /* Routine Name: ips_read_adapter_status */ 5668 /* */ 5669 /* Routine Description: */ 5670 /* */ 5671 /* Do an Inquiry command to the adapter */ 5672 /* */ 5673 /****************************************************************************/ 5674 static int 5675 ips_read_adapter_status(ips_ha_t * ha, int intr) 5676 { 5677 ips_scb_t *scb; 5678 int ret; 5679 5680 METHOD_TRACE("ips_read_adapter_status", 1); 5681 5682 scb = &ha->scbs[ha->max_cmds - 1]; 5683 5684 ips_init_scb(ha, scb); 5685 5686 scb->timeout = ips_cmd_timeout; 5687 scb->cdb[0] = IPS_CMD_ENQUIRY; 5688 5689 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 5690 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5691 scb->cmd.basic_io.sg_count = 0; 5692 scb->cmd.basic_io.lba = 0; 5693 scb->cmd.basic_io.sector_count = 0; 5694 scb->cmd.basic_io.log_drv = 0; 5695 scb->data_len = sizeof (*ha->enq); 5696 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 5697 5698 /* send command */ 5699 if (((ret = 5700 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5701 || (ret == IPS_SUCCESS_IMM) 5702 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5703 return (0); 5704 5705 return (1); 5706 } 5707 5708 /****************************************************************************/ 5709 /* */ 5710 /* Routine Name: ips_read_subsystem_parameters */ 5711 /* */ 5712 /* Routine Description: */ 5713 /* */ 5714 /* Read subsystem parameters from the adapter */ 5715 /* */ 5716 /****************************************************************************/ 5717 static int 5718 ips_read_subsystem_parameters(ips_ha_t * ha, int intr) 5719 { 5720 ips_scb_t *scb; 5721 int ret; 5722 5723 METHOD_TRACE("ips_read_subsystem_parameters", 1); 5724 5725 scb = &ha->scbs[ha->max_cmds - 1]; 5726 5727 ips_init_scb(ha, scb); 5728 5729 scb->timeout = ips_cmd_timeout; 5730 scb->cdb[0] = IPS_CMD_GET_SUBSYS; 5731 5732 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS; 5733 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5734 scb->cmd.basic_io.sg_count = 0; 5735 scb->cmd.basic_io.lba = 0; 5736 scb->cmd.basic_io.sector_count = 0; 5737 scb->cmd.basic_io.log_drv = 0; 5738 scb->data_len = sizeof (*ha->subsys); 5739 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 5740 5741 /* send command */ 5742 if (((ret = 5743 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5744 || (ret == IPS_SUCCESS_IMM) 5745 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5746 return (0); 5747 5748 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys)); 5749 return (1); 5750 } 5751 5752 /****************************************************************************/ 5753 /* */ 5754 /* Routine Name: ips_read_config */ 5755 /* */ 5756 /* Routine Description: */ 5757 /* */ 5758 /* Read the configuration on the adapter */ 5759 /* */ 5760 /****************************************************************************/ 5761 static int 5762 ips_read_config(ips_ha_t * ha, int intr) 5763 { 5764 ips_scb_t *scb; 5765 int i; 5766 int ret; 5767 5768 METHOD_TRACE("ips_read_config", 1); 5769 5770 /* set defaults for initiator IDs */ 5771 for (i = 0; i < 4; i++) 5772 ha->conf->init_id[i] = 7; 5773 5774 scb = &ha->scbs[ha->max_cmds - 1]; 5775 5776 ips_init_scb(ha, scb); 5777 5778 scb->timeout = ips_cmd_timeout; 5779 scb->cdb[0] = IPS_CMD_READ_CONF; 5780 5781 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF; 5782 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5783 scb->data_len = sizeof (*ha->conf); 5784 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 5785 5786 /* send command */ 5787 if (((ret = 5788 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5789 || (ret == IPS_SUCCESS_IMM) 5790 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 5791 5792 memset(ha->conf, 0, sizeof (IPS_CONF)); 5793 5794 /* reset initiator IDs */ 5795 for (i = 0; i < 4; i++) 5796 ha->conf->init_id[i] = 7; 5797 5798 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */ 5799 if ((scb->basic_status & IPS_GSC_STATUS_MASK) == 5800 IPS_CMD_CMPLT_WERROR) 5801 return (1); 5802 5803 return (0); 5804 } 5805 5806 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); 5807 return (1); 5808 } 5809 5810 /****************************************************************************/ 5811 /* */ 5812 /* Routine Name: ips_readwrite_page5 */ 5813 /* */ 5814 /* Routine Description: */ 5815 /* */ 5816 /* Read nvram page 5 from the adapter */ 5817 /* */ 5818 /****************************************************************************/ 5819 static int 5820 ips_readwrite_page5(ips_ha_t * ha, int write, int intr) 5821 { 5822 ips_scb_t *scb; 5823 int ret; 5824 5825 METHOD_TRACE("ips_readwrite_page5", 1); 5826 5827 scb = &ha->scbs[ha->max_cmds - 1]; 5828 5829 ips_init_scb(ha, scb); 5830 5831 scb->timeout = ips_cmd_timeout; 5832 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE; 5833 5834 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE; 5835 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb); 5836 scb->cmd.nvram.page = 5; 5837 scb->cmd.nvram.write = write; 5838 scb->cmd.nvram.reserved = 0; 5839 scb->cmd.nvram.reserved2 = 0; 5840 scb->data_len = sizeof (*ha->nvram); 5841 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; 5842 if (write) 5843 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); 5844 5845 /* issue the command */ 5846 if (((ret = 5847 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5848 || (ret == IPS_SUCCESS_IMM) 5849 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 5850 5851 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5)); 5852 5853 return (0); 5854 } 5855 if (!write) 5856 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram)); 5857 return (1); 5858 } 5859 5860 /****************************************************************************/ 5861 /* */ 5862 /* Routine Name: ips_clear_adapter */ 5863 /* */ 5864 /* Routine Description: */ 5865 /* */ 5866 /* Clear the stripe lock tables */ 5867 /* */ 5868 /****************************************************************************/ 5869 static int 5870 ips_clear_adapter(ips_ha_t * ha, int intr) 5871 { 5872 ips_scb_t *scb; 5873 int ret; 5874 5875 METHOD_TRACE("ips_clear_adapter", 1); 5876 5877 scb = &ha->scbs[ha->max_cmds - 1]; 5878 5879 ips_init_scb(ha, scb); 5880 5881 scb->timeout = ips_reset_timeout; 5882 scb->cdb[0] = IPS_CMD_CONFIG_SYNC; 5883 5884 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC; 5885 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb); 5886 scb->cmd.config_sync.channel = 0; 5887 scb->cmd.config_sync.source_target = IPS_POCL; 5888 scb->cmd.config_sync.reserved = 0; 5889 scb->cmd.config_sync.reserved2 = 0; 5890 scb->cmd.config_sync.reserved3 = 0; 5891 5892 /* issue command */ 5893 if (((ret = 5894 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE) 5895 || (ret == IPS_SUCCESS_IMM) 5896 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5897 return (0); 5898 5899 /* send unlock stripe command */ 5900 ips_init_scb(ha, scb); 5901 5902 scb->cdb[0] = IPS_CMD_ERROR_TABLE; 5903 scb->timeout = ips_reset_timeout; 5904 5905 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE; 5906 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb); 5907 scb->cmd.unlock_stripe.log_drv = 0; 5908 scb->cmd.unlock_stripe.control = IPS_CSL; 5909 scb->cmd.unlock_stripe.reserved = 0; 5910 scb->cmd.unlock_stripe.reserved2 = 0; 5911 scb->cmd.unlock_stripe.reserved3 = 0; 5912 5913 /* issue command */ 5914 if (((ret = 5915 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5916 || (ret == IPS_SUCCESS_IMM) 5917 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5918 return (0); 5919 5920 return (1); 5921 } 5922 5923 /****************************************************************************/ 5924 /* */ 5925 /* Routine Name: ips_ffdc_reset */ 5926 /* */ 5927 /* Routine Description: */ 5928 /* */ 5929 /* FFDC: write reset info */ 5930 /* */ 5931 /****************************************************************************/ 5932 static void 5933 ips_ffdc_reset(ips_ha_t * ha, int intr) 5934 { 5935 ips_scb_t *scb; 5936 5937 METHOD_TRACE("ips_ffdc_reset", 1); 5938 5939 scb = &ha->scbs[ha->max_cmds - 1]; 5940 5941 ips_init_scb(ha, scb); 5942 5943 scb->timeout = ips_cmd_timeout; 5944 scb->cdb[0] = IPS_CMD_FFDC; 5945 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 5946 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 5947 scb->cmd.ffdc.reset_count = ha->reset_count; 5948 scb->cmd.ffdc.reset_type = 0x80; 5949 5950 /* convert time to what the card wants */ 5951 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 5952 5953 /* issue command */ 5954 ips_send_wait(ha, scb, ips_cmd_timeout, intr); 5955 } 5956 5957 /****************************************************************************/ 5958 /* */ 5959 /* Routine Name: ips_ffdc_time */ 5960 /* */ 5961 /* Routine Description: */ 5962 /* */ 5963 /* FFDC: write time info */ 5964 /* */ 5965 /****************************************************************************/ 5966 static void 5967 ips_ffdc_time(ips_ha_t * ha) 5968 { 5969 ips_scb_t *scb; 5970 5971 METHOD_TRACE("ips_ffdc_time", 1); 5972 5973 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num); 5974 5975 scb = &ha->scbs[ha->max_cmds - 1]; 5976 5977 ips_init_scb(ha, scb); 5978 5979 scb->timeout = ips_cmd_timeout; 5980 scb->cdb[0] = IPS_CMD_FFDC; 5981 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 5982 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 5983 scb->cmd.ffdc.reset_count = 0; 5984 scb->cmd.ffdc.reset_type = 0; 5985 5986 /* convert time to what the card wants */ 5987 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 5988 5989 /* issue command */ 5990 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC); 5991 } 5992 5993 /****************************************************************************/ 5994 /* */ 5995 /* Routine Name: ips_fix_ffdc_time */ 5996 /* */ 5997 /* Routine Description: */ 5998 /* Adjust time_t to what the card wants */ 5999 /* */ 6000 /****************************************************************************/ 6001 static void 6002 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time) 6003 { 6004 long days; 6005 long rem; 6006 int i; 6007 int year; 6008 int yleap; 6009 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR }; 6010 int month_lengths[12][2] = { {31, 31}, 6011 {28, 29}, 6012 {31, 31}, 6013 {30, 30}, 6014 {31, 31}, 6015 {30, 30}, 6016 {31, 31}, 6017 {31, 31}, 6018 {30, 30}, 6019 {31, 31}, 6020 {30, 30}, 6021 {31, 31} 6022 }; 6023 6024 METHOD_TRACE("ips_fix_ffdc_time", 1); 6025 6026 days = current_time / IPS_SECS_DAY; 6027 rem = current_time % IPS_SECS_DAY; 6028 6029 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR); 6030 rem = rem % IPS_SECS_HOUR; 6031 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN); 6032 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN); 6033 6034 year = IPS_EPOCH_YEAR; 6035 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) { 6036 int newy; 6037 6038 newy = year + (days / IPS_DAYS_NORMAL_YEAR); 6039 if (days < 0) 6040 --newy; 6041 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR + 6042 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) - 6043 IPS_NUM_LEAP_YEARS_THROUGH(year - 1); 6044 year = newy; 6045 } 6046 6047 scb->cmd.ffdc.yearH = year / 100; 6048 scb->cmd.ffdc.yearL = year % 100; 6049 6050 for (i = 0; days >= month_lengths[i][yleap]; ++i) 6051 days -= month_lengths[i][yleap]; 6052 6053 scb->cmd.ffdc.month = i + 1; 6054 scb->cmd.ffdc.day = days + 1; 6055 } 6056 6057 /**************************************************************************** 6058 * BIOS Flash Routines * 6059 ****************************************************************************/ 6060 6061 /****************************************************************************/ 6062 /* */ 6063 /* Routine Name: ips_erase_bios */ 6064 /* */ 6065 /* Routine Description: */ 6066 /* Erase the BIOS on the adapter */ 6067 /* */ 6068 /****************************************************************************/ 6069 static int 6070 ips_erase_bios(ips_ha_t * ha) 6071 { 6072 int timeout; 6073 uint8_t status = 0; 6074 6075 METHOD_TRACE("ips_erase_bios", 1); 6076 6077 status = 0; 6078 6079 /* Clear the status register */ 6080 outl(0, ha->io_addr + IPS_REG_FLAP); 6081 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6082 udelay(25); /* 25 us */ 6083 6084 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6085 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6086 udelay(25); /* 25 us */ 6087 6088 /* Erase Setup */ 6089 outb(0x20, ha->io_addr + IPS_REG_FLDP); 6090 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6091 udelay(25); /* 25 us */ 6092 6093 /* Erase Confirm */ 6094 outb(0xD0, ha->io_addr + IPS_REG_FLDP); 6095 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6096 udelay(25); /* 25 us */ 6097 6098 /* Erase Status */ 6099 outb(0x70, ha->io_addr + IPS_REG_FLDP); 6100 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6101 udelay(25); /* 25 us */ 6102 6103 timeout = 80000; /* 80 seconds */ 6104 6105 while (timeout > 0) { 6106 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6107 outl(0, ha->io_addr + IPS_REG_FLAP); 6108 udelay(25); /* 25 us */ 6109 } 6110 6111 status = inb(ha->io_addr + IPS_REG_FLDP); 6112 6113 if (status & 0x80) 6114 break; 6115 6116 MDELAY(1); 6117 timeout--; 6118 } 6119 6120 /* check for timeout */ 6121 if (timeout <= 0) { 6122 /* timeout */ 6123 6124 /* try to suspend the erase */ 6125 outb(0xB0, ha->io_addr + IPS_REG_FLDP); 6126 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6127 udelay(25); /* 25 us */ 6128 6129 /* wait for 10 seconds */ 6130 timeout = 10000; 6131 while (timeout > 0) { 6132 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6133 outl(0, ha->io_addr + IPS_REG_FLAP); 6134 udelay(25); /* 25 us */ 6135 } 6136 6137 status = inb(ha->io_addr + IPS_REG_FLDP); 6138 6139 if (status & 0xC0) 6140 break; 6141 6142 MDELAY(1); 6143 timeout--; 6144 } 6145 6146 return (1); 6147 } 6148 6149 /* check for valid VPP */ 6150 if (status & 0x08) 6151 /* VPP failure */ 6152 return (1); 6153 6154 /* check for successful flash */ 6155 if (status & 0x30) 6156 /* sequence error */ 6157 return (1); 6158 6159 /* Otherwise, we were successful */ 6160 /* clear status */ 6161 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6162 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6163 udelay(25); /* 25 us */ 6164 6165 /* enable reads */ 6166 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6167 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6168 udelay(25); /* 25 us */ 6169 6170 return (0); 6171 } 6172 6173 /****************************************************************************/ 6174 /* */ 6175 /* Routine Name: ips_erase_bios_memio */ 6176 /* */ 6177 /* Routine Description: */ 6178 /* Erase the BIOS on the adapter */ 6179 /* */ 6180 /****************************************************************************/ 6181 static int 6182 ips_erase_bios_memio(ips_ha_t * ha) 6183 { 6184 int timeout; 6185 uint8_t status; 6186 6187 METHOD_TRACE("ips_erase_bios_memio", 1); 6188 6189 status = 0; 6190 6191 /* Clear the status register */ 6192 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6193 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6194 udelay(25); /* 25 us */ 6195 6196 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6197 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6198 udelay(25); /* 25 us */ 6199 6200 /* Erase Setup */ 6201 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); 6202 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6203 udelay(25); /* 25 us */ 6204 6205 /* Erase Confirm */ 6206 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); 6207 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6208 udelay(25); /* 25 us */ 6209 6210 /* Erase Status */ 6211 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); 6212 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6213 udelay(25); /* 25 us */ 6214 6215 timeout = 80000; /* 80 seconds */ 6216 6217 while (timeout > 0) { 6218 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6219 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6220 udelay(25); /* 25 us */ 6221 } 6222 6223 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6224 6225 if (status & 0x80) 6226 break; 6227 6228 MDELAY(1); 6229 timeout--; 6230 } 6231 6232 /* check for timeout */ 6233 if (timeout <= 0) { 6234 /* timeout */ 6235 6236 /* try to suspend the erase */ 6237 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); 6238 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6239 udelay(25); /* 25 us */ 6240 6241 /* wait for 10 seconds */ 6242 timeout = 10000; 6243 while (timeout > 0) { 6244 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6245 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6246 udelay(25); /* 25 us */ 6247 } 6248 6249 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6250 6251 if (status & 0xC0) 6252 break; 6253 6254 MDELAY(1); 6255 timeout--; 6256 } 6257 6258 return (1); 6259 } 6260 6261 /* check for valid VPP */ 6262 if (status & 0x08) 6263 /* VPP failure */ 6264 return (1); 6265 6266 /* check for successful flash */ 6267 if (status & 0x30) 6268 /* sequence error */ 6269 return (1); 6270 6271 /* Otherwise, we were successful */ 6272 /* clear status */ 6273 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6274 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6275 udelay(25); /* 25 us */ 6276 6277 /* enable reads */ 6278 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6279 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6280 udelay(25); /* 25 us */ 6281 6282 return (0); 6283 } 6284 6285 /****************************************************************************/ 6286 /* */ 6287 /* Routine Name: ips_program_bios */ 6288 /* */ 6289 /* Routine Description: */ 6290 /* Program the BIOS on the adapter */ 6291 /* */ 6292 /****************************************************************************/ 6293 static int 6294 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6295 uint32_t offset) 6296 { 6297 int i; 6298 int timeout; 6299 uint8_t status = 0; 6300 6301 METHOD_TRACE("ips_program_bios", 1); 6302 6303 status = 0; 6304 6305 for (i = 0; i < buffersize; i++) { 6306 /* write a byte */ 6307 outl(i + offset, ha->io_addr + IPS_REG_FLAP); 6308 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6309 udelay(25); /* 25 us */ 6310 6311 outb(0x40, ha->io_addr + IPS_REG_FLDP); 6312 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6313 udelay(25); /* 25 us */ 6314 6315 outb(buffer[i], ha->io_addr + IPS_REG_FLDP); 6316 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6317 udelay(25); /* 25 us */ 6318 6319 /* wait up to one second */ 6320 timeout = 1000; 6321 while (timeout > 0) { 6322 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6323 outl(0, ha->io_addr + IPS_REG_FLAP); 6324 udelay(25); /* 25 us */ 6325 } 6326 6327 status = inb(ha->io_addr + IPS_REG_FLDP); 6328 6329 if (status & 0x80) 6330 break; 6331 6332 MDELAY(1); 6333 timeout--; 6334 } 6335 6336 if (timeout == 0) { 6337 /* timeout error */ 6338 outl(0, ha->io_addr + IPS_REG_FLAP); 6339 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6340 udelay(25); /* 25 us */ 6341 6342 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6343 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6344 udelay(25); /* 25 us */ 6345 6346 return (1); 6347 } 6348 6349 /* check the status */ 6350 if (status & 0x18) { 6351 /* programming error */ 6352 outl(0, ha->io_addr + IPS_REG_FLAP); 6353 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6354 udelay(25); /* 25 us */ 6355 6356 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6357 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6358 udelay(25); /* 25 us */ 6359 6360 return (1); 6361 } 6362 } /* end for */ 6363 6364 /* Enable reading */ 6365 outl(0, ha->io_addr + IPS_REG_FLAP); 6366 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6367 udelay(25); /* 25 us */ 6368 6369 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6370 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6371 udelay(25); /* 25 us */ 6372 6373 return (0); 6374 } 6375 6376 /****************************************************************************/ 6377 /* */ 6378 /* Routine Name: ips_program_bios_memio */ 6379 /* */ 6380 /* Routine Description: */ 6381 /* Program the BIOS on the adapter */ 6382 /* */ 6383 /****************************************************************************/ 6384 static int 6385 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6386 uint32_t offset) 6387 { 6388 int i; 6389 int timeout; 6390 uint8_t status = 0; 6391 6392 METHOD_TRACE("ips_program_bios_memio", 1); 6393 6394 status = 0; 6395 6396 for (i = 0; i < buffersize; i++) { 6397 /* write a byte */ 6398 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6399 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6400 udelay(25); /* 25 us */ 6401 6402 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); 6403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6404 udelay(25); /* 25 us */ 6405 6406 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); 6407 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6408 udelay(25); /* 25 us */ 6409 6410 /* wait up to one second */ 6411 timeout = 1000; 6412 while (timeout > 0) { 6413 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6414 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6415 udelay(25); /* 25 us */ 6416 } 6417 6418 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6419 6420 if (status & 0x80) 6421 break; 6422 6423 MDELAY(1); 6424 timeout--; 6425 } 6426 6427 if (timeout == 0) { 6428 /* timeout error */ 6429 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6430 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6431 udelay(25); /* 25 us */ 6432 6433 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6434 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6435 udelay(25); /* 25 us */ 6436 6437 return (1); 6438 } 6439 6440 /* check the status */ 6441 if (status & 0x18) { 6442 /* programming error */ 6443 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6444 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6445 udelay(25); /* 25 us */ 6446 6447 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6448 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6449 udelay(25); /* 25 us */ 6450 6451 return (1); 6452 } 6453 } /* end for */ 6454 6455 /* Enable reading */ 6456 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6457 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6458 udelay(25); /* 25 us */ 6459 6460 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6461 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6462 udelay(25); /* 25 us */ 6463 6464 return (0); 6465 } 6466 6467 /****************************************************************************/ 6468 /* */ 6469 /* Routine Name: ips_verify_bios */ 6470 /* */ 6471 /* Routine Description: */ 6472 /* Verify the BIOS on the adapter */ 6473 /* */ 6474 /****************************************************************************/ 6475 static int 6476 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6477 uint32_t offset) 6478 { 6479 uint8_t checksum; 6480 int i; 6481 6482 METHOD_TRACE("ips_verify_bios", 1); 6483 6484 /* test 1st byte */ 6485 outl(0, ha->io_addr + IPS_REG_FLAP); 6486 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6487 udelay(25); /* 25 us */ 6488 6489 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 6490 return (1); 6491 6492 outl(1, ha->io_addr + IPS_REG_FLAP); 6493 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6494 udelay(25); /* 25 us */ 6495 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 6496 return (1); 6497 6498 checksum = 0xff; 6499 for (i = 2; i < buffersize; i++) { 6500 6501 outl(i + offset, ha->io_addr + IPS_REG_FLAP); 6502 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6503 udelay(25); /* 25 us */ 6504 6505 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); 6506 } 6507 6508 if (checksum != 0) 6509 /* failure */ 6510 return (1); 6511 else 6512 /* success */ 6513 return (0); 6514 } 6515 6516 /****************************************************************************/ 6517 /* */ 6518 /* Routine Name: ips_verify_bios_memio */ 6519 /* */ 6520 /* Routine Description: */ 6521 /* Verify the BIOS on the adapter */ 6522 /* */ 6523 /****************************************************************************/ 6524 static int 6525 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6526 uint32_t offset) 6527 { 6528 uint8_t checksum; 6529 int i; 6530 6531 METHOD_TRACE("ips_verify_bios_memio", 1); 6532 6533 /* test 1st byte */ 6534 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6535 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6536 udelay(25); /* 25 us */ 6537 6538 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 6539 return (1); 6540 6541 writel(1, ha->mem_ptr + IPS_REG_FLAP); 6542 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6543 udelay(25); /* 25 us */ 6544 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 6545 return (1); 6546 6547 checksum = 0xff; 6548 for (i = 2; i < buffersize; i++) { 6549 6550 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6551 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6552 udelay(25); /* 25 us */ 6553 6554 checksum = 6555 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); 6556 } 6557 6558 if (checksum != 0) 6559 /* failure */ 6560 return (1); 6561 else 6562 /* success */ 6563 return (0); 6564 } 6565 6566 /****************************************************************************/ 6567 /* */ 6568 /* Routine Name: ips_abort_init */ 6569 /* */ 6570 /* Routine Description: */ 6571 /* cleanup routine for a failed adapter initialization */ 6572 /****************************************************************************/ 6573 static int 6574 ips_abort_init(ips_ha_t * ha, int index) 6575 { 6576 ha->active = 0; 6577 ips_free(ha); 6578 ips_ha[index] = NULL; 6579 ips_sh[index] = NULL; 6580 return -1; 6581 } 6582 6583 /****************************************************************************/ 6584 /* */ 6585 /* Routine Name: ips_shift_controllers */ 6586 /* */ 6587 /* Routine Description: */ 6588 /* helper function for ordering adapters */ 6589 /****************************************************************************/ 6590 static void 6591 ips_shift_controllers(int lowindex, int highindex) 6592 { 6593 ips_ha_t *ha_sav = ips_ha[highindex]; 6594 struct Scsi_Host *sh_sav = ips_sh[highindex]; 6595 int i; 6596 6597 for (i = highindex; i > lowindex; i--) { 6598 ips_ha[i] = ips_ha[i - 1]; 6599 ips_sh[i] = ips_sh[i - 1]; 6600 ips_ha[i]->host_num = i; 6601 } 6602 ha_sav->host_num = lowindex; 6603 ips_ha[lowindex] = ha_sav; 6604 ips_sh[lowindex] = sh_sav; 6605 } 6606 6607 /****************************************************************************/ 6608 /* */ 6609 /* Routine Name: ips_order_controllers */ 6610 /* */ 6611 /* Routine Description: */ 6612 /* place controllers is the "proper" boot order */ 6613 /****************************************************************************/ 6614 static void 6615 ips_order_controllers(void) 6616 { 6617 int i, j, tmp, position = 0; 6618 IPS_NVRAM_P5 *nvram; 6619 if (!ips_ha[0]) 6620 return; 6621 nvram = ips_ha[0]->nvram; 6622 6623 if (nvram->adapter_order[0]) { 6624 for (i = 1; i <= nvram->adapter_order[0]; i++) { 6625 for (j = position; j < ips_num_controllers; j++) { 6626 switch (ips_ha[j]->ad_type) { 6627 case IPS_ADTYPE_SERVERAID6M: 6628 case IPS_ADTYPE_SERVERAID7M: 6629 if (nvram->adapter_order[i] == 'M') { 6630 ips_shift_controllers(position, 6631 j); 6632 position++; 6633 } 6634 break; 6635 case IPS_ADTYPE_SERVERAID4L: 6636 case IPS_ADTYPE_SERVERAID4M: 6637 case IPS_ADTYPE_SERVERAID4MX: 6638 case IPS_ADTYPE_SERVERAID4LX: 6639 if (nvram->adapter_order[i] == 'N') { 6640 ips_shift_controllers(position, 6641 j); 6642 position++; 6643 } 6644 break; 6645 case IPS_ADTYPE_SERVERAID6I: 6646 case IPS_ADTYPE_SERVERAID5I2: 6647 case IPS_ADTYPE_SERVERAID5I1: 6648 case IPS_ADTYPE_SERVERAID7k: 6649 if (nvram->adapter_order[i] == 'S') { 6650 ips_shift_controllers(position, 6651 j); 6652 position++; 6653 } 6654 break; 6655 case IPS_ADTYPE_SERVERAID: 6656 case IPS_ADTYPE_SERVERAID2: 6657 case IPS_ADTYPE_NAVAJO: 6658 case IPS_ADTYPE_KIOWA: 6659 case IPS_ADTYPE_SERVERAID3L: 6660 case IPS_ADTYPE_SERVERAID3: 6661 case IPS_ADTYPE_SERVERAID4H: 6662 if (nvram->adapter_order[i] == 'A') { 6663 ips_shift_controllers(position, 6664 j); 6665 position++; 6666 } 6667 break; 6668 default: 6669 break; 6670 } 6671 } 6672 } 6673 /* if adapter_order[0], then ordering is complete */ 6674 return; 6675 } 6676 /* old bios, use older ordering */ 6677 tmp = 0; 6678 for (i = position; i < ips_num_controllers; i++) { 6679 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 || 6680 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) { 6681 ips_shift_controllers(position, i); 6682 position++; 6683 tmp = 1; 6684 } 6685 } 6686 /* if there were no 5I cards, then don't do any extra ordering */ 6687 if (!tmp) 6688 return; 6689 for (i = position; i < ips_num_controllers; i++) { 6690 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L || 6691 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M || 6692 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX || 6693 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) { 6694 ips_shift_controllers(position, i); 6695 position++; 6696 } 6697 } 6698 6699 return; 6700 } 6701 6702 /****************************************************************************/ 6703 /* */ 6704 /* Routine Name: ips_register_scsi */ 6705 /* */ 6706 /* Routine Description: */ 6707 /* perform any registration and setup with the scsi layer */ 6708 /****************************************************************************/ 6709 static int 6710 ips_register_scsi(int index) 6711 { 6712 struct Scsi_Host *sh; 6713 ips_ha_t *ha, *oldha = ips_ha[index]; 6714 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t)); 6715 if (!sh) { 6716 IPS_PRINTK(KERN_WARNING, oldha->pcidev, 6717 "Unable to register controller with SCSI subsystem\n"); 6718 return -1; 6719 } 6720 ha = IPS_HA(sh); 6721 memcpy(ha, oldha, sizeof (ips_ha_t)); 6722 free_irq(oldha->pcidev->irq, oldha); 6723 /* Install the interrupt handler with the new ha */ 6724 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 6725 IPS_PRINTK(KERN_WARNING, ha->pcidev, 6726 "Unable to install interrupt handler\n"); 6727 goto err_out_sh; 6728 } 6729 6730 kfree(oldha); 6731 6732 /* Store away needed values for later use */ 6733 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; 6734 sh->sg_tablesize = sh->hostt->sg_tablesize; 6735 sh->can_queue = sh->hostt->can_queue; 6736 sh->cmd_per_lun = sh->hostt->cmd_per_lun; 6737 sh->use_clustering = sh->hostt->use_clustering; 6738 sh->max_sectors = 128; 6739 6740 sh->max_id = ha->ntargets; 6741 sh->max_lun = ha->nlun; 6742 sh->max_channel = ha->nbus - 1; 6743 sh->can_queue = ha->max_cmds - 1; 6744 6745 if (scsi_add_host(sh, &ha->pcidev->dev)) 6746 goto err_out; 6747 6748 ips_sh[index] = sh; 6749 ips_ha[index] = ha; 6750 6751 scsi_scan_host(sh); 6752 6753 return 0; 6754 6755 err_out: 6756 free_irq(ha->pcidev->irq, ha); 6757 err_out_sh: 6758 scsi_host_put(sh); 6759 return -1; 6760 } 6761 6762 /*---------------------------------------------------------------------------*/ 6763 /* Routine Name: ips_remove_device */ 6764 /* */ 6765 /* Routine Description: */ 6766 /* Remove one Adapter ( Hot Plugging ) */ 6767 /*---------------------------------------------------------------------------*/ 6768 static void 6769 ips_remove_device(struct pci_dev *pci_dev) 6770 { 6771 struct Scsi_Host *sh = pci_get_drvdata(pci_dev); 6772 6773 pci_set_drvdata(pci_dev, NULL); 6774 6775 ips_release(sh); 6776 6777 pci_release_regions(pci_dev); 6778 pci_disable_device(pci_dev); 6779 } 6780 6781 /****************************************************************************/ 6782 /* */ 6783 /* Routine Name: ips_module_init */ 6784 /* */ 6785 /* Routine Description: */ 6786 /* function called on module load */ 6787 /****************************************************************************/ 6788 static int __init 6789 ips_module_init(void) 6790 { 6791 if (pci_register_driver(&ips_pci_driver) < 0) 6792 return -ENODEV; 6793 ips_driver_template.module = THIS_MODULE; 6794 ips_order_controllers(); 6795 if (!ips_detect(&ips_driver_template)) { 6796 pci_unregister_driver(&ips_pci_driver); 6797 return -ENODEV; 6798 } 6799 register_reboot_notifier(&ips_notifier); 6800 return 0; 6801 } 6802 6803 /****************************************************************************/ 6804 /* */ 6805 /* Routine Name: ips_module_exit */ 6806 /* */ 6807 /* Routine Description: */ 6808 /* function called on module unload */ 6809 /****************************************************************************/ 6810 static void __exit 6811 ips_module_exit(void) 6812 { 6813 pci_unregister_driver(&ips_pci_driver); 6814 unregister_reboot_notifier(&ips_notifier); 6815 } 6816 6817 module_init(ips_module_init); 6818 module_exit(ips_module_exit); 6819 6820 /*---------------------------------------------------------------------------*/ 6821 /* Routine Name: ips_insert_device */ 6822 /* */ 6823 /* Routine Description: */ 6824 /* Add One Adapter ( Hot Plug ) */ 6825 /* */ 6826 /* Return Value: */ 6827 /* 0 if Successful, else non-zero */ 6828 /*---------------------------------------------------------------------------*/ 6829 static int 6830 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) 6831 { 6832 int index = -1; 6833 int rc; 6834 6835 METHOD_TRACE("ips_insert_device", 1); 6836 rc = pci_enable_device(pci_dev); 6837 if (rc) 6838 return rc; 6839 6840 rc = pci_request_regions(pci_dev, "ips"); 6841 if (rc) 6842 goto err_out; 6843 6844 rc = ips_init_phase1(pci_dev, &index); 6845 if (rc == SUCCESS) 6846 rc = ips_init_phase2(index); 6847 6848 if (ips_hotplug) 6849 if (ips_register_scsi(index)) { 6850 ips_free(ips_ha[index]); 6851 rc = -1; 6852 } 6853 6854 if (rc == SUCCESS) 6855 ips_num_controllers++; 6856 6857 ips_next_controller = ips_num_controllers; 6858 6859 if (rc < 0) { 6860 rc = -ENODEV; 6861 goto err_out_regions; 6862 } 6863 6864 pci_set_drvdata(pci_dev, ips_sh[index]); 6865 return 0; 6866 6867 err_out_regions: 6868 pci_release_regions(pci_dev); 6869 err_out: 6870 pci_disable_device(pci_dev); 6871 return rc; 6872 } 6873 6874 /*---------------------------------------------------------------------------*/ 6875 /* Routine Name: ips_init_phase1 */ 6876 /* */ 6877 /* Routine Description: */ 6878 /* Adapter Initialization */ 6879 /* */ 6880 /* Return Value: */ 6881 /* 0 if Successful, else non-zero */ 6882 /*---------------------------------------------------------------------------*/ 6883 static int 6884 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) 6885 { 6886 ips_ha_t *ha; 6887 uint32_t io_addr; 6888 uint32_t mem_addr; 6889 uint32_t io_len; 6890 uint32_t mem_len; 6891 uint8_t bus; 6892 uint8_t func; 6893 int j; 6894 int index; 6895 dma_addr_t dma_address; 6896 char __iomem *ioremap_ptr; 6897 char __iomem *mem_ptr; 6898 uint32_t IsDead; 6899 6900 METHOD_TRACE("ips_init_phase1", 1); 6901 index = IPS_MAX_ADAPTERS; 6902 for (j = 0; j < IPS_MAX_ADAPTERS; j++) { 6903 if (ips_ha[j] == NULL) { 6904 index = j; 6905 break; 6906 } 6907 } 6908 6909 if (index >= IPS_MAX_ADAPTERS) 6910 return -1; 6911 6912 /* stuff that we get in dev */ 6913 bus = pci_dev->bus->number; 6914 func = pci_dev->devfn; 6915 6916 /* Init MEM/IO addresses to 0 */ 6917 mem_addr = 0; 6918 io_addr = 0; 6919 mem_len = 0; 6920 io_len = 0; 6921 6922 for (j = 0; j < 2; j++) { 6923 if (!pci_resource_start(pci_dev, j)) 6924 break; 6925 6926 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) { 6927 io_addr = pci_resource_start(pci_dev, j); 6928 io_len = pci_resource_len(pci_dev, j); 6929 } else { 6930 mem_addr = pci_resource_start(pci_dev, j); 6931 mem_len = pci_resource_len(pci_dev, j); 6932 } 6933 } 6934 6935 /* setup memory mapped area (if applicable) */ 6936 if (mem_addr) { 6937 uint32_t base; 6938 uint32_t offs; 6939 6940 base = mem_addr & PAGE_MASK; 6941 offs = mem_addr - base; 6942 ioremap_ptr = ioremap(base, PAGE_SIZE); 6943 if (!ioremap_ptr) 6944 return -1; 6945 mem_ptr = ioremap_ptr + offs; 6946 } else { 6947 ioremap_ptr = NULL; 6948 mem_ptr = NULL; 6949 } 6950 6951 /* found a controller */ 6952 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL); 6953 if (ha == NULL) { 6954 IPS_PRINTK(KERN_WARNING, pci_dev, 6955 "Unable to allocate temporary ha struct\n"); 6956 return -1; 6957 } 6958 6959 ips_sh[index] = NULL; 6960 ips_ha[index] = ha; 6961 ha->active = 1; 6962 6963 /* Store info in HA structure */ 6964 ha->io_addr = io_addr; 6965 ha->io_len = io_len; 6966 ha->mem_addr = mem_addr; 6967 ha->mem_len = mem_len; 6968 ha->mem_ptr = mem_ptr; 6969 ha->ioremap_ptr = ioremap_ptr; 6970 ha->host_num = (uint32_t) index; 6971 ha->slot_num = PCI_SLOT(pci_dev->devfn); 6972 ha->pcidev = pci_dev; 6973 6974 /* 6975 * Set the pci_dev's dma_mask. Not all adapters support 64bit 6976 * addressing so don't enable it if the adapter can't support 6977 * it! Also, don't use 64bit addressing if dma addresses 6978 * are guaranteed to be < 4G. 6979 */ 6980 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) && 6981 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) { 6982 (ha)->flags |= IPS_HA_ENH_SG; 6983 } else { 6984 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) { 6985 printk(KERN_WARNING "Unable to set DMA Mask\n"); 6986 return ips_abort_init(ha, index); 6987 } 6988 } 6989 if(ips_cd_boot && !ips_FlashData){ 6990 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7, 6991 &ips_flashbusaddr); 6992 } 6993 6994 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ), 6995 &ha->enq_busaddr); 6996 if (!ha->enq) { 6997 IPS_PRINTK(KERN_WARNING, pci_dev, 6998 "Unable to allocate host inquiry structure\n"); 6999 return ips_abort_init(ha, index); 7000 } 7001 7002 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) + 7003 sizeof (IPS_IO_CMD), &dma_address); 7004 if (!ha->adapt) { 7005 IPS_PRINTK(KERN_WARNING, pci_dev, 7006 "Unable to allocate host adapt & dummy structures\n"); 7007 return ips_abort_init(ha, index); 7008 } 7009 ha->adapt->hw_status_start = dma_address; 7010 ha->dummy = (void *) (ha->adapt + 1); 7011 7012 7013 7014 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address); 7015 if (!ha->logical_drive_info) { 7016 IPS_PRINTK(KERN_WARNING, pci_dev, 7017 "Unable to allocate logical drive info structure\n"); 7018 return ips_abort_init(ha, index); 7019 } 7020 ha->logical_drive_info_dma_addr = dma_address; 7021 7022 7023 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL); 7024 7025 if (!ha->conf) { 7026 IPS_PRINTK(KERN_WARNING, pci_dev, 7027 "Unable to allocate host conf structure\n"); 7028 return ips_abort_init(ha, index); 7029 } 7030 7031 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL); 7032 7033 if (!ha->nvram) { 7034 IPS_PRINTK(KERN_WARNING, pci_dev, 7035 "Unable to allocate host NVRAM structure\n"); 7036 return ips_abort_init(ha, index); 7037 } 7038 7039 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL); 7040 7041 if (!ha->subsys) { 7042 IPS_PRINTK(KERN_WARNING, pci_dev, 7043 "Unable to allocate host subsystem structure\n"); 7044 return ips_abort_init(ha, index); 7045 } 7046 7047 /* the ioctl buffer is now used during adapter initialization, so its 7048 * successful allocation is now required */ 7049 if (ips_ioctlsize < PAGE_SIZE) 7050 ips_ioctlsize = PAGE_SIZE; 7051 7052 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize, 7053 &ha->ioctl_busaddr); 7054 ha->ioctl_len = ips_ioctlsize; 7055 if (!ha->ioctl_data) { 7056 IPS_PRINTK(KERN_WARNING, pci_dev, 7057 "Unable to allocate IOCTL data\n"); 7058 return ips_abort_init(ha, index); 7059 } 7060 7061 /* 7062 * Setup Functions 7063 */ 7064 ips_setup_funclist(ha); 7065 7066 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) { 7067 /* If Morpheus appears dead, reset it */ 7068 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 7069 if (IsDead == 0xDEADBEEF) { 7070 ips_reset_morpheus(ha); 7071 } 7072 } 7073 7074 /* 7075 * Initialize the card if it isn't already 7076 */ 7077 7078 if (!(*ha->func.isinit) (ha)) { 7079 if (!(*ha->func.init) (ha)) { 7080 /* 7081 * Initialization failed 7082 */ 7083 IPS_PRINTK(KERN_WARNING, pci_dev, 7084 "Unable to initialize controller\n"); 7085 return ips_abort_init(ha, index); 7086 } 7087 } 7088 7089 *indexPtr = index; 7090 return SUCCESS; 7091 } 7092 7093 /*---------------------------------------------------------------------------*/ 7094 /* Routine Name: ips_init_phase2 */ 7095 /* */ 7096 /* Routine Description: */ 7097 /* Adapter Initialization Phase 2 */ 7098 /* */ 7099 /* Return Value: */ 7100 /* 0 if Successful, else non-zero */ 7101 /*---------------------------------------------------------------------------*/ 7102 static int 7103 ips_init_phase2(int index) 7104 { 7105 ips_ha_t *ha; 7106 7107 ha = ips_ha[index]; 7108 7109 METHOD_TRACE("ips_init_phase2", 1); 7110 if (!ha->active) { 7111 ips_ha[index] = NULL; 7112 return -1; 7113 } 7114 7115 /* Install the interrupt handler */ 7116 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 7117 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7118 "Unable to install interrupt handler\n"); 7119 return ips_abort_init(ha, index); 7120 } 7121 7122 /* 7123 * Allocate a temporary SCB for initialization 7124 */ 7125 ha->max_cmds = 1; 7126 if (!ips_allocatescbs(ha)) { 7127 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7128 "Unable to allocate a CCB\n"); 7129 free_irq(ha->pcidev->irq, ha); 7130 return ips_abort_init(ha, index); 7131 } 7132 7133 if (!ips_hainit(ha)) { 7134 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7135 "Unable to initialize controller\n"); 7136 free_irq(ha->pcidev->irq, ha); 7137 return ips_abort_init(ha, index); 7138 } 7139 /* Free the temporary SCB */ 7140 ips_deallocatescbs(ha, 1); 7141 7142 /* allocate CCBs */ 7143 if (!ips_allocatescbs(ha)) { 7144 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7145 "Unable to allocate CCBs\n"); 7146 free_irq(ha->pcidev->irq, ha); 7147 return ips_abort_init(ha, index); 7148 } 7149 7150 return SUCCESS; 7151 } 7152 7153 MODULE_LICENSE("GPL"); 7154 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING); 7155 MODULE_VERSION(IPS_VER_STRING); 7156 7157 7158 /* 7159 * Overrides for Emacs so that we almost follow Linus's tabbing style. 7160 * Emacs will notice this stuff at the end of the file and automatically 7161 * adjust the settings for this buffer only. This must remain at the end 7162 * of the file. 7163 * --------------------------------------------------------------------------- 7164 * Local variables: 7165 * c-indent-level: 2 7166 * c-brace-imaginary-offset: 0 7167 * c-brace-offset: -2 7168 * c-argdecl-indent: 2 7169 * c-label-offset: -2 7170 * c-continued-statement-offset: 2 7171 * c-continued-brace-offset: 0 7172 * indent-tabs-mode: nil 7173 * tab-width: 8 7174 * End: 7175 */ 7176