1 /*****************************************************************************/ 2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */ 3 /* */ 4 /* Written By: Keith Mitchell, IBM Corporation */ 5 /* Jack Hammer, Adaptec, Inc. */ 6 /* David Jeffery, Adaptec, Inc. */ 7 /* */ 8 /* Copyright (C) 2000 IBM Corporation */ 9 /* Copyright (C) 2002,2003 Adaptec, Inc. */ 10 /* */ 11 /* This program is free software; you can redistribute it and/or modify */ 12 /* it under the terms of the GNU General Public License as published by */ 13 /* the Free Software Foundation; either version 2 of the License, or */ 14 /* (at your option) any later version. */ 15 /* */ 16 /* This program is distributed in the hope that it will be useful, */ 17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */ 18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ 19 /* GNU General Public License for more details. */ 20 /* */ 21 /* NO WARRANTY */ 22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ 23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ 24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ 25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ 26 /* solely responsible for determining the appropriateness of using and */ 27 /* distributing the Program and assumes all risks associated with its */ 28 /* exercise of rights under this Agreement, including but not limited to */ 29 /* the risks and costs of program errors, damage to or loss of data, */ 30 /* programs or equipment, and unavailability or interruption of operations. */ 31 /* */ 32 /* DISCLAIMER OF LIABILITY */ 33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ 34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ 35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ 36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ 37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ 38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ 39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ 40 /* */ 41 /* You should have received a copy of the GNU General Public License */ 42 /* along with this program; if not, write to the Free Software */ 43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ 44 /* */ 45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */ 46 /* ipslinux@adaptec.com */ 47 /* */ 48 /* For system support issues, contact your local IBM Customer support. */ 49 /* Directions to find IBM Customer Support for each country can be found at: */ 50 /* http://www.ibm.com/planetwide/ */ 51 /* */ 52 /*****************************************************************************/ 53 54 /*****************************************************************************/ 55 /* Change Log */ 56 /* */ 57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */ 58 /* 0.99.03 - Make interrupt routine handle all completed request on the */ 59 /* adapter not just the first one */ 60 /* - Make sure passthru commands get woken up if we run out of */ 61 /* SCBs */ 62 /* - Send all of the commands on the queue at once rather than */ 63 /* one at a time since the card will support it. */ 64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */ 65 /* the interface to the utilities to change */ 66 /* - Fix error recovery code */ 67 /* 0.99.05 - Fix an oops when we get certain passthru commands */ 68 /* 1.00.00 - Initial Public Release */ 69 /* Functionally equivalent to 0.99.05 */ 70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */ 71 /* - Change version to 3.60 to coincide with release numbering. */ 72 /* 3.60.01 - Remove bogus error check in passthru routine */ 73 /* 3.60.02 - Make DCDB direction based on lookup table */ 74 /* - Only allow one DCDB command to a SCSI ID at a time */ 75 /* 4.00.00 - Add support for ServeRAID 4 */ 76 /* 4.00.01 - Add support for First Failure Data Capture */ 77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */ 78 /* 4.00.03 - Add alternative passthru interface */ 79 /* - Add ability to flash BIOS */ 80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */ 81 /* 4.00.05 - Remove wish_block from init routine */ 82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */ 83 /* 2.3.18 and later */ 84 /* - Sync with other changes from the 2.3 kernels */ 85 /* 4.00.06 - Fix timeout with initial FFDC command */ 86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */ 87 /* 4.10.00 - Add support for ServeRAID 4M/4L */ 88 /* 4.10.13 - Fix for dynamic unload and proc file system */ 89 /* 4.20.03 - Rename version to coincide with new release schedules */ 90 /* Performance fixes */ 91 /* Fix truncation of /proc files with cat */ 92 /* Merge in changes through kernel 2.4.0test1ac21 */ 93 /* 4.20.13 - Fix some failure cases / reset code */ 94 /* - Hook into the reboot_notifier to flush the controller cache */ 95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */ 96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */ 97 /* - Add IPSSEND Flash Support */ 98 /* - Set Sense Data for Unknown SCSI Command */ 99 /* - Use Slot Number from NVRAM Page 5 */ 100 /* - Restore caller's DCDB Structure */ 101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/ 102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */ 103 /* - Don't release HA Lock in ips_next() until SC taken off queue */ 104 /* - Unregister SCSI device in ips_release() */ 105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */ 106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */ 107 /* Code Clean-Up for 2.4.x kernel */ 108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */ 109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */ 110 /* - Don't Issue Internal FFDC Command if there are Active Commands */ 111 /* - Close Window for getting too many IOCTL's active */ 112 /* 4.80.00 - Make ia64 Safe */ 113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */ 114 /* - Adjustments to Device Queue Depth */ 115 /* 4.80.14 - Take all semaphores off stack */ 116 /* - Clean Up New_IOCTL path */ 117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */ 118 /* - 5 second delay needed after resetting an i960 adapter */ 119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */ 120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */ 121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */ 122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */ 123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */ 124 /* 4.90.11 - Don't actually RESET unless it's physically required */ 125 /* - Remove unused compile options */ 126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */ 127 /* - Get rid on IOCTL_NEW_COMMAND code */ 128 /* - Add Extended DCDB Commands for Tape Support in 5I */ 129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */ 130 /* 5.10.15 - remove unused code (sem, macros, etc.) */ 131 /* 5.30.00 - use __devexit_p() */ 132 /* 6.00.00 - Add 6x Adapters and Battery Flash */ 133 /* 6.10.00 - Remove 1G Addressing Limitations */ 134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */ 135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */ 136 /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */ 137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */ 138 /* - Fix sort order of 7k */ 139 /* - Remove 3 unused "inline" functions */ 140 /* 7.12.xx - Use STATIC functions wherever possible */ 141 /* - Clean up deprecated MODULE_PARM calls */ 142 /* 7.12.05 - Remove Version Matching per IBM request */ 143 /*****************************************************************************/ 144 145 /* 146 * Conditional Compilation directives for this driver: 147 * 148 * IPS_DEBUG - Turn on debugging info 149 * 150 * Parameters: 151 * 152 * debug:<number> - Set debug level to <number> 153 * NOTE: only works when IPS_DEBUG compile directive is used. 154 * 1 - Normal debug messages 155 * 2 - Verbose debug messages 156 * 11 - Method trace (non interrupt) 157 * 12 - Method trace (includes interrupt) 158 * 159 * noi2o - Don't use I2O Queues (ServeRAID 4 only) 160 * nommap - Don't use memory mapped I/O 161 * ioctlsize - Initial size of the IOCTL buffer 162 */ 163 164 #include <asm/io.h> 165 #include <asm/byteorder.h> 166 #include <asm/page.h> 167 #include <linux/stddef.h> 168 #include <linux/string.h> 169 #include <linux/errno.h> 170 #include <linux/kernel.h> 171 #include <linux/ioport.h> 172 #include <linux/slab.h> 173 #include <linux/delay.h> 174 #include <linux/pci.h> 175 #include <linux/proc_fs.h> 176 #include <linux/reboot.h> 177 #include <linux/interrupt.h> 178 179 #include <linux/blkdev.h> 180 #include <linux/types.h> 181 #include <linux/dma-mapping.h> 182 183 #include <scsi/sg.h> 184 #include "scsi.h" 185 #include <scsi/scsi_host.h> 186 187 #include "ips.h" 188 189 #include <linux/module.h> 190 191 #include <linux/stat.h> 192 193 #include <linux/spinlock.h> 194 #include <linux/init.h> 195 196 #include <linux/smp.h> 197 198 #ifdef MODULE 199 static char *ips = NULL; 200 module_param(ips, charp, 0); 201 #endif 202 203 /* 204 * DRIVER_VER 205 */ 206 #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING 207 #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " " 208 209 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \ 210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \ 211 DMA_BIDIRECTIONAL : \ 212 scb->scsi_cmd->sc_data_direction) 213 214 #ifdef IPS_DEBUG 215 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n"); 216 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n"); 217 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v); 218 #else 219 #define METHOD_TRACE(s, i) 220 #define DEBUG(i, s) 221 #define DEBUG_VAR(i, s, v...) 222 #endif 223 224 /* 225 * Function prototypes 226 */ 227 static int ips_eh_abort(struct scsi_cmnd *); 228 static int ips_eh_reset(struct scsi_cmnd *); 229 static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *); 230 static const char *ips_info(struct Scsi_Host *); 231 static irqreturn_t do_ipsintr(int, void *); 232 static int ips_hainit(ips_ha_t *); 233 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *); 234 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int); 235 static int ips_send_cmd(ips_ha_t *, ips_scb_t *); 236 static int ips_online(ips_ha_t *, ips_scb_t *); 237 static int ips_inquiry(ips_ha_t *, ips_scb_t *); 238 static int ips_rdcap(ips_ha_t *, ips_scb_t *); 239 static int ips_msense(ips_ha_t *, ips_scb_t *); 240 static int ips_reqsen(ips_ha_t *, ips_scb_t *); 241 static int ips_deallocatescbs(ips_ha_t *, int); 242 static int ips_allocatescbs(ips_ha_t *); 243 static int ips_reset_copperhead(ips_ha_t *); 244 static int ips_reset_copperhead_memio(ips_ha_t *); 245 static int ips_reset_morpheus(ips_ha_t *); 246 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *); 247 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *); 248 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *); 249 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *); 250 static int ips_isintr_copperhead(ips_ha_t *); 251 static int ips_isintr_copperhead_memio(ips_ha_t *); 252 static int ips_isintr_morpheus(ips_ha_t *); 253 static int ips_wait(ips_ha_t *, int, int); 254 static int ips_write_driver_status(ips_ha_t *, int); 255 static int ips_read_adapter_status(ips_ha_t *, int); 256 static int ips_read_subsystem_parameters(ips_ha_t *, int); 257 static int ips_read_config(ips_ha_t *, int); 258 static int ips_clear_adapter(ips_ha_t *, int); 259 static int ips_readwrite_page5(ips_ha_t *, int, int); 260 static int ips_init_copperhead(ips_ha_t *); 261 static int ips_init_copperhead_memio(ips_ha_t *); 262 static int ips_init_morpheus(ips_ha_t *); 263 static int ips_isinit_copperhead(ips_ha_t *); 264 static int ips_isinit_copperhead_memio(ips_ha_t *); 265 static int ips_isinit_morpheus(ips_ha_t *); 266 static int ips_erase_bios(ips_ha_t *); 267 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); 268 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); 269 static int ips_erase_bios_memio(ips_ha_t *); 270 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 271 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 272 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 273 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 274 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 275 static void ips_free_flash_copperhead(ips_ha_t * ha); 276 static void ips_get_bios_version(ips_ha_t *, int); 277 static void ips_identify_controller(ips_ha_t *); 278 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *); 279 static void ips_enable_int_copperhead(ips_ha_t *); 280 static void ips_enable_int_copperhead_memio(ips_ha_t *); 281 static void ips_enable_int_morpheus(ips_ha_t *); 282 static int ips_intr_copperhead(ips_ha_t *); 283 static int ips_intr_morpheus(ips_ha_t *); 284 static void ips_next(ips_ha_t *, int); 285 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *); 286 static void ipsintr_done(ips_ha_t *, struct ips_scb *); 287 static void ips_done(ips_ha_t *, ips_scb_t *); 288 static void ips_free(ips_ha_t *); 289 static void ips_init_scb(ips_ha_t *, ips_scb_t *); 290 static void ips_freescb(ips_ha_t *, ips_scb_t *); 291 static void ips_setup_funclist(ips_ha_t *); 292 static void ips_statinit(ips_ha_t *); 293 static void ips_statinit_memio(ips_ha_t *); 294 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t); 295 static void ips_ffdc_reset(ips_ha_t *, int); 296 static void ips_ffdc_time(ips_ha_t *); 297 static uint32_t ips_statupd_copperhead(ips_ha_t *); 298 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); 299 static uint32_t ips_statupd_morpheus(ips_ha_t *); 300 static ips_scb_t *ips_getscb(ips_ha_t *); 301 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *); 302 static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *); 303 static void ips_putq_copp_tail(ips_copp_queue_t *, 304 ips_copp_wait_item_t *); 305 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *); 306 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *); 307 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *); 308 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *, 309 struct scsi_cmnd *); 310 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *, 311 ips_copp_wait_item_t *); 312 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *); 313 314 static int ips_is_passthru(struct scsi_cmnd *); 315 static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int); 316 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 317 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *); 318 static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data, 319 unsigned int count); 320 static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data, 321 unsigned int count); 322 323 static int ips_write_info(struct Scsi_Host *, char *, int); 324 static int ips_show_info(struct seq_file *, struct Scsi_Host *); 325 static int ips_host_info(ips_ha_t *, struct seq_file *); 326 static int ips_abort_init(ips_ha_t * ha, int index); 327 static int ips_init_phase2(int index); 328 329 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr); 330 static int ips_register_scsi(int index); 331 332 static int ips_poll_for_flush_complete(ips_ha_t * ha); 333 static void ips_flush_and_reset(ips_ha_t *ha); 334 335 /* 336 * global variables 337 */ 338 static const char ips_name[] = "ips"; 339 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */ 340 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */ 341 static unsigned int ips_next_controller; 342 static unsigned int ips_num_controllers; 343 static unsigned int ips_released_controllers; 344 static int ips_hotplug; 345 static int ips_cmd_timeout = 60; 346 static int ips_reset_timeout = 60 * 5; 347 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */ 348 static int ips_force_i2o = 1; /* Always use I2O command delivery */ 349 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */ 350 static int ips_cd_boot; /* Booting from Manager CD */ 351 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */ 352 static dma_addr_t ips_flashbusaddr; 353 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */ 354 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ 355 static struct scsi_host_template ips_driver_template = { 356 .info = ips_info, 357 .queuecommand = ips_queue, 358 .eh_abort_handler = ips_eh_abort, 359 .eh_host_reset_handler = ips_eh_reset, 360 .proc_name = "ips", 361 .show_info = ips_show_info, 362 .write_info = ips_write_info, 363 .slave_configure = ips_slave_configure, 364 .bios_param = ips_biosparam, 365 .this_id = -1, 366 .sg_tablesize = IPS_MAX_SG, 367 .cmd_per_lun = 3, 368 .use_clustering = ENABLE_CLUSTERING, 369 .no_write_same = 1, 370 }; 371 372 373 /* This table describes all ServeRAID Adapters */ 374 static struct pci_device_id ips_pci_table[] = { 375 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 376 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 377 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 378 { 0, } 379 }; 380 381 MODULE_DEVICE_TABLE( pci, ips_pci_table ); 382 383 static char ips_hot_plug_name[] = "ips"; 384 385 static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); 386 static void ips_remove_device(struct pci_dev *pci_dev); 387 388 static struct pci_driver ips_pci_driver = { 389 .name = ips_hot_plug_name, 390 .id_table = ips_pci_table, 391 .probe = ips_insert_device, 392 .remove = ips_remove_device, 393 }; 394 395 396 /* 397 * Necessary forward function protoypes 398 */ 399 static int ips_halt(struct notifier_block *nb, ulong event, void *buf); 400 401 #define MAX_ADAPTER_NAME 15 402 403 static char ips_adapter_name[][30] = { 404 "ServeRAID", 405 "ServeRAID II", 406 "ServeRAID on motherboard", 407 "ServeRAID on motherboard", 408 "ServeRAID 3H", 409 "ServeRAID 3L", 410 "ServeRAID 4H", 411 "ServeRAID 4M", 412 "ServeRAID 4L", 413 "ServeRAID 4Mx", 414 "ServeRAID 4Lx", 415 "ServeRAID 5i", 416 "ServeRAID 5i", 417 "ServeRAID 6M", 418 "ServeRAID 6i", 419 "ServeRAID 7t", 420 "ServeRAID 7k", 421 "ServeRAID 7M" 422 }; 423 424 static struct notifier_block ips_notifier = { 425 ips_halt, NULL, 0 426 }; 427 428 /* 429 * Direction table 430 */ 431 static char ips_command_direction[] = { 432 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, 433 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, 434 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 435 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 436 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT, 437 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 438 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN, 439 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 440 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK, 441 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 442 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, 443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 444 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, 445 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE, 446 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, 447 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 448 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 449 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 450 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 451 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 453 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 454 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 465 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE, 466 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT, 467 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE, 468 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, 469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT, 479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK 483 }; 484 485 486 /****************************************************************************/ 487 /* */ 488 /* Routine Name: ips_setup */ 489 /* */ 490 /* Routine Description: */ 491 /* */ 492 /* setup parameters to the driver */ 493 /* */ 494 /****************************************************************************/ 495 static int 496 ips_setup(char *ips_str) 497 { 498 499 int i; 500 char *key; 501 char *value; 502 IPS_OPTION options[] = { 503 {"noi2o", &ips_force_i2o, 0}, 504 {"nommap", &ips_force_memio, 0}, 505 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE}, 506 {"cdboot", &ips_cd_boot, 0}, 507 {"maxcmds", &MaxLiteCmds, 32}, 508 }; 509 510 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */ 511 /* Search for value */ 512 while ((key = strsep(&ips_str, ",."))) { 513 if (!*key) 514 continue; 515 value = strchr(key, ':'); 516 if (value) 517 *value++ = '\0'; 518 /* 519 * We now have key/value pairs. 520 * Update the variables 521 */ 522 for (i = 0; i < ARRAY_SIZE(options); i++) { 523 if (strncasecmp 524 (key, options[i].option_name, 525 strlen(options[i].option_name)) == 0) { 526 if (value) 527 *options[i].option_flag = 528 simple_strtoul(value, NULL, 0); 529 else 530 *options[i].option_flag = 531 options[i].option_value; 532 break; 533 } 534 } 535 } 536 537 return (1); 538 } 539 540 __setup("ips=", ips_setup); 541 542 /****************************************************************************/ 543 /* */ 544 /* Routine Name: ips_detect */ 545 /* */ 546 /* Routine Description: */ 547 /* */ 548 /* Detect and initialize the driver */ 549 /* */ 550 /* NOTE: this routine is called under the io_request_lock spinlock */ 551 /* */ 552 /****************************************************************************/ 553 static int 554 ips_detect(struct scsi_host_template * SHT) 555 { 556 int i; 557 558 METHOD_TRACE("ips_detect", 1); 559 560 #ifdef MODULE 561 if (ips) 562 ips_setup(ips); 563 #endif 564 565 for (i = 0; i < ips_num_controllers; i++) { 566 if (ips_register_scsi(i)) 567 ips_free(ips_ha[i]); 568 ips_released_controllers++; 569 } 570 ips_hotplug = 1; 571 return (ips_num_controllers); 572 } 573 574 /****************************************************************************/ 575 /* configure the function pointers to use the functions that will work */ 576 /* with the found version of the adapter */ 577 /****************************************************************************/ 578 static void 579 ips_setup_funclist(ips_ha_t * ha) 580 { 581 582 /* 583 * Setup Functions 584 */ 585 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { 586 /* morpheus / marco / sebring */ 587 ha->func.isintr = ips_isintr_morpheus; 588 ha->func.isinit = ips_isinit_morpheus; 589 ha->func.issue = ips_issue_i2o_memio; 590 ha->func.init = ips_init_morpheus; 591 ha->func.statupd = ips_statupd_morpheus; 592 ha->func.reset = ips_reset_morpheus; 593 ha->func.intr = ips_intr_morpheus; 594 ha->func.enableint = ips_enable_int_morpheus; 595 } else if (IPS_USE_MEMIO(ha)) { 596 /* copperhead w/MEMIO */ 597 ha->func.isintr = ips_isintr_copperhead_memio; 598 ha->func.isinit = ips_isinit_copperhead_memio; 599 ha->func.init = ips_init_copperhead_memio; 600 ha->func.statupd = ips_statupd_copperhead_memio; 601 ha->func.statinit = ips_statinit_memio; 602 ha->func.reset = ips_reset_copperhead_memio; 603 ha->func.intr = ips_intr_copperhead; 604 ha->func.erasebios = ips_erase_bios_memio; 605 ha->func.programbios = ips_program_bios_memio; 606 ha->func.verifybios = ips_verify_bios_memio; 607 ha->func.enableint = ips_enable_int_copperhead_memio; 608 if (IPS_USE_I2O_DELIVER(ha)) 609 ha->func.issue = ips_issue_i2o_memio; 610 else 611 ha->func.issue = ips_issue_copperhead_memio; 612 } else { 613 /* copperhead */ 614 ha->func.isintr = ips_isintr_copperhead; 615 ha->func.isinit = ips_isinit_copperhead; 616 ha->func.init = ips_init_copperhead; 617 ha->func.statupd = ips_statupd_copperhead; 618 ha->func.statinit = ips_statinit; 619 ha->func.reset = ips_reset_copperhead; 620 ha->func.intr = ips_intr_copperhead; 621 ha->func.erasebios = ips_erase_bios; 622 ha->func.programbios = ips_program_bios; 623 ha->func.verifybios = ips_verify_bios; 624 ha->func.enableint = ips_enable_int_copperhead; 625 626 if (IPS_USE_I2O_DELIVER(ha)) 627 ha->func.issue = ips_issue_i2o; 628 else 629 ha->func.issue = ips_issue_copperhead; 630 } 631 } 632 633 /****************************************************************************/ 634 /* */ 635 /* Routine Name: ips_release */ 636 /* */ 637 /* Routine Description: */ 638 /* */ 639 /* Remove a driver */ 640 /* */ 641 /****************************************************************************/ 642 static int 643 ips_release(struct Scsi_Host *sh) 644 { 645 ips_scb_t *scb; 646 ips_ha_t *ha; 647 int i; 648 649 METHOD_TRACE("ips_release", 1); 650 651 scsi_remove_host(sh); 652 653 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ; 654 655 if (i == IPS_MAX_ADAPTERS) { 656 printk(KERN_WARNING 657 "(%s) release, invalid Scsi_Host pointer.\n", ips_name); 658 BUG(); 659 return (FALSE); 660 } 661 662 ha = IPS_HA(sh); 663 664 if (!ha) 665 return (FALSE); 666 667 /* flush the cache on the controller */ 668 scb = &ha->scbs[ha->max_cmds - 1]; 669 670 ips_init_scb(ha, scb); 671 672 scb->timeout = ips_cmd_timeout; 673 scb->cdb[0] = IPS_CMD_FLUSH; 674 675 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 676 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 677 scb->cmd.flush_cache.state = IPS_NORM_STATE; 678 scb->cmd.flush_cache.reserved = 0; 679 scb->cmd.flush_cache.reserved2 = 0; 680 scb->cmd.flush_cache.reserved3 = 0; 681 scb->cmd.flush_cache.reserved4 = 0; 682 683 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 684 685 /* send command */ 686 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE) 687 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n"); 688 689 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n"); 690 691 ips_sh[i] = NULL; 692 ips_ha[i] = NULL; 693 694 /* free extra memory */ 695 ips_free(ha); 696 697 /* free IRQ */ 698 free_irq(ha->pcidev->irq, ha); 699 700 scsi_host_put(sh); 701 702 ips_released_controllers++; 703 704 return (FALSE); 705 } 706 707 /****************************************************************************/ 708 /* */ 709 /* Routine Name: ips_halt */ 710 /* */ 711 /* Routine Description: */ 712 /* */ 713 /* Perform cleanup when the system reboots */ 714 /* */ 715 /****************************************************************************/ 716 static int 717 ips_halt(struct notifier_block *nb, ulong event, void *buf) 718 { 719 ips_scb_t *scb; 720 ips_ha_t *ha; 721 int i; 722 723 if ((event != SYS_RESTART) && (event != SYS_HALT) && 724 (event != SYS_POWER_OFF)) 725 return (NOTIFY_DONE); 726 727 for (i = 0; i < ips_next_controller; i++) { 728 ha = (ips_ha_t *) ips_ha[i]; 729 730 if (!ha) 731 continue; 732 733 if (!ha->active) 734 continue; 735 736 /* flush the cache on the controller */ 737 scb = &ha->scbs[ha->max_cmds - 1]; 738 739 ips_init_scb(ha, scb); 740 741 scb->timeout = ips_cmd_timeout; 742 scb->cdb[0] = IPS_CMD_FLUSH; 743 744 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 745 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 746 scb->cmd.flush_cache.state = IPS_NORM_STATE; 747 scb->cmd.flush_cache.reserved = 0; 748 scb->cmd.flush_cache.reserved2 = 0; 749 scb->cmd.flush_cache.reserved3 = 0; 750 scb->cmd.flush_cache.reserved4 = 0; 751 752 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 753 754 /* send command */ 755 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == 756 IPS_FAILURE) 757 IPS_PRINTK(KERN_WARNING, ha->pcidev, 758 "Incomplete Flush.\n"); 759 else 760 IPS_PRINTK(KERN_WARNING, ha->pcidev, 761 "Flushing Complete.\n"); 762 } 763 764 return (NOTIFY_OK); 765 } 766 767 /****************************************************************************/ 768 /* */ 769 /* Routine Name: ips_eh_abort */ 770 /* */ 771 /* Routine Description: */ 772 /* */ 773 /* Abort a command (using the new error code stuff) */ 774 /* Note: this routine is called under the io_request_lock */ 775 /****************************************************************************/ 776 int ips_eh_abort(struct scsi_cmnd *SC) 777 { 778 ips_ha_t *ha; 779 ips_copp_wait_item_t *item; 780 int ret; 781 struct Scsi_Host *host; 782 783 METHOD_TRACE("ips_eh_abort", 1); 784 785 if (!SC) 786 return (FAILED); 787 788 host = SC->device->host; 789 ha = (ips_ha_t *) SC->device->host->hostdata; 790 791 if (!ha) 792 return (FAILED); 793 794 if (!ha->active) 795 return (FAILED); 796 797 spin_lock(host->host_lock); 798 799 /* See if the command is on the copp queue */ 800 item = ha->copp_waitlist.head; 801 while ((item) && (item->scsi_cmd != SC)) 802 item = item->next; 803 804 if (item) { 805 /* Found it */ 806 ips_removeq_copp(&ha->copp_waitlist, item); 807 ret = (SUCCESS); 808 809 /* See if the command is on the wait queue */ 810 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 811 /* command not sent yet */ 812 ret = (SUCCESS); 813 } else { 814 /* command must have already been sent */ 815 ret = (FAILED); 816 } 817 818 spin_unlock(host->host_lock); 819 return ret; 820 } 821 822 /****************************************************************************/ 823 /* */ 824 /* Routine Name: ips_eh_reset */ 825 /* */ 826 /* Routine Description: */ 827 /* */ 828 /* Reset the controller (with new eh error code) */ 829 /* */ 830 /* NOTE: this routine is called under the io_request_lock spinlock */ 831 /* */ 832 /****************************************************************************/ 833 static int __ips_eh_reset(struct scsi_cmnd *SC) 834 { 835 int ret; 836 int i; 837 ips_ha_t *ha; 838 ips_scb_t *scb; 839 ips_copp_wait_item_t *item; 840 841 METHOD_TRACE("ips_eh_reset", 1); 842 843 #ifdef NO_IPS_RESET 844 return (FAILED); 845 #else 846 847 if (!SC) { 848 DEBUG(1, "Reset called with NULL scsi command"); 849 850 return (FAILED); 851 } 852 853 ha = (ips_ha_t *) SC->device->host->hostdata; 854 855 if (!ha) { 856 DEBUG(1, "Reset called with NULL ha struct"); 857 858 return (FAILED); 859 } 860 861 if (!ha->active) 862 return (FAILED); 863 864 /* See if the command is on the copp queue */ 865 item = ha->copp_waitlist.head; 866 while ((item) && (item->scsi_cmd != SC)) 867 item = item->next; 868 869 if (item) { 870 /* Found it */ 871 ips_removeq_copp(&ha->copp_waitlist, item); 872 return (SUCCESS); 873 } 874 875 /* See if the command is on the wait queue */ 876 if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 877 /* command not sent yet */ 878 return (SUCCESS); 879 } 880 881 /* An explanation for the casual observer: */ 882 /* Part of the function of a RAID controller is automatic error */ 883 /* detection and recovery. As such, the only problem that physically */ 884 /* resetting an adapter will ever fix is when, for some reason, */ 885 /* the driver is not successfully communicating with the adapter. */ 886 /* Therefore, we will attempt to flush this adapter. If that succeeds, */ 887 /* then there's no real purpose in a physical reset. This will complete */ 888 /* much faster and avoids any problems that might be caused by a */ 889 /* physical reset ( such as having to fail all the outstanding I/O's ). */ 890 891 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */ 892 scb = &ha->scbs[ha->max_cmds - 1]; 893 894 ips_init_scb(ha, scb); 895 896 scb->timeout = ips_cmd_timeout; 897 scb->cdb[0] = IPS_CMD_FLUSH; 898 899 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 900 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 901 scb->cmd.flush_cache.state = IPS_NORM_STATE; 902 scb->cmd.flush_cache.reserved = 0; 903 scb->cmd.flush_cache.reserved2 = 0; 904 scb->cmd.flush_cache.reserved3 = 0; 905 scb->cmd.flush_cache.reserved4 = 0; 906 907 /* Attempt the flush command */ 908 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL); 909 if (ret == IPS_SUCCESS) { 910 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 911 "Reset Request - Flushed Cache\n"); 912 return (SUCCESS); 913 } 914 } 915 916 /* Either we can't communicate with the adapter or it's an IOCTL request */ 917 /* from a utility. A physical reset is needed at this point. */ 918 919 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */ 920 921 /* 922 * command must have already been sent 923 * reset the controller 924 */ 925 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n"); 926 ret = (*ha->func.reset) (ha); 927 928 if (!ret) { 929 struct scsi_cmnd *scsi_cmd; 930 931 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 932 "Controller reset failed - controller now offline.\n"); 933 934 /* Now fail all of the active commands */ 935 DEBUG_VAR(1, "(%s%d) Failing active commands", 936 ips_name, ha->host_num); 937 938 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 939 scb->scsi_cmd->result = DID_ERROR << 16; 940 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 941 ips_freescb(ha, scb); 942 } 943 944 /* Now fail all of the pending commands */ 945 DEBUG_VAR(1, "(%s%d) Failing pending commands", 946 ips_name, ha->host_num); 947 948 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 949 scsi_cmd->result = DID_ERROR; 950 scsi_cmd->scsi_done(scsi_cmd); 951 } 952 953 ha->active = FALSE; 954 return (FAILED); 955 } 956 957 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) { 958 struct scsi_cmnd *scsi_cmd; 959 960 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 961 "Controller reset failed - controller now offline.\n"); 962 963 /* Now fail all of the active commands */ 964 DEBUG_VAR(1, "(%s%d) Failing active commands", 965 ips_name, ha->host_num); 966 967 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 968 scb->scsi_cmd->result = DID_ERROR << 16; 969 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 970 ips_freescb(ha, scb); 971 } 972 973 /* Now fail all of the pending commands */ 974 DEBUG_VAR(1, "(%s%d) Failing pending commands", 975 ips_name, ha->host_num); 976 977 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 978 scsi_cmd->result = DID_ERROR << 16; 979 scsi_cmd->scsi_done(scsi_cmd); 980 } 981 982 ha->active = FALSE; 983 return (FAILED); 984 } 985 986 /* FFDC */ 987 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) { 988 ha->last_ffdc = ktime_get_real_seconds(); 989 ha->reset_count++; 990 ips_ffdc_reset(ha, IPS_INTR_IORL); 991 } 992 993 /* Now fail all of the active commands */ 994 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num); 995 996 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 997 scb->scsi_cmd->result = DID_RESET << 16; 998 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 999 ips_freescb(ha, scb); 1000 } 1001 1002 /* Reset DCDB active command bits */ 1003 for (i = 1; i < ha->nbus; i++) 1004 ha->dcdb_active[i - 1] = 0; 1005 1006 /* Reset the number of active IOCTLs */ 1007 ha->num_ioctl = 0; 1008 1009 ips_next(ha, IPS_INTR_IORL); 1010 1011 return (SUCCESS); 1012 #endif /* NO_IPS_RESET */ 1013 1014 } 1015 1016 static int ips_eh_reset(struct scsi_cmnd *SC) 1017 { 1018 int rc; 1019 1020 spin_lock_irq(SC->device->host->host_lock); 1021 rc = __ips_eh_reset(SC); 1022 spin_unlock_irq(SC->device->host->host_lock); 1023 1024 return rc; 1025 } 1026 1027 /****************************************************************************/ 1028 /* */ 1029 /* Routine Name: ips_queue */ 1030 /* */ 1031 /* Routine Description: */ 1032 /* */ 1033 /* Send a command to the controller */ 1034 /* */ 1035 /* NOTE: */ 1036 /* Linux obtains io_request_lock before calling this function */ 1037 /* */ 1038 /****************************************************************************/ 1039 static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *)) 1040 { 1041 ips_ha_t *ha; 1042 ips_passthru_t *pt; 1043 1044 METHOD_TRACE("ips_queue", 1); 1045 1046 ha = (ips_ha_t *) SC->device->host->hostdata; 1047 1048 if (!ha) 1049 return (1); 1050 1051 if (!ha->active) 1052 return (DID_ERROR); 1053 1054 if (ips_is_passthru(SC)) { 1055 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) { 1056 SC->result = DID_BUS_BUSY << 16; 1057 done(SC); 1058 1059 return (0); 1060 } 1061 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) { 1062 SC->result = DID_BUS_BUSY << 16; 1063 done(SC); 1064 1065 return (0); 1066 } 1067 1068 SC->scsi_done = done; 1069 1070 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)", 1071 ips_name, 1072 ha->host_num, 1073 SC->cmnd[0], 1074 SC->device->channel, SC->device->id, SC->device->lun); 1075 1076 /* Check for command to initiator IDs */ 1077 if ((scmd_channel(SC) > 0) 1078 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) { 1079 SC->result = DID_NO_CONNECT << 16; 1080 done(SC); 1081 1082 return (0); 1083 } 1084 1085 if (ips_is_passthru(SC)) { 1086 1087 ips_copp_wait_item_t *scratch; 1088 1089 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */ 1090 /* There can never be any system activity ( network or disk ), but check */ 1091 /* anyway just as a good practice. */ 1092 pt = (ips_passthru_t *) scsi_sglist(SC); 1093 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) && 1094 (pt->CoppCP.cmd.reset.adapter_flag == 1)) { 1095 if (ha->scb_activelist.count != 0) { 1096 SC->result = DID_BUS_BUSY << 16; 1097 done(SC); 1098 return (0); 1099 } 1100 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */ 1101 __ips_eh_reset(SC); 1102 SC->result = DID_OK << 16; 1103 SC->scsi_done(SC); 1104 return (0); 1105 } 1106 1107 /* allocate space for the scribble */ 1108 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC); 1109 1110 if (!scratch) { 1111 SC->result = DID_ERROR << 16; 1112 done(SC); 1113 1114 return (0); 1115 } 1116 1117 scratch->scsi_cmd = SC; 1118 scratch->next = NULL; 1119 1120 ips_putq_copp_tail(&ha->copp_waitlist, scratch); 1121 } else { 1122 ips_putq_wait_tail(&ha->scb_waitlist, SC); 1123 } 1124 1125 ips_next(ha, IPS_INTR_IORL); 1126 1127 return (0); 1128 } 1129 1130 static DEF_SCSI_QCMD(ips_queue) 1131 1132 /****************************************************************************/ 1133 /* */ 1134 /* Routine Name: ips_biosparam */ 1135 /* */ 1136 /* Routine Description: */ 1137 /* */ 1138 /* Set bios geometry for the controller */ 1139 /* */ 1140 /****************************************************************************/ 1141 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, 1142 sector_t capacity, int geom[]) 1143 { 1144 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata; 1145 int heads; 1146 int sectors; 1147 int cylinders; 1148 1149 METHOD_TRACE("ips_biosparam", 1); 1150 1151 if (!ha) 1152 /* ?!?! host adater info invalid */ 1153 return (0); 1154 1155 if (!ha->active) 1156 return (0); 1157 1158 if (!ips_read_adapter_status(ha, IPS_INTR_ON)) 1159 /* ?!?! Enquiry command failed */ 1160 return (0); 1161 1162 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) { 1163 heads = IPS_NORM_HEADS; 1164 sectors = IPS_NORM_SECTORS; 1165 } else { 1166 heads = IPS_COMP_HEADS; 1167 sectors = IPS_COMP_SECTORS; 1168 } 1169 1170 cylinders = (unsigned long) capacity / (heads * sectors); 1171 1172 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d", 1173 heads, sectors, cylinders); 1174 1175 geom[0] = heads; 1176 geom[1] = sectors; 1177 geom[2] = cylinders; 1178 1179 return (0); 1180 } 1181 1182 /****************************************************************************/ 1183 /* */ 1184 /* Routine Name: ips_slave_configure */ 1185 /* */ 1186 /* Routine Description: */ 1187 /* */ 1188 /* Set queue depths on devices once scan is complete */ 1189 /* */ 1190 /****************************************************************************/ 1191 static int 1192 ips_slave_configure(struct scsi_device * SDptr) 1193 { 1194 ips_ha_t *ha; 1195 int min; 1196 1197 ha = IPS_HA(SDptr->host); 1198 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) { 1199 min = ha->max_cmds / 2; 1200 if (ha->enq->ucLogDriveCount <= 2) 1201 min = ha->max_cmds - 1; 1202 scsi_change_queue_depth(SDptr, min); 1203 } 1204 1205 SDptr->skip_ms_page_8 = 1; 1206 SDptr->skip_ms_page_3f = 1; 1207 return 0; 1208 } 1209 1210 /****************************************************************************/ 1211 /* */ 1212 /* Routine Name: do_ipsintr */ 1213 /* */ 1214 /* Routine Description: */ 1215 /* */ 1216 /* Wrapper for the interrupt handler */ 1217 /* */ 1218 /****************************************************************************/ 1219 static irqreturn_t 1220 do_ipsintr(int irq, void *dev_id) 1221 { 1222 ips_ha_t *ha; 1223 struct Scsi_Host *host; 1224 int irqstatus; 1225 1226 METHOD_TRACE("do_ipsintr", 2); 1227 1228 ha = (ips_ha_t *) dev_id; 1229 if (!ha) 1230 return IRQ_NONE; 1231 host = ips_sh[ha->host_num]; 1232 /* interrupt during initialization */ 1233 if (!host) { 1234 (*ha->func.intr) (ha); 1235 return IRQ_HANDLED; 1236 } 1237 1238 spin_lock(host->host_lock); 1239 1240 if (!ha->active) { 1241 spin_unlock(host->host_lock); 1242 return IRQ_HANDLED; 1243 } 1244 1245 irqstatus = (*ha->func.intr) (ha); 1246 1247 spin_unlock(host->host_lock); 1248 1249 /* start the next command */ 1250 ips_next(ha, IPS_INTR_ON); 1251 return IRQ_RETVAL(irqstatus); 1252 } 1253 1254 /****************************************************************************/ 1255 /* */ 1256 /* Routine Name: ips_intr_copperhead */ 1257 /* */ 1258 /* Routine Description: */ 1259 /* */ 1260 /* Polling interrupt handler */ 1261 /* */ 1262 /* ASSUMES interrupts are disabled */ 1263 /* */ 1264 /****************************************************************************/ 1265 int 1266 ips_intr_copperhead(ips_ha_t * ha) 1267 { 1268 ips_stat_t *sp; 1269 ips_scb_t *scb; 1270 IPS_STATUS cstatus; 1271 int intrstatus; 1272 1273 METHOD_TRACE("ips_intr", 2); 1274 1275 if (!ha) 1276 return 0; 1277 1278 if (!ha->active) 1279 return 0; 1280 1281 intrstatus = (*ha->func.isintr) (ha); 1282 1283 if (!intrstatus) { 1284 /* 1285 * Unexpected/Shared interrupt 1286 */ 1287 1288 return 0; 1289 } 1290 1291 while (TRUE) { 1292 sp = &ha->sp; 1293 1294 intrstatus = (*ha->func.isintr) (ha); 1295 1296 if (!intrstatus) 1297 break; 1298 else 1299 cstatus.value = (*ha->func.statupd) (ha); 1300 1301 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1302 /* Spurious Interrupt ? */ 1303 continue; 1304 } 1305 1306 ips_chkstatus(ha, &cstatus); 1307 scb = (ips_scb_t *) sp->scb_addr; 1308 1309 /* 1310 * use the callback function to finish things up 1311 * NOTE: interrupts are OFF for this 1312 */ 1313 (*scb->callback) (ha, scb); 1314 } /* end while */ 1315 return 1; 1316 } 1317 1318 /****************************************************************************/ 1319 /* */ 1320 /* Routine Name: ips_intr_morpheus */ 1321 /* */ 1322 /* Routine Description: */ 1323 /* */ 1324 /* Polling interrupt handler */ 1325 /* */ 1326 /* ASSUMES interrupts are disabled */ 1327 /* */ 1328 /****************************************************************************/ 1329 int 1330 ips_intr_morpheus(ips_ha_t * ha) 1331 { 1332 ips_stat_t *sp; 1333 ips_scb_t *scb; 1334 IPS_STATUS cstatus; 1335 int intrstatus; 1336 1337 METHOD_TRACE("ips_intr_morpheus", 2); 1338 1339 if (!ha) 1340 return 0; 1341 1342 if (!ha->active) 1343 return 0; 1344 1345 intrstatus = (*ha->func.isintr) (ha); 1346 1347 if (!intrstatus) { 1348 /* 1349 * Unexpected/Shared interrupt 1350 */ 1351 1352 return 0; 1353 } 1354 1355 while (TRUE) { 1356 sp = &ha->sp; 1357 1358 intrstatus = (*ha->func.isintr) (ha); 1359 1360 if (!intrstatus) 1361 break; 1362 else 1363 cstatus.value = (*ha->func.statupd) (ha); 1364 1365 if (cstatus.value == 0xffffffff) 1366 /* No more to process */ 1367 break; 1368 1369 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1370 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1371 "Spurious interrupt; no ccb.\n"); 1372 1373 continue; 1374 } 1375 1376 ips_chkstatus(ha, &cstatus); 1377 scb = (ips_scb_t *) sp->scb_addr; 1378 1379 /* 1380 * use the callback function to finish things up 1381 * NOTE: interrupts are OFF for this 1382 */ 1383 (*scb->callback) (ha, scb); 1384 } /* end while */ 1385 return 1; 1386 } 1387 1388 /****************************************************************************/ 1389 /* */ 1390 /* Routine Name: ips_info */ 1391 /* */ 1392 /* Routine Description: */ 1393 /* */ 1394 /* Return info about the driver */ 1395 /* */ 1396 /****************************************************************************/ 1397 static const char * 1398 ips_info(struct Scsi_Host *SH) 1399 { 1400 static char buffer[256]; 1401 char *bp; 1402 ips_ha_t *ha; 1403 1404 METHOD_TRACE("ips_info", 1); 1405 1406 ha = IPS_HA(SH); 1407 1408 if (!ha) 1409 return (NULL); 1410 1411 bp = &buffer[0]; 1412 memset(bp, 0, sizeof (buffer)); 1413 1414 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ", 1415 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT); 1416 1417 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) { 1418 strcat(bp, " <"); 1419 strcat(bp, ips_adapter_name[ha->ad_type - 1]); 1420 strcat(bp, ">"); 1421 } 1422 1423 return (bp); 1424 } 1425 1426 static int 1427 ips_write_info(struct Scsi_Host *host, char *buffer, int length) 1428 { 1429 int i; 1430 ips_ha_t *ha = NULL; 1431 1432 /* Find our host structure */ 1433 for (i = 0; i < ips_next_controller; i++) { 1434 if (ips_sh[i]) { 1435 if (ips_sh[i] == host) { 1436 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1437 break; 1438 } 1439 } 1440 } 1441 1442 if (!ha) 1443 return (-EINVAL); 1444 1445 return 0; 1446 } 1447 1448 static int 1449 ips_show_info(struct seq_file *m, struct Scsi_Host *host) 1450 { 1451 int i; 1452 ips_ha_t *ha = NULL; 1453 1454 /* Find our host structure */ 1455 for (i = 0; i < ips_next_controller; i++) { 1456 if (ips_sh[i]) { 1457 if (ips_sh[i] == host) { 1458 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1459 break; 1460 } 1461 } 1462 } 1463 1464 if (!ha) 1465 return (-EINVAL); 1466 1467 return ips_host_info(ha, m); 1468 } 1469 1470 /*--------------------------------------------------------------------------*/ 1471 /* Helper Functions */ 1472 /*--------------------------------------------------------------------------*/ 1473 1474 /****************************************************************************/ 1475 /* */ 1476 /* Routine Name: ips_is_passthru */ 1477 /* */ 1478 /* Routine Description: */ 1479 /* */ 1480 /* Determine if the specified SCSI command is really a passthru command */ 1481 /* */ 1482 /****************************************************************************/ 1483 static int ips_is_passthru(struct scsi_cmnd *SC) 1484 { 1485 unsigned long flags; 1486 1487 METHOD_TRACE("ips_is_passthru", 1); 1488 1489 if (!SC) 1490 return (0); 1491 1492 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) && 1493 (SC->device->channel == 0) && 1494 (SC->device->id == IPS_ADAPTER_ID) && 1495 (SC->device->lun == 0) && scsi_sglist(SC)) { 1496 struct scatterlist *sg = scsi_sglist(SC); 1497 char *buffer; 1498 1499 /* kmap_atomic() ensures addressability of the user buffer.*/ 1500 /* local_irq_save() protects the KM_IRQ0 address slot. */ 1501 local_irq_save(flags); 1502 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 1503 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' && 1504 buffer[2] == 'P' && buffer[3] == 'P') { 1505 kunmap_atomic(buffer - sg->offset); 1506 local_irq_restore(flags); 1507 return 1; 1508 } 1509 kunmap_atomic(buffer - sg->offset); 1510 local_irq_restore(flags); 1511 } 1512 return 0; 1513 } 1514 1515 /****************************************************************************/ 1516 /* */ 1517 /* Routine Name: ips_alloc_passthru_buffer */ 1518 /* */ 1519 /* Routine Description: */ 1520 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */ 1521 /* is too small or doesn't exist */ 1522 /****************************************************************************/ 1523 static int 1524 ips_alloc_passthru_buffer(ips_ha_t * ha, int length) 1525 { 1526 void *bigger_buf; 1527 dma_addr_t dma_busaddr; 1528 1529 if (ha->ioctl_data && length <= ha->ioctl_len) 1530 return 0; 1531 /* there is no buffer or it's not big enough, allocate a new one */ 1532 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr, 1533 GFP_KERNEL); 1534 if (bigger_buf) { 1535 /* free the old memory */ 1536 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len, 1537 ha->ioctl_data, ha->ioctl_busaddr); 1538 /* use the new memory */ 1539 ha->ioctl_data = (char *) bigger_buf; 1540 ha->ioctl_len = length; 1541 ha->ioctl_busaddr = dma_busaddr; 1542 } else { 1543 return -1; 1544 } 1545 return 0; 1546 } 1547 1548 /****************************************************************************/ 1549 /* */ 1550 /* Routine Name: ips_make_passthru */ 1551 /* */ 1552 /* Routine Description: */ 1553 /* */ 1554 /* Make a passthru command out of the info in the Scsi block */ 1555 /* */ 1556 /****************************************************************************/ 1557 static int 1558 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) 1559 { 1560 ips_passthru_t *pt; 1561 int length = 0; 1562 int i, ret; 1563 struct scatterlist *sg = scsi_sglist(SC); 1564 1565 METHOD_TRACE("ips_make_passthru", 1); 1566 1567 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i) 1568 length += sg->length; 1569 1570 if (length < sizeof (ips_passthru_t)) { 1571 /* wrong size */ 1572 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size", 1573 ips_name, ha->host_num); 1574 return (IPS_FAILURE); 1575 } 1576 if (ips_alloc_passthru_buffer(ha, length)) { 1577 /* allocation failure! If ha->ioctl_data exists, use it to return 1578 some error codes. Return a failed command to the scsi layer. */ 1579 if (ha->ioctl_data) { 1580 pt = (ips_passthru_t *) ha->ioctl_data; 1581 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t)); 1582 pt->BasicStatus = 0x0B; 1583 pt->ExtendedStatus = 0x00; 1584 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t)); 1585 } 1586 return IPS_FAILURE; 1587 } 1588 ha->ioctl_datasize = length; 1589 1590 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize); 1591 pt = (ips_passthru_t *) ha->ioctl_data; 1592 1593 /* 1594 * Some notes about the passthru interface used 1595 * 1596 * IF the scsi op_code == 0x0d then we assume 1597 * that the data came along with/goes with the 1598 * packet we received from the sg driver. In this 1599 * case the CmdBSize field of the pt structure is 1600 * used for the size of the buffer. 1601 */ 1602 1603 switch (pt->CoppCmd) { 1604 case IPS_NUMCTRLS: 1605 memcpy(ha->ioctl_data + sizeof (ips_passthru_t), 1606 &ips_num_controllers, sizeof (int)); 1607 ips_scmd_buf_write(SC, ha->ioctl_data, 1608 sizeof (ips_passthru_t) + sizeof (int)); 1609 SC->result = DID_OK << 16; 1610 1611 return (IPS_SUCCESS_IMM); 1612 1613 case IPS_COPPUSRCMD: 1614 case IPS_COPPIOCCMD: 1615 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) { 1616 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) { 1617 /* wrong size */ 1618 DEBUG_VAR(1, 1619 "(%s%d) Passthru structure wrong size", 1620 ips_name, ha->host_num); 1621 1622 return (IPS_FAILURE); 1623 } 1624 1625 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && 1626 pt->CoppCP.cmd.flashfw.op_code == 1627 IPS_CMD_RW_BIOSFW) { 1628 ret = ips_flash_copperhead(ha, pt, scb); 1629 ips_scmd_buf_write(SC, ha->ioctl_data, 1630 sizeof (ips_passthru_t)); 1631 return ret; 1632 } 1633 if (ips_usrcmd(ha, pt, scb)) 1634 return (IPS_SUCCESS); 1635 else 1636 return (IPS_FAILURE); 1637 } 1638 1639 break; 1640 1641 } /* end switch */ 1642 1643 return (IPS_FAILURE); 1644 } 1645 1646 /****************************************************************************/ 1647 /* Routine Name: ips_flash_copperhead */ 1648 /* Routine Description: */ 1649 /* Flash the BIOS/FW on a Copperhead style controller */ 1650 /****************************************************************************/ 1651 static int 1652 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1653 { 1654 int datasize; 1655 1656 /* Trombone is the only copperhead that can do packet flash, but only 1657 * for firmware. No one said it had to make sense. */ 1658 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) { 1659 if (ips_usrcmd(ha, pt, scb)) 1660 return IPS_SUCCESS; 1661 else 1662 return IPS_FAILURE; 1663 } 1664 pt->BasicStatus = 0x0B; 1665 pt->ExtendedStatus = 0; 1666 scb->scsi_cmd->result = DID_OK << 16; 1667 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */ 1668 /* avoid allocating a huge buffer per adapter ( which can fail ). */ 1669 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1670 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1671 pt->BasicStatus = 0; 1672 return ips_flash_bios(ha, pt, scb); 1673 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) { 1674 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){ 1675 ha->flash_data = ips_FlashData; 1676 ha->flash_busaddr = ips_flashbusaddr; 1677 ha->flash_len = PAGE_SIZE << 7; 1678 ha->flash_datasize = 0; 1679 } else if (!ha->flash_data) { 1680 datasize = pt->CoppCP.cmd.flashfw.total_packets * 1681 pt->CoppCP.cmd.flashfw.count; 1682 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev, 1683 datasize, &ha->flash_busaddr, GFP_KERNEL); 1684 if (!ha->flash_data){ 1685 printk(KERN_WARNING "Unable to allocate a flash buffer\n"); 1686 return IPS_FAILURE; 1687 } 1688 ha->flash_datasize = 0; 1689 ha->flash_len = datasize; 1690 } else 1691 return IPS_FAILURE; 1692 } else { 1693 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize > 1694 ha->flash_len) { 1695 ips_free_flash_copperhead(ha); 1696 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1697 "failed size sanity check\n"); 1698 return IPS_FAILURE; 1699 } 1700 } 1701 if (!ha->flash_data) 1702 return IPS_FAILURE; 1703 pt->BasicStatus = 0; 1704 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1, 1705 pt->CoppCP.cmd.flashfw.count); 1706 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count; 1707 if (pt->CoppCP.cmd.flashfw.packet_num == 1708 pt->CoppCP.cmd.flashfw.total_packets - 1) { 1709 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE) 1710 return ips_flash_bios(ha, pt, scb); 1711 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) 1712 return ips_flash_firmware(ha, pt, scb); 1713 } 1714 return IPS_SUCCESS_IMM; 1715 } 1716 1717 /****************************************************************************/ 1718 /* Routine Name: ips_flash_bios */ 1719 /* Routine Description: */ 1720 /* flashes the bios of a copperhead adapter */ 1721 /****************************************************************************/ 1722 static int 1723 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1724 { 1725 1726 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1727 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) { 1728 if ((!ha->func.programbios) || (!ha->func.erasebios) || 1729 (!ha->func.verifybios)) 1730 goto error; 1731 if ((*ha->func.erasebios) (ha)) { 1732 DEBUG_VAR(1, 1733 "(%s%d) flash bios failed - unable to erase flash", 1734 ips_name, ha->host_num); 1735 goto error; 1736 } else 1737 if ((*ha->func.programbios) (ha, 1738 ha->flash_data + 1739 IPS_BIOS_HEADER, 1740 ha->flash_datasize - 1741 IPS_BIOS_HEADER, 0)) { 1742 DEBUG_VAR(1, 1743 "(%s%d) flash bios failed - unable to flash", 1744 ips_name, ha->host_num); 1745 goto error; 1746 } else 1747 if ((*ha->func.verifybios) (ha, 1748 ha->flash_data + 1749 IPS_BIOS_HEADER, 1750 ha->flash_datasize - 1751 IPS_BIOS_HEADER, 0)) { 1752 DEBUG_VAR(1, 1753 "(%s%d) flash bios failed - unable to verify flash", 1754 ips_name, ha->host_num); 1755 goto error; 1756 } 1757 ips_free_flash_copperhead(ha); 1758 return IPS_SUCCESS_IMM; 1759 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1760 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1761 if (!ha->func.erasebios) 1762 goto error; 1763 if ((*ha->func.erasebios) (ha)) { 1764 DEBUG_VAR(1, 1765 "(%s%d) flash bios failed - unable to erase flash", 1766 ips_name, ha->host_num); 1767 goto error; 1768 } 1769 return IPS_SUCCESS_IMM; 1770 } 1771 error: 1772 pt->BasicStatus = 0x0B; 1773 pt->ExtendedStatus = 0x00; 1774 ips_free_flash_copperhead(ha); 1775 return IPS_FAILURE; 1776 } 1777 1778 /****************************************************************************/ 1779 /* */ 1780 /* Routine Name: ips_fill_scb_sg_single */ 1781 /* */ 1782 /* Routine Description: */ 1783 /* Fill in a single scb sg_list element from an address */ 1784 /* return a -1 if a breakup occurred */ 1785 /****************************************************************************/ 1786 static int 1787 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr, 1788 ips_scb_t * scb, int indx, unsigned int e_len) 1789 { 1790 1791 int ret_val = 0; 1792 1793 if ((scb->data_len + e_len) > ha->max_xfer) { 1794 e_len = ha->max_xfer - scb->data_len; 1795 scb->breakup = indx; 1796 ++scb->sg_break; 1797 ret_val = -1; 1798 } else { 1799 scb->breakup = 0; 1800 scb->sg_break = 0; 1801 } 1802 if (IPS_USE_ENH_SGLIST(ha)) { 1803 scb->sg_list.enh_list[indx].address_lo = 1804 cpu_to_le32(pci_dma_lo32(busaddr)); 1805 scb->sg_list.enh_list[indx].address_hi = 1806 cpu_to_le32(pci_dma_hi32(busaddr)); 1807 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len); 1808 } else { 1809 scb->sg_list.std_list[indx].address = 1810 cpu_to_le32(pci_dma_lo32(busaddr)); 1811 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len); 1812 } 1813 1814 ++scb->sg_len; 1815 scb->data_len += e_len; 1816 return ret_val; 1817 } 1818 1819 /****************************************************************************/ 1820 /* Routine Name: ips_flash_firmware */ 1821 /* Routine Description: */ 1822 /* flashes the firmware of a copperhead adapter */ 1823 /****************************************************************************/ 1824 static int 1825 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1826 { 1827 IPS_SG_LIST sg_list; 1828 uint32_t cmd_busaddr; 1829 1830 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE && 1831 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) { 1832 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND)); 1833 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD; 1834 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize); 1835 } else { 1836 pt->BasicStatus = 0x0B; 1837 pt->ExtendedStatus = 0x00; 1838 ips_free_flash_copperhead(ha); 1839 return IPS_FAILURE; 1840 } 1841 /* Save the S/G list pointer so it doesn't get clobbered */ 1842 sg_list.list = scb->sg_list.list; 1843 cmd_busaddr = scb->scb_busaddr; 1844 /* copy in the CP */ 1845 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1846 /* FIX stuff that might be wrong */ 1847 scb->sg_list.list = sg_list.list; 1848 scb->scb_busaddr = cmd_busaddr; 1849 scb->bus = scb->scsi_cmd->device->channel; 1850 scb->target_id = scb->scsi_cmd->device->id; 1851 scb->lun = scb->scsi_cmd->device->lun; 1852 scb->sg_len = 0; 1853 scb->data_len = 0; 1854 scb->flags = 0; 1855 scb->op_code = 0; 1856 scb->callback = ipsintr_done; 1857 scb->timeout = ips_cmd_timeout; 1858 1859 scb->data_len = ha->flash_datasize; 1860 scb->data_busaddr = 1861 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len, 1862 IPS_DMA_DIR(scb)); 1863 scb->flags |= IPS_SCB_MAP_SINGLE; 1864 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 1865 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr); 1866 if (pt->TimeOut) 1867 scb->timeout = pt->TimeOut; 1868 scb->scsi_cmd->result = DID_OK << 16; 1869 return IPS_SUCCESS; 1870 } 1871 1872 /****************************************************************************/ 1873 /* Routine Name: ips_free_flash_copperhead */ 1874 /* Routine Description: */ 1875 /* release the memory resources used to hold the flash image */ 1876 /****************************************************************************/ 1877 static void 1878 ips_free_flash_copperhead(ips_ha_t * ha) 1879 { 1880 if (ha->flash_data == ips_FlashData) 1881 test_and_clear_bit(0, &ips_FlashDataInUse); 1882 else if (ha->flash_data) 1883 dma_free_coherent(&ha->pcidev->dev, ha->flash_len, 1884 ha->flash_data, ha->flash_busaddr); 1885 ha->flash_data = NULL; 1886 } 1887 1888 /****************************************************************************/ 1889 /* */ 1890 /* Routine Name: ips_usrcmd */ 1891 /* */ 1892 /* Routine Description: */ 1893 /* */ 1894 /* Process a user command and make it ready to send */ 1895 /* */ 1896 /****************************************************************************/ 1897 static int 1898 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1899 { 1900 IPS_SG_LIST sg_list; 1901 uint32_t cmd_busaddr; 1902 1903 METHOD_TRACE("ips_usrcmd", 1); 1904 1905 if ((!scb) || (!pt) || (!ha)) 1906 return (0); 1907 1908 /* Save the S/G list pointer so it doesn't get clobbered */ 1909 sg_list.list = scb->sg_list.list; 1910 cmd_busaddr = scb->scb_busaddr; 1911 /* copy in the CP */ 1912 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1913 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE)); 1914 1915 /* FIX stuff that might be wrong */ 1916 scb->sg_list.list = sg_list.list; 1917 scb->scb_busaddr = cmd_busaddr; 1918 scb->bus = scb->scsi_cmd->device->channel; 1919 scb->target_id = scb->scsi_cmd->device->id; 1920 scb->lun = scb->scsi_cmd->device->lun; 1921 scb->sg_len = 0; 1922 scb->data_len = 0; 1923 scb->flags = 0; 1924 scb->op_code = 0; 1925 scb->callback = ipsintr_done; 1926 scb->timeout = ips_cmd_timeout; 1927 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 1928 1929 /* we don't support DCDB/READ/WRITE Scatter Gather */ 1930 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) || 1931 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) || 1932 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG)) 1933 return (0); 1934 1935 if (pt->CmdBSize) { 1936 scb->data_len = pt->CmdBSize; 1937 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t); 1938 } else { 1939 scb->data_busaddr = 0L; 1940 } 1941 1942 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 1943 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 1944 (unsigned long) &scb-> 1945 dcdb - 1946 (unsigned long) scb); 1947 1948 if (pt->CmdBSize) { 1949 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 1950 scb->dcdb.buffer_pointer = 1951 cpu_to_le32(scb->data_busaddr); 1952 else 1953 scb->cmd.basic_io.sg_addr = 1954 cpu_to_le32(scb->data_busaddr); 1955 } 1956 1957 /* set timeouts */ 1958 if (pt->TimeOut) { 1959 scb->timeout = pt->TimeOut; 1960 1961 if (pt->TimeOut <= 10) 1962 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; 1963 else if (pt->TimeOut <= 60) 1964 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; 1965 else 1966 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; 1967 } 1968 1969 /* assume success */ 1970 scb->scsi_cmd->result = DID_OK << 16; 1971 1972 /* success */ 1973 return (1); 1974 } 1975 1976 /****************************************************************************/ 1977 /* */ 1978 /* Routine Name: ips_cleanup_passthru */ 1979 /* */ 1980 /* Routine Description: */ 1981 /* */ 1982 /* Cleanup after a passthru command */ 1983 /* */ 1984 /****************************************************************************/ 1985 static void 1986 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) 1987 { 1988 ips_passthru_t *pt; 1989 1990 METHOD_TRACE("ips_cleanup_passthru", 1); 1991 1992 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) { 1993 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru", 1994 ips_name, ha->host_num); 1995 1996 return; 1997 } 1998 pt = (ips_passthru_t *) ha->ioctl_data; 1999 2000 /* Copy data back to the user */ 2001 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */ 2002 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE)); 2003 2004 pt->BasicStatus = scb->basic_status; 2005 pt->ExtendedStatus = scb->extended_status; 2006 pt->AdapterType = ha->ad_type; 2007 2008 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && 2009 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || 2010 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) 2011 ips_free_flash_copperhead(ha); 2012 2013 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize); 2014 } 2015 2016 /****************************************************************************/ 2017 /* */ 2018 /* Routine Name: ips_host_info */ 2019 /* */ 2020 /* Routine Description: */ 2021 /* */ 2022 /* The passthru interface for the driver */ 2023 /* */ 2024 /****************************************************************************/ 2025 static int 2026 ips_host_info(ips_ha_t *ha, struct seq_file *m) 2027 { 2028 METHOD_TRACE("ips_host_info", 1); 2029 2030 seq_puts(m, "\nIBM ServeRAID General Information:\n\n"); 2031 2032 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) && 2033 (le16_to_cpu(ha->nvram->adapter_type) != 0)) 2034 seq_printf(m, "\tController Type : %s\n", 2035 ips_adapter_name[ha->ad_type - 1]); 2036 else 2037 seq_puts(m, "\tController Type : Unknown\n"); 2038 2039 if (ha->io_addr) 2040 seq_printf(m, 2041 "\tIO region : 0x%x (%d bytes)\n", 2042 ha->io_addr, ha->io_len); 2043 2044 if (ha->mem_addr) { 2045 seq_printf(m, 2046 "\tMemory region : 0x%x (%d bytes)\n", 2047 ha->mem_addr, ha->mem_len); 2048 seq_printf(m, 2049 "\tShared memory address : 0x%lx\n", 2050 (unsigned long)ha->mem_ptr); 2051 } 2052 2053 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq); 2054 2055 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ 2056 /* That keeps everything happy for "text" operations on the proc file. */ 2057 2058 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { 2059 if (ha->nvram->bios_low[3] == 0) { 2060 seq_printf(m, 2061 "\tBIOS Version : %c%c%c%c%c%c%c\n", 2062 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2063 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2064 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2065 ha->nvram->bios_low[2]); 2066 2067 } else { 2068 seq_printf(m, 2069 "\tBIOS Version : %c%c%c%c%c%c%c%c\n", 2070 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2071 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2072 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2073 ha->nvram->bios_low[2], ha->nvram->bios_low[3]); 2074 } 2075 2076 } 2077 2078 if (ha->enq->CodeBlkVersion[7] == 0) { 2079 seq_printf(m, 2080 "\tFirmware Version : %c%c%c%c%c%c%c\n", 2081 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2082 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2083 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2084 ha->enq->CodeBlkVersion[6]); 2085 } else { 2086 seq_printf(m, 2087 "\tFirmware Version : %c%c%c%c%c%c%c%c\n", 2088 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2089 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2090 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2091 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]); 2092 } 2093 2094 if (ha->enq->BootBlkVersion[7] == 0) { 2095 seq_printf(m, 2096 "\tBoot Block Version : %c%c%c%c%c%c%c\n", 2097 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2098 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2099 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2100 ha->enq->BootBlkVersion[6]); 2101 } else { 2102 seq_printf(m, 2103 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n", 2104 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2105 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2106 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2107 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]); 2108 } 2109 2110 seq_printf(m, "\tDriver Version : %s%s\n", 2111 IPS_VERSION_HIGH, IPS_VERSION_LOW); 2112 2113 seq_printf(m, "\tDriver Build : %d\n", 2114 IPS_BUILD_IDENT); 2115 2116 seq_printf(m, "\tMax Physical Devices : %d\n", 2117 ha->enq->ucMaxPhysicalDevices); 2118 seq_printf(m, "\tMax Active Commands : %d\n", 2119 ha->max_cmds); 2120 seq_printf(m, "\tCurrent Queued Commands : %d\n", 2121 ha->scb_waitlist.count); 2122 seq_printf(m, "\tCurrent Active Commands : %d\n", 2123 ha->scb_activelist.count - ha->num_ioctl); 2124 seq_printf(m, "\tCurrent Queued PT Commands : %d\n", 2125 ha->copp_waitlist.count); 2126 seq_printf(m, "\tCurrent Active PT Commands : %d\n", 2127 ha->num_ioctl); 2128 2129 seq_putc(m, '\n'); 2130 2131 return 0; 2132 } 2133 2134 /****************************************************************************/ 2135 /* */ 2136 /* Routine Name: ips_identify_controller */ 2137 /* */ 2138 /* Routine Description: */ 2139 /* */ 2140 /* Identify this controller */ 2141 /* */ 2142 /****************************************************************************/ 2143 static void 2144 ips_identify_controller(ips_ha_t * ha) 2145 { 2146 METHOD_TRACE("ips_identify_controller", 1); 2147 2148 switch (ha->pcidev->device) { 2149 case IPS_DEVICEID_COPPERHEAD: 2150 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) { 2151 ha->ad_type = IPS_ADTYPE_SERVERAID; 2152 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) { 2153 ha->ad_type = IPS_ADTYPE_SERVERAID2; 2154 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) { 2155 ha->ad_type = IPS_ADTYPE_NAVAJO; 2156 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2) 2157 && (ha->slot_num == 0)) { 2158 ha->ad_type = IPS_ADTYPE_KIOWA; 2159 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) && 2160 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) { 2161 if (ha->enq->ucMaxPhysicalDevices == 15) 2162 ha->ad_type = IPS_ADTYPE_SERVERAID3L; 2163 else 2164 ha->ad_type = IPS_ADTYPE_SERVERAID3; 2165 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) && 2166 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) { 2167 ha->ad_type = IPS_ADTYPE_SERVERAID4H; 2168 } 2169 break; 2170 2171 case IPS_DEVICEID_MORPHEUS: 2172 switch (ha->pcidev->subsystem_device) { 2173 case IPS_SUBDEVICEID_4L: 2174 ha->ad_type = IPS_ADTYPE_SERVERAID4L; 2175 break; 2176 2177 case IPS_SUBDEVICEID_4M: 2178 ha->ad_type = IPS_ADTYPE_SERVERAID4M; 2179 break; 2180 2181 case IPS_SUBDEVICEID_4MX: 2182 ha->ad_type = IPS_ADTYPE_SERVERAID4MX; 2183 break; 2184 2185 case IPS_SUBDEVICEID_4LX: 2186 ha->ad_type = IPS_ADTYPE_SERVERAID4LX; 2187 break; 2188 2189 case IPS_SUBDEVICEID_5I2: 2190 ha->ad_type = IPS_ADTYPE_SERVERAID5I2; 2191 break; 2192 2193 case IPS_SUBDEVICEID_5I1: 2194 ha->ad_type = IPS_ADTYPE_SERVERAID5I1; 2195 break; 2196 } 2197 2198 break; 2199 2200 case IPS_DEVICEID_MARCO: 2201 switch (ha->pcidev->subsystem_device) { 2202 case IPS_SUBDEVICEID_6M: 2203 ha->ad_type = IPS_ADTYPE_SERVERAID6M; 2204 break; 2205 case IPS_SUBDEVICEID_6I: 2206 ha->ad_type = IPS_ADTYPE_SERVERAID6I; 2207 break; 2208 case IPS_SUBDEVICEID_7k: 2209 ha->ad_type = IPS_ADTYPE_SERVERAID7k; 2210 break; 2211 case IPS_SUBDEVICEID_7M: 2212 ha->ad_type = IPS_ADTYPE_SERVERAID7M; 2213 break; 2214 } 2215 break; 2216 } 2217 } 2218 2219 /****************************************************************************/ 2220 /* */ 2221 /* Routine Name: ips_get_bios_version */ 2222 /* */ 2223 /* Routine Description: */ 2224 /* */ 2225 /* Get the BIOS revision number */ 2226 /* */ 2227 /****************************************************************************/ 2228 static void 2229 ips_get_bios_version(ips_ha_t * ha, int intr) 2230 { 2231 ips_scb_t *scb; 2232 int ret; 2233 uint8_t major; 2234 uint8_t minor; 2235 uint8_t subminor; 2236 uint8_t *buffer; 2237 2238 METHOD_TRACE("ips_get_bios_version", 1); 2239 2240 major = 0; 2241 minor = 0; 2242 2243 strncpy(ha->bios_version, " ?", 8); 2244 2245 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) { 2246 if (IPS_USE_MEMIO(ha)) { 2247 /* Memory Mapped I/O */ 2248 2249 /* test 1st byte */ 2250 writel(0, ha->mem_ptr + IPS_REG_FLAP); 2251 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2252 udelay(25); /* 25 us */ 2253 2254 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 2255 return; 2256 2257 writel(1, ha->mem_ptr + IPS_REG_FLAP); 2258 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2259 udelay(25); /* 25 us */ 2260 2261 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 2262 return; 2263 2264 /* Get Major version */ 2265 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); 2266 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2267 udelay(25); /* 25 us */ 2268 2269 major = readb(ha->mem_ptr + IPS_REG_FLDP); 2270 2271 /* Get Minor version */ 2272 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); 2273 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2274 udelay(25); /* 25 us */ 2275 minor = readb(ha->mem_ptr + IPS_REG_FLDP); 2276 2277 /* Get SubMinor version */ 2278 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); 2279 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2280 udelay(25); /* 25 us */ 2281 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); 2282 2283 } else { 2284 /* Programmed I/O */ 2285 2286 /* test 1st byte */ 2287 outl(0, ha->io_addr + IPS_REG_FLAP); 2288 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2289 udelay(25); /* 25 us */ 2290 2291 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 2292 return; 2293 2294 outl(1, ha->io_addr + IPS_REG_FLAP); 2295 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2296 udelay(25); /* 25 us */ 2297 2298 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 2299 return; 2300 2301 /* Get Major version */ 2302 outl(0x1FF, ha->io_addr + IPS_REG_FLAP); 2303 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2304 udelay(25); /* 25 us */ 2305 2306 major = inb(ha->io_addr + IPS_REG_FLDP); 2307 2308 /* Get Minor version */ 2309 outl(0x1FE, ha->io_addr + IPS_REG_FLAP); 2310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2311 udelay(25); /* 25 us */ 2312 2313 minor = inb(ha->io_addr + IPS_REG_FLDP); 2314 2315 /* Get SubMinor version */ 2316 outl(0x1FD, ha->io_addr + IPS_REG_FLAP); 2317 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2318 udelay(25); /* 25 us */ 2319 2320 subminor = inb(ha->io_addr + IPS_REG_FLDP); 2321 2322 } 2323 } else { 2324 /* Morpheus Family - Send Command to the card */ 2325 2326 buffer = ha->ioctl_data; 2327 2328 memset(buffer, 0, 0x1000); 2329 2330 scb = &ha->scbs[ha->max_cmds - 1]; 2331 2332 ips_init_scb(ha, scb); 2333 2334 scb->timeout = ips_cmd_timeout; 2335 scb->cdb[0] = IPS_CMD_RW_BIOSFW; 2336 2337 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW; 2338 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 2339 scb->cmd.flashfw.type = 1; 2340 scb->cmd.flashfw.direction = 0; 2341 scb->cmd.flashfw.count = cpu_to_le32(0x800); 2342 scb->cmd.flashfw.total_packets = 1; 2343 scb->cmd.flashfw.packet_num = 0; 2344 scb->data_len = 0x1000; 2345 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr; 2346 2347 /* issue the command */ 2348 if (((ret = 2349 ips_send_wait(ha, scb, ips_cmd_timeout, 2350 intr)) == IPS_FAILURE) 2351 || (ret == IPS_SUCCESS_IMM) 2352 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 2353 /* Error occurred */ 2354 2355 return; 2356 } 2357 2358 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) { 2359 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */ 2360 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */ 2361 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */ 2362 } else { 2363 return; 2364 } 2365 } 2366 2367 ha->bios_version[0] = hex_asc_upper_hi(major); 2368 ha->bios_version[1] = '.'; 2369 ha->bios_version[2] = hex_asc_upper_lo(major); 2370 ha->bios_version[3] = hex_asc_upper_lo(subminor); 2371 ha->bios_version[4] = '.'; 2372 ha->bios_version[5] = hex_asc_upper_hi(minor); 2373 ha->bios_version[6] = hex_asc_upper_lo(minor); 2374 ha->bios_version[7] = 0; 2375 } 2376 2377 /****************************************************************************/ 2378 /* */ 2379 /* Routine Name: ips_hainit */ 2380 /* */ 2381 /* Routine Description: */ 2382 /* */ 2383 /* Initialize the controller */ 2384 /* */ 2385 /* NOTE: Assumes to be called from with a lock */ 2386 /* */ 2387 /****************************************************************************/ 2388 static int 2389 ips_hainit(ips_ha_t * ha) 2390 { 2391 int i; 2392 2393 METHOD_TRACE("ips_hainit", 1); 2394 2395 if (!ha) 2396 return (0); 2397 2398 if (ha->func.statinit) 2399 (*ha->func.statinit) (ha); 2400 2401 if (ha->func.enableint) 2402 (*ha->func.enableint) (ha); 2403 2404 /* Send FFDC */ 2405 ha->reset_count = 1; 2406 ha->last_ffdc = ktime_get_real_seconds(); 2407 ips_ffdc_reset(ha, IPS_INTR_IORL); 2408 2409 if (!ips_read_config(ha, IPS_INTR_IORL)) { 2410 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2411 "unable to read config from controller.\n"); 2412 2413 return (0); 2414 } 2415 /* end if */ 2416 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) { 2417 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2418 "unable to read controller status.\n"); 2419 2420 return (0); 2421 } 2422 2423 /* Identify this controller */ 2424 ips_identify_controller(ha); 2425 2426 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) { 2427 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2428 "unable to read subsystem parameters.\n"); 2429 2430 return (0); 2431 } 2432 2433 /* write nvram user page 5 */ 2434 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) { 2435 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2436 "unable to write driver info to controller.\n"); 2437 2438 return (0); 2439 } 2440 2441 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */ 2442 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1)) 2443 ips_clear_adapter(ha, IPS_INTR_IORL); 2444 2445 /* set limits on SID, LUN, BUS */ 2446 ha->ntargets = IPS_MAX_TARGETS + 1; 2447 ha->nlun = 1; 2448 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1; 2449 2450 switch (ha->conf->logical_drive[0].ucStripeSize) { 2451 case 4: 2452 ha->max_xfer = 0x10000; 2453 break; 2454 2455 case 5: 2456 ha->max_xfer = 0x20000; 2457 break; 2458 2459 case 6: 2460 ha->max_xfer = 0x40000; 2461 break; 2462 2463 case 7: 2464 default: 2465 ha->max_xfer = 0x80000; 2466 break; 2467 } 2468 2469 /* setup max concurrent commands */ 2470 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) { 2471 /* Use the new method */ 2472 ha->max_cmds = ha->enq->ucConcurrentCmdCount; 2473 } else { 2474 /* use the old method */ 2475 switch (ha->conf->logical_drive[0].ucStripeSize) { 2476 case 4: 2477 ha->max_cmds = 32; 2478 break; 2479 2480 case 5: 2481 ha->max_cmds = 16; 2482 break; 2483 2484 case 6: 2485 ha->max_cmds = 8; 2486 break; 2487 2488 case 7: 2489 default: 2490 ha->max_cmds = 4; 2491 break; 2492 } 2493 } 2494 2495 /* Limit the Active Commands on a Lite Adapter */ 2496 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) || 2497 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) || 2498 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) { 2499 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds)) 2500 ha->max_cmds = MaxLiteCmds; 2501 } 2502 2503 /* set controller IDs */ 2504 ha->ha_id[0] = IPS_ADAPTER_ID; 2505 for (i = 1; i < ha->nbus; i++) { 2506 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f; 2507 ha->dcdb_active[i - 1] = 0; 2508 } 2509 2510 return (1); 2511 } 2512 2513 /****************************************************************************/ 2514 /* */ 2515 /* Routine Name: ips_next */ 2516 /* */ 2517 /* Routine Description: */ 2518 /* */ 2519 /* Take the next command off the queue and send it to the controller */ 2520 /* */ 2521 /****************************************************************************/ 2522 static void 2523 ips_next(ips_ha_t * ha, int intr) 2524 { 2525 ips_scb_t *scb; 2526 struct scsi_cmnd *SC; 2527 struct scsi_cmnd *p; 2528 struct scsi_cmnd *q; 2529 ips_copp_wait_item_t *item; 2530 int ret; 2531 struct Scsi_Host *host; 2532 METHOD_TRACE("ips_next", 1); 2533 2534 if (!ha) 2535 return; 2536 host = ips_sh[ha->host_num]; 2537 /* 2538 * Block access to the queue function so 2539 * this command won't time out 2540 */ 2541 if (intr == IPS_INTR_ON) 2542 spin_lock(host->host_lock); 2543 2544 if ((ha->subsys->param[3] & 0x300000) 2545 && (ha->scb_activelist.count == 0)) { 2546 time64_t now = ktime_get_real_seconds(); 2547 if (now - ha->last_ffdc > IPS_SECS_8HOURS) { 2548 ha->last_ffdc = now; 2549 ips_ffdc_time(ha); 2550 } 2551 } 2552 2553 /* 2554 * Send passthru commands 2555 * These have priority over normal I/O 2556 * but shouldn't affect performance too much 2557 * since we limit the number that can be active 2558 * on the card at any one time 2559 */ 2560 while ((ha->num_ioctl < IPS_MAX_IOCTL) && 2561 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) { 2562 2563 item = ips_removeq_copp_head(&ha->copp_waitlist); 2564 ha->num_ioctl++; 2565 if (intr == IPS_INTR_ON) 2566 spin_unlock(host->host_lock); 2567 scb->scsi_cmd = item->scsi_cmd; 2568 kfree(item); 2569 2570 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr); 2571 2572 if (intr == IPS_INTR_ON) 2573 spin_lock(host->host_lock); 2574 switch (ret) { 2575 case IPS_FAILURE: 2576 if (scb->scsi_cmd) { 2577 scb->scsi_cmd->result = DID_ERROR << 16; 2578 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2579 } 2580 2581 ips_freescb(ha, scb); 2582 break; 2583 case IPS_SUCCESS_IMM: 2584 if (scb->scsi_cmd) { 2585 scb->scsi_cmd->result = DID_OK << 16; 2586 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2587 } 2588 2589 ips_freescb(ha, scb); 2590 break; 2591 default: 2592 break; 2593 } /* end case */ 2594 2595 if (ret != IPS_SUCCESS) { 2596 ha->num_ioctl--; 2597 continue; 2598 } 2599 2600 ret = ips_send_cmd(ha, scb); 2601 2602 if (ret == IPS_SUCCESS) 2603 ips_putq_scb_head(&ha->scb_activelist, scb); 2604 else 2605 ha->num_ioctl--; 2606 2607 switch (ret) { 2608 case IPS_FAILURE: 2609 if (scb->scsi_cmd) { 2610 scb->scsi_cmd->result = DID_ERROR << 16; 2611 } 2612 2613 ips_freescb(ha, scb); 2614 break; 2615 case IPS_SUCCESS_IMM: 2616 ips_freescb(ha, scb); 2617 break; 2618 default: 2619 break; 2620 } /* end case */ 2621 2622 } 2623 2624 /* 2625 * Send "Normal" I/O commands 2626 */ 2627 2628 p = ha->scb_waitlist.head; 2629 while ((p) && (scb = ips_getscb(ha))) { 2630 if ((scmd_channel(p) > 0) 2631 && (ha-> 2632 dcdb_active[scmd_channel(p) - 2633 1] & (1 << scmd_id(p)))) { 2634 ips_freescb(ha, scb); 2635 p = (struct scsi_cmnd *) p->host_scribble; 2636 continue; 2637 } 2638 2639 q = p; 2640 SC = ips_removeq_wait(&ha->scb_waitlist, q); 2641 2642 if (intr == IPS_INTR_ON) 2643 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */ 2644 2645 SC->result = DID_OK; 2646 SC->host_scribble = NULL; 2647 2648 scb->target_id = SC->device->id; 2649 scb->lun = SC->device->lun; 2650 scb->bus = SC->device->channel; 2651 scb->scsi_cmd = SC; 2652 scb->breakup = 0; 2653 scb->data_len = 0; 2654 scb->callback = ipsintr_done; 2655 scb->timeout = ips_cmd_timeout; 2656 memset(&scb->cmd, 0, 16); 2657 2658 /* copy in the CDB */ 2659 memcpy(scb->cdb, SC->cmnd, SC->cmd_len); 2660 2661 scb->sg_count = scsi_dma_map(SC); 2662 BUG_ON(scb->sg_count < 0); 2663 if (scb->sg_count) { 2664 struct scatterlist *sg; 2665 int i; 2666 2667 scb->flags |= IPS_SCB_MAP_SG; 2668 2669 scsi_for_each_sg(SC, sg, scb->sg_count, i) { 2670 if (ips_fill_scb_sg_single 2671 (ha, sg_dma_address(sg), scb, i, 2672 sg_dma_len(sg)) < 0) 2673 break; 2674 } 2675 scb->dcdb.transfer_length = scb->data_len; 2676 } else { 2677 scb->data_busaddr = 0L; 2678 scb->sg_len = 0; 2679 scb->data_len = 0; 2680 scb->dcdb.transfer_length = 0; 2681 } 2682 2683 scb->dcdb.cmd_attribute = 2684 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 2685 2686 /* Allow a WRITE BUFFER Command to Have no Data */ 2687 /* This is Used by Tape Flash Utilites */ 2688 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && 2689 (scb->data_len == 0)) 2690 scb->dcdb.cmd_attribute = 0; 2691 2692 if (!(scb->dcdb.cmd_attribute & 0x3)) 2693 scb->dcdb.transfer_length = 0; 2694 2695 if (scb->data_len >= IPS_MAX_XFER) { 2696 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 2697 scb->dcdb.transfer_length = 0; 2698 } 2699 if (intr == IPS_INTR_ON) 2700 spin_lock(host->host_lock); 2701 2702 ret = ips_send_cmd(ha, scb); 2703 2704 switch (ret) { 2705 case IPS_SUCCESS: 2706 ips_putq_scb_head(&ha->scb_activelist, scb); 2707 break; 2708 case IPS_FAILURE: 2709 if (scb->scsi_cmd) { 2710 scb->scsi_cmd->result = DID_ERROR << 16; 2711 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2712 } 2713 2714 if (scb->bus) 2715 ha->dcdb_active[scb->bus - 1] &= 2716 ~(1 << scb->target_id); 2717 2718 ips_freescb(ha, scb); 2719 break; 2720 case IPS_SUCCESS_IMM: 2721 if (scb->scsi_cmd) 2722 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 2723 2724 if (scb->bus) 2725 ha->dcdb_active[scb->bus - 1] &= 2726 ~(1 << scb->target_id); 2727 2728 ips_freescb(ha, scb); 2729 break; 2730 default: 2731 break; 2732 } /* end case */ 2733 2734 p = (struct scsi_cmnd *) p->host_scribble; 2735 2736 } /* end while */ 2737 2738 if (intr == IPS_INTR_ON) 2739 spin_unlock(host->host_lock); 2740 } 2741 2742 /****************************************************************************/ 2743 /* */ 2744 /* Routine Name: ips_putq_scb_head */ 2745 /* */ 2746 /* Routine Description: */ 2747 /* */ 2748 /* Add an item to the head of the queue */ 2749 /* */ 2750 /* ASSUMED to be called from within the HA lock */ 2751 /* */ 2752 /****************************************************************************/ 2753 static void 2754 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item) 2755 { 2756 METHOD_TRACE("ips_putq_scb_head", 1); 2757 2758 if (!item) 2759 return; 2760 2761 item->q_next = queue->head; 2762 queue->head = item; 2763 2764 if (!queue->tail) 2765 queue->tail = item; 2766 2767 queue->count++; 2768 } 2769 2770 /****************************************************************************/ 2771 /* */ 2772 /* Routine Name: ips_removeq_scb_head */ 2773 /* */ 2774 /* Routine Description: */ 2775 /* */ 2776 /* Remove the head of the queue */ 2777 /* */ 2778 /* ASSUMED to be called from within the HA lock */ 2779 /* */ 2780 /****************************************************************************/ 2781 static ips_scb_t * 2782 ips_removeq_scb_head(ips_scb_queue_t * queue) 2783 { 2784 ips_scb_t *item; 2785 2786 METHOD_TRACE("ips_removeq_scb_head", 1); 2787 2788 item = queue->head; 2789 2790 if (!item) { 2791 return (NULL); 2792 } 2793 2794 queue->head = item->q_next; 2795 item->q_next = NULL; 2796 2797 if (queue->tail == item) 2798 queue->tail = NULL; 2799 2800 queue->count--; 2801 2802 return (item); 2803 } 2804 2805 /****************************************************************************/ 2806 /* */ 2807 /* Routine Name: ips_removeq_scb */ 2808 /* */ 2809 /* Routine Description: */ 2810 /* */ 2811 /* Remove an item from a queue */ 2812 /* */ 2813 /* ASSUMED to be called from within the HA lock */ 2814 /* */ 2815 /****************************************************************************/ 2816 static ips_scb_t * 2817 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item) 2818 { 2819 ips_scb_t *p; 2820 2821 METHOD_TRACE("ips_removeq_scb", 1); 2822 2823 if (!item) 2824 return (NULL); 2825 2826 if (item == queue->head) { 2827 return (ips_removeq_scb_head(queue)); 2828 } 2829 2830 p = queue->head; 2831 2832 while ((p) && (item != p->q_next)) 2833 p = p->q_next; 2834 2835 if (p) { 2836 /* found a match */ 2837 p->q_next = item->q_next; 2838 2839 if (!item->q_next) 2840 queue->tail = p; 2841 2842 item->q_next = NULL; 2843 queue->count--; 2844 2845 return (item); 2846 } 2847 2848 return (NULL); 2849 } 2850 2851 /****************************************************************************/ 2852 /* */ 2853 /* Routine Name: ips_putq_wait_tail */ 2854 /* */ 2855 /* Routine Description: */ 2856 /* */ 2857 /* Add an item to the tail of the queue */ 2858 /* */ 2859 /* ASSUMED to be called from within the HA lock */ 2860 /* */ 2861 /****************************************************************************/ 2862 static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item) 2863 { 2864 METHOD_TRACE("ips_putq_wait_tail", 1); 2865 2866 if (!item) 2867 return; 2868 2869 item->host_scribble = NULL; 2870 2871 if (queue->tail) 2872 queue->tail->host_scribble = (char *) item; 2873 2874 queue->tail = item; 2875 2876 if (!queue->head) 2877 queue->head = item; 2878 2879 queue->count++; 2880 } 2881 2882 /****************************************************************************/ 2883 /* */ 2884 /* Routine Name: ips_removeq_wait_head */ 2885 /* */ 2886 /* Routine Description: */ 2887 /* */ 2888 /* Remove the head of the queue */ 2889 /* */ 2890 /* ASSUMED to be called from within the HA lock */ 2891 /* */ 2892 /****************************************************************************/ 2893 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue) 2894 { 2895 struct scsi_cmnd *item; 2896 2897 METHOD_TRACE("ips_removeq_wait_head", 1); 2898 2899 item = queue->head; 2900 2901 if (!item) { 2902 return (NULL); 2903 } 2904 2905 queue->head = (struct scsi_cmnd *) item->host_scribble; 2906 item->host_scribble = NULL; 2907 2908 if (queue->tail == item) 2909 queue->tail = NULL; 2910 2911 queue->count--; 2912 2913 return (item); 2914 } 2915 2916 /****************************************************************************/ 2917 /* */ 2918 /* Routine Name: ips_removeq_wait */ 2919 /* */ 2920 /* Routine Description: */ 2921 /* */ 2922 /* Remove an item from a queue */ 2923 /* */ 2924 /* ASSUMED to be called from within the HA lock */ 2925 /* */ 2926 /****************************************************************************/ 2927 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue, 2928 struct scsi_cmnd *item) 2929 { 2930 struct scsi_cmnd *p; 2931 2932 METHOD_TRACE("ips_removeq_wait", 1); 2933 2934 if (!item) 2935 return (NULL); 2936 2937 if (item == queue->head) { 2938 return (ips_removeq_wait_head(queue)); 2939 } 2940 2941 p = queue->head; 2942 2943 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble)) 2944 p = (struct scsi_cmnd *) p->host_scribble; 2945 2946 if (p) { 2947 /* found a match */ 2948 p->host_scribble = item->host_scribble; 2949 2950 if (!item->host_scribble) 2951 queue->tail = p; 2952 2953 item->host_scribble = NULL; 2954 queue->count--; 2955 2956 return (item); 2957 } 2958 2959 return (NULL); 2960 } 2961 2962 /****************************************************************************/ 2963 /* */ 2964 /* Routine Name: ips_putq_copp_tail */ 2965 /* */ 2966 /* Routine Description: */ 2967 /* */ 2968 /* Add an item to the tail of the queue */ 2969 /* */ 2970 /* ASSUMED to be called from within the HA lock */ 2971 /* */ 2972 /****************************************************************************/ 2973 static void 2974 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 2975 { 2976 METHOD_TRACE("ips_putq_copp_tail", 1); 2977 2978 if (!item) 2979 return; 2980 2981 item->next = NULL; 2982 2983 if (queue->tail) 2984 queue->tail->next = item; 2985 2986 queue->tail = item; 2987 2988 if (!queue->head) 2989 queue->head = item; 2990 2991 queue->count++; 2992 } 2993 2994 /****************************************************************************/ 2995 /* */ 2996 /* Routine Name: ips_removeq_copp_head */ 2997 /* */ 2998 /* Routine Description: */ 2999 /* */ 3000 /* Remove the head of the queue */ 3001 /* */ 3002 /* ASSUMED to be called from within the HA lock */ 3003 /* */ 3004 /****************************************************************************/ 3005 static ips_copp_wait_item_t * 3006 ips_removeq_copp_head(ips_copp_queue_t * queue) 3007 { 3008 ips_copp_wait_item_t *item; 3009 3010 METHOD_TRACE("ips_removeq_copp_head", 1); 3011 3012 item = queue->head; 3013 3014 if (!item) { 3015 return (NULL); 3016 } 3017 3018 queue->head = item->next; 3019 item->next = NULL; 3020 3021 if (queue->tail == item) 3022 queue->tail = NULL; 3023 3024 queue->count--; 3025 3026 return (item); 3027 } 3028 3029 /****************************************************************************/ 3030 /* */ 3031 /* Routine Name: ips_removeq_copp */ 3032 /* */ 3033 /* Routine Description: */ 3034 /* */ 3035 /* Remove an item from a queue */ 3036 /* */ 3037 /* ASSUMED to be called from within the HA lock */ 3038 /* */ 3039 /****************************************************************************/ 3040 static ips_copp_wait_item_t * 3041 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 3042 { 3043 ips_copp_wait_item_t *p; 3044 3045 METHOD_TRACE("ips_removeq_copp", 1); 3046 3047 if (!item) 3048 return (NULL); 3049 3050 if (item == queue->head) { 3051 return (ips_removeq_copp_head(queue)); 3052 } 3053 3054 p = queue->head; 3055 3056 while ((p) && (item != p->next)) 3057 p = p->next; 3058 3059 if (p) { 3060 /* found a match */ 3061 p->next = item->next; 3062 3063 if (!item->next) 3064 queue->tail = p; 3065 3066 item->next = NULL; 3067 queue->count--; 3068 3069 return (item); 3070 } 3071 3072 return (NULL); 3073 } 3074 3075 /****************************************************************************/ 3076 /* */ 3077 /* Routine Name: ipsintr_blocking */ 3078 /* */ 3079 /* Routine Description: */ 3080 /* */ 3081 /* Finalize an interrupt for internal commands */ 3082 /* */ 3083 /****************************************************************************/ 3084 static void 3085 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb) 3086 { 3087 METHOD_TRACE("ipsintr_blocking", 2); 3088 3089 ips_freescb(ha, scb); 3090 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) { 3091 ha->waitflag = FALSE; 3092 3093 return; 3094 } 3095 } 3096 3097 /****************************************************************************/ 3098 /* */ 3099 /* Routine Name: ipsintr_done */ 3100 /* */ 3101 /* Routine Description: */ 3102 /* */ 3103 /* Finalize an interrupt for non-internal commands */ 3104 /* */ 3105 /****************************************************************************/ 3106 static void 3107 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb) 3108 { 3109 METHOD_TRACE("ipsintr_done", 2); 3110 3111 if (!scb) { 3112 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3113 "Spurious interrupt; scb NULL.\n"); 3114 3115 return; 3116 } 3117 3118 if (scb->scsi_cmd == NULL) { 3119 /* unexpected interrupt */ 3120 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3121 "Spurious interrupt; scsi_cmd not set.\n"); 3122 3123 return; 3124 } 3125 3126 ips_done(ha, scb); 3127 } 3128 3129 /****************************************************************************/ 3130 /* */ 3131 /* Routine Name: ips_done */ 3132 /* */ 3133 /* Routine Description: */ 3134 /* */ 3135 /* Do housekeeping on completed commands */ 3136 /* ASSUMED to be called form within the request lock */ 3137 /****************************************************************************/ 3138 static void 3139 ips_done(ips_ha_t * ha, ips_scb_t * scb) 3140 { 3141 int ret; 3142 3143 METHOD_TRACE("ips_done", 1); 3144 3145 if (!scb) 3146 return; 3147 3148 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) { 3149 ips_cleanup_passthru(ha, scb); 3150 ha->num_ioctl--; 3151 } else { 3152 /* 3153 * Check to see if this command had too much 3154 * data and had to be broke up. If so, queue 3155 * the rest of the data and continue. 3156 */ 3157 if ((scb->breakup) || (scb->sg_break)) { 3158 struct scatterlist *sg; 3159 int i, sg_dma_index, ips_sg_index = 0; 3160 3161 /* we had a data breakup */ 3162 scb->data_len = 0; 3163 3164 sg = scsi_sglist(scb->scsi_cmd); 3165 3166 /* Spin forward to last dma chunk */ 3167 sg_dma_index = scb->breakup; 3168 for (i = 0; i < scb->breakup; i++) 3169 sg = sg_next(sg); 3170 3171 /* Take care of possible partial on last chunk */ 3172 ips_fill_scb_sg_single(ha, 3173 sg_dma_address(sg), 3174 scb, ips_sg_index++, 3175 sg_dma_len(sg)); 3176 3177 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd); 3178 sg_dma_index++, sg = sg_next(sg)) { 3179 if (ips_fill_scb_sg_single 3180 (ha, 3181 sg_dma_address(sg), 3182 scb, ips_sg_index++, 3183 sg_dma_len(sg)) < 0) 3184 break; 3185 } 3186 3187 scb->dcdb.transfer_length = scb->data_len; 3188 scb->dcdb.cmd_attribute |= 3189 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 3190 3191 if (!(scb->dcdb.cmd_attribute & 0x3)) 3192 scb->dcdb.transfer_length = 0; 3193 3194 if (scb->data_len >= IPS_MAX_XFER) { 3195 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 3196 scb->dcdb.transfer_length = 0; 3197 } 3198 3199 ret = ips_send_cmd(ha, scb); 3200 3201 switch (ret) { 3202 case IPS_FAILURE: 3203 if (scb->scsi_cmd) { 3204 scb->scsi_cmd->result = DID_ERROR << 16; 3205 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3206 } 3207 3208 ips_freescb(ha, scb); 3209 break; 3210 case IPS_SUCCESS_IMM: 3211 if (scb->scsi_cmd) { 3212 scb->scsi_cmd->result = DID_ERROR << 16; 3213 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3214 } 3215 3216 ips_freescb(ha, scb); 3217 break; 3218 default: 3219 break; 3220 } /* end case */ 3221 3222 return; 3223 } 3224 } /* end if passthru */ 3225 3226 if (scb->bus) { 3227 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id); 3228 } 3229 3230 scb->scsi_cmd->scsi_done(scb->scsi_cmd); 3231 3232 ips_freescb(ha, scb); 3233 } 3234 3235 /****************************************************************************/ 3236 /* */ 3237 /* Routine Name: ips_map_status */ 3238 /* */ 3239 /* Routine Description: */ 3240 /* */ 3241 /* Map Controller Error codes to Linux Error Codes */ 3242 /* */ 3243 /****************************************************************************/ 3244 static int 3245 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp) 3246 { 3247 int errcode; 3248 int device_error; 3249 uint32_t transfer_len; 3250 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3251 IPS_SCSI_INQ_DATA inquiryData; 3252 3253 METHOD_TRACE("ips_map_status", 1); 3254 3255 if (scb->bus) { 3256 DEBUG_VAR(2, 3257 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x", 3258 ips_name, ha->host_num, 3259 scb->scsi_cmd->device->channel, 3260 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun, 3261 scb->basic_status, scb->extended_status, 3262 scb->extended_status == 3263 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0, 3264 scb->extended_status == 3265 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0, 3266 scb->extended_status == 3267 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0); 3268 } 3269 3270 /* default driver error */ 3271 errcode = DID_ERROR; 3272 device_error = 0; 3273 3274 switch (scb->basic_status & IPS_GSC_STATUS_MASK) { 3275 case IPS_CMD_TIMEOUT: 3276 errcode = DID_TIME_OUT; 3277 break; 3278 3279 case IPS_INVAL_OPCO: 3280 case IPS_INVAL_CMD_BLK: 3281 case IPS_INVAL_PARM_BLK: 3282 case IPS_LD_ERROR: 3283 case IPS_CMD_CMPLT_WERROR: 3284 break; 3285 3286 case IPS_PHYS_DRV_ERROR: 3287 switch (scb->extended_status) { 3288 case IPS_ERR_SEL_TO: 3289 if (scb->bus) 3290 errcode = DID_NO_CONNECT; 3291 3292 break; 3293 3294 case IPS_ERR_OU_RUN: 3295 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) || 3296 (scb->cmd.dcdb.op_code == 3297 IPS_CMD_EXTENDED_DCDB_SG)) { 3298 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3299 transfer_len = tapeDCDB->transfer_length; 3300 } else { 3301 transfer_len = 3302 (uint32_t) scb->dcdb.transfer_length; 3303 } 3304 3305 if ((scb->bus) && (transfer_len < scb->data_len)) { 3306 /* Underrun - set default to no error */ 3307 errcode = DID_OK; 3308 3309 /* Restrict access to physical DASD */ 3310 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3311 ips_scmd_buf_read(scb->scsi_cmd, 3312 &inquiryData, sizeof (inquiryData)); 3313 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { 3314 errcode = DID_TIME_OUT; 3315 break; 3316 } 3317 } 3318 } else 3319 errcode = DID_ERROR; 3320 3321 break; 3322 3323 case IPS_ERR_RECOVERY: 3324 /* don't fail recovered errors */ 3325 if (scb->bus) 3326 errcode = DID_OK; 3327 3328 break; 3329 3330 case IPS_ERR_HOST_RESET: 3331 case IPS_ERR_DEV_RESET: 3332 errcode = DID_RESET; 3333 break; 3334 3335 case IPS_ERR_CKCOND: 3336 if (scb->bus) { 3337 if ((scb->cmd.dcdb.op_code == 3338 IPS_CMD_EXTENDED_DCDB) 3339 || (scb->cmd.dcdb.op_code == 3340 IPS_CMD_EXTENDED_DCDB_SG)) { 3341 tapeDCDB = 3342 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3343 memcpy(scb->scsi_cmd->sense_buffer, 3344 tapeDCDB->sense_info, 3345 SCSI_SENSE_BUFFERSIZE); 3346 } else { 3347 memcpy(scb->scsi_cmd->sense_buffer, 3348 scb->dcdb.sense_info, 3349 SCSI_SENSE_BUFFERSIZE); 3350 } 3351 device_error = 2; /* check condition */ 3352 } 3353 3354 errcode = DID_OK; 3355 3356 break; 3357 3358 default: 3359 errcode = DID_ERROR; 3360 break; 3361 3362 } /* end switch */ 3363 } /* end switch */ 3364 3365 scb->scsi_cmd->result = device_error | (errcode << 16); 3366 3367 return (1); 3368 } 3369 3370 /****************************************************************************/ 3371 /* */ 3372 /* Routine Name: ips_send_wait */ 3373 /* */ 3374 /* Routine Description: */ 3375 /* */ 3376 /* Send a command to the controller and wait for it to return */ 3377 /* */ 3378 /* The FFDC Time Stamp use this function for the callback, but doesn't */ 3379 /* actually need to wait. */ 3380 /****************************************************************************/ 3381 static int 3382 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) 3383 { 3384 int ret; 3385 3386 METHOD_TRACE("ips_send_wait", 1); 3387 3388 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */ 3389 ha->waitflag = TRUE; 3390 ha->cmd_in_progress = scb->cdb[0]; 3391 } 3392 scb->callback = ipsintr_blocking; 3393 ret = ips_send_cmd(ha, scb); 3394 3395 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)) 3396 return (ret); 3397 3398 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */ 3399 ret = ips_wait(ha, timeout, intr); 3400 3401 return (ret); 3402 } 3403 3404 /****************************************************************************/ 3405 /* */ 3406 /* Routine Name: ips_scmd_buf_write */ 3407 /* */ 3408 /* Routine Description: */ 3409 /* Write data to struct scsi_cmnd request_buffer at proper offsets */ 3410 /****************************************************************************/ 3411 static void 3412 ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count) 3413 { 3414 unsigned long flags; 3415 3416 local_irq_save(flags); 3417 scsi_sg_copy_from_buffer(scmd, data, count); 3418 local_irq_restore(flags); 3419 } 3420 3421 /****************************************************************************/ 3422 /* */ 3423 /* Routine Name: ips_scmd_buf_read */ 3424 /* */ 3425 /* Routine Description: */ 3426 /* Copy data from a struct scsi_cmnd to a new, linear buffer */ 3427 /****************************************************************************/ 3428 static void 3429 ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count) 3430 { 3431 unsigned long flags; 3432 3433 local_irq_save(flags); 3434 scsi_sg_copy_to_buffer(scmd, data, count); 3435 local_irq_restore(flags); 3436 } 3437 3438 /****************************************************************************/ 3439 /* */ 3440 /* Routine Name: ips_send_cmd */ 3441 /* */ 3442 /* Routine Description: */ 3443 /* */ 3444 /* Map SCSI commands to ServeRAID commands for logical drives */ 3445 /* */ 3446 /****************************************************************************/ 3447 static int 3448 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb) 3449 { 3450 int ret; 3451 char *sp; 3452 int device_error; 3453 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3454 int TimeOut; 3455 3456 METHOD_TRACE("ips_send_cmd", 1); 3457 3458 ret = IPS_SUCCESS; 3459 3460 if (!scb->scsi_cmd) { 3461 /* internal command */ 3462 3463 if (scb->bus > 0) { 3464 /* Controller commands can't be issued */ 3465 /* to real devices -- fail them */ 3466 if ((ha->waitflag == TRUE) && 3467 (ha->cmd_in_progress == scb->cdb[0])) { 3468 ha->waitflag = FALSE; 3469 } 3470 3471 return (1); 3472 } 3473 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) { 3474 /* command to logical bus -- interpret */ 3475 ret = IPS_SUCCESS_IMM; 3476 3477 switch (scb->scsi_cmd->cmnd[0]) { 3478 case ALLOW_MEDIUM_REMOVAL: 3479 case REZERO_UNIT: 3480 case ERASE: 3481 case WRITE_FILEMARKS: 3482 case SPACE: 3483 scb->scsi_cmd->result = DID_ERROR << 16; 3484 break; 3485 3486 case START_STOP: 3487 scb->scsi_cmd->result = DID_OK << 16; 3488 break; 3489 3490 case TEST_UNIT_READY: 3491 case INQUIRY: 3492 if (scb->target_id == IPS_ADAPTER_ID) { 3493 /* 3494 * Either we have a TUR 3495 * or we have a SCSI inquiry 3496 */ 3497 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY) 3498 scb->scsi_cmd->result = DID_OK << 16; 3499 3500 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3501 IPS_SCSI_INQ_DATA inquiry; 3502 3503 memset(&inquiry, 0, 3504 sizeof (IPS_SCSI_INQ_DATA)); 3505 3506 inquiry.DeviceType = 3507 IPS_SCSI_INQ_TYPE_PROCESSOR; 3508 inquiry.DeviceTypeQualifier = 3509 IPS_SCSI_INQ_LU_CONNECTED; 3510 inquiry.Version = IPS_SCSI_INQ_REV2; 3511 inquiry.ResponseDataFormat = 3512 IPS_SCSI_INQ_RD_REV2; 3513 inquiry.AdditionalLength = 31; 3514 inquiry.Flags[0] = 3515 IPS_SCSI_INQ_Address16; 3516 inquiry.Flags[1] = 3517 IPS_SCSI_INQ_WBus16 | 3518 IPS_SCSI_INQ_Sync; 3519 strncpy(inquiry.VendorId, "IBM ", 3520 8); 3521 strncpy(inquiry.ProductId, 3522 "SERVERAID ", 16); 3523 strncpy(inquiry.ProductRevisionLevel, 3524 "1.00", 4); 3525 3526 ips_scmd_buf_write(scb->scsi_cmd, 3527 &inquiry, 3528 sizeof (inquiry)); 3529 3530 scb->scsi_cmd->result = DID_OK << 16; 3531 } 3532 } else { 3533 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3534 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3535 scb->cmd.logical_info.reserved = 0; 3536 scb->cmd.logical_info.reserved2 = 0; 3537 scb->data_len = sizeof (IPS_LD_INFO); 3538 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3539 scb->flags = 0; 3540 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3541 ret = IPS_SUCCESS; 3542 } 3543 3544 break; 3545 3546 case REQUEST_SENSE: 3547 ips_reqsen(ha, scb); 3548 scb->scsi_cmd->result = DID_OK << 16; 3549 break; 3550 3551 case READ_6: 3552 case WRITE_6: 3553 if (!scb->sg_len) { 3554 scb->cmd.basic_io.op_code = 3555 (scb->scsi_cmd->cmnd[0] == 3556 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE; 3557 scb->cmd.basic_io.enhanced_sg = 0; 3558 scb->cmd.basic_io.sg_addr = 3559 cpu_to_le32(scb->data_busaddr); 3560 } else { 3561 scb->cmd.basic_io.op_code = 3562 (scb->scsi_cmd->cmnd[0] == 3563 READ_6) ? IPS_CMD_READ_SG : 3564 IPS_CMD_WRITE_SG; 3565 scb->cmd.basic_io.enhanced_sg = 3566 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3567 scb->cmd.basic_io.sg_addr = 3568 cpu_to_le32(scb->sg_busaddr); 3569 } 3570 3571 scb->cmd.basic_io.segment_4G = 0; 3572 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3573 scb->cmd.basic_io.log_drv = scb->target_id; 3574 scb->cmd.basic_io.sg_count = scb->sg_len; 3575 3576 if (scb->cmd.basic_io.lba) 3577 le32_add_cpu(&scb->cmd.basic_io.lba, 3578 le16_to_cpu(scb->cmd.basic_io. 3579 sector_count)); 3580 else 3581 scb->cmd.basic_io.lba = 3582 (((scb->scsi_cmd-> 3583 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd-> 3584 cmnd[2] << 8) | 3585 (scb->scsi_cmd->cmnd[3])); 3586 3587 scb->cmd.basic_io.sector_count = 3588 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3589 3590 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0) 3591 scb->cmd.basic_io.sector_count = 3592 cpu_to_le16(256); 3593 3594 ret = IPS_SUCCESS; 3595 break; 3596 3597 case READ_10: 3598 case WRITE_10: 3599 if (!scb->sg_len) { 3600 scb->cmd.basic_io.op_code = 3601 (scb->scsi_cmd->cmnd[0] == 3602 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE; 3603 scb->cmd.basic_io.enhanced_sg = 0; 3604 scb->cmd.basic_io.sg_addr = 3605 cpu_to_le32(scb->data_busaddr); 3606 } else { 3607 scb->cmd.basic_io.op_code = 3608 (scb->scsi_cmd->cmnd[0] == 3609 READ_10) ? IPS_CMD_READ_SG : 3610 IPS_CMD_WRITE_SG; 3611 scb->cmd.basic_io.enhanced_sg = 3612 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3613 scb->cmd.basic_io.sg_addr = 3614 cpu_to_le32(scb->sg_busaddr); 3615 } 3616 3617 scb->cmd.basic_io.segment_4G = 0; 3618 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3619 scb->cmd.basic_io.log_drv = scb->target_id; 3620 scb->cmd.basic_io.sg_count = scb->sg_len; 3621 3622 if (scb->cmd.basic_io.lba) 3623 le32_add_cpu(&scb->cmd.basic_io.lba, 3624 le16_to_cpu(scb->cmd.basic_io. 3625 sector_count)); 3626 else 3627 scb->cmd.basic_io.lba = 3628 ((scb->scsi_cmd->cmnd[2] << 24) | (scb-> 3629 scsi_cmd-> 3630 cmnd[3] 3631 << 16) | 3632 (scb->scsi_cmd->cmnd[4] << 8) | scb-> 3633 scsi_cmd->cmnd[5]); 3634 3635 scb->cmd.basic_io.sector_count = 3636 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3637 3638 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) { 3639 /* 3640 * This is a null condition 3641 * we don't have to do anything 3642 * so just return 3643 */ 3644 scb->scsi_cmd->result = DID_OK << 16; 3645 } else 3646 ret = IPS_SUCCESS; 3647 3648 break; 3649 3650 case RESERVE: 3651 case RELEASE: 3652 scb->scsi_cmd->result = DID_OK << 16; 3653 break; 3654 3655 case MODE_SENSE: 3656 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 3657 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3658 scb->cmd.basic_io.segment_4G = 0; 3659 scb->cmd.basic_io.enhanced_sg = 0; 3660 scb->data_len = sizeof (*ha->enq); 3661 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 3662 ret = IPS_SUCCESS; 3663 break; 3664 3665 case READ_CAPACITY: 3666 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3667 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3668 scb->cmd.logical_info.reserved = 0; 3669 scb->cmd.logical_info.reserved2 = 0; 3670 scb->cmd.logical_info.reserved3 = 0; 3671 scb->data_len = sizeof (IPS_LD_INFO); 3672 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3673 scb->flags = 0; 3674 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3675 ret = IPS_SUCCESS; 3676 break; 3677 3678 case SEND_DIAGNOSTIC: 3679 case REASSIGN_BLOCKS: 3680 case FORMAT_UNIT: 3681 case SEEK_10: 3682 case VERIFY: 3683 case READ_DEFECT_DATA: 3684 case READ_BUFFER: 3685 case WRITE_BUFFER: 3686 scb->scsi_cmd->result = DID_OK << 16; 3687 break; 3688 3689 default: 3690 /* Set the Return Info to appear like the Command was */ 3691 /* attempted, a Check Condition occurred, and Sense */ 3692 /* Data indicating an Invalid CDB OpCode is returned. */ 3693 sp = (char *) scb->scsi_cmd->sense_buffer; 3694 3695 sp[0] = 0x70; /* Error Code */ 3696 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ 3697 sp[7] = 0x0A; /* Additional Sense Length */ 3698 sp[12] = 0x20; /* ASC = Invalid OpCode */ 3699 sp[13] = 0x00; /* ASCQ */ 3700 3701 device_error = 2; /* Indicate Check Condition */ 3702 scb->scsi_cmd->result = device_error | (DID_OK << 16); 3703 break; 3704 } /* end switch */ 3705 } 3706 /* end if */ 3707 if (ret == IPS_SUCCESS_IMM) 3708 return (ret); 3709 3710 /* setup DCDB */ 3711 if (scb->bus > 0) { 3712 3713 /* If we already know the Device is Not there, no need to attempt a Command */ 3714 /* This also protects an NT FailOver Controller from getting CDB's sent to it */ 3715 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) { 3716 scb->scsi_cmd->result = DID_NO_CONNECT << 16; 3717 return (IPS_SUCCESS_IMM); 3718 } 3719 3720 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id); 3721 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb); 3722 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 3723 (unsigned long) &scb-> 3724 dcdb - 3725 (unsigned long) scb); 3726 scb->cmd.dcdb.reserved = 0; 3727 scb->cmd.dcdb.reserved2 = 0; 3728 scb->cmd.dcdb.reserved3 = 0; 3729 scb->cmd.dcdb.segment_4G = 0; 3730 scb->cmd.dcdb.enhanced_sg = 0; 3731 3732 TimeOut = scb->scsi_cmd->request->timeout; 3733 3734 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */ 3735 if (!scb->sg_len) { 3736 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB; 3737 } else { 3738 scb->cmd.dcdb.op_code = 3739 IPS_CMD_EXTENDED_DCDB_SG; 3740 scb->cmd.dcdb.enhanced_sg = 3741 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3742 } 3743 3744 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */ 3745 tapeDCDB->device_address = 3746 ((scb->bus - 1) << 4) | scb->target_id; 3747 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED; 3748 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */ 3749 3750 if (TimeOut) { 3751 if (TimeOut < (10 * HZ)) 3752 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 3753 else if (TimeOut < (60 * HZ)) 3754 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 3755 else if (TimeOut < (1200 * HZ)) 3756 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 3757 } 3758 3759 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len; 3760 tapeDCDB->reserved_for_LUN = 0; 3761 tapeDCDB->transfer_length = scb->data_len; 3762 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG) 3763 tapeDCDB->buffer_pointer = 3764 cpu_to_le32(scb->sg_busaddr); 3765 else 3766 tapeDCDB->buffer_pointer = 3767 cpu_to_le32(scb->data_busaddr); 3768 tapeDCDB->sg_count = scb->sg_len; 3769 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info); 3770 tapeDCDB->scsi_status = 0; 3771 tapeDCDB->reserved = 0; 3772 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd, 3773 scb->scsi_cmd->cmd_len); 3774 } else { 3775 if (!scb->sg_len) { 3776 scb->cmd.dcdb.op_code = IPS_CMD_DCDB; 3777 } else { 3778 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG; 3779 scb->cmd.dcdb.enhanced_sg = 3780 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3781 } 3782 3783 scb->dcdb.device_address = 3784 ((scb->bus - 1) << 4) | scb->target_id; 3785 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED; 3786 3787 if (TimeOut) { 3788 if (TimeOut < (10 * HZ)) 3789 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 3790 else if (TimeOut < (60 * HZ)) 3791 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 3792 else if (TimeOut < (1200 * HZ)) 3793 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 3794 } 3795 3796 scb->dcdb.transfer_length = scb->data_len; 3797 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K) 3798 scb->dcdb.transfer_length = 0; 3799 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG) 3800 scb->dcdb.buffer_pointer = 3801 cpu_to_le32(scb->sg_busaddr); 3802 else 3803 scb->dcdb.buffer_pointer = 3804 cpu_to_le32(scb->data_busaddr); 3805 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len; 3806 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info); 3807 scb->dcdb.sg_count = scb->sg_len; 3808 scb->dcdb.reserved = 0; 3809 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd, 3810 scb->scsi_cmd->cmd_len); 3811 scb->dcdb.scsi_status = 0; 3812 scb->dcdb.reserved2[0] = 0; 3813 scb->dcdb.reserved2[1] = 0; 3814 scb->dcdb.reserved2[2] = 0; 3815 } 3816 } 3817 3818 return ((*ha->func.issue) (ha, scb)); 3819 } 3820 3821 /****************************************************************************/ 3822 /* */ 3823 /* Routine Name: ips_chk_status */ 3824 /* */ 3825 /* Routine Description: */ 3826 /* */ 3827 /* Check the status of commands to logical drives */ 3828 /* Assumed to be called with the HA lock */ 3829 /****************************************************************************/ 3830 static void 3831 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus) 3832 { 3833 ips_scb_t *scb; 3834 ips_stat_t *sp; 3835 uint8_t basic_status; 3836 uint8_t ext_status; 3837 int errcode; 3838 IPS_SCSI_INQ_DATA inquiryData; 3839 3840 METHOD_TRACE("ips_chkstatus", 1); 3841 3842 scb = &ha->scbs[pstatus->fields.command_id]; 3843 scb->basic_status = basic_status = 3844 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK; 3845 scb->extended_status = ext_status = pstatus->fields.extended_status; 3846 3847 sp = &ha->sp; 3848 sp->residue_len = 0; 3849 sp->scb_addr = (void *) scb; 3850 3851 /* Remove the item from the active queue */ 3852 ips_removeq_scb(&ha->scb_activelist, scb); 3853 3854 if (!scb->scsi_cmd) 3855 /* internal commands are handled in do_ipsintr */ 3856 return; 3857 3858 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)", 3859 ips_name, 3860 ha->host_num, 3861 scb->cdb[0], 3862 scb->cmd.basic_io.command_id, 3863 scb->bus, scb->target_id, scb->lun); 3864 3865 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) 3866 /* passthru - just returns the raw result */ 3867 return; 3868 3869 errcode = DID_OK; 3870 3871 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) || 3872 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) { 3873 3874 if (scb->bus == 0) { 3875 if ((basic_status & IPS_GSC_STATUS_MASK) == 3876 IPS_CMD_RECOVERED_ERROR) { 3877 DEBUG_VAR(1, 3878 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 3879 ips_name, ha->host_num, 3880 scb->cmd.basic_io.op_code, 3881 basic_status, ext_status); 3882 } 3883 3884 switch (scb->scsi_cmd->cmnd[0]) { 3885 case ALLOW_MEDIUM_REMOVAL: 3886 case REZERO_UNIT: 3887 case ERASE: 3888 case WRITE_FILEMARKS: 3889 case SPACE: 3890 errcode = DID_ERROR; 3891 break; 3892 3893 case START_STOP: 3894 break; 3895 3896 case TEST_UNIT_READY: 3897 if (!ips_online(ha, scb)) { 3898 errcode = DID_TIME_OUT; 3899 } 3900 break; 3901 3902 case INQUIRY: 3903 if (ips_online(ha, scb)) { 3904 ips_inquiry(ha, scb); 3905 } else { 3906 errcode = DID_TIME_OUT; 3907 } 3908 break; 3909 3910 case REQUEST_SENSE: 3911 ips_reqsen(ha, scb); 3912 break; 3913 3914 case READ_6: 3915 case WRITE_6: 3916 case READ_10: 3917 case WRITE_10: 3918 case RESERVE: 3919 case RELEASE: 3920 break; 3921 3922 case MODE_SENSE: 3923 if (!ips_online(ha, scb) 3924 || !ips_msense(ha, scb)) { 3925 errcode = DID_ERROR; 3926 } 3927 break; 3928 3929 case READ_CAPACITY: 3930 if (ips_online(ha, scb)) 3931 ips_rdcap(ha, scb); 3932 else { 3933 errcode = DID_TIME_OUT; 3934 } 3935 break; 3936 3937 case SEND_DIAGNOSTIC: 3938 case REASSIGN_BLOCKS: 3939 break; 3940 3941 case FORMAT_UNIT: 3942 errcode = DID_ERROR; 3943 break; 3944 3945 case SEEK_10: 3946 case VERIFY: 3947 case READ_DEFECT_DATA: 3948 case READ_BUFFER: 3949 case WRITE_BUFFER: 3950 break; 3951 3952 default: 3953 errcode = DID_ERROR; 3954 } /* end switch */ 3955 3956 scb->scsi_cmd->result = errcode << 16; 3957 } else { /* bus == 0 */ 3958 /* restrict access to physical drives */ 3959 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3960 ips_scmd_buf_read(scb->scsi_cmd, 3961 &inquiryData, sizeof (inquiryData)); 3962 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) 3963 scb->scsi_cmd->result = DID_TIME_OUT << 16; 3964 } 3965 } /* else */ 3966 } else { /* recovered error / success */ 3967 if (scb->bus == 0) { 3968 DEBUG_VAR(1, 3969 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 3970 ips_name, ha->host_num, 3971 scb->cmd.basic_io.op_code, basic_status, 3972 ext_status); 3973 } 3974 3975 ips_map_status(ha, scb, sp); 3976 } /* else */ 3977 } 3978 3979 /****************************************************************************/ 3980 /* */ 3981 /* Routine Name: ips_online */ 3982 /* */ 3983 /* Routine Description: */ 3984 /* */ 3985 /* Determine if a logical drive is online */ 3986 /* */ 3987 /****************************************************************************/ 3988 static int 3989 ips_online(ips_ha_t * ha, ips_scb_t * scb) 3990 { 3991 METHOD_TRACE("ips_online", 1); 3992 3993 if (scb->target_id >= IPS_MAX_LD) 3994 return (0); 3995 3996 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) { 3997 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO)); 3998 return (0); 3999 } 4000 4001 if (ha->logical_drive_info->drive_info[scb->target_id].state != 4002 IPS_LD_OFFLINE 4003 && ha->logical_drive_info->drive_info[scb->target_id].state != 4004 IPS_LD_FREE 4005 && ha->logical_drive_info->drive_info[scb->target_id].state != 4006 IPS_LD_CRS 4007 && ha->logical_drive_info->drive_info[scb->target_id].state != 4008 IPS_LD_SYS) 4009 return (1); 4010 else 4011 return (0); 4012 } 4013 4014 /****************************************************************************/ 4015 /* */ 4016 /* Routine Name: ips_inquiry */ 4017 /* */ 4018 /* Routine Description: */ 4019 /* */ 4020 /* Simulate an inquiry command to a logical drive */ 4021 /* */ 4022 /****************************************************************************/ 4023 static int 4024 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb) 4025 { 4026 IPS_SCSI_INQ_DATA inquiry; 4027 4028 METHOD_TRACE("ips_inquiry", 1); 4029 4030 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA)); 4031 4032 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD; 4033 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED; 4034 inquiry.Version = IPS_SCSI_INQ_REV2; 4035 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2; 4036 inquiry.AdditionalLength = 31; 4037 inquiry.Flags[0] = IPS_SCSI_INQ_Address16; 4038 inquiry.Flags[1] = 4039 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue; 4040 strncpy(inquiry.VendorId, "IBM ", 8); 4041 strncpy(inquiry.ProductId, "SERVERAID ", 16); 4042 strncpy(inquiry.ProductRevisionLevel, "1.00", 4); 4043 4044 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry)); 4045 4046 return (1); 4047 } 4048 4049 /****************************************************************************/ 4050 /* */ 4051 /* Routine Name: ips_rdcap */ 4052 /* */ 4053 /* Routine Description: */ 4054 /* */ 4055 /* Simulate a read capacity command to a logical drive */ 4056 /* */ 4057 /****************************************************************************/ 4058 static int 4059 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb) 4060 { 4061 IPS_SCSI_CAPACITY cap; 4062 4063 METHOD_TRACE("ips_rdcap", 1); 4064 4065 if (scsi_bufflen(scb->scsi_cmd) < 8) 4066 return (0); 4067 4068 cap.lba = 4069 cpu_to_be32(le32_to_cpu 4070 (ha->logical_drive_info-> 4071 drive_info[scb->target_id].sector_count) - 1); 4072 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); 4073 4074 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap)); 4075 4076 return (1); 4077 } 4078 4079 /****************************************************************************/ 4080 /* */ 4081 /* Routine Name: ips_msense */ 4082 /* */ 4083 /* Routine Description: */ 4084 /* */ 4085 /* Simulate a mode sense command to a logical drive */ 4086 /* */ 4087 /****************************************************************************/ 4088 static int 4089 ips_msense(ips_ha_t * ha, ips_scb_t * scb) 4090 { 4091 uint16_t heads; 4092 uint16_t sectors; 4093 uint32_t cylinders; 4094 IPS_SCSI_MODE_PAGE_DATA mdata; 4095 4096 METHOD_TRACE("ips_msense", 1); 4097 4098 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 && 4099 (ha->enq->ucMiscFlag & 0x8) == 0) { 4100 heads = IPS_NORM_HEADS; 4101 sectors = IPS_NORM_SECTORS; 4102 } else { 4103 heads = IPS_COMP_HEADS; 4104 sectors = IPS_COMP_SECTORS; 4105 } 4106 4107 cylinders = 4108 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) - 4109 1) / (heads * sectors); 4110 4111 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA)); 4112 4113 mdata.hdr.BlockDescLength = 8; 4114 4115 switch (scb->scsi_cmd->cmnd[2] & 0x3f) { 4116 case 0x03: /* page 3 */ 4117 mdata.pdata.pg3.PageCode = 3; 4118 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3); 4119 mdata.hdr.DataLength = 4120 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength; 4121 mdata.pdata.pg3.TracksPerZone = 0; 4122 mdata.pdata.pg3.AltSectorsPerZone = 0; 4123 mdata.pdata.pg3.AltTracksPerZone = 0; 4124 mdata.pdata.pg3.AltTracksPerVolume = 0; 4125 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors); 4126 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE); 4127 mdata.pdata.pg3.Interleave = cpu_to_be16(1); 4128 mdata.pdata.pg3.TrackSkew = 0; 4129 mdata.pdata.pg3.CylinderSkew = 0; 4130 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector; 4131 break; 4132 4133 case 0x4: 4134 mdata.pdata.pg4.PageCode = 4; 4135 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4); 4136 mdata.hdr.DataLength = 4137 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength; 4138 mdata.pdata.pg4.CylindersHigh = 4139 cpu_to_be16((cylinders >> 8) & 0xFFFF); 4140 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF); 4141 mdata.pdata.pg4.Heads = heads; 4142 mdata.pdata.pg4.WritePrecompHigh = 0; 4143 mdata.pdata.pg4.WritePrecompLow = 0; 4144 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0; 4145 mdata.pdata.pg4.ReducedWriteCurrentLow = 0; 4146 mdata.pdata.pg4.StepRate = cpu_to_be16(1); 4147 mdata.pdata.pg4.LandingZoneHigh = 0; 4148 mdata.pdata.pg4.LandingZoneLow = 0; 4149 mdata.pdata.pg4.flags = 0; 4150 mdata.pdata.pg4.RotationalOffset = 0; 4151 mdata.pdata.pg4.MediumRotationRate = 0; 4152 break; 4153 case 0x8: 4154 mdata.pdata.pg8.PageCode = 8; 4155 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8); 4156 mdata.hdr.DataLength = 4157 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength; 4158 /* everything else is left set to 0 */ 4159 break; 4160 4161 default: 4162 return (0); 4163 } /* end switch */ 4164 4165 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata)); 4166 4167 return (1); 4168 } 4169 4170 /****************************************************************************/ 4171 /* */ 4172 /* Routine Name: ips_reqsen */ 4173 /* */ 4174 /* Routine Description: */ 4175 /* */ 4176 /* Simulate a request sense command to a logical drive */ 4177 /* */ 4178 /****************************************************************************/ 4179 static int 4180 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb) 4181 { 4182 IPS_SCSI_REQSEN reqsen; 4183 4184 METHOD_TRACE("ips_reqsen", 1); 4185 4186 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN)); 4187 4188 reqsen.ResponseCode = 4189 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR; 4190 reqsen.AdditionalLength = 10; 4191 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE; 4192 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE; 4193 4194 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen)); 4195 4196 return (1); 4197 } 4198 4199 /****************************************************************************/ 4200 /* */ 4201 /* Routine Name: ips_free */ 4202 /* */ 4203 /* Routine Description: */ 4204 /* */ 4205 /* Free any allocated space for this controller */ 4206 /* */ 4207 /****************************************************************************/ 4208 static void 4209 ips_free(ips_ha_t * ha) 4210 { 4211 4212 METHOD_TRACE("ips_free", 1); 4213 4214 if (ha) { 4215 if (ha->enq) { 4216 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ), 4217 ha->enq, ha->enq_busaddr); 4218 ha->enq = NULL; 4219 } 4220 4221 kfree(ha->conf); 4222 ha->conf = NULL; 4223 4224 if (ha->adapt) { 4225 dma_free_coherent(&ha->pcidev->dev, 4226 sizeof (IPS_ADAPTER) + 4227 sizeof (IPS_IO_CMD), ha->adapt, 4228 ha->adapt->hw_status_start); 4229 ha->adapt = NULL; 4230 } 4231 4232 if (ha->logical_drive_info) { 4233 dma_free_coherent(&ha->pcidev->dev, 4234 sizeof (IPS_LD_INFO), 4235 ha->logical_drive_info, 4236 ha->logical_drive_info_dma_addr); 4237 ha->logical_drive_info = NULL; 4238 } 4239 4240 kfree(ha->nvram); 4241 ha->nvram = NULL; 4242 4243 kfree(ha->subsys); 4244 ha->subsys = NULL; 4245 4246 if (ha->ioctl_data) { 4247 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len, 4248 ha->ioctl_data, ha->ioctl_busaddr); 4249 ha->ioctl_data = NULL; 4250 ha->ioctl_datasize = 0; 4251 ha->ioctl_len = 0; 4252 } 4253 ips_deallocatescbs(ha, ha->max_cmds); 4254 4255 /* free memory mapped (if applicable) */ 4256 if (ha->mem_ptr) { 4257 iounmap(ha->ioremap_ptr); 4258 ha->ioremap_ptr = NULL; 4259 ha->mem_ptr = NULL; 4260 } 4261 4262 ha->mem_addr = 0; 4263 4264 } 4265 } 4266 4267 /****************************************************************************/ 4268 /* */ 4269 /* Routine Name: ips_deallocatescbs */ 4270 /* */ 4271 /* Routine Description: */ 4272 /* */ 4273 /* Free the command blocks */ 4274 /* */ 4275 /****************************************************************************/ 4276 static int 4277 ips_deallocatescbs(ips_ha_t * ha, int cmds) 4278 { 4279 if (ha->scbs) { 4280 dma_free_coherent(&ha->pcidev->dev, 4281 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds, 4282 ha->scbs->sg_list.list, 4283 ha->scbs->sg_busaddr); 4284 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds, 4285 ha->scbs, ha->scbs->scb_busaddr); 4286 ha->scbs = NULL; 4287 } /* end if */ 4288 return 1; 4289 } 4290 4291 /****************************************************************************/ 4292 /* */ 4293 /* Routine Name: ips_allocatescbs */ 4294 /* */ 4295 /* Routine Description: */ 4296 /* */ 4297 /* Allocate the command blocks */ 4298 /* */ 4299 /****************************************************************************/ 4300 static int 4301 ips_allocatescbs(ips_ha_t * ha) 4302 { 4303 ips_scb_t *scb_p; 4304 IPS_SG_LIST ips_sg; 4305 int i; 4306 dma_addr_t command_dma, sg_dma; 4307 4308 METHOD_TRACE("ips_allocatescbs", 1); 4309 4310 /* Allocate memory for the SCBs */ 4311 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev, 4312 ha->max_cmds * sizeof (ips_scb_t), 4313 &command_dma, GFP_KERNEL); 4314 if (ha->scbs == NULL) 4315 return 0; 4316 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev, 4317 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds, 4318 &sg_dma, GFP_KERNEL); 4319 if (ips_sg.list == NULL) { 4320 dma_free_coherent(&ha->pcidev->dev, 4321 ha->max_cmds * sizeof (ips_scb_t), ha->scbs, 4322 command_dma); 4323 return 0; 4324 } 4325 4326 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t)); 4327 4328 for (i = 0; i < ha->max_cmds; i++) { 4329 scb_p = &ha->scbs[i]; 4330 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i; 4331 /* set up S/G list */ 4332 if (IPS_USE_ENH_SGLIST(ha)) { 4333 scb_p->sg_list.enh_list = 4334 ips_sg.enh_list + i * IPS_MAX_SG; 4335 scb_p->sg_busaddr = 4336 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4337 } else { 4338 scb_p->sg_list.std_list = 4339 ips_sg.std_list + i * IPS_MAX_SG; 4340 scb_p->sg_busaddr = 4341 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4342 } 4343 4344 /* add to the free list */ 4345 if (i < ha->max_cmds - 1) { 4346 scb_p->q_next = ha->scb_freelist; 4347 ha->scb_freelist = scb_p; 4348 } 4349 } 4350 4351 /* success */ 4352 return (1); 4353 } 4354 4355 /****************************************************************************/ 4356 /* */ 4357 /* Routine Name: ips_init_scb */ 4358 /* */ 4359 /* Routine Description: */ 4360 /* */ 4361 /* Initialize a CCB to default values */ 4362 /* */ 4363 /****************************************************************************/ 4364 static void 4365 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb) 4366 { 4367 IPS_SG_LIST sg_list; 4368 uint32_t cmd_busaddr, sg_busaddr; 4369 METHOD_TRACE("ips_init_scb", 1); 4370 4371 if (scb == NULL) 4372 return; 4373 4374 sg_list.list = scb->sg_list.list; 4375 cmd_busaddr = scb->scb_busaddr; 4376 sg_busaddr = scb->sg_busaddr; 4377 /* zero fill */ 4378 memset(scb, 0, sizeof (ips_scb_t)); 4379 memset(ha->dummy, 0, sizeof (IPS_IO_CMD)); 4380 4381 /* Initialize dummy command bucket */ 4382 ha->dummy->op_code = 0xFF; 4383 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start 4384 + sizeof (IPS_ADAPTER)); 4385 ha->dummy->command_id = IPS_MAX_CMDS; 4386 4387 /* set bus address of scb */ 4388 scb->scb_busaddr = cmd_busaddr; 4389 scb->sg_busaddr = sg_busaddr; 4390 scb->sg_list.list = sg_list.list; 4391 4392 /* Neptune Fix */ 4393 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); 4394 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start 4395 + sizeof (IPS_ADAPTER)); 4396 } 4397 4398 /****************************************************************************/ 4399 /* */ 4400 /* Routine Name: ips_get_scb */ 4401 /* */ 4402 /* Routine Description: */ 4403 /* */ 4404 /* Initialize a CCB to default values */ 4405 /* */ 4406 /* ASSUMED to be called from within a lock */ 4407 /* */ 4408 /****************************************************************************/ 4409 static ips_scb_t * 4410 ips_getscb(ips_ha_t * ha) 4411 { 4412 ips_scb_t *scb; 4413 4414 METHOD_TRACE("ips_getscb", 1); 4415 4416 if ((scb = ha->scb_freelist) == NULL) { 4417 4418 return (NULL); 4419 } 4420 4421 ha->scb_freelist = scb->q_next; 4422 scb->flags = 0; 4423 scb->q_next = NULL; 4424 4425 ips_init_scb(ha, scb); 4426 4427 return (scb); 4428 } 4429 4430 /****************************************************************************/ 4431 /* */ 4432 /* Routine Name: ips_free_scb */ 4433 /* */ 4434 /* Routine Description: */ 4435 /* */ 4436 /* Return an unused CCB back to the free list */ 4437 /* */ 4438 /* ASSUMED to be called from within a lock */ 4439 /* */ 4440 /****************************************************************************/ 4441 static void 4442 ips_freescb(ips_ha_t * ha, ips_scb_t * scb) 4443 { 4444 4445 METHOD_TRACE("ips_freescb", 1); 4446 if (scb->flags & IPS_SCB_MAP_SG) 4447 scsi_dma_unmap(scb->scsi_cmd); 4448 else if (scb->flags & IPS_SCB_MAP_SINGLE) 4449 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr, 4450 scb->data_len, IPS_DMA_DIR(scb)); 4451 4452 /* check to make sure this is not our "special" scb */ 4453 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) { 4454 scb->q_next = ha->scb_freelist; 4455 ha->scb_freelist = scb; 4456 } 4457 } 4458 4459 /****************************************************************************/ 4460 /* */ 4461 /* Routine Name: ips_isinit_copperhead */ 4462 /* */ 4463 /* Routine Description: */ 4464 /* */ 4465 /* Is controller initialized ? */ 4466 /* */ 4467 /****************************************************************************/ 4468 static int 4469 ips_isinit_copperhead(ips_ha_t * ha) 4470 { 4471 uint8_t scpr; 4472 uint8_t isr; 4473 4474 METHOD_TRACE("ips_isinit_copperhead", 1); 4475 4476 isr = inb(ha->io_addr + IPS_REG_HISR); 4477 scpr = inb(ha->io_addr + IPS_REG_SCPR); 4478 4479 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4480 return (0); 4481 else 4482 return (1); 4483 } 4484 4485 /****************************************************************************/ 4486 /* */ 4487 /* Routine Name: ips_isinit_copperhead_memio */ 4488 /* */ 4489 /* Routine Description: */ 4490 /* */ 4491 /* Is controller initialized ? */ 4492 /* */ 4493 /****************************************************************************/ 4494 static int 4495 ips_isinit_copperhead_memio(ips_ha_t * ha) 4496 { 4497 uint8_t isr = 0; 4498 uint8_t scpr; 4499 4500 METHOD_TRACE("ips_is_init_copperhead_memio", 1); 4501 4502 isr = readb(ha->mem_ptr + IPS_REG_HISR); 4503 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); 4504 4505 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4506 return (0); 4507 else 4508 return (1); 4509 } 4510 4511 /****************************************************************************/ 4512 /* */ 4513 /* Routine Name: ips_isinit_morpheus */ 4514 /* */ 4515 /* Routine Description: */ 4516 /* */ 4517 /* Is controller initialized ? */ 4518 /* */ 4519 /****************************************************************************/ 4520 static int 4521 ips_isinit_morpheus(ips_ha_t * ha) 4522 { 4523 uint32_t post; 4524 uint32_t bits; 4525 4526 METHOD_TRACE("ips_is_init_morpheus", 1); 4527 4528 if (ips_isintr_morpheus(ha)) 4529 ips_flush_and_reset(ha); 4530 4531 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4532 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4533 4534 if (post == 0) 4535 return (0); 4536 else if (bits & 0x3) 4537 return (0); 4538 else 4539 return (1); 4540 } 4541 4542 /****************************************************************************/ 4543 /* */ 4544 /* Routine Name: ips_flush_and_reset */ 4545 /* */ 4546 /* Routine Description: */ 4547 /* */ 4548 /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */ 4549 /* state ( was trying to INIT and an interrupt was already pending ) ... */ 4550 /* */ 4551 /****************************************************************************/ 4552 static void 4553 ips_flush_and_reset(ips_ha_t *ha) 4554 { 4555 ips_scb_t *scb; 4556 int ret; 4557 int time; 4558 int done; 4559 dma_addr_t command_dma; 4560 4561 /* Create a usuable SCB */ 4562 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), 4563 &command_dma, GFP_KERNEL); 4564 if (scb) { 4565 memset(scb, 0, sizeof(ips_scb_t)); 4566 ips_init_scb(ha, scb); 4567 scb->scb_busaddr = command_dma; 4568 4569 scb->timeout = ips_cmd_timeout; 4570 scb->cdb[0] = IPS_CMD_FLUSH; 4571 4572 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 4573 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */ 4574 scb->cmd.flush_cache.state = IPS_NORM_STATE; 4575 scb->cmd.flush_cache.reserved = 0; 4576 scb->cmd.flush_cache.reserved2 = 0; 4577 scb->cmd.flush_cache.reserved3 = 0; 4578 scb->cmd.flush_cache.reserved4 = 0; 4579 4580 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */ 4581 4582 if (ret == IPS_SUCCESS) { 4583 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ 4584 done = 0; 4585 4586 while ((time > 0) && (!done)) { 4587 done = ips_poll_for_flush_complete(ha); 4588 /* This may look evil, but it's only done during extremely rare start-up conditions ! */ 4589 udelay(1000); 4590 time--; 4591 } 4592 } 4593 } 4594 4595 /* Now RESET and INIT the adapter */ 4596 (*ha->func.reset) (ha); 4597 4598 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma); 4599 return; 4600 } 4601 4602 /****************************************************************************/ 4603 /* */ 4604 /* Routine Name: ips_poll_for_flush_complete */ 4605 /* */ 4606 /* Routine Description: */ 4607 /* */ 4608 /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */ 4609 /* All other responses are just taken off the queue and ignored */ 4610 /* */ 4611 /****************************************************************************/ 4612 static int 4613 ips_poll_for_flush_complete(ips_ha_t * ha) 4614 { 4615 IPS_STATUS cstatus; 4616 4617 while (TRUE) { 4618 cstatus.value = (*ha->func.statupd) (ha); 4619 4620 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ 4621 break; 4622 4623 /* Success is when we see the Flush Command ID */ 4624 if (cstatus.fields.command_id == IPS_MAX_CMDS) 4625 return 1; 4626 } 4627 4628 return 0; 4629 } 4630 4631 /****************************************************************************/ 4632 /* */ 4633 /* Routine Name: ips_enable_int_copperhead */ 4634 /* */ 4635 /* Routine Description: */ 4636 /* Turn on interrupts */ 4637 /* */ 4638 /****************************************************************************/ 4639 static void 4640 ips_enable_int_copperhead(ips_ha_t * ha) 4641 { 4642 METHOD_TRACE("ips_enable_int_copperhead", 1); 4643 4644 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI); 4645 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4646 } 4647 4648 /****************************************************************************/ 4649 /* */ 4650 /* Routine Name: ips_enable_int_copperhead_memio */ 4651 /* */ 4652 /* Routine Description: */ 4653 /* Turn on interrupts */ 4654 /* */ 4655 /****************************************************************************/ 4656 static void 4657 ips_enable_int_copperhead_memio(ips_ha_t * ha) 4658 { 4659 METHOD_TRACE("ips_enable_int_copperhead_memio", 1); 4660 4661 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4662 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4663 } 4664 4665 /****************************************************************************/ 4666 /* */ 4667 /* Routine Name: ips_enable_int_morpheus */ 4668 /* */ 4669 /* Routine Description: */ 4670 /* Turn on interrupts */ 4671 /* */ 4672 /****************************************************************************/ 4673 static void 4674 ips_enable_int_morpheus(ips_ha_t * ha) 4675 { 4676 uint32_t Oimr; 4677 4678 METHOD_TRACE("ips_enable_int_morpheus", 1); 4679 4680 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4681 Oimr &= ~0x08; 4682 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4683 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ 4684 } 4685 4686 /****************************************************************************/ 4687 /* */ 4688 /* Routine Name: ips_init_copperhead */ 4689 /* */ 4690 /* Routine Description: */ 4691 /* */ 4692 /* Initialize a copperhead controller */ 4693 /* */ 4694 /****************************************************************************/ 4695 static int 4696 ips_init_copperhead(ips_ha_t * ha) 4697 { 4698 uint8_t Isr; 4699 uint8_t Cbsp; 4700 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4701 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; 4702 int i, j; 4703 4704 METHOD_TRACE("ips_init_copperhead", 1); 4705 4706 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4707 for (j = 0; j < 45; j++) { 4708 Isr = inb(ha->io_addr + IPS_REG_HISR); 4709 if (Isr & IPS_BIT_GHI) 4710 break; 4711 4712 /* Delay for 1 Second */ 4713 MDELAY(IPS_ONE_SEC); 4714 } 4715 4716 if (j >= 45) 4717 /* error occurred */ 4718 return (0); 4719 4720 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 4721 outb(Isr, ha->io_addr + IPS_REG_HISR); 4722 } 4723 4724 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 4725 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4726 "reset controller fails (post status %x %x).\n", 4727 PostByte[0], PostByte[1]); 4728 4729 return (0); 4730 } 4731 4732 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 4733 for (j = 0; j < 240; j++) { 4734 Isr = inb(ha->io_addr + IPS_REG_HISR); 4735 if (Isr & IPS_BIT_GHI) 4736 break; 4737 4738 /* Delay for 1 Second */ 4739 MDELAY(IPS_ONE_SEC); 4740 } 4741 4742 if (j >= 240) 4743 /* error occurred */ 4744 return (0); 4745 4746 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 4747 outb(Isr, ha->io_addr + IPS_REG_HISR); 4748 } 4749 4750 for (i = 0; i < 240; i++) { 4751 Cbsp = inb(ha->io_addr + IPS_REG_CBSP); 4752 4753 if ((Cbsp & IPS_BIT_OP) == 0) 4754 break; 4755 4756 /* Delay for 1 Second */ 4757 MDELAY(IPS_ONE_SEC); 4758 } 4759 4760 if (i >= 240) 4761 /* reset failed */ 4762 return (0); 4763 4764 /* setup CCCR */ 4765 outl(0x1010, ha->io_addr + IPS_REG_CCCR); 4766 4767 /* Enable busmastering */ 4768 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); 4769 4770 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 4771 /* fix for anaconda64 */ 4772 outl(0, ha->io_addr + IPS_REG_NDAE); 4773 4774 /* Enable interrupts */ 4775 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR); 4776 4777 return (1); 4778 } 4779 4780 /****************************************************************************/ 4781 /* */ 4782 /* Routine Name: ips_init_copperhead_memio */ 4783 /* */ 4784 /* Routine Description: */ 4785 /* */ 4786 /* Initialize a copperhead controller with memory mapped I/O */ 4787 /* */ 4788 /****************************************************************************/ 4789 static int 4790 ips_init_copperhead_memio(ips_ha_t * ha) 4791 { 4792 uint8_t Isr = 0; 4793 uint8_t Cbsp; 4794 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4795 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES]; 4796 int i, j; 4797 4798 METHOD_TRACE("ips_init_copperhead_memio", 1); 4799 4800 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4801 for (j = 0; j < 45; j++) { 4802 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 4803 if (Isr & IPS_BIT_GHI) 4804 break; 4805 4806 /* Delay for 1 Second */ 4807 MDELAY(IPS_ONE_SEC); 4808 } 4809 4810 if (j >= 45) 4811 /* error occurred */ 4812 return (0); 4813 4814 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 4815 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 4816 } 4817 4818 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 4819 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4820 "reset controller fails (post status %x %x).\n", 4821 PostByte[0], PostByte[1]); 4822 4823 return (0); 4824 } 4825 4826 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 4827 for (j = 0; j < 240; j++) { 4828 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 4829 if (Isr & IPS_BIT_GHI) 4830 break; 4831 4832 /* Delay for 1 Second */ 4833 MDELAY(IPS_ONE_SEC); 4834 } 4835 4836 if (j >= 240) 4837 /* error occurred */ 4838 return (0); 4839 4840 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 4841 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 4842 } 4843 4844 for (i = 0; i < 240; i++) { 4845 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); 4846 4847 if ((Cbsp & IPS_BIT_OP) == 0) 4848 break; 4849 4850 /* Delay for 1 Second */ 4851 MDELAY(IPS_ONE_SEC); 4852 } 4853 4854 if (i >= 240) 4855 /* error occurred */ 4856 return (0); 4857 4858 /* setup CCCR */ 4859 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); 4860 4861 /* Enable busmastering */ 4862 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); 4863 4864 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 4865 /* fix for anaconda64 */ 4866 writel(0, ha->mem_ptr + IPS_REG_NDAE); 4867 4868 /* Enable interrupts */ 4869 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4870 4871 /* if we get here then everything went OK */ 4872 return (1); 4873 } 4874 4875 /****************************************************************************/ 4876 /* */ 4877 /* Routine Name: ips_init_morpheus */ 4878 /* */ 4879 /* Routine Description: */ 4880 /* */ 4881 /* Initialize a morpheus controller */ 4882 /* */ 4883 /****************************************************************************/ 4884 static int 4885 ips_init_morpheus(ips_ha_t * ha) 4886 { 4887 uint32_t Post; 4888 uint32_t Config; 4889 uint32_t Isr; 4890 uint32_t Oimr; 4891 int i; 4892 4893 METHOD_TRACE("ips_init_morpheus", 1); 4894 4895 /* Wait up to 45 secs for Post */ 4896 for (i = 0; i < 45; i++) { 4897 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4898 4899 if (Isr & IPS_BIT_I960_MSG0I) 4900 break; 4901 4902 /* Delay for 1 Second */ 4903 MDELAY(IPS_ONE_SEC); 4904 } 4905 4906 if (i >= 45) { 4907 /* error occurred */ 4908 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4909 "timeout waiting for post.\n"); 4910 4911 return (0); 4912 } 4913 4914 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4915 4916 if (Post == 0x4F00) { /* If Flashing the Battery PIC */ 4917 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4918 "Flashing Battery PIC, Please wait ...\n"); 4919 4920 /* Clear the interrupt bit */ 4921 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 4922 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4923 4924 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */ 4925 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4926 if (Post != 0x4F00) 4927 break; 4928 /* Delay for 1 Second */ 4929 MDELAY(IPS_ONE_SEC); 4930 } 4931 4932 if (i >= 120) { 4933 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4934 "timeout waiting for Battery PIC Flash\n"); 4935 return (0); 4936 } 4937 4938 } 4939 4940 /* Clear the interrupt bit */ 4941 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 4942 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4943 4944 if (Post < (IPS_GOOD_POST_STATUS << 8)) { 4945 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4946 "reset controller fails (post status %x).\n", Post); 4947 4948 return (0); 4949 } 4950 4951 /* Wait up to 240 secs for config bytes */ 4952 for (i = 0; i < 240; i++) { 4953 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4954 4955 if (Isr & IPS_BIT_I960_MSG1I) 4956 break; 4957 4958 /* Delay for 1 Second */ 4959 MDELAY(IPS_ONE_SEC); 4960 } 4961 4962 if (i >= 240) { 4963 /* error occurred */ 4964 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4965 "timeout waiting for config.\n"); 4966 4967 return (0); 4968 } 4969 4970 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 4971 4972 /* Clear interrupt bit */ 4973 Isr = (uint32_t) IPS_BIT_I960_MSG1I; 4974 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4975 4976 /* Turn on the interrupts */ 4977 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4978 Oimr &= ~0x8; 4979 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4980 4981 /* if we get here then everything went OK */ 4982 4983 /* Since we did a RESET, an EraseStripeLock may be needed */ 4984 if (Post == 0xEF10) { 4985 if ((Config == 0x000F) || (Config == 0x0009)) 4986 ha->requires_esl = 1; 4987 } 4988 4989 return (1); 4990 } 4991 4992 /****************************************************************************/ 4993 /* */ 4994 /* Routine Name: ips_reset_copperhead */ 4995 /* */ 4996 /* Routine Description: */ 4997 /* */ 4998 /* Reset the controller */ 4999 /* */ 5000 /****************************************************************************/ 5001 static int 5002 ips_reset_copperhead(ips_ha_t * ha) 5003 { 5004 int reset_counter; 5005 5006 METHOD_TRACE("ips_reset_copperhead", 1); 5007 5008 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", 5009 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq); 5010 5011 reset_counter = 0; 5012 5013 while (reset_counter < 2) { 5014 reset_counter++; 5015 5016 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR); 5017 5018 /* Delay for 1 Second */ 5019 MDELAY(IPS_ONE_SEC); 5020 5021 outb(0, ha->io_addr + IPS_REG_SCPR); 5022 5023 /* Delay for 1 Second */ 5024 MDELAY(IPS_ONE_SEC); 5025 5026 if ((*ha->func.init) (ha)) 5027 break; 5028 else if (reset_counter >= 2) { 5029 5030 return (0); 5031 } 5032 } 5033 5034 return (1); 5035 } 5036 5037 /****************************************************************************/ 5038 /* */ 5039 /* Routine Name: ips_reset_copperhead_memio */ 5040 /* */ 5041 /* Routine Description: */ 5042 /* */ 5043 /* Reset the controller */ 5044 /* */ 5045 /****************************************************************************/ 5046 static int 5047 ips_reset_copperhead_memio(ips_ha_t * ha) 5048 { 5049 int reset_counter; 5050 5051 METHOD_TRACE("ips_reset_copperhead_memio", 1); 5052 5053 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", 5054 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); 5055 5056 reset_counter = 0; 5057 5058 while (reset_counter < 2) { 5059 reset_counter++; 5060 5061 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); 5062 5063 /* Delay for 1 Second */ 5064 MDELAY(IPS_ONE_SEC); 5065 5066 writeb(0, ha->mem_ptr + IPS_REG_SCPR); 5067 5068 /* Delay for 1 Second */ 5069 MDELAY(IPS_ONE_SEC); 5070 5071 if ((*ha->func.init) (ha)) 5072 break; 5073 else if (reset_counter >= 2) { 5074 5075 return (0); 5076 } 5077 } 5078 5079 return (1); 5080 } 5081 5082 /****************************************************************************/ 5083 /* */ 5084 /* Routine Name: ips_reset_morpheus */ 5085 /* */ 5086 /* Routine Description: */ 5087 /* */ 5088 /* Reset the controller */ 5089 /* */ 5090 /****************************************************************************/ 5091 static int 5092 ips_reset_morpheus(ips_ha_t * ha) 5093 { 5094 int reset_counter; 5095 uint8_t junk; 5096 5097 METHOD_TRACE("ips_reset_morpheus", 1); 5098 5099 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", 5100 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); 5101 5102 reset_counter = 0; 5103 5104 while (reset_counter < 2) { 5105 reset_counter++; 5106 5107 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); 5108 5109 /* Delay for 5 Seconds */ 5110 MDELAY(5 * IPS_ONE_SEC); 5111 5112 /* Do a PCI config read to wait for adapter */ 5113 pci_read_config_byte(ha->pcidev, 4, &junk); 5114 5115 if ((*ha->func.init) (ha)) 5116 break; 5117 else if (reset_counter >= 2) { 5118 5119 return (0); 5120 } 5121 } 5122 5123 return (1); 5124 } 5125 5126 /****************************************************************************/ 5127 /* */ 5128 /* Routine Name: ips_statinit */ 5129 /* */ 5130 /* Routine Description: */ 5131 /* */ 5132 /* Initialize the status queues on the controller */ 5133 /* */ 5134 /****************************************************************************/ 5135 static void 5136 ips_statinit(ips_ha_t * ha) 5137 { 5138 uint32_t phys_status_start; 5139 5140 METHOD_TRACE("ips_statinit", 1); 5141 5142 ha->adapt->p_status_start = ha->adapt->status; 5143 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5144 ha->adapt->p_status_tail = ha->adapt->status; 5145 5146 phys_status_start = ha->adapt->hw_status_start; 5147 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR); 5148 outl(phys_status_start + IPS_STATUS_Q_SIZE, 5149 ha->io_addr + IPS_REG_SQER); 5150 outl(phys_status_start + IPS_STATUS_SIZE, 5151 ha->io_addr + IPS_REG_SQHR); 5152 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR); 5153 5154 ha->adapt->hw_status_tail = phys_status_start; 5155 } 5156 5157 /****************************************************************************/ 5158 /* */ 5159 /* Routine Name: ips_statinit_memio */ 5160 /* */ 5161 /* Routine Description: */ 5162 /* */ 5163 /* Initialize the status queues on the controller */ 5164 /* */ 5165 /****************************************************************************/ 5166 static void 5167 ips_statinit_memio(ips_ha_t * ha) 5168 { 5169 uint32_t phys_status_start; 5170 5171 METHOD_TRACE("ips_statinit_memio", 1); 5172 5173 ha->adapt->p_status_start = ha->adapt->status; 5174 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5175 ha->adapt->p_status_tail = ha->adapt->status; 5176 5177 phys_status_start = ha->adapt->hw_status_start; 5178 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); 5179 writel(phys_status_start + IPS_STATUS_Q_SIZE, 5180 ha->mem_ptr + IPS_REG_SQER); 5181 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); 5182 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); 5183 5184 ha->adapt->hw_status_tail = phys_status_start; 5185 } 5186 5187 /****************************************************************************/ 5188 /* */ 5189 /* Routine Name: ips_statupd_copperhead */ 5190 /* */ 5191 /* Routine Description: */ 5192 /* */ 5193 /* Remove an element from the status queue */ 5194 /* */ 5195 /****************************************************************************/ 5196 static uint32_t 5197 ips_statupd_copperhead(ips_ha_t * ha) 5198 { 5199 METHOD_TRACE("ips_statupd_copperhead", 1); 5200 5201 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5202 ha->adapt->p_status_tail++; 5203 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5204 } else { 5205 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5206 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5207 } 5208 5209 outl(ha->adapt->hw_status_tail, 5210 ha->io_addr + IPS_REG_SQTR); 5211 5212 return (ha->adapt->p_status_tail->value); 5213 } 5214 5215 /****************************************************************************/ 5216 /* */ 5217 /* Routine Name: ips_statupd_copperhead_memio */ 5218 /* */ 5219 /* Routine Description: */ 5220 /* */ 5221 /* Remove an element from the status queue */ 5222 /* */ 5223 /****************************************************************************/ 5224 static uint32_t 5225 ips_statupd_copperhead_memio(ips_ha_t * ha) 5226 { 5227 METHOD_TRACE("ips_statupd_copperhead_memio", 1); 5228 5229 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5230 ha->adapt->p_status_tail++; 5231 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5232 } else { 5233 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5234 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5235 } 5236 5237 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); 5238 5239 return (ha->adapt->p_status_tail->value); 5240 } 5241 5242 /****************************************************************************/ 5243 /* */ 5244 /* Routine Name: ips_statupd_morpheus */ 5245 /* */ 5246 /* Routine Description: */ 5247 /* */ 5248 /* Remove an element from the status queue */ 5249 /* */ 5250 /****************************************************************************/ 5251 static uint32_t 5252 ips_statupd_morpheus(ips_ha_t * ha) 5253 { 5254 uint32_t val; 5255 5256 METHOD_TRACE("ips_statupd_morpheus", 1); 5257 5258 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); 5259 5260 return (val); 5261 } 5262 5263 /****************************************************************************/ 5264 /* */ 5265 /* Routine Name: ips_issue_copperhead */ 5266 /* */ 5267 /* Routine Description: */ 5268 /* */ 5269 /* Send a command down to the controller */ 5270 /* */ 5271 /****************************************************************************/ 5272 static int 5273 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb) 5274 { 5275 uint32_t TimeOut; 5276 uint32_t val; 5277 5278 METHOD_TRACE("ips_issue_copperhead", 1); 5279 5280 if (scb->scsi_cmd) { 5281 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5282 ips_name, 5283 ha->host_num, 5284 scb->cdb[0], 5285 scb->cmd.basic_io.command_id, 5286 scb->bus, scb->target_id, scb->lun); 5287 } else { 5288 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d", 5289 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5290 } 5291 5292 TimeOut = 0; 5293 5294 while ((val = 5295 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) { 5296 udelay(1000); 5297 5298 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5299 if (!(val & IPS_BIT_START_STOP)) 5300 break; 5301 5302 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5303 "ips_issue val [0x%x].\n", val); 5304 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5305 "ips_issue semaphore chk timeout.\n"); 5306 5307 return (IPS_FAILURE); 5308 } /* end if */ 5309 } /* end while */ 5310 5311 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR); 5312 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR); 5313 5314 return (IPS_SUCCESS); 5315 } 5316 5317 /****************************************************************************/ 5318 /* */ 5319 /* Routine Name: ips_issue_copperhead_memio */ 5320 /* */ 5321 /* Routine Description: */ 5322 /* */ 5323 /* Send a command down to the controller */ 5324 /* */ 5325 /****************************************************************************/ 5326 static int 5327 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb) 5328 { 5329 uint32_t TimeOut; 5330 uint32_t val; 5331 5332 METHOD_TRACE("ips_issue_copperhead_memio", 1); 5333 5334 if (scb->scsi_cmd) { 5335 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5336 ips_name, 5337 ha->host_num, 5338 scb->cdb[0], 5339 scb->cmd.basic_io.command_id, 5340 scb->bus, scb->target_id, scb->lun); 5341 } else { 5342 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5343 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5344 } 5345 5346 TimeOut = 0; 5347 5348 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { 5349 udelay(1000); 5350 5351 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5352 if (!(val & IPS_BIT_START_STOP)) 5353 break; 5354 5355 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5356 "ips_issue val [0x%x].\n", val); 5357 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5358 "ips_issue semaphore chk timeout.\n"); 5359 5360 return (IPS_FAILURE); 5361 } /* end if */ 5362 } /* end while */ 5363 5364 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); 5365 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); 5366 5367 return (IPS_SUCCESS); 5368 } 5369 5370 /****************************************************************************/ 5371 /* */ 5372 /* Routine Name: ips_issue_i2o */ 5373 /* */ 5374 /* Routine Description: */ 5375 /* */ 5376 /* Send a command down to the controller */ 5377 /* */ 5378 /****************************************************************************/ 5379 static int 5380 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb) 5381 { 5382 5383 METHOD_TRACE("ips_issue_i2o", 1); 5384 5385 if (scb->scsi_cmd) { 5386 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5387 ips_name, 5388 ha->host_num, 5389 scb->cdb[0], 5390 scb->cmd.basic_io.command_id, 5391 scb->bus, scb->target_id, scb->lun); 5392 } else { 5393 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5394 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5395 } 5396 5397 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ); 5398 5399 return (IPS_SUCCESS); 5400 } 5401 5402 /****************************************************************************/ 5403 /* */ 5404 /* Routine Name: ips_issue_i2o_memio */ 5405 /* */ 5406 /* Routine Description: */ 5407 /* */ 5408 /* Send a command down to the controller */ 5409 /* */ 5410 /****************************************************************************/ 5411 static int 5412 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb) 5413 { 5414 5415 METHOD_TRACE("ips_issue_i2o_memio", 1); 5416 5417 if (scb->scsi_cmd) { 5418 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5419 ips_name, 5420 ha->host_num, 5421 scb->cdb[0], 5422 scb->cmd.basic_io.command_id, 5423 scb->bus, scb->target_id, scb->lun); 5424 } else { 5425 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5426 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5427 } 5428 5429 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); 5430 5431 return (IPS_SUCCESS); 5432 } 5433 5434 /****************************************************************************/ 5435 /* */ 5436 /* Routine Name: ips_isintr_copperhead */ 5437 /* */ 5438 /* Routine Description: */ 5439 /* */ 5440 /* Test to see if an interrupt is for us */ 5441 /* */ 5442 /****************************************************************************/ 5443 static int 5444 ips_isintr_copperhead(ips_ha_t * ha) 5445 { 5446 uint8_t Isr; 5447 5448 METHOD_TRACE("ips_isintr_copperhead", 2); 5449 5450 Isr = inb(ha->io_addr + IPS_REG_HISR); 5451 5452 if (Isr == 0xFF) 5453 /* ?!?! Nothing really there */ 5454 return (0); 5455 5456 if (Isr & IPS_BIT_SCE) 5457 return (1); 5458 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5459 /* status queue overflow or GHI */ 5460 /* just clear the interrupt */ 5461 outb(Isr, ha->io_addr + IPS_REG_HISR); 5462 } 5463 5464 return (0); 5465 } 5466 5467 /****************************************************************************/ 5468 /* */ 5469 /* Routine Name: ips_isintr_copperhead_memio */ 5470 /* */ 5471 /* Routine Description: */ 5472 /* */ 5473 /* Test to see if an interrupt is for us */ 5474 /* */ 5475 /****************************************************************************/ 5476 static int 5477 ips_isintr_copperhead_memio(ips_ha_t * ha) 5478 { 5479 uint8_t Isr; 5480 5481 METHOD_TRACE("ips_isintr_memio", 2); 5482 5483 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 5484 5485 if (Isr == 0xFF) 5486 /* ?!?! Nothing really there */ 5487 return (0); 5488 5489 if (Isr & IPS_BIT_SCE) 5490 return (1); 5491 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5492 /* status queue overflow or GHI */ 5493 /* just clear the interrupt */ 5494 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 5495 } 5496 5497 return (0); 5498 } 5499 5500 /****************************************************************************/ 5501 /* */ 5502 /* Routine Name: ips_isintr_morpheus */ 5503 /* */ 5504 /* Routine Description: */ 5505 /* */ 5506 /* Test to see if an interrupt is for us */ 5507 /* */ 5508 /****************************************************************************/ 5509 static int 5510 ips_isintr_morpheus(ips_ha_t * ha) 5511 { 5512 uint32_t Isr; 5513 5514 METHOD_TRACE("ips_isintr_morpheus", 2); 5515 5516 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 5517 5518 if (Isr & IPS_BIT_I2O_OPQI) 5519 return (1); 5520 else 5521 return (0); 5522 } 5523 5524 /****************************************************************************/ 5525 /* */ 5526 /* Routine Name: ips_wait */ 5527 /* */ 5528 /* Routine Description: */ 5529 /* */ 5530 /* Wait for a command to complete */ 5531 /* */ 5532 /****************************************************************************/ 5533 static int 5534 ips_wait(ips_ha_t * ha, int time, int intr) 5535 { 5536 int ret; 5537 int done; 5538 5539 METHOD_TRACE("ips_wait", 1); 5540 5541 ret = IPS_FAILURE; 5542 done = FALSE; 5543 5544 time *= IPS_ONE_SEC; /* convert seconds */ 5545 5546 while ((time > 0) && (!done)) { 5547 if (intr == IPS_INTR_ON) { 5548 if (ha->waitflag == FALSE) { 5549 ret = IPS_SUCCESS; 5550 done = TRUE; 5551 break; 5552 } 5553 } else if (intr == IPS_INTR_IORL) { 5554 if (ha->waitflag == FALSE) { 5555 /* 5556 * controller generated an interrupt to 5557 * acknowledge completion of the command 5558 * and ips_intr() has serviced the interrupt. 5559 */ 5560 ret = IPS_SUCCESS; 5561 done = TRUE; 5562 break; 5563 } 5564 5565 /* 5566 * NOTE: we already have the io_request_lock so 5567 * even if we get an interrupt it won't get serviced 5568 * until after we finish. 5569 */ 5570 5571 (*ha->func.intr) (ha); 5572 } 5573 5574 /* This looks like a very evil loop, but it only does this during start-up */ 5575 udelay(1000); 5576 time--; 5577 } 5578 5579 return (ret); 5580 } 5581 5582 /****************************************************************************/ 5583 /* */ 5584 /* Routine Name: ips_write_driver_status */ 5585 /* */ 5586 /* Routine Description: */ 5587 /* */ 5588 /* Write OS/Driver version to Page 5 of the nvram on the controller */ 5589 /* */ 5590 /****************************************************************************/ 5591 static int 5592 ips_write_driver_status(ips_ha_t * ha, int intr) 5593 { 5594 METHOD_TRACE("ips_write_driver_status", 1); 5595 5596 if (!ips_readwrite_page5(ha, FALSE, intr)) { 5597 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5598 "unable to read NVRAM page 5.\n"); 5599 5600 return (0); 5601 } 5602 5603 /* check to make sure the page has a valid */ 5604 /* signature */ 5605 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) { 5606 DEBUG_VAR(1, 5607 "(%s%d) NVRAM page 5 has an invalid signature: %X.", 5608 ips_name, ha->host_num, ha->nvram->signature); 5609 ha->nvram->signature = IPS_NVRAM_P5_SIG; 5610 } 5611 5612 DEBUG_VAR(2, 5613 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.", 5614 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type), 5615 ha->nvram->adapter_slot, ha->nvram->bios_high[0], 5616 ha->nvram->bios_high[1], ha->nvram->bios_high[2], 5617 ha->nvram->bios_high[3], ha->nvram->bios_low[0], 5618 ha->nvram->bios_low[1], ha->nvram->bios_low[2], 5619 ha->nvram->bios_low[3]); 5620 5621 ips_get_bios_version(ha, intr); 5622 5623 /* change values (as needed) */ 5624 ha->nvram->operating_system = IPS_OS_LINUX; 5625 ha->nvram->adapter_type = ha->ad_type; 5626 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4); 5627 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4); 5628 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4); 5629 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4); 5630 5631 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */ 5632 5633 /* now update the page */ 5634 if (!ips_readwrite_page5(ha, TRUE, intr)) { 5635 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5636 "unable to write NVRAM page 5.\n"); 5637 5638 return (0); 5639 } 5640 5641 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */ 5642 ha->slot_num = ha->nvram->adapter_slot; 5643 5644 return (1); 5645 } 5646 5647 /****************************************************************************/ 5648 /* */ 5649 /* Routine Name: ips_read_adapter_status */ 5650 /* */ 5651 /* Routine Description: */ 5652 /* */ 5653 /* Do an Inquiry command to the adapter */ 5654 /* */ 5655 /****************************************************************************/ 5656 static int 5657 ips_read_adapter_status(ips_ha_t * ha, int intr) 5658 { 5659 ips_scb_t *scb; 5660 int ret; 5661 5662 METHOD_TRACE("ips_read_adapter_status", 1); 5663 5664 scb = &ha->scbs[ha->max_cmds - 1]; 5665 5666 ips_init_scb(ha, scb); 5667 5668 scb->timeout = ips_cmd_timeout; 5669 scb->cdb[0] = IPS_CMD_ENQUIRY; 5670 5671 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 5672 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5673 scb->cmd.basic_io.sg_count = 0; 5674 scb->cmd.basic_io.lba = 0; 5675 scb->cmd.basic_io.sector_count = 0; 5676 scb->cmd.basic_io.log_drv = 0; 5677 scb->data_len = sizeof (*ha->enq); 5678 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 5679 5680 /* send command */ 5681 if (((ret = 5682 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5683 || (ret == IPS_SUCCESS_IMM) 5684 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5685 return (0); 5686 5687 return (1); 5688 } 5689 5690 /****************************************************************************/ 5691 /* */ 5692 /* Routine Name: ips_read_subsystem_parameters */ 5693 /* */ 5694 /* Routine Description: */ 5695 /* */ 5696 /* Read subsystem parameters from the adapter */ 5697 /* */ 5698 /****************************************************************************/ 5699 static int 5700 ips_read_subsystem_parameters(ips_ha_t * ha, int intr) 5701 { 5702 ips_scb_t *scb; 5703 int ret; 5704 5705 METHOD_TRACE("ips_read_subsystem_parameters", 1); 5706 5707 scb = &ha->scbs[ha->max_cmds - 1]; 5708 5709 ips_init_scb(ha, scb); 5710 5711 scb->timeout = ips_cmd_timeout; 5712 scb->cdb[0] = IPS_CMD_GET_SUBSYS; 5713 5714 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS; 5715 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5716 scb->cmd.basic_io.sg_count = 0; 5717 scb->cmd.basic_io.lba = 0; 5718 scb->cmd.basic_io.sector_count = 0; 5719 scb->cmd.basic_io.log_drv = 0; 5720 scb->data_len = sizeof (*ha->subsys); 5721 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 5722 5723 /* send command */ 5724 if (((ret = 5725 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5726 || (ret == IPS_SUCCESS_IMM) 5727 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5728 return (0); 5729 5730 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys)); 5731 return (1); 5732 } 5733 5734 /****************************************************************************/ 5735 /* */ 5736 /* Routine Name: ips_read_config */ 5737 /* */ 5738 /* Routine Description: */ 5739 /* */ 5740 /* Read the configuration on the adapter */ 5741 /* */ 5742 /****************************************************************************/ 5743 static int 5744 ips_read_config(ips_ha_t * ha, int intr) 5745 { 5746 ips_scb_t *scb; 5747 int i; 5748 int ret; 5749 5750 METHOD_TRACE("ips_read_config", 1); 5751 5752 /* set defaults for initiator IDs */ 5753 for (i = 0; i < 4; i++) 5754 ha->conf->init_id[i] = 7; 5755 5756 scb = &ha->scbs[ha->max_cmds - 1]; 5757 5758 ips_init_scb(ha, scb); 5759 5760 scb->timeout = ips_cmd_timeout; 5761 scb->cdb[0] = IPS_CMD_READ_CONF; 5762 5763 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF; 5764 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5765 scb->data_len = sizeof (*ha->conf); 5766 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 5767 5768 /* send command */ 5769 if (((ret = 5770 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5771 || (ret == IPS_SUCCESS_IMM) 5772 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 5773 5774 memset(ha->conf, 0, sizeof (IPS_CONF)); 5775 5776 /* reset initiator IDs */ 5777 for (i = 0; i < 4; i++) 5778 ha->conf->init_id[i] = 7; 5779 5780 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */ 5781 if ((scb->basic_status & IPS_GSC_STATUS_MASK) == 5782 IPS_CMD_CMPLT_WERROR) 5783 return (1); 5784 5785 return (0); 5786 } 5787 5788 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); 5789 return (1); 5790 } 5791 5792 /****************************************************************************/ 5793 /* */ 5794 /* Routine Name: ips_readwrite_page5 */ 5795 /* */ 5796 /* Routine Description: */ 5797 /* */ 5798 /* Read nvram page 5 from the adapter */ 5799 /* */ 5800 /****************************************************************************/ 5801 static int 5802 ips_readwrite_page5(ips_ha_t * ha, int write, int intr) 5803 { 5804 ips_scb_t *scb; 5805 int ret; 5806 5807 METHOD_TRACE("ips_readwrite_page5", 1); 5808 5809 scb = &ha->scbs[ha->max_cmds - 1]; 5810 5811 ips_init_scb(ha, scb); 5812 5813 scb->timeout = ips_cmd_timeout; 5814 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE; 5815 5816 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE; 5817 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb); 5818 scb->cmd.nvram.page = 5; 5819 scb->cmd.nvram.write = write; 5820 scb->cmd.nvram.reserved = 0; 5821 scb->cmd.nvram.reserved2 = 0; 5822 scb->data_len = sizeof (*ha->nvram); 5823 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; 5824 if (write) 5825 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); 5826 5827 /* issue the command */ 5828 if (((ret = 5829 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5830 || (ret == IPS_SUCCESS_IMM) 5831 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 5832 5833 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5)); 5834 5835 return (0); 5836 } 5837 if (!write) 5838 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram)); 5839 return (1); 5840 } 5841 5842 /****************************************************************************/ 5843 /* */ 5844 /* Routine Name: ips_clear_adapter */ 5845 /* */ 5846 /* Routine Description: */ 5847 /* */ 5848 /* Clear the stripe lock tables */ 5849 /* */ 5850 /****************************************************************************/ 5851 static int 5852 ips_clear_adapter(ips_ha_t * ha, int intr) 5853 { 5854 ips_scb_t *scb; 5855 int ret; 5856 5857 METHOD_TRACE("ips_clear_adapter", 1); 5858 5859 scb = &ha->scbs[ha->max_cmds - 1]; 5860 5861 ips_init_scb(ha, scb); 5862 5863 scb->timeout = ips_reset_timeout; 5864 scb->cdb[0] = IPS_CMD_CONFIG_SYNC; 5865 5866 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC; 5867 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb); 5868 scb->cmd.config_sync.channel = 0; 5869 scb->cmd.config_sync.source_target = IPS_POCL; 5870 scb->cmd.config_sync.reserved = 0; 5871 scb->cmd.config_sync.reserved2 = 0; 5872 scb->cmd.config_sync.reserved3 = 0; 5873 5874 /* issue command */ 5875 if (((ret = 5876 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE) 5877 || (ret == IPS_SUCCESS_IMM) 5878 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5879 return (0); 5880 5881 /* send unlock stripe command */ 5882 ips_init_scb(ha, scb); 5883 5884 scb->cdb[0] = IPS_CMD_ERROR_TABLE; 5885 scb->timeout = ips_reset_timeout; 5886 5887 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE; 5888 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb); 5889 scb->cmd.unlock_stripe.log_drv = 0; 5890 scb->cmd.unlock_stripe.control = IPS_CSL; 5891 scb->cmd.unlock_stripe.reserved = 0; 5892 scb->cmd.unlock_stripe.reserved2 = 0; 5893 scb->cmd.unlock_stripe.reserved3 = 0; 5894 5895 /* issue command */ 5896 if (((ret = 5897 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5898 || (ret == IPS_SUCCESS_IMM) 5899 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5900 return (0); 5901 5902 return (1); 5903 } 5904 5905 /****************************************************************************/ 5906 /* */ 5907 /* Routine Name: ips_ffdc_reset */ 5908 /* */ 5909 /* Routine Description: */ 5910 /* */ 5911 /* FFDC: write reset info */ 5912 /* */ 5913 /****************************************************************************/ 5914 static void 5915 ips_ffdc_reset(ips_ha_t * ha, int intr) 5916 { 5917 ips_scb_t *scb; 5918 5919 METHOD_TRACE("ips_ffdc_reset", 1); 5920 5921 scb = &ha->scbs[ha->max_cmds - 1]; 5922 5923 ips_init_scb(ha, scb); 5924 5925 scb->timeout = ips_cmd_timeout; 5926 scb->cdb[0] = IPS_CMD_FFDC; 5927 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 5928 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 5929 scb->cmd.ffdc.reset_count = ha->reset_count; 5930 scb->cmd.ffdc.reset_type = 0x80; 5931 5932 /* convert time to what the card wants */ 5933 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 5934 5935 /* issue command */ 5936 ips_send_wait(ha, scb, ips_cmd_timeout, intr); 5937 } 5938 5939 /****************************************************************************/ 5940 /* */ 5941 /* Routine Name: ips_ffdc_time */ 5942 /* */ 5943 /* Routine Description: */ 5944 /* */ 5945 /* FFDC: write time info */ 5946 /* */ 5947 /****************************************************************************/ 5948 static void 5949 ips_ffdc_time(ips_ha_t * ha) 5950 { 5951 ips_scb_t *scb; 5952 5953 METHOD_TRACE("ips_ffdc_time", 1); 5954 5955 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num); 5956 5957 scb = &ha->scbs[ha->max_cmds - 1]; 5958 5959 ips_init_scb(ha, scb); 5960 5961 scb->timeout = ips_cmd_timeout; 5962 scb->cdb[0] = IPS_CMD_FFDC; 5963 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 5964 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 5965 scb->cmd.ffdc.reset_count = 0; 5966 scb->cmd.ffdc.reset_type = 0; 5967 5968 /* convert time to what the card wants */ 5969 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 5970 5971 /* issue command */ 5972 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC); 5973 } 5974 5975 /****************************************************************************/ 5976 /* */ 5977 /* Routine Name: ips_fix_ffdc_time */ 5978 /* */ 5979 /* Routine Description: */ 5980 /* Adjust time_t to what the card wants */ 5981 /* */ 5982 /****************************************************************************/ 5983 static void 5984 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time) 5985 { 5986 struct tm tm; 5987 5988 METHOD_TRACE("ips_fix_ffdc_time", 1); 5989 5990 time64_to_tm(current_time, 0, &tm); 5991 5992 scb->cmd.ffdc.hour = tm.tm_hour; 5993 scb->cmd.ffdc.minute = tm.tm_min; 5994 scb->cmd.ffdc.second = tm.tm_sec; 5995 scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100; 5996 scb->cmd.ffdc.yearL = tm.tm_year % 100; 5997 scb->cmd.ffdc.month = tm.tm_mon + 1; 5998 scb->cmd.ffdc.day = tm.tm_mday; 5999 } 6000 6001 /**************************************************************************** 6002 * BIOS Flash Routines * 6003 ****************************************************************************/ 6004 6005 /****************************************************************************/ 6006 /* */ 6007 /* Routine Name: ips_erase_bios */ 6008 /* */ 6009 /* Routine Description: */ 6010 /* Erase the BIOS on the adapter */ 6011 /* */ 6012 /****************************************************************************/ 6013 static int 6014 ips_erase_bios(ips_ha_t * ha) 6015 { 6016 int timeout; 6017 uint8_t status = 0; 6018 6019 METHOD_TRACE("ips_erase_bios", 1); 6020 6021 status = 0; 6022 6023 /* Clear the status register */ 6024 outl(0, ha->io_addr + IPS_REG_FLAP); 6025 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6026 udelay(25); /* 25 us */ 6027 6028 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6029 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6030 udelay(25); /* 25 us */ 6031 6032 /* Erase Setup */ 6033 outb(0x20, ha->io_addr + IPS_REG_FLDP); 6034 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6035 udelay(25); /* 25 us */ 6036 6037 /* Erase Confirm */ 6038 outb(0xD0, ha->io_addr + IPS_REG_FLDP); 6039 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6040 udelay(25); /* 25 us */ 6041 6042 /* Erase Status */ 6043 outb(0x70, ha->io_addr + IPS_REG_FLDP); 6044 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6045 udelay(25); /* 25 us */ 6046 6047 timeout = 80000; /* 80 seconds */ 6048 6049 while (timeout > 0) { 6050 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6051 outl(0, ha->io_addr + IPS_REG_FLAP); 6052 udelay(25); /* 25 us */ 6053 } 6054 6055 status = inb(ha->io_addr + IPS_REG_FLDP); 6056 6057 if (status & 0x80) 6058 break; 6059 6060 MDELAY(1); 6061 timeout--; 6062 } 6063 6064 /* check for timeout */ 6065 if (timeout <= 0) { 6066 /* timeout */ 6067 6068 /* try to suspend the erase */ 6069 outb(0xB0, ha->io_addr + IPS_REG_FLDP); 6070 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6071 udelay(25); /* 25 us */ 6072 6073 /* wait for 10 seconds */ 6074 timeout = 10000; 6075 while (timeout > 0) { 6076 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6077 outl(0, ha->io_addr + IPS_REG_FLAP); 6078 udelay(25); /* 25 us */ 6079 } 6080 6081 status = inb(ha->io_addr + IPS_REG_FLDP); 6082 6083 if (status & 0xC0) 6084 break; 6085 6086 MDELAY(1); 6087 timeout--; 6088 } 6089 6090 return (1); 6091 } 6092 6093 /* check for valid VPP */ 6094 if (status & 0x08) 6095 /* VPP failure */ 6096 return (1); 6097 6098 /* check for successful flash */ 6099 if (status & 0x30) 6100 /* sequence error */ 6101 return (1); 6102 6103 /* Otherwise, we were successful */ 6104 /* clear status */ 6105 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6106 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6107 udelay(25); /* 25 us */ 6108 6109 /* enable reads */ 6110 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6111 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6112 udelay(25); /* 25 us */ 6113 6114 return (0); 6115 } 6116 6117 /****************************************************************************/ 6118 /* */ 6119 /* Routine Name: ips_erase_bios_memio */ 6120 /* */ 6121 /* Routine Description: */ 6122 /* Erase the BIOS on the adapter */ 6123 /* */ 6124 /****************************************************************************/ 6125 static int 6126 ips_erase_bios_memio(ips_ha_t * ha) 6127 { 6128 int timeout; 6129 uint8_t status; 6130 6131 METHOD_TRACE("ips_erase_bios_memio", 1); 6132 6133 status = 0; 6134 6135 /* Clear the status register */ 6136 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6137 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6138 udelay(25); /* 25 us */ 6139 6140 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6141 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6142 udelay(25); /* 25 us */ 6143 6144 /* Erase Setup */ 6145 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); 6146 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6147 udelay(25); /* 25 us */ 6148 6149 /* Erase Confirm */ 6150 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); 6151 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6152 udelay(25); /* 25 us */ 6153 6154 /* Erase Status */ 6155 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); 6156 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6157 udelay(25); /* 25 us */ 6158 6159 timeout = 80000; /* 80 seconds */ 6160 6161 while (timeout > 0) { 6162 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6163 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6164 udelay(25); /* 25 us */ 6165 } 6166 6167 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6168 6169 if (status & 0x80) 6170 break; 6171 6172 MDELAY(1); 6173 timeout--; 6174 } 6175 6176 /* check for timeout */ 6177 if (timeout <= 0) { 6178 /* timeout */ 6179 6180 /* try to suspend the erase */ 6181 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); 6182 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6183 udelay(25); /* 25 us */ 6184 6185 /* wait for 10 seconds */ 6186 timeout = 10000; 6187 while (timeout > 0) { 6188 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6189 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6190 udelay(25); /* 25 us */ 6191 } 6192 6193 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6194 6195 if (status & 0xC0) 6196 break; 6197 6198 MDELAY(1); 6199 timeout--; 6200 } 6201 6202 return (1); 6203 } 6204 6205 /* check for valid VPP */ 6206 if (status & 0x08) 6207 /* VPP failure */ 6208 return (1); 6209 6210 /* check for successful flash */ 6211 if (status & 0x30) 6212 /* sequence error */ 6213 return (1); 6214 6215 /* Otherwise, we were successful */ 6216 /* clear status */ 6217 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6218 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6219 udelay(25); /* 25 us */ 6220 6221 /* enable reads */ 6222 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6223 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6224 udelay(25); /* 25 us */ 6225 6226 return (0); 6227 } 6228 6229 /****************************************************************************/ 6230 /* */ 6231 /* Routine Name: ips_program_bios */ 6232 /* */ 6233 /* Routine Description: */ 6234 /* Program the BIOS on the adapter */ 6235 /* */ 6236 /****************************************************************************/ 6237 static int 6238 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6239 uint32_t offset) 6240 { 6241 int i; 6242 int timeout; 6243 uint8_t status = 0; 6244 6245 METHOD_TRACE("ips_program_bios", 1); 6246 6247 status = 0; 6248 6249 for (i = 0; i < buffersize; i++) { 6250 /* write a byte */ 6251 outl(i + offset, ha->io_addr + IPS_REG_FLAP); 6252 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6253 udelay(25); /* 25 us */ 6254 6255 outb(0x40, ha->io_addr + IPS_REG_FLDP); 6256 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6257 udelay(25); /* 25 us */ 6258 6259 outb(buffer[i], ha->io_addr + IPS_REG_FLDP); 6260 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6261 udelay(25); /* 25 us */ 6262 6263 /* wait up to one second */ 6264 timeout = 1000; 6265 while (timeout > 0) { 6266 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6267 outl(0, ha->io_addr + IPS_REG_FLAP); 6268 udelay(25); /* 25 us */ 6269 } 6270 6271 status = inb(ha->io_addr + IPS_REG_FLDP); 6272 6273 if (status & 0x80) 6274 break; 6275 6276 MDELAY(1); 6277 timeout--; 6278 } 6279 6280 if (timeout == 0) { 6281 /* timeout error */ 6282 outl(0, ha->io_addr + IPS_REG_FLAP); 6283 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6284 udelay(25); /* 25 us */ 6285 6286 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6287 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6288 udelay(25); /* 25 us */ 6289 6290 return (1); 6291 } 6292 6293 /* check the status */ 6294 if (status & 0x18) { 6295 /* programming error */ 6296 outl(0, ha->io_addr + IPS_REG_FLAP); 6297 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6298 udelay(25); /* 25 us */ 6299 6300 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6301 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6302 udelay(25); /* 25 us */ 6303 6304 return (1); 6305 } 6306 } /* end for */ 6307 6308 /* Enable reading */ 6309 outl(0, ha->io_addr + IPS_REG_FLAP); 6310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6311 udelay(25); /* 25 us */ 6312 6313 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6314 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6315 udelay(25); /* 25 us */ 6316 6317 return (0); 6318 } 6319 6320 /****************************************************************************/ 6321 /* */ 6322 /* Routine Name: ips_program_bios_memio */ 6323 /* */ 6324 /* Routine Description: */ 6325 /* Program the BIOS on the adapter */ 6326 /* */ 6327 /****************************************************************************/ 6328 static int 6329 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6330 uint32_t offset) 6331 { 6332 int i; 6333 int timeout; 6334 uint8_t status = 0; 6335 6336 METHOD_TRACE("ips_program_bios_memio", 1); 6337 6338 status = 0; 6339 6340 for (i = 0; i < buffersize; i++) { 6341 /* write a byte */ 6342 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6343 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6344 udelay(25); /* 25 us */ 6345 6346 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); 6347 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6348 udelay(25); /* 25 us */ 6349 6350 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); 6351 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6352 udelay(25); /* 25 us */ 6353 6354 /* wait up to one second */ 6355 timeout = 1000; 6356 while (timeout > 0) { 6357 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6358 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6359 udelay(25); /* 25 us */ 6360 } 6361 6362 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6363 6364 if (status & 0x80) 6365 break; 6366 6367 MDELAY(1); 6368 timeout--; 6369 } 6370 6371 if (timeout == 0) { 6372 /* timeout error */ 6373 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6374 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6375 udelay(25); /* 25 us */ 6376 6377 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6378 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6379 udelay(25); /* 25 us */ 6380 6381 return (1); 6382 } 6383 6384 /* check the status */ 6385 if (status & 0x18) { 6386 /* programming error */ 6387 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6388 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6389 udelay(25); /* 25 us */ 6390 6391 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6392 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6393 udelay(25); /* 25 us */ 6394 6395 return (1); 6396 } 6397 } /* end for */ 6398 6399 /* Enable reading */ 6400 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6401 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6402 udelay(25); /* 25 us */ 6403 6404 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6405 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6406 udelay(25); /* 25 us */ 6407 6408 return (0); 6409 } 6410 6411 /****************************************************************************/ 6412 /* */ 6413 /* Routine Name: ips_verify_bios */ 6414 /* */ 6415 /* Routine Description: */ 6416 /* Verify the BIOS on the adapter */ 6417 /* */ 6418 /****************************************************************************/ 6419 static int 6420 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6421 uint32_t offset) 6422 { 6423 uint8_t checksum; 6424 int i; 6425 6426 METHOD_TRACE("ips_verify_bios", 1); 6427 6428 /* test 1st byte */ 6429 outl(0, ha->io_addr + IPS_REG_FLAP); 6430 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6431 udelay(25); /* 25 us */ 6432 6433 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 6434 return (1); 6435 6436 outl(1, ha->io_addr + IPS_REG_FLAP); 6437 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6438 udelay(25); /* 25 us */ 6439 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 6440 return (1); 6441 6442 checksum = 0xff; 6443 for (i = 2; i < buffersize; i++) { 6444 6445 outl(i + offset, ha->io_addr + IPS_REG_FLAP); 6446 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6447 udelay(25); /* 25 us */ 6448 6449 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); 6450 } 6451 6452 if (checksum != 0) 6453 /* failure */ 6454 return (1); 6455 else 6456 /* success */ 6457 return (0); 6458 } 6459 6460 /****************************************************************************/ 6461 /* */ 6462 /* Routine Name: ips_verify_bios_memio */ 6463 /* */ 6464 /* Routine Description: */ 6465 /* Verify the BIOS on the adapter */ 6466 /* */ 6467 /****************************************************************************/ 6468 static int 6469 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6470 uint32_t offset) 6471 { 6472 uint8_t checksum; 6473 int i; 6474 6475 METHOD_TRACE("ips_verify_bios_memio", 1); 6476 6477 /* test 1st byte */ 6478 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6479 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6480 udelay(25); /* 25 us */ 6481 6482 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 6483 return (1); 6484 6485 writel(1, ha->mem_ptr + IPS_REG_FLAP); 6486 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6487 udelay(25); /* 25 us */ 6488 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 6489 return (1); 6490 6491 checksum = 0xff; 6492 for (i = 2; i < buffersize; i++) { 6493 6494 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6495 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6496 udelay(25); /* 25 us */ 6497 6498 checksum = 6499 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); 6500 } 6501 6502 if (checksum != 0) 6503 /* failure */ 6504 return (1); 6505 else 6506 /* success */ 6507 return (0); 6508 } 6509 6510 /****************************************************************************/ 6511 /* */ 6512 /* Routine Name: ips_abort_init */ 6513 /* */ 6514 /* Routine Description: */ 6515 /* cleanup routine for a failed adapter initialization */ 6516 /****************************************************************************/ 6517 static int 6518 ips_abort_init(ips_ha_t * ha, int index) 6519 { 6520 ha->active = 0; 6521 ips_free(ha); 6522 ips_ha[index] = NULL; 6523 ips_sh[index] = NULL; 6524 return -1; 6525 } 6526 6527 /****************************************************************************/ 6528 /* */ 6529 /* Routine Name: ips_shift_controllers */ 6530 /* */ 6531 /* Routine Description: */ 6532 /* helper function for ordering adapters */ 6533 /****************************************************************************/ 6534 static void 6535 ips_shift_controllers(int lowindex, int highindex) 6536 { 6537 ips_ha_t *ha_sav = ips_ha[highindex]; 6538 struct Scsi_Host *sh_sav = ips_sh[highindex]; 6539 int i; 6540 6541 for (i = highindex; i > lowindex; i--) { 6542 ips_ha[i] = ips_ha[i - 1]; 6543 ips_sh[i] = ips_sh[i - 1]; 6544 ips_ha[i]->host_num = i; 6545 } 6546 ha_sav->host_num = lowindex; 6547 ips_ha[lowindex] = ha_sav; 6548 ips_sh[lowindex] = sh_sav; 6549 } 6550 6551 /****************************************************************************/ 6552 /* */ 6553 /* Routine Name: ips_order_controllers */ 6554 /* */ 6555 /* Routine Description: */ 6556 /* place controllers is the "proper" boot order */ 6557 /****************************************************************************/ 6558 static void 6559 ips_order_controllers(void) 6560 { 6561 int i, j, tmp, position = 0; 6562 IPS_NVRAM_P5 *nvram; 6563 if (!ips_ha[0]) 6564 return; 6565 nvram = ips_ha[0]->nvram; 6566 6567 if (nvram->adapter_order[0]) { 6568 for (i = 1; i <= nvram->adapter_order[0]; i++) { 6569 for (j = position; j < ips_num_controllers; j++) { 6570 switch (ips_ha[j]->ad_type) { 6571 case IPS_ADTYPE_SERVERAID6M: 6572 case IPS_ADTYPE_SERVERAID7M: 6573 if (nvram->adapter_order[i] == 'M') { 6574 ips_shift_controllers(position, 6575 j); 6576 position++; 6577 } 6578 break; 6579 case IPS_ADTYPE_SERVERAID4L: 6580 case IPS_ADTYPE_SERVERAID4M: 6581 case IPS_ADTYPE_SERVERAID4MX: 6582 case IPS_ADTYPE_SERVERAID4LX: 6583 if (nvram->adapter_order[i] == 'N') { 6584 ips_shift_controllers(position, 6585 j); 6586 position++; 6587 } 6588 break; 6589 case IPS_ADTYPE_SERVERAID6I: 6590 case IPS_ADTYPE_SERVERAID5I2: 6591 case IPS_ADTYPE_SERVERAID5I1: 6592 case IPS_ADTYPE_SERVERAID7k: 6593 if (nvram->adapter_order[i] == 'S') { 6594 ips_shift_controllers(position, 6595 j); 6596 position++; 6597 } 6598 break; 6599 case IPS_ADTYPE_SERVERAID: 6600 case IPS_ADTYPE_SERVERAID2: 6601 case IPS_ADTYPE_NAVAJO: 6602 case IPS_ADTYPE_KIOWA: 6603 case IPS_ADTYPE_SERVERAID3L: 6604 case IPS_ADTYPE_SERVERAID3: 6605 case IPS_ADTYPE_SERVERAID4H: 6606 if (nvram->adapter_order[i] == 'A') { 6607 ips_shift_controllers(position, 6608 j); 6609 position++; 6610 } 6611 break; 6612 default: 6613 break; 6614 } 6615 } 6616 } 6617 /* if adapter_order[0], then ordering is complete */ 6618 return; 6619 } 6620 /* old bios, use older ordering */ 6621 tmp = 0; 6622 for (i = position; i < ips_num_controllers; i++) { 6623 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 || 6624 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) { 6625 ips_shift_controllers(position, i); 6626 position++; 6627 tmp = 1; 6628 } 6629 } 6630 /* if there were no 5I cards, then don't do any extra ordering */ 6631 if (!tmp) 6632 return; 6633 for (i = position; i < ips_num_controllers; i++) { 6634 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L || 6635 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M || 6636 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX || 6637 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) { 6638 ips_shift_controllers(position, i); 6639 position++; 6640 } 6641 } 6642 6643 return; 6644 } 6645 6646 /****************************************************************************/ 6647 /* */ 6648 /* Routine Name: ips_register_scsi */ 6649 /* */ 6650 /* Routine Description: */ 6651 /* perform any registration and setup with the scsi layer */ 6652 /****************************************************************************/ 6653 static int 6654 ips_register_scsi(int index) 6655 { 6656 struct Scsi_Host *sh; 6657 ips_ha_t *ha, *oldha = ips_ha[index]; 6658 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t)); 6659 if (!sh) { 6660 IPS_PRINTK(KERN_WARNING, oldha->pcidev, 6661 "Unable to register controller with SCSI subsystem\n"); 6662 return -1; 6663 } 6664 ha = IPS_HA(sh); 6665 memcpy(ha, oldha, sizeof (ips_ha_t)); 6666 free_irq(oldha->pcidev->irq, oldha); 6667 /* Install the interrupt handler with the new ha */ 6668 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 6669 IPS_PRINTK(KERN_WARNING, ha->pcidev, 6670 "Unable to install interrupt handler\n"); 6671 goto err_out_sh; 6672 } 6673 6674 kfree(oldha); 6675 6676 /* Store away needed values for later use */ 6677 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; 6678 sh->sg_tablesize = sh->hostt->sg_tablesize; 6679 sh->can_queue = sh->hostt->can_queue; 6680 sh->cmd_per_lun = sh->hostt->cmd_per_lun; 6681 sh->use_clustering = sh->hostt->use_clustering; 6682 sh->max_sectors = 128; 6683 6684 sh->max_id = ha->ntargets; 6685 sh->max_lun = ha->nlun; 6686 sh->max_channel = ha->nbus - 1; 6687 sh->can_queue = ha->max_cmds - 1; 6688 6689 if (scsi_add_host(sh, &ha->pcidev->dev)) 6690 goto err_out; 6691 6692 ips_sh[index] = sh; 6693 ips_ha[index] = ha; 6694 6695 scsi_scan_host(sh); 6696 6697 return 0; 6698 6699 err_out: 6700 free_irq(ha->pcidev->irq, ha); 6701 err_out_sh: 6702 scsi_host_put(sh); 6703 return -1; 6704 } 6705 6706 /*---------------------------------------------------------------------------*/ 6707 /* Routine Name: ips_remove_device */ 6708 /* */ 6709 /* Routine Description: */ 6710 /* Remove one Adapter ( Hot Plugging ) */ 6711 /*---------------------------------------------------------------------------*/ 6712 static void 6713 ips_remove_device(struct pci_dev *pci_dev) 6714 { 6715 struct Scsi_Host *sh = pci_get_drvdata(pci_dev); 6716 6717 pci_set_drvdata(pci_dev, NULL); 6718 6719 ips_release(sh); 6720 6721 pci_release_regions(pci_dev); 6722 pci_disable_device(pci_dev); 6723 } 6724 6725 /****************************************************************************/ 6726 /* */ 6727 /* Routine Name: ips_module_init */ 6728 /* */ 6729 /* Routine Description: */ 6730 /* function called on module load */ 6731 /****************************************************************************/ 6732 static int __init 6733 ips_module_init(void) 6734 { 6735 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__) 6736 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n"); 6737 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 6738 #endif 6739 6740 if (pci_register_driver(&ips_pci_driver) < 0) 6741 return -ENODEV; 6742 ips_driver_template.module = THIS_MODULE; 6743 ips_order_controllers(); 6744 if (!ips_detect(&ips_driver_template)) { 6745 pci_unregister_driver(&ips_pci_driver); 6746 return -ENODEV; 6747 } 6748 register_reboot_notifier(&ips_notifier); 6749 return 0; 6750 } 6751 6752 /****************************************************************************/ 6753 /* */ 6754 /* Routine Name: ips_module_exit */ 6755 /* */ 6756 /* Routine Description: */ 6757 /* function called on module unload */ 6758 /****************************************************************************/ 6759 static void __exit 6760 ips_module_exit(void) 6761 { 6762 pci_unregister_driver(&ips_pci_driver); 6763 unregister_reboot_notifier(&ips_notifier); 6764 } 6765 6766 module_init(ips_module_init); 6767 module_exit(ips_module_exit); 6768 6769 /*---------------------------------------------------------------------------*/ 6770 /* Routine Name: ips_insert_device */ 6771 /* */ 6772 /* Routine Description: */ 6773 /* Add One Adapter ( Hot Plug ) */ 6774 /* */ 6775 /* Return Value: */ 6776 /* 0 if Successful, else non-zero */ 6777 /*---------------------------------------------------------------------------*/ 6778 static int 6779 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) 6780 { 6781 int index = -1; 6782 int rc; 6783 6784 METHOD_TRACE("ips_insert_device", 1); 6785 rc = pci_enable_device(pci_dev); 6786 if (rc) 6787 return rc; 6788 6789 rc = pci_request_regions(pci_dev, "ips"); 6790 if (rc) 6791 goto err_out; 6792 6793 rc = ips_init_phase1(pci_dev, &index); 6794 if (rc == SUCCESS) 6795 rc = ips_init_phase2(index); 6796 6797 if (ips_hotplug) 6798 if (ips_register_scsi(index)) { 6799 ips_free(ips_ha[index]); 6800 rc = -1; 6801 } 6802 6803 if (rc == SUCCESS) 6804 ips_num_controllers++; 6805 6806 ips_next_controller = ips_num_controllers; 6807 6808 if (rc < 0) { 6809 rc = -ENODEV; 6810 goto err_out_regions; 6811 } 6812 6813 pci_set_drvdata(pci_dev, ips_sh[index]); 6814 return 0; 6815 6816 err_out_regions: 6817 pci_release_regions(pci_dev); 6818 err_out: 6819 pci_disable_device(pci_dev); 6820 return rc; 6821 } 6822 6823 /*---------------------------------------------------------------------------*/ 6824 /* Routine Name: ips_init_phase1 */ 6825 /* */ 6826 /* Routine Description: */ 6827 /* Adapter Initialization */ 6828 /* */ 6829 /* Return Value: */ 6830 /* 0 if Successful, else non-zero */ 6831 /*---------------------------------------------------------------------------*/ 6832 static int 6833 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) 6834 { 6835 ips_ha_t *ha; 6836 uint32_t io_addr; 6837 uint32_t mem_addr; 6838 uint32_t io_len; 6839 uint32_t mem_len; 6840 uint8_t bus; 6841 uint8_t func; 6842 int j; 6843 int index; 6844 dma_addr_t dma_address; 6845 char __iomem *ioremap_ptr; 6846 char __iomem *mem_ptr; 6847 uint32_t IsDead; 6848 6849 METHOD_TRACE("ips_init_phase1", 1); 6850 index = IPS_MAX_ADAPTERS; 6851 for (j = 0; j < IPS_MAX_ADAPTERS; j++) { 6852 if (ips_ha[j] == NULL) { 6853 index = j; 6854 break; 6855 } 6856 } 6857 6858 if (index >= IPS_MAX_ADAPTERS) 6859 return -1; 6860 6861 /* stuff that we get in dev */ 6862 bus = pci_dev->bus->number; 6863 func = pci_dev->devfn; 6864 6865 /* Init MEM/IO addresses to 0 */ 6866 mem_addr = 0; 6867 io_addr = 0; 6868 mem_len = 0; 6869 io_len = 0; 6870 6871 for (j = 0; j < 2; j++) { 6872 if (!pci_resource_start(pci_dev, j)) 6873 break; 6874 6875 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) { 6876 io_addr = pci_resource_start(pci_dev, j); 6877 io_len = pci_resource_len(pci_dev, j); 6878 } else { 6879 mem_addr = pci_resource_start(pci_dev, j); 6880 mem_len = pci_resource_len(pci_dev, j); 6881 } 6882 } 6883 6884 /* setup memory mapped area (if applicable) */ 6885 if (mem_addr) { 6886 uint32_t base; 6887 uint32_t offs; 6888 6889 base = mem_addr & PAGE_MASK; 6890 offs = mem_addr - base; 6891 ioremap_ptr = ioremap(base, PAGE_SIZE); 6892 if (!ioremap_ptr) 6893 return -1; 6894 mem_ptr = ioremap_ptr + offs; 6895 } else { 6896 ioremap_ptr = NULL; 6897 mem_ptr = NULL; 6898 } 6899 6900 /* found a controller */ 6901 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL); 6902 if (ha == NULL) { 6903 IPS_PRINTK(KERN_WARNING, pci_dev, 6904 "Unable to allocate temporary ha struct\n"); 6905 return -1; 6906 } 6907 6908 ips_sh[index] = NULL; 6909 ips_ha[index] = ha; 6910 ha->active = 1; 6911 6912 /* Store info in HA structure */ 6913 ha->io_addr = io_addr; 6914 ha->io_len = io_len; 6915 ha->mem_addr = mem_addr; 6916 ha->mem_len = mem_len; 6917 ha->mem_ptr = mem_ptr; 6918 ha->ioremap_ptr = ioremap_ptr; 6919 ha->host_num = (uint32_t) index; 6920 ha->slot_num = PCI_SLOT(pci_dev->devfn); 6921 ha->pcidev = pci_dev; 6922 6923 /* 6924 * Set the pci_dev's dma_mask. Not all adapters support 64bit 6925 * addressing so don't enable it if the adapter can't support 6926 * it! Also, don't use 64bit addressing if dma addresses 6927 * are guaranteed to be < 4G. 6928 */ 6929 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) && 6930 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) { 6931 (ha)->flags |= IPS_HA_ENH_SG; 6932 } else { 6933 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) { 6934 printk(KERN_WARNING "Unable to set DMA Mask\n"); 6935 return ips_abort_init(ha, index); 6936 } 6937 } 6938 if(ips_cd_boot && !ips_FlashData){ 6939 ips_FlashData = dma_alloc_coherent(&pci_dev->dev, 6940 PAGE_SIZE << 7, &ips_flashbusaddr, GFP_KERNEL); 6941 } 6942 6943 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ), 6944 &ha->enq_busaddr, GFP_KERNEL); 6945 if (!ha->enq) { 6946 IPS_PRINTK(KERN_WARNING, pci_dev, 6947 "Unable to allocate host inquiry structure\n"); 6948 return ips_abort_init(ha, index); 6949 } 6950 6951 ha->adapt = dma_alloc_coherent(&pci_dev->dev, 6952 sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD), 6953 &dma_address, GFP_KERNEL); 6954 if (!ha->adapt) { 6955 IPS_PRINTK(KERN_WARNING, pci_dev, 6956 "Unable to allocate host adapt & dummy structures\n"); 6957 return ips_abort_init(ha, index); 6958 } 6959 ha->adapt->hw_status_start = dma_address; 6960 ha->dummy = (void *) (ha->adapt + 1); 6961 6962 6963 6964 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev, 6965 sizeof (IPS_LD_INFO), &dma_address, GFP_KERNEL); 6966 if (!ha->logical_drive_info) { 6967 IPS_PRINTK(KERN_WARNING, pci_dev, 6968 "Unable to allocate logical drive info structure\n"); 6969 return ips_abort_init(ha, index); 6970 } 6971 ha->logical_drive_info_dma_addr = dma_address; 6972 6973 6974 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL); 6975 6976 if (!ha->conf) { 6977 IPS_PRINTK(KERN_WARNING, pci_dev, 6978 "Unable to allocate host conf structure\n"); 6979 return ips_abort_init(ha, index); 6980 } 6981 6982 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL); 6983 6984 if (!ha->nvram) { 6985 IPS_PRINTK(KERN_WARNING, pci_dev, 6986 "Unable to allocate host NVRAM structure\n"); 6987 return ips_abort_init(ha, index); 6988 } 6989 6990 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL); 6991 6992 if (!ha->subsys) { 6993 IPS_PRINTK(KERN_WARNING, pci_dev, 6994 "Unable to allocate host subsystem structure\n"); 6995 return ips_abort_init(ha, index); 6996 } 6997 6998 /* the ioctl buffer is now used during adapter initialization, so its 6999 * successful allocation is now required */ 7000 if (ips_ioctlsize < PAGE_SIZE) 7001 ips_ioctlsize = PAGE_SIZE; 7002 7003 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize, 7004 &ha->ioctl_busaddr, GFP_KERNEL); 7005 ha->ioctl_len = ips_ioctlsize; 7006 if (!ha->ioctl_data) { 7007 IPS_PRINTK(KERN_WARNING, pci_dev, 7008 "Unable to allocate IOCTL data\n"); 7009 return ips_abort_init(ha, index); 7010 } 7011 7012 /* 7013 * Setup Functions 7014 */ 7015 ips_setup_funclist(ha); 7016 7017 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) { 7018 /* If Morpheus appears dead, reset it */ 7019 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 7020 if (IsDead == 0xDEADBEEF) { 7021 ips_reset_morpheus(ha); 7022 } 7023 } 7024 7025 /* 7026 * Initialize the card if it isn't already 7027 */ 7028 7029 if (!(*ha->func.isinit) (ha)) { 7030 if (!(*ha->func.init) (ha)) { 7031 /* 7032 * Initialization failed 7033 */ 7034 IPS_PRINTK(KERN_WARNING, pci_dev, 7035 "Unable to initialize controller\n"); 7036 return ips_abort_init(ha, index); 7037 } 7038 } 7039 7040 *indexPtr = index; 7041 return SUCCESS; 7042 } 7043 7044 /*---------------------------------------------------------------------------*/ 7045 /* Routine Name: ips_init_phase2 */ 7046 /* */ 7047 /* Routine Description: */ 7048 /* Adapter Initialization Phase 2 */ 7049 /* */ 7050 /* Return Value: */ 7051 /* 0 if Successful, else non-zero */ 7052 /*---------------------------------------------------------------------------*/ 7053 static int 7054 ips_init_phase2(int index) 7055 { 7056 ips_ha_t *ha; 7057 7058 ha = ips_ha[index]; 7059 7060 METHOD_TRACE("ips_init_phase2", 1); 7061 if (!ha->active) { 7062 ips_ha[index] = NULL; 7063 return -1; 7064 } 7065 7066 /* Install the interrupt handler */ 7067 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 7068 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7069 "Unable to install interrupt handler\n"); 7070 return ips_abort_init(ha, index); 7071 } 7072 7073 /* 7074 * Allocate a temporary SCB for initialization 7075 */ 7076 ha->max_cmds = 1; 7077 if (!ips_allocatescbs(ha)) { 7078 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7079 "Unable to allocate a CCB\n"); 7080 free_irq(ha->pcidev->irq, ha); 7081 return ips_abort_init(ha, index); 7082 } 7083 7084 if (!ips_hainit(ha)) { 7085 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7086 "Unable to initialize controller\n"); 7087 free_irq(ha->pcidev->irq, ha); 7088 return ips_abort_init(ha, index); 7089 } 7090 /* Free the temporary SCB */ 7091 ips_deallocatescbs(ha, 1); 7092 7093 /* allocate CCBs */ 7094 if (!ips_allocatescbs(ha)) { 7095 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7096 "Unable to allocate CCBs\n"); 7097 free_irq(ha->pcidev->irq, ha); 7098 return ips_abort_init(ha, index); 7099 } 7100 7101 return SUCCESS; 7102 } 7103 7104 MODULE_LICENSE("GPL"); 7105 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING); 7106 MODULE_VERSION(IPS_VER_STRING); 7107 7108 7109 /* 7110 * Overrides for Emacs so that we almost follow Linus's tabbing style. 7111 * Emacs will notice this stuff at the end of the file and automatically 7112 * adjust the settings for this buffer only. This must remain at the end 7113 * of the file. 7114 * --------------------------------------------------------------------------- 7115 * Local variables: 7116 * c-indent-level: 2 7117 * c-brace-imaginary-offset: 0 7118 * c-brace-offset: -2 7119 * c-argdecl-indent: 2 7120 * c-label-offset: -2 7121 * c-continued-statement-offset: 2 7122 * c-continued-brace-offset: 0 7123 * indent-tabs-mode: nil 7124 * tab-width: 8 7125 * End: 7126 */ 7127