1 /*****************************************************************************/ 2 /* ips.c -- driver for the Adaptec / IBM ServeRAID controller */ 3 /* */ 4 /* Written By: Keith Mitchell, IBM Corporation */ 5 /* Jack Hammer, Adaptec, Inc. */ 6 /* David Jeffery, Adaptec, Inc. */ 7 /* */ 8 /* Copyright (C) 2000 IBM Corporation */ 9 /* Copyright (C) 2002,2003 Adaptec, Inc. */ 10 /* */ 11 /* This program is free software; you can redistribute it and/or modify */ 12 /* it under the terms of the GNU General Public License as published by */ 13 /* the Free Software Foundation; either version 2 of the License, or */ 14 /* (at your option) any later version. */ 15 /* */ 16 /* This program is distributed in the hope that it will be useful, */ 17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */ 18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ 19 /* GNU General Public License for more details. */ 20 /* */ 21 /* NO WARRANTY */ 22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */ 23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */ 24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */ 25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */ 26 /* solely responsible for determining the appropriateness of using and */ 27 /* distributing the Program and assumes all risks associated with its */ 28 /* exercise of rights under this Agreement, including but not limited to */ 29 /* the risks and costs of program errors, damage to or loss of data, */ 30 /* programs or equipment, and unavailability or interruption of operations. */ 31 /* */ 32 /* DISCLAIMER OF LIABILITY */ 33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */ 34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */ 35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */ 36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */ 37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */ 38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */ 39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */ 40 /* */ 41 /* You should have received a copy of the GNU General Public License */ 42 /* along with this program; if not, write to the Free Software */ 43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ 44 /* */ 45 /* Bugs/Comments/Suggestions about this driver should be mailed to: */ 46 /* ipslinux@adaptec.com */ 47 /* */ 48 /* For system support issues, contact your local IBM Customer support. */ 49 /* Directions to find IBM Customer Support for each country can be found at: */ 50 /* http://www.ibm.com/planetwide/ */ 51 /* */ 52 /*****************************************************************************/ 53 54 /*****************************************************************************/ 55 /* Change Log */ 56 /* */ 57 /* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */ 58 /* 0.99.03 - Make interrupt routine handle all completed request on the */ 59 /* adapter not just the first one */ 60 /* - Make sure passthru commands get woken up if we run out of */ 61 /* SCBs */ 62 /* - Send all of the commands on the queue at once rather than */ 63 /* one at a time since the card will support it. */ 64 /* 0.99.04 - Fix race condition in the passthru mechanism -- this required */ 65 /* the interface to the utilities to change */ 66 /* - Fix error recovery code */ 67 /* 0.99.05 - Fix an oops when we get certain passthru commands */ 68 /* 1.00.00 - Initial Public Release */ 69 /* Functionally equivalent to 0.99.05 */ 70 /* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */ 71 /* - Change version to 3.60 to coincide with release numbering. */ 72 /* 3.60.01 - Remove bogus error check in passthru routine */ 73 /* 3.60.02 - Make DCDB direction based on lookup table */ 74 /* - Only allow one DCDB command to a SCSI ID at a time */ 75 /* 4.00.00 - Add support for ServeRAID 4 */ 76 /* 4.00.01 - Add support for First Failure Data Capture */ 77 /* 4.00.02 - Fix problem with PT DCDB with no buffer */ 78 /* 4.00.03 - Add alternative passthru interface */ 79 /* - Add ability to flash BIOS */ 80 /* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */ 81 /* 4.00.05 - Remove wish_block from init routine */ 82 /* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */ 83 /* 2.3.18 and later */ 84 /* - Sync with other changes from the 2.3 kernels */ 85 /* 4.00.06 - Fix timeout with initial FFDC command */ 86 /* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */ 87 /* 4.10.00 - Add support for ServeRAID 4M/4L */ 88 /* 4.10.13 - Fix for dynamic unload and proc file system */ 89 /* 4.20.03 - Rename version to coincide with new release schedules */ 90 /* Performance fixes */ 91 /* Fix truncation of /proc files with cat */ 92 /* Merge in changes through kernel 2.4.0test1ac21 */ 93 /* 4.20.13 - Fix some failure cases / reset code */ 94 /* - Hook into the reboot_notifier to flush the controller cache */ 95 /* 4.50.01 - Fix problem when there is a hole in logical drive numbering */ 96 /* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */ 97 /* - Add IPSSEND Flash Support */ 98 /* - Set Sense Data for Unknown SCSI Command */ 99 /* - Use Slot Number from NVRAM Page 5 */ 100 /* - Restore caller's DCDB Structure */ 101 /* 4.70.12 - Corrective actions for bad controller ( during initialization )*/ 102 /* 4.70.13 - Don't Send CDB's if we already know the device is not present */ 103 /* - Don't release HA Lock in ips_next() until SC taken off queue */ 104 /* - Unregister SCSI device in ips_release() */ 105 /* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */ 106 /* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */ 107 /* Code Clean-Up for 2.4.x kernel */ 108 /* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */ 109 /* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */ 110 /* - Don't Issue Internal FFDC Command if there are Active Commands */ 111 /* - Close Window for getting too many IOCTL's active */ 112 /* 4.80.00 - Make ia64 Safe */ 113 /* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */ 114 /* - Adjustments to Device Queue Depth */ 115 /* 4.80.14 - Take all semaphores off stack */ 116 /* - Clean Up New_IOCTL path */ 117 /* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */ 118 /* - 5 second delay needed after resetting an i960 adapter */ 119 /* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */ 120 /* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */ 121 /* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */ 122 /* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */ 123 /* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */ 124 /* 4.90.11 - Don't actually RESET unless it's physically required */ 125 /* - Remove unused compile options */ 126 /* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */ 127 /* - Get rid on IOCTL_NEW_COMMAND code */ 128 /* - Add Extended DCDB Commands for Tape Support in 5I */ 129 /* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */ 130 /* 5.10.15 - remove unused code (sem, macros, etc.) */ 131 /* 5.30.00 - use __devexit_p() */ 132 /* 6.00.00 - Add 6x Adapters and Battery Flash */ 133 /* 6.10.00 - Remove 1G Addressing Limitations */ 134 /* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */ 135 /* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */ 136 /* 7.10.18 - Add highmem_io flag in SCSI Templete for 2.4 kernels */ 137 /* - Fix path/name for scsi_hosts.h include for 2.6 kernels */ 138 /* - Fix sort order of 7k */ 139 /* - Remove 3 unused "inline" functions */ 140 /* 7.12.xx - Use STATIC functions wherever possible */ 141 /* - Clean up deprecated MODULE_PARM calls */ 142 /* 7.12.05 - Remove Version Matching per IBM request */ 143 /*****************************************************************************/ 144 145 /* 146 * Conditional Compilation directives for this driver: 147 * 148 * IPS_DEBUG - Turn on debugging info 149 * 150 * Parameters: 151 * 152 * debug:<number> - Set debug level to <number> 153 * NOTE: only works when IPS_DEBUG compile directive is used. 154 * 1 - Normal debug messages 155 * 2 - Verbose debug messages 156 * 11 - Method trace (non interrupt) 157 * 12 - Method trace (includes interrupt) 158 * 159 * noi2o - Don't use I2O Queues (ServeRAID 4 only) 160 * nommap - Don't use memory mapped I/O 161 * ioctlsize - Initial size of the IOCTL buffer 162 */ 163 164 #include <asm/io.h> 165 #include <asm/byteorder.h> 166 #include <asm/page.h> 167 #include <linux/stddef.h> 168 #include <linux/string.h> 169 #include <linux/errno.h> 170 #include <linux/kernel.h> 171 #include <linux/ioport.h> 172 #include <linux/slab.h> 173 #include <linux/delay.h> 174 #include <linux/pci.h> 175 #include <linux/proc_fs.h> 176 #include <linux/reboot.h> 177 #include <linux/interrupt.h> 178 179 #include <linux/blkdev.h> 180 #include <linux/types.h> 181 #include <linux/dma-mapping.h> 182 183 #include <scsi/sg.h> 184 #include "scsi.h" 185 #include <scsi/scsi_host.h> 186 187 #include "ips.h" 188 189 #include <linux/module.h> 190 191 #include <linux/stat.h> 192 193 #include <linux/spinlock.h> 194 #include <linux/init.h> 195 196 #include <linux/smp.h> 197 198 #ifdef MODULE 199 static char *ips = NULL; 200 module_param(ips, charp, 0); 201 #endif 202 203 /* 204 * DRIVER_VER 205 */ 206 #define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING 207 #define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " " 208 209 #define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \ 210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \ 211 DMA_BIDIRECTIONAL : \ 212 scb->scsi_cmd->sc_data_direction) 213 214 #ifdef IPS_DEBUG 215 #define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n"); 216 #define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n"); 217 #define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v); 218 #else 219 #define METHOD_TRACE(s, i) 220 #define DEBUG(i, s) 221 #define DEBUG_VAR(i, s, v...) 222 #endif 223 224 /* 225 * Function prototypes 226 */ 227 static int ips_eh_abort(struct scsi_cmnd *); 228 static int ips_eh_reset(struct scsi_cmnd *); 229 static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *); 230 static const char *ips_info(struct Scsi_Host *); 231 static irqreturn_t do_ipsintr(int, void *); 232 static int ips_hainit(ips_ha_t *); 233 static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *); 234 static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int); 235 static int ips_send_cmd(ips_ha_t *, ips_scb_t *); 236 static int ips_online(ips_ha_t *, ips_scb_t *); 237 static int ips_inquiry(ips_ha_t *, ips_scb_t *); 238 static int ips_rdcap(ips_ha_t *, ips_scb_t *); 239 static int ips_msense(ips_ha_t *, ips_scb_t *); 240 static int ips_reqsen(ips_ha_t *, ips_scb_t *); 241 static int ips_deallocatescbs(ips_ha_t *, int); 242 static int ips_allocatescbs(ips_ha_t *); 243 static int ips_reset_copperhead(ips_ha_t *); 244 static int ips_reset_copperhead_memio(ips_ha_t *); 245 static int ips_reset_morpheus(ips_ha_t *); 246 static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *); 247 static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *); 248 static int ips_issue_i2o(ips_ha_t *, ips_scb_t *); 249 static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *); 250 static int ips_isintr_copperhead(ips_ha_t *); 251 static int ips_isintr_copperhead_memio(ips_ha_t *); 252 static int ips_isintr_morpheus(ips_ha_t *); 253 static int ips_wait(ips_ha_t *, int, int); 254 static int ips_write_driver_status(ips_ha_t *, int); 255 static int ips_read_adapter_status(ips_ha_t *, int); 256 static int ips_read_subsystem_parameters(ips_ha_t *, int); 257 static int ips_read_config(ips_ha_t *, int); 258 static int ips_clear_adapter(ips_ha_t *, int); 259 static int ips_readwrite_page5(ips_ha_t *, int, int); 260 static int ips_init_copperhead(ips_ha_t *); 261 static int ips_init_copperhead_memio(ips_ha_t *); 262 static int ips_init_morpheus(ips_ha_t *); 263 static int ips_isinit_copperhead(ips_ha_t *); 264 static int ips_isinit_copperhead_memio(ips_ha_t *); 265 static int ips_isinit_morpheus(ips_ha_t *); 266 static int ips_erase_bios(ips_ha_t *); 267 static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t); 268 static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t); 269 static int ips_erase_bios_memio(ips_ha_t *); 270 static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 271 static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t); 272 static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 273 static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 274 static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 275 static void ips_free_flash_copperhead(ips_ha_t * ha); 276 static void ips_get_bios_version(ips_ha_t *, int); 277 static void ips_identify_controller(ips_ha_t *); 278 static void ips_chkstatus(ips_ha_t *, IPS_STATUS *); 279 static void ips_enable_int_copperhead(ips_ha_t *); 280 static void ips_enable_int_copperhead_memio(ips_ha_t *); 281 static void ips_enable_int_morpheus(ips_ha_t *); 282 static int ips_intr_copperhead(ips_ha_t *); 283 static int ips_intr_morpheus(ips_ha_t *); 284 static void ips_next(ips_ha_t *, int); 285 static void ipsintr_blocking(ips_ha_t *, struct ips_scb *); 286 static void ipsintr_done(ips_ha_t *, struct ips_scb *); 287 static void ips_done(ips_ha_t *, ips_scb_t *); 288 static void ips_free(ips_ha_t *); 289 static void ips_init_scb(ips_ha_t *, ips_scb_t *); 290 static void ips_freescb(ips_ha_t *, ips_scb_t *); 291 static void ips_setup_funclist(ips_ha_t *); 292 static void ips_statinit(ips_ha_t *); 293 static void ips_statinit_memio(ips_ha_t *); 294 static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time64_t); 295 static void ips_ffdc_reset(ips_ha_t *, int); 296 static void ips_ffdc_time(ips_ha_t *); 297 static uint32_t ips_statupd_copperhead(ips_ha_t *); 298 static uint32_t ips_statupd_copperhead_memio(ips_ha_t *); 299 static uint32_t ips_statupd_morpheus(ips_ha_t *); 300 static ips_scb_t *ips_getscb(ips_ha_t *); 301 static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *); 302 static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *); 303 static void ips_putq_copp_tail(ips_copp_queue_t *, 304 ips_copp_wait_item_t *); 305 static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *); 306 static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *); 307 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *); 308 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *, 309 struct scsi_cmnd *); 310 static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *, 311 ips_copp_wait_item_t *); 312 static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *); 313 314 static int ips_is_passthru(struct scsi_cmnd *); 315 static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int); 316 static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *); 317 static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *); 318 static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data, 319 unsigned int count); 320 static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data, 321 unsigned int count); 322 323 static int ips_write_info(struct Scsi_Host *, char *, int); 324 static int ips_show_info(struct seq_file *, struct Scsi_Host *); 325 static int ips_host_info(ips_ha_t *, struct seq_file *); 326 static int ips_abort_init(ips_ha_t * ha, int index); 327 static int ips_init_phase2(int index); 328 329 static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr); 330 static int ips_register_scsi(int index); 331 332 static int ips_poll_for_flush_complete(ips_ha_t * ha); 333 static void ips_flush_and_reset(ips_ha_t *ha); 334 335 /* 336 * global variables 337 */ 338 static const char ips_name[] = "ips"; 339 static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */ 340 static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */ 341 static unsigned int ips_next_controller; 342 static unsigned int ips_num_controllers; 343 static unsigned int ips_released_controllers; 344 static int ips_hotplug; 345 static int ips_cmd_timeout = 60; 346 static int ips_reset_timeout = 60 * 5; 347 static int ips_force_memio = 1; /* Always use Memory Mapped I/O */ 348 static int ips_force_i2o = 1; /* Always use I2O command delivery */ 349 static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */ 350 static int ips_cd_boot; /* Booting from Manager CD */ 351 static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */ 352 static dma_addr_t ips_flashbusaddr; 353 static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */ 354 static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */ 355 static struct scsi_host_template ips_driver_template = { 356 .info = ips_info, 357 .queuecommand = ips_queue, 358 .eh_abort_handler = ips_eh_abort, 359 .eh_host_reset_handler = ips_eh_reset, 360 .proc_name = "ips", 361 .show_info = ips_show_info, 362 .write_info = ips_write_info, 363 .slave_configure = ips_slave_configure, 364 .bios_param = ips_biosparam, 365 .this_id = -1, 366 .sg_tablesize = IPS_MAX_SG, 367 .cmd_per_lun = 3, 368 .no_write_same = 1, 369 }; 370 371 372 /* This table describes all ServeRAID Adapters */ 373 static struct pci_device_id ips_pci_table[] = { 374 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 375 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 376 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 }, 377 { 0, } 378 }; 379 380 MODULE_DEVICE_TABLE( pci, ips_pci_table ); 381 382 static char ips_hot_plug_name[] = "ips"; 383 384 static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent); 385 static void ips_remove_device(struct pci_dev *pci_dev); 386 387 static struct pci_driver ips_pci_driver = { 388 .name = ips_hot_plug_name, 389 .id_table = ips_pci_table, 390 .probe = ips_insert_device, 391 .remove = ips_remove_device, 392 }; 393 394 395 /* 396 * Necessary forward function protoypes 397 */ 398 static int ips_halt(struct notifier_block *nb, ulong event, void *buf); 399 400 #define MAX_ADAPTER_NAME 15 401 402 static char ips_adapter_name[][30] = { 403 "ServeRAID", 404 "ServeRAID II", 405 "ServeRAID on motherboard", 406 "ServeRAID on motherboard", 407 "ServeRAID 3H", 408 "ServeRAID 3L", 409 "ServeRAID 4H", 410 "ServeRAID 4M", 411 "ServeRAID 4L", 412 "ServeRAID 4Mx", 413 "ServeRAID 4Lx", 414 "ServeRAID 5i", 415 "ServeRAID 5i", 416 "ServeRAID 6M", 417 "ServeRAID 6i", 418 "ServeRAID 7t", 419 "ServeRAID 7k", 420 "ServeRAID 7M" 421 }; 422 423 static struct notifier_block ips_notifier = { 424 ips_halt, NULL, 0 425 }; 426 427 /* 428 * Direction table 429 */ 430 static char ips_command_direction[] = { 431 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, 432 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, 433 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 434 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 435 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT, 436 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT, 437 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN, 438 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 439 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK, 440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 441 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, 442 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, 443 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, 444 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE, 445 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, 446 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, 447 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 448 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 449 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 450 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 451 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 453 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 454 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 464 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE, 465 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT, 466 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE, 467 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, 468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 469 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 470 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 471 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 472 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT, 478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, 481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK 482 }; 483 484 485 /****************************************************************************/ 486 /* */ 487 /* Routine Name: ips_setup */ 488 /* */ 489 /* Routine Description: */ 490 /* */ 491 /* setup parameters to the driver */ 492 /* */ 493 /****************************************************************************/ 494 static int 495 ips_setup(char *ips_str) 496 { 497 498 int i; 499 char *key; 500 char *value; 501 static const IPS_OPTION options[] = { 502 {"noi2o", &ips_force_i2o, 0}, 503 {"nommap", &ips_force_memio, 0}, 504 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE}, 505 {"cdboot", &ips_cd_boot, 0}, 506 {"maxcmds", &MaxLiteCmds, 32}, 507 }; 508 509 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */ 510 /* Search for value */ 511 while ((key = strsep(&ips_str, ",."))) { 512 if (!*key) 513 continue; 514 value = strchr(key, ':'); 515 if (value) 516 *value++ = '\0'; 517 /* 518 * We now have key/value pairs. 519 * Update the variables 520 */ 521 for (i = 0; i < ARRAY_SIZE(options); i++) { 522 if (strncasecmp 523 (key, options[i].option_name, 524 strlen(options[i].option_name)) == 0) { 525 if (value) 526 *options[i].option_flag = 527 simple_strtoul(value, NULL, 0); 528 else 529 *options[i].option_flag = 530 options[i].option_value; 531 break; 532 } 533 } 534 } 535 536 return (1); 537 } 538 539 __setup("ips=", ips_setup); 540 541 /****************************************************************************/ 542 /* */ 543 /* Routine Name: ips_detect */ 544 /* */ 545 /* Routine Description: */ 546 /* */ 547 /* Detect and initialize the driver */ 548 /* */ 549 /* NOTE: this routine is called under the io_request_lock spinlock */ 550 /* */ 551 /****************************************************************************/ 552 static int 553 ips_detect(struct scsi_host_template * SHT) 554 { 555 int i; 556 557 METHOD_TRACE("ips_detect", 1); 558 559 #ifdef MODULE 560 if (ips) 561 ips_setup(ips); 562 #endif 563 564 for (i = 0; i < ips_num_controllers; i++) { 565 if (ips_register_scsi(i)) 566 ips_free(ips_ha[i]); 567 ips_released_controllers++; 568 } 569 ips_hotplug = 1; 570 return (ips_num_controllers); 571 } 572 573 /****************************************************************************/ 574 /* configure the function pointers to use the functions that will work */ 575 /* with the found version of the adapter */ 576 /****************************************************************************/ 577 static void 578 ips_setup_funclist(ips_ha_t * ha) 579 { 580 581 /* 582 * Setup Functions 583 */ 584 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) { 585 /* morpheus / marco / sebring */ 586 ha->func.isintr = ips_isintr_morpheus; 587 ha->func.isinit = ips_isinit_morpheus; 588 ha->func.issue = ips_issue_i2o_memio; 589 ha->func.init = ips_init_morpheus; 590 ha->func.statupd = ips_statupd_morpheus; 591 ha->func.reset = ips_reset_morpheus; 592 ha->func.intr = ips_intr_morpheus; 593 ha->func.enableint = ips_enable_int_morpheus; 594 } else if (IPS_USE_MEMIO(ha)) { 595 /* copperhead w/MEMIO */ 596 ha->func.isintr = ips_isintr_copperhead_memio; 597 ha->func.isinit = ips_isinit_copperhead_memio; 598 ha->func.init = ips_init_copperhead_memio; 599 ha->func.statupd = ips_statupd_copperhead_memio; 600 ha->func.statinit = ips_statinit_memio; 601 ha->func.reset = ips_reset_copperhead_memio; 602 ha->func.intr = ips_intr_copperhead; 603 ha->func.erasebios = ips_erase_bios_memio; 604 ha->func.programbios = ips_program_bios_memio; 605 ha->func.verifybios = ips_verify_bios_memio; 606 ha->func.enableint = ips_enable_int_copperhead_memio; 607 if (IPS_USE_I2O_DELIVER(ha)) 608 ha->func.issue = ips_issue_i2o_memio; 609 else 610 ha->func.issue = ips_issue_copperhead_memio; 611 } else { 612 /* copperhead */ 613 ha->func.isintr = ips_isintr_copperhead; 614 ha->func.isinit = ips_isinit_copperhead; 615 ha->func.init = ips_init_copperhead; 616 ha->func.statupd = ips_statupd_copperhead; 617 ha->func.statinit = ips_statinit; 618 ha->func.reset = ips_reset_copperhead; 619 ha->func.intr = ips_intr_copperhead; 620 ha->func.erasebios = ips_erase_bios; 621 ha->func.programbios = ips_program_bios; 622 ha->func.verifybios = ips_verify_bios; 623 ha->func.enableint = ips_enable_int_copperhead; 624 625 if (IPS_USE_I2O_DELIVER(ha)) 626 ha->func.issue = ips_issue_i2o; 627 else 628 ha->func.issue = ips_issue_copperhead; 629 } 630 } 631 632 /****************************************************************************/ 633 /* */ 634 /* Routine Name: ips_release */ 635 /* */ 636 /* Routine Description: */ 637 /* */ 638 /* Remove a driver */ 639 /* */ 640 /****************************************************************************/ 641 static int 642 ips_release(struct Scsi_Host *sh) 643 { 644 ips_scb_t *scb; 645 ips_ha_t *ha; 646 int i; 647 648 METHOD_TRACE("ips_release", 1); 649 650 scsi_remove_host(sh); 651 652 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ; 653 654 if (i == IPS_MAX_ADAPTERS) { 655 printk(KERN_WARNING 656 "(%s) release, invalid Scsi_Host pointer.\n", ips_name); 657 BUG(); 658 return (FALSE); 659 } 660 661 ha = IPS_HA(sh); 662 663 if (!ha) 664 return (FALSE); 665 666 /* flush the cache on the controller */ 667 scb = &ha->scbs[ha->max_cmds - 1]; 668 669 ips_init_scb(ha, scb); 670 671 scb->timeout = ips_cmd_timeout; 672 scb->cdb[0] = IPS_CMD_FLUSH; 673 674 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 675 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 676 scb->cmd.flush_cache.state = IPS_NORM_STATE; 677 scb->cmd.flush_cache.reserved = 0; 678 scb->cmd.flush_cache.reserved2 = 0; 679 scb->cmd.flush_cache.reserved3 = 0; 680 scb->cmd.flush_cache.reserved4 = 0; 681 682 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 683 684 /* send command */ 685 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE) 686 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n"); 687 688 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n"); 689 690 ips_sh[i] = NULL; 691 ips_ha[i] = NULL; 692 693 /* free extra memory */ 694 ips_free(ha); 695 696 /* free IRQ */ 697 free_irq(ha->pcidev->irq, ha); 698 699 scsi_host_put(sh); 700 701 ips_released_controllers++; 702 703 return (FALSE); 704 } 705 706 /****************************************************************************/ 707 /* */ 708 /* Routine Name: ips_halt */ 709 /* */ 710 /* Routine Description: */ 711 /* */ 712 /* Perform cleanup when the system reboots */ 713 /* */ 714 /****************************************************************************/ 715 static int 716 ips_halt(struct notifier_block *nb, ulong event, void *buf) 717 { 718 ips_scb_t *scb; 719 ips_ha_t *ha; 720 int i; 721 722 if ((event != SYS_RESTART) && (event != SYS_HALT) && 723 (event != SYS_POWER_OFF)) 724 return (NOTIFY_DONE); 725 726 for (i = 0; i < ips_next_controller; i++) { 727 ha = (ips_ha_t *) ips_ha[i]; 728 729 if (!ha) 730 continue; 731 732 if (!ha->active) 733 continue; 734 735 /* flush the cache on the controller */ 736 scb = &ha->scbs[ha->max_cmds - 1]; 737 738 ips_init_scb(ha, scb); 739 740 scb->timeout = ips_cmd_timeout; 741 scb->cdb[0] = IPS_CMD_FLUSH; 742 743 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 744 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 745 scb->cmd.flush_cache.state = IPS_NORM_STATE; 746 scb->cmd.flush_cache.reserved = 0; 747 scb->cmd.flush_cache.reserved2 = 0; 748 scb->cmd.flush_cache.reserved3 = 0; 749 scb->cmd.flush_cache.reserved4 = 0; 750 751 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n"); 752 753 /* send command */ 754 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == 755 IPS_FAILURE) 756 IPS_PRINTK(KERN_WARNING, ha->pcidev, 757 "Incomplete Flush.\n"); 758 else 759 IPS_PRINTK(KERN_WARNING, ha->pcidev, 760 "Flushing Complete.\n"); 761 } 762 763 return (NOTIFY_OK); 764 } 765 766 /****************************************************************************/ 767 /* */ 768 /* Routine Name: ips_eh_abort */ 769 /* */ 770 /* Routine Description: */ 771 /* */ 772 /* Abort a command (using the new error code stuff) */ 773 /* Note: this routine is called under the io_request_lock */ 774 /****************************************************************************/ 775 int ips_eh_abort(struct scsi_cmnd *SC) 776 { 777 ips_ha_t *ha; 778 ips_copp_wait_item_t *item; 779 int ret; 780 struct Scsi_Host *host; 781 782 METHOD_TRACE("ips_eh_abort", 1); 783 784 if (!SC) 785 return (FAILED); 786 787 host = SC->device->host; 788 ha = (ips_ha_t *) SC->device->host->hostdata; 789 790 if (!ha) 791 return (FAILED); 792 793 if (!ha->active) 794 return (FAILED); 795 796 spin_lock(host->host_lock); 797 798 /* See if the command is on the copp queue */ 799 item = ha->copp_waitlist.head; 800 while ((item) && (item->scsi_cmd != SC)) 801 item = item->next; 802 803 if (item) { 804 /* Found it */ 805 ips_removeq_copp(&ha->copp_waitlist, item); 806 ret = (SUCCESS); 807 808 /* See if the command is on the wait queue */ 809 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 810 /* command not sent yet */ 811 ret = (SUCCESS); 812 } else { 813 /* command must have already been sent */ 814 ret = (FAILED); 815 } 816 817 spin_unlock(host->host_lock); 818 return ret; 819 } 820 821 /****************************************************************************/ 822 /* */ 823 /* Routine Name: ips_eh_reset */ 824 /* */ 825 /* Routine Description: */ 826 /* */ 827 /* Reset the controller (with new eh error code) */ 828 /* */ 829 /* NOTE: this routine is called under the io_request_lock spinlock */ 830 /* */ 831 /****************************************************************************/ 832 static int __ips_eh_reset(struct scsi_cmnd *SC) 833 { 834 int ret; 835 int i; 836 ips_ha_t *ha; 837 ips_scb_t *scb; 838 ips_copp_wait_item_t *item; 839 840 METHOD_TRACE("ips_eh_reset", 1); 841 842 #ifdef NO_IPS_RESET 843 return (FAILED); 844 #else 845 846 if (!SC) { 847 DEBUG(1, "Reset called with NULL scsi command"); 848 849 return (FAILED); 850 } 851 852 ha = (ips_ha_t *) SC->device->host->hostdata; 853 854 if (!ha) { 855 DEBUG(1, "Reset called with NULL ha struct"); 856 857 return (FAILED); 858 } 859 860 if (!ha->active) 861 return (FAILED); 862 863 /* See if the command is on the copp queue */ 864 item = ha->copp_waitlist.head; 865 while ((item) && (item->scsi_cmd != SC)) 866 item = item->next; 867 868 if (item) { 869 /* Found it */ 870 ips_removeq_copp(&ha->copp_waitlist, item); 871 return (SUCCESS); 872 } 873 874 /* See if the command is on the wait queue */ 875 if (ips_removeq_wait(&ha->scb_waitlist, SC)) { 876 /* command not sent yet */ 877 return (SUCCESS); 878 } 879 880 /* An explanation for the casual observer: */ 881 /* Part of the function of a RAID controller is automatic error */ 882 /* detection and recovery. As such, the only problem that physically */ 883 /* resetting an adapter will ever fix is when, for some reason, */ 884 /* the driver is not successfully communicating with the adapter. */ 885 /* Therefore, we will attempt to flush this adapter. If that succeeds, */ 886 /* then there's no real purpose in a physical reset. This will complete */ 887 /* much faster and avoids any problems that might be caused by a */ 888 /* physical reset ( such as having to fail all the outstanding I/O's ). */ 889 890 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */ 891 scb = &ha->scbs[ha->max_cmds - 1]; 892 893 ips_init_scb(ha, scb); 894 895 scb->timeout = ips_cmd_timeout; 896 scb->cdb[0] = IPS_CMD_FLUSH; 897 898 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 899 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb); 900 scb->cmd.flush_cache.state = IPS_NORM_STATE; 901 scb->cmd.flush_cache.reserved = 0; 902 scb->cmd.flush_cache.reserved2 = 0; 903 scb->cmd.flush_cache.reserved3 = 0; 904 scb->cmd.flush_cache.reserved4 = 0; 905 906 /* Attempt the flush command */ 907 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL); 908 if (ret == IPS_SUCCESS) { 909 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 910 "Reset Request - Flushed Cache\n"); 911 return (SUCCESS); 912 } 913 } 914 915 /* Either we can't communicate with the adapter or it's an IOCTL request */ 916 /* from a utility. A physical reset is needed at this point. */ 917 918 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */ 919 920 /* 921 * command must have already been sent 922 * reset the controller 923 */ 924 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n"); 925 ret = (*ha->func.reset) (ha); 926 927 if (!ret) { 928 struct scsi_cmnd *scsi_cmd; 929 930 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 931 "Controller reset failed - controller now offline.\n"); 932 933 /* Now fail all of the active commands */ 934 DEBUG_VAR(1, "(%s%d) Failing active commands", 935 ips_name, ha->host_num); 936 937 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 938 scb->scsi_cmd->result = DID_ERROR << 16; 939 scsi_done(scb->scsi_cmd); 940 ips_freescb(ha, scb); 941 } 942 943 /* Now fail all of the pending commands */ 944 DEBUG_VAR(1, "(%s%d) Failing pending commands", 945 ips_name, ha->host_num); 946 947 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 948 scsi_cmd->result = DID_ERROR; 949 scsi_done(scsi_cmd); 950 } 951 952 ha->active = FALSE; 953 return (FAILED); 954 } 955 956 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) { 957 struct scsi_cmnd *scsi_cmd; 958 959 IPS_PRINTK(KERN_NOTICE, ha->pcidev, 960 "Controller reset failed - controller now offline.\n"); 961 962 /* Now fail all of the active commands */ 963 DEBUG_VAR(1, "(%s%d) Failing active commands", 964 ips_name, ha->host_num); 965 966 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 967 scb->scsi_cmd->result = DID_ERROR << 16; 968 scsi_done(scb->scsi_cmd); 969 ips_freescb(ha, scb); 970 } 971 972 /* Now fail all of the pending commands */ 973 DEBUG_VAR(1, "(%s%d) Failing pending commands", 974 ips_name, ha->host_num); 975 976 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) { 977 scsi_cmd->result = DID_ERROR << 16; 978 scsi_done(scsi_cmd); 979 } 980 981 ha->active = FALSE; 982 return (FAILED); 983 } 984 985 /* FFDC */ 986 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) { 987 ha->last_ffdc = ktime_get_real_seconds(); 988 ha->reset_count++; 989 ips_ffdc_reset(ha, IPS_INTR_IORL); 990 } 991 992 /* Now fail all of the active commands */ 993 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num); 994 995 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) { 996 scb->scsi_cmd->result = DID_RESET << 16; 997 scsi_done(scb->scsi_cmd); 998 ips_freescb(ha, scb); 999 } 1000 1001 /* Reset DCDB active command bits */ 1002 for (i = 1; i < ha->nbus; i++) 1003 ha->dcdb_active[i - 1] = 0; 1004 1005 /* Reset the number of active IOCTLs */ 1006 ha->num_ioctl = 0; 1007 1008 ips_next(ha, IPS_INTR_IORL); 1009 1010 return (SUCCESS); 1011 #endif /* NO_IPS_RESET */ 1012 1013 } 1014 1015 static int ips_eh_reset(struct scsi_cmnd *SC) 1016 { 1017 int rc; 1018 1019 spin_lock_irq(SC->device->host->host_lock); 1020 rc = __ips_eh_reset(SC); 1021 spin_unlock_irq(SC->device->host->host_lock); 1022 1023 return rc; 1024 } 1025 1026 /****************************************************************************/ 1027 /* */ 1028 /* Routine Name: ips_queue */ 1029 /* */ 1030 /* Routine Description: */ 1031 /* */ 1032 /* Send a command to the controller */ 1033 /* */ 1034 /* NOTE: */ 1035 /* Linux obtains io_request_lock before calling this function */ 1036 /* */ 1037 /****************************************************************************/ 1038 static int ips_queue_lck(struct scsi_cmnd *SC) 1039 { 1040 void (*done)(struct scsi_cmnd *) = scsi_done; 1041 ips_ha_t *ha; 1042 ips_passthru_t *pt; 1043 1044 METHOD_TRACE("ips_queue", 1); 1045 1046 ha = (ips_ha_t *) SC->device->host->hostdata; 1047 1048 if (!ha) 1049 goto out_error; 1050 1051 if (!ha->active) 1052 goto out_error; 1053 1054 if (ips_is_passthru(SC)) { 1055 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) { 1056 SC->result = DID_BUS_BUSY << 16; 1057 done(SC); 1058 1059 return (0); 1060 } 1061 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) { 1062 SC->result = DID_BUS_BUSY << 16; 1063 done(SC); 1064 1065 return (0); 1066 } 1067 1068 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)", 1069 ips_name, 1070 ha->host_num, 1071 SC->cmnd[0], 1072 SC->device->channel, SC->device->id, SC->device->lun); 1073 1074 /* Check for command to initiator IDs */ 1075 if ((scmd_channel(SC) > 0) 1076 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) { 1077 SC->result = DID_NO_CONNECT << 16; 1078 done(SC); 1079 1080 return (0); 1081 } 1082 1083 if (ips_is_passthru(SC)) { 1084 1085 ips_copp_wait_item_t *scratch; 1086 1087 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */ 1088 /* There can never be any system activity ( network or disk ), but check */ 1089 /* anyway just as a good practice. */ 1090 pt = (ips_passthru_t *) scsi_sglist(SC); 1091 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) && 1092 (pt->CoppCP.cmd.reset.adapter_flag == 1)) { 1093 if (ha->scb_activelist.count != 0) { 1094 SC->result = DID_BUS_BUSY << 16; 1095 done(SC); 1096 return (0); 1097 } 1098 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */ 1099 __ips_eh_reset(SC); 1100 SC->result = DID_OK << 16; 1101 scsi_done(SC); 1102 return (0); 1103 } 1104 1105 /* allocate space for the scribble */ 1106 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC); 1107 1108 if (!scratch) { 1109 SC->result = DID_ERROR << 16; 1110 done(SC); 1111 1112 return (0); 1113 } 1114 1115 scratch->scsi_cmd = SC; 1116 scratch->next = NULL; 1117 1118 ips_putq_copp_tail(&ha->copp_waitlist, scratch); 1119 } else { 1120 ips_putq_wait_tail(&ha->scb_waitlist, SC); 1121 } 1122 1123 ips_next(ha, IPS_INTR_IORL); 1124 1125 return (0); 1126 out_error: 1127 SC->result = DID_ERROR << 16; 1128 done(SC); 1129 1130 return (0); 1131 } 1132 1133 static DEF_SCSI_QCMD(ips_queue) 1134 1135 /****************************************************************************/ 1136 /* */ 1137 /* Routine Name: ips_biosparam */ 1138 /* */ 1139 /* Routine Description: */ 1140 /* */ 1141 /* Set bios geometry for the controller */ 1142 /* */ 1143 /****************************************************************************/ 1144 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev, 1145 sector_t capacity, int geom[]) 1146 { 1147 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata; 1148 int heads; 1149 int sectors; 1150 int cylinders; 1151 1152 METHOD_TRACE("ips_biosparam", 1); 1153 1154 if (!ha) 1155 /* ?!?! host adater info invalid */ 1156 return (0); 1157 1158 if (!ha->active) 1159 return (0); 1160 1161 if (!ips_read_adapter_status(ha, IPS_INTR_ON)) 1162 /* ?!?! Enquiry command failed */ 1163 return (0); 1164 1165 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) { 1166 heads = IPS_NORM_HEADS; 1167 sectors = IPS_NORM_SECTORS; 1168 } else { 1169 heads = IPS_COMP_HEADS; 1170 sectors = IPS_COMP_SECTORS; 1171 } 1172 1173 cylinders = (unsigned long) capacity / (heads * sectors); 1174 1175 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d", 1176 heads, sectors, cylinders); 1177 1178 geom[0] = heads; 1179 geom[1] = sectors; 1180 geom[2] = cylinders; 1181 1182 return (0); 1183 } 1184 1185 /****************************************************************************/ 1186 /* */ 1187 /* Routine Name: ips_slave_configure */ 1188 /* */ 1189 /* Routine Description: */ 1190 /* */ 1191 /* Set queue depths on devices once scan is complete */ 1192 /* */ 1193 /****************************************************************************/ 1194 static int 1195 ips_slave_configure(struct scsi_device * SDptr) 1196 { 1197 ips_ha_t *ha; 1198 int min; 1199 1200 ha = IPS_HA(SDptr->host); 1201 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) { 1202 min = ha->max_cmds / 2; 1203 if (ha->enq->ucLogDriveCount <= 2) 1204 min = ha->max_cmds - 1; 1205 scsi_change_queue_depth(SDptr, min); 1206 } 1207 1208 SDptr->skip_ms_page_8 = 1; 1209 SDptr->skip_ms_page_3f = 1; 1210 return 0; 1211 } 1212 1213 /****************************************************************************/ 1214 /* */ 1215 /* Routine Name: do_ipsintr */ 1216 /* */ 1217 /* Routine Description: */ 1218 /* */ 1219 /* Wrapper for the interrupt handler */ 1220 /* */ 1221 /****************************************************************************/ 1222 static irqreturn_t 1223 do_ipsintr(int irq, void *dev_id) 1224 { 1225 ips_ha_t *ha; 1226 struct Scsi_Host *host; 1227 int irqstatus; 1228 1229 METHOD_TRACE("do_ipsintr", 2); 1230 1231 ha = (ips_ha_t *) dev_id; 1232 if (!ha) 1233 return IRQ_NONE; 1234 host = ips_sh[ha->host_num]; 1235 /* interrupt during initialization */ 1236 if (!host) { 1237 (*ha->func.intr) (ha); 1238 return IRQ_HANDLED; 1239 } 1240 1241 spin_lock(host->host_lock); 1242 1243 if (!ha->active) { 1244 spin_unlock(host->host_lock); 1245 return IRQ_HANDLED; 1246 } 1247 1248 irqstatus = (*ha->func.intr) (ha); 1249 1250 spin_unlock(host->host_lock); 1251 1252 /* start the next command */ 1253 ips_next(ha, IPS_INTR_ON); 1254 return IRQ_RETVAL(irqstatus); 1255 } 1256 1257 /****************************************************************************/ 1258 /* */ 1259 /* Routine Name: ips_intr_copperhead */ 1260 /* */ 1261 /* Routine Description: */ 1262 /* */ 1263 /* Polling interrupt handler */ 1264 /* */ 1265 /* ASSUMES interrupts are disabled */ 1266 /* */ 1267 /****************************************************************************/ 1268 int 1269 ips_intr_copperhead(ips_ha_t * ha) 1270 { 1271 ips_stat_t *sp; 1272 ips_scb_t *scb; 1273 IPS_STATUS cstatus; 1274 int intrstatus; 1275 1276 METHOD_TRACE("ips_intr", 2); 1277 1278 if (!ha) 1279 return 0; 1280 1281 if (!ha->active) 1282 return 0; 1283 1284 intrstatus = (*ha->func.isintr) (ha); 1285 1286 if (!intrstatus) { 1287 /* 1288 * Unexpected/Shared interrupt 1289 */ 1290 1291 return 0; 1292 } 1293 1294 while (TRUE) { 1295 sp = &ha->sp; 1296 1297 intrstatus = (*ha->func.isintr) (ha); 1298 1299 if (!intrstatus) 1300 break; 1301 else 1302 cstatus.value = (*ha->func.statupd) (ha); 1303 1304 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1305 /* Spurious Interrupt ? */ 1306 continue; 1307 } 1308 1309 ips_chkstatus(ha, &cstatus); 1310 scb = (ips_scb_t *) sp->scb_addr; 1311 1312 /* 1313 * use the callback function to finish things up 1314 * NOTE: interrupts are OFF for this 1315 */ 1316 (*scb->callback) (ha, scb); 1317 } /* end while */ 1318 return 1; 1319 } 1320 1321 /****************************************************************************/ 1322 /* */ 1323 /* Routine Name: ips_intr_morpheus */ 1324 /* */ 1325 /* Routine Description: */ 1326 /* */ 1327 /* Polling interrupt handler */ 1328 /* */ 1329 /* ASSUMES interrupts are disabled */ 1330 /* */ 1331 /****************************************************************************/ 1332 int 1333 ips_intr_morpheus(ips_ha_t * ha) 1334 { 1335 ips_stat_t *sp; 1336 ips_scb_t *scb; 1337 IPS_STATUS cstatus; 1338 int intrstatus; 1339 1340 METHOD_TRACE("ips_intr_morpheus", 2); 1341 1342 if (!ha) 1343 return 0; 1344 1345 if (!ha->active) 1346 return 0; 1347 1348 intrstatus = (*ha->func.isintr) (ha); 1349 1350 if (!intrstatus) { 1351 /* 1352 * Unexpected/Shared interrupt 1353 */ 1354 1355 return 0; 1356 } 1357 1358 while (TRUE) { 1359 sp = &ha->sp; 1360 1361 intrstatus = (*ha->func.isintr) (ha); 1362 1363 if (!intrstatus) 1364 break; 1365 else 1366 cstatus.value = (*ha->func.statupd) (ha); 1367 1368 if (cstatus.value == 0xffffffff) 1369 /* No more to process */ 1370 break; 1371 1372 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) { 1373 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1374 "Spurious interrupt; no ccb.\n"); 1375 1376 continue; 1377 } 1378 1379 ips_chkstatus(ha, &cstatus); 1380 scb = (ips_scb_t *) sp->scb_addr; 1381 1382 /* 1383 * use the callback function to finish things up 1384 * NOTE: interrupts are OFF for this 1385 */ 1386 (*scb->callback) (ha, scb); 1387 } /* end while */ 1388 return 1; 1389 } 1390 1391 /****************************************************************************/ 1392 /* */ 1393 /* Routine Name: ips_info */ 1394 /* */ 1395 /* Routine Description: */ 1396 /* */ 1397 /* Return info about the driver */ 1398 /* */ 1399 /****************************************************************************/ 1400 static const char * 1401 ips_info(struct Scsi_Host *SH) 1402 { 1403 static char buffer[256]; 1404 char *bp; 1405 ips_ha_t *ha; 1406 1407 METHOD_TRACE("ips_info", 1); 1408 1409 ha = IPS_HA(SH); 1410 1411 if (!ha) 1412 return (NULL); 1413 1414 bp = &buffer[0]; 1415 memset(bp, 0, sizeof (buffer)); 1416 1417 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ", 1418 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT); 1419 1420 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) { 1421 strcat(bp, " <"); 1422 strcat(bp, ips_adapter_name[ha->ad_type - 1]); 1423 strcat(bp, ">"); 1424 } 1425 1426 return (bp); 1427 } 1428 1429 static int 1430 ips_write_info(struct Scsi_Host *host, char *buffer, int length) 1431 { 1432 int i; 1433 ips_ha_t *ha = NULL; 1434 1435 /* Find our host structure */ 1436 for (i = 0; i < ips_next_controller; i++) { 1437 if (ips_sh[i]) { 1438 if (ips_sh[i] == host) { 1439 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1440 break; 1441 } 1442 } 1443 } 1444 1445 if (!ha) 1446 return (-EINVAL); 1447 1448 return 0; 1449 } 1450 1451 static int 1452 ips_show_info(struct seq_file *m, struct Scsi_Host *host) 1453 { 1454 int i; 1455 ips_ha_t *ha = NULL; 1456 1457 /* Find our host structure */ 1458 for (i = 0; i < ips_next_controller; i++) { 1459 if (ips_sh[i]) { 1460 if (ips_sh[i] == host) { 1461 ha = (ips_ha_t *) ips_sh[i]->hostdata; 1462 break; 1463 } 1464 } 1465 } 1466 1467 if (!ha) 1468 return (-EINVAL); 1469 1470 return ips_host_info(ha, m); 1471 } 1472 1473 /*--------------------------------------------------------------------------*/ 1474 /* Helper Functions */ 1475 /*--------------------------------------------------------------------------*/ 1476 1477 /****************************************************************************/ 1478 /* */ 1479 /* Routine Name: ips_is_passthru */ 1480 /* */ 1481 /* Routine Description: */ 1482 /* */ 1483 /* Determine if the specified SCSI command is really a passthru command */ 1484 /* */ 1485 /****************************************************************************/ 1486 static int ips_is_passthru(struct scsi_cmnd *SC) 1487 { 1488 unsigned long flags; 1489 1490 METHOD_TRACE("ips_is_passthru", 1); 1491 1492 if (!SC) 1493 return (0); 1494 1495 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) && 1496 (SC->device->channel == 0) && 1497 (SC->device->id == IPS_ADAPTER_ID) && 1498 (SC->device->lun == 0) && scsi_sglist(SC)) { 1499 struct scatterlist *sg = scsi_sglist(SC); 1500 char *buffer; 1501 1502 /* kmap_atomic() ensures addressability of the user buffer.*/ 1503 /* local_irq_save() protects the KM_IRQ0 address slot. */ 1504 local_irq_save(flags); 1505 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 1506 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' && 1507 buffer[2] == 'P' && buffer[3] == 'P') { 1508 kunmap_atomic(buffer - sg->offset); 1509 local_irq_restore(flags); 1510 return 1; 1511 } 1512 kunmap_atomic(buffer - sg->offset); 1513 local_irq_restore(flags); 1514 } 1515 return 0; 1516 } 1517 1518 /****************************************************************************/ 1519 /* */ 1520 /* Routine Name: ips_alloc_passthru_buffer */ 1521 /* */ 1522 /* Routine Description: */ 1523 /* allocate a buffer large enough for the ioctl data if the ioctl buffer */ 1524 /* is too small or doesn't exist */ 1525 /****************************************************************************/ 1526 static int 1527 ips_alloc_passthru_buffer(ips_ha_t * ha, int length) 1528 { 1529 void *bigger_buf; 1530 dma_addr_t dma_busaddr; 1531 1532 if (ha->ioctl_data && length <= ha->ioctl_len) 1533 return 0; 1534 /* there is no buffer or it's not big enough, allocate a new one */ 1535 bigger_buf = dma_alloc_coherent(&ha->pcidev->dev, length, &dma_busaddr, 1536 GFP_KERNEL); 1537 if (bigger_buf) { 1538 /* free the old memory */ 1539 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len, 1540 ha->ioctl_data, ha->ioctl_busaddr); 1541 /* use the new memory */ 1542 ha->ioctl_data = (char *) bigger_buf; 1543 ha->ioctl_len = length; 1544 ha->ioctl_busaddr = dma_busaddr; 1545 } else { 1546 return -1; 1547 } 1548 return 0; 1549 } 1550 1551 /****************************************************************************/ 1552 /* */ 1553 /* Routine Name: ips_make_passthru */ 1554 /* */ 1555 /* Routine Description: */ 1556 /* */ 1557 /* Make a passthru command out of the info in the Scsi block */ 1558 /* */ 1559 /****************************************************************************/ 1560 static int 1561 ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr) 1562 { 1563 ips_passthru_t *pt; 1564 int length = 0; 1565 int i, ret; 1566 struct scatterlist *sg = scsi_sglist(SC); 1567 1568 METHOD_TRACE("ips_make_passthru", 1); 1569 1570 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i) 1571 length += sg->length; 1572 1573 if (length < sizeof (ips_passthru_t)) { 1574 /* wrong size */ 1575 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size", 1576 ips_name, ha->host_num); 1577 return (IPS_FAILURE); 1578 } 1579 if (ips_alloc_passthru_buffer(ha, length)) { 1580 /* allocation failure! If ha->ioctl_data exists, use it to return 1581 some error codes. Return a failed command to the scsi layer. */ 1582 if (ha->ioctl_data) { 1583 pt = (ips_passthru_t *) ha->ioctl_data; 1584 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t)); 1585 pt->BasicStatus = 0x0B; 1586 pt->ExtendedStatus = 0x00; 1587 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t)); 1588 } 1589 return IPS_FAILURE; 1590 } 1591 ha->ioctl_datasize = length; 1592 1593 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize); 1594 pt = (ips_passthru_t *) ha->ioctl_data; 1595 1596 /* 1597 * Some notes about the passthru interface used 1598 * 1599 * IF the scsi op_code == 0x0d then we assume 1600 * that the data came along with/goes with the 1601 * packet we received from the sg driver. In this 1602 * case the CmdBSize field of the pt structure is 1603 * used for the size of the buffer. 1604 */ 1605 1606 switch (pt->CoppCmd) { 1607 case IPS_NUMCTRLS: 1608 memcpy(ha->ioctl_data + sizeof (ips_passthru_t), 1609 &ips_num_controllers, sizeof (int)); 1610 ips_scmd_buf_write(SC, ha->ioctl_data, 1611 sizeof (ips_passthru_t) + sizeof (int)); 1612 SC->result = DID_OK << 16; 1613 1614 return (IPS_SUCCESS_IMM); 1615 1616 case IPS_COPPUSRCMD: 1617 case IPS_COPPIOCCMD: 1618 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) { 1619 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) { 1620 /* wrong size */ 1621 DEBUG_VAR(1, 1622 "(%s%d) Passthru structure wrong size", 1623 ips_name, ha->host_num); 1624 1625 return (IPS_FAILURE); 1626 } 1627 1628 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && 1629 pt->CoppCP.cmd.flashfw.op_code == 1630 IPS_CMD_RW_BIOSFW) { 1631 ret = ips_flash_copperhead(ha, pt, scb); 1632 ips_scmd_buf_write(SC, ha->ioctl_data, 1633 sizeof (ips_passthru_t)); 1634 return ret; 1635 } 1636 if (ips_usrcmd(ha, pt, scb)) 1637 return (IPS_SUCCESS); 1638 else 1639 return (IPS_FAILURE); 1640 } 1641 1642 break; 1643 1644 } /* end switch */ 1645 1646 return (IPS_FAILURE); 1647 } 1648 1649 /****************************************************************************/ 1650 /* Routine Name: ips_flash_copperhead */ 1651 /* Routine Description: */ 1652 /* Flash the BIOS/FW on a Copperhead style controller */ 1653 /****************************************************************************/ 1654 static int 1655 ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1656 { 1657 int datasize; 1658 1659 /* Trombone is the only copperhead that can do packet flash, but only 1660 * for firmware. No one said it had to make sense. */ 1661 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) { 1662 if (ips_usrcmd(ha, pt, scb)) 1663 return IPS_SUCCESS; 1664 else 1665 return IPS_FAILURE; 1666 } 1667 pt->BasicStatus = 0x0B; 1668 pt->ExtendedStatus = 0; 1669 scb->scsi_cmd->result = DID_OK << 16; 1670 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */ 1671 /* avoid allocating a huge buffer per adapter ( which can fail ). */ 1672 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1673 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1674 pt->BasicStatus = 0; 1675 return ips_flash_bios(ha, pt, scb); 1676 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) { 1677 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){ 1678 ha->flash_data = ips_FlashData; 1679 ha->flash_busaddr = ips_flashbusaddr; 1680 ha->flash_len = PAGE_SIZE << 7; 1681 ha->flash_datasize = 0; 1682 } else if (!ha->flash_data) { 1683 datasize = pt->CoppCP.cmd.flashfw.total_packets * 1684 pt->CoppCP.cmd.flashfw.count; 1685 ha->flash_data = dma_alloc_coherent(&ha->pcidev->dev, 1686 datasize, &ha->flash_busaddr, GFP_KERNEL); 1687 if (!ha->flash_data){ 1688 printk(KERN_WARNING "Unable to allocate a flash buffer\n"); 1689 return IPS_FAILURE; 1690 } 1691 ha->flash_datasize = 0; 1692 ha->flash_len = datasize; 1693 } else 1694 return IPS_FAILURE; 1695 } else { 1696 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize > 1697 ha->flash_len) { 1698 ips_free_flash_copperhead(ha); 1699 IPS_PRINTK(KERN_WARNING, ha->pcidev, 1700 "failed size sanity check\n"); 1701 return IPS_FAILURE; 1702 } 1703 } 1704 if (!ha->flash_data) 1705 return IPS_FAILURE; 1706 pt->BasicStatus = 0; 1707 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1, 1708 pt->CoppCP.cmd.flashfw.count); 1709 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count; 1710 if (pt->CoppCP.cmd.flashfw.packet_num == 1711 pt->CoppCP.cmd.flashfw.total_packets - 1) { 1712 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE) 1713 return ips_flash_bios(ha, pt, scb); 1714 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) 1715 return ips_flash_firmware(ha, pt, scb); 1716 } 1717 return IPS_SUCCESS_IMM; 1718 } 1719 1720 /****************************************************************************/ 1721 /* Routine Name: ips_flash_bios */ 1722 /* Routine Description: */ 1723 /* flashes the bios of a copperhead adapter */ 1724 /****************************************************************************/ 1725 static int 1726 ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1727 { 1728 1729 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1730 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) { 1731 if ((!ha->func.programbios) || (!ha->func.erasebios) || 1732 (!ha->func.verifybios)) 1733 goto error; 1734 if ((*ha->func.erasebios) (ha)) { 1735 DEBUG_VAR(1, 1736 "(%s%d) flash bios failed - unable to erase flash", 1737 ips_name, ha->host_num); 1738 goto error; 1739 } else 1740 if ((*ha->func.programbios) (ha, 1741 ha->flash_data + 1742 IPS_BIOS_HEADER, 1743 ha->flash_datasize - 1744 IPS_BIOS_HEADER, 0)) { 1745 DEBUG_VAR(1, 1746 "(%s%d) flash bios failed - unable to flash", 1747 ips_name, ha->host_num); 1748 goto error; 1749 } else 1750 if ((*ha->func.verifybios) (ha, 1751 ha->flash_data + 1752 IPS_BIOS_HEADER, 1753 ha->flash_datasize - 1754 IPS_BIOS_HEADER, 0)) { 1755 DEBUG_VAR(1, 1756 "(%s%d) flash bios failed - unable to verify flash", 1757 ips_name, ha->host_num); 1758 goto error; 1759 } 1760 ips_free_flash_copperhead(ha); 1761 return IPS_SUCCESS_IMM; 1762 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE && 1763 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) { 1764 if (!ha->func.erasebios) 1765 goto error; 1766 if ((*ha->func.erasebios) (ha)) { 1767 DEBUG_VAR(1, 1768 "(%s%d) flash bios failed - unable to erase flash", 1769 ips_name, ha->host_num); 1770 goto error; 1771 } 1772 return IPS_SUCCESS_IMM; 1773 } 1774 error: 1775 pt->BasicStatus = 0x0B; 1776 pt->ExtendedStatus = 0x00; 1777 ips_free_flash_copperhead(ha); 1778 return IPS_FAILURE; 1779 } 1780 1781 /****************************************************************************/ 1782 /* */ 1783 /* Routine Name: ips_fill_scb_sg_single */ 1784 /* */ 1785 /* Routine Description: */ 1786 /* Fill in a single scb sg_list element from an address */ 1787 /* return a -1 if a breakup occurred */ 1788 /****************************************************************************/ 1789 static int 1790 ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr, 1791 ips_scb_t * scb, int indx, unsigned int e_len) 1792 { 1793 1794 int ret_val = 0; 1795 1796 if ((scb->data_len + e_len) > ha->max_xfer) { 1797 e_len = ha->max_xfer - scb->data_len; 1798 scb->breakup = indx; 1799 ++scb->sg_break; 1800 ret_val = -1; 1801 } else { 1802 scb->breakup = 0; 1803 scb->sg_break = 0; 1804 } 1805 if (IPS_USE_ENH_SGLIST(ha)) { 1806 scb->sg_list.enh_list[indx].address_lo = 1807 cpu_to_le32(lower_32_bits(busaddr)); 1808 scb->sg_list.enh_list[indx].address_hi = 1809 cpu_to_le32(upper_32_bits(busaddr)); 1810 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len); 1811 } else { 1812 scb->sg_list.std_list[indx].address = 1813 cpu_to_le32(lower_32_bits(busaddr)); 1814 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len); 1815 } 1816 1817 ++scb->sg_len; 1818 scb->data_len += e_len; 1819 return ret_val; 1820 } 1821 1822 /****************************************************************************/ 1823 /* Routine Name: ips_flash_firmware */ 1824 /* Routine Description: */ 1825 /* flashes the firmware of a copperhead adapter */ 1826 /****************************************************************************/ 1827 static int 1828 ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1829 { 1830 IPS_SG_LIST sg_list; 1831 uint32_t cmd_busaddr; 1832 1833 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE && 1834 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) { 1835 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND)); 1836 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD; 1837 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize); 1838 } else { 1839 pt->BasicStatus = 0x0B; 1840 pt->ExtendedStatus = 0x00; 1841 ips_free_flash_copperhead(ha); 1842 return IPS_FAILURE; 1843 } 1844 /* Save the S/G list pointer so it doesn't get clobbered */ 1845 sg_list.list = scb->sg_list.list; 1846 cmd_busaddr = scb->scb_busaddr; 1847 /* copy in the CP */ 1848 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1849 /* FIX stuff that might be wrong */ 1850 scb->sg_list.list = sg_list.list; 1851 scb->scb_busaddr = cmd_busaddr; 1852 scb->bus = scb->scsi_cmd->device->channel; 1853 scb->target_id = scb->scsi_cmd->device->id; 1854 scb->lun = scb->scsi_cmd->device->lun; 1855 scb->sg_len = 0; 1856 scb->data_len = 0; 1857 scb->flags = 0; 1858 scb->op_code = 0; 1859 scb->callback = ipsintr_done; 1860 scb->timeout = ips_cmd_timeout; 1861 1862 scb->data_len = ha->flash_datasize; 1863 scb->data_busaddr = 1864 dma_map_single(&ha->pcidev->dev, ha->flash_data, scb->data_len, 1865 IPS_DMA_DIR(scb)); 1866 scb->flags |= IPS_SCB_MAP_SINGLE; 1867 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 1868 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr); 1869 if (pt->TimeOut) 1870 scb->timeout = pt->TimeOut; 1871 scb->scsi_cmd->result = DID_OK << 16; 1872 return IPS_SUCCESS; 1873 } 1874 1875 /****************************************************************************/ 1876 /* Routine Name: ips_free_flash_copperhead */ 1877 /* Routine Description: */ 1878 /* release the memory resources used to hold the flash image */ 1879 /****************************************************************************/ 1880 static void 1881 ips_free_flash_copperhead(ips_ha_t * ha) 1882 { 1883 if (ha->flash_data == ips_FlashData) 1884 test_and_clear_bit(0, &ips_FlashDataInUse); 1885 else if (ha->flash_data) 1886 dma_free_coherent(&ha->pcidev->dev, ha->flash_len, 1887 ha->flash_data, ha->flash_busaddr); 1888 ha->flash_data = NULL; 1889 } 1890 1891 /****************************************************************************/ 1892 /* */ 1893 /* Routine Name: ips_usrcmd */ 1894 /* */ 1895 /* Routine Description: */ 1896 /* */ 1897 /* Process a user command and make it ready to send */ 1898 /* */ 1899 /****************************************************************************/ 1900 static int 1901 ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb) 1902 { 1903 IPS_SG_LIST sg_list; 1904 uint32_t cmd_busaddr; 1905 1906 METHOD_TRACE("ips_usrcmd", 1); 1907 1908 if ((!scb) || (!pt) || (!ha)) 1909 return (0); 1910 1911 /* Save the S/G list pointer so it doesn't get clobbered */ 1912 sg_list.list = scb->sg_list.list; 1913 cmd_busaddr = scb->scb_busaddr; 1914 /* copy in the CP */ 1915 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD)); 1916 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE)); 1917 1918 /* FIX stuff that might be wrong */ 1919 scb->sg_list.list = sg_list.list; 1920 scb->scb_busaddr = cmd_busaddr; 1921 scb->bus = scb->scsi_cmd->device->channel; 1922 scb->target_id = scb->scsi_cmd->device->id; 1923 scb->lun = scb->scsi_cmd->device->lun; 1924 scb->sg_len = 0; 1925 scb->data_len = 0; 1926 scb->flags = 0; 1927 scb->op_code = 0; 1928 scb->callback = ipsintr_done; 1929 scb->timeout = ips_cmd_timeout; 1930 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 1931 1932 /* we don't support DCDB/READ/WRITE Scatter Gather */ 1933 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) || 1934 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) || 1935 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG)) 1936 return (0); 1937 1938 if (pt->CmdBSize) { 1939 scb->data_len = pt->CmdBSize; 1940 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t); 1941 } else { 1942 scb->data_busaddr = 0L; 1943 } 1944 1945 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 1946 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 1947 (unsigned long) &scb-> 1948 dcdb - 1949 (unsigned long) scb); 1950 1951 if (pt->CmdBSize) { 1952 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) 1953 scb->dcdb.buffer_pointer = 1954 cpu_to_le32(scb->data_busaddr); 1955 else 1956 scb->cmd.basic_io.sg_addr = 1957 cpu_to_le32(scb->data_busaddr); 1958 } 1959 1960 /* set timeouts */ 1961 if (pt->TimeOut) { 1962 scb->timeout = pt->TimeOut; 1963 1964 if (pt->TimeOut <= 10) 1965 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; 1966 else if (pt->TimeOut <= 60) 1967 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; 1968 else 1969 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; 1970 } 1971 1972 /* assume success */ 1973 scb->scsi_cmd->result = DID_OK << 16; 1974 1975 /* success */ 1976 return (1); 1977 } 1978 1979 /****************************************************************************/ 1980 /* */ 1981 /* Routine Name: ips_cleanup_passthru */ 1982 /* */ 1983 /* Routine Description: */ 1984 /* */ 1985 /* Cleanup after a passthru command */ 1986 /* */ 1987 /****************************************************************************/ 1988 static void 1989 ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb) 1990 { 1991 ips_passthru_t *pt; 1992 1993 METHOD_TRACE("ips_cleanup_passthru", 1); 1994 1995 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) { 1996 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru", 1997 ips_name, ha->host_num); 1998 1999 return; 2000 } 2001 pt = (ips_passthru_t *) ha->ioctl_data; 2002 2003 /* Copy data back to the user */ 2004 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */ 2005 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE)); 2006 2007 pt->BasicStatus = scb->basic_status; 2008 pt->ExtendedStatus = scb->extended_status; 2009 pt->AdapterType = ha->ad_type; 2010 2011 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD && 2012 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD || 2013 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW)) 2014 ips_free_flash_copperhead(ha); 2015 2016 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize); 2017 } 2018 2019 /****************************************************************************/ 2020 /* */ 2021 /* Routine Name: ips_host_info */ 2022 /* */ 2023 /* Routine Description: */ 2024 /* */ 2025 /* The passthru interface for the driver */ 2026 /* */ 2027 /****************************************************************************/ 2028 static int 2029 ips_host_info(ips_ha_t *ha, struct seq_file *m) 2030 { 2031 METHOD_TRACE("ips_host_info", 1); 2032 2033 seq_puts(m, "\nIBM ServeRAID General Information:\n\n"); 2034 2035 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) && 2036 (le16_to_cpu(ha->nvram->adapter_type) != 0)) 2037 seq_printf(m, "\tController Type : %s\n", 2038 ips_adapter_name[ha->ad_type - 1]); 2039 else 2040 seq_puts(m, "\tController Type : Unknown\n"); 2041 2042 if (ha->io_addr) 2043 seq_printf(m, 2044 "\tIO region : 0x%x (%d bytes)\n", 2045 ha->io_addr, ha->io_len); 2046 2047 if (ha->mem_addr) { 2048 seq_printf(m, 2049 "\tMemory region : 0x%x (%d bytes)\n", 2050 ha->mem_addr, ha->mem_len); 2051 seq_printf(m, 2052 "\tShared memory address : 0x%lx\n", 2053 (unsigned long)ha->mem_ptr); 2054 } 2055 2056 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq); 2057 2058 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */ 2059 /* That keeps everything happy for "text" operations on the proc file. */ 2060 2061 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) { 2062 if (ha->nvram->bios_low[3] == 0) { 2063 seq_printf(m, 2064 "\tBIOS Version : %c%c%c%c%c%c%c\n", 2065 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2066 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2067 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2068 ha->nvram->bios_low[2]); 2069 2070 } else { 2071 seq_printf(m, 2072 "\tBIOS Version : %c%c%c%c%c%c%c%c\n", 2073 ha->nvram->bios_high[0], ha->nvram->bios_high[1], 2074 ha->nvram->bios_high[2], ha->nvram->bios_high[3], 2075 ha->nvram->bios_low[0], ha->nvram->bios_low[1], 2076 ha->nvram->bios_low[2], ha->nvram->bios_low[3]); 2077 } 2078 2079 } 2080 2081 if (ha->enq->CodeBlkVersion[7] == 0) { 2082 seq_printf(m, 2083 "\tFirmware Version : %c%c%c%c%c%c%c\n", 2084 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2085 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2086 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2087 ha->enq->CodeBlkVersion[6]); 2088 } else { 2089 seq_printf(m, 2090 "\tFirmware Version : %c%c%c%c%c%c%c%c\n", 2091 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1], 2092 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3], 2093 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5], 2094 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]); 2095 } 2096 2097 if (ha->enq->BootBlkVersion[7] == 0) { 2098 seq_printf(m, 2099 "\tBoot Block Version : %c%c%c%c%c%c%c\n", 2100 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2101 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2102 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2103 ha->enq->BootBlkVersion[6]); 2104 } else { 2105 seq_printf(m, 2106 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n", 2107 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1], 2108 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3], 2109 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5], 2110 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]); 2111 } 2112 2113 seq_printf(m, "\tDriver Version : %s%s\n", 2114 IPS_VERSION_HIGH, IPS_VERSION_LOW); 2115 2116 seq_printf(m, "\tDriver Build : %d\n", 2117 IPS_BUILD_IDENT); 2118 2119 seq_printf(m, "\tMax Physical Devices : %d\n", 2120 ha->enq->ucMaxPhysicalDevices); 2121 seq_printf(m, "\tMax Active Commands : %d\n", 2122 ha->max_cmds); 2123 seq_printf(m, "\tCurrent Queued Commands : %d\n", 2124 ha->scb_waitlist.count); 2125 seq_printf(m, "\tCurrent Active Commands : %d\n", 2126 ha->scb_activelist.count - ha->num_ioctl); 2127 seq_printf(m, "\tCurrent Queued PT Commands : %d\n", 2128 ha->copp_waitlist.count); 2129 seq_printf(m, "\tCurrent Active PT Commands : %d\n", 2130 ha->num_ioctl); 2131 2132 seq_putc(m, '\n'); 2133 2134 return 0; 2135 } 2136 2137 /****************************************************************************/ 2138 /* */ 2139 /* Routine Name: ips_identify_controller */ 2140 /* */ 2141 /* Routine Description: */ 2142 /* */ 2143 /* Identify this controller */ 2144 /* */ 2145 /****************************************************************************/ 2146 static void 2147 ips_identify_controller(ips_ha_t * ha) 2148 { 2149 METHOD_TRACE("ips_identify_controller", 1); 2150 2151 switch (ha->pcidev->device) { 2152 case IPS_DEVICEID_COPPERHEAD: 2153 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) { 2154 ha->ad_type = IPS_ADTYPE_SERVERAID; 2155 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) { 2156 ha->ad_type = IPS_ADTYPE_SERVERAID2; 2157 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) { 2158 ha->ad_type = IPS_ADTYPE_NAVAJO; 2159 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2) 2160 && (ha->slot_num == 0)) { 2161 ha->ad_type = IPS_ADTYPE_KIOWA; 2162 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) && 2163 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) { 2164 if (ha->enq->ucMaxPhysicalDevices == 15) 2165 ha->ad_type = IPS_ADTYPE_SERVERAID3L; 2166 else 2167 ha->ad_type = IPS_ADTYPE_SERVERAID3; 2168 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) && 2169 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) { 2170 ha->ad_type = IPS_ADTYPE_SERVERAID4H; 2171 } 2172 break; 2173 2174 case IPS_DEVICEID_MORPHEUS: 2175 switch (ha->pcidev->subsystem_device) { 2176 case IPS_SUBDEVICEID_4L: 2177 ha->ad_type = IPS_ADTYPE_SERVERAID4L; 2178 break; 2179 2180 case IPS_SUBDEVICEID_4M: 2181 ha->ad_type = IPS_ADTYPE_SERVERAID4M; 2182 break; 2183 2184 case IPS_SUBDEVICEID_4MX: 2185 ha->ad_type = IPS_ADTYPE_SERVERAID4MX; 2186 break; 2187 2188 case IPS_SUBDEVICEID_4LX: 2189 ha->ad_type = IPS_ADTYPE_SERVERAID4LX; 2190 break; 2191 2192 case IPS_SUBDEVICEID_5I2: 2193 ha->ad_type = IPS_ADTYPE_SERVERAID5I2; 2194 break; 2195 2196 case IPS_SUBDEVICEID_5I1: 2197 ha->ad_type = IPS_ADTYPE_SERVERAID5I1; 2198 break; 2199 } 2200 2201 break; 2202 2203 case IPS_DEVICEID_MARCO: 2204 switch (ha->pcidev->subsystem_device) { 2205 case IPS_SUBDEVICEID_6M: 2206 ha->ad_type = IPS_ADTYPE_SERVERAID6M; 2207 break; 2208 case IPS_SUBDEVICEID_6I: 2209 ha->ad_type = IPS_ADTYPE_SERVERAID6I; 2210 break; 2211 case IPS_SUBDEVICEID_7k: 2212 ha->ad_type = IPS_ADTYPE_SERVERAID7k; 2213 break; 2214 case IPS_SUBDEVICEID_7M: 2215 ha->ad_type = IPS_ADTYPE_SERVERAID7M; 2216 break; 2217 } 2218 break; 2219 } 2220 } 2221 2222 /****************************************************************************/ 2223 /* */ 2224 /* Routine Name: ips_get_bios_version */ 2225 /* */ 2226 /* Routine Description: */ 2227 /* */ 2228 /* Get the BIOS revision number */ 2229 /* */ 2230 /****************************************************************************/ 2231 static void 2232 ips_get_bios_version(ips_ha_t * ha, int intr) 2233 { 2234 ips_scb_t *scb; 2235 int ret; 2236 uint8_t major; 2237 uint8_t minor; 2238 uint8_t subminor; 2239 uint8_t *buffer; 2240 2241 METHOD_TRACE("ips_get_bios_version", 1); 2242 2243 major = 0; 2244 minor = 0; 2245 2246 memcpy(ha->bios_version, " ?", 8); 2247 2248 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) { 2249 if (IPS_USE_MEMIO(ha)) { 2250 /* Memory Mapped I/O */ 2251 2252 /* test 1st byte */ 2253 writel(0, ha->mem_ptr + IPS_REG_FLAP); 2254 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2255 udelay(25); /* 25 us */ 2256 2257 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 2258 return; 2259 2260 writel(1, ha->mem_ptr + IPS_REG_FLAP); 2261 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2262 udelay(25); /* 25 us */ 2263 2264 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 2265 return; 2266 2267 /* Get Major version */ 2268 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP); 2269 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2270 udelay(25); /* 25 us */ 2271 2272 major = readb(ha->mem_ptr + IPS_REG_FLDP); 2273 2274 /* Get Minor version */ 2275 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP); 2276 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2277 udelay(25); /* 25 us */ 2278 minor = readb(ha->mem_ptr + IPS_REG_FLDP); 2279 2280 /* Get SubMinor version */ 2281 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP); 2282 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2283 udelay(25); /* 25 us */ 2284 subminor = readb(ha->mem_ptr + IPS_REG_FLDP); 2285 2286 } else { 2287 /* Programmed I/O */ 2288 2289 /* test 1st byte */ 2290 outl(0, ha->io_addr + IPS_REG_FLAP); 2291 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2292 udelay(25); /* 25 us */ 2293 2294 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 2295 return; 2296 2297 outl(1, ha->io_addr + IPS_REG_FLAP); 2298 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2299 udelay(25); /* 25 us */ 2300 2301 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 2302 return; 2303 2304 /* Get Major version */ 2305 outl(0x1FF, ha->io_addr + IPS_REG_FLAP); 2306 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2307 udelay(25); /* 25 us */ 2308 2309 major = inb(ha->io_addr + IPS_REG_FLDP); 2310 2311 /* Get Minor version */ 2312 outl(0x1FE, ha->io_addr + IPS_REG_FLAP); 2313 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2314 udelay(25); /* 25 us */ 2315 2316 minor = inb(ha->io_addr + IPS_REG_FLDP); 2317 2318 /* Get SubMinor version */ 2319 outl(0x1FD, ha->io_addr + IPS_REG_FLAP); 2320 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 2321 udelay(25); /* 25 us */ 2322 2323 subminor = inb(ha->io_addr + IPS_REG_FLDP); 2324 2325 } 2326 } else { 2327 /* Morpheus Family - Send Command to the card */ 2328 2329 buffer = ha->ioctl_data; 2330 2331 memset(buffer, 0, 0x1000); 2332 2333 scb = &ha->scbs[ha->max_cmds - 1]; 2334 2335 ips_init_scb(ha, scb); 2336 2337 scb->timeout = ips_cmd_timeout; 2338 scb->cdb[0] = IPS_CMD_RW_BIOSFW; 2339 2340 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW; 2341 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb); 2342 scb->cmd.flashfw.type = 1; 2343 scb->cmd.flashfw.direction = 0; 2344 scb->cmd.flashfw.count = cpu_to_le32(0x800); 2345 scb->cmd.flashfw.total_packets = 1; 2346 scb->cmd.flashfw.packet_num = 0; 2347 scb->data_len = 0x1000; 2348 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr; 2349 2350 /* issue the command */ 2351 if (((ret = 2352 ips_send_wait(ha, scb, ips_cmd_timeout, 2353 intr)) == IPS_FAILURE) 2354 || (ret == IPS_SUCCESS_IMM) 2355 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 2356 /* Error occurred */ 2357 2358 return; 2359 } 2360 2361 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) { 2362 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */ 2363 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */ 2364 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */ 2365 } else { 2366 return; 2367 } 2368 } 2369 2370 ha->bios_version[0] = hex_asc_upper_hi(major); 2371 ha->bios_version[1] = '.'; 2372 ha->bios_version[2] = hex_asc_upper_lo(major); 2373 ha->bios_version[3] = hex_asc_upper_lo(subminor); 2374 ha->bios_version[4] = '.'; 2375 ha->bios_version[5] = hex_asc_upper_hi(minor); 2376 ha->bios_version[6] = hex_asc_upper_lo(minor); 2377 ha->bios_version[7] = 0; 2378 } 2379 2380 /****************************************************************************/ 2381 /* */ 2382 /* Routine Name: ips_hainit */ 2383 /* */ 2384 /* Routine Description: */ 2385 /* */ 2386 /* Initialize the controller */ 2387 /* */ 2388 /* NOTE: Assumes to be called from with a lock */ 2389 /* */ 2390 /****************************************************************************/ 2391 static int 2392 ips_hainit(ips_ha_t * ha) 2393 { 2394 int i; 2395 2396 METHOD_TRACE("ips_hainit", 1); 2397 2398 if (!ha) 2399 return (0); 2400 2401 if (ha->func.statinit) 2402 (*ha->func.statinit) (ha); 2403 2404 if (ha->func.enableint) 2405 (*ha->func.enableint) (ha); 2406 2407 /* Send FFDC */ 2408 ha->reset_count = 1; 2409 ha->last_ffdc = ktime_get_real_seconds(); 2410 ips_ffdc_reset(ha, IPS_INTR_IORL); 2411 2412 if (!ips_read_config(ha, IPS_INTR_IORL)) { 2413 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2414 "unable to read config from controller.\n"); 2415 2416 return (0); 2417 } 2418 /* end if */ 2419 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) { 2420 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2421 "unable to read controller status.\n"); 2422 2423 return (0); 2424 } 2425 2426 /* Identify this controller */ 2427 ips_identify_controller(ha); 2428 2429 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) { 2430 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2431 "unable to read subsystem parameters.\n"); 2432 2433 return (0); 2434 } 2435 2436 /* write nvram user page 5 */ 2437 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) { 2438 IPS_PRINTK(KERN_WARNING, ha->pcidev, 2439 "unable to write driver info to controller.\n"); 2440 2441 return (0); 2442 } 2443 2444 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */ 2445 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1)) 2446 ips_clear_adapter(ha, IPS_INTR_IORL); 2447 2448 /* set limits on SID, LUN, BUS */ 2449 ha->ntargets = IPS_MAX_TARGETS + 1; 2450 ha->nlun = 1; 2451 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1; 2452 2453 switch (ha->conf->logical_drive[0].ucStripeSize) { 2454 case 4: 2455 ha->max_xfer = 0x10000; 2456 break; 2457 2458 case 5: 2459 ha->max_xfer = 0x20000; 2460 break; 2461 2462 case 6: 2463 ha->max_xfer = 0x40000; 2464 break; 2465 2466 case 7: 2467 default: 2468 ha->max_xfer = 0x80000; 2469 break; 2470 } 2471 2472 /* setup max concurrent commands */ 2473 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) { 2474 /* Use the new method */ 2475 ha->max_cmds = ha->enq->ucConcurrentCmdCount; 2476 } else { 2477 /* use the old method */ 2478 switch (ha->conf->logical_drive[0].ucStripeSize) { 2479 case 4: 2480 ha->max_cmds = 32; 2481 break; 2482 2483 case 5: 2484 ha->max_cmds = 16; 2485 break; 2486 2487 case 6: 2488 ha->max_cmds = 8; 2489 break; 2490 2491 case 7: 2492 default: 2493 ha->max_cmds = 4; 2494 break; 2495 } 2496 } 2497 2498 /* Limit the Active Commands on a Lite Adapter */ 2499 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) || 2500 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) || 2501 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) { 2502 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds)) 2503 ha->max_cmds = MaxLiteCmds; 2504 } 2505 2506 /* set controller IDs */ 2507 ha->ha_id[0] = IPS_ADAPTER_ID; 2508 for (i = 1; i < ha->nbus; i++) { 2509 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f; 2510 ha->dcdb_active[i - 1] = 0; 2511 } 2512 2513 return (1); 2514 } 2515 2516 /****************************************************************************/ 2517 /* */ 2518 /* Routine Name: ips_next */ 2519 /* */ 2520 /* Routine Description: */ 2521 /* */ 2522 /* Take the next command off the queue and send it to the controller */ 2523 /* */ 2524 /****************************************************************************/ 2525 static void 2526 ips_next(ips_ha_t * ha, int intr) 2527 { 2528 ips_scb_t *scb; 2529 struct scsi_cmnd *SC; 2530 struct scsi_cmnd *p; 2531 struct scsi_cmnd *q; 2532 ips_copp_wait_item_t *item; 2533 int ret; 2534 struct Scsi_Host *host; 2535 METHOD_TRACE("ips_next", 1); 2536 2537 if (!ha) 2538 return; 2539 host = ips_sh[ha->host_num]; 2540 /* 2541 * Block access to the queue function so 2542 * this command won't time out 2543 */ 2544 if (intr == IPS_INTR_ON) 2545 spin_lock(host->host_lock); 2546 2547 if ((ha->subsys->param[3] & 0x300000) 2548 && (ha->scb_activelist.count == 0)) { 2549 time64_t now = ktime_get_real_seconds(); 2550 if (now - ha->last_ffdc > IPS_SECS_8HOURS) { 2551 ha->last_ffdc = now; 2552 ips_ffdc_time(ha); 2553 } 2554 } 2555 2556 /* 2557 * Send passthru commands 2558 * These have priority over normal I/O 2559 * but shouldn't affect performance too much 2560 * since we limit the number that can be active 2561 * on the card at any one time 2562 */ 2563 while ((ha->num_ioctl < IPS_MAX_IOCTL) && 2564 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) { 2565 2566 item = ips_removeq_copp_head(&ha->copp_waitlist); 2567 ha->num_ioctl++; 2568 if (intr == IPS_INTR_ON) 2569 spin_unlock(host->host_lock); 2570 scb->scsi_cmd = item->scsi_cmd; 2571 kfree(item); 2572 2573 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr); 2574 2575 if (intr == IPS_INTR_ON) 2576 spin_lock(host->host_lock); 2577 switch (ret) { 2578 case IPS_FAILURE: 2579 if (scb->scsi_cmd) { 2580 scb->scsi_cmd->result = DID_ERROR << 16; 2581 scsi_done(scb->scsi_cmd); 2582 } 2583 2584 ips_freescb(ha, scb); 2585 break; 2586 case IPS_SUCCESS_IMM: 2587 if (scb->scsi_cmd) { 2588 scb->scsi_cmd->result = DID_OK << 16; 2589 scsi_done(scb->scsi_cmd); 2590 } 2591 2592 ips_freescb(ha, scb); 2593 break; 2594 default: 2595 break; 2596 } /* end case */ 2597 2598 if (ret != IPS_SUCCESS) { 2599 ha->num_ioctl--; 2600 continue; 2601 } 2602 2603 ret = ips_send_cmd(ha, scb); 2604 2605 if (ret == IPS_SUCCESS) 2606 ips_putq_scb_head(&ha->scb_activelist, scb); 2607 else 2608 ha->num_ioctl--; 2609 2610 switch (ret) { 2611 case IPS_FAILURE: 2612 if (scb->scsi_cmd) { 2613 scb->scsi_cmd->result = DID_ERROR << 16; 2614 } 2615 2616 ips_freescb(ha, scb); 2617 break; 2618 case IPS_SUCCESS_IMM: 2619 ips_freescb(ha, scb); 2620 break; 2621 default: 2622 break; 2623 } /* end case */ 2624 2625 } 2626 2627 /* 2628 * Send "Normal" I/O commands 2629 */ 2630 2631 p = ha->scb_waitlist.head; 2632 while ((p) && (scb = ips_getscb(ha))) { 2633 if ((scmd_channel(p) > 0) 2634 && (ha-> 2635 dcdb_active[scmd_channel(p) - 2636 1] & (1 << scmd_id(p)))) { 2637 ips_freescb(ha, scb); 2638 p = (struct scsi_cmnd *) p->host_scribble; 2639 continue; 2640 } 2641 2642 q = p; 2643 SC = ips_removeq_wait(&ha->scb_waitlist, q); 2644 2645 if (intr == IPS_INTR_ON) 2646 spin_unlock(host->host_lock); /* Unlock HA after command is taken off queue */ 2647 2648 SC->result = DID_OK; 2649 SC->host_scribble = NULL; 2650 2651 scb->target_id = SC->device->id; 2652 scb->lun = SC->device->lun; 2653 scb->bus = SC->device->channel; 2654 scb->scsi_cmd = SC; 2655 scb->breakup = 0; 2656 scb->data_len = 0; 2657 scb->callback = ipsintr_done; 2658 scb->timeout = ips_cmd_timeout; 2659 memset(&scb->cmd, 0, 16); 2660 2661 /* copy in the CDB */ 2662 memcpy(scb->cdb, SC->cmnd, SC->cmd_len); 2663 2664 scb->sg_count = scsi_dma_map(SC); 2665 BUG_ON(scb->sg_count < 0); 2666 if (scb->sg_count) { 2667 struct scatterlist *sg; 2668 int i; 2669 2670 scb->flags |= IPS_SCB_MAP_SG; 2671 2672 scsi_for_each_sg(SC, sg, scb->sg_count, i) { 2673 if (ips_fill_scb_sg_single 2674 (ha, sg_dma_address(sg), scb, i, 2675 sg_dma_len(sg)) < 0) 2676 break; 2677 } 2678 scb->dcdb.transfer_length = scb->data_len; 2679 } else { 2680 scb->data_busaddr = 0L; 2681 scb->sg_len = 0; 2682 scb->data_len = 0; 2683 scb->dcdb.transfer_length = 0; 2684 } 2685 2686 scb->dcdb.cmd_attribute = 2687 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 2688 2689 /* Allow a WRITE BUFFER Command to Have no Data */ 2690 /* This is Used by Tape Flash Utilites */ 2691 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && 2692 (scb->data_len == 0)) 2693 scb->dcdb.cmd_attribute = 0; 2694 2695 if (!(scb->dcdb.cmd_attribute & 0x3)) 2696 scb->dcdb.transfer_length = 0; 2697 2698 if (scb->data_len >= IPS_MAX_XFER) { 2699 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 2700 scb->dcdb.transfer_length = 0; 2701 } 2702 if (intr == IPS_INTR_ON) 2703 spin_lock(host->host_lock); 2704 2705 ret = ips_send_cmd(ha, scb); 2706 2707 switch (ret) { 2708 case IPS_SUCCESS: 2709 ips_putq_scb_head(&ha->scb_activelist, scb); 2710 break; 2711 case IPS_FAILURE: 2712 if (scb->scsi_cmd) { 2713 scb->scsi_cmd->result = DID_ERROR << 16; 2714 scsi_done(scb->scsi_cmd); 2715 } 2716 2717 if (scb->bus) 2718 ha->dcdb_active[scb->bus - 1] &= 2719 ~(1 << scb->target_id); 2720 2721 ips_freescb(ha, scb); 2722 break; 2723 case IPS_SUCCESS_IMM: 2724 if (scb->scsi_cmd) 2725 scsi_done(scb->scsi_cmd); 2726 2727 if (scb->bus) 2728 ha->dcdb_active[scb->bus - 1] &= 2729 ~(1 << scb->target_id); 2730 2731 ips_freescb(ha, scb); 2732 break; 2733 default: 2734 break; 2735 } /* end case */ 2736 2737 p = (struct scsi_cmnd *) p->host_scribble; 2738 2739 } /* end while */ 2740 2741 if (intr == IPS_INTR_ON) 2742 spin_unlock(host->host_lock); 2743 } 2744 2745 /****************************************************************************/ 2746 /* */ 2747 /* Routine Name: ips_putq_scb_head */ 2748 /* */ 2749 /* Routine Description: */ 2750 /* */ 2751 /* Add an item to the head of the queue */ 2752 /* */ 2753 /* ASSUMED to be called from within the HA lock */ 2754 /* */ 2755 /****************************************************************************/ 2756 static void 2757 ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item) 2758 { 2759 METHOD_TRACE("ips_putq_scb_head", 1); 2760 2761 if (!item) 2762 return; 2763 2764 item->q_next = queue->head; 2765 queue->head = item; 2766 2767 if (!queue->tail) 2768 queue->tail = item; 2769 2770 queue->count++; 2771 } 2772 2773 /****************************************************************************/ 2774 /* */ 2775 /* Routine Name: ips_removeq_scb_head */ 2776 /* */ 2777 /* Routine Description: */ 2778 /* */ 2779 /* Remove the head of the queue */ 2780 /* */ 2781 /* ASSUMED to be called from within the HA lock */ 2782 /* */ 2783 /****************************************************************************/ 2784 static ips_scb_t * 2785 ips_removeq_scb_head(ips_scb_queue_t * queue) 2786 { 2787 ips_scb_t *item; 2788 2789 METHOD_TRACE("ips_removeq_scb_head", 1); 2790 2791 item = queue->head; 2792 2793 if (!item) { 2794 return (NULL); 2795 } 2796 2797 queue->head = item->q_next; 2798 item->q_next = NULL; 2799 2800 if (queue->tail == item) 2801 queue->tail = NULL; 2802 2803 queue->count--; 2804 2805 return (item); 2806 } 2807 2808 /****************************************************************************/ 2809 /* */ 2810 /* Routine Name: ips_removeq_scb */ 2811 /* */ 2812 /* Routine Description: */ 2813 /* */ 2814 /* Remove an item from a queue */ 2815 /* */ 2816 /* ASSUMED to be called from within the HA lock */ 2817 /* */ 2818 /****************************************************************************/ 2819 static ips_scb_t * 2820 ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item) 2821 { 2822 ips_scb_t *p; 2823 2824 METHOD_TRACE("ips_removeq_scb", 1); 2825 2826 if (!item) 2827 return (NULL); 2828 2829 if (item == queue->head) { 2830 return (ips_removeq_scb_head(queue)); 2831 } 2832 2833 p = queue->head; 2834 2835 while ((p) && (item != p->q_next)) 2836 p = p->q_next; 2837 2838 if (p) { 2839 /* found a match */ 2840 p->q_next = item->q_next; 2841 2842 if (!item->q_next) 2843 queue->tail = p; 2844 2845 item->q_next = NULL; 2846 queue->count--; 2847 2848 return (item); 2849 } 2850 2851 return (NULL); 2852 } 2853 2854 /****************************************************************************/ 2855 /* */ 2856 /* Routine Name: ips_putq_wait_tail */ 2857 /* */ 2858 /* Routine Description: */ 2859 /* */ 2860 /* Add an item to the tail of the queue */ 2861 /* */ 2862 /* ASSUMED to be called from within the HA lock */ 2863 /* */ 2864 /****************************************************************************/ 2865 static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item) 2866 { 2867 METHOD_TRACE("ips_putq_wait_tail", 1); 2868 2869 if (!item) 2870 return; 2871 2872 item->host_scribble = NULL; 2873 2874 if (queue->tail) 2875 queue->tail->host_scribble = (char *) item; 2876 2877 queue->tail = item; 2878 2879 if (!queue->head) 2880 queue->head = item; 2881 2882 queue->count++; 2883 } 2884 2885 /****************************************************************************/ 2886 /* */ 2887 /* Routine Name: ips_removeq_wait_head */ 2888 /* */ 2889 /* Routine Description: */ 2890 /* */ 2891 /* Remove the head of the queue */ 2892 /* */ 2893 /* ASSUMED to be called from within the HA lock */ 2894 /* */ 2895 /****************************************************************************/ 2896 static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue) 2897 { 2898 struct scsi_cmnd *item; 2899 2900 METHOD_TRACE("ips_removeq_wait_head", 1); 2901 2902 item = queue->head; 2903 2904 if (!item) { 2905 return (NULL); 2906 } 2907 2908 queue->head = (struct scsi_cmnd *) item->host_scribble; 2909 item->host_scribble = NULL; 2910 2911 if (queue->tail == item) 2912 queue->tail = NULL; 2913 2914 queue->count--; 2915 2916 return (item); 2917 } 2918 2919 /****************************************************************************/ 2920 /* */ 2921 /* Routine Name: ips_removeq_wait */ 2922 /* */ 2923 /* Routine Description: */ 2924 /* */ 2925 /* Remove an item from a queue */ 2926 /* */ 2927 /* ASSUMED to be called from within the HA lock */ 2928 /* */ 2929 /****************************************************************************/ 2930 static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue, 2931 struct scsi_cmnd *item) 2932 { 2933 struct scsi_cmnd *p; 2934 2935 METHOD_TRACE("ips_removeq_wait", 1); 2936 2937 if (!item) 2938 return (NULL); 2939 2940 if (item == queue->head) { 2941 return (ips_removeq_wait_head(queue)); 2942 } 2943 2944 p = queue->head; 2945 2946 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble)) 2947 p = (struct scsi_cmnd *) p->host_scribble; 2948 2949 if (p) { 2950 /* found a match */ 2951 p->host_scribble = item->host_scribble; 2952 2953 if (!item->host_scribble) 2954 queue->tail = p; 2955 2956 item->host_scribble = NULL; 2957 queue->count--; 2958 2959 return (item); 2960 } 2961 2962 return (NULL); 2963 } 2964 2965 /****************************************************************************/ 2966 /* */ 2967 /* Routine Name: ips_putq_copp_tail */ 2968 /* */ 2969 /* Routine Description: */ 2970 /* */ 2971 /* Add an item to the tail of the queue */ 2972 /* */ 2973 /* ASSUMED to be called from within the HA lock */ 2974 /* */ 2975 /****************************************************************************/ 2976 static void 2977 ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 2978 { 2979 METHOD_TRACE("ips_putq_copp_tail", 1); 2980 2981 if (!item) 2982 return; 2983 2984 item->next = NULL; 2985 2986 if (queue->tail) 2987 queue->tail->next = item; 2988 2989 queue->tail = item; 2990 2991 if (!queue->head) 2992 queue->head = item; 2993 2994 queue->count++; 2995 } 2996 2997 /****************************************************************************/ 2998 /* */ 2999 /* Routine Name: ips_removeq_copp_head */ 3000 /* */ 3001 /* Routine Description: */ 3002 /* */ 3003 /* Remove the head of the queue */ 3004 /* */ 3005 /* ASSUMED to be called from within the HA lock */ 3006 /* */ 3007 /****************************************************************************/ 3008 static ips_copp_wait_item_t * 3009 ips_removeq_copp_head(ips_copp_queue_t * queue) 3010 { 3011 ips_copp_wait_item_t *item; 3012 3013 METHOD_TRACE("ips_removeq_copp_head", 1); 3014 3015 item = queue->head; 3016 3017 if (!item) { 3018 return (NULL); 3019 } 3020 3021 queue->head = item->next; 3022 item->next = NULL; 3023 3024 if (queue->tail == item) 3025 queue->tail = NULL; 3026 3027 queue->count--; 3028 3029 return (item); 3030 } 3031 3032 /****************************************************************************/ 3033 /* */ 3034 /* Routine Name: ips_removeq_copp */ 3035 /* */ 3036 /* Routine Description: */ 3037 /* */ 3038 /* Remove an item from a queue */ 3039 /* */ 3040 /* ASSUMED to be called from within the HA lock */ 3041 /* */ 3042 /****************************************************************************/ 3043 static ips_copp_wait_item_t * 3044 ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item) 3045 { 3046 ips_copp_wait_item_t *p; 3047 3048 METHOD_TRACE("ips_removeq_copp", 1); 3049 3050 if (!item) 3051 return (NULL); 3052 3053 if (item == queue->head) { 3054 return (ips_removeq_copp_head(queue)); 3055 } 3056 3057 p = queue->head; 3058 3059 while ((p) && (item != p->next)) 3060 p = p->next; 3061 3062 if (p) { 3063 /* found a match */ 3064 p->next = item->next; 3065 3066 if (!item->next) 3067 queue->tail = p; 3068 3069 item->next = NULL; 3070 queue->count--; 3071 3072 return (item); 3073 } 3074 3075 return (NULL); 3076 } 3077 3078 /****************************************************************************/ 3079 /* */ 3080 /* Routine Name: ipsintr_blocking */ 3081 /* */ 3082 /* Routine Description: */ 3083 /* */ 3084 /* Finalize an interrupt for internal commands */ 3085 /* */ 3086 /****************************************************************************/ 3087 static void 3088 ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb) 3089 { 3090 METHOD_TRACE("ipsintr_blocking", 2); 3091 3092 ips_freescb(ha, scb); 3093 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) { 3094 ha->waitflag = FALSE; 3095 3096 return; 3097 } 3098 } 3099 3100 /****************************************************************************/ 3101 /* */ 3102 /* Routine Name: ipsintr_done */ 3103 /* */ 3104 /* Routine Description: */ 3105 /* */ 3106 /* Finalize an interrupt for non-internal commands */ 3107 /* */ 3108 /****************************************************************************/ 3109 static void 3110 ipsintr_done(ips_ha_t * ha, ips_scb_t * scb) 3111 { 3112 METHOD_TRACE("ipsintr_done", 2); 3113 3114 if (!scb) { 3115 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3116 "Spurious interrupt; scb NULL.\n"); 3117 3118 return; 3119 } 3120 3121 if (scb->scsi_cmd == NULL) { 3122 /* unexpected interrupt */ 3123 IPS_PRINTK(KERN_WARNING, ha->pcidev, 3124 "Spurious interrupt; scsi_cmd not set.\n"); 3125 3126 return; 3127 } 3128 3129 ips_done(ha, scb); 3130 } 3131 3132 /****************************************************************************/ 3133 /* */ 3134 /* Routine Name: ips_done */ 3135 /* */ 3136 /* Routine Description: */ 3137 /* */ 3138 /* Do housekeeping on completed commands */ 3139 /* ASSUMED to be called form within the request lock */ 3140 /****************************************************************************/ 3141 static void 3142 ips_done(ips_ha_t * ha, ips_scb_t * scb) 3143 { 3144 int ret; 3145 3146 METHOD_TRACE("ips_done", 1); 3147 3148 if (!scb) 3149 return; 3150 3151 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) { 3152 ips_cleanup_passthru(ha, scb); 3153 ha->num_ioctl--; 3154 } else { 3155 /* 3156 * Check to see if this command had too much 3157 * data and had to be broke up. If so, queue 3158 * the rest of the data and continue. 3159 */ 3160 if ((scb->breakup) || (scb->sg_break)) { 3161 struct scatterlist *sg; 3162 int i, sg_dma_index, ips_sg_index = 0; 3163 3164 /* we had a data breakup */ 3165 scb->data_len = 0; 3166 3167 sg = scsi_sglist(scb->scsi_cmd); 3168 3169 /* Spin forward to last dma chunk */ 3170 sg_dma_index = scb->breakup; 3171 for (i = 0; i < scb->breakup; i++) 3172 sg = sg_next(sg); 3173 3174 /* Take care of possible partial on last chunk */ 3175 ips_fill_scb_sg_single(ha, 3176 sg_dma_address(sg), 3177 scb, ips_sg_index++, 3178 sg_dma_len(sg)); 3179 3180 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd); 3181 sg_dma_index++, sg = sg_next(sg)) { 3182 if (ips_fill_scb_sg_single 3183 (ha, 3184 sg_dma_address(sg), 3185 scb, ips_sg_index++, 3186 sg_dma_len(sg)) < 0) 3187 break; 3188 } 3189 3190 scb->dcdb.transfer_length = scb->data_len; 3191 scb->dcdb.cmd_attribute |= 3192 ips_command_direction[scb->scsi_cmd->cmnd[0]]; 3193 3194 if (!(scb->dcdb.cmd_attribute & 0x3)) 3195 scb->dcdb.transfer_length = 0; 3196 3197 if (scb->data_len >= IPS_MAX_XFER) { 3198 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K; 3199 scb->dcdb.transfer_length = 0; 3200 } 3201 3202 ret = ips_send_cmd(ha, scb); 3203 3204 switch (ret) { 3205 case IPS_FAILURE: 3206 if (scb->scsi_cmd) { 3207 scb->scsi_cmd->result = DID_ERROR << 16; 3208 scsi_done(scb->scsi_cmd); 3209 } 3210 3211 ips_freescb(ha, scb); 3212 break; 3213 case IPS_SUCCESS_IMM: 3214 if (scb->scsi_cmd) { 3215 scb->scsi_cmd->result = DID_ERROR << 16; 3216 scsi_done(scb->scsi_cmd); 3217 } 3218 3219 ips_freescb(ha, scb); 3220 break; 3221 default: 3222 break; 3223 } /* end case */ 3224 3225 return; 3226 } 3227 } /* end if passthru */ 3228 3229 if (scb->bus) { 3230 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id); 3231 } 3232 3233 scsi_done(scb->scsi_cmd); 3234 3235 ips_freescb(ha, scb); 3236 } 3237 3238 /****************************************************************************/ 3239 /* */ 3240 /* Routine Name: ips_map_status */ 3241 /* */ 3242 /* Routine Description: */ 3243 /* */ 3244 /* Map Controller Error codes to Linux Error Codes */ 3245 /* */ 3246 /****************************************************************************/ 3247 static int 3248 ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp) 3249 { 3250 int errcode; 3251 int device_error; 3252 uint32_t transfer_len; 3253 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3254 IPS_SCSI_INQ_DATA inquiryData; 3255 3256 METHOD_TRACE("ips_map_status", 1); 3257 3258 if (scb->bus) { 3259 DEBUG_VAR(2, 3260 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x", 3261 ips_name, ha->host_num, 3262 scb->scsi_cmd->device->channel, 3263 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun, 3264 scb->basic_status, scb->extended_status, 3265 scb->extended_status == 3266 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0, 3267 scb->extended_status == 3268 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0, 3269 scb->extended_status == 3270 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0); 3271 } 3272 3273 /* default driver error */ 3274 errcode = DID_ERROR; 3275 device_error = 0; 3276 3277 switch (scb->basic_status & IPS_GSC_STATUS_MASK) { 3278 case IPS_CMD_TIMEOUT: 3279 errcode = DID_TIME_OUT; 3280 break; 3281 3282 case IPS_INVAL_OPCO: 3283 case IPS_INVAL_CMD_BLK: 3284 case IPS_INVAL_PARM_BLK: 3285 case IPS_LD_ERROR: 3286 case IPS_CMD_CMPLT_WERROR: 3287 break; 3288 3289 case IPS_PHYS_DRV_ERROR: 3290 switch (scb->extended_status) { 3291 case IPS_ERR_SEL_TO: 3292 if (scb->bus) 3293 errcode = DID_NO_CONNECT; 3294 3295 break; 3296 3297 case IPS_ERR_OU_RUN: 3298 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) || 3299 (scb->cmd.dcdb.op_code == 3300 IPS_CMD_EXTENDED_DCDB_SG)) { 3301 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3302 transfer_len = tapeDCDB->transfer_length; 3303 } else { 3304 transfer_len = 3305 (uint32_t) scb->dcdb.transfer_length; 3306 } 3307 3308 if ((scb->bus) && (transfer_len < scb->data_len)) { 3309 /* Underrun - set default to no error */ 3310 errcode = DID_OK; 3311 3312 /* Restrict access to physical DASD */ 3313 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3314 ips_scmd_buf_read(scb->scsi_cmd, 3315 &inquiryData, sizeof (inquiryData)); 3316 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) { 3317 errcode = DID_TIME_OUT; 3318 break; 3319 } 3320 } 3321 } else 3322 errcode = DID_ERROR; 3323 3324 break; 3325 3326 case IPS_ERR_RECOVERY: 3327 /* don't fail recovered errors */ 3328 if (scb->bus) 3329 errcode = DID_OK; 3330 3331 break; 3332 3333 case IPS_ERR_HOST_RESET: 3334 case IPS_ERR_DEV_RESET: 3335 errcode = DID_RESET; 3336 break; 3337 3338 case IPS_ERR_CKCOND: 3339 if (scb->bus) { 3340 if ((scb->cmd.dcdb.op_code == 3341 IPS_CMD_EXTENDED_DCDB) 3342 || (scb->cmd.dcdb.op_code == 3343 IPS_CMD_EXTENDED_DCDB_SG)) { 3344 tapeDCDB = 3345 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; 3346 memcpy_and_pad(scb->scsi_cmd->sense_buffer, 3347 SCSI_SENSE_BUFFERSIZE, 3348 tapeDCDB->sense_info, 3349 sizeof(tapeDCDB->sense_info), 0); 3350 } else { 3351 memcpy_and_pad(scb->scsi_cmd->sense_buffer, 3352 SCSI_SENSE_BUFFERSIZE, 3353 scb->dcdb.sense_info, 3354 sizeof(scb->dcdb.sense_info), 0); 3355 } 3356 device_error = 2; /* check condition */ 3357 } 3358 3359 errcode = DID_OK; 3360 3361 break; 3362 3363 default: 3364 errcode = DID_ERROR; 3365 break; 3366 3367 } /* end switch */ 3368 } /* end switch */ 3369 3370 scb->scsi_cmd->result = device_error | (errcode << 16); 3371 3372 return (1); 3373 } 3374 3375 /****************************************************************************/ 3376 /* */ 3377 /* Routine Name: ips_send_wait */ 3378 /* */ 3379 /* Routine Description: */ 3380 /* */ 3381 /* Send a command to the controller and wait for it to return */ 3382 /* */ 3383 /* The FFDC Time Stamp use this function for the callback, but doesn't */ 3384 /* actually need to wait. */ 3385 /****************************************************************************/ 3386 static int 3387 ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr) 3388 { 3389 int ret; 3390 3391 METHOD_TRACE("ips_send_wait", 1); 3392 3393 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */ 3394 ha->waitflag = TRUE; 3395 ha->cmd_in_progress = scb->cdb[0]; 3396 } 3397 scb->callback = ipsintr_blocking; 3398 ret = ips_send_cmd(ha, scb); 3399 3400 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM)) 3401 return (ret); 3402 3403 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */ 3404 ret = ips_wait(ha, timeout, intr); 3405 3406 return (ret); 3407 } 3408 3409 /****************************************************************************/ 3410 /* */ 3411 /* Routine Name: ips_scmd_buf_write */ 3412 /* */ 3413 /* Routine Description: */ 3414 /* Write data to struct scsi_cmnd request_buffer at proper offsets */ 3415 /****************************************************************************/ 3416 static void 3417 ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count) 3418 { 3419 unsigned long flags; 3420 3421 local_irq_save(flags); 3422 scsi_sg_copy_from_buffer(scmd, data, count); 3423 local_irq_restore(flags); 3424 } 3425 3426 /****************************************************************************/ 3427 /* */ 3428 /* Routine Name: ips_scmd_buf_read */ 3429 /* */ 3430 /* Routine Description: */ 3431 /* Copy data from a struct scsi_cmnd to a new, linear buffer */ 3432 /****************************************************************************/ 3433 static void 3434 ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count) 3435 { 3436 unsigned long flags; 3437 3438 local_irq_save(flags); 3439 scsi_sg_copy_to_buffer(scmd, data, count); 3440 local_irq_restore(flags); 3441 } 3442 3443 /****************************************************************************/ 3444 /* */ 3445 /* Routine Name: ips_send_cmd */ 3446 /* */ 3447 /* Routine Description: */ 3448 /* */ 3449 /* Map SCSI commands to ServeRAID commands for logical drives */ 3450 /* */ 3451 /****************************************************************************/ 3452 static int 3453 ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb) 3454 { 3455 int ret; 3456 char *sp; 3457 int device_error; 3458 IPS_DCDB_TABLE_TAPE *tapeDCDB; 3459 int TimeOut; 3460 3461 METHOD_TRACE("ips_send_cmd", 1); 3462 3463 ret = IPS_SUCCESS; 3464 3465 if (!scb->scsi_cmd) { 3466 /* internal command */ 3467 3468 if (scb->bus > 0) { 3469 /* Controller commands can't be issued */ 3470 /* to real devices -- fail them */ 3471 if ((ha->waitflag == TRUE) && 3472 (ha->cmd_in_progress == scb->cdb[0])) { 3473 ha->waitflag = FALSE; 3474 } 3475 3476 return (1); 3477 } 3478 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) { 3479 /* command to logical bus -- interpret */ 3480 ret = IPS_SUCCESS_IMM; 3481 3482 switch (scb->scsi_cmd->cmnd[0]) { 3483 case ALLOW_MEDIUM_REMOVAL: 3484 case REZERO_UNIT: 3485 case ERASE: 3486 case WRITE_FILEMARKS: 3487 case SPACE: 3488 scb->scsi_cmd->result = DID_ERROR << 16; 3489 break; 3490 3491 case START_STOP: 3492 scb->scsi_cmd->result = DID_OK << 16; 3493 break; 3494 3495 case TEST_UNIT_READY: 3496 case INQUIRY: 3497 if (scb->target_id == IPS_ADAPTER_ID) { 3498 /* 3499 * Either we have a TUR 3500 * or we have a SCSI inquiry 3501 */ 3502 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY) 3503 scb->scsi_cmd->result = DID_OK << 16; 3504 3505 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3506 IPS_SCSI_INQ_DATA inquiry; 3507 3508 memset(&inquiry, 0, 3509 sizeof (IPS_SCSI_INQ_DATA)); 3510 3511 inquiry.DeviceType = 3512 IPS_SCSI_INQ_TYPE_PROCESSOR; 3513 inquiry.DeviceTypeQualifier = 3514 IPS_SCSI_INQ_LU_CONNECTED; 3515 inquiry.Version = IPS_SCSI_INQ_REV2; 3516 inquiry.ResponseDataFormat = 3517 IPS_SCSI_INQ_RD_REV2; 3518 inquiry.AdditionalLength = 31; 3519 inquiry.Flags[0] = 3520 IPS_SCSI_INQ_Address16; 3521 inquiry.Flags[1] = 3522 IPS_SCSI_INQ_WBus16 | 3523 IPS_SCSI_INQ_Sync; 3524 memcpy(inquiry.VendorId, "IBM ", 3525 8); 3526 memcpy(inquiry.ProductId, 3527 "SERVERAID ", 16); 3528 memcpy(inquiry.ProductRevisionLevel, 3529 "1.00", 4); 3530 3531 ips_scmd_buf_write(scb->scsi_cmd, 3532 &inquiry, 3533 sizeof (inquiry)); 3534 3535 scb->scsi_cmd->result = DID_OK << 16; 3536 } 3537 } else { 3538 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3539 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3540 scb->cmd.logical_info.reserved = 0; 3541 scb->cmd.logical_info.reserved2 = 0; 3542 scb->data_len = sizeof (IPS_LD_INFO); 3543 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3544 scb->flags = 0; 3545 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3546 ret = IPS_SUCCESS; 3547 } 3548 3549 break; 3550 3551 case REQUEST_SENSE: 3552 ips_reqsen(ha, scb); 3553 scb->scsi_cmd->result = DID_OK << 16; 3554 break; 3555 3556 case READ_6: 3557 case WRITE_6: 3558 if (!scb->sg_len) { 3559 scb->cmd.basic_io.op_code = 3560 (scb->scsi_cmd->cmnd[0] == 3561 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE; 3562 scb->cmd.basic_io.enhanced_sg = 0; 3563 scb->cmd.basic_io.sg_addr = 3564 cpu_to_le32(scb->data_busaddr); 3565 } else { 3566 scb->cmd.basic_io.op_code = 3567 (scb->scsi_cmd->cmnd[0] == 3568 READ_6) ? IPS_CMD_READ_SG : 3569 IPS_CMD_WRITE_SG; 3570 scb->cmd.basic_io.enhanced_sg = 3571 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3572 scb->cmd.basic_io.sg_addr = 3573 cpu_to_le32(scb->sg_busaddr); 3574 } 3575 3576 scb->cmd.basic_io.segment_4G = 0; 3577 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3578 scb->cmd.basic_io.log_drv = scb->target_id; 3579 scb->cmd.basic_io.sg_count = scb->sg_len; 3580 3581 if (scb->cmd.basic_io.lba) 3582 le32_add_cpu(&scb->cmd.basic_io.lba, 3583 le16_to_cpu(scb->cmd.basic_io. 3584 sector_count)); 3585 else 3586 scb->cmd.basic_io.lba = 3587 (((scb->scsi_cmd-> 3588 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd-> 3589 cmnd[2] << 8) | 3590 (scb->scsi_cmd->cmnd[3])); 3591 3592 scb->cmd.basic_io.sector_count = 3593 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3594 3595 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0) 3596 scb->cmd.basic_io.sector_count = 3597 cpu_to_le16(256); 3598 3599 ret = IPS_SUCCESS; 3600 break; 3601 3602 case READ_10: 3603 case WRITE_10: 3604 if (!scb->sg_len) { 3605 scb->cmd.basic_io.op_code = 3606 (scb->scsi_cmd->cmnd[0] == 3607 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE; 3608 scb->cmd.basic_io.enhanced_sg = 0; 3609 scb->cmd.basic_io.sg_addr = 3610 cpu_to_le32(scb->data_busaddr); 3611 } else { 3612 scb->cmd.basic_io.op_code = 3613 (scb->scsi_cmd->cmnd[0] == 3614 READ_10) ? IPS_CMD_READ_SG : 3615 IPS_CMD_WRITE_SG; 3616 scb->cmd.basic_io.enhanced_sg = 3617 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3618 scb->cmd.basic_io.sg_addr = 3619 cpu_to_le32(scb->sg_busaddr); 3620 } 3621 3622 scb->cmd.basic_io.segment_4G = 0; 3623 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3624 scb->cmd.basic_io.log_drv = scb->target_id; 3625 scb->cmd.basic_io.sg_count = scb->sg_len; 3626 3627 if (scb->cmd.basic_io.lba) 3628 le32_add_cpu(&scb->cmd.basic_io.lba, 3629 le16_to_cpu(scb->cmd.basic_io. 3630 sector_count)); 3631 else 3632 scb->cmd.basic_io.lba = 3633 ((scb->scsi_cmd->cmnd[2] << 24) | (scb-> 3634 scsi_cmd-> 3635 cmnd[3] 3636 << 16) | 3637 (scb->scsi_cmd->cmnd[4] << 8) | scb-> 3638 scsi_cmd->cmnd[5]); 3639 3640 scb->cmd.basic_io.sector_count = 3641 cpu_to_le16(scb->data_len / IPS_BLKSIZE); 3642 3643 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) { 3644 /* 3645 * This is a null condition 3646 * we don't have to do anything 3647 * so just return 3648 */ 3649 scb->scsi_cmd->result = DID_OK << 16; 3650 } else 3651 ret = IPS_SUCCESS; 3652 3653 break; 3654 3655 case RESERVE: 3656 case RELEASE: 3657 scb->scsi_cmd->result = DID_OK << 16; 3658 break; 3659 3660 case MODE_SENSE: 3661 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 3662 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 3663 scb->cmd.basic_io.segment_4G = 0; 3664 scb->cmd.basic_io.enhanced_sg = 0; 3665 scb->data_len = sizeof (*ha->enq); 3666 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 3667 ret = IPS_SUCCESS; 3668 break; 3669 3670 case READ_CAPACITY: 3671 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO; 3672 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb); 3673 scb->cmd.logical_info.reserved = 0; 3674 scb->cmd.logical_info.reserved2 = 0; 3675 scb->cmd.logical_info.reserved3 = 0; 3676 scb->data_len = sizeof (IPS_LD_INFO); 3677 scb->data_busaddr = ha->logical_drive_info_dma_addr; 3678 scb->flags = 0; 3679 scb->cmd.logical_info.buffer_addr = scb->data_busaddr; 3680 ret = IPS_SUCCESS; 3681 break; 3682 3683 case SEND_DIAGNOSTIC: 3684 case REASSIGN_BLOCKS: 3685 case FORMAT_UNIT: 3686 case SEEK_10: 3687 case VERIFY: 3688 case READ_DEFECT_DATA: 3689 case READ_BUFFER: 3690 case WRITE_BUFFER: 3691 scb->scsi_cmd->result = DID_OK << 16; 3692 break; 3693 3694 default: 3695 /* Set the Return Info to appear like the Command was */ 3696 /* attempted, a Check Condition occurred, and Sense */ 3697 /* Data indicating an Invalid CDB OpCode is returned. */ 3698 sp = (char *) scb->scsi_cmd->sense_buffer; 3699 3700 sp[0] = 0x70; /* Error Code */ 3701 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */ 3702 sp[7] = 0x0A; /* Additional Sense Length */ 3703 sp[12] = 0x20; /* ASC = Invalid OpCode */ 3704 sp[13] = 0x00; /* ASCQ */ 3705 3706 device_error = 2; /* Indicate Check Condition */ 3707 scb->scsi_cmd->result = device_error | (DID_OK << 16); 3708 break; 3709 } /* end switch */ 3710 } 3711 /* end if */ 3712 if (ret == IPS_SUCCESS_IMM) 3713 return (ret); 3714 3715 /* setup DCDB */ 3716 if (scb->bus > 0) { 3717 3718 /* If we already know the Device is Not there, no need to attempt a Command */ 3719 /* This also protects an NT FailOver Controller from getting CDB's sent to it */ 3720 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) { 3721 scb->scsi_cmd->result = DID_NO_CONNECT << 16; 3722 return (IPS_SUCCESS_IMM); 3723 } 3724 3725 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id); 3726 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb); 3727 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr + 3728 (unsigned long) &scb-> 3729 dcdb - 3730 (unsigned long) scb); 3731 scb->cmd.dcdb.reserved = 0; 3732 scb->cmd.dcdb.reserved2 = 0; 3733 scb->cmd.dcdb.reserved3 = 0; 3734 scb->cmd.dcdb.segment_4G = 0; 3735 scb->cmd.dcdb.enhanced_sg = 0; 3736 3737 TimeOut = scsi_cmd_to_rq(scb->scsi_cmd)->timeout; 3738 3739 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */ 3740 if (!scb->sg_len) { 3741 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB; 3742 } else { 3743 scb->cmd.dcdb.op_code = 3744 IPS_CMD_EXTENDED_DCDB_SG; 3745 scb->cmd.dcdb.enhanced_sg = 3746 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3747 } 3748 3749 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */ 3750 tapeDCDB->device_address = 3751 ((scb->bus - 1) << 4) | scb->target_id; 3752 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED; 3753 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */ 3754 3755 if (TimeOut) { 3756 if (TimeOut < (10 * HZ)) 3757 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 3758 else if (TimeOut < (60 * HZ)) 3759 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 3760 else if (TimeOut < (1200 * HZ)) 3761 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 3762 } 3763 3764 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len; 3765 tapeDCDB->reserved_for_LUN = 0; 3766 tapeDCDB->transfer_length = scb->data_len; 3767 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG) 3768 tapeDCDB->buffer_pointer = 3769 cpu_to_le32(scb->sg_busaddr); 3770 else 3771 tapeDCDB->buffer_pointer = 3772 cpu_to_le32(scb->data_busaddr); 3773 tapeDCDB->sg_count = scb->sg_len; 3774 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info); 3775 tapeDCDB->scsi_status = 0; 3776 tapeDCDB->reserved = 0; 3777 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd, 3778 scb->scsi_cmd->cmd_len); 3779 } else { 3780 if (!scb->sg_len) { 3781 scb->cmd.dcdb.op_code = IPS_CMD_DCDB; 3782 } else { 3783 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG; 3784 scb->cmd.dcdb.enhanced_sg = 3785 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0; 3786 } 3787 3788 scb->dcdb.device_address = 3789 ((scb->bus - 1) << 4) | scb->target_id; 3790 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED; 3791 3792 if (TimeOut) { 3793 if (TimeOut < (10 * HZ)) 3794 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */ 3795 else if (TimeOut < (60 * HZ)) 3796 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */ 3797 else if (TimeOut < (1200 * HZ)) 3798 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */ 3799 } 3800 3801 scb->dcdb.transfer_length = scb->data_len; 3802 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K) 3803 scb->dcdb.transfer_length = 0; 3804 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG) 3805 scb->dcdb.buffer_pointer = 3806 cpu_to_le32(scb->sg_busaddr); 3807 else 3808 scb->dcdb.buffer_pointer = 3809 cpu_to_le32(scb->data_busaddr); 3810 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len; 3811 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info); 3812 scb->dcdb.sg_count = scb->sg_len; 3813 scb->dcdb.reserved = 0; 3814 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd, 3815 scb->scsi_cmd->cmd_len); 3816 scb->dcdb.scsi_status = 0; 3817 scb->dcdb.reserved2[0] = 0; 3818 scb->dcdb.reserved2[1] = 0; 3819 scb->dcdb.reserved2[2] = 0; 3820 } 3821 } 3822 3823 return ((*ha->func.issue) (ha, scb)); 3824 } 3825 3826 /****************************************************************************/ 3827 /* */ 3828 /* Routine Name: ips_chk_status */ 3829 /* */ 3830 /* Routine Description: */ 3831 /* */ 3832 /* Check the status of commands to logical drives */ 3833 /* Assumed to be called with the HA lock */ 3834 /****************************************************************************/ 3835 static void 3836 ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus) 3837 { 3838 ips_scb_t *scb; 3839 ips_stat_t *sp; 3840 uint8_t basic_status; 3841 uint8_t ext_status; 3842 int errcode; 3843 IPS_SCSI_INQ_DATA inquiryData; 3844 3845 METHOD_TRACE("ips_chkstatus", 1); 3846 3847 scb = &ha->scbs[pstatus->fields.command_id]; 3848 scb->basic_status = basic_status = 3849 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK; 3850 scb->extended_status = ext_status = pstatus->fields.extended_status; 3851 3852 sp = &ha->sp; 3853 sp->residue_len = 0; 3854 sp->scb_addr = (void *) scb; 3855 3856 /* Remove the item from the active queue */ 3857 ips_removeq_scb(&ha->scb_activelist, scb); 3858 3859 if (!scb->scsi_cmd) 3860 /* internal commands are handled in do_ipsintr */ 3861 return; 3862 3863 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)", 3864 ips_name, 3865 ha->host_num, 3866 scb->cdb[0], 3867 scb->cmd.basic_io.command_id, 3868 scb->bus, scb->target_id, scb->lun); 3869 3870 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) 3871 /* passthru - just returns the raw result */ 3872 return; 3873 3874 errcode = DID_OK; 3875 3876 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) || 3877 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) { 3878 3879 if (scb->bus == 0) { 3880 if ((basic_status & IPS_GSC_STATUS_MASK) == 3881 IPS_CMD_RECOVERED_ERROR) { 3882 DEBUG_VAR(1, 3883 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 3884 ips_name, ha->host_num, 3885 scb->cmd.basic_io.op_code, 3886 basic_status, ext_status); 3887 } 3888 3889 switch (scb->scsi_cmd->cmnd[0]) { 3890 case ALLOW_MEDIUM_REMOVAL: 3891 case REZERO_UNIT: 3892 case ERASE: 3893 case WRITE_FILEMARKS: 3894 case SPACE: 3895 errcode = DID_ERROR; 3896 break; 3897 3898 case START_STOP: 3899 break; 3900 3901 case TEST_UNIT_READY: 3902 if (!ips_online(ha, scb)) { 3903 errcode = DID_TIME_OUT; 3904 } 3905 break; 3906 3907 case INQUIRY: 3908 if (ips_online(ha, scb)) { 3909 ips_inquiry(ha, scb); 3910 } else { 3911 errcode = DID_TIME_OUT; 3912 } 3913 break; 3914 3915 case REQUEST_SENSE: 3916 ips_reqsen(ha, scb); 3917 break; 3918 3919 case READ_6: 3920 case WRITE_6: 3921 case READ_10: 3922 case WRITE_10: 3923 case RESERVE: 3924 case RELEASE: 3925 break; 3926 3927 case MODE_SENSE: 3928 if (!ips_online(ha, scb) 3929 || !ips_msense(ha, scb)) { 3930 errcode = DID_ERROR; 3931 } 3932 break; 3933 3934 case READ_CAPACITY: 3935 if (ips_online(ha, scb)) 3936 ips_rdcap(ha, scb); 3937 else { 3938 errcode = DID_TIME_OUT; 3939 } 3940 break; 3941 3942 case SEND_DIAGNOSTIC: 3943 case REASSIGN_BLOCKS: 3944 break; 3945 3946 case FORMAT_UNIT: 3947 errcode = DID_ERROR; 3948 break; 3949 3950 case SEEK_10: 3951 case VERIFY: 3952 case READ_DEFECT_DATA: 3953 case READ_BUFFER: 3954 case WRITE_BUFFER: 3955 break; 3956 3957 default: 3958 errcode = DID_ERROR; 3959 } /* end switch */ 3960 3961 scb->scsi_cmd->result = errcode << 16; 3962 } else { /* bus == 0 */ 3963 /* restrict access to physical drives */ 3964 if (scb->scsi_cmd->cmnd[0] == INQUIRY) { 3965 ips_scmd_buf_read(scb->scsi_cmd, 3966 &inquiryData, sizeof (inquiryData)); 3967 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) 3968 scb->scsi_cmd->result = DID_TIME_OUT << 16; 3969 } 3970 } /* else */ 3971 } else { /* recovered error / success */ 3972 if (scb->bus == 0) { 3973 DEBUG_VAR(1, 3974 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x", 3975 ips_name, ha->host_num, 3976 scb->cmd.basic_io.op_code, basic_status, 3977 ext_status); 3978 } 3979 3980 ips_map_status(ha, scb, sp); 3981 } /* else */ 3982 } 3983 3984 /****************************************************************************/ 3985 /* */ 3986 /* Routine Name: ips_online */ 3987 /* */ 3988 /* Routine Description: */ 3989 /* */ 3990 /* Determine if a logical drive is online */ 3991 /* */ 3992 /****************************************************************************/ 3993 static int 3994 ips_online(ips_ha_t * ha, ips_scb_t * scb) 3995 { 3996 METHOD_TRACE("ips_online", 1); 3997 3998 if (scb->target_id >= IPS_MAX_LD) 3999 return (0); 4000 4001 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) { 4002 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO)); 4003 return (0); 4004 } 4005 4006 if (ha->logical_drive_info->drive_info[scb->target_id].state != 4007 IPS_LD_OFFLINE 4008 && ha->logical_drive_info->drive_info[scb->target_id].state != 4009 IPS_LD_FREE 4010 && ha->logical_drive_info->drive_info[scb->target_id].state != 4011 IPS_LD_CRS 4012 && ha->logical_drive_info->drive_info[scb->target_id].state != 4013 IPS_LD_SYS) 4014 return (1); 4015 else 4016 return (0); 4017 } 4018 4019 /****************************************************************************/ 4020 /* */ 4021 /* Routine Name: ips_inquiry */ 4022 /* */ 4023 /* Routine Description: */ 4024 /* */ 4025 /* Simulate an inquiry command to a logical drive */ 4026 /* */ 4027 /****************************************************************************/ 4028 static int 4029 ips_inquiry(ips_ha_t * ha, ips_scb_t * scb) 4030 { 4031 IPS_SCSI_INQ_DATA inquiry; 4032 4033 METHOD_TRACE("ips_inquiry", 1); 4034 4035 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA)); 4036 4037 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD; 4038 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED; 4039 inquiry.Version = IPS_SCSI_INQ_REV2; 4040 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2; 4041 inquiry.AdditionalLength = 31; 4042 inquiry.Flags[0] = IPS_SCSI_INQ_Address16; 4043 inquiry.Flags[1] = 4044 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue; 4045 memcpy(inquiry.VendorId, "IBM ", 8); 4046 memcpy(inquiry.ProductId, "SERVERAID ", 16); 4047 memcpy(inquiry.ProductRevisionLevel, "1.00", 4); 4048 4049 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry)); 4050 4051 return (1); 4052 } 4053 4054 /****************************************************************************/ 4055 /* */ 4056 /* Routine Name: ips_rdcap */ 4057 /* */ 4058 /* Routine Description: */ 4059 /* */ 4060 /* Simulate a read capacity command to a logical drive */ 4061 /* */ 4062 /****************************************************************************/ 4063 static int 4064 ips_rdcap(ips_ha_t * ha, ips_scb_t * scb) 4065 { 4066 IPS_SCSI_CAPACITY cap; 4067 4068 METHOD_TRACE("ips_rdcap", 1); 4069 4070 if (scsi_bufflen(scb->scsi_cmd) < 8) 4071 return (0); 4072 4073 cap.lba = 4074 cpu_to_be32(le32_to_cpu 4075 (ha->logical_drive_info-> 4076 drive_info[scb->target_id].sector_count) - 1); 4077 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE); 4078 4079 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap)); 4080 4081 return (1); 4082 } 4083 4084 /****************************************************************************/ 4085 /* */ 4086 /* Routine Name: ips_msense */ 4087 /* */ 4088 /* Routine Description: */ 4089 /* */ 4090 /* Simulate a mode sense command to a logical drive */ 4091 /* */ 4092 /****************************************************************************/ 4093 static int 4094 ips_msense(ips_ha_t * ha, ips_scb_t * scb) 4095 { 4096 uint16_t heads; 4097 uint16_t sectors; 4098 uint32_t cylinders; 4099 IPS_SCSI_MODE_PAGE_DATA mdata; 4100 4101 METHOD_TRACE("ips_msense", 1); 4102 4103 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 && 4104 (ha->enq->ucMiscFlag & 0x8) == 0) { 4105 heads = IPS_NORM_HEADS; 4106 sectors = IPS_NORM_SECTORS; 4107 } else { 4108 heads = IPS_COMP_HEADS; 4109 sectors = IPS_COMP_SECTORS; 4110 } 4111 4112 cylinders = 4113 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) - 4114 1) / (heads * sectors); 4115 4116 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA)); 4117 4118 mdata.hdr.BlockDescLength = 8; 4119 4120 switch (scb->scsi_cmd->cmnd[2] & 0x3f) { 4121 case 0x03: /* page 3 */ 4122 mdata.pdata.pg3.PageCode = 3; 4123 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3); 4124 mdata.hdr.DataLength = 4125 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength; 4126 mdata.pdata.pg3.TracksPerZone = 0; 4127 mdata.pdata.pg3.AltSectorsPerZone = 0; 4128 mdata.pdata.pg3.AltTracksPerZone = 0; 4129 mdata.pdata.pg3.AltTracksPerVolume = 0; 4130 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors); 4131 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE); 4132 mdata.pdata.pg3.Interleave = cpu_to_be16(1); 4133 mdata.pdata.pg3.TrackSkew = 0; 4134 mdata.pdata.pg3.CylinderSkew = 0; 4135 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector; 4136 break; 4137 4138 case 0x4: 4139 mdata.pdata.pg4.PageCode = 4; 4140 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4); 4141 mdata.hdr.DataLength = 4142 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength; 4143 mdata.pdata.pg4.CylindersHigh = 4144 cpu_to_be16((cylinders >> 8) & 0xFFFF); 4145 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF); 4146 mdata.pdata.pg4.Heads = heads; 4147 mdata.pdata.pg4.WritePrecompHigh = 0; 4148 mdata.pdata.pg4.WritePrecompLow = 0; 4149 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0; 4150 mdata.pdata.pg4.ReducedWriteCurrentLow = 0; 4151 mdata.pdata.pg4.StepRate = cpu_to_be16(1); 4152 mdata.pdata.pg4.LandingZoneHigh = 0; 4153 mdata.pdata.pg4.LandingZoneLow = 0; 4154 mdata.pdata.pg4.flags = 0; 4155 mdata.pdata.pg4.RotationalOffset = 0; 4156 mdata.pdata.pg4.MediumRotationRate = 0; 4157 break; 4158 case 0x8: 4159 mdata.pdata.pg8.PageCode = 8; 4160 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8); 4161 mdata.hdr.DataLength = 4162 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength; 4163 /* everything else is left set to 0 */ 4164 break; 4165 4166 default: 4167 return (0); 4168 } /* end switch */ 4169 4170 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata)); 4171 4172 return (1); 4173 } 4174 4175 /****************************************************************************/ 4176 /* */ 4177 /* Routine Name: ips_reqsen */ 4178 /* */ 4179 /* Routine Description: */ 4180 /* */ 4181 /* Simulate a request sense command to a logical drive */ 4182 /* */ 4183 /****************************************************************************/ 4184 static int 4185 ips_reqsen(ips_ha_t * ha, ips_scb_t * scb) 4186 { 4187 IPS_SCSI_REQSEN reqsen; 4188 4189 METHOD_TRACE("ips_reqsen", 1); 4190 4191 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN)); 4192 4193 reqsen.ResponseCode = 4194 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR; 4195 reqsen.AdditionalLength = 10; 4196 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE; 4197 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE; 4198 4199 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen)); 4200 4201 return (1); 4202 } 4203 4204 /****************************************************************************/ 4205 /* */ 4206 /* Routine Name: ips_free */ 4207 /* */ 4208 /* Routine Description: */ 4209 /* */ 4210 /* Free any allocated space for this controller */ 4211 /* */ 4212 /****************************************************************************/ 4213 static void 4214 ips_free(ips_ha_t * ha) 4215 { 4216 4217 METHOD_TRACE("ips_free", 1); 4218 4219 if (ha) { 4220 if (ha->enq) { 4221 dma_free_coherent(&ha->pcidev->dev, sizeof(IPS_ENQ), 4222 ha->enq, ha->enq_busaddr); 4223 ha->enq = NULL; 4224 } 4225 4226 kfree(ha->conf); 4227 ha->conf = NULL; 4228 4229 if (ha->adapt) { 4230 dma_free_coherent(&ha->pcidev->dev, 4231 sizeof (IPS_ADAPTER) + 4232 sizeof (IPS_IO_CMD), ha->adapt, 4233 ha->adapt->hw_status_start); 4234 ha->adapt = NULL; 4235 } 4236 4237 if (ha->logical_drive_info) { 4238 dma_free_coherent(&ha->pcidev->dev, 4239 sizeof (IPS_LD_INFO), 4240 ha->logical_drive_info, 4241 ha->logical_drive_info_dma_addr); 4242 ha->logical_drive_info = NULL; 4243 } 4244 4245 kfree(ha->nvram); 4246 ha->nvram = NULL; 4247 4248 kfree(ha->subsys); 4249 ha->subsys = NULL; 4250 4251 if (ha->ioctl_data) { 4252 dma_free_coherent(&ha->pcidev->dev, ha->ioctl_len, 4253 ha->ioctl_data, ha->ioctl_busaddr); 4254 ha->ioctl_data = NULL; 4255 ha->ioctl_datasize = 0; 4256 ha->ioctl_len = 0; 4257 } 4258 ips_deallocatescbs(ha, ha->max_cmds); 4259 4260 /* free memory mapped (if applicable) */ 4261 if (ha->mem_ptr) { 4262 iounmap(ha->ioremap_ptr); 4263 ha->ioremap_ptr = NULL; 4264 ha->mem_ptr = NULL; 4265 } 4266 4267 ha->mem_addr = 0; 4268 4269 } 4270 } 4271 4272 /****************************************************************************/ 4273 /* */ 4274 /* Routine Name: ips_deallocatescbs */ 4275 /* */ 4276 /* Routine Description: */ 4277 /* */ 4278 /* Free the command blocks */ 4279 /* */ 4280 /****************************************************************************/ 4281 static int 4282 ips_deallocatescbs(ips_ha_t * ha, int cmds) 4283 { 4284 if (ha->scbs) { 4285 dma_free_coherent(&ha->pcidev->dev, 4286 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds, 4287 ha->scbs->sg_list.list, 4288 ha->scbs->sg_busaddr); 4289 dma_free_coherent(&ha->pcidev->dev, sizeof (ips_scb_t) * cmds, 4290 ha->scbs, ha->scbs->scb_busaddr); 4291 ha->scbs = NULL; 4292 } /* end if */ 4293 return 1; 4294 } 4295 4296 /****************************************************************************/ 4297 /* */ 4298 /* Routine Name: ips_allocatescbs */ 4299 /* */ 4300 /* Routine Description: */ 4301 /* */ 4302 /* Allocate the command blocks */ 4303 /* */ 4304 /****************************************************************************/ 4305 static int 4306 ips_allocatescbs(ips_ha_t * ha) 4307 { 4308 ips_scb_t *scb_p; 4309 IPS_SG_LIST ips_sg; 4310 int i; 4311 dma_addr_t command_dma, sg_dma; 4312 4313 METHOD_TRACE("ips_allocatescbs", 1); 4314 4315 /* Allocate memory for the SCBs */ 4316 ha->scbs = dma_alloc_coherent(&ha->pcidev->dev, 4317 ha->max_cmds * sizeof (ips_scb_t), 4318 &command_dma, GFP_KERNEL); 4319 if (ha->scbs == NULL) 4320 return 0; 4321 ips_sg.list = dma_alloc_coherent(&ha->pcidev->dev, 4322 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * ha->max_cmds, 4323 &sg_dma, GFP_KERNEL); 4324 if (ips_sg.list == NULL) { 4325 dma_free_coherent(&ha->pcidev->dev, 4326 ha->max_cmds * sizeof (ips_scb_t), ha->scbs, 4327 command_dma); 4328 return 0; 4329 } 4330 4331 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t)); 4332 4333 for (i = 0; i < ha->max_cmds; i++) { 4334 scb_p = &ha->scbs[i]; 4335 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i; 4336 /* set up S/G list */ 4337 if (IPS_USE_ENH_SGLIST(ha)) { 4338 scb_p->sg_list.enh_list = 4339 ips_sg.enh_list + i * IPS_MAX_SG; 4340 scb_p->sg_busaddr = 4341 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4342 } else { 4343 scb_p->sg_list.std_list = 4344 ips_sg.std_list + i * IPS_MAX_SG; 4345 scb_p->sg_busaddr = 4346 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i; 4347 } 4348 4349 /* add to the free list */ 4350 if (i < ha->max_cmds - 1) { 4351 scb_p->q_next = ha->scb_freelist; 4352 ha->scb_freelist = scb_p; 4353 } 4354 } 4355 4356 /* success */ 4357 return (1); 4358 } 4359 4360 /****************************************************************************/ 4361 /* */ 4362 /* Routine Name: ips_init_scb */ 4363 /* */ 4364 /* Routine Description: */ 4365 /* */ 4366 /* Initialize a CCB to default values */ 4367 /* */ 4368 /****************************************************************************/ 4369 static void 4370 ips_init_scb(ips_ha_t * ha, ips_scb_t * scb) 4371 { 4372 IPS_SG_LIST sg_list; 4373 uint32_t cmd_busaddr, sg_busaddr; 4374 METHOD_TRACE("ips_init_scb", 1); 4375 4376 if (scb == NULL) 4377 return; 4378 4379 sg_list.list = scb->sg_list.list; 4380 cmd_busaddr = scb->scb_busaddr; 4381 sg_busaddr = scb->sg_busaddr; 4382 /* zero fill */ 4383 memset(scb, 0, sizeof (ips_scb_t)); 4384 memset(ha->dummy, 0, sizeof (IPS_IO_CMD)); 4385 4386 /* Initialize dummy command bucket */ 4387 ha->dummy->op_code = 0xFF; 4388 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start 4389 + sizeof (IPS_ADAPTER)); 4390 ha->dummy->command_id = IPS_MAX_CMDS; 4391 4392 /* set bus address of scb */ 4393 scb->scb_busaddr = cmd_busaddr; 4394 scb->sg_busaddr = sg_busaddr; 4395 scb->sg_list.list = sg_list.list; 4396 4397 /* Neptune Fix */ 4398 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE); 4399 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start 4400 + sizeof (IPS_ADAPTER)); 4401 } 4402 4403 /****************************************************************************/ 4404 /* */ 4405 /* Routine Name: ips_get_scb */ 4406 /* */ 4407 /* Routine Description: */ 4408 /* */ 4409 /* Initialize a CCB to default values */ 4410 /* */ 4411 /* ASSUMED to be called from within a lock */ 4412 /* */ 4413 /****************************************************************************/ 4414 static ips_scb_t * 4415 ips_getscb(ips_ha_t * ha) 4416 { 4417 ips_scb_t *scb; 4418 4419 METHOD_TRACE("ips_getscb", 1); 4420 4421 if ((scb = ha->scb_freelist) == NULL) { 4422 4423 return (NULL); 4424 } 4425 4426 ha->scb_freelist = scb->q_next; 4427 scb->flags = 0; 4428 scb->q_next = NULL; 4429 4430 ips_init_scb(ha, scb); 4431 4432 return (scb); 4433 } 4434 4435 /****************************************************************************/ 4436 /* */ 4437 /* Routine Name: ips_free_scb */ 4438 /* */ 4439 /* Routine Description: */ 4440 /* */ 4441 /* Return an unused CCB back to the free list */ 4442 /* */ 4443 /* ASSUMED to be called from within a lock */ 4444 /* */ 4445 /****************************************************************************/ 4446 static void 4447 ips_freescb(ips_ha_t * ha, ips_scb_t * scb) 4448 { 4449 4450 METHOD_TRACE("ips_freescb", 1); 4451 if (scb->flags & IPS_SCB_MAP_SG) 4452 scsi_dma_unmap(scb->scsi_cmd); 4453 else if (scb->flags & IPS_SCB_MAP_SINGLE) 4454 dma_unmap_single(&ha->pcidev->dev, scb->data_busaddr, 4455 scb->data_len, IPS_DMA_DIR(scb)); 4456 4457 /* check to make sure this is not our "special" scb */ 4458 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) { 4459 scb->q_next = ha->scb_freelist; 4460 ha->scb_freelist = scb; 4461 } 4462 } 4463 4464 /****************************************************************************/ 4465 /* */ 4466 /* Routine Name: ips_isinit_copperhead */ 4467 /* */ 4468 /* Routine Description: */ 4469 /* */ 4470 /* Is controller initialized ? */ 4471 /* */ 4472 /****************************************************************************/ 4473 static int 4474 ips_isinit_copperhead(ips_ha_t * ha) 4475 { 4476 uint8_t scpr; 4477 uint8_t isr; 4478 4479 METHOD_TRACE("ips_isinit_copperhead", 1); 4480 4481 isr = inb(ha->io_addr + IPS_REG_HISR); 4482 scpr = inb(ha->io_addr + IPS_REG_SCPR); 4483 4484 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4485 return (0); 4486 else 4487 return (1); 4488 } 4489 4490 /****************************************************************************/ 4491 /* */ 4492 /* Routine Name: ips_isinit_copperhead_memio */ 4493 /* */ 4494 /* Routine Description: */ 4495 /* */ 4496 /* Is controller initialized ? */ 4497 /* */ 4498 /****************************************************************************/ 4499 static int 4500 ips_isinit_copperhead_memio(ips_ha_t * ha) 4501 { 4502 uint8_t isr = 0; 4503 uint8_t scpr; 4504 4505 METHOD_TRACE("ips_is_init_copperhead_memio", 1); 4506 4507 isr = readb(ha->mem_ptr + IPS_REG_HISR); 4508 scpr = readb(ha->mem_ptr + IPS_REG_SCPR); 4509 4510 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0)) 4511 return (0); 4512 else 4513 return (1); 4514 } 4515 4516 /****************************************************************************/ 4517 /* */ 4518 /* Routine Name: ips_isinit_morpheus */ 4519 /* */ 4520 /* Routine Description: */ 4521 /* */ 4522 /* Is controller initialized ? */ 4523 /* */ 4524 /****************************************************************************/ 4525 static int 4526 ips_isinit_morpheus(ips_ha_t * ha) 4527 { 4528 uint32_t post; 4529 uint32_t bits; 4530 4531 METHOD_TRACE("ips_is_init_morpheus", 1); 4532 4533 if (ips_isintr_morpheus(ha)) 4534 ips_flush_and_reset(ha); 4535 4536 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4537 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4538 4539 if (post == 0) 4540 return (0); 4541 else if (bits & 0x3) 4542 return (0); 4543 else 4544 return (1); 4545 } 4546 4547 /****************************************************************************/ 4548 /* */ 4549 /* Routine Name: ips_flush_and_reset */ 4550 /* */ 4551 /* Routine Description: */ 4552 /* */ 4553 /* Perform cleanup ( FLUSH and RESET ) when the adapter is in an unknown */ 4554 /* state ( was trying to INIT and an interrupt was already pending ) ... */ 4555 /* */ 4556 /****************************************************************************/ 4557 static void 4558 ips_flush_and_reset(ips_ha_t *ha) 4559 { 4560 ips_scb_t *scb; 4561 int ret; 4562 int time; 4563 int done; 4564 dma_addr_t command_dma; 4565 4566 /* Create a usuable SCB */ 4567 scb = dma_alloc_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), 4568 &command_dma, GFP_KERNEL); 4569 if (scb) { 4570 memset(scb, 0, sizeof(ips_scb_t)); 4571 ips_init_scb(ha, scb); 4572 scb->scb_busaddr = command_dma; 4573 4574 scb->timeout = ips_cmd_timeout; 4575 scb->cdb[0] = IPS_CMD_FLUSH; 4576 4577 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH; 4578 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS; /* Use an ID that would otherwise not exist */ 4579 scb->cmd.flush_cache.state = IPS_NORM_STATE; 4580 scb->cmd.flush_cache.reserved = 0; 4581 scb->cmd.flush_cache.reserved2 = 0; 4582 scb->cmd.flush_cache.reserved3 = 0; 4583 scb->cmd.flush_cache.reserved4 = 0; 4584 4585 ret = ips_send_cmd(ha, scb); /* Send the Flush Command */ 4586 4587 if (ret == IPS_SUCCESS) { 4588 time = 60 * IPS_ONE_SEC; /* Max Wait time is 60 seconds */ 4589 done = 0; 4590 4591 while ((time > 0) && (!done)) { 4592 done = ips_poll_for_flush_complete(ha); 4593 /* This may look evil, but it's only done during extremely rare start-up conditions ! */ 4594 udelay(1000); 4595 time--; 4596 } 4597 } 4598 } 4599 4600 /* Now RESET and INIT the adapter */ 4601 (*ha->func.reset) (ha); 4602 4603 dma_free_coherent(&ha->pcidev->dev, sizeof(ips_scb_t), scb, command_dma); 4604 return; 4605 } 4606 4607 /****************************************************************************/ 4608 /* */ 4609 /* Routine Name: ips_poll_for_flush_complete */ 4610 /* */ 4611 /* Routine Description: */ 4612 /* */ 4613 /* Poll for the Flush Command issued by ips_flush_and_reset() to complete */ 4614 /* All other responses are just taken off the queue and ignored */ 4615 /* */ 4616 /****************************************************************************/ 4617 static int 4618 ips_poll_for_flush_complete(ips_ha_t * ha) 4619 { 4620 IPS_STATUS cstatus; 4621 4622 while (TRUE) { 4623 cstatus.value = (*ha->func.statupd) (ha); 4624 4625 if (cstatus.value == 0xffffffff) /* If No Interrupt to process */ 4626 break; 4627 4628 /* Success is when we see the Flush Command ID */ 4629 if (cstatus.fields.command_id == IPS_MAX_CMDS) 4630 return 1; 4631 } 4632 4633 return 0; 4634 } 4635 4636 /****************************************************************************/ 4637 /* */ 4638 /* Routine Name: ips_enable_int_copperhead */ 4639 /* */ 4640 /* Routine Description: */ 4641 /* Turn on interrupts */ 4642 /* */ 4643 /****************************************************************************/ 4644 static void 4645 ips_enable_int_copperhead(ips_ha_t * ha) 4646 { 4647 METHOD_TRACE("ips_enable_int_copperhead", 1); 4648 4649 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI); 4650 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4651 } 4652 4653 /****************************************************************************/ 4654 /* */ 4655 /* Routine Name: ips_enable_int_copperhead_memio */ 4656 /* */ 4657 /* Routine Description: */ 4658 /* Turn on interrupts */ 4659 /* */ 4660 /****************************************************************************/ 4661 static void 4662 ips_enable_int_copperhead_memio(ips_ha_t * ha) 4663 { 4664 METHOD_TRACE("ips_enable_int_copperhead_memio", 1); 4665 4666 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4667 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/ 4668 } 4669 4670 /****************************************************************************/ 4671 /* */ 4672 /* Routine Name: ips_enable_int_morpheus */ 4673 /* */ 4674 /* Routine Description: */ 4675 /* Turn on interrupts */ 4676 /* */ 4677 /****************************************************************************/ 4678 static void 4679 ips_enable_int_morpheus(ips_ha_t * ha) 4680 { 4681 uint32_t Oimr; 4682 4683 METHOD_TRACE("ips_enable_int_morpheus", 1); 4684 4685 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4686 Oimr &= ~0x08; 4687 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4688 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/ 4689 } 4690 4691 /****************************************************************************/ 4692 /* */ 4693 /* Routine Name: ips_init_copperhead */ 4694 /* */ 4695 /* Routine Description: */ 4696 /* */ 4697 /* Initialize a copperhead controller */ 4698 /* */ 4699 /****************************************************************************/ 4700 static int 4701 ips_init_copperhead(ips_ha_t * ha) 4702 { 4703 uint8_t Isr; 4704 uint8_t Cbsp; 4705 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4706 int i, j; 4707 4708 METHOD_TRACE("ips_init_copperhead", 1); 4709 4710 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4711 for (j = 0; j < 45; j++) { 4712 Isr = inb(ha->io_addr + IPS_REG_HISR); 4713 if (Isr & IPS_BIT_GHI) 4714 break; 4715 4716 /* Delay for 1 Second */ 4717 MDELAY(IPS_ONE_SEC); 4718 } 4719 4720 if (j >= 45) 4721 /* error occurred */ 4722 return (0); 4723 4724 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR); 4725 outb(Isr, ha->io_addr + IPS_REG_HISR); 4726 } 4727 4728 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 4729 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4730 "reset controller fails (post status %x %x).\n", 4731 PostByte[0], PostByte[1]); 4732 4733 return (0); 4734 } 4735 4736 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 4737 for (j = 0; j < 240; j++) { 4738 Isr = inb(ha->io_addr + IPS_REG_HISR); 4739 if (Isr & IPS_BIT_GHI) 4740 break; 4741 4742 /* Delay for 1 Second */ 4743 MDELAY(IPS_ONE_SEC); 4744 } 4745 4746 if (j >= 240) 4747 /* error occurred */ 4748 return (0); 4749 4750 inb(ha->io_addr + IPS_REG_ISPR); 4751 outb(Isr, ha->io_addr + IPS_REG_HISR); 4752 } 4753 4754 for (i = 0; i < 240; i++) { 4755 Cbsp = inb(ha->io_addr + IPS_REG_CBSP); 4756 4757 if ((Cbsp & IPS_BIT_OP) == 0) 4758 break; 4759 4760 /* Delay for 1 Second */ 4761 MDELAY(IPS_ONE_SEC); 4762 } 4763 4764 if (i >= 240) 4765 /* reset failed */ 4766 return (0); 4767 4768 /* setup CCCR */ 4769 outl(0x1010, ha->io_addr + IPS_REG_CCCR); 4770 4771 /* Enable busmastering */ 4772 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR); 4773 4774 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 4775 /* fix for anaconda64 */ 4776 outl(0, ha->io_addr + IPS_REG_NDAE); 4777 4778 /* Enable interrupts */ 4779 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR); 4780 4781 return (1); 4782 } 4783 4784 /****************************************************************************/ 4785 /* */ 4786 /* Routine Name: ips_init_copperhead_memio */ 4787 /* */ 4788 /* Routine Description: */ 4789 /* */ 4790 /* Initialize a copperhead controller with memory mapped I/O */ 4791 /* */ 4792 /****************************************************************************/ 4793 static int 4794 ips_init_copperhead_memio(ips_ha_t * ha) 4795 { 4796 uint8_t Isr = 0; 4797 uint8_t Cbsp; 4798 uint8_t PostByte[IPS_MAX_POST_BYTES]; 4799 int i, j; 4800 4801 METHOD_TRACE("ips_init_copperhead_memio", 1); 4802 4803 for (i = 0; i < IPS_MAX_POST_BYTES; i++) { 4804 for (j = 0; j < 45; j++) { 4805 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 4806 if (Isr & IPS_BIT_GHI) 4807 break; 4808 4809 /* Delay for 1 Second */ 4810 MDELAY(IPS_ONE_SEC); 4811 } 4812 4813 if (j >= 45) 4814 /* error occurred */ 4815 return (0); 4816 4817 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR); 4818 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 4819 } 4820 4821 if (PostByte[0] < IPS_GOOD_POST_STATUS) { 4822 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4823 "reset controller fails (post status %x %x).\n", 4824 PostByte[0], PostByte[1]); 4825 4826 return (0); 4827 } 4828 4829 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) { 4830 for (j = 0; j < 240; j++) { 4831 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 4832 if (Isr & IPS_BIT_GHI) 4833 break; 4834 4835 /* Delay for 1 Second */ 4836 MDELAY(IPS_ONE_SEC); 4837 } 4838 4839 if (j >= 240) 4840 /* error occurred */ 4841 return (0); 4842 4843 readb(ha->mem_ptr + IPS_REG_ISPR); 4844 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 4845 } 4846 4847 for (i = 0; i < 240; i++) { 4848 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP); 4849 4850 if ((Cbsp & IPS_BIT_OP) == 0) 4851 break; 4852 4853 /* Delay for 1 Second */ 4854 MDELAY(IPS_ONE_SEC); 4855 } 4856 4857 if (i >= 240) 4858 /* error occurred */ 4859 return (0); 4860 4861 /* setup CCCR */ 4862 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR); 4863 4864 /* Enable busmastering */ 4865 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR); 4866 4867 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 4868 /* fix for anaconda64 */ 4869 writel(0, ha->mem_ptr + IPS_REG_NDAE); 4870 4871 /* Enable interrupts */ 4872 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR); 4873 4874 /* if we get here then everything went OK */ 4875 return (1); 4876 } 4877 4878 /****************************************************************************/ 4879 /* */ 4880 /* Routine Name: ips_init_morpheus */ 4881 /* */ 4882 /* Routine Description: */ 4883 /* */ 4884 /* Initialize a morpheus controller */ 4885 /* */ 4886 /****************************************************************************/ 4887 static int 4888 ips_init_morpheus(ips_ha_t * ha) 4889 { 4890 uint32_t Post; 4891 uint32_t Config; 4892 uint32_t Isr; 4893 uint32_t Oimr; 4894 int i; 4895 4896 METHOD_TRACE("ips_init_morpheus", 1); 4897 4898 /* Wait up to 45 secs for Post */ 4899 for (i = 0; i < 45; i++) { 4900 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4901 4902 if (Isr & IPS_BIT_I960_MSG0I) 4903 break; 4904 4905 /* Delay for 1 Second */ 4906 MDELAY(IPS_ONE_SEC); 4907 } 4908 4909 if (i >= 45) { 4910 /* error occurred */ 4911 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4912 "timeout waiting for post.\n"); 4913 4914 return (0); 4915 } 4916 4917 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4918 4919 if (Post == 0x4F00) { /* If Flashing the Battery PIC */ 4920 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4921 "Flashing Battery PIC, Please wait ...\n"); 4922 4923 /* Clear the interrupt bit */ 4924 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 4925 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4926 4927 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */ 4928 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0); 4929 if (Post != 0x4F00) 4930 break; 4931 /* Delay for 1 Second */ 4932 MDELAY(IPS_ONE_SEC); 4933 } 4934 4935 if (i >= 120) { 4936 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4937 "timeout waiting for Battery PIC Flash\n"); 4938 return (0); 4939 } 4940 4941 } 4942 4943 /* Clear the interrupt bit */ 4944 Isr = (uint32_t) IPS_BIT_I960_MSG0I; 4945 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4946 4947 if (Post < (IPS_GOOD_POST_STATUS << 8)) { 4948 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4949 "reset controller fails (post status %x).\n", Post); 4950 4951 return (0); 4952 } 4953 4954 /* Wait up to 240 secs for config bytes */ 4955 for (i = 0; i < 240; i++) { 4956 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 4957 4958 if (Isr & IPS_BIT_I960_MSG1I) 4959 break; 4960 4961 /* Delay for 1 Second */ 4962 MDELAY(IPS_ONE_SEC); 4963 } 4964 4965 if (i >= 240) { 4966 /* error occurred */ 4967 IPS_PRINTK(KERN_WARNING, ha->pcidev, 4968 "timeout waiting for config.\n"); 4969 4970 return (0); 4971 } 4972 4973 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 4974 4975 /* Clear interrupt bit */ 4976 Isr = (uint32_t) IPS_BIT_I960_MSG1I; 4977 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR); 4978 4979 /* Turn on the interrupts */ 4980 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR); 4981 Oimr &= ~0x8; 4982 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR); 4983 4984 /* if we get here then everything went OK */ 4985 4986 /* Since we did a RESET, an EraseStripeLock may be needed */ 4987 if (Post == 0xEF10) { 4988 if ((Config == 0x000F) || (Config == 0x0009)) 4989 ha->requires_esl = 1; 4990 } 4991 4992 return (1); 4993 } 4994 4995 /****************************************************************************/ 4996 /* */ 4997 /* Routine Name: ips_reset_copperhead */ 4998 /* */ 4999 /* Routine Description: */ 5000 /* */ 5001 /* Reset the controller */ 5002 /* */ 5003 /****************************************************************************/ 5004 static int 5005 ips_reset_copperhead(ips_ha_t * ha) 5006 { 5007 int reset_counter; 5008 5009 METHOD_TRACE("ips_reset_copperhead", 1); 5010 5011 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d", 5012 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq); 5013 5014 reset_counter = 0; 5015 5016 while (reset_counter < 2) { 5017 reset_counter++; 5018 5019 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR); 5020 5021 /* Delay for 1 Second */ 5022 MDELAY(IPS_ONE_SEC); 5023 5024 outb(0, ha->io_addr + IPS_REG_SCPR); 5025 5026 /* Delay for 1 Second */ 5027 MDELAY(IPS_ONE_SEC); 5028 5029 if ((*ha->func.init) (ha)) 5030 break; 5031 else if (reset_counter >= 2) { 5032 5033 return (0); 5034 } 5035 } 5036 5037 return (1); 5038 } 5039 5040 /****************************************************************************/ 5041 /* */ 5042 /* Routine Name: ips_reset_copperhead_memio */ 5043 /* */ 5044 /* Routine Description: */ 5045 /* */ 5046 /* Reset the controller */ 5047 /* */ 5048 /****************************************************************************/ 5049 static int 5050 ips_reset_copperhead_memio(ips_ha_t * ha) 5051 { 5052 int reset_counter; 5053 5054 METHOD_TRACE("ips_reset_copperhead_memio", 1); 5055 5056 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d", 5057 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); 5058 5059 reset_counter = 0; 5060 5061 while (reset_counter < 2) { 5062 reset_counter++; 5063 5064 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR); 5065 5066 /* Delay for 1 Second */ 5067 MDELAY(IPS_ONE_SEC); 5068 5069 writeb(0, ha->mem_ptr + IPS_REG_SCPR); 5070 5071 /* Delay for 1 Second */ 5072 MDELAY(IPS_ONE_SEC); 5073 5074 if ((*ha->func.init) (ha)) 5075 break; 5076 else if (reset_counter >= 2) { 5077 5078 return (0); 5079 } 5080 } 5081 5082 return (1); 5083 } 5084 5085 /****************************************************************************/ 5086 /* */ 5087 /* Routine Name: ips_reset_morpheus */ 5088 /* */ 5089 /* Routine Description: */ 5090 /* */ 5091 /* Reset the controller */ 5092 /* */ 5093 /****************************************************************************/ 5094 static int 5095 ips_reset_morpheus(ips_ha_t * ha) 5096 { 5097 int reset_counter; 5098 uint8_t junk; 5099 5100 METHOD_TRACE("ips_reset_morpheus", 1); 5101 5102 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d", 5103 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq); 5104 5105 reset_counter = 0; 5106 5107 while (reset_counter < 2) { 5108 reset_counter++; 5109 5110 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR); 5111 5112 /* Delay for 5 Seconds */ 5113 MDELAY(5 * IPS_ONE_SEC); 5114 5115 /* Do a PCI config read to wait for adapter */ 5116 pci_read_config_byte(ha->pcidev, 4, &junk); 5117 5118 if ((*ha->func.init) (ha)) 5119 break; 5120 else if (reset_counter >= 2) { 5121 5122 return (0); 5123 } 5124 } 5125 5126 return (1); 5127 } 5128 5129 /****************************************************************************/ 5130 /* */ 5131 /* Routine Name: ips_statinit */ 5132 /* */ 5133 /* Routine Description: */ 5134 /* */ 5135 /* Initialize the status queues on the controller */ 5136 /* */ 5137 /****************************************************************************/ 5138 static void 5139 ips_statinit(ips_ha_t * ha) 5140 { 5141 uint32_t phys_status_start; 5142 5143 METHOD_TRACE("ips_statinit", 1); 5144 5145 ha->adapt->p_status_start = ha->adapt->status; 5146 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5147 ha->adapt->p_status_tail = ha->adapt->status; 5148 5149 phys_status_start = ha->adapt->hw_status_start; 5150 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR); 5151 outl(phys_status_start + IPS_STATUS_Q_SIZE, 5152 ha->io_addr + IPS_REG_SQER); 5153 outl(phys_status_start + IPS_STATUS_SIZE, 5154 ha->io_addr + IPS_REG_SQHR); 5155 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR); 5156 5157 ha->adapt->hw_status_tail = phys_status_start; 5158 } 5159 5160 /****************************************************************************/ 5161 /* */ 5162 /* Routine Name: ips_statinit_memio */ 5163 /* */ 5164 /* Routine Description: */ 5165 /* */ 5166 /* Initialize the status queues on the controller */ 5167 /* */ 5168 /****************************************************************************/ 5169 static void 5170 ips_statinit_memio(ips_ha_t * ha) 5171 { 5172 uint32_t phys_status_start; 5173 5174 METHOD_TRACE("ips_statinit_memio", 1); 5175 5176 ha->adapt->p_status_start = ha->adapt->status; 5177 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS; 5178 ha->adapt->p_status_tail = ha->adapt->status; 5179 5180 phys_status_start = ha->adapt->hw_status_start; 5181 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR); 5182 writel(phys_status_start + IPS_STATUS_Q_SIZE, 5183 ha->mem_ptr + IPS_REG_SQER); 5184 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR); 5185 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR); 5186 5187 ha->adapt->hw_status_tail = phys_status_start; 5188 } 5189 5190 /****************************************************************************/ 5191 /* */ 5192 /* Routine Name: ips_statupd_copperhead */ 5193 /* */ 5194 /* Routine Description: */ 5195 /* */ 5196 /* Remove an element from the status queue */ 5197 /* */ 5198 /****************************************************************************/ 5199 static uint32_t 5200 ips_statupd_copperhead(ips_ha_t * ha) 5201 { 5202 METHOD_TRACE("ips_statupd_copperhead", 1); 5203 5204 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5205 ha->adapt->p_status_tail++; 5206 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5207 } else { 5208 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5209 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5210 } 5211 5212 outl(ha->adapt->hw_status_tail, 5213 ha->io_addr + IPS_REG_SQTR); 5214 5215 return (ha->adapt->p_status_tail->value); 5216 } 5217 5218 /****************************************************************************/ 5219 /* */ 5220 /* Routine Name: ips_statupd_copperhead_memio */ 5221 /* */ 5222 /* Routine Description: */ 5223 /* */ 5224 /* Remove an element from the status queue */ 5225 /* */ 5226 /****************************************************************************/ 5227 static uint32_t 5228 ips_statupd_copperhead_memio(ips_ha_t * ha) 5229 { 5230 METHOD_TRACE("ips_statupd_copperhead_memio", 1); 5231 5232 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) { 5233 ha->adapt->p_status_tail++; 5234 ha->adapt->hw_status_tail += sizeof (IPS_STATUS); 5235 } else { 5236 ha->adapt->p_status_tail = ha->adapt->p_status_start; 5237 ha->adapt->hw_status_tail = ha->adapt->hw_status_start; 5238 } 5239 5240 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR); 5241 5242 return (ha->adapt->p_status_tail->value); 5243 } 5244 5245 /****************************************************************************/ 5246 /* */ 5247 /* Routine Name: ips_statupd_morpheus */ 5248 /* */ 5249 /* Routine Description: */ 5250 /* */ 5251 /* Remove an element from the status queue */ 5252 /* */ 5253 /****************************************************************************/ 5254 static uint32_t 5255 ips_statupd_morpheus(ips_ha_t * ha) 5256 { 5257 uint32_t val; 5258 5259 METHOD_TRACE("ips_statupd_morpheus", 1); 5260 5261 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ); 5262 5263 return (val); 5264 } 5265 5266 /****************************************************************************/ 5267 /* */ 5268 /* Routine Name: ips_issue_copperhead */ 5269 /* */ 5270 /* Routine Description: */ 5271 /* */ 5272 /* Send a command down to the controller */ 5273 /* */ 5274 /****************************************************************************/ 5275 static int 5276 ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb) 5277 { 5278 uint32_t TimeOut; 5279 uint32_t val; 5280 5281 METHOD_TRACE("ips_issue_copperhead", 1); 5282 5283 if (scb->scsi_cmd) { 5284 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5285 ips_name, 5286 ha->host_num, 5287 scb->cdb[0], 5288 scb->cmd.basic_io.command_id, 5289 scb->bus, scb->target_id, scb->lun); 5290 } else { 5291 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d", 5292 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5293 } 5294 5295 TimeOut = 0; 5296 5297 while ((val = 5298 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) { 5299 udelay(1000); 5300 5301 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5302 if (!(val & IPS_BIT_START_STOP)) 5303 break; 5304 5305 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5306 "ips_issue val [0x%x].\n", val); 5307 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5308 "ips_issue semaphore chk timeout.\n"); 5309 5310 return (IPS_FAILURE); 5311 } /* end if */ 5312 } /* end while */ 5313 5314 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR); 5315 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR); 5316 5317 return (IPS_SUCCESS); 5318 } 5319 5320 /****************************************************************************/ 5321 /* */ 5322 /* Routine Name: ips_issue_copperhead_memio */ 5323 /* */ 5324 /* Routine Description: */ 5325 /* */ 5326 /* Send a command down to the controller */ 5327 /* */ 5328 /****************************************************************************/ 5329 static int 5330 ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb) 5331 { 5332 uint32_t TimeOut; 5333 uint32_t val; 5334 5335 METHOD_TRACE("ips_issue_copperhead_memio", 1); 5336 5337 if (scb->scsi_cmd) { 5338 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5339 ips_name, 5340 ha->host_num, 5341 scb->cdb[0], 5342 scb->cmd.basic_io.command_id, 5343 scb->bus, scb->target_id, scb->lun); 5344 } else { 5345 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5346 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5347 } 5348 5349 TimeOut = 0; 5350 5351 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) { 5352 udelay(1000); 5353 5354 if (++TimeOut >= IPS_SEM_TIMEOUT) { 5355 if (!(val & IPS_BIT_START_STOP)) 5356 break; 5357 5358 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5359 "ips_issue val [0x%x].\n", val); 5360 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5361 "ips_issue semaphore chk timeout.\n"); 5362 5363 return (IPS_FAILURE); 5364 } /* end if */ 5365 } /* end while */ 5366 5367 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR); 5368 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR); 5369 5370 return (IPS_SUCCESS); 5371 } 5372 5373 /****************************************************************************/ 5374 /* */ 5375 /* Routine Name: ips_issue_i2o */ 5376 /* */ 5377 /* Routine Description: */ 5378 /* */ 5379 /* Send a command down to the controller */ 5380 /* */ 5381 /****************************************************************************/ 5382 static int 5383 ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb) 5384 { 5385 5386 METHOD_TRACE("ips_issue_i2o", 1); 5387 5388 if (scb->scsi_cmd) { 5389 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5390 ips_name, 5391 ha->host_num, 5392 scb->cdb[0], 5393 scb->cmd.basic_io.command_id, 5394 scb->bus, scb->target_id, scb->lun); 5395 } else { 5396 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5397 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5398 } 5399 5400 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ); 5401 5402 return (IPS_SUCCESS); 5403 } 5404 5405 /****************************************************************************/ 5406 /* */ 5407 /* Routine Name: ips_issue_i2o_memio */ 5408 /* */ 5409 /* Routine Description: */ 5410 /* */ 5411 /* Send a command down to the controller */ 5412 /* */ 5413 /****************************************************************************/ 5414 static int 5415 ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb) 5416 { 5417 5418 METHOD_TRACE("ips_issue_i2o_memio", 1); 5419 5420 if (scb->scsi_cmd) { 5421 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)", 5422 ips_name, 5423 ha->host_num, 5424 scb->cdb[0], 5425 scb->cmd.basic_io.command_id, 5426 scb->bus, scb->target_id, scb->lun); 5427 } else { 5428 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d", 5429 ips_name, ha->host_num, scb->cmd.basic_io.command_id); 5430 } 5431 5432 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ); 5433 5434 return (IPS_SUCCESS); 5435 } 5436 5437 /****************************************************************************/ 5438 /* */ 5439 /* Routine Name: ips_isintr_copperhead */ 5440 /* */ 5441 /* Routine Description: */ 5442 /* */ 5443 /* Test to see if an interrupt is for us */ 5444 /* */ 5445 /****************************************************************************/ 5446 static int 5447 ips_isintr_copperhead(ips_ha_t * ha) 5448 { 5449 uint8_t Isr; 5450 5451 METHOD_TRACE("ips_isintr_copperhead", 2); 5452 5453 Isr = inb(ha->io_addr + IPS_REG_HISR); 5454 5455 if (Isr == 0xFF) 5456 /* ?!?! Nothing really there */ 5457 return (0); 5458 5459 if (Isr & IPS_BIT_SCE) 5460 return (1); 5461 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5462 /* status queue overflow or GHI */ 5463 /* just clear the interrupt */ 5464 outb(Isr, ha->io_addr + IPS_REG_HISR); 5465 } 5466 5467 return (0); 5468 } 5469 5470 /****************************************************************************/ 5471 /* */ 5472 /* Routine Name: ips_isintr_copperhead_memio */ 5473 /* */ 5474 /* Routine Description: */ 5475 /* */ 5476 /* Test to see if an interrupt is for us */ 5477 /* */ 5478 /****************************************************************************/ 5479 static int 5480 ips_isintr_copperhead_memio(ips_ha_t * ha) 5481 { 5482 uint8_t Isr; 5483 5484 METHOD_TRACE("ips_isintr_memio", 2); 5485 5486 Isr = readb(ha->mem_ptr + IPS_REG_HISR); 5487 5488 if (Isr == 0xFF) 5489 /* ?!?! Nothing really there */ 5490 return (0); 5491 5492 if (Isr & IPS_BIT_SCE) 5493 return (1); 5494 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) { 5495 /* status queue overflow or GHI */ 5496 /* just clear the interrupt */ 5497 writeb(Isr, ha->mem_ptr + IPS_REG_HISR); 5498 } 5499 5500 return (0); 5501 } 5502 5503 /****************************************************************************/ 5504 /* */ 5505 /* Routine Name: ips_isintr_morpheus */ 5506 /* */ 5507 /* Routine Description: */ 5508 /* */ 5509 /* Test to see if an interrupt is for us */ 5510 /* */ 5511 /****************************************************************************/ 5512 static int 5513 ips_isintr_morpheus(ips_ha_t * ha) 5514 { 5515 uint32_t Isr; 5516 5517 METHOD_TRACE("ips_isintr_morpheus", 2); 5518 5519 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR); 5520 5521 if (Isr & IPS_BIT_I2O_OPQI) 5522 return (1); 5523 else 5524 return (0); 5525 } 5526 5527 /****************************************************************************/ 5528 /* */ 5529 /* Routine Name: ips_wait */ 5530 /* */ 5531 /* Routine Description: */ 5532 /* */ 5533 /* Wait for a command to complete */ 5534 /* */ 5535 /****************************************************************************/ 5536 static int 5537 ips_wait(ips_ha_t * ha, int time, int intr) 5538 { 5539 int ret; 5540 int done; 5541 5542 METHOD_TRACE("ips_wait", 1); 5543 5544 ret = IPS_FAILURE; 5545 done = FALSE; 5546 5547 time *= IPS_ONE_SEC; /* convert seconds */ 5548 5549 while ((time > 0) && (!done)) { 5550 if (intr == IPS_INTR_ON) { 5551 if (ha->waitflag == FALSE) { 5552 ret = IPS_SUCCESS; 5553 done = TRUE; 5554 break; 5555 } 5556 } else if (intr == IPS_INTR_IORL) { 5557 if (ha->waitflag == FALSE) { 5558 /* 5559 * controller generated an interrupt to 5560 * acknowledge completion of the command 5561 * and ips_intr() has serviced the interrupt. 5562 */ 5563 ret = IPS_SUCCESS; 5564 done = TRUE; 5565 break; 5566 } 5567 5568 /* 5569 * NOTE: we already have the io_request_lock so 5570 * even if we get an interrupt it won't get serviced 5571 * until after we finish. 5572 */ 5573 5574 (*ha->func.intr) (ha); 5575 } 5576 5577 /* This looks like a very evil loop, but it only does this during start-up */ 5578 udelay(1000); 5579 time--; 5580 } 5581 5582 return (ret); 5583 } 5584 5585 /****************************************************************************/ 5586 /* */ 5587 /* Routine Name: ips_write_driver_status */ 5588 /* */ 5589 /* Routine Description: */ 5590 /* */ 5591 /* Write OS/Driver version to Page 5 of the nvram on the controller */ 5592 /* */ 5593 /****************************************************************************/ 5594 static int 5595 ips_write_driver_status(ips_ha_t * ha, int intr) 5596 { 5597 METHOD_TRACE("ips_write_driver_status", 1); 5598 5599 if (!ips_readwrite_page5(ha, FALSE, intr)) { 5600 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5601 "unable to read NVRAM page 5.\n"); 5602 5603 return (0); 5604 } 5605 5606 /* check to make sure the page has a valid */ 5607 /* signature */ 5608 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) { 5609 DEBUG_VAR(1, 5610 "(%s%d) NVRAM page 5 has an invalid signature: %X.", 5611 ips_name, ha->host_num, ha->nvram->signature); 5612 ha->nvram->signature = IPS_NVRAM_P5_SIG; 5613 } 5614 5615 DEBUG_VAR(2, 5616 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.", 5617 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type), 5618 ha->nvram->adapter_slot, ha->nvram->bios_high[0], 5619 ha->nvram->bios_high[1], ha->nvram->bios_high[2], 5620 ha->nvram->bios_high[3], ha->nvram->bios_low[0], 5621 ha->nvram->bios_low[1], ha->nvram->bios_low[2], 5622 ha->nvram->bios_low[3]); 5623 5624 ips_get_bios_version(ha, intr); 5625 5626 /* change values (as needed) */ 5627 ha->nvram->operating_system = IPS_OS_LINUX; 5628 ha->nvram->adapter_type = ha->ad_type; 5629 memcpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4); 5630 memcpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4); 5631 memcpy((char *) ha->nvram->bios_high, ha->bios_version, 4); 5632 memcpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4); 5633 5634 ha->nvram->versioning = 0; /* Indicate the Driver Does Not Support Versioning */ 5635 5636 /* now update the page */ 5637 if (!ips_readwrite_page5(ha, TRUE, intr)) { 5638 IPS_PRINTK(KERN_WARNING, ha->pcidev, 5639 "unable to write NVRAM page 5.\n"); 5640 5641 return (0); 5642 } 5643 5644 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */ 5645 ha->slot_num = ha->nvram->adapter_slot; 5646 5647 return (1); 5648 } 5649 5650 /****************************************************************************/ 5651 /* */ 5652 /* Routine Name: ips_read_adapter_status */ 5653 /* */ 5654 /* Routine Description: */ 5655 /* */ 5656 /* Do an Inquiry command to the adapter */ 5657 /* */ 5658 /****************************************************************************/ 5659 static int 5660 ips_read_adapter_status(ips_ha_t * ha, int intr) 5661 { 5662 ips_scb_t *scb; 5663 int ret; 5664 5665 METHOD_TRACE("ips_read_adapter_status", 1); 5666 5667 scb = &ha->scbs[ha->max_cmds - 1]; 5668 5669 ips_init_scb(ha, scb); 5670 5671 scb->timeout = ips_cmd_timeout; 5672 scb->cdb[0] = IPS_CMD_ENQUIRY; 5673 5674 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY; 5675 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5676 scb->cmd.basic_io.sg_count = 0; 5677 scb->cmd.basic_io.lba = 0; 5678 scb->cmd.basic_io.sector_count = 0; 5679 scb->cmd.basic_io.log_drv = 0; 5680 scb->data_len = sizeof (*ha->enq); 5681 scb->cmd.basic_io.sg_addr = ha->enq_busaddr; 5682 5683 /* send command */ 5684 if (((ret = 5685 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5686 || (ret == IPS_SUCCESS_IMM) 5687 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5688 return (0); 5689 5690 return (1); 5691 } 5692 5693 /****************************************************************************/ 5694 /* */ 5695 /* Routine Name: ips_read_subsystem_parameters */ 5696 /* */ 5697 /* Routine Description: */ 5698 /* */ 5699 /* Read subsystem parameters from the adapter */ 5700 /* */ 5701 /****************************************************************************/ 5702 static int 5703 ips_read_subsystem_parameters(ips_ha_t * ha, int intr) 5704 { 5705 ips_scb_t *scb; 5706 int ret; 5707 5708 METHOD_TRACE("ips_read_subsystem_parameters", 1); 5709 5710 scb = &ha->scbs[ha->max_cmds - 1]; 5711 5712 ips_init_scb(ha, scb); 5713 5714 scb->timeout = ips_cmd_timeout; 5715 scb->cdb[0] = IPS_CMD_GET_SUBSYS; 5716 5717 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS; 5718 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5719 scb->cmd.basic_io.sg_count = 0; 5720 scb->cmd.basic_io.lba = 0; 5721 scb->cmd.basic_io.sector_count = 0; 5722 scb->cmd.basic_io.log_drv = 0; 5723 scb->data_len = sizeof (*ha->subsys); 5724 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 5725 5726 /* send command */ 5727 if (((ret = 5728 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5729 || (ret == IPS_SUCCESS_IMM) 5730 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5731 return (0); 5732 5733 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys)); 5734 return (1); 5735 } 5736 5737 /****************************************************************************/ 5738 /* */ 5739 /* Routine Name: ips_read_config */ 5740 /* */ 5741 /* Routine Description: */ 5742 /* */ 5743 /* Read the configuration on the adapter */ 5744 /* */ 5745 /****************************************************************************/ 5746 static int 5747 ips_read_config(ips_ha_t * ha, int intr) 5748 { 5749 ips_scb_t *scb; 5750 int i; 5751 int ret; 5752 5753 METHOD_TRACE("ips_read_config", 1); 5754 5755 /* set defaults for initiator IDs */ 5756 for (i = 0; i < 4; i++) 5757 ha->conf->init_id[i] = 7; 5758 5759 scb = &ha->scbs[ha->max_cmds - 1]; 5760 5761 ips_init_scb(ha, scb); 5762 5763 scb->timeout = ips_cmd_timeout; 5764 scb->cdb[0] = IPS_CMD_READ_CONF; 5765 5766 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF; 5767 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb); 5768 scb->data_len = sizeof (*ha->conf); 5769 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr; 5770 5771 /* send command */ 5772 if (((ret = 5773 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5774 || (ret == IPS_SUCCESS_IMM) 5775 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 5776 5777 memset(ha->conf, 0, sizeof (IPS_CONF)); 5778 5779 /* reset initiator IDs */ 5780 for (i = 0; i < 4; i++) 5781 ha->conf->init_id[i] = 7; 5782 5783 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */ 5784 if ((scb->basic_status & IPS_GSC_STATUS_MASK) == 5785 IPS_CMD_CMPLT_WERROR) 5786 return (1); 5787 5788 return (0); 5789 } 5790 5791 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf)); 5792 return (1); 5793 } 5794 5795 /****************************************************************************/ 5796 /* */ 5797 /* Routine Name: ips_readwrite_page5 */ 5798 /* */ 5799 /* Routine Description: */ 5800 /* */ 5801 /* Read nvram page 5 from the adapter */ 5802 /* */ 5803 /****************************************************************************/ 5804 static int 5805 ips_readwrite_page5(ips_ha_t * ha, int write, int intr) 5806 { 5807 ips_scb_t *scb; 5808 int ret; 5809 5810 METHOD_TRACE("ips_readwrite_page5", 1); 5811 5812 scb = &ha->scbs[ha->max_cmds - 1]; 5813 5814 ips_init_scb(ha, scb); 5815 5816 scb->timeout = ips_cmd_timeout; 5817 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE; 5818 5819 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE; 5820 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb); 5821 scb->cmd.nvram.page = 5; 5822 scb->cmd.nvram.write = write; 5823 scb->cmd.nvram.reserved = 0; 5824 scb->cmd.nvram.reserved2 = 0; 5825 scb->data_len = sizeof (*ha->nvram); 5826 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr; 5827 if (write) 5828 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram)); 5829 5830 /* issue the command */ 5831 if (((ret = 5832 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5833 || (ret == IPS_SUCCESS_IMM) 5834 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) { 5835 5836 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5)); 5837 5838 return (0); 5839 } 5840 if (!write) 5841 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram)); 5842 return (1); 5843 } 5844 5845 /****************************************************************************/ 5846 /* */ 5847 /* Routine Name: ips_clear_adapter */ 5848 /* */ 5849 /* Routine Description: */ 5850 /* */ 5851 /* Clear the stripe lock tables */ 5852 /* */ 5853 /****************************************************************************/ 5854 static int 5855 ips_clear_adapter(ips_ha_t * ha, int intr) 5856 { 5857 ips_scb_t *scb; 5858 int ret; 5859 5860 METHOD_TRACE("ips_clear_adapter", 1); 5861 5862 scb = &ha->scbs[ha->max_cmds - 1]; 5863 5864 ips_init_scb(ha, scb); 5865 5866 scb->timeout = ips_reset_timeout; 5867 scb->cdb[0] = IPS_CMD_CONFIG_SYNC; 5868 5869 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC; 5870 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb); 5871 scb->cmd.config_sync.channel = 0; 5872 scb->cmd.config_sync.source_target = IPS_POCL; 5873 scb->cmd.config_sync.reserved = 0; 5874 scb->cmd.config_sync.reserved2 = 0; 5875 scb->cmd.config_sync.reserved3 = 0; 5876 5877 /* issue command */ 5878 if (((ret = 5879 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE) 5880 || (ret == IPS_SUCCESS_IMM) 5881 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5882 return (0); 5883 5884 /* send unlock stripe command */ 5885 ips_init_scb(ha, scb); 5886 5887 scb->cdb[0] = IPS_CMD_ERROR_TABLE; 5888 scb->timeout = ips_reset_timeout; 5889 5890 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE; 5891 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb); 5892 scb->cmd.unlock_stripe.log_drv = 0; 5893 scb->cmd.unlock_stripe.control = IPS_CSL; 5894 scb->cmd.unlock_stripe.reserved = 0; 5895 scb->cmd.unlock_stripe.reserved2 = 0; 5896 scb->cmd.unlock_stripe.reserved3 = 0; 5897 5898 /* issue command */ 5899 if (((ret = 5900 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE) 5901 || (ret == IPS_SUCCESS_IMM) 5902 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) 5903 return (0); 5904 5905 return (1); 5906 } 5907 5908 /****************************************************************************/ 5909 /* */ 5910 /* Routine Name: ips_ffdc_reset */ 5911 /* */ 5912 /* Routine Description: */ 5913 /* */ 5914 /* FFDC: write reset info */ 5915 /* */ 5916 /****************************************************************************/ 5917 static void 5918 ips_ffdc_reset(ips_ha_t * ha, int intr) 5919 { 5920 ips_scb_t *scb; 5921 5922 METHOD_TRACE("ips_ffdc_reset", 1); 5923 5924 scb = &ha->scbs[ha->max_cmds - 1]; 5925 5926 ips_init_scb(ha, scb); 5927 5928 scb->timeout = ips_cmd_timeout; 5929 scb->cdb[0] = IPS_CMD_FFDC; 5930 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 5931 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 5932 scb->cmd.ffdc.reset_count = ha->reset_count; 5933 scb->cmd.ffdc.reset_type = 0x80; 5934 5935 /* convert time to what the card wants */ 5936 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 5937 5938 /* issue command */ 5939 ips_send_wait(ha, scb, ips_cmd_timeout, intr); 5940 } 5941 5942 /****************************************************************************/ 5943 /* */ 5944 /* Routine Name: ips_ffdc_time */ 5945 /* */ 5946 /* Routine Description: */ 5947 /* */ 5948 /* FFDC: write time info */ 5949 /* */ 5950 /****************************************************************************/ 5951 static void 5952 ips_ffdc_time(ips_ha_t * ha) 5953 { 5954 ips_scb_t *scb; 5955 5956 METHOD_TRACE("ips_ffdc_time", 1); 5957 5958 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num); 5959 5960 scb = &ha->scbs[ha->max_cmds - 1]; 5961 5962 ips_init_scb(ha, scb); 5963 5964 scb->timeout = ips_cmd_timeout; 5965 scb->cdb[0] = IPS_CMD_FFDC; 5966 scb->cmd.ffdc.op_code = IPS_CMD_FFDC; 5967 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb); 5968 scb->cmd.ffdc.reset_count = 0; 5969 scb->cmd.ffdc.reset_type = 0; 5970 5971 /* convert time to what the card wants */ 5972 ips_fix_ffdc_time(ha, scb, ha->last_ffdc); 5973 5974 /* issue command */ 5975 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC); 5976 } 5977 5978 /****************************************************************************/ 5979 /* */ 5980 /* Routine Name: ips_fix_ffdc_time */ 5981 /* */ 5982 /* Routine Description: */ 5983 /* Adjust time_t to what the card wants */ 5984 /* */ 5985 /****************************************************************************/ 5986 static void 5987 ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time64_t current_time) 5988 { 5989 struct tm tm; 5990 5991 METHOD_TRACE("ips_fix_ffdc_time", 1); 5992 5993 time64_to_tm(current_time, 0, &tm); 5994 5995 scb->cmd.ffdc.hour = tm.tm_hour; 5996 scb->cmd.ffdc.minute = tm.tm_min; 5997 scb->cmd.ffdc.second = tm.tm_sec; 5998 scb->cmd.ffdc.yearH = (tm.tm_year + 1900) / 100; 5999 scb->cmd.ffdc.yearL = tm.tm_year % 100; 6000 scb->cmd.ffdc.month = tm.tm_mon + 1; 6001 scb->cmd.ffdc.day = tm.tm_mday; 6002 } 6003 6004 /**************************************************************************** 6005 * BIOS Flash Routines * 6006 ****************************************************************************/ 6007 6008 /****************************************************************************/ 6009 /* */ 6010 /* Routine Name: ips_erase_bios */ 6011 /* */ 6012 /* Routine Description: */ 6013 /* Erase the BIOS on the adapter */ 6014 /* */ 6015 /****************************************************************************/ 6016 static int 6017 ips_erase_bios(ips_ha_t * ha) 6018 { 6019 int timeout; 6020 uint8_t status = 0; 6021 6022 METHOD_TRACE("ips_erase_bios", 1); 6023 6024 status = 0; 6025 6026 /* Clear the status register */ 6027 outl(0, ha->io_addr + IPS_REG_FLAP); 6028 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6029 udelay(25); /* 25 us */ 6030 6031 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6032 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6033 udelay(25); /* 25 us */ 6034 6035 /* Erase Setup */ 6036 outb(0x20, ha->io_addr + IPS_REG_FLDP); 6037 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6038 udelay(25); /* 25 us */ 6039 6040 /* Erase Confirm */ 6041 outb(0xD0, ha->io_addr + IPS_REG_FLDP); 6042 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6043 udelay(25); /* 25 us */ 6044 6045 /* Erase Status */ 6046 outb(0x70, ha->io_addr + IPS_REG_FLDP); 6047 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6048 udelay(25); /* 25 us */ 6049 6050 timeout = 80000; /* 80 seconds */ 6051 6052 while (timeout > 0) { 6053 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6054 outl(0, ha->io_addr + IPS_REG_FLAP); 6055 udelay(25); /* 25 us */ 6056 } 6057 6058 status = inb(ha->io_addr + IPS_REG_FLDP); 6059 6060 if (status & 0x80) 6061 break; 6062 6063 MDELAY(1); 6064 timeout--; 6065 } 6066 6067 /* check for timeout */ 6068 if (timeout <= 0) { 6069 /* timeout */ 6070 6071 /* try to suspend the erase */ 6072 outb(0xB0, ha->io_addr + IPS_REG_FLDP); 6073 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6074 udelay(25); /* 25 us */ 6075 6076 /* wait for 10 seconds */ 6077 timeout = 10000; 6078 while (timeout > 0) { 6079 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6080 outl(0, ha->io_addr + IPS_REG_FLAP); 6081 udelay(25); /* 25 us */ 6082 } 6083 6084 status = inb(ha->io_addr + IPS_REG_FLDP); 6085 6086 if (status & 0xC0) 6087 break; 6088 6089 MDELAY(1); 6090 timeout--; 6091 } 6092 6093 return (1); 6094 } 6095 6096 /* check for valid VPP */ 6097 if (status & 0x08) 6098 /* VPP failure */ 6099 return (1); 6100 6101 /* check for successful flash */ 6102 if (status & 0x30) 6103 /* sequence error */ 6104 return (1); 6105 6106 /* Otherwise, we were successful */ 6107 /* clear status */ 6108 outb(0x50, ha->io_addr + IPS_REG_FLDP); 6109 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6110 udelay(25); /* 25 us */ 6111 6112 /* enable reads */ 6113 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6114 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6115 udelay(25); /* 25 us */ 6116 6117 return (0); 6118 } 6119 6120 /****************************************************************************/ 6121 /* */ 6122 /* Routine Name: ips_erase_bios_memio */ 6123 /* */ 6124 /* Routine Description: */ 6125 /* Erase the BIOS on the adapter */ 6126 /* */ 6127 /****************************************************************************/ 6128 static int 6129 ips_erase_bios_memio(ips_ha_t * ha) 6130 { 6131 int timeout; 6132 uint8_t status; 6133 6134 METHOD_TRACE("ips_erase_bios_memio", 1); 6135 6136 status = 0; 6137 6138 /* Clear the status register */ 6139 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6140 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6141 udelay(25); /* 25 us */ 6142 6143 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6144 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6145 udelay(25); /* 25 us */ 6146 6147 /* Erase Setup */ 6148 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP); 6149 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6150 udelay(25); /* 25 us */ 6151 6152 /* Erase Confirm */ 6153 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP); 6154 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6155 udelay(25); /* 25 us */ 6156 6157 /* Erase Status */ 6158 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP); 6159 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6160 udelay(25); /* 25 us */ 6161 6162 timeout = 80000; /* 80 seconds */ 6163 6164 while (timeout > 0) { 6165 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6166 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6167 udelay(25); /* 25 us */ 6168 } 6169 6170 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6171 6172 if (status & 0x80) 6173 break; 6174 6175 MDELAY(1); 6176 timeout--; 6177 } 6178 6179 /* check for timeout */ 6180 if (timeout <= 0) { 6181 /* timeout */ 6182 6183 /* try to suspend the erase */ 6184 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP); 6185 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6186 udelay(25); /* 25 us */ 6187 6188 /* wait for 10 seconds */ 6189 timeout = 10000; 6190 while (timeout > 0) { 6191 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6192 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6193 udelay(25); /* 25 us */ 6194 } 6195 6196 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6197 6198 if (status & 0xC0) 6199 break; 6200 6201 MDELAY(1); 6202 timeout--; 6203 } 6204 6205 return (1); 6206 } 6207 6208 /* check for valid VPP */ 6209 if (status & 0x08) 6210 /* VPP failure */ 6211 return (1); 6212 6213 /* check for successful flash */ 6214 if (status & 0x30) 6215 /* sequence error */ 6216 return (1); 6217 6218 /* Otherwise, we were successful */ 6219 /* clear status */ 6220 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP); 6221 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6222 udelay(25); /* 25 us */ 6223 6224 /* enable reads */ 6225 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6226 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6227 udelay(25); /* 25 us */ 6228 6229 return (0); 6230 } 6231 6232 /****************************************************************************/ 6233 /* */ 6234 /* Routine Name: ips_program_bios */ 6235 /* */ 6236 /* Routine Description: */ 6237 /* Program the BIOS on the adapter */ 6238 /* */ 6239 /****************************************************************************/ 6240 static int 6241 ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6242 uint32_t offset) 6243 { 6244 int i; 6245 int timeout; 6246 uint8_t status = 0; 6247 6248 METHOD_TRACE("ips_program_bios", 1); 6249 6250 status = 0; 6251 6252 for (i = 0; i < buffersize; i++) { 6253 /* write a byte */ 6254 outl(i + offset, ha->io_addr + IPS_REG_FLAP); 6255 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6256 udelay(25); /* 25 us */ 6257 6258 outb(0x40, ha->io_addr + IPS_REG_FLDP); 6259 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6260 udelay(25); /* 25 us */ 6261 6262 outb(buffer[i], ha->io_addr + IPS_REG_FLDP); 6263 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6264 udelay(25); /* 25 us */ 6265 6266 /* wait up to one second */ 6267 timeout = 1000; 6268 while (timeout > 0) { 6269 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6270 outl(0, ha->io_addr + IPS_REG_FLAP); 6271 udelay(25); /* 25 us */ 6272 } 6273 6274 status = inb(ha->io_addr + IPS_REG_FLDP); 6275 6276 if (status & 0x80) 6277 break; 6278 6279 MDELAY(1); 6280 timeout--; 6281 } 6282 6283 if (timeout == 0) { 6284 /* timeout error */ 6285 outl(0, ha->io_addr + IPS_REG_FLAP); 6286 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6287 udelay(25); /* 25 us */ 6288 6289 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6290 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6291 udelay(25); /* 25 us */ 6292 6293 return (1); 6294 } 6295 6296 /* check the status */ 6297 if (status & 0x18) { 6298 /* programming error */ 6299 outl(0, ha->io_addr + IPS_REG_FLAP); 6300 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6301 udelay(25); /* 25 us */ 6302 6303 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6304 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6305 udelay(25); /* 25 us */ 6306 6307 return (1); 6308 } 6309 } /* end for */ 6310 6311 /* Enable reading */ 6312 outl(0, ha->io_addr + IPS_REG_FLAP); 6313 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6314 udelay(25); /* 25 us */ 6315 6316 outb(0xFF, ha->io_addr + IPS_REG_FLDP); 6317 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6318 udelay(25); /* 25 us */ 6319 6320 return (0); 6321 } 6322 6323 /****************************************************************************/ 6324 /* */ 6325 /* Routine Name: ips_program_bios_memio */ 6326 /* */ 6327 /* Routine Description: */ 6328 /* Program the BIOS on the adapter */ 6329 /* */ 6330 /****************************************************************************/ 6331 static int 6332 ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6333 uint32_t offset) 6334 { 6335 int i; 6336 int timeout; 6337 uint8_t status = 0; 6338 6339 METHOD_TRACE("ips_program_bios_memio", 1); 6340 6341 status = 0; 6342 6343 for (i = 0; i < buffersize; i++) { 6344 /* write a byte */ 6345 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6346 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6347 udelay(25); /* 25 us */ 6348 6349 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP); 6350 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6351 udelay(25); /* 25 us */ 6352 6353 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP); 6354 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6355 udelay(25); /* 25 us */ 6356 6357 /* wait up to one second */ 6358 timeout = 1000; 6359 while (timeout > 0) { 6360 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) { 6361 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6362 udelay(25); /* 25 us */ 6363 } 6364 6365 status = readb(ha->mem_ptr + IPS_REG_FLDP); 6366 6367 if (status & 0x80) 6368 break; 6369 6370 MDELAY(1); 6371 timeout--; 6372 } 6373 6374 if (timeout == 0) { 6375 /* timeout error */ 6376 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6377 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6378 udelay(25); /* 25 us */ 6379 6380 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6381 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6382 udelay(25); /* 25 us */ 6383 6384 return (1); 6385 } 6386 6387 /* check the status */ 6388 if (status & 0x18) { 6389 /* programming error */ 6390 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6391 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6392 udelay(25); /* 25 us */ 6393 6394 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6395 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6396 udelay(25); /* 25 us */ 6397 6398 return (1); 6399 } 6400 } /* end for */ 6401 6402 /* Enable reading */ 6403 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6404 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6405 udelay(25); /* 25 us */ 6406 6407 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP); 6408 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6409 udelay(25); /* 25 us */ 6410 6411 return (0); 6412 } 6413 6414 /****************************************************************************/ 6415 /* */ 6416 /* Routine Name: ips_verify_bios */ 6417 /* */ 6418 /* Routine Description: */ 6419 /* Verify the BIOS on the adapter */ 6420 /* */ 6421 /****************************************************************************/ 6422 static int 6423 ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6424 uint32_t offset) 6425 { 6426 uint8_t checksum; 6427 int i; 6428 6429 METHOD_TRACE("ips_verify_bios", 1); 6430 6431 /* test 1st byte */ 6432 outl(0, ha->io_addr + IPS_REG_FLAP); 6433 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6434 udelay(25); /* 25 us */ 6435 6436 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55) 6437 return (1); 6438 6439 outl(1, ha->io_addr + IPS_REG_FLAP); 6440 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6441 udelay(25); /* 25 us */ 6442 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA) 6443 return (1); 6444 6445 checksum = 0xff; 6446 for (i = 2; i < buffersize; i++) { 6447 6448 outl(i + offset, ha->io_addr + IPS_REG_FLAP); 6449 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6450 udelay(25); /* 25 us */ 6451 6452 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP); 6453 } 6454 6455 if (checksum != 0) 6456 /* failure */ 6457 return (1); 6458 else 6459 /* success */ 6460 return (0); 6461 } 6462 6463 /****************************************************************************/ 6464 /* */ 6465 /* Routine Name: ips_verify_bios_memio */ 6466 /* */ 6467 /* Routine Description: */ 6468 /* Verify the BIOS on the adapter */ 6469 /* */ 6470 /****************************************************************************/ 6471 static int 6472 ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize, 6473 uint32_t offset) 6474 { 6475 uint8_t checksum; 6476 int i; 6477 6478 METHOD_TRACE("ips_verify_bios_memio", 1); 6479 6480 /* test 1st byte */ 6481 writel(0, ha->mem_ptr + IPS_REG_FLAP); 6482 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6483 udelay(25); /* 25 us */ 6484 6485 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55) 6486 return (1); 6487 6488 writel(1, ha->mem_ptr + IPS_REG_FLAP); 6489 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6490 udelay(25); /* 25 us */ 6491 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA) 6492 return (1); 6493 6494 checksum = 0xff; 6495 for (i = 2; i < buffersize; i++) { 6496 6497 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP); 6498 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) 6499 udelay(25); /* 25 us */ 6500 6501 checksum = 6502 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP); 6503 } 6504 6505 if (checksum != 0) 6506 /* failure */ 6507 return (1); 6508 else 6509 /* success */ 6510 return (0); 6511 } 6512 6513 /****************************************************************************/ 6514 /* */ 6515 /* Routine Name: ips_abort_init */ 6516 /* */ 6517 /* Routine Description: */ 6518 /* cleanup routine for a failed adapter initialization */ 6519 /****************************************************************************/ 6520 static int 6521 ips_abort_init(ips_ha_t * ha, int index) 6522 { 6523 ha->active = 0; 6524 ips_free(ha); 6525 ips_ha[index] = NULL; 6526 ips_sh[index] = NULL; 6527 return -1; 6528 } 6529 6530 /****************************************************************************/ 6531 /* */ 6532 /* Routine Name: ips_shift_controllers */ 6533 /* */ 6534 /* Routine Description: */ 6535 /* helper function for ordering adapters */ 6536 /****************************************************************************/ 6537 static void 6538 ips_shift_controllers(int lowindex, int highindex) 6539 { 6540 ips_ha_t *ha_sav = ips_ha[highindex]; 6541 struct Scsi_Host *sh_sav = ips_sh[highindex]; 6542 int i; 6543 6544 for (i = highindex; i > lowindex; i--) { 6545 ips_ha[i] = ips_ha[i - 1]; 6546 ips_sh[i] = ips_sh[i - 1]; 6547 ips_ha[i]->host_num = i; 6548 } 6549 ha_sav->host_num = lowindex; 6550 ips_ha[lowindex] = ha_sav; 6551 ips_sh[lowindex] = sh_sav; 6552 } 6553 6554 /****************************************************************************/ 6555 /* */ 6556 /* Routine Name: ips_order_controllers */ 6557 /* */ 6558 /* Routine Description: */ 6559 /* place controllers is the "proper" boot order */ 6560 /****************************************************************************/ 6561 static void 6562 ips_order_controllers(void) 6563 { 6564 int i, j, tmp, position = 0; 6565 IPS_NVRAM_P5 *nvram; 6566 if (!ips_ha[0]) 6567 return; 6568 nvram = ips_ha[0]->nvram; 6569 6570 if (nvram->adapter_order[0]) { 6571 for (i = 1; i <= nvram->adapter_order[0]; i++) { 6572 for (j = position; j < ips_num_controllers; j++) { 6573 switch (ips_ha[j]->ad_type) { 6574 case IPS_ADTYPE_SERVERAID6M: 6575 case IPS_ADTYPE_SERVERAID7M: 6576 if (nvram->adapter_order[i] == 'M') { 6577 ips_shift_controllers(position, 6578 j); 6579 position++; 6580 } 6581 break; 6582 case IPS_ADTYPE_SERVERAID4L: 6583 case IPS_ADTYPE_SERVERAID4M: 6584 case IPS_ADTYPE_SERVERAID4MX: 6585 case IPS_ADTYPE_SERVERAID4LX: 6586 if (nvram->adapter_order[i] == 'N') { 6587 ips_shift_controllers(position, 6588 j); 6589 position++; 6590 } 6591 break; 6592 case IPS_ADTYPE_SERVERAID6I: 6593 case IPS_ADTYPE_SERVERAID5I2: 6594 case IPS_ADTYPE_SERVERAID5I1: 6595 case IPS_ADTYPE_SERVERAID7k: 6596 if (nvram->adapter_order[i] == 'S') { 6597 ips_shift_controllers(position, 6598 j); 6599 position++; 6600 } 6601 break; 6602 case IPS_ADTYPE_SERVERAID: 6603 case IPS_ADTYPE_SERVERAID2: 6604 case IPS_ADTYPE_NAVAJO: 6605 case IPS_ADTYPE_KIOWA: 6606 case IPS_ADTYPE_SERVERAID3L: 6607 case IPS_ADTYPE_SERVERAID3: 6608 case IPS_ADTYPE_SERVERAID4H: 6609 if (nvram->adapter_order[i] == 'A') { 6610 ips_shift_controllers(position, 6611 j); 6612 position++; 6613 } 6614 break; 6615 default: 6616 break; 6617 } 6618 } 6619 } 6620 /* if adapter_order[0], then ordering is complete */ 6621 return; 6622 } 6623 /* old bios, use older ordering */ 6624 tmp = 0; 6625 for (i = position; i < ips_num_controllers; i++) { 6626 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 || 6627 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) { 6628 ips_shift_controllers(position, i); 6629 position++; 6630 tmp = 1; 6631 } 6632 } 6633 /* if there were no 5I cards, then don't do any extra ordering */ 6634 if (!tmp) 6635 return; 6636 for (i = position; i < ips_num_controllers; i++) { 6637 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L || 6638 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M || 6639 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX || 6640 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) { 6641 ips_shift_controllers(position, i); 6642 position++; 6643 } 6644 } 6645 6646 return; 6647 } 6648 6649 /****************************************************************************/ 6650 /* */ 6651 /* Routine Name: ips_register_scsi */ 6652 /* */ 6653 /* Routine Description: */ 6654 /* perform any registration and setup with the scsi layer */ 6655 /****************************************************************************/ 6656 static int 6657 ips_register_scsi(int index) 6658 { 6659 struct Scsi_Host *sh; 6660 ips_ha_t *ha, *oldha = ips_ha[index]; 6661 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t)); 6662 if (!sh) { 6663 IPS_PRINTK(KERN_WARNING, oldha->pcidev, 6664 "Unable to register controller with SCSI subsystem\n"); 6665 return -1; 6666 } 6667 ha = IPS_HA(sh); 6668 memcpy(ha, oldha, sizeof (ips_ha_t)); 6669 free_irq(oldha->pcidev->irq, oldha); 6670 /* Install the interrupt handler with the new ha */ 6671 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 6672 IPS_PRINTK(KERN_WARNING, ha->pcidev, 6673 "Unable to install interrupt handler\n"); 6674 goto err_out_sh; 6675 } 6676 6677 kfree(oldha); 6678 6679 /* Store away needed values for later use */ 6680 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr; 6681 sh->sg_tablesize = sh->hostt->sg_tablesize; 6682 sh->can_queue = sh->hostt->can_queue; 6683 sh->cmd_per_lun = sh->hostt->cmd_per_lun; 6684 sh->max_sectors = 128; 6685 6686 sh->max_id = ha->ntargets; 6687 sh->max_lun = ha->nlun; 6688 sh->max_channel = ha->nbus - 1; 6689 sh->can_queue = ha->max_cmds - 1; 6690 6691 if (scsi_add_host(sh, &ha->pcidev->dev)) 6692 goto err_out; 6693 6694 ips_sh[index] = sh; 6695 ips_ha[index] = ha; 6696 6697 scsi_scan_host(sh); 6698 6699 return 0; 6700 6701 err_out: 6702 free_irq(ha->pcidev->irq, ha); 6703 err_out_sh: 6704 scsi_host_put(sh); 6705 return -1; 6706 } 6707 6708 /*---------------------------------------------------------------------------*/ 6709 /* Routine Name: ips_remove_device */ 6710 /* */ 6711 /* Routine Description: */ 6712 /* Remove one Adapter ( Hot Plugging ) */ 6713 /*---------------------------------------------------------------------------*/ 6714 static void 6715 ips_remove_device(struct pci_dev *pci_dev) 6716 { 6717 struct Scsi_Host *sh = pci_get_drvdata(pci_dev); 6718 6719 pci_set_drvdata(pci_dev, NULL); 6720 6721 ips_release(sh); 6722 6723 pci_release_regions(pci_dev); 6724 pci_disable_device(pci_dev); 6725 } 6726 6727 /****************************************************************************/ 6728 /* */ 6729 /* Routine Name: ips_module_init */ 6730 /* */ 6731 /* Routine Description: */ 6732 /* function called on module load */ 6733 /****************************************************************************/ 6734 static int __init 6735 ips_module_init(void) 6736 { 6737 #if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__) 6738 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n"); 6739 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 6740 #endif 6741 6742 if (pci_register_driver(&ips_pci_driver) < 0) 6743 return -ENODEV; 6744 ips_driver_template.module = THIS_MODULE; 6745 ips_order_controllers(); 6746 if (!ips_detect(&ips_driver_template)) { 6747 pci_unregister_driver(&ips_pci_driver); 6748 return -ENODEV; 6749 } 6750 register_reboot_notifier(&ips_notifier); 6751 return 0; 6752 } 6753 6754 /****************************************************************************/ 6755 /* */ 6756 /* Routine Name: ips_module_exit */ 6757 /* */ 6758 /* Routine Description: */ 6759 /* function called on module unload */ 6760 /****************************************************************************/ 6761 static void __exit 6762 ips_module_exit(void) 6763 { 6764 pci_unregister_driver(&ips_pci_driver); 6765 unregister_reboot_notifier(&ips_notifier); 6766 } 6767 6768 module_init(ips_module_init); 6769 module_exit(ips_module_exit); 6770 6771 /*---------------------------------------------------------------------------*/ 6772 /* Routine Name: ips_insert_device */ 6773 /* */ 6774 /* Routine Description: */ 6775 /* Add One Adapter ( Hot Plug ) */ 6776 /* */ 6777 /* Return Value: */ 6778 /* 0 if Successful, else non-zero */ 6779 /*---------------------------------------------------------------------------*/ 6780 static int 6781 ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent) 6782 { 6783 int index = -1; 6784 int rc; 6785 6786 METHOD_TRACE("ips_insert_device", 1); 6787 rc = pci_enable_device(pci_dev); 6788 if (rc) 6789 return rc; 6790 6791 rc = pci_request_regions(pci_dev, "ips"); 6792 if (rc) 6793 goto err_out; 6794 6795 rc = ips_init_phase1(pci_dev, &index); 6796 if (rc == SUCCESS) 6797 rc = ips_init_phase2(index); 6798 6799 if (ips_hotplug) 6800 if (ips_register_scsi(index)) { 6801 ips_free(ips_ha[index]); 6802 rc = -1; 6803 } 6804 6805 if (rc == SUCCESS) 6806 ips_num_controllers++; 6807 6808 ips_next_controller = ips_num_controllers; 6809 6810 if (rc < 0) { 6811 rc = -ENODEV; 6812 goto err_out_regions; 6813 } 6814 6815 pci_set_drvdata(pci_dev, ips_sh[index]); 6816 return 0; 6817 6818 err_out_regions: 6819 pci_release_regions(pci_dev); 6820 err_out: 6821 pci_disable_device(pci_dev); 6822 return rc; 6823 } 6824 6825 /*---------------------------------------------------------------------------*/ 6826 /* Routine Name: ips_init_phase1 */ 6827 /* */ 6828 /* Routine Description: */ 6829 /* Adapter Initialization */ 6830 /* */ 6831 /* Return Value: */ 6832 /* 0 if Successful, else non-zero */ 6833 /*---------------------------------------------------------------------------*/ 6834 static int 6835 ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr) 6836 { 6837 ips_ha_t *ha; 6838 uint32_t io_addr; 6839 uint32_t mem_addr; 6840 uint32_t io_len; 6841 uint32_t mem_len; 6842 int j; 6843 int index; 6844 dma_addr_t dma_address; 6845 char __iomem *ioremap_ptr; 6846 char __iomem *mem_ptr; 6847 uint32_t IsDead; 6848 6849 METHOD_TRACE("ips_init_phase1", 1); 6850 index = IPS_MAX_ADAPTERS; 6851 for (j = 0; j < IPS_MAX_ADAPTERS; j++) { 6852 if (ips_ha[j] == NULL) { 6853 index = j; 6854 break; 6855 } 6856 } 6857 6858 if (index >= IPS_MAX_ADAPTERS) 6859 return -1; 6860 6861 /* Init MEM/IO addresses to 0 */ 6862 mem_addr = 0; 6863 io_addr = 0; 6864 mem_len = 0; 6865 io_len = 0; 6866 6867 for (j = 0; j < 2; j++) { 6868 if (!pci_resource_start(pci_dev, j)) 6869 break; 6870 6871 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) { 6872 io_addr = pci_resource_start(pci_dev, j); 6873 io_len = pci_resource_len(pci_dev, j); 6874 } else { 6875 mem_addr = pci_resource_start(pci_dev, j); 6876 mem_len = pci_resource_len(pci_dev, j); 6877 } 6878 } 6879 6880 /* setup memory mapped area (if applicable) */ 6881 if (mem_addr) { 6882 uint32_t base; 6883 uint32_t offs; 6884 6885 base = mem_addr & PAGE_MASK; 6886 offs = mem_addr - base; 6887 ioremap_ptr = ioremap(base, PAGE_SIZE); 6888 if (!ioremap_ptr) 6889 return -1; 6890 mem_ptr = ioremap_ptr + offs; 6891 } else { 6892 ioremap_ptr = NULL; 6893 mem_ptr = NULL; 6894 } 6895 6896 /* found a controller */ 6897 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL); 6898 if (ha == NULL) { 6899 IPS_PRINTK(KERN_WARNING, pci_dev, 6900 "Unable to allocate temporary ha struct\n"); 6901 return -1; 6902 } 6903 6904 ips_sh[index] = NULL; 6905 ips_ha[index] = ha; 6906 ha->active = 1; 6907 6908 /* Store info in HA structure */ 6909 ha->io_addr = io_addr; 6910 ha->io_len = io_len; 6911 ha->mem_addr = mem_addr; 6912 ha->mem_len = mem_len; 6913 ha->mem_ptr = mem_ptr; 6914 ha->ioremap_ptr = ioremap_ptr; 6915 ha->host_num = (uint32_t) index; 6916 ha->slot_num = PCI_SLOT(pci_dev->devfn); 6917 ha->pcidev = pci_dev; 6918 6919 /* 6920 * Set the pci_dev's dma_mask. Not all adapters support 64bit 6921 * addressing so don't enable it if the adapter can't support 6922 * it! Also, don't use 64bit addressing if dma addresses 6923 * are guaranteed to be < 4G. 6924 */ 6925 if (sizeof(dma_addr_t) > 4 && IPS_HAS_ENH_SGLIST(ha) && 6926 !dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(64))) { 6927 (ha)->flags |= IPS_HA_ENH_SG; 6928 } else { 6929 if (dma_set_mask(&ha->pcidev->dev, DMA_BIT_MASK(32)) != 0) { 6930 printk(KERN_WARNING "Unable to set DMA Mask\n"); 6931 return ips_abort_init(ha, index); 6932 } 6933 } 6934 if(ips_cd_boot && !ips_FlashData){ 6935 ips_FlashData = dma_alloc_coherent(&pci_dev->dev, 6936 PAGE_SIZE << 7, &ips_flashbusaddr, GFP_KERNEL); 6937 } 6938 6939 ha->enq = dma_alloc_coherent(&pci_dev->dev, sizeof (IPS_ENQ), 6940 &ha->enq_busaddr, GFP_KERNEL); 6941 if (!ha->enq) { 6942 IPS_PRINTK(KERN_WARNING, pci_dev, 6943 "Unable to allocate host inquiry structure\n"); 6944 return ips_abort_init(ha, index); 6945 } 6946 6947 ha->adapt = dma_alloc_coherent(&pci_dev->dev, 6948 sizeof (IPS_ADAPTER) + sizeof (IPS_IO_CMD), 6949 &dma_address, GFP_KERNEL); 6950 if (!ha->adapt) { 6951 IPS_PRINTK(KERN_WARNING, pci_dev, 6952 "Unable to allocate host adapt & dummy structures\n"); 6953 return ips_abort_init(ha, index); 6954 } 6955 ha->adapt->hw_status_start = dma_address; 6956 ha->dummy = (void *) (ha->adapt + 1); 6957 6958 6959 6960 ha->logical_drive_info = dma_alloc_coherent(&pci_dev->dev, 6961 sizeof (IPS_LD_INFO), &dma_address, GFP_KERNEL); 6962 if (!ha->logical_drive_info) { 6963 IPS_PRINTK(KERN_WARNING, pci_dev, 6964 "Unable to allocate logical drive info structure\n"); 6965 return ips_abort_init(ha, index); 6966 } 6967 ha->logical_drive_info_dma_addr = dma_address; 6968 6969 6970 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL); 6971 6972 if (!ha->conf) { 6973 IPS_PRINTK(KERN_WARNING, pci_dev, 6974 "Unable to allocate host conf structure\n"); 6975 return ips_abort_init(ha, index); 6976 } 6977 6978 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL); 6979 6980 if (!ha->nvram) { 6981 IPS_PRINTK(KERN_WARNING, pci_dev, 6982 "Unable to allocate host NVRAM structure\n"); 6983 return ips_abort_init(ha, index); 6984 } 6985 6986 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL); 6987 6988 if (!ha->subsys) { 6989 IPS_PRINTK(KERN_WARNING, pci_dev, 6990 "Unable to allocate host subsystem structure\n"); 6991 return ips_abort_init(ha, index); 6992 } 6993 6994 /* the ioctl buffer is now used during adapter initialization, so its 6995 * successful allocation is now required */ 6996 if (ips_ioctlsize < PAGE_SIZE) 6997 ips_ioctlsize = PAGE_SIZE; 6998 6999 ha->ioctl_data = dma_alloc_coherent(&pci_dev->dev, ips_ioctlsize, 7000 &ha->ioctl_busaddr, GFP_KERNEL); 7001 ha->ioctl_len = ips_ioctlsize; 7002 if (!ha->ioctl_data) { 7003 IPS_PRINTK(KERN_WARNING, pci_dev, 7004 "Unable to allocate IOCTL data\n"); 7005 return ips_abort_init(ha, index); 7006 } 7007 7008 /* 7009 * Setup Functions 7010 */ 7011 ips_setup_funclist(ha); 7012 7013 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) { 7014 /* If Morpheus appears dead, reset it */ 7015 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1); 7016 if (IsDead == 0xDEADBEEF) { 7017 ips_reset_morpheus(ha); 7018 } 7019 } 7020 7021 /* 7022 * Initialize the card if it isn't already 7023 */ 7024 7025 if (!(*ha->func.isinit) (ha)) { 7026 if (!(*ha->func.init) (ha)) { 7027 /* 7028 * Initialization failed 7029 */ 7030 IPS_PRINTK(KERN_WARNING, pci_dev, 7031 "Unable to initialize controller\n"); 7032 return ips_abort_init(ha, index); 7033 } 7034 } 7035 7036 *indexPtr = index; 7037 return SUCCESS; 7038 } 7039 7040 /*---------------------------------------------------------------------------*/ 7041 /* Routine Name: ips_init_phase2 */ 7042 /* */ 7043 /* Routine Description: */ 7044 /* Adapter Initialization Phase 2 */ 7045 /* */ 7046 /* Return Value: */ 7047 /* 0 if Successful, else non-zero */ 7048 /*---------------------------------------------------------------------------*/ 7049 static int 7050 ips_init_phase2(int index) 7051 { 7052 ips_ha_t *ha; 7053 7054 ha = ips_ha[index]; 7055 7056 METHOD_TRACE("ips_init_phase2", 1); 7057 if (!ha->active) { 7058 ips_ha[index] = NULL; 7059 return -1; 7060 } 7061 7062 /* Install the interrupt handler */ 7063 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) { 7064 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7065 "Unable to install interrupt handler\n"); 7066 return ips_abort_init(ha, index); 7067 } 7068 7069 /* 7070 * Allocate a temporary SCB for initialization 7071 */ 7072 ha->max_cmds = 1; 7073 if (!ips_allocatescbs(ha)) { 7074 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7075 "Unable to allocate a CCB\n"); 7076 free_irq(ha->pcidev->irq, ha); 7077 return ips_abort_init(ha, index); 7078 } 7079 7080 if (!ips_hainit(ha)) { 7081 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7082 "Unable to initialize controller\n"); 7083 free_irq(ha->pcidev->irq, ha); 7084 return ips_abort_init(ha, index); 7085 } 7086 /* Free the temporary SCB */ 7087 ips_deallocatescbs(ha, 1); 7088 7089 /* allocate CCBs */ 7090 if (!ips_allocatescbs(ha)) { 7091 IPS_PRINTK(KERN_WARNING, ha->pcidev, 7092 "Unable to allocate CCBs\n"); 7093 free_irq(ha->pcidev->irq, ha); 7094 return ips_abort_init(ha, index); 7095 } 7096 7097 return SUCCESS; 7098 } 7099 7100 MODULE_LICENSE("GPL"); 7101 MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING); 7102 MODULE_VERSION(IPS_VER_STRING); 7103