xref: /openbmc/linux/drivers/scsi/ipr.h (revision 81d67439)
1 /*
2  * ipr.h -- driver for IBM Power Linux RAID adapters
3  *
4  * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5  *
6  * Copyright (C) 2003, 2004 IBM Corporation
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21  *
22  * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
23  *				that broke 64bit platforms.
24  */
25 
26 #ifndef _IPR_H
27 #define _IPR_H
28 
29 #include <asm/unaligned.h>
30 #include <linux/types.h>
31 #include <linux/completion.h>
32 #include <linux/libata.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <scsi/scsi.h>
36 #include <scsi/scsi_cmnd.h>
37 
38 /*
39  * Literals
40  */
41 #define IPR_DRIVER_VERSION "2.5.2"
42 #define IPR_DRIVER_DATE "(April 27, 2011)"
43 
44 /*
45  * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
46  *	ops per device for devices not running tagged command queuing.
47  *	This can be adjusted at runtime through sysfs device attributes.
48  */
49 #define IPR_MAX_CMD_PER_LUN				6
50 #define IPR_MAX_CMD_PER_ATA_LUN			1
51 
52 /*
53  * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
54  *	ops the mid-layer can send to the adapter.
55  */
56 #define IPR_NUM_BASE_CMD_BLKS				100
57 
58 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E	0x0339
59 
60 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2          0x033D
61 #define PCI_DEVICE_ID_IBM_CROC_ASIC_E2          0x034A
62 
63 #define IPR_SUBS_DEV_ID_2780	0x0264
64 #define IPR_SUBS_DEV_ID_5702	0x0266
65 #define IPR_SUBS_DEV_ID_5703	0x0278
66 #define IPR_SUBS_DEV_ID_572E	0x028D
67 #define IPR_SUBS_DEV_ID_573E	0x02D3
68 #define IPR_SUBS_DEV_ID_573D	0x02D4
69 #define IPR_SUBS_DEV_ID_571A	0x02C0
70 #define IPR_SUBS_DEV_ID_571B	0x02BE
71 #define IPR_SUBS_DEV_ID_571E	0x02BF
72 #define IPR_SUBS_DEV_ID_571F	0x02D5
73 #define IPR_SUBS_DEV_ID_572A	0x02C1
74 #define IPR_SUBS_DEV_ID_572B	0x02C2
75 #define IPR_SUBS_DEV_ID_572F	0x02C3
76 #define IPR_SUBS_DEV_ID_574E	0x030A
77 #define IPR_SUBS_DEV_ID_575B	0x030D
78 #define IPR_SUBS_DEV_ID_575C	0x0338
79 #define IPR_SUBS_DEV_ID_57B3	0x033A
80 #define IPR_SUBS_DEV_ID_57B7	0x0360
81 #define IPR_SUBS_DEV_ID_57B8	0x02C2
82 
83 #define IPR_SUBS_DEV_ID_57B4    0x033B
84 #define IPR_SUBS_DEV_ID_57B2    0x035F
85 #define IPR_SUBS_DEV_ID_57C4    0x0354
86 #define IPR_SUBS_DEV_ID_57C6    0x0357
87 #define IPR_SUBS_DEV_ID_57CC    0x035C
88 
89 #define IPR_SUBS_DEV_ID_57B5    0x033C
90 #define IPR_SUBS_DEV_ID_57CE    0x035E
91 #define IPR_SUBS_DEV_ID_57B1    0x0355
92 
93 #define IPR_SUBS_DEV_ID_574D    0x0356
94 #define IPR_SUBS_DEV_ID_575D    0x035D
95 
96 #define IPR_NAME				"ipr"
97 
98 /*
99  * Return codes
100  */
101 #define IPR_RC_JOB_CONTINUE		1
102 #define IPR_RC_JOB_RETURN		2
103 
104 /*
105  * IOASCs
106  */
107 #define IPR_IOASC_NR_INIT_CMD_REQUIRED		0x02040200
108 #define IPR_IOASC_NR_IOA_RESET_REQUIRED		0x02048000
109 #define IPR_IOASC_SYNC_REQUIRED			0x023f0000
110 #define IPR_IOASC_MED_DO_NOT_REALLOC		0x03110C00
111 #define IPR_IOASC_HW_SEL_TIMEOUT			0x04050000
112 #define IPR_IOASC_HW_DEV_BUS_STATUS			0x04448500
113 #define	IPR_IOASC_IOASC_MASK			0xFFFFFF00
114 #define	IPR_IOASC_SCSI_STATUS_MASK		0x000000FF
115 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT	0x05240000
116 #define IPR_IOASC_IR_RESOURCE_HANDLE		0x05250000
117 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA		0x05258100
118 #define IPR_IOASA_IR_DUAL_IOA_DISABLED		0x052C8000
119 #define IPR_IOASC_BUS_WAS_RESET			0x06290000
120 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER		0x06298000
121 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST	0x0B5A0000
122 
123 #define IPR_FIRST_DRIVER_IOASC			0x10000000
124 #define IPR_IOASC_IOA_WAS_RESET			0x10000001
125 #define IPR_IOASC_PCI_ACCESS_ERROR			0x10000002
126 
127 /* Driver data flags */
128 #define IPR_USE_LONG_TRANSOP_TIMEOUT		0x00000001
129 #define IPR_USE_PCI_WARM_RESET			0x00000002
130 
131 #define IPR_DEFAULT_MAX_ERROR_DUMP			984
132 #define IPR_NUM_LOG_HCAMS				2
133 #define IPR_NUM_CFG_CHG_HCAMS				2
134 #define IPR_NUM_HCAMS	(IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
135 
136 #define IPR_MAX_SIS64_TARGETS_PER_BUS			1024
137 #define IPR_MAX_SIS64_LUNS_PER_TARGET			0xffffffff
138 
139 #define IPR_MAX_NUM_TARGETS_PER_BUS			256
140 #define IPR_MAX_NUM_LUNS_PER_TARGET			256
141 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET	8
142 #define IPR_VSET_BUS					0xff
143 #define IPR_IOA_BUS						0xff
144 #define IPR_IOA_TARGET					0xff
145 #define IPR_IOA_LUN						0xff
146 #define IPR_MAX_NUM_BUSES				16
147 #define IPR_MAX_BUS_TO_SCAN				IPR_MAX_NUM_BUSES
148 
149 #define IPR_NUM_RESET_RELOAD_RETRIES		3
150 
151 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
152 #define IPR_NUM_INTERNAL_CMD_BLKS	(IPR_NUM_HCAMS + \
153                                      ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
154 
155 #define IPR_MAX_COMMANDS		IPR_NUM_BASE_CMD_BLKS
156 #define IPR_NUM_CMD_BLKS		(IPR_NUM_BASE_CMD_BLKS + \
157 						IPR_NUM_INTERNAL_CMD_BLKS)
158 
159 #define IPR_MAX_PHYSICAL_DEVS				192
160 #define IPR_DEFAULT_SIS64_DEVS				1024
161 #define IPR_MAX_SIS64_DEVS				4096
162 
163 #define IPR_MAX_SGLIST					64
164 #define IPR_IOA_MAX_SECTORS				32767
165 #define IPR_VSET_MAX_SECTORS				512
166 #define IPR_MAX_CDB_LEN					16
167 #define IPR_MAX_HRRQ_RETRIES				3
168 
169 #define IPR_DEFAULT_BUS_WIDTH				16
170 #define IPR_80MBs_SCSI_RATE		((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
171 #define IPR_U160_SCSI_RATE	((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
172 #define IPR_U320_SCSI_RATE	((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
173 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
174 
175 #define IPR_IOA_RES_HANDLE				0xffffffff
176 #define IPR_INVALID_RES_HANDLE			0
177 #define IPR_IOA_RES_ADDR				0x00ffffff
178 
179 /*
180  * Adapter Commands
181  */
182 #define IPR_QUERY_RSRC_STATE				0xC2
183 #define IPR_RESET_DEVICE				0xC3
184 #define	IPR_RESET_TYPE_SELECT				0x80
185 #define	IPR_LUN_RESET					0x40
186 #define	IPR_TARGET_RESET					0x20
187 #define	IPR_BUS_RESET					0x10
188 #define	IPR_ATA_PHY_RESET					0x80
189 #define IPR_ID_HOST_RR_Q				0xC4
190 #define IPR_QUERY_IOA_CONFIG				0xC5
191 #define IPR_CANCEL_ALL_REQUESTS			0xCE
192 #define IPR_HOST_CONTROLLED_ASYNC			0xCF
193 #define	IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE	0x01
194 #define	IPR_HCAM_CDB_OP_CODE_LOG_DATA		0x02
195 #define IPR_SET_SUPPORTED_DEVICES			0xFB
196 #define IPR_SET_ALL_SUPPORTED_DEVICES			0x80
197 #define IPR_IOA_SHUTDOWN				0xF7
198 #define	IPR_WR_BUF_DOWNLOAD_AND_SAVE			0x05
199 
200 /*
201  * Timeouts
202  */
203 #define IPR_SHUTDOWN_TIMEOUT			(ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
204 #define IPR_VSET_RW_TIMEOUT			(ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
205 #define IPR_ABBREV_SHUTDOWN_TIMEOUT		(10 * HZ)
206 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO	(2 * 60 * HZ)
207 #define IPR_DEVICE_RESET_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)
208 #define IPR_CANCEL_ALL_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)
209 #define IPR_ABORT_TASK_TIMEOUT		(ipr_fastfail ? 10 * HZ : 30 * HZ)
210 #define IPR_INTERNAL_TIMEOUT			(ipr_fastfail ? 10 * HZ : 30 * HZ)
211 #define IPR_WRITE_BUFFER_TIMEOUT		(10 * 60 * HZ)
212 #define IPR_SET_SUP_DEVICE_TIMEOUT		(2 * 60 * HZ)
213 #define IPR_REQUEST_SENSE_TIMEOUT		(10 * HZ)
214 #define IPR_OPERATIONAL_TIMEOUT		(5 * 60)
215 #define IPR_LONG_OPERATIONAL_TIMEOUT	(12 * 60)
216 #define IPR_WAIT_FOR_RESET_TIMEOUT		(2 * HZ)
217 #define IPR_CHECK_FOR_RESET_TIMEOUT		(HZ / 10)
218 #define IPR_WAIT_FOR_BIST_TIMEOUT		(2 * HZ)
219 #define IPR_PCI_RESET_TIMEOUT			(HZ / 2)
220 #define IPR_SIS32_DUMP_TIMEOUT			(15 * HZ)
221 #define IPR_SIS64_DUMP_TIMEOUT			(40 * HZ)
222 #define IPR_DUMP_DELAY_SECONDS			4
223 #define IPR_DUMP_DELAY_TIMEOUT			(IPR_DUMP_DELAY_SECONDS * HZ)
224 
225 /*
226  * SCSI Literals
227  */
228 #define IPR_VENDOR_ID_LEN			8
229 #define IPR_PROD_ID_LEN				16
230 #define IPR_SERIAL_NUM_LEN			8
231 
232 /*
233  * Hardware literals
234  */
235 #define IPR_FMT2_MBX_ADDR_MASK				0x0fffffff
236 #define IPR_FMT2_MBX_BAR_SEL_MASK			0xf0000000
237 #define IPR_FMT2_MKR_BAR_SEL_SHIFT			28
238 #define IPR_GET_FMT2_BAR_SEL(mbx) \
239 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
240 #define IPR_SDT_FMT2_BAR0_SEL				0x0
241 #define IPR_SDT_FMT2_BAR1_SEL				0x1
242 #define IPR_SDT_FMT2_BAR2_SEL				0x2
243 #define IPR_SDT_FMT2_BAR3_SEL				0x3
244 #define IPR_SDT_FMT2_BAR4_SEL				0x4
245 #define IPR_SDT_FMT2_BAR5_SEL				0x5
246 #define IPR_SDT_FMT2_EXP_ROM_SEL			0x8
247 #define IPR_FMT2_SDT_READY_TO_USE			0xC4D4E3F2
248 #define IPR_FMT3_SDT_READY_TO_USE			0xC4D4E3F3
249 #define IPR_DOORBELL					0x82800000
250 #define IPR_RUNTIME_RESET				0x40000000
251 
252 #define IPR_IPL_INIT_MIN_STAGE_TIME			5
253 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME                 15
254 #define IPR_IPL_INIT_STAGE_UNKNOWN			0x0
255 #define IPR_IPL_INIT_STAGE_TRANSOP			0xB0000000
256 #define IPR_IPL_INIT_STAGE_MASK				0xff000000
257 #define IPR_IPL_INIT_STAGE_TIME_MASK			0x0000ffff
258 #define IPR_PCII_IPL_STAGE_CHANGE			(0x80000000 >> 0)
259 
260 #define IPR_PCII_IOA_TRANS_TO_OPER			(0x80000000 >> 0)
261 #define IPR_PCII_IOARCB_XFER_FAILED			(0x80000000 >> 3)
262 #define IPR_PCII_IOA_UNIT_CHECKED			(0x80000000 >> 4)
263 #define IPR_PCII_NO_HOST_RRQ				(0x80000000 >> 5)
264 #define IPR_PCII_CRITICAL_OPERATION			(0x80000000 >> 6)
265 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE		(0x80000000 >> 7)
266 #define IPR_PCII_IOARRIN_LOST				(0x80000000 >> 27)
267 #define IPR_PCII_MMIO_ERROR				(0x80000000 >> 28)
268 #define IPR_PCII_PROC_ERR_STATE			(0x80000000 >> 29)
269 #define IPR_PCII_HRRQ_UPDATED				(0x80000000 >> 30)
270 #define IPR_PCII_CORE_ISSUED_RST_REQ		(0x80000000 >> 31)
271 
272 #define IPR_PCII_ERROR_INTERRUPTS \
273 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
274 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
275 
276 #define IPR_PCII_OPER_INTERRUPTS \
277 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
278 
279 #define IPR_UPROCI_RESET_ALERT			(0x80000000 >> 7)
280 #define IPR_UPROCI_IO_DEBUG_ALERT			(0x80000000 >> 9)
281 #define IPR_UPROCI_SIS64_START_BIST			(0x80000000 >> 23)
282 
283 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC		200000	/* 200 ms */
284 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC		200000	/* 200 ms */
285 
286 /*
287  * Dump literals
288  */
289 #define IPR_FMT2_MAX_IOA_DUMP_SIZE			(4 * 1024 * 1024)
290 #define IPR_FMT3_MAX_IOA_DUMP_SIZE			(32 * 1024 * 1024)
291 #define IPR_FMT2_NUM_SDT_ENTRIES			511
292 #define IPR_FMT3_NUM_SDT_ENTRIES			0xFFF
293 #define IPR_FMT2_MAX_NUM_DUMP_PAGES	((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
294 #define IPR_FMT3_MAX_NUM_DUMP_PAGES	((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
295 
296 /*
297  * Misc literals
298  */
299 #define IPR_NUM_IOADL_ENTRIES			IPR_MAX_SGLIST
300 
301 /*
302  * Adapter interface types
303  */
304 
305 struct ipr_res_addr {
306 	u8 reserved;
307 	u8 bus;
308 	u8 target;
309 	u8 lun;
310 #define IPR_GET_PHYS_LOC(res_addr) \
311 	(((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
312 }__attribute__((packed, aligned (4)));
313 
314 struct ipr_std_inq_vpids {
315 	u8 vendor_id[IPR_VENDOR_ID_LEN];
316 	u8 product_id[IPR_PROD_ID_LEN];
317 }__attribute__((packed));
318 
319 struct ipr_vpd {
320 	struct ipr_std_inq_vpids vpids;
321 	u8 sn[IPR_SERIAL_NUM_LEN];
322 }__attribute__((packed));
323 
324 struct ipr_ext_vpd {
325 	struct ipr_vpd vpd;
326 	__be32 wwid[2];
327 }__attribute__((packed));
328 
329 struct ipr_ext_vpd64 {
330 	struct ipr_vpd vpd;
331 	__be32 wwid[4];
332 }__attribute__((packed));
333 
334 struct ipr_std_inq_data {
335 	u8 peri_qual_dev_type;
336 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
337 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
338 
339 	u8 removeable_medium_rsvd;
340 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
341 
342 #define IPR_IS_DASD_DEVICE(std_inq) \
343 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
344 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
345 
346 #define IPR_IS_SES_DEVICE(std_inq) \
347 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
348 
349 	u8 version;
350 	u8 aen_naca_fmt;
351 	u8 additional_len;
352 	u8 sccs_rsvd;
353 	u8 bq_enc_multi;
354 	u8 sync_cmdq_flags;
355 
356 	struct ipr_std_inq_vpids vpids;
357 
358 	u8 ros_rsvd_ram_rsvd[4];
359 
360 	u8 serial_num[IPR_SERIAL_NUM_LEN];
361 }__attribute__ ((packed));
362 
363 #define IPR_RES_TYPE_AF_DASD		0x00
364 #define IPR_RES_TYPE_GENERIC_SCSI	0x01
365 #define IPR_RES_TYPE_VOLUME_SET		0x02
366 #define IPR_RES_TYPE_REMOTE_AF_DASD	0x03
367 #define IPR_RES_TYPE_GENERIC_ATA	0x04
368 #define IPR_RES_TYPE_ARRAY		0x05
369 #define IPR_RES_TYPE_IOAFP		0xff
370 
371 struct ipr_config_table_entry {
372 	u8 proto;
373 #define IPR_PROTO_SATA			0x02
374 #define IPR_PROTO_SATA_ATAPI		0x03
375 #define IPR_PROTO_SAS_STP		0x06
376 #define IPR_PROTO_SAS_STP_ATAPI		0x07
377 	u8 array_id;
378 	u8 flags;
379 #define IPR_IS_IOA_RESOURCE		0x80
380 	u8 rsvd_subtype;
381 
382 #define IPR_QUEUEING_MODEL(res)	((((res)->flags) & 0x70) >> 4)
383 #define IPR_QUEUE_FROZEN_MODEL		0
384 #define IPR_QUEUE_NACA_MODEL		1
385 
386 	struct ipr_res_addr res_addr;
387 	__be32 res_handle;
388 	__be32 lun_wwn[2];
389 	struct ipr_std_inq_data std_inq_data;
390 }__attribute__ ((packed, aligned (4)));
391 
392 struct ipr_config_table_entry64 {
393 	u8 res_type;
394 	u8 proto;
395 	u8 vset_num;
396 	u8 array_id;
397 	__be16 flags;
398 	__be16 res_flags;
399 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
400 	__be32 res_handle;
401 	u8 dev_id_type;
402 	u8 reserved[3];
403 	__be64 dev_id;
404 	__be64 lun;
405 	__be64 lun_wwn[2];
406 #define IPR_MAX_RES_PATH_LENGTH		24
407 	__be64 res_path;
408 	struct ipr_std_inq_data std_inq_data;
409 	u8 reserved2[4];
410 	__be64 reserved3[2];
411 	u8 reserved4[8];
412 }__attribute__ ((packed, aligned (8)));
413 
414 struct ipr_config_table_hdr {
415 	u8 num_entries;
416 	u8 flags;
417 #define IPR_UCODE_DOWNLOAD_REQ	0x10
418 	__be16 reserved;
419 }__attribute__((packed, aligned (4)));
420 
421 struct ipr_config_table_hdr64 {
422 	__be16 num_entries;
423 	__be16 reserved;
424 	u8 flags;
425 	u8 reserved2[11];
426 }__attribute__((packed, aligned (4)));
427 
428 struct ipr_config_table {
429 	struct ipr_config_table_hdr hdr;
430 	struct ipr_config_table_entry dev[0];
431 }__attribute__((packed, aligned (4)));
432 
433 struct ipr_config_table64 {
434 	struct ipr_config_table_hdr64 hdr64;
435 	struct ipr_config_table_entry64 dev[0];
436 }__attribute__((packed, aligned (8)));
437 
438 struct ipr_config_table_entry_wrapper {
439 	union {
440 		struct ipr_config_table_entry *cfgte;
441 		struct ipr_config_table_entry64 *cfgte64;
442 	} u;
443 };
444 
445 struct ipr_hostrcb_cfg_ch_not {
446 	union {
447 		struct ipr_config_table_entry cfgte;
448 		struct ipr_config_table_entry64 cfgte64;
449 	} u;
450 	u8 reserved[936];
451 }__attribute__((packed, aligned (4)));
452 
453 struct ipr_supported_device {
454 	__be16 data_length;
455 	u8 reserved;
456 	u8 num_records;
457 	struct ipr_std_inq_vpids vpids;
458 	u8 reserved2[16];
459 }__attribute__((packed, aligned (4)));
460 
461 /* Command packet structure */
462 struct ipr_cmd_pkt {
463 	__be16 reserved;		/* Reserved by IOA */
464 	u8 request_type;
465 #define IPR_RQTYPE_SCSICDB		0x00
466 #define IPR_RQTYPE_IOACMD		0x01
467 #define IPR_RQTYPE_HCAM			0x02
468 #define IPR_RQTYPE_ATA_PASSTHRU	0x04
469 
470 	u8 reserved2;
471 
472 	u8 flags_hi;
473 #define IPR_FLAGS_HI_WRITE_NOT_READ		0x80
474 #define IPR_FLAGS_HI_NO_ULEN_CHK		0x20
475 #define IPR_FLAGS_HI_SYNC_OVERRIDE		0x10
476 #define IPR_FLAGS_HI_SYNC_COMPLETE		0x08
477 #define IPR_FLAGS_HI_NO_LINK_DESC		0x04
478 
479 	u8 flags_lo;
480 #define IPR_FLAGS_LO_ALIGNED_BFR		0x20
481 #define IPR_FLAGS_LO_DELAY_AFTER_RST		0x10
482 #define IPR_FLAGS_LO_UNTAGGED_TASK		0x00
483 #define IPR_FLAGS_LO_SIMPLE_TASK		0x02
484 #define IPR_FLAGS_LO_ORDERED_TASK		0x04
485 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK		0x06
486 #define IPR_FLAGS_LO_ACA_TASK			0x08
487 
488 	u8 cdb[16];
489 	__be16 timeout;
490 }__attribute__ ((packed, aligned(4)));
491 
492 struct ipr_ioarcb_ata_regs {	/* 22 bytes */
493 	u8 flags;
494 #define IPR_ATA_FLAG_PACKET_CMD			0x80
495 #define IPR_ATA_FLAG_XFER_TYPE_DMA			0x40
496 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION	0x20
497 	u8 reserved[3];
498 
499 	__be16 data;
500 	u8 feature;
501 	u8 nsect;
502 	u8 lbal;
503 	u8 lbam;
504 	u8 lbah;
505 	u8 device;
506 	u8 command;
507 	u8 reserved2[3];
508 	u8 hob_feature;
509 	u8 hob_nsect;
510 	u8 hob_lbal;
511 	u8 hob_lbam;
512 	u8 hob_lbah;
513 	u8 ctl;
514 }__attribute__ ((packed, aligned(4)));
515 
516 struct ipr_ioadl_desc {
517 	__be32 flags_and_data_len;
518 #define IPR_IOADL_FLAGS_MASK		0xff000000
519 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
520 #define IPR_IOADL_DATA_LEN_MASK		0x00ffffff
521 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
522 #define IPR_IOADL_FLAGS_READ		0x48000000
523 #define IPR_IOADL_FLAGS_READ_LAST	0x49000000
524 #define IPR_IOADL_FLAGS_WRITE		0x68000000
525 #define IPR_IOADL_FLAGS_WRITE_LAST	0x69000000
526 #define IPR_IOADL_FLAGS_LAST		0x01000000
527 
528 	__be32 address;
529 }__attribute__((packed, aligned (8)));
530 
531 struct ipr_ioadl64_desc {
532 	__be32 flags;
533 	__be32 data_len;
534 	__be64 address;
535 }__attribute__((packed, aligned (16)));
536 
537 struct ipr_ata64_ioadl {
538 	struct ipr_ioarcb_ata_regs regs;
539 	u16 reserved[5];
540 	struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
541 }__attribute__((packed, aligned (16)));
542 
543 struct ipr_ioarcb_add_data {
544 	union {
545 		struct ipr_ioarcb_ata_regs regs;
546 		struct ipr_ioadl_desc ioadl[5];
547 		__be32 add_cmd_parms[10];
548 	} u;
549 }__attribute__ ((packed, aligned (4)));
550 
551 struct ipr_ioarcb_sis64_add_addr_ecb {
552 	__be64 ioasa_host_pci_addr;
553 	__be64 data_ioadl_addr;
554 	__be64 reserved;
555 	__be32 ext_control_buf[4];
556 }__attribute__((packed, aligned (8)));
557 
558 /* IOA Request Control Block    128 bytes  */
559 struct ipr_ioarcb {
560 	union {
561 		__be32 ioarcb_host_pci_addr;
562 		__be64 ioarcb_host_pci_addr64;
563 	} a;
564 	__be32 res_handle;
565 	__be32 host_response_handle;
566 	__be32 reserved1;
567 	__be32 reserved2;
568 	__be32 reserved3;
569 
570 	__be32 data_transfer_length;
571 	__be32 read_data_transfer_length;
572 	__be32 write_ioadl_addr;
573 	__be32 ioadl_len;
574 	__be32 read_ioadl_addr;
575 	__be32 read_ioadl_len;
576 
577 	__be32 ioasa_host_pci_addr;
578 	__be16 ioasa_len;
579 	__be16 reserved4;
580 
581 	struct ipr_cmd_pkt cmd_pkt;
582 
583 	__be16 add_cmd_parms_offset;
584 	__be16 add_cmd_parms_len;
585 
586 	union {
587 		struct ipr_ioarcb_add_data add_data;
588 		struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
589 	} u;
590 
591 }__attribute__((packed, aligned (4)));
592 
593 struct ipr_ioasa_vset {
594 	__be32 failing_lba_hi;
595 	__be32 failing_lba_lo;
596 	__be32 reserved;
597 }__attribute__((packed, aligned (4)));
598 
599 struct ipr_ioasa_af_dasd {
600 	__be32 failing_lba;
601 	__be32 reserved[2];
602 }__attribute__((packed, aligned (4)));
603 
604 struct ipr_ioasa_gpdd {
605 	u8 end_state;
606 	u8 bus_phase;
607 	__be16 reserved;
608 	__be32 ioa_data[2];
609 }__attribute__((packed, aligned (4)));
610 
611 struct ipr_ioasa_gata {
612 	u8 error;
613 	u8 nsect;		/* Interrupt reason */
614 	u8 lbal;
615 	u8 lbam;
616 	u8 lbah;
617 	u8 device;
618 	u8 status;
619 	u8 alt_status;	/* ATA CTL */
620 	u8 hob_nsect;
621 	u8 hob_lbal;
622 	u8 hob_lbam;
623 	u8 hob_lbah;
624 }__attribute__((packed, aligned (4)));
625 
626 struct ipr_auto_sense {
627 	__be16 auto_sense_len;
628 	__be16 ioa_data_len;
629 	__be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
630 };
631 
632 struct ipr_ioasa_hdr {
633 	__be32 ioasc;
634 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
635 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
636 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
637 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
638 
639 	__be16 ret_stat_len;	/* Length of the returned IOASA */
640 
641 	__be16 avail_stat_len;	/* Total Length of status available. */
642 
643 	__be32 residual_data_len;	/* number of bytes in the host data */
644 	/* buffers that were not used by the IOARCB command. */
645 
646 	__be32 ilid;
647 #define IPR_NO_ILID			0
648 #define IPR_DRIVER_ILID		0xffffffff
649 
650 	__be32 fd_ioasc;
651 
652 	__be32 fd_phys_locator;
653 
654 	__be32 fd_res_handle;
655 
656 	__be32 ioasc_specific;	/* status code specific field */
657 #define IPR_ADDITIONAL_STATUS_FMT		0x80000000
658 #define IPR_AUTOSENSE_VALID			0x40000000
659 #define IPR_ATA_DEVICE_WAS_RESET		0x20000000
660 #define IPR_IOASC_SPECIFIC_MASK		0x00ffffff
661 #define IPR_FIELD_POINTER_VALID		(0x80000000 >> 8)
662 #define IPR_FIELD_POINTER_MASK		0x0000ffff
663 
664 }__attribute__((packed, aligned (4)));
665 
666 struct ipr_ioasa {
667 	struct ipr_ioasa_hdr hdr;
668 
669 	union {
670 		struct ipr_ioasa_vset vset;
671 		struct ipr_ioasa_af_dasd dasd;
672 		struct ipr_ioasa_gpdd gpdd;
673 		struct ipr_ioasa_gata gata;
674 	} u;
675 
676 	struct ipr_auto_sense auto_sense;
677 }__attribute__((packed, aligned (4)));
678 
679 struct ipr_ioasa64 {
680 	struct ipr_ioasa_hdr hdr;
681 	u8 fd_res_path[8];
682 
683 	union {
684 		struct ipr_ioasa_vset vset;
685 		struct ipr_ioasa_af_dasd dasd;
686 		struct ipr_ioasa_gpdd gpdd;
687 		struct ipr_ioasa_gata gata;
688 	} u;
689 
690 	struct ipr_auto_sense auto_sense;
691 }__attribute__((packed, aligned (4)));
692 
693 struct ipr_mode_parm_hdr {
694 	u8 length;
695 	u8 medium_type;
696 	u8 device_spec_parms;
697 	u8 block_desc_len;
698 }__attribute__((packed));
699 
700 struct ipr_mode_pages {
701 	struct ipr_mode_parm_hdr hdr;
702 	u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
703 }__attribute__((packed));
704 
705 struct ipr_mode_page_hdr {
706 	u8 ps_page_code;
707 #define IPR_MODE_PAGE_PS	0x80
708 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
709 	u8 page_length;
710 }__attribute__ ((packed));
711 
712 struct ipr_dev_bus_entry {
713 	struct ipr_res_addr res_addr;
714 	u8 flags;
715 #define IPR_SCSI_ATTR_ENABLE_QAS			0x80
716 #define IPR_SCSI_ATTR_DISABLE_QAS			0x40
717 #define IPR_SCSI_ATTR_QAS_MASK				0xC0
718 #define IPR_SCSI_ATTR_ENABLE_TM				0x20
719 #define IPR_SCSI_ATTR_NO_TERM_PWR			0x10
720 #define IPR_SCSI_ATTR_TM_SUPPORTED			0x08
721 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED	0x04
722 
723 	u8 scsi_id;
724 	u8 bus_width;
725 	u8 extended_reset_delay;
726 #define IPR_EXTENDED_RESET_DELAY	7
727 
728 	__be32 max_xfer_rate;
729 
730 	u8 spinup_delay;
731 	u8 reserved3;
732 	__be16 reserved4;
733 }__attribute__((packed, aligned (4)));
734 
735 struct ipr_mode_page28 {
736 	struct ipr_mode_page_hdr hdr;
737 	u8 num_entries;
738 	u8 entry_length;
739 	struct ipr_dev_bus_entry bus[0];
740 }__attribute__((packed));
741 
742 struct ipr_mode_page24 {
743 	struct ipr_mode_page_hdr hdr;
744 	u8 flags;
745 #define IPR_ENABLE_DUAL_IOA_AF 0x80
746 }__attribute__((packed));
747 
748 struct ipr_ioa_vpd {
749 	struct ipr_std_inq_data std_inq_data;
750 	u8 ascii_part_num[12];
751 	u8 reserved[40];
752 	u8 ascii_plant_code[4];
753 }__attribute__((packed));
754 
755 struct ipr_inquiry_page3 {
756 	u8 peri_qual_dev_type;
757 	u8 page_code;
758 	u8 reserved1;
759 	u8 page_length;
760 	u8 ascii_len;
761 	u8 reserved2[3];
762 	u8 load_id[4];
763 	u8 major_release;
764 	u8 card_type;
765 	u8 minor_release[2];
766 	u8 ptf_number[4];
767 	u8 patch_number[4];
768 }__attribute__((packed));
769 
770 struct ipr_inquiry_cap {
771 	u8 peri_qual_dev_type;
772 	u8 page_code;
773 	u8 reserved1;
774 	u8 page_length;
775 	u8 ascii_len;
776 	u8 reserved2;
777 	u8 sis_version[2];
778 	u8 cap;
779 #define IPR_CAP_DUAL_IOA_RAID		0x80
780 	u8 reserved3[15];
781 }__attribute__((packed));
782 
783 #define IPR_INQUIRY_PAGE0_ENTRIES 20
784 struct ipr_inquiry_page0 {
785 	u8 peri_qual_dev_type;
786 	u8 page_code;
787 	u8 reserved1;
788 	u8 len;
789 	u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
790 }__attribute__((packed));
791 
792 struct ipr_hostrcb_device_data_entry {
793 	struct ipr_vpd vpd;
794 	struct ipr_res_addr dev_res_addr;
795 	struct ipr_vpd new_vpd;
796 	struct ipr_vpd ioa_last_with_dev_vpd;
797 	struct ipr_vpd cfc_last_with_dev_vpd;
798 	__be32 ioa_data[5];
799 }__attribute__((packed, aligned (4)));
800 
801 struct ipr_hostrcb_device_data_entry_enhanced {
802 	struct ipr_ext_vpd vpd;
803 	u8 ccin[4];
804 	struct ipr_res_addr dev_res_addr;
805 	struct ipr_ext_vpd new_vpd;
806 	u8 new_ccin[4];
807 	struct ipr_ext_vpd ioa_last_with_dev_vpd;
808 	struct ipr_ext_vpd cfc_last_with_dev_vpd;
809 }__attribute__((packed, aligned (4)));
810 
811 struct ipr_hostrcb64_device_data_entry_enhanced {
812 	struct ipr_ext_vpd vpd;
813 	u8 ccin[4];
814 	u8 res_path[8];
815 	struct ipr_ext_vpd new_vpd;
816 	u8 new_ccin[4];
817 	struct ipr_ext_vpd ioa_last_with_dev_vpd;
818 	struct ipr_ext_vpd cfc_last_with_dev_vpd;
819 }__attribute__((packed, aligned (4)));
820 
821 struct ipr_hostrcb_array_data_entry {
822 	struct ipr_vpd vpd;
823 	struct ipr_res_addr expected_dev_res_addr;
824 	struct ipr_res_addr dev_res_addr;
825 }__attribute__((packed, aligned (4)));
826 
827 struct ipr_hostrcb64_array_data_entry {
828 	struct ipr_ext_vpd vpd;
829 	u8 ccin[4];
830 	u8 expected_res_path[8];
831 	u8 res_path[8];
832 }__attribute__((packed, aligned (4)));
833 
834 struct ipr_hostrcb_array_data_entry_enhanced {
835 	struct ipr_ext_vpd vpd;
836 	u8 ccin[4];
837 	struct ipr_res_addr expected_dev_res_addr;
838 	struct ipr_res_addr dev_res_addr;
839 }__attribute__((packed, aligned (4)));
840 
841 struct ipr_hostrcb_type_ff_error {
842 	__be32 ioa_data[758];
843 }__attribute__((packed, aligned (4)));
844 
845 struct ipr_hostrcb_type_01_error {
846 	__be32 seek_counter;
847 	__be32 read_counter;
848 	u8 sense_data[32];
849 	__be32 ioa_data[236];
850 }__attribute__((packed, aligned (4)));
851 
852 struct ipr_hostrcb_type_02_error {
853 	struct ipr_vpd ioa_vpd;
854 	struct ipr_vpd cfc_vpd;
855 	struct ipr_vpd ioa_last_attached_to_cfc_vpd;
856 	struct ipr_vpd cfc_last_attached_to_ioa_vpd;
857 	__be32 ioa_data[3];
858 }__attribute__((packed, aligned (4)));
859 
860 struct ipr_hostrcb_type_12_error {
861 	struct ipr_ext_vpd ioa_vpd;
862 	struct ipr_ext_vpd cfc_vpd;
863 	struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
864 	struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
865 	__be32 ioa_data[3];
866 }__attribute__((packed, aligned (4)));
867 
868 struct ipr_hostrcb_type_03_error {
869 	struct ipr_vpd ioa_vpd;
870 	struct ipr_vpd cfc_vpd;
871 	__be32 errors_detected;
872 	__be32 errors_logged;
873 	u8 ioa_data[12];
874 	struct ipr_hostrcb_device_data_entry dev[3];
875 }__attribute__((packed, aligned (4)));
876 
877 struct ipr_hostrcb_type_13_error {
878 	struct ipr_ext_vpd ioa_vpd;
879 	struct ipr_ext_vpd cfc_vpd;
880 	__be32 errors_detected;
881 	__be32 errors_logged;
882 	struct ipr_hostrcb_device_data_entry_enhanced dev[3];
883 }__attribute__((packed, aligned (4)));
884 
885 struct ipr_hostrcb_type_23_error {
886 	struct ipr_ext_vpd ioa_vpd;
887 	struct ipr_ext_vpd cfc_vpd;
888 	__be32 errors_detected;
889 	__be32 errors_logged;
890 	struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
891 }__attribute__((packed, aligned (4)));
892 
893 struct ipr_hostrcb_type_04_error {
894 	struct ipr_vpd ioa_vpd;
895 	struct ipr_vpd cfc_vpd;
896 	u8 ioa_data[12];
897 	struct ipr_hostrcb_array_data_entry array_member[10];
898 	__be32 exposed_mode_adn;
899 	__be32 array_id;
900 	struct ipr_vpd incomp_dev_vpd;
901 	__be32 ioa_data2;
902 	struct ipr_hostrcb_array_data_entry array_member2[8];
903 	struct ipr_res_addr last_func_vset_res_addr;
904 	u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
905 	u8 protection_level[8];
906 }__attribute__((packed, aligned (4)));
907 
908 struct ipr_hostrcb_type_14_error {
909 	struct ipr_ext_vpd ioa_vpd;
910 	struct ipr_ext_vpd cfc_vpd;
911 	__be32 exposed_mode_adn;
912 	__be32 array_id;
913 	struct ipr_res_addr last_func_vset_res_addr;
914 	u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
915 	u8 protection_level[8];
916 	__be32 num_entries;
917 	struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
918 }__attribute__((packed, aligned (4)));
919 
920 struct ipr_hostrcb_type_24_error {
921 	struct ipr_ext_vpd ioa_vpd;
922 	struct ipr_ext_vpd cfc_vpd;
923 	u8 reserved[2];
924 	u8 exposed_mode_adn;
925 #define IPR_INVALID_ARRAY_DEV_NUM		0xff
926 	u8 array_id;
927 	u8 last_res_path[8];
928 	u8 protection_level[8];
929 	struct ipr_ext_vpd64 array_vpd;
930 	u8 description[16];
931 	u8 reserved2[3];
932 	u8 num_entries;
933 	struct ipr_hostrcb64_array_data_entry array_member[32];
934 }__attribute__((packed, aligned (4)));
935 
936 struct ipr_hostrcb_type_07_error {
937 	u8 failure_reason[64];
938 	struct ipr_vpd vpd;
939 	u32 data[222];
940 }__attribute__((packed, aligned (4)));
941 
942 struct ipr_hostrcb_type_17_error {
943 	u8 failure_reason[64];
944 	struct ipr_ext_vpd vpd;
945 	u32 data[476];
946 }__attribute__((packed, aligned (4)));
947 
948 struct ipr_hostrcb_config_element {
949 	u8 type_status;
950 #define IPR_PATH_CFG_TYPE_MASK	0xF0
951 #define IPR_PATH_CFG_NOT_EXIST	0x00
952 #define IPR_PATH_CFG_IOA_PORT		0x10
953 #define IPR_PATH_CFG_EXP_PORT		0x20
954 #define IPR_PATH_CFG_DEVICE_PORT	0x30
955 #define IPR_PATH_CFG_DEVICE_LUN	0x40
956 
957 #define IPR_PATH_CFG_STATUS_MASK	0x0F
958 #define IPR_PATH_CFG_NO_PROB		0x00
959 #define IPR_PATH_CFG_DEGRADED		0x01
960 #define IPR_PATH_CFG_FAILED		0x02
961 #define IPR_PATH_CFG_SUSPECT		0x03
962 #define IPR_PATH_NOT_DETECTED		0x04
963 #define IPR_PATH_INCORRECT_CONN	0x05
964 
965 	u8 cascaded_expander;
966 	u8 phy;
967 	u8 link_rate;
968 #define IPR_PHY_LINK_RATE_MASK	0x0F
969 
970 	__be32 wwid[2];
971 }__attribute__((packed, aligned (4)));
972 
973 struct ipr_hostrcb64_config_element {
974 	__be16 length;
975 	u8 descriptor_id;
976 #define IPR_DESCRIPTOR_MASK		0xC0
977 #define IPR_DESCRIPTOR_SIS64		0x00
978 
979 	u8 reserved;
980 	u8 type_status;
981 
982 	u8 reserved2[2];
983 	u8 link_rate;
984 
985 	u8 res_path[8];
986 	__be32 wwid[2];
987 }__attribute__((packed, aligned (8)));
988 
989 struct ipr_hostrcb_fabric_desc {
990 	__be16 length;
991 	u8 ioa_port;
992 	u8 cascaded_expander;
993 	u8 phy;
994 	u8 path_state;
995 #define IPR_PATH_ACTIVE_MASK		0xC0
996 #define IPR_PATH_NO_INFO		0x00
997 #define IPR_PATH_ACTIVE			0x40
998 #define IPR_PATH_NOT_ACTIVE		0x80
999 
1000 #define IPR_PATH_STATE_MASK		0x0F
1001 #define IPR_PATH_STATE_NO_INFO	0x00
1002 #define IPR_PATH_HEALTHY		0x01
1003 #define IPR_PATH_DEGRADED		0x02
1004 #define IPR_PATH_FAILED			0x03
1005 
1006 	__be16 num_entries;
1007 	struct ipr_hostrcb_config_element elem[1];
1008 }__attribute__((packed, aligned (4)));
1009 
1010 struct ipr_hostrcb64_fabric_desc {
1011 	__be16 length;
1012 	u8 descriptor_id;
1013 
1014 	u8 reserved[2];
1015 	u8 path_state;
1016 
1017 	u8 reserved2[2];
1018 	u8 res_path[8];
1019 	u8 reserved3[6];
1020 	__be16 num_entries;
1021 	struct ipr_hostrcb64_config_element elem[1];
1022 }__attribute__((packed, aligned (8)));
1023 
1024 #define for_each_fabric_cfg(fabric, cfg) \
1025 		for (cfg = (fabric)->elem; \
1026 			cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1027 			cfg++)
1028 
1029 struct ipr_hostrcb_type_20_error {
1030 	u8 failure_reason[64];
1031 	u8 reserved[3];
1032 	u8 num_entries;
1033 	struct ipr_hostrcb_fabric_desc desc[1];
1034 }__attribute__((packed, aligned (4)));
1035 
1036 struct ipr_hostrcb_type_30_error {
1037 	u8 failure_reason[64];
1038 	u8 reserved[3];
1039 	u8 num_entries;
1040 	struct ipr_hostrcb64_fabric_desc desc[1];
1041 }__attribute__((packed, aligned (4)));
1042 
1043 struct ipr_hostrcb_error {
1044 	__be32 fd_ioasc;
1045 	struct ipr_res_addr fd_res_addr;
1046 	__be32 fd_res_handle;
1047 	__be32 prc;
1048 	union {
1049 		struct ipr_hostrcb_type_ff_error type_ff_error;
1050 		struct ipr_hostrcb_type_01_error type_01_error;
1051 		struct ipr_hostrcb_type_02_error type_02_error;
1052 		struct ipr_hostrcb_type_03_error type_03_error;
1053 		struct ipr_hostrcb_type_04_error type_04_error;
1054 		struct ipr_hostrcb_type_07_error type_07_error;
1055 		struct ipr_hostrcb_type_12_error type_12_error;
1056 		struct ipr_hostrcb_type_13_error type_13_error;
1057 		struct ipr_hostrcb_type_14_error type_14_error;
1058 		struct ipr_hostrcb_type_17_error type_17_error;
1059 		struct ipr_hostrcb_type_20_error type_20_error;
1060 	} u;
1061 }__attribute__((packed, aligned (4)));
1062 
1063 struct ipr_hostrcb64_error {
1064 	__be32 fd_ioasc;
1065 	__be32 ioa_fw_level;
1066 	__be32 fd_res_handle;
1067 	__be32 prc;
1068 	__be64 fd_dev_id;
1069 	__be64 fd_lun;
1070 	u8 fd_res_path[8];
1071 	__be64 time_stamp;
1072 	u8 reserved[16];
1073 	union {
1074 		struct ipr_hostrcb_type_ff_error type_ff_error;
1075 		struct ipr_hostrcb_type_12_error type_12_error;
1076 		struct ipr_hostrcb_type_17_error type_17_error;
1077 		struct ipr_hostrcb_type_23_error type_23_error;
1078 		struct ipr_hostrcb_type_24_error type_24_error;
1079 		struct ipr_hostrcb_type_30_error type_30_error;
1080 	} u;
1081 }__attribute__((packed, aligned (8)));
1082 
1083 struct ipr_hostrcb_raw {
1084 	__be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1085 }__attribute__((packed, aligned (4)));
1086 
1087 struct ipr_hcam {
1088 	u8 op_code;
1089 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE			0xE1
1090 #define IPR_HOST_RCB_OP_CODE_LOG_DATA				0xE2
1091 
1092 	u8 notify_type;
1093 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED	0x00
1094 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY			0x01
1095 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY			0x02
1096 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY		0x10
1097 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY	0x11
1098 
1099 	u8 notifications_lost;
1100 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST			0
1101 #define IPR_HOST_RCB_NOTIFICATIONS_LOST				0x80
1102 
1103 	u8 flags;
1104 #define IPR_HOSTRCB_INTERNAL_OPER	0x80
1105 #define IPR_HOSTRCB_ERR_RESP_SENT	0x40
1106 
1107 	u8 overlay_id;
1108 #define IPR_HOST_RCB_OVERLAY_ID_1				0x01
1109 #define IPR_HOST_RCB_OVERLAY_ID_2				0x02
1110 #define IPR_HOST_RCB_OVERLAY_ID_3				0x03
1111 #define IPR_HOST_RCB_OVERLAY_ID_4				0x04
1112 #define IPR_HOST_RCB_OVERLAY_ID_6				0x06
1113 #define IPR_HOST_RCB_OVERLAY_ID_7				0x07
1114 #define IPR_HOST_RCB_OVERLAY_ID_12				0x12
1115 #define IPR_HOST_RCB_OVERLAY_ID_13				0x13
1116 #define IPR_HOST_RCB_OVERLAY_ID_14				0x14
1117 #define IPR_HOST_RCB_OVERLAY_ID_16				0x16
1118 #define IPR_HOST_RCB_OVERLAY_ID_17				0x17
1119 #define IPR_HOST_RCB_OVERLAY_ID_20				0x20
1120 #define IPR_HOST_RCB_OVERLAY_ID_23				0x23
1121 #define IPR_HOST_RCB_OVERLAY_ID_24				0x24
1122 #define IPR_HOST_RCB_OVERLAY_ID_26				0x26
1123 #define IPR_HOST_RCB_OVERLAY_ID_30				0x30
1124 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT				0xFF
1125 
1126 	u8 reserved1[3];
1127 	__be32 ilid;
1128 	__be32 time_since_last_ioa_reset;
1129 	__be32 reserved2;
1130 	__be32 length;
1131 
1132 	union {
1133 		struct ipr_hostrcb_error error;
1134 		struct ipr_hostrcb64_error error64;
1135 		struct ipr_hostrcb_cfg_ch_not ccn;
1136 		struct ipr_hostrcb_raw raw;
1137 	} u;
1138 }__attribute__((packed, aligned (4)));
1139 
1140 struct ipr_hostrcb {
1141 	struct ipr_hcam hcam;
1142 	dma_addr_t hostrcb_dma;
1143 	struct list_head queue;
1144 	struct ipr_ioa_cfg *ioa_cfg;
1145 	char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1146 };
1147 
1148 /* IPR smart dump table structures */
1149 struct ipr_sdt_entry {
1150 	__be32 start_token;
1151 	__be32 end_token;
1152 	u8 reserved[4];
1153 
1154 	u8 flags;
1155 #define IPR_SDT_ENDIAN		0x80
1156 #define IPR_SDT_VALID_ENTRY	0x20
1157 
1158 	u8 resv;
1159 	__be16 priority;
1160 }__attribute__((packed, aligned (4)));
1161 
1162 struct ipr_sdt_header {
1163 	__be32 state;
1164 	__be32 num_entries;
1165 	__be32 num_entries_used;
1166 	__be32 dump_size;
1167 }__attribute__((packed, aligned (4)));
1168 
1169 struct ipr_sdt {
1170 	struct ipr_sdt_header hdr;
1171 	struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1172 }__attribute__((packed, aligned (4)));
1173 
1174 struct ipr_uc_sdt {
1175 	struct ipr_sdt_header hdr;
1176 	struct ipr_sdt_entry entry[1];
1177 }__attribute__((packed, aligned (4)));
1178 
1179 /*
1180  * Driver types
1181  */
1182 struct ipr_bus_attributes {
1183 	u8 bus;
1184 	u8 qas_enabled;
1185 	u8 bus_width;
1186 	u8 reserved;
1187 	u32 max_xfer_rate;
1188 };
1189 
1190 struct ipr_sata_port {
1191 	struct ipr_ioa_cfg *ioa_cfg;
1192 	struct ata_port *ap;
1193 	struct ipr_resource_entry *res;
1194 	struct ipr_ioasa_gata ioasa;
1195 };
1196 
1197 struct ipr_resource_entry {
1198 	u8 needs_sync_complete:1;
1199 	u8 in_erp:1;
1200 	u8 add_to_ml:1;
1201 	u8 del_from_ml:1;
1202 	u8 resetting_device:1;
1203 
1204 	u32 bus;		/* AKA channel */
1205 	u32 target;		/* AKA id */
1206 	u32 lun;
1207 #define IPR_ARRAY_VIRTUAL_BUS			0x1
1208 #define IPR_VSET_VIRTUAL_BUS			0x2
1209 #define IPR_IOAFP_VIRTUAL_BUS			0x3
1210 
1211 #define IPR_GET_RES_PHYS_LOC(res) \
1212 	(((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1213 
1214 	u8 ata_class;
1215 
1216 	u8 flags;
1217 	__be16 res_flags;
1218 
1219 	u8 type;
1220 
1221 	u8 qmodel;
1222 	struct ipr_std_inq_data std_inq_data;
1223 
1224 	__be32 res_handle;
1225 	__be64 dev_id;
1226 	__be64 lun_wwn;
1227 	struct scsi_lun dev_lun;
1228 	u8 res_path[8];
1229 
1230 	struct ipr_ioa_cfg *ioa_cfg;
1231 	struct scsi_device *sdev;
1232 	struct ipr_sata_port *sata_port;
1233 	struct list_head queue;
1234 }; /* struct ipr_resource_entry */
1235 
1236 struct ipr_resource_hdr {
1237 	u16 num_entries;
1238 	u16 reserved;
1239 };
1240 
1241 struct ipr_misc_cbs {
1242 	struct ipr_ioa_vpd ioa_vpd;
1243 	struct ipr_inquiry_page0 page0_data;
1244 	struct ipr_inquiry_page3 page3_data;
1245 	struct ipr_inquiry_cap cap;
1246 	struct ipr_mode_pages mode_pages;
1247 	struct ipr_supported_device supp_dev;
1248 };
1249 
1250 struct ipr_interrupt_offsets {
1251 	unsigned long set_interrupt_mask_reg;
1252 	unsigned long clr_interrupt_mask_reg;
1253 	unsigned long clr_interrupt_mask_reg32;
1254 	unsigned long sense_interrupt_mask_reg;
1255 	unsigned long sense_interrupt_mask_reg32;
1256 	unsigned long clr_interrupt_reg;
1257 	unsigned long clr_interrupt_reg32;
1258 
1259 	unsigned long sense_interrupt_reg;
1260 	unsigned long sense_interrupt_reg32;
1261 	unsigned long ioarrin_reg;
1262 	unsigned long sense_uproc_interrupt_reg;
1263 	unsigned long sense_uproc_interrupt_reg32;
1264 	unsigned long set_uproc_interrupt_reg;
1265 	unsigned long set_uproc_interrupt_reg32;
1266 	unsigned long clr_uproc_interrupt_reg;
1267 	unsigned long clr_uproc_interrupt_reg32;
1268 
1269 	unsigned long init_feedback_reg;
1270 
1271 	unsigned long dump_addr_reg;
1272 	unsigned long dump_data_reg;
1273 
1274 #define IPR_ENDIAN_SWAP_KEY		0x00080800
1275 	unsigned long endian_swap_reg;
1276 };
1277 
1278 struct ipr_interrupts {
1279 	void __iomem *set_interrupt_mask_reg;
1280 	void __iomem *clr_interrupt_mask_reg;
1281 	void __iomem *clr_interrupt_mask_reg32;
1282 	void __iomem *sense_interrupt_mask_reg;
1283 	void __iomem *sense_interrupt_mask_reg32;
1284 	void __iomem *clr_interrupt_reg;
1285 	void __iomem *clr_interrupt_reg32;
1286 
1287 	void __iomem *sense_interrupt_reg;
1288 	void __iomem *sense_interrupt_reg32;
1289 	void __iomem *ioarrin_reg;
1290 	void __iomem *sense_uproc_interrupt_reg;
1291 	void __iomem *sense_uproc_interrupt_reg32;
1292 	void __iomem *set_uproc_interrupt_reg;
1293 	void __iomem *set_uproc_interrupt_reg32;
1294 	void __iomem *clr_uproc_interrupt_reg;
1295 	void __iomem *clr_uproc_interrupt_reg32;
1296 
1297 	void __iomem *init_feedback_reg;
1298 
1299 	void __iomem *dump_addr_reg;
1300 	void __iomem *dump_data_reg;
1301 
1302 	void __iomem *endian_swap_reg;
1303 };
1304 
1305 struct ipr_chip_cfg_t {
1306 	u32 mailbox;
1307 	u8 cache_line_size;
1308 	struct ipr_interrupt_offsets regs;
1309 };
1310 
1311 struct ipr_chip_t {
1312 	u16 vendor;
1313 	u16 device;
1314 	u16 intr_type;
1315 #define IPR_USE_LSI			0x00
1316 #define IPR_USE_MSI			0x01
1317 	u16 sis_type;
1318 #define IPR_SIS32			0x00
1319 #define IPR_SIS64			0x01
1320 	u16 bist_method;
1321 #define IPR_PCI_CFG			0x00
1322 #define IPR_MMIO			0x01
1323 	const struct ipr_chip_cfg_t *cfg;
1324 };
1325 
1326 enum ipr_shutdown_type {
1327 	IPR_SHUTDOWN_NORMAL = 0x00,
1328 	IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1329 	IPR_SHUTDOWN_ABBREV = 0x80,
1330 	IPR_SHUTDOWN_NONE = 0x100
1331 };
1332 
1333 struct ipr_trace_entry {
1334 	u32 time;
1335 
1336 	u8 op_code;
1337 	u8 ata_op_code;
1338 	u8 type;
1339 #define IPR_TRACE_START			0x00
1340 #define IPR_TRACE_FINISH		0xff
1341 	u8 cmd_index;
1342 
1343 	__be32 res_handle;
1344 	union {
1345 		u32 ioasc;
1346 		u32 add_data;
1347 		u32 res_addr;
1348 	} u;
1349 };
1350 
1351 struct ipr_sglist {
1352 	u32 order;
1353 	u32 num_sg;
1354 	u32 num_dma_sg;
1355 	u32 buffer_len;
1356 	struct scatterlist scatterlist[1];
1357 };
1358 
1359 enum ipr_sdt_state {
1360 	INACTIVE,
1361 	WAIT_FOR_DUMP,
1362 	GET_DUMP,
1363 	ABORT_DUMP,
1364 	DUMP_OBTAINED
1365 };
1366 
1367 /* Per-controller data */
1368 struct ipr_ioa_cfg {
1369 	char eye_catcher[8];
1370 #define IPR_EYECATCHER			"iprcfg"
1371 
1372 	struct list_head queue;
1373 
1374 	u8 allow_interrupts:1;
1375 	u8 in_reset_reload:1;
1376 	u8 in_ioa_bringdown:1;
1377 	u8 ioa_unit_checked:1;
1378 	u8 ioa_is_dead:1;
1379 	u8 dump_taken:1;
1380 	u8 allow_cmds:1;
1381 	u8 allow_ml_add_del:1;
1382 	u8 needs_hard_reset:1;
1383 	u8 dual_raid:1;
1384 	u8 needs_warm_reset:1;
1385 	u8 msi_received:1;
1386 	u8 sis64:1;
1387 
1388 	u8 revid;
1389 
1390 	/*
1391 	 * Bitmaps for SIS64 generated target values
1392 	 */
1393 	unsigned long *target_ids;
1394 	unsigned long *array_ids;
1395 	unsigned long *vset_ids;
1396 
1397 	u16 type; /* CCIN of the card */
1398 
1399 	u8 log_level;
1400 #define IPR_MAX_LOG_LEVEL			4
1401 #define IPR_DEFAULT_LOG_LEVEL		2
1402 
1403 #define IPR_NUM_TRACE_INDEX_BITS	8
1404 #define IPR_NUM_TRACE_ENTRIES		(1 << IPR_NUM_TRACE_INDEX_BITS)
1405 #define IPR_TRACE_SIZE	(sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1406 	char trace_start[8];
1407 #define IPR_TRACE_START_LABEL			"trace"
1408 	struct ipr_trace_entry *trace;
1409 	u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1410 
1411 	/*
1412 	 * Queue for free command blocks
1413 	 */
1414 	char ipr_free_label[8];
1415 #define IPR_FREEQ_LABEL			"free-q"
1416 	struct list_head free_q;
1417 
1418 	/*
1419 	 * Queue for command blocks outstanding to the adapter
1420 	 */
1421 	char ipr_pending_label[8];
1422 #define IPR_PENDQ_LABEL			"pend-q"
1423 	struct list_head pending_q;
1424 
1425 	char cfg_table_start[8];
1426 #define IPR_CFG_TBL_START		"cfg"
1427 	union {
1428 		struct ipr_config_table *cfg_table;
1429 		struct ipr_config_table64 *cfg_table64;
1430 	} u;
1431 	dma_addr_t cfg_table_dma;
1432 	u32 cfg_table_size;
1433 	u32 max_devs_supported;
1434 
1435 	char resource_table_label[8];
1436 #define IPR_RES_TABLE_LABEL		"res_tbl"
1437 	struct ipr_resource_entry *res_entries;
1438 	struct list_head free_res_q;
1439 	struct list_head used_res_q;
1440 
1441 	char ipr_hcam_label[8];
1442 #define IPR_HCAM_LABEL			"hcams"
1443 	struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1444 	dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1445 	struct list_head hostrcb_free_q;
1446 	struct list_head hostrcb_pending_q;
1447 
1448 	__be32 *host_rrq;
1449 	dma_addr_t host_rrq_dma;
1450 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK	0xfffffffc
1451 #define IPR_HRRQ_RESP_BIT_SET			0x00000002
1452 #define IPR_HRRQ_TOGGLE_BIT				0x00000001
1453 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT	2
1454 	volatile __be32 *hrrq_start;
1455 	volatile __be32 *hrrq_end;
1456 	volatile __be32 *hrrq_curr;
1457 	volatile u32 toggle_bit;
1458 
1459 	struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1460 
1461 	unsigned int transop_timeout;
1462 	const struct ipr_chip_cfg_t *chip_cfg;
1463 	const struct ipr_chip_t *ipr_chip;
1464 
1465 	void __iomem *hdw_dma_regs;	/* iomapped PCI memory space */
1466 	unsigned long hdw_dma_regs_pci;	/* raw PCI memory space */
1467 	void __iomem *ioa_mailbox;
1468 	struct ipr_interrupts regs;
1469 
1470 	u16 saved_pcix_cmd_reg;
1471 	u16 reset_retries;
1472 
1473 	u32 errors_logged;
1474 	u32 doorbell;
1475 
1476 	struct Scsi_Host *host;
1477 	struct pci_dev *pdev;
1478 	struct ipr_sglist *ucode_sglist;
1479 	u8 saved_mode_page_len;
1480 
1481 	struct work_struct work_q;
1482 
1483 	wait_queue_head_t reset_wait_q;
1484 	wait_queue_head_t msi_wait_q;
1485 
1486 	struct ipr_dump *dump;
1487 	enum ipr_sdt_state sdt_state;
1488 
1489 	struct ipr_misc_cbs *vpd_cbs;
1490 	dma_addr_t vpd_cbs_dma;
1491 
1492 	struct pci_pool *ipr_cmd_pool;
1493 
1494 	struct ipr_cmnd *reset_cmd;
1495 	int (*reset) (struct ipr_cmnd *);
1496 
1497 	struct ata_host ata_host;
1498 	char ipr_cmd_label[8];
1499 #define IPR_CMD_LABEL		"ipr_cmd"
1500 	struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1501 	dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1502 }; /* struct ipr_ioa_cfg */
1503 
1504 struct ipr_cmnd {
1505 	struct ipr_ioarcb ioarcb;
1506 	union {
1507 		struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1508 		struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1509 		struct ipr_ata64_ioadl ata_ioadl;
1510 	} i;
1511 	union {
1512 		struct ipr_ioasa ioasa;
1513 		struct ipr_ioasa64 ioasa64;
1514 	} s;
1515 	struct list_head queue;
1516 	struct scsi_cmnd *scsi_cmd;
1517 	struct ata_queued_cmd *qc;
1518 	struct completion completion;
1519 	struct timer_list timer;
1520 	void (*done) (struct ipr_cmnd *);
1521 	int (*job_step) (struct ipr_cmnd *);
1522 	int (*job_step_failed) (struct ipr_cmnd *);
1523 	u16 cmd_index;
1524 	u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1525 	dma_addr_t sense_buffer_dma;
1526 	unsigned short dma_use_sg;
1527 	dma_addr_t dma_addr;
1528 	struct ipr_cmnd *sibling;
1529 	union {
1530 		enum ipr_shutdown_type shutdown_type;
1531 		struct ipr_hostrcb *hostrcb;
1532 		unsigned long time_left;
1533 		unsigned long scratch;
1534 		struct ipr_resource_entry *res;
1535 		struct scsi_device *sdev;
1536 	} u;
1537 
1538 	struct ipr_ioa_cfg *ioa_cfg;
1539 };
1540 
1541 struct ipr_ses_table_entry {
1542 	char product_id[17];
1543 	char compare_product_id_byte[17];
1544 	u32 max_bus_speed_limit;	/* MB/sec limit for this backplane */
1545 };
1546 
1547 struct ipr_dump_header {
1548 	u32 eye_catcher;
1549 #define IPR_DUMP_EYE_CATCHER		0xC5D4E3F2
1550 	u32 len;
1551 	u32 num_entries;
1552 	u32 first_entry_offset;
1553 	u32 status;
1554 #define IPR_DUMP_STATUS_SUCCESS			0
1555 #define IPR_DUMP_STATUS_QUAL_SUCCESS		2
1556 #define IPR_DUMP_STATUS_FAILED			0xffffffff
1557 	u32 os;
1558 #define IPR_DUMP_OS_LINUX	0x4C4E5558
1559 	u32 driver_name;
1560 #define IPR_DUMP_DRIVER_NAME	0x49505232
1561 }__attribute__((packed, aligned (4)));
1562 
1563 struct ipr_dump_entry_header {
1564 	u32 eye_catcher;
1565 #define IPR_DUMP_EYE_CATCHER		0xC5D4E3F2
1566 	u32 len;
1567 	u32 num_elems;
1568 	u32 offset;
1569 	u32 data_type;
1570 #define IPR_DUMP_DATA_TYPE_ASCII	0x41534349
1571 #define IPR_DUMP_DATA_TYPE_BINARY	0x42494E41
1572 	u32 id;
1573 #define IPR_DUMP_IOA_DUMP_ID		0x494F4131
1574 #define IPR_DUMP_LOCATION_ID		0x4C4F4341
1575 #define IPR_DUMP_TRACE_ID		0x54524143
1576 #define IPR_DUMP_DRIVER_VERSION_ID	0x44525652
1577 #define IPR_DUMP_DRIVER_TYPE_ID	0x54595045
1578 #define IPR_DUMP_IOA_CTRL_BLK		0x494F4342
1579 #define IPR_DUMP_PEND_OPS		0x414F5053
1580 	u32 status;
1581 }__attribute__((packed, aligned (4)));
1582 
1583 struct ipr_dump_location_entry {
1584 	struct ipr_dump_entry_header hdr;
1585 	u8 location[20];
1586 }__attribute__((packed));
1587 
1588 struct ipr_dump_trace_entry {
1589 	struct ipr_dump_entry_header hdr;
1590 	u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1591 }__attribute__((packed, aligned (4)));
1592 
1593 struct ipr_dump_version_entry {
1594 	struct ipr_dump_entry_header hdr;
1595 	u8 version[sizeof(IPR_DRIVER_VERSION)];
1596 };
1597 
1598 struct ipr_dump_ioa_type_entry {
1599 	struct ipr_dump_entry_header hdr;
1600 	u32 type;
1601 	u32 fw_version;
1602 };
1603 
1604 struct ipr_driver_dump {
1605 	struct ipr_dump_header hdr;
1606 	struct ipr_dump_version_entry version_entry;
1607 	struct ipr_dump_location_entry location_entry;
1608 	struct ipr_dump_ioa_type_entry ioa_type_entry;
1609 	struct ipr_dump_trace_entry trace_entry;
1610 }__attribute__((packed));
1611 
1612 struct ipr_ioa_dump {
1613 	struct ipr_dump_entry_header hdr;
1614 	struct ipr_sdt sdt;
1615 	__be32 **ioa_data;
1616 	u32 reserved;
1617 	u32 next_page_index;
1618 	u32 page_offset;
1619 	u32 format;
1620 }__attribute__((packed, aligned (4)));
1621 
1622 struct ipr_dump {
1623 	struct kref kref;
1624 	struct ipr_ioa_cfg *ioa_cfg;
1625 	struct ipr_driver_dump driver_dump;
1626 	struct ipr_ioa_dump ioa_dump;
1627 };
1628 
1629 struct ipr_error_table_t {
1630 	u32 ioasc;
1631 	int log_ioasa;
1632 	int log_hcam;
1633 	char *error;
1634 };
1635 
1636 struct ipr_software_inq_lid_info {
1637 	__be32 load_id;
1638 	__be32 timestamp[3];
1639 }__attribute__((packed, aligned (4)));
1640 
1641 struct ipr_ucode_image_header {
1642 	__be32 header_length;
1643 	__be32 lid_table_offset;
1644 	u8 major_release;
1645 	u8 card_type;
1646 	u8 minor_release[2];
1647 	u8 reserved[20];
1648 	char eyecatcher[16];
1649 	__be32 num_lids;
1650 	struct ipr_software_inq_lid_info lid[1];
1651 }__attribute__((packed, aligned (4)));
1652 
1653 /*
1654  * Macros
1655  */
1656 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1657 
1658 #ifdef CONFIG_SCSI_IPR_TRACE
1659 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1660 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1661 #else
1662 #define ipr_create_trace_file(kobj, attr) 0
1663 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1664 #endif
1665 
1666 #ifdef CONFIG_SCSI_IPR_DUMP
1667 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1668 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1669 #else
1670 #define ipr_create_dump_file(kobj, attr) 0
1671 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1672 #endif
1673 
1674 /*
1675  * Error logging macros
1676  */
1677 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1678 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1679 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1680 
1681 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1682 	printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1683 		bus, target, lun, ##__VA_ARGS__)
1684 
1685 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1686 	ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1687 
1688 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1689 	printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1690 		(ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1691 
1692 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1693 	ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1694 
1695 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...)			\
1696 {									\
1697 	if ((res).bus >= IPR_MAX_NUM_BUSES) {				\
1698 		ipr_err(fmt": unknown\n", ##__VA_ARGS__);		\
1699 	} else {							\
1700 		ipr_err(fmt": %d:%d:%d:%d\n",				\
1701 			##__VA_ARGS__, (ioa_cfg)->host->host_no,	\
1702 			(res).bus, (res).target, (res).lun);		\
1703 	}								\
1704 }
1705 
1706 #define ipr_hcam_err(hostrcb, fmt, ...)					\
1707 {									\
1708 	if (ipr_is_device(hostrcb)) {					\
1709 		if ((hostrcb)->ioa_cfg->sis64) {			\
1710 			printk(KERN_ERR IPR_NAME ": %s: " fmt, 		\
1711 				ipr_format_res_path(hostrcb->hcam.u.error64.fd_res_path, \
1712 					hostrcb->rp_buffer,		\
1713 					sizeof(hostrcb->rp_buffer)),	\
1714 				__VA_ARGS__);				\
1715 		} else {						\
1716 			ipr_ra_err((hostrcb)->ioa_cfg,			\
1717 				(hostrcb)->hcam.u.error.fd_res_addr,	\
1718 				fmt, __VA_ARGS__);			\
1719 		}							\
1720 	} else {							\
1721 		dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1722 	}								\
1723 }
1724 
1725 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1726 	__FILE__, __func__, __LINE__)
1727 
1728 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1729 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1730 
1731 #define ipr_err_separator \
1732 ipr_err("----------------------------------------------------------\n")
1733 
1734 
1735 /*
1736  * Inlines
1737  */
1738 
1739 /**
1740  * ipr_is_ioa_resource - Determine if a resource is the IOA
1741  * @res:	resource entry struct
1742  *
1743  * Return value:
1744  * 	1 if IOA / 0 if not IOA
1745  **/
1746 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1747 {
1748 	return res->type == IPR_RES_TYPE_IOAFP;
1749 }
1750 
1751 /**
1752  * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1753  * @res:	resource entry struct
1754  *
1755  * Return value:
1756  * 	1 if AF DASD / 0 if not AF DASD
1757  **/
1758 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1759 {
1760 	return res->type == IPR_RES_TYPE_AF_DASD ||
1761 		res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1762 }
1763 
1764 /**
1765  * ipr_is_vset_device - Determine if a resource is a VSET
1766  * @res:	resource entry struct
1767  *
1768  * Return value:
1769  * 	1 if VSET / 0 if not VSET
1770  **/
1771 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1772 {
1773 	return res->type == IPR_RES_TYPE_VOLUME_SET;
1774 }
1775 
1776 /**
1777  * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1778  * @res:	resource entry struct
1779  *
1780  * Return value:
1781  * 	1 if GSCSI / 0 if not GSCSI
1782  **/
1783 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1784 {
1785 	return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1786 }
1787 
1788 /**
1789  * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1790  * @res:	resource entry struct
1791  *
1792  * Return value:
1793  * 	1 if SCSI disk / 0 if not SCSI disk
1794  **/
1795 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1796 {
1797 	if (ipr_is_af_dasd_device(res) ||
1798 	    (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1799 		return 1;
1800 	else
1801 		return 0;
1802 }
1803 
1804 /**
1805  * ipr_is_gata - Determine if a resource is a generic ATA resource
1806  * @res:	resource entry struct
1807  *
1808  * Return value:
1809  * 	1 if GATA / 0 if not GATA
1810  **/
1811 static inline int ipr_is_gata(struct ipr_resource_entry *res)
1812 {
1813 	return res->type == IPR_RES_TYPE_GENERIC_ATA;
1814 }
1815 
1816 /**
1817  * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1818  * @res:	resource entry struct
1819  *
1820  * Return value:
1821  * 	1 if NACA queueing model / 0 if not NACA queueing model
1822  **/
1823 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1824 {
1825 	if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1826 		return 1;
1827 	return 0;
1828 }
1829 
1830 /**
1831  * ipr_is_device - Determine if the hostrcb structure is related to a device
1832  * @hostrcb:	host resource control blocks struct
1833  *
1834  * Return value:
1835  * 	1 if AF / 0 if not AF
1836  **/
1837 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1838 {
1839 	struct ipr_res_addr *res_addr;
1840 	u8 *res_path;
1841 
1842 	if (hostrcb->ioa_cfg->sis64) {
1843 		res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1844 		if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1845 		    res_path[0] == 0x81) && res_path[2] != 0xFF)
1846 			return 1;
1847 	} else {
1848 		res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1849 
1850 		if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1851 		    (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1852 			return 1;
1853 	}
1854 	return 0;
1855 }
1856 
1857 /**
1858  * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1859  * @sdt_word:	SDT address
1860  *
1861  * Return value:
1862  * 	1 if format 2 / 0 if not
1863  **/
1864 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1865 {
1866 	u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1867 
1868 	switch (bar_sel) {
1869 	case IPR_SDT_FMT2_BAR0_SEL:
1870 	case IPR_SDT_FMT2_BAR1_SEL:
1871 	case IPR_SDT_FMT2_BAR2_SEL:
1872 	case IPR_SDT_FMT2_BAR3_SEL:
1873 	case IPR_SDT_FMT2_BAR4_SEL:
1874 	case IPR_SDT_FMT2_BAR5_SEL:
1875 	case IPR_SDT_FMT2_EXP_ROM_SEL:
1876 		return 1;
1877 	};
1878 
1879 	return 0;
1880 }
1881 
1882 #ifndef writeq
1883 static inline void writeq(u64 val, void __iomem *addr)
1884 {
1885         writel(((u32) (val >> 32)), addr);
1886         writel(((u32) (val)), (addr + 4));
1887 }
1888 #endif
1889 
1890 #endif /* _IPR_H */
1891