1 /* 2 * ipr.h -- driver for IBM Power Linux RAID adapters 3 * 4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation 5 * 6 * Copyright (C) 2003, 2004 IBM Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors 23 * that broke 64bit platforms. 24 */ 25 26 #ifndef _IPR_H 27 #define _IPR_H 28 29 #include <asm/unaligned.h> 30 #include <linux/types.h> 31 #include <linux/completion.h> 32 #include <linux/libata.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/blk-iopoll.h> 36 #include <scsi/scsi.h> 37 #include <scsi/scsi_cmnd.h> 38 39 /* 40 * Literals 41 */ 42 #define IPR_DRIVER_VERSION "2.6.0" 43 #define IPR_DRIVER_DATE "(November 16, 2012)" 44 45 /* 46 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding 47 * ops per device for devices not running tagged command queuing. 48 * This can be adjusted at runtime through sysfs device attributes. 49 */ 50 #define IPR_MAX_CMD_PER_LUN 6 51 #define IPR_MAX_CMD_PER_ATA_LUN 1 52 53 /* 54 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of 55 * ops the mid-layer can send to the adapter. 56 */ 57 #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds) 58 59 #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 60 61 #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D 62 #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A 63 64 #define IPR_SUBS_DEV_ID_2780 0x0264 65 #define IPR_SUBS_DEV_ID_5702 0x0266 66 #define IPR_SUBS_DEV_ID_5703 0x0278 67 #define IPR_SUBS_DEV_ID_572E 0x028D 68 #define IPR_SUBS_DEV_ID_573E 0x02D3 69 #define IPR_SUBS_DEV_ID_573D 0x02D4 70 #define IPR_SUBS_DEV_ID_571A 0x02C0 71 #define IPR_SUBS_DEV_ID_571B 0x02BE 72 #define IPR_SUBS_DEV_ID_571E 0x02BF 73 #define IPR_SUBS_DEV_ID_571F 0x02D5 74 #define IPR_SUBS_DEV_ID_572A 0x02C1 75 #define IPR_SUBS_DEV_ID_572B 0x02C2 76 #define IPR_SUBS_DEV_ID_572F 0x02C3 77 #define IPR_SUBS_DEV_ID_574E 0x030A 78 #define IPR_SUBS_DEV_ID_575B 0x030D 79 #define IPR_SUBS_DEV_ID_575C 0x0338 80 #define IPR_SUBS_DEV_ID_57B3 0x033A 81 #define IPR_SUBS_DEV_ID_57B7 0x0360 82 #define IPR_SUBS_DEV_ID_57B8 0x02C2 83 84 #define IPR_SUBS_DEV_ID_57B4 0x033B 85 #define IPR_SUBS_DEV_ID_57B2 0x035F 86 #define IPR_SUBS_DEV_ID_57C0 0x0352 87 #define IPR_SUBS_DEV_ID_57C3 0x0353 88 #define IPR_SUBS_DEV_ID_57C4 0x0354 89 #define IPR_SUBS_DEV_ID_57C6 0x0357 90 #define IPR_SUBS_DEV_ID_57CC 0x035C 91 92 #define IPR_SUBS_DEV_ID_57B5 0x033C 93 #define IPR_SUBS_DEV_ID_57CE 0x035E 94 #define IPR_SUBS_DEV_ID_57B1 0x0355 95 96 #define IPR_SUBS_DEV_ID_574D 0x0356 97 #define IPR_SUBS_DEV_ID_57C8 0x035D 98 99 #define IPR_SUBS_DEV_ID_57D5 0x03FB 100 #define IPR_SUBS_DEV_ID_57D6 0x03FC 101 #define IPR_SUBS_DEV_ID_57D7 0x03FF 102 #define IPR_SUBS_DEV_ID_57D8 0x03FE 103 #define IPR_SUBS_DEV_ID_57D9 0x046D 104 #define IPR_SUBS_DEV_ID_57DA 0x04CA 105 #define IPR_SUBS_DEV_ID_57EB 0x0474 106 #define IPR_SUBS_DEV_ID_57EC 0x0475 107 #define IPR_SUBS_DEV_ID_57ED 0x0499 108 #define IPR_SUBS_DEV_ID_57EE 0x049A 109 #define IPR_SUBS_DEV_ID_57EF 0x049B 110 #define IPR_SUBS_DEV_ID_57F0 0x049C 111 #define IPR_SUBS_DEV_ID_2CCA 0x04C7 112 #define IPR_SUBS_DEV_ID_2CD2 0x04C8 113 #define IPR_SUBS_DEV_ID_2CCD 0x04C9 114 #define IPR_NAME "ipr" 115 116 /* 117 * Return codes 118 */ 119 #define IPR_RC_JOB_CONTINUE 1 120 #define IPR_RC_JOB_RETURN 2 121 122 /* 123 * IOASCs 124 */ 125 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 126 #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 127 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 128 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 129 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 130 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 131 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 132 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF 133 #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 134 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 135 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 136 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 137 #define IPR_IOASC_BUS_WAS_RESET 0x06290000 138 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 139 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 140 141 #define IPR_FIRST_DRIVER_IOASC 0x10000000 142 #define IPR_IOASC_IOA_WAS_RESET 0x10000001 143 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 144 145 /* Driver data flags */ 146 #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 147 #define IPR_USE_PCI_WARM_RESET 0x00000002 148 149 #define IPR_DEFAULT_MAX_ERROR_DUMP 984 150 #define IPR_NUM_LOG_HCAMS 2 151 #define IPR_NUM_CFG_CHG_HCAMS 2 152 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) 153 154 #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024 155 #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff 156 157 #define IPR_MAX_NUM_TARGETS_PER_BUS 256 158 #define IPR_MAX_NUM_LUNS_PER_TARGET 256 159 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8 160 #define IPR_VSET_BUS 0xff 161 #define IPR_IOA_BUS 0xff 162 #define IPR_IOA_TARGET 0xff 163 #define IPR_IOA_LUN 0xff 164 #define IPR_MAX_NUM_BUSES 16 165 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES 166 167 #define IPR_NUM_RESET_RELOAD_RETRIES 3 168 169 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ 170 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ 171 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) 172 173 #define IPR_MAX_COMMANDS 100 174 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ 175 IPR_NUM_INTERNAL_CMD_BLKS) 176 177 #define IPR_MAX_PHYSICAL_DEVS 192 178 #define IPR_DEFAULT_SIS64_DEVS 1024 179 #define IPR_MAX_SIS64_DEVS 4096 180 181 #define IPR_MAX_SGLIST 64 182 #define IPR_IOA_MAX_SECTORS 32767 183 #define IPR_VSET_MAX_SECTORS 512 184 #define IPR_MAX_CDB_LEN 16 185 #define IPR_MAX_HRRQ_RETRIES 3 186 187 #define IPR_DEFAULT_BUS_WIDTH 16 188 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 189 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 190 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) 191 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) 192 193 #define IPR_IOA_RES_HANDLE 0xffffffff 194 #define IPR_INVALID_RES_HANDLE 0 195 #define IPR_IOA_RES_ADDR 0x00ffffff 196 197 /* 198 * Adapter Commands 199 */ 200 #define IPR_QUERY_RSRC_STATE 0xC2 201 #define IPR_RESET_DEVICE 0xC3 202 #define IPR_RESET_TYPE_SELECT 0x80 203 #define IPR_LUN_RESET 0x40 204 #define IPR_TARGET_RESET 0x20 205 #define IPR_BUS_RESET 0x10 206 #define IPR_ATA_PHY_RESET 0x80 207 #define IPR_ID_HOST_RR_Q 0xC4 208 #define IPR_QUERY_IOA_CONFIG 0xC5 209 #define IPR_CANCEL_ALL_REQUESTS 0xCE 210 #define IPR_HOST_CONTROLLED_ASYNC 0xCF 211 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 212 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 213 #define IPR_SET_SUPPORTED_DEVICES 0xFB 214 #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 215 #define IPR_IOA_SHUTDOWN 0xF7 216 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 217 218 /* 219 * Timeouts 220 */ 221 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) 222 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) 223 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) 224 #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) 225 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 226 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 227 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 228 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) 229 #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ) 230 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) 231 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) 232 #define IPR_OPERATIONAL_TIMEOUT (5 * 60) 233 #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) 234 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) 235 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) 236 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) 237 #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) 238 #define IPR_PCI_RESET_TIMEOUT (HZ / 2) 239 #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ) 240 #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ) 241 #define IPR_DUMP_DELAY_SECONDS 4 242 #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ) 243 244 /* 245 * SCSI Literals 246 */ 247 #define IPR_VENDOR_ID_LEN 8 248 #define IPR_PROD_ID_LEN 16 249 #define IPR_SERIAL_NUM_LEN 8 250 251 /* 252 * Hardware literals 253 */ 254 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff 255 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 256 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 257 #define IPR_GET_FMT2_BAR_SEL(mbx) \ 258 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) 259 #define IPR_SDT_FMT2_BAR0_SEL 0x0 260 #define IPR_SDT_FMT2_BAR1_SEL 0x1 261 #define IPR_SDT_FMT2_BAR2_SEL 0x2 262 #define IPR_SDT_FMT2_BAR3_SEL 0x3 263 #define IPR_SDT_FMT2_BAR4_SEL 0x4 264 #define IPR_SDT_FMT2_BAR5_SEL 0x5 265 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 266 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 267 #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 268 #define IPR_DOORBELL 0x82800000 269 #define IPR_RUNTIME_RESET 0x40000000 270 271 #define IPR_IPL_INIT_MIN_STAGE_TIME 5 272 #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15 273 #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0 274 #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 275 #define IPR_IPL_INIT_STAGE_MASK 0xff000000 276 #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff 277 #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) 278 279 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) 280 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) 281 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) 282 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) 283 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) 284 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) 285 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) 286 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) 287 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) 288 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) 289 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) 290 291 #define IPR_PCII_ERROR_INTERRUPTS \ 292 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ 293 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) 294 295 #define IPR_PCII_OPER_INTERRUPTS \ 296 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) 297 298 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) 299 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) 300 #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23) 301 302 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 303 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ 304 305 /* 306 * Dump literals 307 */ 308 #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) 309 #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024) 310 #define IPR_FMT2_NUM_SDT_ENTRIES 511 311 #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF 312 #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) 313 #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) 314 315 /* 316 * Misc literals 317 */ 318 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST 319 #define IPR_MAX_MSIX_VECTORS 0x10 320 #define IPR_MAX_HRRQ_NUM 0x10 321 #define IPR_INIT_HRRQ 0x0 322 323 /* 324 * Adapter interface types 325 */ 326 327 struct ipr_res_addr { 328 u8 reserved; 329 u8 bus; 330 u8 target; 331 u8 lun; 332 #define IPR_GET_PHYS_LOC(res_addr) \ 333 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) 334 }__attribute__((packed, aligned (4))); 335 336 struct ipr_std_inq_vpids { 337 u8 vendor_id[IPR_VENDOR_ID_LEN]; 338 u8 product_id[IPR_PROD_ID_LEN]; 339 }__attribute__((packed)); 340 341 struct ipr_vpd { 342 struct ipr_std_inq_vpids vpids; 343 u8 sn[IPR_SERIAL_NUM_LEN]; 344 }__attribute__((packed)); 345 346 struct ipr_ext_vpd { 347 struct ipr_vpd vpd; 348 __be32 wwid[2]; 349 }__attribute__((packed)); 350 351 struct ipr_ext_vpd64 { 352 struct ipr_vpd vpd; 353 __be32 wwid[4]; 354 }__attribute__((packed)); 355 356 struct ipr_std_inq_data { 357 u8 peri_qual_dev_type; 358 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) 359 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) 360 361 u8 removeable_medium_rsvd; 362 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 363 364 #define IPR_IS_DASD_DEVICE(std_inq) \ 365 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ 366 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) 367 368 #define IPR_IS_SES_DEVICE(std_inq) \ 369 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) 370 371 u8 version; 372 u8 aen_naca_fmt; 373 u8 additional_len; 374 u8 sccs_rsvd; 375 u8 bq_enc_multi; 376 u8 sync_cmdq_flags; 377 378 struct ipr_std_inq_vpids vpids; 379 380 u8 ros_rsvd_ram_rsvd[4]; 381 382 u8 serial_num[IPR_SERIAL_NUM_LEN]; 383 }__attribute__ ((packed)); 384 385 #define IPR_RES_TYPE_AF_DASD 0x00 386 #define IPR_RES_TYPE_GENERIC_SCSI 0x01 387 #define IPR_RES_TYPE_VOLUME_SET 0x02 388 #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03 389 #define IPR_RES_TYPE_GENERIC_ATA 0x04 390 #define IPR_RES_TYPE_ARRAY 0x05 391 #define IPR_RES_TYPE_IOAFP 0xff 392 393 struct ipr_config_table_entry { 394 u8 proto; 395 #define IPR_PROTO_SATA 0x02 396 #define IPR_PROTO_SATA_ATAPI 0x03 397 #define IPR_PROTO_SAS_STP 0x06 398 #define IPR_PROTO_SAS_STP_ATAPI 0x07 399 u8 array_id; 400 u8 flags; 401 #define IPR_IS_IOA_RESOURCE 0x80 402 u8 rsvd_subtype; 403 404 #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) 405 #define IPR_QUEUE_FROZEN_MODEL 0 406 #define IPR_QUEUE_NACA_MODEL 1 407 408 struct ipr_res_addr res_addr; 409 __be32 res_handle; 410 __be32 lun_wwn[2]; 411 struct ipr_std_inq_data std_inq_data; 412 }__attribute__ ((packed, aligned (4))); 413 414 struct ipr_config_table_entry64 { 415 u8 res_type; 416 u8 proto; 417 u8 vset_num; 418 u8 array_id; 419 __be16 flags; 420 __be16 res_flags; 421 #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) 422 __be32 res_handle; 423 u8 dev_id_type; 424 u8 reserved[3]; 425 __be64 dev_id; 426 __be64 lun; 427 __be64 lun_wwn[2]; 428 #define IPR_MAX_RES_PATH_LENGTH 48 429 __be64 res_path; 430 struct ipr_std_inq_data std_inq_data; 431 u8 reserved2[4]; 432 __be64 reserved3[2]; 433 u8 reserved4[8]; 434 }__attribute__ ((packed, aligned (8))); 435 436 struct ipr_config_table_hdr { 437 u8 num_entries; 438 u8 flags; 439 #define IPR_UCODE_DOWNLOAD_REQ 0x10 440 __be16 reserved; 441 }__attribute__((packed, aligned (4))); 442 443 struct ipr_config_table_hdr64 { 444 __be16 num_entries; 445 __be16 reserved; 446 u8 flags; 447 u8 reserved2[11]; 448 }__attribute__((packed, aligned (4))); 449 450 struct ipr_config_table { 451 struct ipr_config_table_hdr hdr; 452 struct ipr_config_table_entry dev[0]; 453 }__attribute__((packed, aligned (4))); 454 455 struct ipr_config_table64 { 456 struct ipr_config_table_hdr64 hdr64; 457 struct ipr_config_table_entry64 dev[0]; 458 }__attribute__((packed, aligned (8))); 459 460 struct ipr_config_table_entry_wrapper { 461 union { 462 struct ipr_config_table_entry *cfgte; 463 struct ipr_config_table_entry64 *cfgte64; 464 } u; 465 }; 466 467 struct ipr_hostrcb_cfg_ch_not { 468 union { 469 struct ipr_config_table_entry cfgte; 470 struct ipr_config_table_entry64 cfgte64; 471 } u; 472 u8 reserved[936]; 473 }__attribute__((packed, aligned (4))); 474 475 struct ipr_supported_device { 476 __be16 data_length; 477 u8 reserved; 478 u8 num_records; 479 struct ipr_std_inq_vpids vpids; 480 u8 reserved2[16]; 481 }__attribute__((packed, aligned (4))); 482 483 struct ipr_hrr_queue { 484 struct ipr_ioa_cfg *ioa_cfg; 485 __be32 *host_rrq; 486 dma_addr_t host_rrq_dma; 487 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc 488 #define IPR_HRRQ_RESP_BIT_SET 0x00000002 489 #define IPR_HRRQ_TOGGLE_BIT 0x00000001 490 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 491 #define IPR_ID_HRRQ_SELE_ENABLE 0x02 492 volatile __be32 *hrrq_start; 493 volatile __be32 *hrrq_end; 494 volatile __be32 *hrrq_curr; 495 496 struct list_head hrrq_free_q; 497 struct list_head hrrq_pending_q; 498 spinlock_t _lock; 499 spinlock_t *lock; 500 501 volatile u32 toggle_bit; 502 u32 size; 503 u32 min_cmd_id; 504 u32 max_cmd_id; 505 u8 allow_interrupts:1; 506 u8 ioa_is_dead:1; 507 u8 allow_cmds:1; 508 u8 removing_ioa:1; 509 510 struct blk_iopoll iopoll; 511 }; 512 513 /* Command packet structure */ 514 struct ipr_cmd_pkt { 515 u8 reserved; /* Reserved by IOA */ 516 u8 hrrq_id; 517 u8 request_type; 518 #define IPR_RQTYPE_SCSICDB 0x00 519 #define IPR_RQTYPE_IOACMD 0x01 520 #define IPR_RQTYPE_HCAM 0x02 521 #define IPR_RQTYPE_ATA_PASSTHRU 0x04 522 523 u8 reserved2; 524 525 u8 flags_hi; 526 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 527 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 528 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 529 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 530 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 531 532 u8 flags_lo; 533 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 534 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 535 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 536 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 537 #define IPR_FLAGS_LO_ORDERED_TASK 0x04 538 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 539 #define IPR_FLAGS_LO_ACA_TASK 0x08 540 541 u8 cdb[16]; 542 __be16 timeout; 543 }__attribute__ ((packed, aligned(4))); 544 545 struct ipr_ioarcb_ata_regs { /* 22 bytes */ 546 u8 flags; 547 #define IPR_ATA_FLAG_PACKET_CMD 0x80 548 #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 549 #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 550 u8 reserved[3]; 551 552 __be16 data; 553 u8 feature; 554 u8 nsect; 555 u8 lbal; 556 u8 lbam; 557 u8 lbah; 558 u8 device; 559 u8 command; 560 u8 reserved2[3]; 561 u8 hob_feature; 562 u8 hob_nsect; 563 u8 hob_lbal; 564 u8 hob_lbam; 565 u8 hob_lbah; 566 u8 ctl; 567 }__attribute__ ((packed, aligned(2))); 568 569 struct ipr_ioadl_desc { 570 __be32 flags_and_data_len; 571 #define IPR_IOADL_FLAGS_MASK 0xff000000 572 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) 573 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff 574 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) 575 #define IPR_IOADL_FLAGS_READ 0x48000000 576 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 577 #define IPR_IOADL_FLAGS_WRITE 0x68000000 578 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 579 #define IPR_IOADL_FLAGS_LAST 0x01000000 580 581 __be32 address; 582 }__attribute__((packed, aligned (8))); 583 584 struct ipr_ioadl64_desc { 585 __be32 flags; 586 __be32 data_len; 587 __be64 address; 588 }__attribute__((packed, aligned (16))); 589 590 struct ipr_ata64_ioadl { 591 struct ipr_ioarcb_ata_regs regs; 592 u16 reserved[5]; 593 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; 594 }__attribute__((packed, aligned (16))); 595 596 struct ipr_ioarcb_add_data { 597 union { 598 struct ipr_ioarcb_ata_regs regs; 599 struct ipr_ioadl_desc ioadl[5]; 600 __be32 add_cmd_parms[10]; 601 } u; 602 }__attribute__ ((packed, aligned (4))); 603 604 struct ipr_ioarcb_sis64_add_addr_ecb { 605 __be64 ioasa_host_pci_addr; 606 __be64 data_ioadl_addr; 607 __be64 reserved; 608 __be32 ext_control_buf[4]; 609 }__attribute__((packed, aligned (8))); 610 611 /* IOA Request Control Block 128 bytes */ 612 struct ipr_ioarcb { 613 union { 614 __be32 ioarcb_host_pci_addr; 615 __be64 ioarcb_host_pci_addr64; 616 } a; 617 __be32 res_handle; 618 __be32 host_response_handle; 619 __be32 reserved1; 620 __be32 reserved2; 621 __be32 reserved3; 622 623 __be32 data_transfer_length; 624 __be32 read_data_transfer_length; 625 __be32 write_ioadl_addr; 626 __be32 ioadl_len; 627 __be32 read_ioadl_addr; 628 __be32 read_ioadl_len; 629 630 __be32 ioasa_host_pci_addr; 631 __be16 ioasa_len; 632 __be16 reserved4; 633 634 struct ipr_cmd_pkt cmd_pkt; 635 636 __be16 add_cmd_parms_offset; 637 __be16 add_cmd_parms_len; 638 639 union { 640 struct ipr_ioarcb_add_data add_data; 641 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data; 642 } u; 643 644 }__attribute__((packed, aligned (4))); 645 646 struct ipr_ioasa_vset { 647 __be32 failing_lba_hi; 648 __be32 failing_lba_lo; 649 __be32 reserved; 650 }__attribute__((packed, aligned (4))); 651 652 struct ipr_ioasa_af_dasd { 653 __be32 failing_lba; 654 __be32 reserved[2]; 655 }__attribute__((packed, aligned (4))); 656 657 struct ipr_ioasa_gpdd { 658 u8 end_state; 659 u8 bus_phase; 660 __be16 reserved; 661 __be32 ioa_data[2]; 662 }__attribute__((packed, aligned (4))); 663 664 struct ipr_ioasa_gata { 665 u8 error; 666 u8 nsect; /* Interrupt reason */ 667 u8 lbal; 668 u8 lbam; 669 u8 lbah; 670 u8 device; 671 u8 status; 672 u8 alt_status; /* ATA CTL */ 673 u8 hob_nsect; 674 u8 hob_lbal; 675 u8 hob_lbam; 676 u8 hob_lbah; 677 }__attribute__((packed, aligned (4))); 678 679 struct ipr_auto_sense { 680 __be16 auto_sense_len; 681 __be16 ioa_data_len; 682 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; 683 }; 684 685 struct ipr_ioasa_hdr { 686 __be32 ioasc; 687 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) 688 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) 689 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) 690 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) 691 692 __be16 ret_stat_len; /* Length of the returned IOASA */ 693 694 __be16 avail_stat_len; /* Total Length of status available. */ 695 696 __be32 residual_data_len; /* number of bytes in the host data */ 697 /* buffers that were not used by the IOARCB command. */ 698 699 __be32 ilid; 700 #define IPR_NO_ILID 0 701 #define IPR_DRIVER_ILID 0xffffffff 702 703 __be32 fd_ioasc; 704 705 __be32 fd_phys_locator; 706 707 __be32 fd_res_handle; 708 709 __be32 ioasc_specific; /* status code specific field */ 710 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 711 #define IPR_AUTOSENSE_VALID 0x40000000 712 #define IPR_ATA_DEVICE_WAS_RESET 0x20000000 713 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff 714 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) 715 #define IPR_FIELD_POINTER_MASK 0x0000ffff 716 717 }__attribute__((packed, aligned (4))); 718 719 struct ipr_ioasa { 720 struct ipr_ioasa_hdr hdr; 721 722 union { 723 struct ipr_ioasa_vset vset; 724 struct ipr_ioasa_af_dasd dasd; 725 struct ipr_ioasa_gpdd gpdd; 726 struct ipr_ioasa_gata gata; 727 } u; 728 729 struct ipr_auto_sense auto_sense; 730 }__attribute__((packed, aligned (4))); 731 732 struct ipr_ioasa64 { 733 struct ipr_ioasa_hdr hdr; 734 u8 fd_res_path[8]; 735 736 union { 737 struct ipr_ioasa_vset vset; 738 struct ipr_ioasa_af_dasd dasd; 739 struct ipr_ioasa_gpdd gpdd; 740 struct ipr_ioasa_gata gata; 741 } u; 742 743 struct ipr_auto_sense auto_sense; 744 }__attribute__((packed, aligned (4))); 745 746 struct ipr_mode_parm_hdr { 747 u8 length; 748 u8 medium_type; 749 u8 device_spec_parms; 750 u8 block_desc_len; 751 }__attribute__((packed)); 752 753 struct ipr_mode_pages { 754 struct ipr_mode_parm_hdr hdr; 755 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; 756 }__attribute__((packed)); 757 758 struct ipr_mode_page_hdr { 759 u8 ps_page_code; 760 #define IPR_MODE_PAGE_PS 0x80 761 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) 762 u8 page_length; 763 }__attribute__ ((packed)); 764 765 struct ipr_dev_bus_entry { 766 struct ipr_res_addr res_addr; 767 u8 flags; 768 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 769 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 770 #define IPR_SCSI_ATTR_QAS_MASK 0xC0 771 #define IPR_SCSI_ATTR_ENABLE_TM 0x20 772 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 773 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 774 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 775 776 u8 scsi_id; 777 u8 bus_width; 778 u8 extended_reset_delay; 779 #define IPR_EXTENDED_RESET_DELAY 7 780 781 __be32 max_xfer_rate; 782 783 u8 spinup_delay; 784 u8 reserved3; 785 __be16 reserved4; 786 }__attribute__((packed, aligned (4))); 787 788 struct ipr_mode_page28 { 789 struct ipr_mode_page_hdr hdr; 790 u8 num_entries; 791 u8 entry_length; 792 struct ipr_dev_bus_entry bus[0]; 793 }__attribute__((packed)); 794 795 struct ipr_mode_page24 { 796 struct ipr_mode_page_hdr hdr; 797 u8 flags; 798 #define IPR_ENABLE_DUAL_IOA_AF 0x80 799 }__attribute__((packed)); 800 801 struct ipr_ioa_vpd { 802 struct ipr_std_inq_data std_inq_data; 803 u8 ascii_part_num[12]; 804 u8 reserved[40]; 805 u8 ascii_plant_code[4]; 806 }__attribute__((packed)); 807 808 struct ipr_inquiry_page3 { 809 u8 peri_qual_dev_type; 810 u8 page_code; 811 u8 reserved1; 812 u8 page_length; 813 u8 ascii_len; 814 u8 reserved2[3]; 815 u8 load_id[4]; 816 u8 major_release; 817 u8 card_type; 818 u8 minor_release[2]; 819 u8 ptf_number[4]; 820 u8 patch_number[4]; 821 }__attribute__((packed)); 822 823 struct ipr_inquiry_cap { 824 u8 peri_qual_dev_type; 825 u8 page_code; 826 u8 reserved1; 827 u8 page_length; 828 u8 ascii_len; 829 u8 reserved2; 830 u8 sis_version[2]; 831 u8 cap; 832 #define IPR_CAP_DUAL_IOA_RAID 0x80 833 u8 reserved3[15]; 834 }__attribute__((packed)); 835 836 #define IPR_INQUIRY_PAGE0_ENTRIES 20 837 struct ipr_inquiry_page0 { 838 u8 peri_qual_dev_type; 839 u8 page_code; 840 u8 reserved1; 841 u8 len; 842 u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; 843 }__attribute__((packed)); 844 845 struct ipr_hostrcb_device_data_entry { 846 struct ipr_vpd vpd; 847 struct ipr_res_addr dev_res_addr; 848 struct ipr_vpd new_vpd; 849 struct ipr_vpd ioa_last_with_dev_vpd; 850 struct ipr_vpd cfc_last_with_dev_vpd; 851 __be32 ioa_data[5]; 852 }__attribute__((packed, aligned (4))); 853 854 struct ipr_hostrcb_device_data_entry_enhanced { 855 struct ipr_ext_vpd vpd; 856 u8 ccin[4]; 857 struct ipr_res_addr dev_res_addr; 858 struct ipr_ext_vpd new_vpd; 859 u8 new_ccin[4]; 860 struct ipr_ext_vpd ioa_last_with_dev_vpd; 861 struct ipr_ext_vpd cfc_last_with_dev_vpd; 862 }__attribute__((packed, aligned (4))); 863 864 struct ipr_hostrcb64_device_data_entry_enhanced { 865 struct ipr_ext_vpd vpd; 866 u8 ccin[4]; 867 u8 res_path[8]; 868 struct ipr_ext_vpd new_vpd; 869 u8 new_ccin[4]; 870 struct ipr_ext_vpd ioa_last_with_dev_vpd; 871 struct ipr_ext_vpd cfc_last_with_dev_vpd; 872 }__attribute__((packed, aligned (4))); 873 874 struct ipr_hostrcb_array_data_entry { 875 struct ipr_vpd vpd; 876 struct ipr_res_addr expected_dev_res_addr; 877 struct ipr_res_addr dev_res_addr; 878 }__attribute__((packed, aligned (4))); 879 880 struct ipr_hostrcb64_array_data_entry { 881 struct ipr_ext_vpd vpd; 882 u8 ccin[4]; 883 u8 expected_res_path[8]; 884 u8 res_path[8]; 885 }__attribute__((packed, aligned (4))); 886 887 struct ipr_hostrcb_array_data_entry_enhanced { 888 struct ipr_ext_vpd vpd; 889 u8 ccin[4]; 890 struct ipr_res_addr expected_dev_res_addr; 891 struct ipr_res_addr dev_res_addr; 892 }__attribute__((packed, aligned (4))); 893 894 struct ipr_hostrcb_type_ff_error { 895 __be32 ioa_data[758]; 896 }__attribute__((packed, aligned (4))); 897 898 struct ipr_hostrcb_type_01_error { 899 __be32 seek_counter; 900 __be32 read_counter; 901 u8 sense_data[32]; 902 __be32 ioa_data[236]; 903 }__attribute__((packed, aligned (4))); 904 905 struct ipr_hostrcb_type_21_error { 906 __be32 wwn[4]; 907 u8 res_path[8]; 908 u8 primary_problem_desc[32]; 909 u8 second_problem_desc[32]; 910 __be32 sense_data[8]; 911 __be32 cdb[4]; 912 __be32 residual_trans_length; 913 __be32 length_of_error; 914 __be32 ioa_data[236]; 915 }__attribute__((packed, aligned (4))); 916 917 struct ipr_hostrcb_type_02_error { 918 struct ipr_vpd ioa_vpd; 919 struct ipr_vpd cfc_vpd; 920 struct ipr_vpd ioa_last_attached_to_cfc_vpd; 921 struct ipr_vpd cfc_last_attached_to_ioa_vpd; 922 __be32 ioa_data[3]; 923 }__attribute__((packed, aligned (4))); 924 925 struct ipr_hostrcb_type_12_error { 926 struct ipr_ext_vpd ioa_vpd; 927 struct ipr_ext_vpd cfc_vpd; 928 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; 929 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; 930 __be32 ioa_data[3]; 931 }__attribute__((packed, aligned (4))); 932 933 struct ipr_hostrcb_type_03_error { 934 struct ipr_vpd ioa_vpd; 935 struct ipr_vpd cfc_vpd; 936 __be32 errors_detected; 937 __be32 errors_logged; 938 u8 ioa_data[12]; 939 struct ipr_hostrcb_device_data_entry dev[3]; 940 }__attribute__((packed, aligned (4))); 941 942 struct ipr_hostrcb_type_13_error { 943 struct ipr_ext_vpd ioa_vpd; 944 struct ipr_ext_vpd cfc_vpd; 945 __be32 errors_detected; 946 __be32 errors_logged; 947 struct ipr_hostrcb_device_data_entry_enhanced dev[3]; 948 }__attribute__((packed, aligned (4))); 949 950 struct ipr_hostrcb_type_23_error { 951 struct ipr_ext_vpd ioa_vpd; 952 struct ipr_ext_vpd cfc_vpd; 953 __be32 errors_detected; 954 __be32 errors_logged; 955 struct ipr_hostrcb64_device_data_entry_enhanced dev[3]; 956 }__attribute__((packed, aligned (4))); 957 958 struct ipr_hostrcb_type_04_error { 959 struct ipr_vpd ioa_vpd; 960 struct ipr_vpd cfc_vpd; 961 u8 ioa_data[12]; 962 struct ipr_hostrcb_array_data_entry array_member[10]; 963 __be32 exposed_mode_adn; 964 __be32 array_id; 965 struct ipr_vpd incomp_dev_vpd; 966 __be32 ioa_data2; 967 struct ipr_hostrcb_array_data_entry array_member2[8]; 968 struct ipr_res_addr last_func_vset_res_addr; 969 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 970 u8 protection_level[8]; 971 }__attribute__((packed, aligned (4))); 972 973 struct ipr_hostrcb_type_14_error { 974 struct ipr_ext_vpd ioa_vpd; 975 struct ipr_ext_vpd cfc_vpd; 976 __be32 exposed_mode_adn; 977 __be32 array_id; 978 struct ipr_res_addr last_func_vset_res_addr; 979 u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; 980 u8 protection_level[8]; 981 __be32 num_entries; 982 struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; 983 }__attribute__((packed, aligned (4))); 984 985 struct ipr_hostrcb_type_24_error { 986 struct ipr_ext_vpd ioa_vpd; 987 struct ipr_ext_vpd cfc_vpd; 988 u8 reserved[2]; 989 u8 exposed_mode_adn; 990 #define IPR_INVALID_ARRAY_DEV_NUM 0xff 991 u8 array_id; 992 u8 last_res_path[8]; 993 u8 protection_level[8]; 994 struct ipr_ext_vpd64 array_vpd; 995 u8 description[16]; 996 u8 reserved2[3]; 997 u8 num_entries; 998 struct ipr_hostrcb64_array_data_entry array_member[32]; 999 }__attribute__((packed, aligned (4))); 1000 1001 struct ipr_hostrcb_type_07_error { 1002 u8 failure_reason[64]; 1003 struct ipr_vpd vpd; 1004 u32 data[222]; 1005 }__attribute__((packed, aligned (4))); 1006 1007 struct ipr_hostrcb_type_17_error { 1008 u8 failure_reason[64]; 1009 struct ipr_ext_vpd vpd; 1010 u32 data[476]; 1011 }__attribute__((packed, aligned (4))); 1012 1013 struct ipr_hostrcb_config_element { 1014 u8 type_status; 1015 #define IPR_PATH_CFG_TYPE_MASK 0xF0 1016 #define IPR_PATH_CFG_NOT_EXIST 0x00 1017 #define IPR_PATH_CFG_IOA_PORT 0x10 1018 #define IPR_PATH_CFG_EXP_PORT 0x20 1019 #define IPR_PATH_CFG_DEVICE_PORT 0x30 1020 #define IPR_PATH_CFG_DEVICE_LUN 0x40 1021 1022 #define IPR_PATH_CFG_STATUS_MASK 0x0F 1023 #define IPR_PATH_CFG_NO_PROB 0x00 1024 #define IPR_PATH_CFG_DEGRADED 0x01 1025 #define IPR_PATH_CFG_FAILED 0x02 1026 #define IPR_PATH_CFG_SUSPECT 0x03 1027 #define IPR_PATH_NOT_DETECTED 0x04 1028 #define IPR_PATH_INCORRECT_CONN 0x05 1029 1030 u8 cascaded_expander; 1031 u8 phy; 1032 u8 link_rate; 1033 #define IPR_PHY_LINK_RATE_MASK 0x0F 1034 1035 __be32 wwid[2]; 1036 }__attribute__((packed, aligned (4))); 1037 1038 struct ipr_hostrcb64_config_element { 1039 __be16 length; 1040 u8 descriptor_id; 1041 #define IPR_DESCRIPTOR_MASK 0xC0 1042 #define IPR_DESCRIPTOR_SIS64 0x00 1043 1044 u8 reserved; 1045 u8 type_status; 1046 1047 u8 reserved2[2]; 1048 u8 link_rate; 1049 1050 u8 res_path[8]; 1051 __be32 wwid[2]; 1052 }__attribute__((packed, aligned (8))); 1053 1054 struct ipr_hostrcb_fabric_desc { 1055 __be16 length; 1056 u8 ioa_port; 1057 u8 cascaded_expander; 1058 u8 phy; 1059 u8 path_state; 1060 #define IPR_PATH_ACTIVE_MASK 0xC0 1061 #define IPR_PATH_NO_INFO 0x00 1062 #define IPR_PATH_ACTIVE 0x40 1063 #define IPR_PATH_NOT_ACTIVE 0x80 1064 1065 #define IPR_PATH_STATE_MASK 0x0F 1066 #define IPR_PATH_STATE_NO_INFO 0x00 1067 #define IPR_PATH_HEALTHY 0x01 1068 #define IPR_PATH_DEGRADED 0x02 1069 #define IPR_PATH_FAILED 0x03 1070 1071 __be16 num_entries; 1072 struct ipr_hostrcb_config_element elem[1]; 1073 }__attribute__((packed, aligned (4))); 1074 1075 struct ipr_hostrcb64_fabric_desc { 1076 __be16 length; 1077 u8 descriptor_id; 1078 1079 u8 reserved[2]; 1080 u8 path_state; 1081 1082 u8 reserved2[2]; 1083 u8 res_path[8]; 1084 u8 reserved3[6]; 1085 __be16 num_entries; 1086 struct ipr_hostrcb64_config_element elem[1]; 1087 }__attribute__((packed, aligned (8))); 1088 1089 #define for_each_hrrq(hrrq, ioa_cfg) \ 1090 for (hrrq = (ioa_cfg)->hrrq; \ 1091 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++) 1092 1093 #define for_each_fabric_cfg(fabric, cfg) \ 1094 for (cfg = (fabric)->elem; \ 1095 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ 1096 cfg++) 1097 1098 struct ipr_hostrcb_type_20_error { 1099 u8 failure_reason[64]; 1100 u8 reserved[3]; 1101 u8 num_entries; 1102 struct ipr_hostrcb_fabric_desc desc[1]; 1103 }__attribute__((packed, aligned (4))); 1104 1105 struct ipr_hostrcb_type_30_error { 1106 u8 failure_reason[64]; 1107 u8 reserved[3]; 1108 u8 num_entries; 1109 struct ipr_hostrcb64_fabric_desc desc[1]; 1110 }__attribute__((packed, aligned (4))); 1111 1112 struct ipr_hostrcb_error { 1113 __be32 fd_ioasc; 1114 struct ipr_res_addr fd_res_addr; 1115 __be32 fd_res_handle; 1116 __be32 prc; 1117 union { 1118 struct ipr_hostrcb_type_ff_error type_ff_error; 1119 struct ipr_hostrcb_type_01_error type_01_error; 1120 struct ipr_hostrcb_type_02_error type_02_error; 1121 struct ipr_hostrcb_type_03_error type_03_error; 1122 struct ipr_hostrcb_type_04_error type_04_error; 1123 struct ipr_hostrcb_type_07_error type_07_error; 1124 struct ipr_hostrcb_type_12_error type_12_error; 1125 struct ipr_hostrcb_type_13_error type_13_error; 1126 struct ipr_hostrcb_type_14_error type_14_error; 1127 struct ipr_hostrcb_type_17_error type_17_error; 1128 struct ipr_hostrcb_type_20_error type_20_error; 1129 } u; 1130 }__attribute__((packed, aligned (4))); 1131 1132 struct ipr_hostrcb64_error { 1133 __be32 fd_ioasc; 1134 __be32 ioa_fw_level; 1135 __be32 fd_res_handle; 1136 __be32 prc; 1137 __be64 fd_dev_id; 1138 __be64 fd_lun; 1139 u8 fd_res_path[8]; 1140 __be64 time_stamp; 1141 u8 reserved[16]; 1142 union { 1143 struct ipr_hostrcb_type_ff_error type_ff_error; 1144 struct ipr_hostrcb_type_12_error type_12_error; 1145 struct ipr_hostrcb_type_17_error type_17_error; 1146 struct ipr_hostrcb_type_21_error type_21_error; 1147 struct ipr_hostrcb_type_23_error type_23_error; 1148 struct ipr_hostrcb_type_24_error type_24_error; 1149 struct ipr_hostrcb_type_30_error type_30_error; 1150 } u; 1151 }__attribute__((packed, aligned (8))); 1152 1153 struct ipr_hostrcb_raw { 1154 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; 1155 }__attribute__((packed, aligned (4))); 1156 1157 struct ipr_hcam { 1158 u8 op_code; 1159 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 1160 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 1161 1162 u8 notify_type; 1163 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 1164 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 1165 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 1166 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 1167 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 1168 1169 u8 notifications_lost; 1170 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 1171 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 1172 1173 u8 flags; 1174 #define IPR_HOSTRCB_INTERNAL_OPER 0x80 1175 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 1176 1177 u8 overlay_id; 1178 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 1179 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 1180 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 1181 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 1182 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 1183 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 1184 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 1185 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 1186 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 1187 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 1188 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 1189 #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 1190 #define IPR_HOST_RCB_OVERLAY_ID_21 0x21 1191 #define IPR_HOST_RCB_OVERLAY_ID_23 0x23 1192 #define IPR_HOST_RCB_OVERLAY_ID_24 0x24 1193 #define IPR_HOST_RCB_OVERLAY_ID_26 0x26 1194 #define IPR_HOST_RCB_OVERLAY_ID_30 0x30 1195 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF 1196 1197 u8 reserved1[3]; 1198 __be32 ilid; 1199 __be32 time_since_last_ioa_reset; 1200 __be32 reserved2; 1201 __be32 length; 1202 1203 union { 1204 struct ipr_hostrcb_error error; 1205 struct ipr_hostrcb64_error error64; 1206 struct ipr_hostrcb_cfg_ch_not ccn; 1207 struct ipr_hostrcb_raw raw; 1208 } u; 1209 }__attribute__((packed, aligned (4))); 1210 1211 struct ipr_hostrcb { 1212 struct ipr_hcam hcam; 1213 dma_addr_t hostrcb_dma; 1214 struct list_head queue; 1215 struct ipr_ioa_cfg *ioa_cfg; 1216 char rp_buffer[IPR_MAX_RES_PATH_LENGTH]; 1217 }; 1218 1219 /* IPR smart dump table structures */ 1220 struct ipr_sdt_entry { 1221 __be32 start_token; 1222 __be32 end_token; 1223 u8 reserved[4]; 1224 1225 u8 flags; 1226 #define IPR_SDT_ENDIAN 0x80 1227 #define IPR_SDT_VALID_ENTRY 0x20 1228 1229 u8 resv; 1230 __be16 priority; 1231 }__attribute__((packed, aligned (4))); 1232 1233 struct ipr_sdt_header { 1234 __be32 state; 1235 __be32 num_entries; 1236 __be32 num_entries_used; 1237 __be32 dump_size; 1238 }__attribute__((packed, aligned (4))); 1239 1240 struct ipr_sdt { 1241 struct ipr_sdt_header hdr; 1242 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES]; 1243 }__attribute__((packed, aligned (4))); 1244 1245 struct ipr_uc_sdt { 1246 struct ipr_sdt_header hdr; 1247 struct ipr_sdt_entry entry[1]; 1248 }__attribute__((packed, aligned (4))); 1249 1250 /* 1251 * Driver types 1252 */ 1253 struct ipr_bus_attributes { 1254 u8 bus; 1255 u8 qas_enabled; 1256 u8 bus_width; 1257 u8 reserved; 1258 u32 max_xfer_rate; 1259 }; 1260 1261 struct ipr_sata_port { 1262 struct ipr_ioa_cfg *ioa_cfg; 1263 struct ata_port *ap; 1264 struct ipr_resource_entry *res; 1265 struct ipr_ioasa_gata ioasa; 1266 }; 1267 1268 struct ipr_resource_entry { 1269 u8 needs_sync_complete:1; 1270 u8 in_erp:1; 1271 u8 add_to_ml:1; 1272 u8 del_from_ml:1; 1273 u8 resetting_device:1; 1274 u8 reset_occurred:1; 1275 1276 u32 bus; /* AKA channel */ 1277 u32 target; /* AKA id */ 1278 u32 lun; 1279 #define IPR_ARRAY_VIRTUAL_BUS 0x1 1280 #define IPR_VSET_VIRTUAL_BUS 0x2 1281 #define IPR_IOAFP_VIRTUAL_BUS 0x3 1282 1283 #define IPR_GET_RES_PHYS_LOC(res) \ 1284 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) 1285 1286 u8 ata_class; 1287 1288 u8 flags; 1289 __be16 res_flags; 1290 1291 u8 type; 1292 1293 u8 qmodel; 1294 struct ipr_std_inq_data std_inq_data; 1295 1296 __be32 res_handle; 1297 __be64 dev_id; 1298 __be64 lun_wwn; 1299 struct scsi_lun dev_lun; 1300 u8 res_path[8]; 1301 1302 struct ipr_ioa_cfg *ioa_cfg; 1303 struct scsi_device *sdev; 1304 struct ipr_sata_port *sata_port; 1305 struct list_head queue; 1306 }; /* struct ipr_resource_entry */ 1307 1308 struct ipr_resource_hdr { 1309 u16 num_entries; 1310 u16 reserved; 1311 }; 1312 1313 struct ipr_misc_cbs { 1314 struct ipr_ioa_vpd ioa_vpd; 1315 struct ipr_inquiry_page0 page0_data; 1316 struct ipr_inquiry_page3 page3_data; 1317 struct ipr_inquiry_cap cap; 1318 struct ipr_mode_pages mode_pages; 1319 struct ipr_supported_device supp_dev; 1320 }; 1321 1322 struct ipr_interrupt_offsets { 1323 unsigned long set_interrupt_mask_reg; 1324 unsigned long clr_interrupt_mask_reg; 1325 unsigned long clr_interrupt_mask_reg32; 1326 unsigned long sense_interrupt_mask_reg; 1327 unsigned long sense_interrupt_mask_reg32; 1328 unsigned long clr_interrupt_reg; 1329 unsigned long clr_interrupt_reg32; 1330 1331 unsigned long sense_interrupt_reg; 1332 unsigned long sense_interrupt_reg32; 1333 unsigned long ioarrin_reg; 1334 unsigned long sense_uproc_interrupt_reg; 1335 unsigned long sense_uproc_interrupt_reg32; 1336 unsigned long set_uproc_interrupt_reg; 1337 unsigned long set_uproc_interrupt_reg32; 1338 unsigned long clr_uproc_interrupt_reg; 1339 unsigned long clr_uproc_interrupt_reg32; 1340 1341 unsigned long init_feedback_reg; 1342 1343 unsigned long dump_addr_reg; 1344 unsigned long dump_data_reg; 1345 1346 #define IPR_ENDIAN_SWAP_KEY 0x00080800 1347 unsigned long endian_swap_reg; 1348 }; 1349 1350 struct ipr_interrupts { 1351 void __iomem *set_interrupt_mask_reg; 1352 void __iomem *clr_interrupt_mask_reg; 1353 void __iomem *clr_interrupt_mask_reg32; 1354 void __iomem *sense_interrupt_mask_reg; 1355 void __iomem *sense_interrupt_mask_reg32; 1356 void __iomem *clr_interrupt_reg; 1357 void __iomem *clr_interrupt_reg32; 1358 1359 void __iomem *sense_interrupt_reg; 1360 void __iomem *sense_interrupt_reg32; 1361 void __iomem *ioarrin_reg; 1362 void __iomem *sense_uproc_interrupt_reg; 1363 void __iomem *sense_uproc_interrupt_reg32; 1364 void __iomem *set_uproc_interrupt_reg; 1365 void __iomem *set_uproc_interrupt_reg32; 1366 void __iomem *clr_uproc_interrupt_reg; 1367 void __iomem *clr_uproc_interrupt_reg32; 1368 1369 void __iomem *init_feedback_reg; 1370 1371 void __iomem *dump_addr_reg; 1372 void __iomem *dump_data_reg; 1373 1374 void __iomem *endian_swap_reg; 1375 }; 1376 1377 struct ipr_chip_cfg_t { 1378 u32 mailbox; 1379 u16 max_cmds; 1380 u8 cache_line_size; 1381 u8 clear_isr; 1382 u32 iopoll_weight; 1383 struct ipr_interrupt_offsets regs; 1384 }; 1385 1386 struct ipr_chip_t { 1387 u16 vendor; 1388 u16 device; 1389 u16 intr_type; 1390 #define IPR_USE_LSI 0x00 1391 #define IPR_USE_MSI 0x01 1392 #define IPR_USE_MSIX 0x02 1393 u16 sis_type; 1394 #define IPR_SIS32 0x00 1395 #define IPR_SIS64 0x01 1396 u16 bist_method; 1397 #define IPR_PCI_CFG 0x00 1398 #define IPR_MMIO 0x01 1399 const struct ipr_chip_cfg_t *cfg; 1400 }; 1401 1402 enum ipr_shutdown_type { 1403 IPR_SHUTDOWN_NORMAL = 0x00, 1404 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, 1405 IPR_SHUTDOWN_ABBREV = 0x80, 1406 IPR_SHUTDOWN_NONE = 0x100 1407 }; 1408 1409 struct ipr_trace_entry { 1410 u32 time; 1411 1412 u8 op_code; 1413 u8 ata_op_code; 1414 u8 type; 1415 #define IPR_TRACE_START 0x00 1416 #define IPR_TRACE_FINISH 0xff 1417 u8 cmd_index; 1418 1419 __be32 res_handle; 1420 union { 1421 u32 ioasc; 1422 u32 add_data; 1423 u32 res_addr; 1424 } u; 1425 }; 1426 1427 struct ipr_sglist { 1428 u32 order; 1429 u32 num_sg; 1430 u32 num_dma_sg; 1431 u32 buffer_len; 1432 struct scatterlist scatterlist[1]; 1433 }; 1434 1435 enum ipr_sdt_state { 1436 INACTIVE, 1437 WAIT_FOR_DUMP, 1438 GET_DUMP, 1439 READ_DUMP, 1440 ABORT_DUMP, 1441 DUMP_OBTAINED 1442 }; 1443 1444 /* Per-controller data */ 1445 struct ipr_ioa_cfg { 1446 char eye_catcher[8]; 1447 #define IPR_EYECATCHER "iprcfg" 1448 1449 struct list_head queue; 1450 1451 u8 in_reset_reload:1; 1452 u8 in_ioa_bringdown:1; 1453 u8 ioa_unit_checked:1; 1454 u8 dump_taken:1; 1455 u8 allow_ml_add_del:1; 1456 u8 needs_hard_reset:1; 1457 u8 dual_raid:1; 1458 u8 needs_warm_reset:1; 1459 u8 msi_received:1; 1460 u8 sis64:1; 1461 u8 dump_timeout:1; 1462 u8 cfg_locked:1; 1463 u8 clear_isr:1; 1464 u8 probe_done:1; 1465 1466 u8 revid; 1467 1468 /* 1469 * Bitmaps for SIS64 generated target values 1470 */ 1471 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; 1472 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; 1473 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; 1474 1475 u16 type; /* CCIN of the card */ 1476 1477 u8 log_level; 1478 #define IPR_MAX_LOG_LEVEL 4 1479 #define IPR_DEFAULT_LOG_LEVEL 2 1480 1481 #define IPR_NUM_TRACE_INDEX_BITS 8 1482 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) 1483 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) 1484 char trace_start[8]; 1485 #define IPR_TRACE_START_LABEL "trace" 1486 struct ipr_trace_entry *trace; 1487 atomic_t trace_index; 1488 1489 char cfg_table_start[8]; 1490 #define IPR_CFG_TBL_START "cfg" 1491 union { 1492 struct ipr_config_table *cfg_table; 1493 struct ipr_config_table64 *cfg_table64; 1494 } u; 1495 dma_addr_t cfg_table_dma; 1496 u32 cfg_table_size; 1497 u32 max_devs_supported; 1498 1499 char resource_table_label[8]; 1500 #define IPR_RES_TABLE_LABEL "res_tbl" 1501 struct ipr_resource_entry *res_entries; 1502 struct list_head free_res_q; 1503 struct list_head used_res_q; 1504 1505 char ipr_hcam_label[8]; 1506 #define IPR_HCAM_LABEL "hcams" 1507 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; 1508 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; 1509 struct list_head hostrcb_free_q; 1510 struct list_head hostrcb_pending_q; 1511 1512 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM]; 1513 u32 hrrq_num; 1514 atomic_t hrrq_index; 1515 u16 identify_hrrq_index; 1516 1517 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; 1518 1519 unsigned int transop_timeout; 1520 const struct ipr_chip_cfg_t *chip_cfg; 1521 const struct ipr_chip_t *ipr_chip; 1522 1523 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ 1524 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ 1525 void __iomem *ioa_mailbox; 1526 struct ipr_interrupts regs; 1527 1528 u16 saved_pcix_cmd_reg; 1529 u16 reset_retries; 1530 1531 u32 errors_logged; 1532 u32 doorbell; 1533 1534 struct Scsi_Host *host; 1535 struct pci_dev *pdev; 1536 struct ipr_sglist *ucode_sglist; 1537 u8 saved_mode_page_len; 1538 1539 struct work_struct work_q; 1540 1541 wait_queue_head_t reset_wait_q; 1542 wait_queue_head_t msi_wait_q; 1543 wait_queue_head_t eeh_wait_q; 1544 1545 struct ipr_dump *dump; 1546 enum ipr_sdt_state sdt_state; 1547 1548 struct ipr_misc_cbs *vpd_cbs; 1549 dma_addr_t vpd_cbs_dma; 1550 1551 struct pci_pool *ipr_cmd_pool; 1552 1553 struct ipr_cmnd *reset_cmd; 1554 int (*reset) (struct ipr_cmnd *); 1555 1556 struct ata_host ata_host; 1557 char ipr_cmd_label[8]; 1558 #define IPR_CMD_LABEL "ipr_cmd" 1559 u32 max_cmds; 1560 struct ipr_cmnd **ipr_cmnd_list; 1561 dma_addr_t *ipr_cmnd_list_dma; 1562 1563 u16 intr_flag; 1564 unsigned int nvectors; 1565 1566 struct { 1567 unsigned short vec; 1568 char desc[22]; 1569 } vectors_info[IPR_MAX_MSIX_VECTORS]; 1570 1571 u32 iopoll_weight; 1572 1573 }; /* struct ipr_ioa_cfg */ 1574 1575 struct ipr_cmnd { 1576 struct ipr_ioarcb ioarcb; 1577 union { 1578 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; 1579 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; 1580 struct ipr_ata64_ioadl ata_ioadl; 1581 } i; 1582 union { 1583 struct ipr_ioasa ioasa; 1584 struct ipr_ioasa64 ioasa64; 1585 } s; 1586 struct list_head queue; 1587 struct scsi_cmnd *scsi_cmd; 1588 struct ata_queued_cmd *qc; 1589 struct completion completion; 1590 struct timer_list timer; 1591 void (*fast_done) (struct ipr_cmnd *); 1592 void (*done) (struct ipr_cmnd *); 1593 int (*job_step) (struct ipr_cmnd *); 1594 int (*job_step_failed) (struct ipr_cmnd *); 1595 u16 cmd_index; 1596 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; 1597 dma_addr_t sense_buffer_dma; 1598 unsigned short dma_use_sg; 1599 dma_addr_t dma_addr; 1600 struct ipr_cmnd *sibling; 1601 union { 1602 enum ipr_shutdown_type shutdown_type; 1603 struct ipr_hostrcb *hostrcb; 1604 unsigned long time_left; 1605 unsigned long scratch; 1606 struct ipr_resource_entry *res; 1607 struct scsi_device *sdev; 1608 } u; 1609 1610 struct ipr_hrr_queue *hrrq; 1611 struct ipr_ioa_cfg *ioa_cfg; 1612 }; 1613 1614 struct ipr_ses_table_entry { 1615 char product_id[17]; 1616 char compare_product_id_byte[17]; 1617 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ 1618 }; 1619 1620 struct ipr_dump_header { 1621 u32 eye_catcher; 1622 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1623 u32 len; 1624 u32 num_entries; 1625 u32 first_entry_offset; 1626 u32 status; 1627 #define IPR_DUMP_STATUS_SUCCESS 0 1628 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 1629 #define IPR_DUMP_STATUS_FAILED 0xffffffff 1630 u32 os; 1631 #define IPR_DUMP_OS_LINUX 0x4C4E5558 1632 u32 driver_name; 1633 #define IPR_DUMP_DRIVER_NAME 0x49505232 1634 }__attribute__((packed, aligned (4))); 1635 1636 struct ipr_dump_entry_header { 1637 u32 eye_catcher; 1638 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 1639 u32 len; 1640 u32 num_elems; 1641 u32 offset; 1642 u32 data_type; 1643 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 1644 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 1645 u32 id; 1646 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 1647 #define IPR_DUMP_LOCATION_ID 0x4C4F4341 1648 #define IPR_DUMP_TRACE_ID 0x54524143 1649 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 1650 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 1651 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 1652 #define IPR_DUMP_PEND_OPS 0x414F5053 1653 u32 status; 1654 }__attribute__((packed, aligned (4))); 1655 1656 struct ipr_dump_location_entry { 1657 struct ipr_dump_entry_header hdr; 1658 u8 location[20]; 1659 }__attribute__((packed)); 1660 1661 struct ipr_dump_trace_entry { 1662 struct ipr_dump_entry_header hdr; 1663 u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; 1664 }__attribute__((packed, aligned (4))); 1665 1666 struct ipr_dump_version_entry { 1667 struct ipr_dump_entry_header hdr; 1668 u8 version[sizeof(IPR_DRIVER_VERSION)]; 1669 }; 1670 1671 struct ipr_dump_ioa_type_entry { 1672 struct ipr_dump_entry_header hdr; 1673 u32 type; 1674 u32 fw_version; 1675 }; 1676 1677 struct ipr_driver_dump { 1678 struct ipr_dump_header hdr; 1679 struct ipr_dump_version_entry version_entry; 1680 struct ipr_dump_location_entry location_entry; 1681 struct ipr_dump_ioa_type_entry ioa_type_entry; 1682 struct ipr_dump_trace_entry trace_entry; 1683 }__attribute__((packed)); 1684 1685 struct ipr_ioa_dump { 1686 struct ipr_dump_entry_header hdr; 1687 struct ipr_sdt sdt; 1688 __be32 **ioa_data; 1689 u32 reserved; 1690 u32 next_page_index; 1691 u32 page_offset; 1692 u32 format; 1693 }__attribute__((packed, aligned (4))); 1694 1695 struct ipr_dump { 1696 struct kref kref; 1697 struct ipr_ioa_cfg *ioa_cfg; 1698 struct ipr_driver_dump driver_dump; 1699 struct ipr_ioa_dump ioa_dump; 1700 }; 1701 1702 struct ipr_error_table_t { 1703 u32 ioasc; 1704 int log_ioasa; 1705 int log_hcam; 1706 char *error; 1707 }; 1708 1709 struct ipr_software_inq_lid_info { 1710 __be32 load_id; 1711 __be32 timestamp[3]; 1712 }__attribute__((packed, aligned (4))); 1713 1714 struct ipr_ucode_image_header { 1715 __be32 header_length; 1716 __be32 lid_table_offset; 1717 u8 major_release; 1718 u8 card_type; 1719 u8 minor_release[2]; 1720 u8 reserved[20]; 1721 char eyecatcher[16]; 1722 __be32 num_lids; 1723 struct ipr_software_inq_lid_info lid[1]; 1724 }__attribute__((packed, aligned (4))); 1725 1726 /* 1727 * Macros 1728 */ 1729 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } 1730 1731 #ifdef CONFIG_SCSI_IPR_TRACE 1732 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1733 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1734 #else 1735 #define ipr_create_trace_file(kobj, attr) 0 1736 #define ipr_remove_trace_file(kobj, attr) do { } while(0) 1737 #endif 1738 1739 #ifdef CONFIG_SCSI_IPR_DUMP 1740 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) 1741 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) 1742 #else 1743 #define ipr_create_dump_file(kobj, attr) 0 1744 #define ipr_remove_dump_file(kobj, attr) do { } while(0) 1745 #endif 1746 1747 /* 1748 * Error logging macros 1749 */ 1750 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) 1751 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) 1752 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) 1753 1754 #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \ 1755 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1756 bus, target, lun, ##__VA_ARGS__) 1757 1758 #define ipr_res_err(ioa_cfg, res, fmt, ...) \ 1759 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) 1760 1761 #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ 1762 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ 1763 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) 1764 1765 #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ 1766 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) 1767 1768 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ 1769 { \ 1770 if ((res).bus >= IPR_MAX_NUM_BUSES) { \ 1771 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ 1772 } else { \ 1773 ipr_err(fmt": %d:%d:%d:%d\n", \ 1774 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ 1775 (res).bus, (res).target, (res).lun); \ 1776 } \ 1777 } 1778 1779 #define ipr_hcam_err(hostrcb, fmt, ...) \ 1780 { \ 1781 if (ipr_is_device(hostrcb)) { \ 1782 if ((hostrcb)->ioa_cfg->sis64) { \ 1783 printk(KERN_ERR IPR_NAME ": %s: " fmt, \ 1784 ipr_format_res_path(hostrcb->ioa_cfg, \ 1785 hostrcb->hcam.u.error64.fd_res_path, \ 1786 hostrcb->rp_buffer, \ 1787 sizeof(hostrcb->rp_buffer)), \ 1788 __VA_ARGS__); \ 1789 } else { \ 1790 ipr_ra_err((hostrcb)->ioa_cfg, \ 1791 (hostrcb)->hcam.u.error.fd_res_addr, \ 1792 fmt, __VA_ARGS__); \ 1793 } \ 1794 } else { \ 1795 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \ 1796 } \ 1797 } 1798 1799 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ 1800 __FILE__, __func__, __LINE__) 1801 1802 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) 1803 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) 1804 1805 #define ipr_err_separator \ 1806 ipr_err("----------------------------------------------------------\n") 1807 1808 1809 /* 1810 * Inlines 1811 */ 1812 1813 /** 1814 * ipr_is_ioa_resource - Determine if a resource is the IOA 1815 * @res: resource entry struct 1816 * 1817 * Return value: 1818 * 1 if IOA / 0 if not IOA 1819 **/ 1820 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) 1821 { 1822 return res->type == IPR_RES_TYPE_IOAFP; 1823 } 1824 1825 /** 1826 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD 1827 * @res: resource entry struct 1828 * 1829 * Return value: 1830 * 1 if AF DASD / 0 if not AF DASD 1831 **/ 1832 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) 1833 { 1834 return res->type == IPR_RES_TYPE_AF_DASD || 1835 res->type == IPR_RES_TYPE_REMOTE_AF_DASD; 1836 } 1837 1838 /** 1839 * ipr_is_vset_device - Determine if a resource is a VSET 1840 * @res: resource entry struct 1841 * 1842 * Return value: 1843 * 1 if VSET / 0 if not VSET 1844 **/ 1845 static inline int ipr_is_vset_device(struct ipr_resource_entry *res) 1846 { 1847 return res->type == IPR_RES_TYPE_VOLUME_SET; 1848 } 1849 1850 /** 1851 * ipr_is_gscsi - Determine if a resource is a generic scsi resource 1852 * @res: resource entry struct 1853 * 1854 * Return value: 1855 * 1 if GSCSI / 0 if not GSCSI 1856 **/ 1857 static inline int ipr_is_gscsi(struct ipr_resource_entry *res) 1858 { 1859 return res->type == IPR_RES_TYPE_GENERIC_SCSI; 1860 } 1861 1862 /** 1863 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk 1864 * @res: resource entry struct 1865 * 1866 * Return value: 1867 * 1 if SCSI disk / 0 if not SCSI disk 1868 **/ 1869 static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) 1870 { 1871 if (ipr_is_af_dasd_device(res) || 1872 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data))) 1873 return 1; 1874 else 1875 return 0; 1876 } 1877 1878 /** 1879 * ipr_is_gata - Determine if a resource is a generic ATA resource 1880 * @res: resource entry struct 1881 * 1882 * Return value: 1883 * 1 if GATA / 0 if not GATA 1884 **/ 1885 static inline int ipr_is_gata(struct ipr_resource_entry *res) 1886 { 1887 return res->type == IPR_RES_TYPE_GENERIC_ATA; 1888 } 1889 1890 /** 1891 * ipr_is_naca_model - Determine if a resource is using NACA queueing model 1892 * @res: resource entry struct 1893 * 1894 * Return value: 1895 * 1 if NACA queueing model / 0 if not NACA queueing model 1896 **/ 1897 static inline int ipr_is_naca_model(struct ipr_resource_entry *res) 1898 { 1899 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL) 1900 return 1; 1901 return 0; 1902 } 1903 1904 /** 1905 * ipr_is_device - Determine if the hostrcb structure is related to a device 1906 * @hostrcb: host resource control blocks struct 1907 * 1908 * Return value: 1909 * 1 if AF / 0 if not AF 1910 **/ 1911 static inline int ipr_is_device(struct ipr_hostrcb *hostrcb) 1912 { 1913 struct ipr_res_addr *res_addr; 1914 u8 *res_path; 1915 1916 if (hostrcb->ioa_cfg->sis64) { 1917 res_path = &hostrcb->hcam.u.error64.fd_res_path[0]; 1918 if ((res_path[0] == 0x00 || res_path[0] == 0x80 || 1919 res_path[0] == 0x81) && res_path[2] != 0xFF) 1920 return 1; 1921 } else { 1922 res_addr = &hostrcb->hcam.u.error.fd_res_addr; 1923 1924 if ((res_addr->bus < IPR_MAX_NUM_BUSES) && 1925 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) 1926 return 1; 1927 } 1928 return 0; 1929 } 1930 1931 /** 1932 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 1933 * @sdt_word: SDT address 1934 * 1935 * Return value: 1936 * 1 if format 2 / 0 if not 1937 **/ 1938 static inline int ipr_sdt_is_fmt2(u32 sdt_word) 1939 { 1940 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); 1941 1942 switch (bar_sel) { 1943 case IPR_SDT_FMT2_BAR0_SEL: 1944 case IPR_SDT_FMT2_BAR1_SEL: 1945 case IPR_SDT_FMT2_BAR2_SEL: 1946 case IPR_SDT_FMT2_BAR3_SEL: 1947 case IPR_SDT_FMT2_BAR4_SEL: 1948 case IPR_SDT_FMT2_BAR5_SEL: 1949 case IPR_SDT_FMT2_EXP_ROM_SEL: 1950 return 1; 1951 }; 1952 1953 return 0; 1954 } 1955 1956 #ifndef writeq 1957 static inline void writeq(u64 val, void __iomem *addr) 1958 { 1959 writel(((u32) (val >> 32)), addr); 1960 writel(((u32) (val)), (addr + 4)); 1961 } 1962 #endif 1963 1964 #endif /* _IPR_H */ 1965