1 /* 2 * HighPoint RR3xxx/4xxx controller driver for Linux 3 * Copyright (C) 2006-2009 HighPoint Technologies, Inc. All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * Please report bugs/comments/suggestions to linux@highpoint-tech.com 15 * 16 * For more information, visit http://www.highpoint-tech.com 17 */ 18 #ifndef _HPTIOP_H_ 19 #define _HPTIOP_H_ 20 21 struct hpt_iopmu_itl { 22 __le32 resrved0[4]; 23 __le32 inbound_msgaddr0; 24 __le32 inbound_msgaddr1; 25 __le32 outbound_msgaddr0; 26 __le32 outbound_msgaddr1; 27 __le32 inbound_doorbell; 28 __le32 inbound_intstatus; 29 __le32 inbound_intmask; 30 __le32 outbound_doorbell; 31 __le32 outbound_intstatus; 32 __le32 outbound_intmask; 33 __le32 reserved1[2]; 34 __le32 inbound_queue; 35 __le32 outbound_queue; 36 }; 37 38 #define IOPMU_QUEUE_EMPTY 0xffffffff 39 #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000 40 #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000 41 #define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000 42 #define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000 43 44 #define IOPMU_OUTBOUND_INT_MSG0 1 45 #define IOPMU_OUTBOUND_INT_MSG1 2 46 #define IOPMU_OUTBOUND_INT_DOORBELL 4 47 #define IOPMU_OUTBOUND_INT_POSTQUEUE 8 48 #define IOPMU_OUTBOUND_INT_PCI 0x10 49 50 #define IOPMU_INBOUND_INT_MSG0 1 51 #define IOPMU_INBOUND_INT_MSG1 2 52 #define IOPMU_INBOUND_INT_DOORBELL 4 53 #define IOPMU_INBOUND_INT_ERROR 8 54 #define IOPMU_INBOUND_INT_POSTQUEUE 0x10 55 56 #define MVIOP_QUEUE_LEN 512 57 58 struct hpt_iopmu_mv { 59 __le32 inbound_head; 60 __le32 inbound_tail; 61 __le32 outbound_head; 62 __le32 outbound_tail; 63 __le32 inbound_msg; 64 __le32 outbound_msg; 65 __le32 reserve[10]; 66 __le64 inbound_q[MVIOP_QUEUE_LEN]; 67 __le64 outbound_q[MVIOP_QUEUE_LEN]; 68 }; 69 70 struct hpt_iopmv_regs { 71 __le32 reserved[0x20400 / 4]; 72 __le32 inbound_doorbell; 73 __le32 inbound_intmask; 74 __le32 outbound_doorbell; 75 __le32 outbound_intmask; 76 }; 77 78 #define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full)) 79 #define MVIOP_MU_QUEUE_ADDR_HOST_BIT 4 80 81 #define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32 0xffffffff 82 #define MVIOP_MU_QUEUE_REQUEST_RESULT_BIT 1 83 #define MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT 2 84 85 #define MVIOP_MU_INBOUND_INT_MSG 1 86 #define MVIOP_MU_INBOUND_INT_POSTQUEUE 2 87 #define MVIOP_MU_OUTBOUND_INT_MSG 1 88 #define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2 89 90 enum hpt_iopmu_message { 91 /* host-to-iop messages */ 92 IOPMU_INBOUND_MSG0_NOP = 0, 93 IOPMU_INBOUND_MSG0_RESET, 94 IOPMU_INBOUND_MSG0_FLUSH, 95 IOPMU_INBOUND_MSG0_SHUTDOWN, 96 IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK, 97 IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK, 98 IOPMU_INBOUND_MSG0_MAX = 0xff, 99 /* iop-to-host messages */ 100 IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100, 101 IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff, 102 IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200, 103 IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff, 104 IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300, 105 IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff, 106 }; 107 108 struct hpt_iop_request_header { 109 __le32 size; 110 __le32 type; 111 __le32 flags; 112 __le32 result; 113 __le32 context; /* host context */ 114 __le32 context_hi32; 115 }; 116 117 #define IOP_REQUEST_FLAG_SYNC_REQUEST 1 118 #define IOP_REQUEST_FLAG_BIST_REQUEST 2 119 #define IOP_REQUEST_FLAG_REMAPPED 4 120 #define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8 121 122 enum hpt_iop_request_type { 123 IOP_REQUEST_TYPE_GET_CONFIG = 0, 124 IOP_REQUEST_TYPE_SET_CONFIG, 125 IOP_REQUEST_TYPE_BLOCK_COMMAND, 126 IOP_REQUEST_TYPE_SCSI_COMMAND, 127 IOP_REQUEST_TYPE_IOCTL_COMMAND, 128 IOP_REQUEST_TYPE_MAX 129 }; 130 131 enum hpt_iop_result_type { 132 IOP_RESULT_PENDING = 0, 133 IOP_RESULT_SUCCESS, 134 IOP_RESULT_FAIL, 135 IOP_RESULT_BUSY, 136 IOP_RESULT_RESET, 137 IOP_RESULT_INVALID_REQUEST, 138 IOP_RESULT_BAD_TARGET, 139 IOP_RESULT_CHECK_CONDITION, 140 }; 141 142 struct hpt_iop_request_get_config { 143 struct hpt_iop_request_header header; 144 __le32 interface_version; 145 __le32 firmware_version; 146 __le32 max_requests; 147 __le32 request_size; 148 __le32 max_sg_count; 149 __le32 data_transfer_length; 150 __le32 alignment_mask; 151 __le32 max_devices; 152 __le32 sdram_size; 153 }; 154 155 struct hpt_iop_request_set_config { 156 struct hpt_iop_request_header header; 157 __le32 iop_id; 158 __le16 vbus_id; 159 __le16 max_host_request_size; 160 __le32 reserve[6]; 161 }; 162 163 struct hpt_iopsg { 164 __le32 size; 165 __le32 eot; /* non-zero: end of table */ 166 __le64 pci_address; 167 }; 168 169 struct hpt_iop_request_block_command { 170 struct hpt_iop_request_header header; 171 u8 channel; 172 u8 target; 173 u8 lun; 174 u8 pad1; 175 __le16 command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */ 176 __le16 sectors; 177 __le64 lba; 178 struct hpt_iopsg sg_list[1]; 179 }; 180 181 #define IOP_BLOCK_COMMAND_READ 1 182 #define IOP_BLOCK_COMMAND_WRITE 2 183 #define IOP_BLOCK_COMMAND_VERIFY 3 184 #define IOP_BLOCK_COMMAND_FLUSH 4 185 #define IOP_BLOCK_COMMAND_SHUTDOWN 5 186 187 struct hpt_iop_request_scsi_command { 188 struct hpt_iop_request_header header; 189 u8 channel; 190 u8 target; 191 u8 lun; 192 u8 pad1; 193 u8 cdb[16]; 194 __le32 dataxfer_length; 195 struct hpt_iopsg sg_list[1]; 196 }; 197 198 struct hpt_iop_request_ioctl_command { 199 struct hpt_iop_request_header header; 200 __le32 ioctl_code; 201 __le32 inbuf_size; 202 __le32 outbuf_size; 203 __le32 bytes_returned; 204 u8 buf[1]; 205 /* out data should be put at buf[(inbuf_size+3)&~3] */ 206 }; 207 208 #define HPTIOP_MAX_REQUESTS 256u 209 210 struct hptiop_request { 211 struct hptiop_request *next; 212 void *req_virt; 213 u32 req_shifted_phy; 214 struct scsi_cmnd *scp; 215 int index; 216 }; 217 218 struct hpt_scsi_pointer { 219 int mapped; 220 int sgcnt; 221 dma_addr_t dma_handle; 222 }; 223 224 #define HPT_SCP(scp) ((struct hpt_scsi_pointer *)&(scp)->SCp) 225 226 struct hptiop_hba { 227 struct hptiop_adapter_ops *ops; 228 union { 229 struct { 230 struct hpt_iopmu_itl __iomem *iop; 231 void __iomem *plx; 232 } itl; 233 struct { 234 struct hpt_iopmv_regs *regs; 235 struct hpt_iopmu_mv __iomem *mu; 236 void *internal_req; 237 dma_addr_t internal_req_phy; 238 } mv; 239 } u; 240 241 struct Scsi_Host *host; 242 struct pci_dev *pcidev; 243 244 /* IOP config info */ 245 u32 interface_version; 246 u32 firmware_version; 247 u32 sdram_size; 248 u32 max_devices; 249 u32 max_requests; 250 u32 max_request_size; 251 u32 max_sg_descriptors; 252 253 u32 req_size; /* host-allocated request buffer size */ 254 255 u32 iopintf_v2: 1; 256 u32 initialized: 1; 257 u32 msg_done: 1; 258 259 struct hptiop_request * req_list; 260 struct hptiop_request reqs[HPTIOP_MAX_REQUESTS]; 261 262 /* used to free allocated dma area */ 263 void *dma_coherent; 264 dma_addr_t dma_coherent_handle; 265 266 atomic_t reset_count; 267 atomic_t resetting; 268 269 wait_queue_head_t reset_wq; 270 wait_queue_head_t ioctl_wq; 271 }; 272 273 struct hpt_ioctl_k { 274 struct hptiop_hba * hba; 275 u32 ioctl_code; 276 u32 inbuf_size; 277 u32 outbuf_size; 278 void *inbuf; 279 void *outbuf; 280 u32 *bytes_returned; 281 void (*done)(struct hpt_ioctl_k *); 282 int result; /* HPT_IOCTL_RESULT_ */ 283 }; 284 285 struct hptiop_adapter_ops { 286 int (*iop_wait_ready)(struct hptiop_hba *hba, u32 millisec); 287 int (*internal_memalloc)(struct hptiop_hba *hba); 288 int (*internal_memfree)(struct hptiop_hba *hba); 289 int (*map_pci_bar)(struct hptiop_hba *hba); 290 void (*unmap_pci_bar)(struct hptiop_hba *hba); 291 void (*enable_intr)(struct hptiop_hba *hba); 292 void (*disable_intr)(struct hptiop_hba *hba); 293 int (*get_config)(struct hptiop_hba *hba, 294 struct hpt_iop_request_get_config *config); 295 int (*set_config)(struct hptiop_hba *hba, 296 struct hpt_iop_request_set_config *config); 297 int (*iop_intr)(struct hptiop_hba *hba); 298 void (*post_msg)(struct hptiop_hba *hba, u32 msg); 299 void (*post_req)(struct hptiop_hba *hba, struct hptiop_request *_req); 300 int hw_dma_bit_mask; 301 }; 302 303 #define HPT_IOCTL_RESULT_OK 0 304 #define HPT_IOCTL_RESULT_FAILED (-1) 305 306 #if 0 307 #define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0) 308 #else 309 #define dprintk(fmt, args...) 310 #endif 311 312 #endif 313