1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_CMD_H 22 #define HPSA_CMD_H 23 24 /* general boundary defintions */ 25 #define SENSEINFOBYTES 32 /* may vary between hbas */ 26 #define MAXSGENTRIES 31 27 #define MAXREPLYQS 256 28 29 /* Command Status value */ 30 #define CMD_SUCCESS 0x0000 31 #define CMD_TARGET_STATUS 0x0001 32 #define CMD_DATA_UNDERRUN 0x0002 33 #define CMD_DATA_OVERRUN 0x0003 34 #define CMD_INVALID 0x0004 35 #define CMD_PROTOCOL_ERR 0x0005 36 #define CMD_HARDWARE_ERR 0x0006 37 #define CMD_CONNECTION_LOST 0x0007 38 #define CMD_ABORTED 0x0008 39 #define CMD_ABORT_FAILED 0x0009 40 #define CMD_UNSOLICITED_ABORT 0x000A 41 #define CMD_TIMEOUT 0x000B 42 #define CMD_UNABORTABLE 0x000C 43 44 /* Unit Attentions ASC's as defined for the MSA2012sa */ 45 #define POWER_OR_RESET 0x29 46 #define STATE_CHANGED 0x2a 47 #define UNIT_ATTENTION_CLEARED 0x2f 48 #define LUN_FAILED 0x3e 49 #define REPORT_LUNS_CHANGED 0x3f 50 51 /* Unit Attentions ASCQ's as defined for the MSA2012sa */ 52 53 /* These ASCQ's defined for ASC = POWER_OR_RESET */ 54 #define POWER_ON_RESET 0x00 55 #define POWER_ON_REBOOT 0x01 56 #define SCSI_BUS_RESET 0x02 57 #define MSA_TARGET_RESET 0x03 58 #define CONTROLLER_FAILOVER 0x04 59 #define TRANSCEIVER_SE 0x05 60 #define TRANSCEIVER_LVD 0x06 61 62 /* These ASCQ's defined for ASC = STATE_CHANGED */ 63 #define RESERVATION_PREEMPTED 0x03 64 #define ASYM_ACCESS_CHANGED 0x06 65 #define LUN_CAPACITY_CHANGED 0x09 66 67 /* transfer direction */ 68 #define XFER_NONE 0x00 69 #define XFER_WRITE 0x01 70 #define XFER_READ 0x02 71 #define XFER_RSVD 0x03 72 73 /* task attribute */ 74 #define ATTR_UNTAGGED 0x00 75 #define ATTR_SIMPLE 0x04 76 #define ATTR_HEADOFQUEUE 0x05 77 #define ATTR_ORDERED 0x06 78 #define ATTR_ACA 0x07 79 80 /* cdb type */ 81 #define TYPE_CMD 0x00 82 #define TYPE_MSG 0x01 83 84 /* config space register offsets */ 85 #define CFG_VENDORID 0x00 86 #define CFG_DEVICEID 0x02 87 #define CFG_I2OBAR 0x10 88 #define CFG_MEM1BAR 0x14 89 90 /* i2o space register offsets */ 91 #define I2O_IBDB_SET 0x20 92 #define I2O_IBDB_CLEAR 0x70 93 #define I2O_INT_STATUS 0x30 94 #define I2O_INT_MASK 0x34 95 #define I2O_IBPOST_Q 0x40 96 #define I2O_OBPOST_Q 0x44 97 #define I2O_DMA1_CFG 0x214 98 99 /* Configuration Table */ 100 #define CFGTBL_ChangeReq 0x00000001l 101 #define CFGTBL_AccCmds 0x00000001l 102 103 #define CFGTBL_Trans_Simple 0x00000002l 104 #define CFGTBL_Trans_Performant 0x00000004l 105 106 #define CFGTBL_BusType_Ultra2 0x00000001l 107 #define CFGTBL_BusType_Ultra3 0x00000002l 108 #define CFGTBL_BusType_Fibre1G 0x00000100l 109 #define CFGTBL_BusType_Fibre2G 0x00000200l 110 struct vals32 { 111 u32 lower; 112 u32 upper; 113 }; 114 115 union u64bit { 116 struct vals32 val32; 117 u64 val; 118 }; 119 120 /* FIXME this is a per controller value (barf!) */ 121 #define HPSA_MAX_TARGETS_PER_CTLR 16 122 #define HPSA_MAX_LUN 256 123 #define HPSA_MAX_PHYS_LUN 1024 124 125 /* SCSI-3 Commands */ 126 #pragma pack(1) 127 128 #define HPSA_INQUIRY 0x12 129 struct InquiryData { 130 u8 data_byte[36]; 131 }; 132 133 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 134 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 135 struct ReportLUNdata { 136 u8 LUNListLength[4]; 137 u32 reserved; 138 u8 LUN[HPSA_MAX_LUN][8]; 139 }; 140 141 struct ReportExtendedLUNdata { 142 u8 LUNListLength[4]; 143 u8 extended_response_flag; 144 u8 reserved[3]; 145 u8 LUN[HPSA_MAX_LUN][24]; 146 }; 147 148 struct SenseSubsystem_info { 149 u8 reserved[36]; 150 u8 portname[8]; 151 u8 reserved1[1108]; 152 }; 153 154 #define HPSA_READ_CAPACITY 0x25 /* Read Capacity */ 155 struct ReadCapdata { 156 u8 total_size[4]; /* Total size in blocks */ 157 u8 block_size[4]; /* Size of blocks in bytes */ 158 }; 159 160 #if 0 161 /* 12 byte commands not implemented in firmware yet. */ 162 #define HPSA_READ 0xa8 163 #define HPSA_WRITE 0xaa 164 #endif 165 166 #define HPSA_READ 0x28 /* Read(10) */ 167 #define HPSA_WRITE 0x2a /* Write(10) */ 168 169 /* BMIC commands */ 170 #define BMIC_READ 0x26 171 #define BMIC_WRITE 0x27 172 #define BMIC_CACHE_FLUSH 0xc2 173 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ 174 175 /* Command List Structure */ 176 union SCSI3Addr { 177 struct { 178 u8 Dev; 179 u8 Bus:6; 180 u8 Mode:2; /* b00 */ 181 } PeripDev; 182 struct { 183 u8 DevLSB; 184 u8 DevMSB:6; 185 u8 Mode:2; /* b01 */ 186 } LogDev; 187 struct { 188 u8 Dev:5; 189 u8 Bus:3; 190 u8 Targ:6; 191 u8 Mode:2; /* b10 */ 192 } LogUnit; 193 }; 194 195 struct PhysDevAddr { 196 u32 TargetId:24; 197 u32 Bus:6; 198 u32 Mode:2; 199 /* 2 level target device addr */ 200 union SCSI3Addr Target[2]; 201 }; 202 203 struct LogDevAddr { 204 u32 VolId:30; 205 u32 Mode:2; 206 u8 reserved[4]; 207 }; 208 209 union LUNAddr { 210 u8 LunAddrBytes[8]; 211 union SCSI3Addr SCSI3Lun[4]; 212 struct PhysDevAddr PhysDev; 213 struct LogDevAddr LogDev; 214 }; 215 216 struct CommandListHeader { 217 u8 ReplyQueue; 218 u8 SGList; 219 u16 SGTotal; 220 struct vals32 Tag; 221 union LUNAddr LUN; 222 }; 223 224 struct RequestBlock { 225 u8 CDBLen; 226 struct { 227 u8 Type:3; 228 u8 Attribute:3; 229 u8 Direction:2; 230 } Type; 231 u16 Timeout; 232 u8 CDB[16]; 233 }; 234 235 struct ErrDescriptor { 236 struct vals32 Addr; 237 u32 Len; 238 }; 239 240 struct SGDescriptor { 241 struct vals32 Addr; 242 u32 Len; 243 u32 Ext; 244 }; 245 246 union MoreErrInfo { 247 struct { 248 u8 Reserved[3]; 249 u8 Type; 250 u32 ErrorInfo; 251 } Common_Info; 252 struct { 253 u8 Reserved[2]; 254 u8 offense_size; /* size of offending entry */ 255 u8 offense_num; /* byte # of offense 0-base */ 256 u32 offense_value; 257 } Invalid_Cmd; 258 }; 259 struct ErrorInfo { 260 u8 ScsiStatus; 261 u8 SenseLen; 262 u16 CommandStatus; 263 u32 ResidualCnt; 264 union MoreErrInfo MoreErrInfo; 265 u8 SenseInfo[SENSEINFOBYTES]; 266 }; 267 /* Command types */ 268 #define CMD_IOCTL_PEND 0x01 269 #define CMD_SCSI 0x03 270 271 /* This structure needs to be divisible by 32 for new 272 * indexing method and performant mode. 273 */ 274 #define PAD32 32 275 #define PAD64DIFF 0 276 #define USEEXTRA ((sizeof(void *) - 4)/4) 277 #define PADSIZE (PAD32 + PAD64DIFF * USEEXTRA) 278 279 #define DIRECT_LOOKUP_SHIFT 5 280 #define DIRECT_LOOKUP_BIT 0x10 281 282 #define HPSA_ERROR_BIT 0x02 283 struct ctlr_info; /* defined in hpsa.h */ 284 /* The size of this structure needs to be divisible by 32 285 * on all architectures because low 5 bits of the addresses 286 * are used as follows: 287 * 288 * bit 0: to device, used to indicate "performant mode" command 289 * from device, indidcates error status. 290 * bit 1-3: to device, indicates block fetch table entry for 291 * reducing DMA in fetching commands from host memory. 292 * bit 4: used to indicate whether tag is "direct lookup" (index), 293 * or a bus address. 294 */ 295 296 struct CommandList { 297 struct CommandListHeader Header; 298 struct RequestBlock Request; 299 struct ErrDescriptor ErrDesc; 300 struct SGDescriptor SG[MAXSGENTRIES]; 301 /* information associated with the command */ 302 u32 busaddr; /* physical addr of this record */ 303 struct ErrorInfo *err_info; /* pointer to the allocated mem */ 304 struct ctlr_info *h; 305 int cmd_type; 306 long cmdindex; 307 struct hlist_node list; 308 struct CommandList *prev; 309 struct CommandList *next; 310 struct request *rq; 311 struct completion *waiting; 312 int retry_count; 313 void *scsi_cmd; 314 315 /* on 64 bit architectures, to get this to be 32-byte-aligned 316 * it so happens we need no padding, on 32 bit systems, 317 * we need 8 bytes of padding. This does that. 318 */ 319 #define COMMANDLIST_PAD ((8 - sizeof(long))/4 * 8) 320 u8 pad[COMMANDLIST_PAD]; 321 322 }; 323 324 /* Configuration Table Structure */ 325 struct HostWrite { 326 u32 TransportRequest; 327 u32 Reserved; 328 u32 CoalIntDelay; 329 u32 CoalIntCount; 330 }; 331 332 #define SIMPLE_MODE 0x02 333 #define PERFORMANT_MODE 0x04 334 #define MEMQ_MODE 0x08 335 336 struct CfgTable { 337 u8 Signature[4]; 338 u32 SpecValence; 339 u32 TransportSupport; 340 u32 TransportActive; 341 struct HostWrite HostWrite; 342 u32 CmdsOutMax; 343 u32 BusTypes; 344 u32 TransMethodOffset; 345 u8 ServerName[16]; 346 u32 HeartBeat; 347 u32 SCSI_Prefetch; 348 u32 MaxScatterGatherElements; 349 u32 MaxLogicalUnits; 350 u32 MaxPhysicalDevices; 351 u32 MaxPhysicalDrivesPerLogicalUnit; 352 u32 MaxPerformantModeCommands; 353 }; 354 355 #define NUM_BLOCKFETCH_ENTRIES 8 356 struct TransTable_struct { 357 u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; 358 u32 RepQSize; 359 u32 RepQCount; 360 u32 RepQCtrAddrLow32; 361 u32 RepQCtrAddrHigh32; 362 u32 RepQAddr0Low32; 363 u32 RepQAddr0High32; 364 }; 365 366 struct hpsa_pci_info { 367 unsigned char bus; 368 unsigned char dev_fn; 369 unsigned short domain; 370 u32 board_id; 371 }; 372 373 #pragma pack() 374 #endif /* HPSA_CMD_H */ 375