1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2016 Microsemi Corporation 4 * Copyright 2014-2015 PMC-Sierra, Inc. 5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14 * NON INFRINGEMENT. See the GNU General Public License for more details. 15 * 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17 * 18 */ 19 #ifndef HPSA_CMD_H 20 #define HPSA_CMD_H 21 22 /* general boundary defintions */ 23 #define SENSEINFOBYTES 32 /* may vary between hbas */ 24 #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ 25 #define HPSA_SG_CHAIN 0x80000000 26 #define HPSA_SG_LAST 0x40000000 27 #define MAXREPLYQS 256 28 29 /* Command Status value */ 30 #define CMD_SUCCESS 0x0000 31 #define CMD_TARGET_STATUS 0x0001 32 #define CMD_DATA_UNDERRUN 0x0002 33 #define CMD_DATA_OVERRUN 0x0003 34 #define CMD_INVALID 0x0004 35 #define CMD_PROTOCOL_ERR 0x0005 36 #define CMD_HARDWARE_ERR 0x0006 37 #define CMD_CONNECTION_LOST 0x0007 38 #define CMD_ABORTED 0x0008 39 #define CMD_ABORT_FAILED 0x0009 40 #define CMD_UNSOLICITED_ABORT 0x000A 41 #define CMD_TIMEOUT 0x000B 42 #define CMD_UNABORTABLE 0x000C 43 #define CMD_TMF_STATUS 0x000D 44 #define CMD_IOACCEL_DISABLED 0x000E 45 #define CMD_CTLR_LOCKUP 0xffff 46 /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec 47 * it is a value defined by the driver that commands can be marked 48 * with when a controller lockup has been detected by the driver 49 */ 50 51 /* TMF function status values */ 52 #define CISS_TMF_COMPLETE 0x00 53 #define CISS_TMF_INVALID_FRAME 0x02 54 #define CISS_TMF_NOT_SUPPORTED 0x04 55 #define CISS_TMF_FAILED 0x05 56 #define CISS_TMF_SUCCESS 0x08 57 #define CISS_TMF_WRONG_LUN 0x09 58 #define CISS_TMF_OVERLAPPED_TAG 0x0a 59 60 /* Unit Attentions ASC's as defined for the MSA2012sa */ 61 #define POWER_OR_RESET 0x29 62 #define STATE_CHANGED 0x2a 63 #define UNIT_ATTENTION_CLEARED 0x2f 64 #define LUN_FAILED 0x3e 65 #define REPORT_LUNS_CHANGED 0x3f 66 67 /* Unit Attentions ASCQ's as defined for the MSA2012sa */ 68 69 /* These ASCQ's defined for ASC = POWER_OR_RESET */ 70 #define POWER_ON_RESET 0x00 71 #define POWER_ON_REBOOT 0x01 72 #define SCSI_BUS_RESET 0x02 73 #define MSA_TARGET_RESET 0x03 74 #define CONTROLLER_FAILOVER 0x04 75 #define TRANSCEIVER_SE 0x05 76 #define TRANSCEIVER_LVD 0x06 77 78 /* These ASCQ's defined for ASC = STATE_CHANGED */ 79 #define RESERVATION_PREEMPTED 0x03 80 #define ASYM_ACCESS_CHANGED 0x06 81 #define LUN_CAPACITY_CHANGED 0x09 82 83 /* transfer direction */ 84 #define XFER_NONE 0x00 85 #define XFER_WRITE 0x01 86 #define XFER_READ 0x02 87 #define XFER_RSVD 0x03 88 89 /* task attribute */ 90 #define ATTR_UNTAGGED 0x00 91 #define ATTR_SIMPLE 0x04 92 #define ATTR_HEADOFQUEUE 0x05 93 #define ATTR_ORDERED 0x06 94 #define ATTR_ACA 0x07 95 96 /* cdb type */ 97 #define TYPE_CMD 0x00 98 #define TYPE_MSG 0x01 99 #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */ 100 101 /* Message Types */ 102 #define HPSA_TASK_MANAGEMENT 0x00 103 #define HPSA_RESET 0x01 104 #define HPSA_SCAN 0x02 105 #define HPSA_NOOP 0x03 106 107 #define HPSA_CTLR_RESET_TYPE 0x00 108 #define HPSA_BUS_RESET_TYPE 0x01 109 #define HPSA_TARGET_RESET_TYPE 0x03 110 #define HPSA_LUN_RESET_TYPE 0x04 111 #define HPSA_NEXUS_RESET_TYPE 0x05 112 113 /* Task Management Functions */ 114 #define HPSA_TMF_ABORT_TASK 0x00 115 #define HPSA_TMF_ABORT_TASK_SET 0x01 116 #define HPSA_TMF_CLEAR_ACA 0x02 117 #define HPSA_TMF_CLEAR_TASK_SET 0x03 118 #define HPSA_TMF_QUERY_TASK 0x04 119 #define HPSA_TMF_QUERY_TASK_SET 0x05 120 #define HPSA_TMF_QUERY_ASYNCEVENT 0x06 121 122 123 124 /* config space register offsets */ 125 #define CFG_VENDORID 0x00 126 #define CFG_DEVICEID 0x02 127 #define CFG_I2OBAR 0x10 128 #define CFG_MEM1BAR 0x14 129 130 /* i2o space register offsets */ 131 #define I2O_IBDB_SET 0x20 132 #define I2O_IBDB_CLEAR 0x70 133 #define I2O_INT_STATUS 0x30 134 #define I2O_INT_MASK 0x34 135 #define I2O_IBPOST_Q 0x40 136 #define I2O_OBPOST_Q 0x44 137 #define I2O_DMA1_CFG 0x214 138 139 /* Configuration Table */ 140 #define CFGTBL_ChangeReq 0x00000001l 141 #define CFGTBL_AccCmds 0x00000001l 142 #define DOORBELL_CTLR_RESET 0x00000004l 143 #define DOORBELL_CTLR_RESET2 0x00000020l 144 #define DOORBELL_CLEAR_EVENTS 0x00000040l 145 146 #define CFGTBL_Trans_Simple 0x00000002l 147 #define CFGTBL_Trans_Performant 0x00000004l 148 #define CFGTBL_Trans_io_accel1 0x00000080l 149 #define CFGTBL_Trans_io_accel2 0x00000100l 150 #define CFGTBL_Trans_use_short_tags 0x20000000l 151 #define CFGTBL_Trans_enable_directed_msix (1 << 30) 152 153 #define CFGTBL_BusType_Ultra2 0x00000001l 154 #define CFGTBL_BusType_Ultra3 0x00000002l 155 #define CFGTBL_BusType_Fibre1G 0x00000100l 156 #define CFGTBL_BusType_Fibre2G 0x00000200l 157 158 /* VPD Inquiry types */ 159 #define HPSA_VPD_SUPPORTED_PAGES 0x00 160 #define HPSA_VPD_LV_DEVICE_ID 0x83 161 #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1 162 #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2 163 #define HPSA_VPD_LV_STATUS 0xC3 164 #define HPSA_VPD_HEADER_SZ 4 165 166 /* Logical volume states */ 167 #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff 168 #define HPSA_LV_OK 0x0 169 #define HPSA_LV_NOT_AVAILABLE 0x0b 170 #define HPSA_LV_UNDERGOING_ERASE 0x0F 171 #define HPSA_LV_UNDERGOING_RPI 0x12 172 #define HPSA_LV_PENDING_RPI 0x13 173 #define HPSA_LV_ENCRYPTED_NO_KEY 0x14 174 #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 175 #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16 176 #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 177 #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 178 #define HPSA_LV_PENDING_ENCRYPTION 0x19 179 #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A 180 181 struct vals32 { 182 u32 lower; 183 u32 upper; 184 }; 185 186 union u64bit { 187 struct vals32 val32; 188 u64 val; 189 }; 190 191 /* FIXME this is a per controller value (barf!) */ 192 #define HPSA_MAX_LUN 1024 193 #define HPSA_MAX_PHYS_LUN 1024 194 #define MAX_EXT_TARGETS 32 195 #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ 196 MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ 197 198 /* SCSI-3 Commands */ 199 #pragma pack(1) 200 201 #define HPSA_INQUIRY 0x12 202 struct InquiryData { 203 u8 data_byte[36]; 204 }; 205 206 #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ 207 #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ 208 #define HPSA_REPORT_PHYS_EXTENDED 0x02 209 #define HPSA_CISS_READ 0xc0 /* CISS Read */ 210 #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */ 211 212 #define RAID_MAP_MAX_ENTRIES 256 213 214 struct raid_map_disk_data { 215 u32 ioaccel_handle; /**< Handle to access this disk via the 216 * I/O accelerator */ 217 u8 xor_mult[2]; /**< XOR multipliers for this position, 218 * valid for data disks only */ 219 u8 reserved[2]; 220 }; 221 222 struct raid_map_data { 223 __le32 structure_size; /* Size of entire structure in bytes */ 224 __le32 volume_blk_size; /* bytes / block in the volume */ 225 __le64 volume_blk_cnt; /* logical blocks on the volume */ 226 u8 phys_blk_shift; /* Shift factor to convert between 227 * units of logical blocks and physical 228 * disk blocks */ 229 u8 parity_rotation_shift; /* Shift factor to convert between units 230 * of logical stripes and physical 231 * stripes */ 232 __le16 strip_size; /* blocks used on each disk / stripe */ 233 __le64 disk_starting_blk; /* First disk block used in volume */ 234 __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ 235 __le16 data_disks_per_row; /* data disk entries / row in the map */ 236 __le16 metadata_disks_per_row;/* mirror/parity disk entries / row 237 * in the map */ 238 __le16 row_cnt; /* rows in each layout map */ 239 __le16 layout_map_count; /* layout maps (1 map per mirror/parity 240 * group) */ 241 __le16 flags; /* Bit 0 set if encryption enabled */ 242 #define RAID_MAP_FLAG_ENCRYPT_ON 0x01 243 __le16 dekindex; /* Data encryption key index. */ 244 u8 reserved[16]; 245 struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES]; 246 }; 247 248 struct ReportLUNdata { 249 u8 LUNListLength[4]; 250 u8 extended_response_flag; 251 u8 reserved[3]; 252 u8 LUN[HPSA_MAX_LUN][8]; 253 }; 254 255 struct ext_report_lun_entry { 256 u8 lunid[8]; 257 #define MASKED_DEVICE(x) ((x)[3] & 0xC0) 258 #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F) 259 #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) 260 #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \ 261 GET_BMIC_LEVEL_TWO_TARGET((lunid))) 262 u8 wwid[8]; 263 u8 device_type; 264 u8 device_flags; 265 u8 lun_count; /* multi-lun device, how many luns */ 266 u8 redundant_paths; 267 u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */ 268 }; 269 270 struct ReportExtendedLUNdata { 271 u8 LUNListLength[4]; 272 u8 extended_response_flag; 273 u8 reserved[3]; 274 struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN]; 275 }; 276 277 struct SenseSubsystem_info { 278 u8 reserved[36]; 279 u8 portname[8]; 280 u8 reserved1[1108]; 281 }; 282 283 /* BMIC commands */ 284 #define BMIC_READ 0x26 285 #define BMIC_WRITE 0x27 286 #define BMIC_CACHE_FLUSH 0xc2 287 #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ 288 #define BMIC_FLASH_FIRMWARE 0xF7 289 #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 290 #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 291 #define BMIC_IDENTIFY_CONTROLLER 0x11 292 #define BMIC_SET_DIAG_OPTIONS 0xF4 293 #define BMIC_SENSE_DIAG_OPTIONS 0xF5 294 #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000 295 #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 296 #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65 297 298 /* Command List Structure */ 299 union SCSI3Addr { 300 struct { 301 u8 Dev; 302 u8 Bus:6; 303 u8 Mode:2; /* b00 */ 304 } PeripDev; 305 struct { 306 u8 DevLSB; 307 u8 DevMSB:6; 308 u8 Mode:2; /* b01 */ 309 } LogDev; 310 struct { 311 u8 Dev:5; 312 u8 Bus:3; 313 u8 Targ:6; 314 u8 Mode:2; /* b10 */ 315 } LogUnit; 316 }; 317 318 struct PhysDevAddr { 319 u32 TargetId:24; 320 u32 Bus:6; 321 u32 Mode:2; 322 /* 2 level target device addr */ 323 union SCSI3Addr Target[2]; 324 }; 325 326 struct LogDevAddr { 327 u32 VolId:30; 328 u32 Mode:2; 329 u8 reserved[4]; 330 }; 331 332 union LUNAddr { 333 u8 LunAddrBytes[8]; 334 union SCSI3Addr SCSI3Lun[4]; 335 struct PhysDevAddr PhysDev; 336 struct LogDevAddr LogDev; 337 }; 338 339 struct CommandListHeader { 340 u8 ReplyQueue; 341 u8 SGList; 342 __le16 SGTotal; 343 __le64 tag; 344 union LUNAddr LUN; 345 }; 346 347 struct RequestBlock { 348 u8 CDBLen; 349 /* 350 * type_attr_dir: 351 * type: low 3 bits 352 * attr: middle 3 bits 353 * dir: high 2 bits 354 */ 355 u8 type_attr_dir; 356 #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\ 357 (((a) & 0x07) << 3) |\ 358 ((t) & 0x07)) 359 #define GET_TYPE(tad) ((tad) & 0x07) 360 #define GET_ATTR(tad) (((tad) >> 3) & 0x07) 361 #define GET_DIR(tad) (((tad) >> 6) & 0x03) 362 u16 Timeout; 363 u8 CDB[16]; 364 }; 365 366 struct ErrDescriptor { 367 __le64 Addr; 368 __le32 Len; 369 }; 370 371 struct SGDescriptor { 372 __le64 Addr; 373 __le32 Len; 374 __le32 Ext; 375 }; 376 377 union MoreErrInfo { 378 struct { 379 u8 Reserved[3]; 380 u8 Type; 381 u32 ErrorInfo; 382 } Common_Info; 383 struct { 384 u8 Reserved[2]; 385 u8 offense_size; /* size of offending entry */ 386 u8 offense_num; /* byte # of offense 0-base */ 387 u32 offense_value; 388 } Invalid_Cmd; 389 }; 390 struct ErrorInfo { 391 u8 ScsiStatus; 392 u8 SenseLen; 393 u16 CommandStatus; 394 u32 ResidualCnt; 395 union MoreErrInfo MoreErrInfo; 396 u8 SenseInfo[SENSEINFOBYTES]; 397 }; 398 /* Command types */ 399 #define CMD_IOCTL_PEND 0x01 400 #define CMD_SCSI 0x03 401 #define CMD_IOACCEL1 0x04 402 #define CMD_IOACCEL2 0x05 403 #define IOACCEL2_TMF 0x06 404 405 #define DIRECT_LOOKUP_SHIFT 4 406 #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) 407 408 #define HPSA_ERROR_BIT 0x02 409 struct ctlr_info; /* defined in hpsa.h */ 410 /* The size of this structure needs to be divisible by 128 411 * on all architectures. The low 4 bits of the addresses 412 * are used as follows: 413 * 414 * bit 0: to device, used to indicate "performant mode" command 415 * from device, indidcates error status. 416 * bit 1-3: to device, indicates block fetch table entry for 417 * reducing DMA in fetching commands from host memory. 418 */ 419 420 #define COMMANDLIST_ALIGNMENT 128 421 struct CommandList { 422 struct CommandListHeader Header; 423 struct RequestBlock Request; 424 struct ErrDescriptor ErrDesc; 425 struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; 426 /* information associated with the command */ 427 u32 busaddr; /* physical addr of this record */ 428 struct ErrorInfo *err_info; /* pointer to the allocated mem */ 429 struct ctlr_info *h; 430 int cmd_type; 431 long cmdindex; 432 struct completion *waiting; 433 struct scsi_cmnd *scsi_cmd; 434 struct work_struct work; 435 436 /* 437 * For commands using either of the two "ioaccel" paths to 438 * bypass the RAID stack and go directly to the physical disk 439 * phys_disk is a pointer to the hpsa_scsi_dev_t to which the 440 * i/o is destined. We need to store that here because the command 441 * may potentially encounter TASK SET FULL and need to be resubmitted 442 * For "normal" i/o's not using the "ioaccel" paths, phys_disk is 443 * not used. 444 */ 445 struct hpsa_scsi_dev_t *phys_disk; 446 447 int abort_pending; 448 struct hpsa_scsi_dev_t *reset_pending; 449 atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */ 450 } __aligned(COMMANDLIST_ALIGNMENT); 451 452 /* Max S/G elements in I/O accelerator command */ 453 #define IOACCEL1_MAXSGENTRIES 24 454 #define IOACCEL2_MAXSGENTRIES 28 455 456 /* 457 * Structure for I/O accelerator (mode 1) commands. 458 * Note that this structure must be 128-byte aligned in size. 459 */ 460 #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 461 struct io_accel1_cmd { 462 __le16 dev_handle; /* 0x00 - 0x01 */ 463 u8 reserved1; /* 0x02 */ 464 u8 function; /* 0x03 */ 465 u8 reserved2[8]; /* 0x04 - 0x0B */ 466 u32 err_info; /* 0x0C - 0x0F */ 467 u8 reserved3[2]; /* 0x10 - 0x11 */ 468 u8 err_info_len; /* 0x12 */ 469 u8 reserved4; /* 0x13 */ 470 u8 sgl_offset; /* 0x14 */ 471 u8 reserved5[7]; /* 0x15 - 0x1B */ 472 __le32 transfer_len; /* 0x1C - 0x1F */ 473 u8 reserved6[4]; /* 0x20 - 0x23 */ 474 __le16 io_flags; /* 0x24 - 0x25 */ 475 u8 reserved7[14]; /* 0x26 - 0x33 */ 476 u8 LUN[8]; /* 0x34 - 0x3B */ 477 __le32 control; /* 0x3C - 0x3F */ 478 u8 CDB[16]; /* 0x40 - 0x4F */ 479 u8 reserved8[16]; /* 0x50 - 0x5F */ 480 __le16 host_context_flags; /* 0x60 - 0x61 */ 481 __le16 timeout_sec; /* 0x62 - 0x63 */ 482 u8 ReplyQueue; /* 0x64 */ 483 u8 reserved9[3]; /* 0x65 - 0x67 */ 484 __le64 tag; /* 0x68 - 0x6F */ 485 __le64 host_addr; /* 0x70 - 0x77 */ 486 u8 CISS_LUN[8]; /* 0x78 - 0x7F */ 487 struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; 488 } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); 489 490 #define IOACCEL1_FUNCTION_SCSIIO 0x00 491 #define IOACCEL1_SGLOFFSET 32 492 493 #define IOACCEL1_IOFLAGS_IO_REQ 0x4000 494 #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F 495 #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16 496 497 #define IOACCEL1_CONTROL_NODATAXFER 0x00000000 498 #define IOACCEL1_CONTROL_DATA_OUT 0x01000000 499 #define IOACCEL1_CONTROL_DATA_IN 0x02000000 500 #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800 501 #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11 502 #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000 503 #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100 504 #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200 505 #define IOACCEL1_CONTROL_ACA 0x00000400 506 507 #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013 508 509 #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060 510 511 struct ioaccel2_sg_element { 512 __le64 address; 513 __le32 length; 514 u8 reserved[3]; 515 u8 chain_indicator; 516 #define IOACCEL2_CHAIN 0x80 517 }; 518 519 /* 520 * SCSI Response Format structure for IO Accelerator Mode 2 521 */ 522 struct io_accel2_scsi_response { 523 u8 IU_type; 524 #define IOACCEL2_IU_TYPE_SRF 0x60 525 u8 reserved1[3]; 526 u8 req_id[4]; /* request identifier */ 527 u8 reserved2[4]; 528 u8 serv_response; /* service response */ 529 #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000 530 #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001 531 #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002 532 #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003 533 #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004 534 #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005 535 u8 status; /* status */ 536 #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00 537 #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02 538 #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08 539 #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18 540 #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28 541 #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40 542 #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E 543 #define IOACCEL2_STATUS_SR_IO_ERROR 0x01 544 #define IOACCEL2_STATUS_SR_IO_ABORTED 0x02 545 #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03 546 #define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04 547 #define IOACCEL2_STATUS_SR_UNDERRUN 0x51 548 #define IOACCEL2_STATUS_SR_OVERRUN 0x75 549 u8 data_present; /* low 2 bits */ 550 #define IOACCEL2_NO_DATAPRESENT 0x000 551 #define IOACCEL2_RESPONSE_DATAPRESENT 0x001 552 #define IOACCEL2_SENSE_DATA_PRESENT 0x002 553 #define IOACCEL2_RESERVED 0x003 554 u8 sense_data_len; /* sense/response data length */ 555 u8 resid_cnt[4]; /* residual count */ 556 u8 sense_data_buff[32]; /* sense/response data buffer */ 557 }; 558 559 /* 560 * Structure for I/O accelerator (mode 2 or m2) commands. 561 * Note that this structure must be 128-byte aligned in size. 562 */ 563 #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 564 struct io_accel2_cmd { 565 u8 IU_type; /* IU Type */ 566 u8 direction; /* direction, memtype, and encryption */ 567 #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */ 568 #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */ 569 /* 0b=PCIe, 1b=DDR */ 570 #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */ 571 /* 0=off, 1=on */ 572 u8 reply_queue; /* Reply Queue ID */ 573 u8 reserved1; /* Reserved */ 574 __le32 scsi_nexus; /* Device Handle */ 575 __le32 Tag; /* cciss tag, lower 4 bytes only */ 576 __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */ 577 u8 cdb[16]; /* SCSI Command Descriptor Block */ 578 u8 cciss_lun[8]; /* 8 byte SCSI address */ 579 __le32 data_len; /* Total bytes to transfer */ 580 u8 cmd_priority_task_attr; /* priority and task attrs */ 581 #define IOACCEL2_PRIORITY_MASK 0x78 582 #define IOACCEL2_ATTR_MASK 0x07 583 u8 sg_count; /* Number of sg elements */ 584 __le16 dekindex; /* Data encryption key index */ 585 __le64 err_ptr; /* Error Pointer */ 586 __le32 err_len; /* Error Length*/ 587 __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */ 588 struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; 589 struct io_accel2_scsi_response error_data; 590 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); 591 592 /* 593 * defines for Mode 2 command struct 594 * FIXME: this can't be all I need mfm 595 */ 596 #define IOACCEL2_IU_TYPE 0x40 597 #define IOACCEL2_IU_TMF_TYPE 0x41 598 #define IOACCEL2_DIR_NO_DATA 0x00 599 #define IOACCEL2_DIR_DATA_IN 0x01 600 #define IOACCEL2_DIR_DATA_OUT 0x02 601 #define IOACCEL2_TMF_ABORT 0x01 602 /* 603 * SCSI Task Management Request format for Accelerator Mode 2 604 */ 605 struct hpsa_tmf_struct { 606 u8 iu_type; /* Information Unit Type */ 607 u8 reply_queue; /* Reply Queue ID */ 608 u8 tmf; /* Task Management Function */ 609 u8 reserved1; /* byte 3 Reserved */ 610 __le32 it_nexus; /* SCSI I-T Nexus */ 611 u8 lun_id[8]; /* LUN ID for TMF request */ 612 __le64 tag; /* cciss tag associated w/ request */ 613 __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */ 614 __le64 error_ptr; /* Error Pointer */ 615 __le32 error_len; /* Error Length */ 616 } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); 617 618 /* Configuration Table Structure */ 619 struct HostWrite { 620 __le32 TransportRequest; 621 __le32 command_pool_addr_hi; 622 __le32 CoalIntDelay; 623 __le32 CoalIntCount; 624 }; 625 626 #define SIMPLE_MODE 0x02 627 #define PERFORMANT_MODE 0x04 628 #define MEMQ_MODE 0x08 629 #define IOACCEL_MODE_1 0x80 630 631 #define DRIVER_SUPPORT_UA_ENABLE 0x00000001 632 633 struct CfgTable { 634 u8 Signature[4]; 635 __le32 SpecValence; 636 __le32 TransportSupport; 637 __le32 TransportActive; 638 struct HostWrite HostWrite; 639 __le32 CmdsOutMax; 640 __le32 BusTypes; 641 __le32 TransMethodOffset; 642 u8 ServerName[16]; 643 __le32 HeartBeat; 644 __le32 driver_support; 645 #define ENABLE_SCSI_PREFETCH 0x100 646 #define ENABLE_UNIT_ATTN 0x01 647 __le32 MaxScatterGatherElements; 648 __le32 MaxLogicalUnits; 649 __le32 MaxPhysicalDevices; 650 __le32 MaxPhysicalDrivesPerLogicalUnit; 651 __le32 MaxPerformantModeCommands; 652 __le32 MaxBlockFetch; 653 __le32 PowerConservationSupport; 654 __le32 PowerConservationEnable; 655 __le32 TMFSupportFlags; 656 u8 TMFTagMask[8]; 657 u8 reserved[0x78 - 0x70]; 658 __le32 misc_fw_support; /* offset 0x78 */ 659 #define MISC_FW_DOORBELL_RESET 0x02 660 #define MISC_FW_DOORBELL_RESET2 0x010 661 #define MISC_FW_RAID_OFFLOAD_BASIC 0x020 662 #define MISC_FW_EVENT_NOTIFY 0x080 663 u8 driver_version[32]; 664 __le32 max_cached_write_size; 665 u8 driver_scratchpad[16]; 666 __le32 max_error_info_length; 667 __le32 io_accel_max_embedded_sg_count; 668 __le32 io_accel_request_size_offset; 669 __le32 event_notify; 670 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30) 671 #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31) 672 __le32 clear_event_notify; 673 }; 674 675 #define NUM_BLOCKFETCH_ENTRIES 8 676 struct TransTable_struct { 677 __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; 678 __le32 RepQSize; 679 __le32 RepQCount; 680 __le32 RepQCtrAddrLow32; 681 __le32 RepQCtrAddrHigh32; 682 #define MAX_REPLY_QUEUES 64 683 struct vals32 RepQAddr[MAX_REPLY_QUEUES]; 684 }; 685 686 struct hpsa_pci_info { 687 unsigned char bus; 688 unsigned char dev_fn; 689 unsigned short domain; 690 u32 board_id; 691 }; 692 693 struct bmic_identify_controller { 694 u8 configured_logical_drive_count; /* offset 0 */ 695 u8 pad1[153]; 696 __le16 extended_logical_unit_count; /* offset 154 */ 697 u8 pad2[136]; 698 u8 controller_mode; /* offset 292 */ 699 u8 pad3[32]; 700 }; 701 702 703 struct bmic_identify_physical_device { 704 u8 scsi_bus; /* SCSI Bus number on controller */ 705 u8 scsi_id; /* SCSI ID on this bus */ 706 __le16 block_size; /* sector size in bytes */ 707 __le32 total_blocks; /* number for sectors on drive */ 708 __le32 reserved_blocks; /* controller reserved (RIS) */ 709 u8 model[40]; /* Physical Drive Model */ 710 u8 serial_number[40]; /* Drive Serial Number */ 711 u8 firmware_revision[8]; /* drive firmware revision */ 712 u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ 713 u8 compaq_drive_stamp; /* 0 means drive not stamped */ 714 u8 last_failure_reason; 715 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01 716 #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02 717 #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03 718 #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04 719 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05 720 #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06 721 #define BMIC_LAST_FAILURE_TIMEOUT 0x07 722 #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08 723 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09 724 #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a 725 #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b 726 #define BMIC_LAST_FAILURE_NOT_READY 0x0c 727 #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d 728 #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e 729 #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f 730 #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10 731 #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11 732 #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12 733 #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13 734 #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14 735 #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15 736 #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16 737 #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17 738 #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18 739 #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19 740 #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a 741 #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b 742 #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c 743 #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d 744 #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e 745 #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f 746 #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20 747 #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21 748 #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22 749 #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23 750 #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24 751 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25 752 #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26 753 #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27 754 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28 755 #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29 756 #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a 757 #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b 758 759 #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37 760 #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38 761 #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40 762 #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41 763 #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42 764 #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80 765 #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81 766 #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82 767 #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83 768 769 u8 flags; 770 u8 more_flags; 771 u8 scsi_lun; /* SCSI LUN for phys drive */ 772 u8 yet_more_flags; 773 u8 even_more_flags; 774 __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */ 775 u8 phys_connector[2]; /* connector number on controller */ 776 u8 phys_box_on_bus; /* phys enclosure this drive resides */ 777 u8 phys_bay_in_box; /* phys drv bay this drive resides */ 778 __le32 rpm; /* Drive rotational speed in rpm */ 779 u8 device_type; /* type of drive */ 780 u8 sata_version; /* only valid when drive_type is SATA */ 781 __le64 big_total_block_count; 782 __le64 ris_starting_lba; 783 __le32 ris_size; 784 u8 wwid[20]; 785 u8 controller_phy_map[32]; 786 __le16 phy_count; 787 u8 phy_connected_dev_type[256]; 788 u8 phy_to_drive_bay_num[256]; 789 __le16 phy_to_attached_dev_index[256]; 790 u8 box_index; 791 u8 reserved; 792 __le16 extra_physical_drive_flags; 793 #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \ 794 (idphydrv->extra_physical_drive_flags & (1 << 10)) 795 u8 negotiated_link_rate[256]; 796 u8 phy_to_phy_map[256]; 797 u8 redundant_path_present_map; 798 u8 redundant_path_failure_map; 799 u8 active_path_number; 800 __le16 alternate_paths_phys_connector[8]; 801 u8 alternate_paths_phys_box_on_port[8]; 802 u8 multi_lun_device_lun_count; 803 u8 minimum_good_fw_revision[8]; 804 u8 unique_inquiry_bytes[20]; 805 u8 current_temperature_degreesC; 806 u8 temperature_threshold_degreesC; 807 u8 max_temperature_degreesC; 808 u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */ 809 __le16 current_queue_depth_limit; 810 u8 switch_name[10]; 811 __le16 switch_port; 812 u8 alternate_paths_switch_name[40]; 813 u8 alternate_paths_switch_port[8]; 814 __le16 power_on_hours; /* valid only if gas gauge supported */ 815 __le16 percent_endurance_used; /* valid only if gas gauge supported. */ 816 #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \ 817 ((idphydrv->percent_endurance_used & 0x80) || \ 818 (idphydrv->percent_endurance_used > 10000)) 819 u8 drive_authentication; 820 #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \ 821 (idphydrv->drive_authentication == 0x80) 822 u8 smart_carrier_authentication; 823 #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \ 824 (idphydrv->smart_carrier_authentication != 0x0) 825 #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \ 826 (idphydrv->smart_carrier_authentication == 0x01) 827 u8 smart_carrier_app_fw_version; 828 u8 smart_carrier_bootloader_fw_version; 829 u8 encryption_key_name[64]; 830 __le32 misc_drive_flags; 831 __le16 dek_index; 832 u8 padding[112]; 833 }; 834 835 struct bmic_sense_subsystem_info { 836 u8 primary_slot_number; 837 u8 reserved[3]; 838 u8 chasis_serial_number[32]; 839 u8 primary_world_wide_id[8]; 840 u8 primary_array_serial_number[32]; /* NULL terminated */ 841 u8 primary_cache_serial_number[32]; /* NULL terminated */ 842 u8 reserved_2[8]; 843 u8 secondary_array_serial_number[32]; 844 u8 secondary_cache_serial_number[32]; 845 u8 pad[332]; 846 }; 847 848 struct bmic_sense_storage_box_params { 849 u8 reserved[36]; 850 u8 inquiry_valid; 851 u8 reserved_1[68]; 852 u8 phys_box_on_port; 853 u8 reserved_2[22]; 854 u16 connection_info; 855 u8 reserver_3[84]; 856 u8 phys_connector[2]; 857 u8 reserved_4[296]; 858 }; 859 860 #pragma pack() 861 #endif /* HPSA_CMD_H */ 862