1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_H 22 #define HPSA_H 23 24 #include <scsi/scsicam.h> 25 26 #define IO_OK 0 27 #define IO_ERROR 1 28 29 struct ctlr_info; 30 31 struct access_method { 32 void (*submit_command)(struct ctlr_info *h, 33 struct CommandList *c); 34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 35 unsigned long (*fifo_full)(struct ctlr_info *h); 36 bool (*intr_pending)(struct ctlr_info *h); 37 unsigned long (*command_completed)(struct ctlr_info *h); 38 }; 39 40 struct hpsa_scsi_dev_t { 41 int devtype; 42 int bus, target, lun; /* as presented to the OS */ 43 unsigned char scsi3addr[8]; /* as presented to the HW */ 44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 47 unsigned char model[16]; /* bytes 16-31 of inquiry data */ 48 unsigned char raid_level; /* from inquiry page 0xC1 */ 49 }; 50 51 struct ctlr_info { 52 int ctlr; 53 char devname[8]; 54 char *product_name; 55 struct pci_dev *pdev; 56 u32 board_id; 57 void __iomem *vaddr; 58 unsigned long paddr; 59 int nr_cmds; /* Number of commands allowed on this controller */ 60 struct CfgTable __iomem *cfgtable; 61 int max_sg_entries; 62 int interrupts_enabled; 63 int major; 64 int max_commands; 65 int commands_outstanding; 66 int max_outstanding; /* Debug */ 67 int usage_count; /* number of opens all all minor devices */ 68 # define PERF_MODE_INT 0 69 # define DOORBELL_INT 1 70 # define SIMPLE_MODE_INT 2 71 # define MEMQ_MODE_INT 3 72 unsigned int intr[4]; 73 unsigned int msix_vector; 74 unsigned int msi_vector; 75 struct access_method access; 76 77 /* queue and queue Info */ 78 struct hlist_head reqQ; 79 struct hlist_head cmpQ; 80 unsigned int Qdepth; 81 unsigned int maxQsinceinit; 82 unsigned int maxSG; 83 spinlock_t lock; 84 int maxsgentries; 85 u8 max_cmd_sg_entries; 86 int chainsize; 87 struct SGDescriptor **cmd_sg_list; 88 89 /* pointers to command and error info pool */ 90 struct CommandList *cmd_pool; 91 dma_addr_t cmd_pool_dhandle; 92 struct ErrorInfo *errinfo_pool; 93 dma_addr_t errinfo_pool_dhandle; 94 unsigned long *cmd_pool_bits; 95 int nr_allocs; 96 int nr_frees; 97 int busy_initializing; 98 int busy_scanning; 99 int scan_finished; 100 spinlock_t scan_lock; 101 wait_queue_head_t scan_wait_queue; 102 103 struct Scsi_Host *scsi_host; 104 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 105 int ndevices; /* number of used elements in .dev[] array. */ 106 #define HPSA_MAX_SCSI_DEVS_PER_HBA 256 107 struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA]; 108 /* 109 * Performant mode tables. 110 */ 111 u32 trans_support; 112 u32 trans_offset; 113 struct TransTable_struct *transtable; 114 unsigned long transMethod; 115 116 /* 117 * Performant mode completion buffer 118 */ 119 u64 *reply_pool; 120 dma_addr_t reply_pool_dhandle; 121 u64 *reply_pool_head; 122 size_t reply_pool_size; 123 unsigned char reply_pool_wraparound; 124 u32 *blockFetchTable; 125 unsigned char *hba_inquiry_data; 126 }; 127 #define HPSA_ABORT_MSG 0 128 #define HPSA_DEVICE_RESET_MSG 1 129 #define HPSA_BUS_RESET_MSG 2 130 #define HPSA_HOST_RESET_MSG 3 131 #define HPSA_MSG_SEND_RETRY_LIMIT 10 132 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000 133 134 /* Maximum time in seconds driver will wait for command completions 135 * when polling before giving up. 136 */ 137 #define HPSA_MAX_POLL_TIME_SECS (20) 138 139 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 140 * how many times to retry TEST UNIT READY on a device 141 * while waiting for it to become ready before giving up. 142 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 143 * between sending TURs while waiting for a device 144 * to become ready. 145 */ 146 #define HPSA_TUR_RETRY_LIMIT (20) 147 #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 148 149 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 150 * to become ready, in seconds, before giving up on it. 151 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 152 * between polling the board to see if it is ready, in 153 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 154 * HPSA_BOARD_READY_ITERATIONS are derived from those. 155 */ 156 #define HPSA_BOARD_READY_WAIT_SECS (120) 157 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 158 #define HPSA_BOARD_READY_POLL_INTERVAL \ 159 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 160 #define HPSA_BOARD_READY_ITERATIONS \ 161 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 162 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 163 #define HPSA_POST_RESET_PAUSE_MSECS (3000) 164 #define HPSA_POST_RESET_NOOP_RETRIES (12) 165 166 /* Defining the diffent access_menthods */ 167 /* 168 * Memory mapped FIFO interface (SMART 53xx cards) 169 */ 170 #define SA5_DOORBELL 0x20 171 #define SA5_REQUEST_PORT_OFFSET 0x40 172 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 173 #define SA5_REPLY_PORT_OFFSET 0x44 174 #define SA5_INTR_STATUS 0x30 175 #define SA5_SCRATCHPAD_OFFSET 0xB0 176 177 #define SA5_CTCFG_OFFSET 0xB4 178 #define SA5_CTMEM_OFFSET 0xB8 179 180 #define SA5_INTR_OFF 0x08 181 #define SA5B_INTR_OFF 0x04 182 #define SA5_INTR_PENDING 0x08 183 #define SA5B_INTR_PENDING 0x04 184 #define FIFO_EMPTY 0xffffffff 185 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 186 187 #define HPSA_ERROR_BIT 0x02 188 189 /* Performant mode flags */ 190 #define SA5_PERF_INTR_PENDING 0x04 191 #define SA5_PERF_INTR_OFF 0x05 192 #define SA5_OUTDB_STATUS_PERF_BIT 0x01 193 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 194 #define SA5_OUTDB_CLEAR 0xA0 195 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 196 #define SA5_OUTDB_STATUS 0x9C 197 198 199 #define HPSA_INTR_ON 1 200 #define HPSA_INTR_OFF 0 201 /* 202 Send the command to the hardware 203 */ 204 static void SA5_submit_command(struct ctlr_info *h, 205 struct CommandList *c) 206 { 207 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, 208 c->Header.Tag.lower); 209 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 210 h->commands_outstanding++; 211 if (h->commands_outstanding > h->max_outstanding) 212 h->max_outstanding = h->commands_outstanding; 213 } 214 215 /* 216 * This card is the opposite of the other cards. 217 * 0 turns interrupts on... 218 * 0x08 turns them off... 219 */ 220 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 221 { 222 if (val) { /* Turn interrupts on */ 223 h->interrupts_enabled = 1; 224 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 225 } else { /* Turn them off */ 226 h->interrupts_enabled = 0; 227 writel(SA5_INTR_OFF, 228 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 229 } 230 } 231 232 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 233 { 234 if (val) { /* turn on interrupts */ 235 h->interrupts_enabled = 1; 236 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 237 } else { 238 h->interrupts_enabled = 0; 239 writel(SA5_PERF_INTR_OFF, 240 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 241 } 242 } 243 244 static unsigned long SA5_performant_completed(struct ctlr_info *h) 245 { 246 unsigned long register_value = FIFO_EMPTY; 247 248 /* flush the controller write of the reply queue by reading 249 * outbound doorbell status register. 250 */ 251 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 252 /* msi auto clears the interrupt pending bit. */ 253 if (!(h->msi_vector || h->msix_vector)) { 254 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 255 /* Do a read in order to flush the write to the controller 256 * (as per spec.) 257 */ 258 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 259 } 260 261 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) { 262 register_value = *(h->reply_pool_head); 263 (h->reply_pool_head)++; 264 h->commands_outstanding--; 265 } else { 266 register_value = FIFO_EMPTY; 267 } 268 /* Check for wraparound */ 269 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) { 270 h->reply_pool_head = h->reply_pool; 271 h->reply_pool_wraparound ^= 1; 272 } 273 274 return register_value; 275 } 276 277 /* 278 * Returns true if fifo is full. 279 * 280 */ 281 static unsigned long SA5_fifo_full(struct ctlr_info *h) 282 { 283 if (h->commands_outstanding >= h->max_commands) 284 return 1; 285 else 286 return 0; 287 288 } 289 /* 290 * returns value read from hardware. 291 * returns FIFO_EMPTY if there is nothing to read 292 */ 293 static unsigned long SA5_completed(struct ctlr_info *h) 294 { 295 unsigned long register_value 296 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 297 298 if (register_value != FIFO_EMPTY) 299 h->commands_outstanding--; 300 301 #ifdef HPSA_DEBUG 302 if (register_value != FIFO_EMPTY) 303 dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 304 register_value); 305 else 306 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n"); 307 #endif 308 309 return register_value; 310 } 311 /* 312 * Returns true if an interrupt is pending.. 313 */ 314 static bool SA5_intr_pending(struct ctlr_info *h) 315 { 316 unsigned long register_value = 317 readl(h->vaddr + SA5_INTR_STATUS); 318 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value); 319 return register_value & SA5_INTR_PENDING; 320 } 321 322 static bool SA5_performant_intr_pending(struct ctlr_info *h) 323 { 324 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 325 326 if (!register_value) 327 return false; 328 329 if (h->msi_vector || h->msix_vector) 330 return true; 331 332 /* Read outbound doorbell to flush */ 333 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 334 return register_value & SA5_OUTDB_STATUS_PERF_BIT; 335 } 336 337 static struct access_method SA5_access = { 338 SA5_submit_command, 339 SA5_intr_mask, 340 SA5_fifo_full, 341 SA5_intr_pending, 342 SA5_completed, 343 }; 344 345 static struct access_method SA5_performant_access = { 346 SA5_submit_command, 347 SA5_performant_intr_mask, 348 SA5_fifo_full, 349 SA5_performant_intr_pending, 350 SA5_performant_completed, 351 }; 352 353 struct board_type { 354 u32 board_id; 355 char *product_name; 356 struct access_method *access; 357 }; 358 359 #endif /* HPSA_H */ 360 361