1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2016 Microsemi Corporation 4 * Copyright 2014-2015 PMC-Sierra, Inc. 5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14 * NON INFRINGEMENT. See the GNU General Public License for more details. 15 * 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17 * 18 */ 19 #ifndef HPSA_H 20 #define HPSA_H 21 22 #include <scsi/scsicam.h> 23 24 #define IO_OK 0 25 #define IO_ERROR 1 26 27 struct ctlr_info; 28 29 struct access_method { 30 void (*submit_command)(struct ctlr_info *h, 31 struct CommandList *c); 32 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 33 bool (*intr_pending)(struct ctlr_info *h); 34 unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 35 }; 36 37 /* for SAS hosts and SAS expanders */ 38 struct hpsa_sas_node { 39 struct device *parent_dev; 40 struct list_head port_list_head; 41 }; 42 43 struct hpsa_sas_port { 44 struct list_head port_list_entry; 45 u64 sas_address; 46 struct sas_port *port; 47 int next_phy_index; 48 struct list_head phy_list_head; 49 struct hpsa_sas_node *parent_node; 50 struct sas_rphy *rphy; 51 }; 52 53 struct hpsa_sas_phy { 54 struct list_head phy_list_entry; 55 struct sas_phy *phy; 56 struct hpsa_sas_port *parent_port; 57 bool added_to_port; 58 }; 59 60 #define EXTERNAL_QD 7 61 struct hpsa_scsi_dev_t { 62 unsigned int devtype; 63 int bus, target, lun; /* as presented to the OS */ 64 unsigned char scsi3addr[8]; /* as presented to the HW */ 65 u8 physical_device : 1; 66 u8 expose_device; 67 u8 removed : 1; /* device is marked for death */ 68 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 69 unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 70 u64 sas_address; 71 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 72 unsigned char model[16]; /* bytes 16-31 of inquiry data */ 73 unsigned char rev; /* byte 2 of inquiry data */ 74 unsigned char raid_level; /* from inquiry page 0xC1 */ 75 unsigned char volume_offline; /* discovered via TUR or VPD */ 76 u16 queue_depth; /* max queue_depth for this device */ 77 atomic_t reset_cmds_out; /* Count of commands to-be affected */ 78 atomic_t ioaccel_cmds_out; /* Only used for physical devices 79 * counts commands sent to physical 80 * device via "ioaccel" path. 81 */ 82 u32 ioaccel_handle; 83 u8 active_path_index; 84 u8 path_map; 85 u8 bay; 86 u8 box[8]; 87 u16 phys_connector[8]; 88 int offload_config; /* I/O accel RAID offload configured */ 89 int offload_enabled; /* I/O accel RAID offload enabled */ 90 int offload_to_be_enabled; 91 int hba_ioaccel_enabled; 92 int offload_to_mirror; /* Send next I/O accelerator RAID 93 * offload request to mirror drive 94 */ 95 struct raid_map_data raid_map; /* I/O accelerator RAID map */ 96 97 /* 98 * Pointers from logical drive map indices to the phys drives that 99 * make those logical drives. Note, multiple logical drives may 100 * share physical drives. You can have for instance 5 physical 101 * drives with 3 logical drives each using those same 5 physical 102 * disks. We need these pointers for counting i/o's out to physical 103 * devices in order to honor physical device queue depth limits. 104 */ 105 struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 106 int nphysical_disks; 107 int supports_aborts; 108 struct hpsa_sas_port *sas_port; 109 int external; /* 1-from external array 0-not <0-unknown */ 110 }; 111 112 struct reply_queue_buffer { 113 u64 *head; 114 size_t size; 115 u8 wraparound; 116 u32 current_entry; 117 dma_addr_t busaddr; 118 }; 119 120 #pragma pack(1) 121 struct bmic_controller_parameters { 122 u8 led_flags; 123 u8 enable_command_list_verification; 124 u8 backed_out_write_drives; 125 u16 stripes_for_parity; 126 u8 parity_distribution_mode_flags; 127 u16 max_driver_requests; 128 u16 elevator_trend_count; 129 u8 disable_elevator; 130 u8 force_scan_complete; 131 u8 scsi_transfer_mode; 132 u8 force_narrow; 133 u8 rebuild_priority; 134 u8 expand_priority; 135 u8 host_sdb_asic_fix; 136 u8 pdpi_burst_from_host_disabled; 137 char software_name[64]; 138 char hardware_name[32]; 139 u8 bridge_revision; 140 u8 snapshot_priority; 141 u32 os_specific; 142 u8 post_prompt_timeout; 143 u8 automatic_drive_slamming; 144 u8 reserved1; 145 u8 nvram_flags; 146 u8 cache_nvram_flags; 147 u8 drive_config_flags; 148 u16 reserved2; 149 u8 temp_warning_level; 150 u8 temp_shutdown_level; 151 u8 temp_condition_reset; 152 u8 max_coalesce_commands; 153 u32 max_coalesce_delay; 154 u8 orca_password[4]; 155 u8 access_id[16]; 156 u8 reserved[356]; 157 }; 158 #pragma pack() 159 160 struct ctlr_info { 161 unsigned int *reply_map; 162 int ctlr; 163 char devname[8]; 164 char *product_name; 165 struct pci_dev *pdev; 166 u32 board_id; 167 u64 sas_address; 168 void __iomem *vaddr; 169 unsigned long paddr; 170 int nr_cmds; /* Number of commands allowed on this controller */ 171 #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 172 #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 173 struct CfgTable __iomem *cfgtable; 174 int interrupts_enabled; 175 int max_commands; 176 atomic_t commands_outstanding; 177 # define PERF_MODE_INT 0 178 # define DOORBELL_INT 1 179 # define SIMPLE_MODE_INT 2 180 # define MEMQ_MODE_INT 3 181 unsigned int msix_vectors; 182 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 183 struct access_method access; 184 185 /* queue and queue Info */ 186 unsigned int Qdepth; 187 unsigned int maxSG; 188 spinlock_t lock; 189 int maxsgentries; 190 u8 max_cmd_sg_entries; 191 int chainsize; 192 struct SGDescriptor **cmd_sg_list; 193 struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; 194 195 /* pointers to command and error info pool */ 196 struct CommandList *cmd_pool; 197 dma_addr_t cmd_pool_dhandle; 198 struct io_accel1_cmd *ioaccel_cmd_pool; 199 dma_addr_t ioaccel_cmd_pool_dhandle; 200 struct io_accel2_cmd *ioaccel2_cmd_pool; 201 dma_addr_t ioaccel2_cmd_pool_dhandle; 202 struct ErrorInfo *errinfo_pool; 203 dma_addr_t errinfo_pool_dhandle; 204 unsigned long *cmd_pool_bits; 205 int scan_finished; 206 u8 scan_waiting : 1; 207 spinlock_t scan_lock; 208 wait_queue_head_t scan_wait_queue; 209 210 struct Scsi_Host *scsi_host; 211 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 212 int ndevices; /* number of used elements in .dev[] array. */ 213 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 214 /* 215 * Performant mode tables. 216 */ 217 u32 trans_support; 218 u32 trans_offset; 219 struct TransTable_struct __iomem *transtable; 220 unsigned long transMethod; 221 222 /* cap concurrent passthrus at some reasonable maximum */ 223 #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 224 atomic_t passthru_cmds_avail; 225 226 /* 227 * Performant mode completion buffers 228 */ 229 size_t reply_queue_size; 230 struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 231 u8 nreply_queues; 232 u32 *blockFetchTable; 233 u32 *ioaccel1_blockFetchTable; 234 u32 *ioaccel2_blockFetchTable; 235 u32 __iomem *ioaccel2_bft2_regs; 236 unsigned char *hba_inquiry_data; 237 u32 driver_support; 238 u32 fw_support; 239 int ioaccel_support; 240 int ioaccel_maxsg; 241 u64 last_intr_timestamp; 242 u32 last_heartbeat; 243 u64 last_heartbeat_timestamp; 244 u32 heartbeat_sample_interval; 245 atomic_t firmware_flash_in_progress; 246 u32 __percpu *lockup_detected; 247 struct delayed_work monitor_ctlr_work; 248 struct delayed_work rescan_ctlr_work; 249 struct delayed_work event_monitor_work; 250 int remove_in_progress; 251 /* Address of h->q[x] is passed to intr handler to know which queue */ 252 u8 q[MAX_REPLY_QUEUES]; 253 char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ 254 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 255 #define HPSATMF_BITS_SUPPORTED (1 << 0) 256 #define HPSATMF_PHYS_LUN_RESET (1 << 1) 257 #define HPSATMF_PHYS_NEX_RESET (1 << 2) 258 #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 259 #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 260 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 261 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 262 #define HPSATMF_PHYS_QRY_TASK (1 << 7) 263 #define HPSATMF_PHYS_QRY_TSET (1 << 8) 264 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 265 #define HPSATMF_IOACCEL_ENABLED (1 << 15) 266 #define HPSATMF_MASK_SUPPORTED (1 << 16) 267 #define HPSATMF_LOG_LUN_RESET (1 << 17) 268 #define HPSATMF_LOG_NEX_RESET (1 << 18) 269 #define HPSATMF_LOG_TASK_ABORT (1 << 19) 270 #define HPSATMF_LOG_TSET_ABORT (1 << 20) 271 #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 272 #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 273 #define HPSATMF_LOG_QRY_TASK (1 << 23) 274 #define HPSATMF_LOG_QRY_TSET (1 << 24) 275 #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 276 u32 events; 277 #define CTLR_STATE_CHANGE_EVENT (1 << 0) 278 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 279 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 280 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 281 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 282 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 283 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 284 285 #define RESCAN_REQUIRED_EVENT_BITS \ 286 (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 287 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 288 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 289 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 290 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 291 spinlock_t offline_device_lock; 292 struct list_head offline_device_list; 293 int acciopath_status; 294 int drv_req_rescan; 295 int raid_offload_debug; 296 int discovery_polling; 297 int legacy_board; 298 struct ReportLUNdata *lastlogicals; 299 int needs_abort_tags_swizzled; 300 struct workqueue_struct *resubmit_wq; 301 struct workqueue_struct *rescan_ctlr_wq; 302 atomic_t abort_cmds_available; 303 wait_queue_head_t event_sync_wait_queue; 304 struct mutex reset_mutex; 305 u8 reset_in_progress; 306 struct hpsa_sas_node *sas_host; 307 spinlock_t reset_lock; 308 }; 309 310 struct offline_device_entry { 311 unsigned char scsi3addr[8]; 312 struct list_head offline_list; 313 }; 314 315 #define HPSA_ABORT_MSG 0 316 #define HPSA_DEVICE_RESET_MSG 1 317 #define HPSA_RESET_TYPE_CONTROLLER 0x00 318 #define HPSA_RESET_TYPE_BUS 0x01 319 #define HPSA_RESET_TYPE_LUN 0x04 320 #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ 321 #define HPSA_MSG_SEND_RETRY_LIMIT 10 322 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 323 324 /* Maximum time in seconds driver will wait for command completions 325 * when polling before giving up. 326 */ 327 #define HPSA_MAX_POLL_TIME_SECS (20) 328 329 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 330 * how many times to retry TEST UNIT READY on a device 331 * while waiting for it to become ready before giving up. 332 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 333 * between sending TURs while waiting for a device 334 * to become ready. 335 */ 336 #define HPSA_TUR_RETRY_LIMIT (20) 337 #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 338 339 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 340 * to become ready, in seconds, before giving up on it. 341 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 342 * between polling the board to see if it is ready, in 343 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 344 * HPSA_BOARD_READY_ITERATIONS are derived from those. 345 */ 346 #define HPSA_BOARD_READY_WAIT_SECS (120) 347 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 348 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 349 #define HPSA_BOARD_READY_POLL_INTERVAL \ 350 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 351 #define HPSA_BOARD_READY_ITERATIONS \ 352 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 353 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 354 #define HPSA_BOARD_NOT_READY_ITERATIONS \ 355 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 356 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 357 #define HPSA_POST_RESET_PAUSE_MSECS (3000) 358 #define HPSA_POST_RESET_NOOP_RETRIES (12) 359 360 /* Defining the diffent access_menthods */ 361 /* 362 * Memory mapped FIFO interface (SMART 53xx cards) 363 */ 364 #define SA5_DOORBELL 0x20 365 #define SA5_REQUEST_PORT_OFFSET 0x40 366 #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 367 #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 368 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 369 #define SA5_REPLY_PORT_OFFSET 0x44 370 #define SA5_INTR_STATUS 0x30 371 #define SA5_SCRATCHPAD_OFFSET 0xB0 372 373 #define SA5_CTCFG_OFFSET 0xB4 374 #define SA5_CTMEM_OFFSET 0xB8 375 376 #define SA5_INTR_OFF 0x08 377 #define SA5B_INTR_OFF 0x04 378 #define SA5_INTR_PENDING 0x08 379 #define SA5B_INTR_PENDING 0x04 380 #define FIFO_EMPTY 0xffffffff 381 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 382 383 #define HPSA_ERROR_BIT 0x02 384 385 /* Performant mode flags */ 386 #define SA5_PERF_INTR_PENDING 0x04 387 #define SA5_PERF_INTR_OFF 0x05 388 #define SA5_OUTDB_STATUS_PERF_BIT 0x01 389 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 390 #define SA5_OUTDB_CLEAR 0xA0 391 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 392 #define SA5_OUTDB_STATUS 0x9C 393 394 395 #define HPSA_INTR_ON 1 396 #define HPSA_INTR_OFF 0 397 398 /* 399 * Inbound Post Queue offsets for IO Accelerator Mode 2 400 */ 401 #define IOACCEL2_INBOUND_POSTQ_32 0x48 402 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 403 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 404 405 #define HPSA_PHYSICAL_DEVICE_BUS 0 406 #define HPSA_RAID_VOLUME_BUS 1 407 #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 408 #define HPSA_HBA_BUS 0 409 #define HPSA_LEGACY_HBA_BUS 3 410 411 /* 412 Send the command to the hardware 413 */ 414 static void SA5_submit_command(struct ctlr_info *h, 415 struct CommandList *c) 416 { 417 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 418 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 419 } 420 421 static void SA5_submit_command_no_read(struct ctlr_info *h, 422 struct CommandList *c) 423 { 424 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 425 } 426 427 static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 428 struct CommandList *c) 429 { 430 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 431 } 432 433 /* 434 * This card is the opposite of the other cards. 435 * 0 turns interrupts on... 436 * 0x08 turns them off... 437 */ 438 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 439 { 440 if (val) { /* Turn interrupts on */ 441 h->interrupts_enabled = 1; 442 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 443 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 444 } else { /* Turn them off */ 445 h->interrupts_enabled = 0; 446 writel(SA5_INTR_OFF, 447 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 448 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 449 } 450 } 451 452 /* 453 * Variant of the above; 0x04 turns interrupts off... 454 */ 455 static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val) 456 { 457 if (val) { /* Turn interrupts on */ 458 h->interrupts_enabled = 1; 459 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 460 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 461 } else { /* Turn them off */ 462 h->interrupts_enabled = 0; 463 writel(SA5B_INTR_OFF, 464 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 465 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 466 } 467 } 468 469 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 470 { 471 if (val) { /* turn on interrupts */ 472 h->interrupts_enabled = 1; 473 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 474 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 475 } else { 476 h->interrupts_enabled = 0; 477 writel(SA5_PERF_INTR_OFF, 478 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 479 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 480 } 481 } 482 483 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 484 { 485 struct reply_queue_buffer *rq = &h->reply_queue[q]; 486 unsigned long register_value = FIFO_EMPTY; 487 488 /* msi auto clears the interrupt pending bit. */ 489 if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) { 490 /* flush the controller write of the reply queue by reading 491 * outbound doorbell status register. 492 */ 493 (void) readl(h->vaddr + SA5_OUTDB_STATUS); 494 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 495 /* Do a read in order to flush the write to the controller 496 * (as per spec.) 497 */ 498 (void) readl(h->vaddr + SA5_OUTDB_STATUS); 499 } 500 501 if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 502 register_value = rq->head[rq->current_entry]; 503 rq->current_entry++; 504 atomic_dec(&h->commands_outstanding); 505 } else { 506 register_value = FIFO_EMPTY; 507 } 508 /* Check for wraparound */ 509 if (rq->current_entry == h->max_commands) { 510 rq->current_entry = 0; 511 rq->wraparound ^= 1; 512 } 513 return register_value; 514 } 515 516 /* 517 * returns value read from hardware. 518 * returns FIFO_EMPTY if there is nothing to read 519 */ 520 static unsigned long SA5_completed(struct ctlr_info *h, 521 __attribute__((unused)) u8 q) 522 { 523 unsigned long register_value 524 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 525 526 if (register_value != FIFO_EMPTY) 527 atomic_dec(&h->commands_outstanding); 528 529 #ifdef HPSA_DEBUG 530 if (register_value != FIFO_EMPTY) 531 dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 532 register_value); 533 else 534 dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 535 #endif 536 537 return register_value; 538 } 539 /* 540 * Returns true if an interrupt is pending.. 541 */ 542 static bool SA5_intr_pending(struct ctlr_info *h) 543 { 544 unsigned long register_value = 545 readl(h->vaddr + SA5_INTR_STATUS); 546 return register_value & SA5_INTR_PENDING; 547 } 548 549 static bool SA5_performant_intr_pending(struct ctlr_info *h) 550 { 551 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 552 553 if (!register_value) 554 return false; 555 556 /* Read outbound doorbell to flush */ 557 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 558 return register_value & SA5_OUTDB_STATUS_PERF_BIT; 559 } 560 561 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 562 563 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 564 { 565 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 566 567 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 568 true : false; 569 } 570 571 /* 572 * Returns true if an interrupt is pending.. 573 */ 574 static bool SA5B_intr_pending(struct ctlr_info *h) 575 { 576 return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING; 577 } 578 579 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 580 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 581 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 582 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 583 584 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 585 { 586 u64 register_value; 587 struct reply_queue_buffer *rq = &h->reply_queue[q]; 588 589 BUG_ON(q >= h->nreply_queues); 590 591 register_value = rq->head[rq->current_entry]; 592 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 593 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 594 if (++rq->current_entry == rq->size) 595 rq->current_entry = 0; 596 /* 597 * @todo 598 * 599 * Don't really need to write the new index after each command, 600 * but with current driver design this is easiest. 601 */ 602 wmb(); 603 writel((q << 24) | rq->current_entry, h->vaddr + 604 IOACCEL_MODE1_CONSUMER_INDEX); 605 atomic_dec(&h->commands_outstanding); 606 } 607 return (unsigned long) register_value; 608 } 609 610 static struct access_method SA5_access = { 611 .submit_command = SA5_submit_command, 612 .set_intr_mask = SA5_intr_mask, 613 .intr_pending = SA5_intr_pending, 614 .command_completed = SA5_completed, 615 }; 616 617 /* Duplicate entry of the above to mark unsupported boards */ 618 static struct access_method SA5A_access = { 619 .submit_command = SA5_submit_command, 620 .set_intr_mask = SA5_intr_mask, 621 .intr_pending = SA5_intr_pending, 622 .command_completed = SA5_completed, 623 }; 624 625 static struct access_method SA5B_access = { 626 .submit_command = SA5_submit_command, 627 .set_intr_mask = SA5B_intr_mask, 628 .intr_pending = SA5B_intr_pending, 629 .command_completed = SA5_completed, 630 }; 631 632 static struct access_method SA5_ioaccel_mode1_access = { 633 .submit_command = SA5_submit_command, 634 .set_intr_mask = SA5_performant_intr_mask, 635 .intr_pending = SA5_ioaccel_mode1_intr_pending, 636 .command_completed = SA5_ioaccel_mode1_completed, 637 }; 638 639 static struct access_method SA5_ioaccel_mode2_access = { 640 .submit_command = SA5_submit_command_ioaccel2, 641 .set_intr_mask = SA5_performant_intr_mask, 642 .intr_pending = SA5_performant_intr_pending, 643 .command_completed = SA5_performant_completed, 644 }; 645 646 static struct access_method SA5_performant_access = { 647 .submit_command = SA5_submit_command, 648 .set_intr_mask = SA5_performant_intr_mask, 649 .intr_pending = SA5_performant_intr_pending, 650 .command_completed = SA5_performant_completed, 651 }; 652 653 static struct access_method SA5_performant_access_no_read = { 654 .submit_command = SA5_submit_command_no_read, 655 .set_intr_mask = SA5_performant_intr_mask, 656 .intr_pending = SA5_performant_intr_pending, 657 .command_completed = SA5_performant_completed, 658 }; 659 660 struct board_type { 661 u32 board_id; 662 char *product_name; 663 struct access_method *access; 664 }; 665 666 #endif /* HPSA_H */ 667 668