1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 * 18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19 * 20 */ 21 #ifndef HPSA_H 22 #define HPSA_H 23 24 #include <scsi/scsicam.h> 25 26 #define IO_OK 0 27 #define IO_ERROR 1 28 29 struct ctlr_info; 30 31 struct access_method { 32 void (*submit_command)(struct ctlr_info *h, 33 struct CommandList *c); 34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 35 unsigned long (*fifo_full)(struct ctlr_info *h); 36 bool (*intr_pending)(struct ctlr_info *h); 37 unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 38 }; 39 40 struct hpsa_scsi_dev_t { 41 int devtype; 42 int bus, target, lun; /* as presented to the OS */ 43 unsigned char scsi3addr[8]; /* as presented to the HW */ 44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 47 unsigned char model[16]; /* bytes 16-31 of inquiry data */ 48 unsigned char raid_level; /* from inquiry page 0xC1 */ 49 unsigned char volume_offline; /* discovered via TUR or VPD */ 50 u32 ioaccel_handle; 51 int offload_config; /* I/O accel RAID offload configured */ 52 int offload_enabled; /* I/O accel RAID offload enabled */ 53 int offload_to_mirror; /* Send next I/O accelerator RAID 54 * offload request to mirror drive 55 */ 56 struct raid_map_data raid_map; /* I/O accelerator RAID map */ 57 58 }; 59 60 struct reply_pool { 61 u64 *head; 62 size_t size; 63 u8 wraparound; 64 u32 current_entry; 65 }; 66 67 #pragma pack(1) 68 struct bmic_controller_parameters { 69 u8 led_flags; 70 u8 enable_command_list_verification; 71 u8 backed_out_write_drives; 72 u16 stripes_for_parity; 73 u8 parity_distribution_mode_flags; 74 u16 max_driver_requests; 75 u16 elevator_trend_count; 76 u8 disable_elevator; 77 u8 force_scan_complete; 78 u8 scsi_transfer_mode; 79 u8 force_narrow; 80 u8 rebuild_priority; 81 u8 expand_priority; 82 u8 host_sdb_asic_fix; 83 u8 pdpi_burst_from_host_disabled; 84 char software_name[64]; 85 char hardware_name[32]; 86 u8 bridge_revision; 87 u8 snapshot_priority; 88 u32 os_specific; 89 u8 post_prompt_timeout; 90 u8 automatic_drive_slamming; 91 u8 reserved1; 92 u8 nvram_flags; 93 #define HBA_MODE_ENABLED_FLAG (1 << 3) 94 u8 cache_nvram_flags; 95 u8 drive_config_flags; 96 u16 reserved2; 97 u8 temp_warning_level; 98 u8 temp_shutdown_level; 99 u8 temp_condition_reset; 100 u8 max_coalesce_commands; 101 u32 max_coalesce_delay; 102 u8 orca_password[4]; 103 u8 access_id[16]; 104 u8 reserved[356]; 105 }; 106 #pragma pack() 107 108 struct ctlr_info { 109 int ctlr; 110 char devname[8]; 111 char *product_name; 112 struct pci_dev *pdev; 113 u32 board_id; 114 void __iomem *vaddr; 115 unsigned long paddr; 116 int nr_cmds; /* Number of commands allowed on this controller */ 117 struct CfgTable __iomem *cfgtable; 118 int interrupts_enabled; 119 int major; 120 int max_commands; 121 int commands_outstanding; 122 int max_outstanding; /* Debug */ 123 int usage_count; /* number of opens all all minor devices */ 124 # define PERF_MODE_INT 0 125 # define DOORBELL_INT 1 126 # define SIMPLE_MODE_INT 2 127 # define MEMQ_MODE_INT 3 128 unsigned int intr[MAX_REPLY_QUEUES]; 129 unsigned int msix_vector; 130 unsigned int msi_vector; 131 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 132 struct access_method access; 133 char hba_mode_enabled; 134 135 /* queue and queue Info */ 136 struct list_head reqQ; 137 struct list_head cmpQ; 138 unsigned int Qdepth; 139 unsigned int maxSG; 140 spinlock_t lock; 141 int maxsgentries; 142 u8 max_cmd_sg_entries; 143 int chainsize; 144 struct SGDescriptor **cmd_sg_list; 145 146 /* pointers to command and error info pool */ 147 struct CommandList *cmd_pool; 148 dma_addr_t cmd_pool_dhandle; 149 struct io_accel1_cmd *ioaccel_cmd_pool; 150 dma_addr_t ioaccel_cmd_pool_dhandle; 151 struct io_accel2_cmd *ioaccel2_cmd_pool; 152 dma_addr_t ioaccel2_cmd_pool_dhandle; 153 struct ErrorInfo *errinfo_pool; 154 dma_addr_t errinfo_pool_dhandle; 155 unsigned long *cmd_pool_bits; 156 int scan_finished; 157 spinlock_t scan_lock; 158 wait_queue_head_t scan_wait_queue; 159 160 struct Scsi_Host *scsi_host; 161 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 162 int ndevices; /* number of used elements in .dev[] array. */ 163 struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 164 /* 165 * Performant mode tables. 166 */ 167 u32 trans_support; 168 u32 trans_offset; 169 struct TransTable_struct *transtable; 170 unsigned long transMethod; 171 172 /* cap concurrent passthrus at some reasonable maximum */ 173 #define HPSA_MAX_CONCURRENT_PASSTHRUS (20) 174 spinlock_t passthru_count_lock; /* protects passthru_count */ 175 int passthru_count; 176 177 /* 178 * Performant mode completion buffers 179 */ 180 u64 *reply_pool; 181 size_t reply_pool_size; 182 struct reply_pool reply_queue[MAX_REPLY_QUEUES]; 183 u8 nreply_queues; 184 dma_addr_t reply_pool_dhandle; 185 u32 *blockFetchTable; 186 u32 *ioaccel1_blockFetchTable; 187 u32 *ioaccel2_blockFetchTable; 188 u32 *ioaccel2_bft2_regs; 189 unsigned char *hba_inquiry_data; 190 u32 driver_support; 191 u32 fw_support; 192 int ioaccel_support; 193 int ioaccel_maxsg; 194 u64 last_intr_timestamp; 195 u32 last_heartbeat; 196 u64 last_heartbeat_timestamp; 197 u32 heartbeat_sample_interval; 198 atomic_t firmware_flash_in_progress; 199 u32 lockup_detected; 200 struct delayed_work monitor_ctlr_work; 201 int remove_in_progress; 202 u32 fifo_recently_full; 203 /* Address of h->q[x] is passed to intr handler to know which queue */ 204 u8 q[MAX_REPLY_QUEUES]; 205 u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 206 #define HPSATMF_BITS_SUPPORTED (1 << 0) 207 #define HPSATMF_PHYS_LUN_RESET (1 << 1) 208 #define HPSATMF_PHYS_NEX_RESET (1 << 2) 209 #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 210 #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 211 #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 212 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 213 #define HPSATMF_PHYS_QRY_TASK (1 << 7) 214 #define HPSATMF_PHYS_QRY_TSET (1 << 8) 215 #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 216 #define HPSATMF_MASK_SUPPORTED (1 << 16) 217 #define HPSATMF_LOG_LUN_RESET (1 << 17) 218 #define HPSATMF_LOG_NEX_RESET (1 << 18) 219 #define HPSATMF_LOG_TASK_ABORT (1 << 19) 220 #define HPSATMF_LOG_TSET_ABORT (1 << 20) 221 #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 222 #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 223 #define HPSATMF_LOG_QRY_TASK (1 << 23) 224 #define HPSATMF_LOG_QRY_TSET (1 << 24) 225 #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 226 u32 events; 227 #define CTLR_STATE_CHANGE_EVENT (1 << 0) 228 #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 229 #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 230 #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 231 #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 232 #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 233 #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 234 235 #define RESCAN_REQUIRED_EVENT_BITS \ 236 (CTLR_STATE_CHANGE_EVENT | \ 237 CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 238 CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 239 CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 240 CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL | \ 241 CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 242 CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 243 spinlock_t offline_device_lock; 244 struct list_head offline_device_list; 245 int acciopath_status; 246 int drv_req_rescan; /* flag for driver to request rescan event */ 247 int raid_offload_debug; 248 }; 249 250 struct offline_device_entry { 251 unsigned char scsi3addr[8]; 252 struct list_head offline_list; 253 }; 254 255 #define HPSA_ABORT_MSG 0 256 #define HPSA_DEVICE_RESET_MSG 1 257 #define HPSA_RESET_TYPE_CONTROLLER 0x00 258 #define HPSA_RESET_TYPE_BUS 0x01 259 #define HPSA_RESET_TYPE_TARGET 0x03 260 #define HPSA_RESET_TYPE_LUN 0x04 261 #define HPSA_MSG_SEND_RETRY_LIMIT 10 262 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 263 264 /* Maximum time in seconds driver will wait for command completions 265 * when polling before giving up. 266 */ 267 #define HPSA_MAX_POLL_TIME_SECS (20) 268 269 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 270 * how many times to retry TEST UNIT READY on a device 271 * while waiting for it to become ready before giving up. 272 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 273 * between sending TURs while waiting for a device 274 * to become ready. 275 */ 276 #define HPSA_TUR_RETRY_LIMIT (20) 277 #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 278 279 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 280 * to become ready, in seconds, before giving up on it. 281 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 282 * between polling the board to see if it is ready, in 283 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 284 * HPSA_BOARD_READY_ITERATIONS are derived from those. 285 */ 286 #define HPSA_BOARD_READY_WAIT_SECS (120) 287 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 288 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 289 #define HPSA_BOARD_READY_POLL_INTERVAL \ 290 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 291 #define HPSA_BOARD_READY_ITERATIONS \ 292 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 293 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 294 #define HPSA_BOARD_NOT_READY_ITERATIONS \ 295 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 296 HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 297 #define HPSA_POST_RESET_PAUSE_MSECS (3000) 298 #define HPSA_POST_RESET_NOOP_RETRIES (12) 299 300 /* Defining the diffent access_menthods */ 301 /* 302 * Memory mapped FIFO interface (SMART 53xx cards) 303 */ 304 #define SA5_DOORBELL 0x20 305 #define SA5_REQUEST_PORT_OFFSET 0x40 306 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 307 #define SA5_REPLY_PORT_OFFSET 0x44 308 #define SA5_INTR_STATUS 0x30 309 #define SA5_SCRATCHPAD_OFFSET 0xB0 310 311 #define SA5_CTCFG_OFFSET 0xB4 312 #define SA5_CTMEM_OFFSET 0xB8 313 314 #define SA5_INTR_OFF 0x08 315 #define SA5B_INTR_OFF 0x04 316 #define SA5_INTR_PENDING 0x08 317 #define SA5B_INTR_PENDING 0x04 318 #define FIFO_EMPTY 0xffffffff 319 #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 320 321 #define HPSA_ERROR_BIT 0x02 322 323 /* Performant mode flags */ 324 #define SA5_PERF_INTR_PENDING 0x04 325 #define SA5_PERF_INTR_OFF 0x05 326 #define SA5_OUTDB_STATUS_PERF_BIT 0x01 327 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 328 #define SA5_OUTDB_CLEAR 0xA0 329 #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 330 #define SA5_OUTDB_STATUS 0x9C 331 332 333 #define HPSA_INTR_ON 1 334 #define HPSA_INTR_OFF 0 335 336 /* 337 * Inbound Post Queue offsets for IO Accelerator Mode 2 338 */ 339 #define IOACCEL2_INBOUND_POSTQ_32 0x48 340 #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 341 #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 342 343 /* 344 Send the command to the hardware 345 */ 346 static void SA5_submit_command(struct ctlr_info *h, 347 struct CommandList *c) 348 { 349 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, 350 c->Header.Tag.lower); 351 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 352 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 353 } 354 355 static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 356 struct CommandList *c) 357 { 358 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr, 359 c->Header.Tag.lower); 360 if (c->cmd_type == CMD_IOACCEL2) 361 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 362 else 363 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 364 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 365 } 366 367 /* 368 * This card is the opposite of the other cards. 369 * 0 turns interrupts on... 370 * 0x08 turns them off... 371 */ 372 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 373 { 374 if (val) { /* Turn interrupts on */ 375 h->interrupts_enabled = 1; 376 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 377 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 378 } else { /* Turn them off */ 379 h->interrupts_enabled = 0; 380 writel(SA5_INTR_OFF, 381 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 382 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 383 } 384 } 385 386 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 387 { 388 if (val) { /* turn on interrupts */ 389 h->interrupts_enabled = 1; 390 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 391 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 392 } else { 393 h->interrupts_enabled = 0; 394 writel(SA5_PERF_INTR_OFF, 395 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 396 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 397 } 398 } 399 400 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 401 { 402 struct reply_pool *rq = &h->reply_queue[q]; 403 unsigned long flags, register_value = FIFO_EMPTY; 404 405 /* msi auto clears the interrupt pending bit. */ 406 if (!(h->msi_vector || h->msix_vector)) { 407 /* flush the controller write of the reply queue by reading 408 * outbound doorbell status register. 409 */ 410 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 411 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 412 /* Do a read in order to flush the write to the controller 413 * (as per spec.) 414 */ 415 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 416 } 417 418 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { 419 register_value = rq->head[rq->current_entry]; 420 rq->current_entry++; 421 spin_lock_irqsave(&h->lock, flags); 422 h->commands_outstanding--; 423 spin_unlock_irqrestore(&h->lock, flags); 424 } else { 425 register_value = FIFO_EMPTY; 426 } 427 /* Check for wraparound */ 428 if (rq->current_entry == h->max_commands) { 429 rq->current_entry = 0; 430 rq->wraparound ^= 1; 431 } 432 return register_value; 433 } 434 435 /* 436 * Returns true if fifo is full. 437 * 438 */ 439 static unsigned long SA5_fifo_full(struct ctlr_info *h) 440 { 441 if (h->commands_outstanding >= h->max_commands) 442 return 1; 443 else 444 return 0; 445 446 } 447 /* 448 * returns value read from hardware. 449 * returns FIFO_EMPTY if there is nothing to read 450 */ 451 static unsigned long SA5_completed(struct ctlr_info *h, 452 __attribute__((unused)) u8 q) 453 { 454 unsigned long register_value 455 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 456 unsigned long flags; 457 458 if (register_value != FIFO_EMPTY) { 459 spin_lock_irqsave(&h->lock, flags); 460 h->commands_outstanding--; 461 spin_unlock_irqrestore(&h->lock, flags); 462 } 463 464 #ifdef HPSA_DEBUG 465 if (register_value != FIFO_EMPTY) 466 dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 467 register_value); 468 else 469 dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 470 #endif 471 472 return register_value; 473 } 474 /* 475 * Returns true if an interrupt is pending.. 476 */ 477 static bool SA5_intr_pending(struct ctlr_info *h) 478 { 479 unsigned long register_value = 480 readl(h->vaddr + SA5_INTR_STATUS); 481 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value); 482 return register_value & SA5_INTR_PENDING; 483 } 484 485 static bool SA5_performant_intr_pending(struct ctlr_info *h) 486 { 487 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 488 489 if (!register_value) 490 return false; 491 492 if (h->msi_vector || h->msix_vector) 493 return true; 494 495 /* Read outbound doorbell to flush */ 496 register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 497 return register_value & SA5_OUTDB_STATUS_PERF_BIT; 498 } 499 500 #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 501 502 static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 503 { 504 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 505 506 return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 507 true : false; 508 } 509 510 #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 511 #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 512 #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 513 #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 514 515 static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 516 { 517 u64 register_value; 518 struct reply_pool *rq = &h->reply_queue[q]; 519 unsigned long flags; 520 521 BUG_ON(q >= h->nreply_queues); 522 523 register_value = rq->head[rq->current_entry]; 524 if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 525 rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 526 if (++rq->current_entry == rq->size) 527 rq->current_entry = 0; 528 /* 529 * @todo 530 * 531 * Don't really need to write the new index after each command, 532 * but with current driver design this is easiest. 533 */ 534 wmb(); 535 writel((q << 24) | rq->current_entry, h->vaddr + 536 IOACCEL_MODE1_CONSUMER_INDEX); 537 spin_lock_irqsave(&h->lock, flags); 538 h->commands_outstanding--; 539 spin_unlock_irqrestore(&h->lock, flags); 540 } 541 return (unsigned long) register_value; 542 } 543 544 static struct access_method SA5_access = { 545 SA5_submit_command, 546 SA5_intr_mask, 547 SA5_fifo_full, 548 SA5_intr_pending, 549 SA5_completed, 550 }; 551 552 static struct access_method SA5_ioaccel_mode1_access = { 553 SA5_submit_command, 554 SA5_performant_intr_mask, 555 SA5_fifo_full, 556 SA5_ioaccel_mode1_intr_pending, 557 SA5_ioaccel_mode1_completed, 558 }; 559 560 static struct access_method SA5_ioaccel_mode2_access = { 561 SA5_submit_command_ioaccel2, 562 SA5_performant_intr_mask, 563 SA5_fifo_full, 564 SA5_performant_intr_pending, 565 SA5_performant_completed, 566 }; 567 568 static struct access_method SA5_performant_access = { 569 SA5_submit_command, 570 SA5_performant_intr_mask, 571 SA5_fifo_full, 572 SA5_performant_intr_pending, 573 SA5_performant_completed, 574 }; 575 576 struct board_type { 577 u32 board_id; 578 char *product_name; 579 struct access_method *access; 580 }; 581 582 #endif /* HPSA_H */ 583 584