1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 31358f6dcSDon Brace * Copyright 2014-2015 PMC-Sierra, Inc. 41358f6dcSDon Brace * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 5edd16368SStephen M. Cameron * 6edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 7edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 8edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 9edd16368SStephen M. Cameron * 10edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 11edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 12edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 14edd16368SStephen M. Cameron * 151358f6dcSDon Brace * Questions/Comments/Bugfixes to storagedev@pmcs.com 16edd16368SStephen M. Cameron * 17edd16368SStephen M. Cameron */ 18edd16368SStephen M. Cameron #ifndef HPSA_H 19edd16368SStephen M. Cameron #define HPSA_H 20edd16368SStephen M. Cameron 21edd16368SStephen M. Cameron #include <scsi/scsicam.h> 22edd16368SStephen M. Cameron 23edd16368SStephen M. Cameron #define IO_OK 0 24edd16368SStephen M. Cameron #define IO_ERROR 1 25edd16368SStephen M. Cameron 26edd16368SStephen M. Cameron struct ctlr_info; 27edd16368SStephen M. Cameron 28edd16368SStephen M. Cameron struct access_method { 29edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 30edd16368SStephen M. Cameron struct CommandList *c); 31edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 32900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 33254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 34edd16368SStephen M. Cameron }; 35edd16368SStephen M. Cameron 36d04e62b9SKevin Barnett /* for SAS hosts and SAS expanders */ 37d04e62b9SKevin Barnett struct hpsa_sas_node { 38d04e62b9SKevin Barnett struct device *parent_dev; 39d04e62b9SKevin Barnett struct list_head port_list_head; 40d04e62b9SKevin Barnett }; 41d04e62b9SKevin Barnett 42d04e62b9SKevin Barnett struct hpsa_sas_port { 43d04e62b9SKevin Barnett struct list_head port_list_entry; 44d04e62b9SKevin Barnett u64 sas_address; 45d04e62b9SKevin Barnett struct sas_port *port; 46d04e62b9SKevin Barnett int next_phy_index; 47d04e62b9SKevin Barnett struct list_head phy_list_head; 48d04e62b9SKevin Barnett struct hpsa_sas_node *parent_node; 49d04e62b9SKevin Barnett struct sas_rphy *rphy; 50d04e62b9SKevin Barnett }; 51d04e62b9SKevin Barnett 52d04e62b9SKevin Barnett struct hpsa_sas_phy { 53d04e62b9SKevin Barnett struct list_head phy_list_entry; 54d04e62b9SKevin Barnett struct sas_phy *phy; 55d04e62b9SKevin Barnett struct hpsa_sas_port *parent_port; 56d04e62b9SKevin Barnett bool added_to_port; 57d04e62b9SKevin Barnett }; 58d04e62b9SKevin Barnett 59edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 603ad7de6bSDon Brace unsigned int devtype; 61edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 62edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 6304fa2f44SKevin Barnett u8 physical_device : 1; 642a168208SKevin Barnett u8 expose_device; 65edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 66edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 67d04e62b9SKevin Barnett u64 sas_address; 68edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 69edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 70edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 719846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 7203383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 73d604f533SWebb Scales atomic_t reset_cmds_out; /* Count of commands to-be affected */ 7403383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 7503383736SDon Brace * counts commands sent to physical 7603383736SDon Brace * device via "ioaccel" path. 7703383736SDon Brace */ 78e1f7de0cSMatt Gates u32 ioaccel_handle; 798270b862SJoe Handzik u8 active_path_index; 808270b862SJoe Handzik u8 path_map; 818270b862SJoe Handzik u8 bay; 828270b862SJoe Handzik u8 box[8]; 838270b862SJoe Handzik u16 phys_connector[8]; 84283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 85283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 8641ce4c35SStephen Cameron int offload_to_be_enabled; 87a3144e0bSJoe Handzik int hba_ioaccel_enabled; 88283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 89283b4a9bSStephen M. Cameron * offload request to mirror drive 90283b4a9bSStephen M. Cameron */ 91283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 92283b4a9bSStephen M. Cameron 9303383736SDon Brace /* 9403383736SDon Brace * Pointers from logical drive map indices to the phys drives that 9503383736SDon Brace * make those logical drives. Note, multiple logical drives may 9603383736SDon Brace * share physical drives. You can have for instance 5 physical 9703383736SDon Brace * drives with 3 logical drives each using those same 5 physical 9803383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 9903383736SDon Brace * devices in order to honor physical device queue depth limits. 10003383736SDon Brace */ 10103383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 102d604f533SWebb Scales int nphysical_disks; 1039b5c48c2SStephen Cameron int supports_aborts; 104d04e62b9SKevin Barnett struct hpsa_sas_port *sas_port; 10566749d0dSScott Teel int external; /* 1-from external array 0-not <0-unknown */ 106edd16368SStephen M. Cameron }; 107edd16368SStephen M. Cameron 108072b0518SStephen M. Cameron struct reply_queue_buffer { 109254f796bSMatt Gates u64 *head; 110254f796bSMatt Gates size_t size; 111254f796bSMatt Gates u8 wraparound; 112254f796bSMatt Gates u32 current_entry; 113072b0518SStephen M. Cameron dma_addr_t busaddr; 114254f796bSMatt Gates }; 115254f796bSMatt Gates 116316b221aSStephen M. Cameron #pragma pack(1) 117316b221aSStephen M. Cameron struct bmic_controller_parameters { 118316b221aSStephen M. Cameron u8 led_flags; 119316b221aSStephen M. Cameron u8 enable_command_list_verification; 120316b221aSStephen M. Cameron u8 backed_out_write_drives; 121316b221aSStephen M. Cameron u16 stripes_for_parity; 122316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 123316b221aSStephen M. Cameron u16 max_driver_requests; 124316b221aSStephen M. Cameron u16 elevator_trend_count; 125316b221aSStephen M. Cameron u8 disable_elevator; 126316b221aSStephen M. Cameron u8 force_scan_complete; 127316b221aSStephen M. Cameron u8 scsi_transfer_mode; 128316b221aSStephen M. Cameron u8 force_narrow; 129316b221aSStephen M. Cameron u8 rebuild_priority; 130316b221aSStephen M. Cameron u8 expand_priority; 131316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 132316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 133316b221aSStephen M. Cameron char software_name[64]; 134316b221aSStephen M. Cameron char hardware_name[32]; 135316b221aSStephen M. Cameron u8 bridge_revision; 136316b221aSStephen M. Cameron u8 snapshot_priority; 137316b221aSStephen M. Cameron u32 os_specific; 138316b221aSStephen M. Cameron u8 post_prompt_timeout; 139316b221aSStephen M. Cameron u8 automatic_drive_slamming; 140316b221aSStephen M. Cameron u8 reserved1; 141316b221aSStephen M. Cameron u8 nvram_flags; 142316b221aSStephen M. Cameron u8 cache_nvram_flags; 143316b221aSStephen M. Cameron u8 drive_config_flags; 144316b221aSStephen M. Cameron u16 reserved2; 145316b221aSStephen M. Cameron u8 temp_warning_level; 146316b221aSStephen M. Cameron u8 temp_shutdown_level; 147316b221aSStephen M. Cameron u8 temp_condition_reset; 148316b221aSStephen M. Cameron u8 max_coalesce_commands; 149316b221aSStephen M. Cameron u32 max_coalesce_delay; 150316b221aSStephen M. Cameron u8 orca_password[4]; 151316b221aSStephen M. Cameron u8 access_id[16]; 152316b221aSStephen M. Cameron u8 reserved[356]; 153316b221aSStephen M. Cameron }; 154316b221aSStephen M. Cameron #pragma pack() 155316b221aSStephen M. Cameron 156edd16368SStephen M. Cameron struct ctlr_info { 157edd16368SStephen M. Cameron int ctlr; 158edd16368SStephen M. Cameron char devname[8]; 159edd16368SStephen M. Cameron char *product_name; 160edd16368SStephen M. Cameron struct pci_dev *pdev; 16101a02ffcSStephen M. Cameron u32 board_id; 162d04e62b9SKevin Barnett u64 sas_address; 163edd16368SStephen M. Cameron void __iomem *vaddr; 164edd16368SStephen M. Cameron unsigned long paddr; 165edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 166d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 167d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 168edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 169edd16368SStephen M. Cameron int interrupts_enabled; 170edd16368SStephen M. Cameron int max_commands; 1710cbf768eSStephen M. Cameron atomic_t commands_outstanding; 172303932fdSDon Brace # define PERF_MODE_INT 0 173303932fdSDon Brace # define DOORBELL_INT 1 174edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 175edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 176254f796bSMatt Gates unsigned int intr[MAX_REPLY_QUEUES]; 177edd16368SStephen M. Cameron unsigned int msix_vector; 178edd16368SStephen M. Cameron unsigned int msi_vector; 179a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 180edd16368SStephen M. Cameron struct access_method access; 181edd16368SStephen M. Cameron 182edd16368SStephen M. Cameron /* queue and queue Info */ 183edd16368SStephen M. Cameron unsigned int Qdepth; 184edd16368SStephen M. Cameron unsigned int maxSG; 185edd16368SStephen M. Cameron spinlock_t lock; 18633a2ffceSStephen M. Cameron int maxsgentries; 18733a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 18833a2ffceSStephen M. Cameron int chainsize; 18933a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 190d9a729f3SWebb Scales struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; 191edd16368SStephen M. Cameron 192edd16368SStephen M. Cameron /* pointers to command and error info pool */ 193edd16368SStephen M. Cameron struct CommandList *cmd_pool; 194edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 195e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 196e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 197aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 198aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 199edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 200edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 201edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 202a08a8471SStephen M. Cameron int scan_finished; 203a08a8471SStephen M. Cameron spinlock_t scan_lock; 204a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 205edd16368SStephen M. Cameron 206edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 207edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 208edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 209cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 210303932fdSDon Brace /* 211303932fdSDon Brace * Performant mode tables. 212303932fdSDon Brace */ 213303932fdSDon Brace u32 trans_support; 214303932fdSDon Brace u32 trans_offset; 21542a91641SDon Brace struct TransTable_struct __iomem *transtable; 216303932fdSDon Brace unsigned long transMethod; 217303932fdSDon Brace 2180390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 21945fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 22034f0c627SDon Brace atomic_t passthru_cmds_avail; 2210390f0c0SStephen M. Cameron 222303932fdSDon Brace /* 223254f796bSMatt Gates * Performant mode completion buffers 224303932fdSDon Brace */ 225072b0518SStephen M. Cameron size_t reply_queue_size; 226072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 227254f796bSMatt Gates u8 nreply_queues; 228303932fdSDon Brace u32 *blockFetchTable; 229e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 230aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 23142a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 232339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 233283b4a9bSStephen M. Cameron u32 driver_support; 234283b4a9bSStephen M. Cameron u32 fw_support; 235283b4a9bSStephen M. Cameron int ioaccel_support; 236283b4a9bSStephen M. Cameron int ioaccel_maxsg; 237a0c12413SStephen M. Cameron u64 last_intr_timestamp; 238a0c12413SStephen M. Cameron u32 last_heartbeat; 239a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 240e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 241e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 24242a91641SDon Brace u32 __percpu *lockup_detected; 2438a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2446636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2458a98db73SStephen M. Cameron int remove_in_progress; 246254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 247254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 2488b47004aSRobert Elliott char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ 24975167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 25075167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 25175167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 25275167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 25375167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 25475167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 25575167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 25675167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 25775167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 25875167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 25975167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 2608be986ccSStephen Cameron #define HPSATMF_IOACCEL_ENABLED (1 << 15) 26175167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 26275167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 26375167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 26475167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 26575167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 26675167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 26775167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 26875167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 26975167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 27075167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 27176438d08SStephen M. Cameron u32 events; 272faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 273faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 274faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 275faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 276faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 277faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 278faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 279faff6ee0SStephen M. Cameron 280faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2817b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 282faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 283faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 284faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 285faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2869846590eSStephen M. Cameron spinlock_t offline_device_lock; 2879846590eSStephen M. Cameron struct list_head offline_device_list; 288da0697bdSScott Teel int acciopath_status; 289853633e8SDon Brace int drv_req_rescan; 2902ba8bfc8SStephen M. Cameron int raid_offload_debug; 29134592254SScott Teel int discovery_polling; 29234592254SScott Teel struct ReportLUNdata *lastlogicals; 2939b5c48c2SStephen Cameron int needs_abort_tags_swizzled; 294080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 2956636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 2969b5c48c2SStephen Cameron atomic_t abort_cmds_available; 2979b5c48c2SStephen Cameron wait_queue_head_t abort_cmd_wait_queue; 298d604f533SWebb Scales wait_queue_head_t event_sync_wait_queue; 299d604f533SWebb Scales struct mutex reset_mutex; 300da03ded0SDon Brace u8 reset_in_progress; 301d04e62b9SKevin Barnett struct hpsa_sas_node *sas_host; 302edd16368SStephen M. Cameron }; 3039846590eSStephen M. Cameron 3049846590eSStephen M. Cameron struct offline_device_entry { 3059846590eSStephen M. Cameron unsigned char scsi3addr[8]; 3069846590eSStephen M. Cameron struct list_head offline_list; 3079846590eSStephen M. Cameron }; 3089846590eSStephen M. Cameron 309edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 310edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 31164670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 31264670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 31364670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_TARGET 0x03 31464670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 3150b9b7b6eSScott Teel #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ 316edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 317516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 318edd16368SStephen M. Cameron 319edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 320edd16368SStephen M. Cameron * when polling before giving up. 321edd16368SStephen M. Cameron */ 322edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 323edd16368SStephen M. Cameron 324edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 325edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 326edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 327edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 328edd16368SStephen M. Cameron * between sending TURs while waiting for a device 329edd16368SStephen M. Cameron * to become ready. 330edd16368SStephen M. Cameron */ 331edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 332edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 333edd16368SStephen M. Cameron 334edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 335edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 336edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 337edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 338edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 339edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 340edd16368SStephen M. Cameron */ 341edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3422ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 343edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 344edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 345edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 346edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 347edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 348edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 349fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 350fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 351fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 352edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 353edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 354edd16368SStephen M. Cameron 355edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 356edd16368SStephen M. Cameron /* 357edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 358edd16368SStephen M. Cameron */ 359edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 360edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 361281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 362281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 363edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 364edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 365edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 366edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 367edd16368SStephen M. Cameron 368edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 369edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 370edd16368SStephen M. Cameron 371edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 372edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 373edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 374edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 375edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 376edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 377edd16368SStephen M. Cameron 378edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 379edd16368SStephen M. Cameron 380303932fdSDon Brace /* Performant mode flags */ 381303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 382303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 383303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 384303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 385303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 386303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 387303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 388303932fdSDon Brace 389303932fdSDon Brace 390edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 391edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 392b66cc250SMike Miller 393b66cc250SMike Miller /* 394b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 395b66cc250SMike Miller */ 396b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 397b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 398b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 399b66cc250SMike Miller 400c795505aSKevin Barnett #define HPSA_PHYSICAL_DEVICE_BUS 0 401c795505aSKevin Barnett #define HPSA_RAID_VOLUME_BUS 1 402c795505aSKevin Barnett #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 403c795505aSKevin Barnett #define HPSA_HBA_BUS 3 404c795505aSKevin Barnett 405edd16368SStephen M. Cameron /* 406edd16368SStephen M. Cameron Send the command to the hardware 407edd16368SStephen M. Cameron */ 408edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 409edd16368SStephen M. Cameron struct CommandList *c) 410edd16368SStephen M. Cameron { 411edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 412fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 413edd16368SStephen M. Cameron } 414edd16368SStephen M. Cameron 415b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 416b3a52e79SStephen M. Cameron struct CommandList *c) 417b3a52e79SStephen M. Cameron { 418b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 419b3a52e79SStephen M. Cameron } 420b3a52e79SStephen M. Cameron 421c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 422c349775eSScott Teel struct CommandList *c) 423c349775eSScott Teel { 424c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 425c349775eSScott Teel } 426c349775eSScott Teel 427edd16368SStephen M. Cameron /* 428edd16368SStephen M. Cameron * This card is the opposite of the other cards. 429edd16368SStephen M. Cameron * 0 turns interrupts on... 430edd16368SStephen M. Cameron * 0x08 turns them off... 431edd16368SStephen M. Cameron */ 432edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 433edd16368SStephen M. Cameron { 434edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 435edd16368SStephen M. Cameron h->interrupts_enabled = 1; 436edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4378cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 438edd16368SStephen M. Cameron } else { /* Turn them off */ 439edd16368SStephen M. Cameron h->interrupts_enabled = 0; 440edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 441edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4428cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 443edd16368SStephen M. Cameron } 444edd16368SStephen M. Cameron } 445303932fdSDon Brace 446303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 447303932fdSDon Brace { 448303932fdSDon Brace if (val) { /* turn on interrupts */ 449303932fdSDon Brace h->interrupts_enabled = 1; 450303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4518cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 452303932fdSDon Brace } else { 453303932fdSDon Brace h->interrupts_enabled = 0; 454303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 455303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4568cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 457303932fdSDon Brace } 458303932fdSDon Brace } 459303932fdSDon Brace 460254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 461303932fdSDon Brace { 462072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4630cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 464303932fdSDon Brace 4652c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 466bee266a6SDon Brace if (unlikely(!(h->msi_vector || h->msix_vector))) { 467303932fdSDon Brace /* flush the controller write of the reply queue by reading 468303932fdSDon Brace * outbound doorbell status register. 469303932fdSDon Brace */ 470bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 471303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 472303932fdSDon Brace /* Do a read in order to flush the write to the controller 473303932fdSDon Brace * (as per spec.) 474303932fdSDon Brace */ 475bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 476303932fdSDon Brace } 477303932fdSDon Brace 478bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 479254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 480254f796bSMatt Gates rq->current_entry++; 4810cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 482303932fdSDon Brace } else { 483303932fdSDon Brace register_value = FIFO_EMPTY; 484303932fdSDon Brace } 485303932fdSDon Brace /* Check for wraparound */ 486254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 487254f796bSMatt Gates rq->current_entry = 0; 488254f796bSMatt Gates rq->wraparound ^= 1; 489303932fdSDon Brace } 490303932fdSDon Brace return register_value; 491303932fdSDon Brace } 492303932fdSDon Brace 493edd16368SStephen M. Cameron /* 494edd16368SStephen M. Cameron * returns value read from hardware. 495edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 496edd16368SStephen M. Cameron */ 497254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 498254f796bSMatt Gates __attribute__((unused)) u8 q) 499edd16368SStephen M. Cameron { 500edd16368SStephen M. Cameron unsigned long register_value 501edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 502edd16368SStephen M. Cameron 5030cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 5040cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 505edd16368SStephen M. Cameron 506edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 507edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 50884ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 509edd16368SStephen M. Cameron register_value); 510edd16368SStephen M. Cameron else 511f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 512edd16368SStephen M. Cameron #endif 513edd16368SStephen M. Cameron 514edd16368SStephen M. Cameron return register_value; 515edd16368SStephen M. Cameron } 516edd16368SStephen M. Cameron /* 517edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 518edd16368SStephen M. Cameron */ 519900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 520edd16368SStephen M. Cameron { 521edd16368SStephen M. Cameron unsigned long register_value = 522edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 523900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 524edd16368SStephen M. Cameron } 525edd16368SStephen M. Cameron 526303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 527303932fdSDon Brace { 528303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 529303932fdSDon Brace 530303932fdSDon Brace if (!register_value) 531303932fdSDon Brace return false; 532303932fdSDon Brace 533303932fdSDon Brace /* Read outbound doorbell to flush */ 534303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 535303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 536303932fdSDon Brace } 537edd16368SStephen M. Cameron 538e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 539e1f7de0cSMatt Gates 540e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 541e1f7de0cSMatt Gates { 542e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 543e1f7de0cSMatt Gates 544e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 545e1f7de0cSMatt Gates true : false; 546e1f7de0cSMatt Gates } 547e1f7de0cSMatt Gates 548e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 549e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 550e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 551e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 552e1f7de0cSMatt Gates 553283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 554e1f7de0cSMatt Gates { 555e1f7de0cSMatt Gates u64 register_value; 556072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 557e1f7de0cSMatt Gates 558e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 559e1f7de0cSMatt Gates 560e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 561e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 562e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 563e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 564e1f7de0cSMatt Gates rq->current_entry = 0; 565283b4a9bSStephen M. Cameron /* 566283b4a9bSStephen M. Cameron * @todo 567283b4a9bSStephen M. Cameron * 568283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 569283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 570283b4a9bSStephen M. Cameron */ 571283b4a9bSStephen M. Cameron wmb(); 572283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 573283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5740cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 575e1f7de0cSMatt Gates } 576e1f7de0cSMatt Gates return (unsigned long) register_value; 577e1f7de0cSMatt Gates } 578e1f7de0cSMatt Gates 579edd16368SStephen M. Cameron static struct access_method SA5_access = { 580edd16368SStephen M. Cameron SA5_submit_command, 581edd16368SStephen M. Cameron SA5_intr_mask, 582edd16368SStephen M. Cameron SA5_intr_pending, 583edd16368SStephen M. Cameron SA5_completed, 584edd16368SStephen M. Cameron }; 585edd16368SStephen M. Cameron 586e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 587e1f7de0cSMatt Gates SA5_submit_command, 588e1f7de0cSMatt Gates SA5_performant_intr_mask, 589e1f7de0cSMatt Gates SA5_ioaccel_mode1_intr_pending, 590e1f7de0cSMatt Gates SA5_ioaccel_mode1_completed, 591e1f7de0cSMatt Gates }; 592e1f7de0cSMatt Gates 593c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 594c349775eSScott Teel SA5_submit_command_ioaccel2, 595c349775eSScott Teel SA5_performant_intr_mask, 596c349775eSScott Teel SA5_performant_intr_pending, 597c349775eSScott Teel SA5_performant_completed, 598c349775eSScott Teel }; 599c349775eSScott Teel 600303932fdSDon Brace static struct access_method SA5_performant_access = { 601303932fdSDon Brace SA5_submit_command, 602303932fdSDon Brace SA5_performant_intr_mask, 603303932fdSDon Brace SA5_performant_intr_pending, 604303932fdSDon Brace SA5_performant_completed, 605303932fdSDon Brace }; 606303932fdSDon Brace 607b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 608b3a52e79SStephen M. Cameron SA5_submit_command_no_read, 609b3a52e79SStephen M. Cameron SA5_performant_intr_mask, 610b3a52e79SStephen M. Cameron SA5_performant_intr_pending, 611b3a52e79SStephen M. Cameron SA5_performant_completed, 612b3a52e79SStephen M. Cameron }; 613b3a52e79SStephen M. Cameron 614edd16368SStephen M. Cameron struct board_type { 61501a02ffcSStephen M. Cameron u32 board_id; 616edd16368SStephen M. Cameron char *product_name; 617edd16368SStephen M. Cameron struct access_method *access; 618edd16368SStephen M. Cameron }; 619edd16368SStephen M. Cameron 620edd16368SStephen M. Cameron #endif /* HPSA_H */ 621edd16368SStephen M. Cameron 622