1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 351c35139SScott Teel * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. 4edd16368SStephen M. Cameron * 5edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 6edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 7edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 8edd16368SStephen M. Cameron * 9edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 10edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 11edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 13edd16368SStephen M. Cameron * 14edd16368SStephen M. Cameron * You should have received a copy of the GNU General Public License 15edd16368SStephen M. Cameron * along with this program; if not, write to the Free Software 16edd16368SStephen M. Cameron * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17edd16368SStephen M. Cameron * 18edd16368SStephen M. Cameron * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19edd16368SStephen M. Cameron * 20edd16368SStephen M. Cameron */ 21edd16368SStephen M. Cameron #ifndef HPSA_H 22edd16368SStephen M. Cameron #define HPSA_H 23edd16368SStephen M. Cameron 24edd16368SStephen M. Cameron #include <scsi/scsicam.h> 25edd16368SStephen M. Cameron 26edd16368SStephen M. Cameron #define IO_OK 0 27edd16368SStephen M. Cameron #define IO_ERROR 1 28edd16368SStephen M. Cameron 29edd16368SStephen M. Cameron struct ctlr_info; 30edd16368SStephen M. Cameron 31edd16368SStephen M. Cameron struct access_method { 32edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 33edd16368SStephen M. Cameron struct CommandList *c); 34edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 35900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 36254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 37edd16368SStephen M. Cameron }; 38edd16368SStephen M. Cameron 39edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 40edd16368SStephen M. Cameron int devtype; 41edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 42edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 43edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 44edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 45edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 46edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 47edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 489846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 4903383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 5003383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 5103383736SDon Brace * counts commands sent to physical 5203383736SDon Brace * device via "ioaccel" path. 5303383736SDon Brace */ 54e1f7de0cSMatt Gates u32 ioaccel_handle; 55283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 56283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 57283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 58283b4a9bSStephen M. Cameron * offload request to mirror drive 59283b4a9bSStephen M. Cameron */ 60283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 61283b4a9bSStephen M. Cameron 6203383736SDon Brace /* 6303383736SDon Brace * Pointers from logical drive map indices to the phys drives that 6403383736SDon Brace * make those logical drives. Note, multiple logical drives may 6503383736SDon Brace * share physical drives. You can have for instance 5 physical 6603383736SDon Brace * drives with 3 logical drives each using those same 5 physical 6703383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 6803383736SDon Brace * devices in order to honor physical device queue depth limits. 6903383736SDon Brace */ 7003383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 71edd16368SStephen M. Cameron }; 72edd16368SStephen M. Cameron 73072b0518SStephen M. Cameron struct reply_queue_buffer { 74254f796bSMatt Gates u64 *head; 75254f796bSMatt Gates size_t size; 76254f796bSMatt Gates u8 wraparound; 77254f796bSMatt Gates u32 current_entry; 78072b0518SStephen M. Cameron dma_addr_t busaddr; 79254f796bSMatt Gates }; 80254f796bSMatt Gates 81316b221aSStephen M. Cameron #pragma pack(1) 82316b221aSStephen M. Cameron struct bmic_controller_parameters { 83316b221aSStephen M. Cameron u8 led_flags; 84316b221aSStephen M. Cameron u8 enable_command_list_verification; 85316b221aSStephen M. Cameron u8 backed_out_write_drives; 86316b221aSStephen M. Cameron u16 stripes_for_parity; 87316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 88316b221aSStephen M. Cameron u16 max_driver_requests; 89316b221aSStephen M. Cameron u16 elevator_trend_count; 90316b221aSStephen M. Cameron u8 disable_elevator; 91316b221aSStephen M. Cameron u8 force_scan_complete; 92316b221aSStephen M. Cameron u8 scsi_transfer_mode; 93316b221aSStephen M. Cameron u8 force_narrow; 94316b221aSStephen M. Cameron u8 rebuild_priority; 95316b221aSStephen M. Cameron u8 expand_priority; 96316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 97316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 98316b221aSStephen M. Cameron char software_name[64]; 99316b221aSStephen M. Cameron char hardware_name[32]; 100316b221aSStephen M. Cameron u8 bridge_revision; 101316b221aSStephen M. Cameron u8 snapshot_priority; 102316b221aSStephen M. Cameron u32 os_specific; 103316b221aSStephen M. Cameron u8 post_prompt_timeout; 104316b221aSStephen M. Cameron u8 automatic_drive_slamming; 105316b221aSStephen M. Cameron u8 reserved1; 106316b221aSStephen M. Cameron u8 nvram_flags; 1076e8e8088SJoe Handzik #define HBA_MODE_ENABLED_FLAG (1 << 3) 108316b221aSStephen M. Cameron u8 cache_nvram_flags; 109316b221aSStephen M. Cameron u8 drive_config_flags; 110316b221aSStephen M. Cameron u16 reserved2; 111316b221aSStephen M. Cameron u8 temp_warning_level; 112316b221aSStephen M. Cameron u8 temp_shutdown_level; 113316b221aSStephen M. Cameron u8 temp_condition_reset; 114316b221aSStephen M. Cameron u8 max_coalesce_commands; 115316b221aSStephen M. Cameron u32 max_coalesce_delay; 116316b221aSStephen M. Cameron u8 orca_password[4]; 117316b221aSStephen M. Cameron u8 access_id[16]; 118316b221aSStephen M. Cameron u8 reserved[356]; 119316b221aSStephen M. Cameron }; 120316b221aSStephen M. Cameron #pragma pack() 121316b221aSStephen M. Cameron 122edd16368SStephen M. Cameron struct ctlr_info { 123edd16368SStephen M. Cameron int ctlr; 124edd16368SStephen M. Cameron char devname[8]; 125edd16368SStephen M. Cameron char *product_name; 126edd16368SStephen M. Cameron struct pci_dev *pdev; 12701a02ffcSStephen M. Cameron u32 board_id; 128edd16368SStephen M. Cameron void __iomem *vaddr; 129edd16368SStephen M. Cameron unsigned long paddr; 130edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 131d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 132d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 133edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 134edd16368SStephen M. Cameron int interrupts_enabled; 135edd16368SStephen M. Cameron int max_commands; 13633811026SRobert Elliott int last_allocation; 1370cbf768eSStephen M. Cameron atomic_t commands_outstanding; 138303932fdSDon Brace # define PERF_MODE_INT 0 139303932fdSDon Brace # define DOORBELL_INT 1 140edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 141edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 142254f796bSMatt Gates unsigned int intr[MAX_REPLY_QUEUES]; 143edd16368SStephen M. Cameron unsigned int msix_vector; 144edd16368SStephen M. Cameron unsigned int msi_vector; 145a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 146edd16368SStephen M. Cameron struct access_method access; 147316b221aSStephen M. Cameron char hba_mode_enabled; 148edd16368SStephen M. Cameron 149edd16368SStephen M. Cameron /* queue and queue Info */ 150edd16368SStephen M. Cameron unsigned int Qdepth; 151edd16368SStephen M. Cameron unsigned int maxSG; 152edd16368SStephen M. Cameron spinlock_t lock; 15333a2ffceSStephen M. Cameron int maxsgentries; 15433a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 15533a2ffceSStephen M. Cameron int chainsize; 15633a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 157edd16368SStephen M. Cameron 158edd16368SStephen M. Cameron /* pointers to command and error info pool */ 159edd16368SStephen M. Cameron struct CommandList *cmd_pool; 160edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 161e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 162e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 163aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 164aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 165edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 166edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 167edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 168a08a8471SStephen M. Cameron int scan_finished; 169a08a8471SStephen M. Cameron spinlock_t scan_lock; 170a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 171edd16368SStephen M. Cameron 172edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 173edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 174edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 175cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 176303932fdSDon Brace /* 177303932fdSDon Brace * Performant mode tables. 178303932fdSDon Brace */ 179303932fdSDon Brace u32 trans_support; 180303932fdSDon Brace u32 trans_offset; 18142a91641SDon Brace struct TransTable_struct __iomem *transtable; 182303932fdSDon Brace unsigned long transMethod; 183303932fdSDon Brace 1840390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 18545fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 18634f0c627SDon Brace atomic_t passthru_cmds_avail; 1870390f0c0SStephen M. Cameron 188303932fdSDon Brace /* 189254f796bSMatt Gates * Performant mode completion buffers 190303932fdSDon Brace */ 191072b0518SStephen M. Cameron size_t reply_queue_size; 192072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 193254f796bSMatt Gates u8 nreply_queues; 194303932fdSDon Brace u32 *blockFetchTable; 195e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 196aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 19742a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 198339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 199283b4a9bSStephen M. Cameron u32 driver_support; 200283b4a9bSStephen M. Cameron u32 fw_support; 201283b4a9bSStephen M. Cameron int ioaccel_support; 202283b4a9bSStephen M. Cameron int ioaccel_maxsg; 203a0c12413SStephen M. Cameron u64 last_intr_timestamp; 204a0c12413SStephen M. Cameron u32 last_heartbeat; 205a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 206e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 207e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 20842a91641SDon Brace u32 __percpu *lockup_detected; 2098a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2108a98db73SStephen M. Cameron int remove_in_progress; 211254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 212254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 21375167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 21475167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 21575167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 21675167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 21775167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 21875167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 21975167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 22075167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 22175167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 22275167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 22375167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 22475167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 22575167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 22675167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 22775167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 22875167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 22975167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 23075167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 23175167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 23275167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 23375167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 23476438d08SStephen M. Cameron u32 events; 235faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 236faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 237faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 238faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 239faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 240faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 241faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 242faff6ee0SStephen M. Cameron 243faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2447b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 245faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 246faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 247faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 248faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2499846590eSStephen M. Cameron spinlock_t offline_device_lock; 2509846590eSStephen M. Cameron struct list_head offline_device_list; 251da0697bdSScott Teel int acciopath_status; 2522ba8bfc8SStephen M. Cameron int raid_offload_debug; 253080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 254edd16368SStephen M. Cameron }; 2559846590eSStephen M. Cameron 2569846590eSStephen M. Cameron struct offline_device_entry { 2579846590eSStephen M. Cameron unsigned char scsi3addr[8]; 2589846590eSStephen M. Cameron struct list_head offline_list; 2599846590eSStephen M. Cameron }; 2609846590eSStephen M. Cameron 261edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 262edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 26364670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 26464670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 26564670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_TARGET 0x03 26664670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 267edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 268516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 269edd16368SStephen M. Cameron 270edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 271edd16368SStephen M. Cameron * when polling before giving up. 272edd16368SStephen M. Cameron */ 273edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 274edd16368SStephen M. Cameron 275edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 276edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 277edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 278edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 279edd16368SStephen M. Cameron * between sending TURs while waiting for a device 280edd16368SStephen M. Cameron * to become ready. 281edd16368SStephen M. Cameron */ 282edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 283edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 284edd16368SStephen M. Cameron 285edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 286edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 287edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 288edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 289edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 290edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 291edd16368SStephen M. Cameron */ 292edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 2932ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 294edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 295edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 296edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 297edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 298edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 299edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 300fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 301fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 302fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 303edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 304edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 305edd16368SStephen M. Cameron 306edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 307edd16368SStephen M. Cameron /* 308edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 309edd16368SStephen M. Cameron */ 310edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 311edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 312281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 313281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 314edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 315edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 316edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 317edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 318edd16368SStephen M. Cameron 319edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 320edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 321edd16368SStephen M. Cameron 322edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 323edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 324edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 325edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 326edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 327edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 328edd16368SStephen M. Cameron 329edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 330edd16368SStephen M. Cameron 331303932fdSDon Brace /* Performant mode flags */ 332303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 333303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 334303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 335303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 336303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 337303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 338303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 339303932fdSDon Brace 340303932fdSDon Brace 341edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 342edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 343b66cc250SMike Miller 344b66cc250SMike Miller /* 345b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 346b66cc250SMike Miller */ 347b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 348b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 349b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 350b66cc250SMike Miller 351edd16368SStephen M. Cameron /* 352edd16368SStephen M. Cameron Send the command to the hardware 353edd16368SStephen M. Cameron */ 354edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 355edd16368SStephen M. Cameron struct CommandList *c) 356edd16368SStephen M. Cameron { 357edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 358fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 359edd16368SStephen M. Cameron } 360edd16368SStephen M. Cameron 361b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 362b3a52e79SStephen M. Cameron struct CommandList *c) 363b3a52e79SStephen M. Cameron { 364b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 365b3a52e79SStephen M. Cameron } 366b3a52e79SStephen M. Cameron 367c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 368c349775eSScott Teel struct CommandList *c) 369c349775eSScott Teel { 370c349775eSScott Teel if (c->cmd_type == CMD_IOACCEL2) 371c349775eSScott Teel writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 372c349775eSScott Teel else 373c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 374c349775eSScott Teel } 375c349775eSScott Teel 376edd16368SStephen M. Cameron /* 377edd16368SStephen M. Cameron * This card is the opposite of the other cards. 378edd16368SStephen M. Cameron * 0 turns interrupts on... 379edd16368SStephen M. Cameron * 0x08 turns them off... 380edd16368SStephen M. Cameron */ 381edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 382edd16368SStephen M. Cameron { 383edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 384edd16368SStephen M. Cameron h->interrupts_enabled = 1; 385edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 3868cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 387edd16368SStephen M. Cameron } else { /* Turn them off */ 388edd16368SStephen M. Cameron h->interrupts_enabled = 0; 389edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 390edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 3918cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 392edd16368SStephen M. Cameron } 393edd16368SStephen M. Cameron } 394303932fdSDon Brace 395303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 396303932fdSDon Brace { 397303932fdSDon Brace if (val) { /* turn on interrupts */ 398303932fdSDon Brace h->interrupts_enabled = 1; 399303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4008cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 401303932fdSDon Brace } else { 402303932fdSDon Brace h->interrupts_enabled = 0; 403303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 404303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4058cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 406303932fdSDon Brace } 407303932fdSDon Brace } 408303932fdSDon Brace 409254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 410303932fdSDon Brace { 411072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4120cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 413303932fdSDon Brace 4142c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 415bee266a6SDon Brace if (unlikely(!(h->msi_vector || h->msix_vector))) { 416303932fdSDon Brace /* flush the controller write of the reply queue by reading 417303932fdSDon Brace * outbound doorbell status register. 418303932fdSDon Brace */ 419bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 420303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 421303932fdSDon Brace /* Do a read in order to flush the write to the controller 422303932fdSDon Brace * (as per spec.) 423303932fdSDon Brace */ 424bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 425303932fdSDon Brace } 426303932fdSDon Brace 427bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 428254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 429254f796bSMatt Gates rq->current_entry++; 4300cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 431303932fdSDon Brace } else { 432303932fdSDon Brace register_value = FIFO_EMPTY; 433303932fdSDon Brace } 434303932fdSDon Brace /* Check for wraparound */ 435254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 436254f796bSMatt Gates rq->current_entry = 0; 437254f796bSMatt Gates rq->wraparound ^= 1; 438303932fdSDon Brace } 439303932fdSDon Brace return register_value; 440303932fdSDon Brace } 441303932fdSDon Brace 442edd16368SStephen M. Cameron /* 443edd16368SStephen M. Cameron * returns value read from hardware. 444edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 445edd16368SStephen M. Cameron */ 446254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 447254f796bSMatt Gates __attribute__((unused)) u8 q) 448edd16368SStephen M. Cameron { 449edd16368SStephen M. Cameron unsigned long register_value 450edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 451edd16368SStephen M. Cameron 4520cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 4530cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 454edd16368SStephen M. Cameron 455edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 456edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 45784ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 458edd16368SStephen M. Cameron register_value); 459edd16368SStephen M. Cameron else 460f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 461edd16368SStephen M. Cameron #endif 462edd16368SStephen M. Cameron 463edd16368SStephen M. Cameron return register_value; 464edd16368SStephen M. Cameron } 465edd16368SStephen M. Cameron /* 466edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 467edd16368SStephen M. Cameron */ 468900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 469edd16368SStephen M. Cameron { 470edd16368SStephen M. Cameron unsigned long register_value = 471edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 472900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 473edd16368SStephen M. Cameron } 474edd16368SStephen M. Cameron 475303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 476303932fdSDon Brace { 477303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 478303932fdSDon Brace 479303932fdSDon Brace if (!register_value) 480303932fdSDon Brace return false; 481303932fdSDon Brace 482303932fdSDon Brace if (h->msi_vector || h->msix_vector) 483303932fdSDon Brace return true; 484303932fdSDon Brace 485303932fdSDon Brace /* Read outbound doorbell to flush */ 486303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 487303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 488303932fdSDon Brace } 489edd16368SStephen M. Cameron 490e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 491e1f7de0cSMatt Gates 492e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 493e1f7de0cSMatt Gates { 494e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 495e1f7de0cSMatt Gates 496e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 497e1f7de0cSMatt Gates true : false; 498e1f7de0cSMatt Gates } 499e1f7de0cSMatt Gates 500e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 501e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 502e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 503e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 504e1f7de0cSMatt Gates 505283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 506e1f7de0cSMatt Gates { 507e1f7de0cSMatt Gates u64 register_value; 508072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 509e1f7de0cSMatt Gates 510e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 511e1f7de0cSMatt Gates 512e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 513e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 514e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 515e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 516e1f7de0cSMatt Gates rq->current_entry = 0; 517283b4a9bSStephen M. Cameron /* 518283b4a9bSStephen M. Cameron * @todo 519283b4a9bSStephen M. Cameron * 520283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 521283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 522283b4a9bSStephen M. Cameron */ 523283b4a9bSStephen M. Cameron wmb(); 524283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 525283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5260cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 527e1f7de0cSMatt Gates } 528e1f7de0cSMatt Gates return (unsigned long) register_value; 529e1f7de0cSMatt Gates } 530e1f7de0cSMatt Gates 531edd16368SStephen M. Cameron static struct access_method SA5_access = { 532edd16368SStephen M. Cameron SA5_submit_command, 533edd16368SStephen M. Cameron SA5_intr_mask, 534edd16368SStephen M. Cameron SA5_intr_pending, 535edd16368SStephen M. Cameron SA5_completed, 536edd16368SStephen M. Cameron }; 537edd16368SStephen M. Cameron 538e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 539e1f7de0cSMatt Gates SA5_submit_command, 540e1f7de0cSMatt Gates SA5_performant_intr_mask, 541e1f7de0cSMatt Gates SA5_ioaccel_mode1_intr_pending, 542e1f7de0cSMatt Gates SA5_ioaccel_mode1_completed, 543e1f7de0cSMatt Gates }; 544e1f7de0cSMatt Gates 545c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 546c349775eSScott Teel SA5_submit_command_ioaccel2, 547c349775eSScott Teel SA5_performant_intr_mask, 548c349775eSScott Teel SA5_performant_intr_pending, 549c349775eSScott Teel SA5_performant_completed, 550c349775eSScott Teel }; 551c349775eSScott Teel 552303932fdSDon Brace static struct access_method SA5_performant_access = { 553303932fdSDon Brace SA5_submit_command, 554303932fdSDon Brace SA5_performant_intr_mask, 555303932fdSDon Brace SA5_performant_intr_pending, 556303932fdSDon Brace SA5_performant_completed, 557303932fdSDon Brace }; 558303932fdSDon Brace 559b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 560b3a52e79SStephen M. Cameron SA5_submit_command_no_read, 561b3a52e79SStephen M. Cameron SA5_performant_intr_mask, 562b3a52e79SStephen M. Cameron SA5_performant_intr_pending, 563b3a52e79SStephen M. Cameron SA5_performant_completed, 564b3a52e79SStephen M. Cameron }; 565b3a52e79SStephen M. Cameron 566edd16368SStephen M. Cameron struct board_type { 56701a02ffcSStephen M. Cameron u32 board_id; 568edd16368SStephen M. Cameron char *product_name; 569edd16368SStephen M. Cameron struct access_method *access; 570edd16368SStephen M. Cameron }; 571edd16368SStephen M. Cameron 572edd16368SStephen M. Cameron #endif /* HPSA_H */ 573edd16368SStephen M. Cameron 574