1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 351c35139SScott Teel * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. 4edd16368SStephen M. Cameron * 5edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 6edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 7edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 8edd16368SStephen M. Cameron * 9edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 10edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 11edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 13edd16368SStephen M. Cameron * 14edd16368SStephen M. Cameron * You should have received a copy of the GNU General Public License 15edd16368SStephen M. Cameron * along with this program; if not, write to the Free Software 16edd16368SStephen M. Cameron * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17edd16368SStephen M. Cameron * 18edd16368SStephen M. Cameron * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19edd16368SStephen M. Cameron * 20edd16368SStephen M. Cameron */ 21edd16368SStephen M. Cameron #ifndef HPSA_H 22edd16368SStephen M. Cameron #define HPSA_H 23edd16368SStephen M. Cameron 24edd16368SStephen M. Cameron #include <scsi/scsicam.h> 25edd16368SStephen M. Cameron 26edd16368SStephen M. Cameron #define IO_OK 0 27edd16368SStephen M. Cameron #define IO_ERROR 1 28edd16368SStephen M. Cameron 29edd16368SStephen M. Cameron struct ctlr_info; 30edd16368SStephen M. Cameron 31edd16368SStephen M. Cameron struct access_method { 32edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 33edd16368SStephen M. Cameron struct CommandList *c); 34edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 35900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 36254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 37edd16368SStephen M. Cameron }; 38edd16368SStephen M. Cameron 39edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 40edd16368SStephen M. Cameron int devtype; 41edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 42edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 43edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 44edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 45edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 46edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 47edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 489846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 4903383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 5003383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 5103383736SDon Brace * counts commands sent to physical 5203383736SDon Brace * device via "ioaccel" path. 5303383736SDon Brace */ 54e1f7de0cSMatt Gates u32 ioaccel_handle; 55283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 56283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 5741ce4c35SStephen Cameron int offload_to_be_enabled; 58a3144e0bSJoe Handzik int hba_ioaccel_enabled; 59283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 60283b4a9bSStephen M. Cameron * offload request to mirror drive 61283b4a9bSStephen M. Cameron */ 62283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 63283b4a9bSStephen M. Cameron 6403383736SDon Brace /* 6503383736SDon Brace * Pointers from logical drive map indices to the phys drives that 6603383736SDon Brace * make those logical drives. Note, multiple logical drives may 6703383736SDon Brace * share physical drives. You can have for instance 5 physical 6803383736SDon Brace * drives with 3 logical drives each using those same 5 physical 6903383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 7003383736SDon Brace * devices in order to honor physical device queue depth limits. 7103383736SDon Brace */ 7203383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 739b5c48c2SStephen Cameron int supports_aborts; 7441ce4c35SStephen Cameron #define HPSA_DO_NOT_EXPOSE 0x0 7541ce4c35SStephen Cameron #define HPSA_SG_ATTACH 0x1 7641ce4c35SStephen Cameron #define HPSA_ULD_ATTACH 0x2 7741ce4c35SStephen Cameron #define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH) 7841ce4c35SStephen Cameron u8 expose_state; 79edd16368SStephen M. Cameron }; 80edd16368SStephen M. Cameron 81072b0518SStephen M. Cameron struct reply_queue_buffer { 82254f796bSMatt Gates u64 *head; 83254f796bSMatt Gates size_t size; 84254f796bSMatt Gates u8 wraparound; 85254f796bSMatt Gates u32 current_entry; 86072b0518SStephen M. Cameron dma_addr_t busaddr; 87254f796bSMatt Gates }; 88254f796bSMatt Gates 89316b221aSStephen M. Cameron #pragma pack(1) 90316b221aSStephen M. Cameron struct bmic_controller_parameters { 91316b221aSStephen M. Cameron u8 led_flags; 92316b221aSStephen M. Cameron u8 enable_command_list_verification; 93316b221aSStephen M. Cameron u8 backed_out_write_drives; 94316b221aSStephen M. Cameron u16 stripes_for_parity; 95316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 96316b221aSStephen M. Cameron u16 max_driver_requests; 97316b221aSStephen M. Cameron u16 elevator_trend_count; 98316b221aSStephen M. Cameron u8 disable_elevator; 99316b221aSStephen M. Cameron u8 force_scan_complete; 100316b221aSStephen M. Cameron u8 scsi_transfer_mode; 101316b221aSStephen M. Cameron u8 force_narrow; 102316b221aSStephen M. Cameron u8 rebuild_priority; 103316b221aSStephen M. Cameron u8 expand_priority; 104316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 105316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 106316b221aSStephen M. Cameron char software_name[64]; 107316b221aSStephen M. Cameron char hardware_name[32]; 108316b221aSStephen M. Cameron u8 bridge_revision; 109316b221aSStephen M. Cameron u8 snapshot_priority; 110316b221aSStephen M. Cameron u32 os_specific; 111316b221aSStephen M. Cameron u8 post_prompt_timeout; 112316b221aSStephen M. Cameron u8 automatic_drive_slamming; 113316b221aSStephen M. Cameron u8 reserved1; 114316b221aSStephen M. Cameron u8 nvram_flags; 1156e8e8088SJoe Handzik #define HBA_MODE_ENABLED_FLAG (1 << 3) 116316b221aSStephen M. Cameron u8 cache_nvram_flags; 117316b221aSStephen M. Cameron u8 drive_config_flags; 118316b221aSStephen M. Cameron u16 reserved2; 119316b221aSStephen M. Cameron u8 temp_warning_level; 120316b221aSStephen M. Cameron u8 temp_shutdown_level; 121316b221aSStephen M. Cameron u8 temp_condition_reset; 122316b221aSStephen M. Cameron u8 max_coalesce_commands; 123316b221aSStephen M. Cameron u32 max_coalesce_delay; 124316b221aSStephen M. Cameron u8 orca_password[4]; 125316b221aSStephen M. Cameron u8 access_id[16]; 126316b221aSStephen M. Cameron u8 reserved[356]; 127316b221aSStephen M. Cameron }; 128316b221aSStephen M. Cameron #pragma pack() 129316b221aSStephen M. Cameron 130edd16368SStephen M. Cameron struct ctlr_info { 131edd16368SStephen M. Cameron int ctlr; 132edd16368SStephen M. Cameron char devname[8]; 133edd16368SStephen M. Cameron char *product_name; 134edd16368SStephen M. Cameron struct pci_dev *pdev; 13501a02ffcSStephen M. Cameron u32 board_id; 136edd16368SStephen M. Cameron void __iomem *vaddr; 137edd16368SStephen M. Cameron unsigned long paddr; 138edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 139d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 140d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 141edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 142edd16368SStephen M. Cameron int interrupts_enabled; 143edd16368SStephen M. Cameron int max_commands; 14433811026SRobert Elliott int last_allocation; 1450cbf768eSStephen M. Cameron atomic_t commands_outstanding; 146303932fdSDon Brace # define PERF_MODE_INT 0 147303932fdSDon Brace # define DOORBELL_INT 1 148edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 149edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 150254f796bSMatt Gates unsigned int intr[MAX_REPLY_QUEUES]; 151edd16368SStephen M. Cameron unsigned int msix_vector; 152edd16368SStephen M. Cameron unsigned int msi_vector; 153a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 154edd16368SStephen M. Cameron struct access_method access; 155316b221aSStephen M. Cameron char hba_mode_enabled; 156edd16368SStephen M. Cameron 157edd16368SStephen M. Cameron /* queue and queue Info */ 158edd16368SStephen M. Cameron unsigned int Qdepth; 159edd16368SStephen M. Cameron unsigned int maxSG; 160edd16368SStephen M. Cameron spinlock_t lock; 16133a2ffceSStephen M. Cameron int maxsgentries; 16233a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 16333a2ffceSStephen M. Cameron int chainsize; 16433a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 165edd16368SStephen M. Cameron 166edd16368SStephen M. Cameron /* pointers to command and error info pool */ 167edd16368SStephen M. Cameron struct CommandList *cmd_pool; 168edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 169e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 170e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 171aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 172aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 173edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 174edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 175edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 176a08a8471SStephen M. Cameron int scan_finished; 177a08a8471SStephen M. Cameron spinlock_t scan_lock; 178a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 179edd16368SStephen M. Cameron 180edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 181edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 182edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 183cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 184303932fdSDon Brace /* 185303932fdSDon Brace * Performant mode tables. 186303932fdSDon Brace */ 187303932fdSDon Brace u32 trans_support; 188303932fdSDon Brace u32 trans_offset; 18942a91641SDon Brace struct TransTable_struct __iomem *transtable; 190303932fdSDon Brace unsigned long transMethod; 191303932fdSDon Brace 1920390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 19345fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 19434f0c627SDon Brace atomic_t passthru_cmds_avail; 1950390f0c0SStephen M. Cameron 196303932fdSDon Brace /* 197254f796bSMatt Gates * Performant mode completion buffers 198303932fdSDon Brace */ 199072b0518SStephen M. Cameron size_t reply_queue_size; 200072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 201254f796bSMatt Gates u8 nreply_queues; 202303932fdSDon Brace u32 *blockFetchTable; 203e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 204aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 20542a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 206339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 207283b4a9bSStephen M. Cameron u32 driver_support; 208283b4a9bSStephen M. Cameron u32 fw_support; 209283b4a9bSStephen M. Cameron int ioaccel_support; 210283b4a9bSStephen M. Cameron int ioaccel_maxsg; 211a0c12413SStephen M. Cameron u64 last_intr_timestamp; 212a0c12413SStephen M. Cameron u32 last_heartbeat; 213a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 214e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 215e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 21642a91641SDon Brace u32 __percpu *lockup_detected; 2178a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2186636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2198a98db73SStephen M. Cameron int remove_in_progress; 220254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 221254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 22275167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 22375167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 22475167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 22575167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 22675167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 22775167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 22875167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 22975167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 23075167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 23175167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 23275167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 23375167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 23475167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 23575167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 23675167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 23775167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 23875167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 23975167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 24075167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 24175167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 24275167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 24376438d08SStephen M. Cameron u32 events; 244faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 245faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 246faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 247faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 248faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 249faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 250faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 251faff6ee0SStephen M. Cameron 252faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2537b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 254faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 255faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 256faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 257faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2589846590eSStephen M. Cameron spinlock_t offline_device_lock; 2599846590eSStephen M. Cameron struct list_head offline_device_list; 260da0697bdSScott Teel int acciopath_status; 2612ba8bfc8SStephen M. Cameron int raid_offload_debug; 2629b5c48c2SStephen Cameron int needs_abort_tags_swizzled; 263080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 2646636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 2659b5c48c2SStephen Cameron atomic_t abort_cmds_available; 2669b5c48c2SStephen Cameron wait_queue_head_t abort_cmd_wait_queue; 267edd16368SStephen M. Cameron }; 2689846590eSStephen M. Cameron 2699846590eSStephen M. Cameron struct offline_device_entry { 2709846590eSStephen M. Cameron unsigned char scsi3addr[8]; 2719846590eSStephen M. Cameron struct list_head offline_list; 2729846590eSStephen M. Cameron }; 2739846590eSStephen M. Cameron 274edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 275edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 27664670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 27764670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 27864670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_TARGET 0x03 27964670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 280edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 281516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 282edd16368SStephen M. Cameron 283edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 284edd16368SStephen M. Cameron * when polling before giving up. 285edd16368SStephen M. Cameron */ 286edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 287edd16368SStephen M. Cameron 288edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 289edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 290edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 291edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 292edd16368SStephen M. Cameron * between sending TURs while waiting for a device 293edd16368SStephen M. Cameron * to become ready. 294edd16368SStephen M. Cameron */ 295edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 296edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 297edd16368SStephen M. Cameron 298edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 299edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 300edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 301edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 302edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 303edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 304edd16368SStephen M. Cameron */ 305edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3062ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 307edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 308edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 309edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 310edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 311edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 312edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 313fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 314fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 315fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 316edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 317edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 318edd16368SStephen M. Cameron 319edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 320edd16368SStephen M. Cameron /* 321edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 322edd16368SStephen M. Cameron */ 323edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 324edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 325281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 326281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 327edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 328edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 329edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 330edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 331edd16368SStephen M. Cameron 332edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 333edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 334edd16368SStephen M. Cameron 335edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 336edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 337edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 338edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 339edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 340edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 341edd16368SStephen M. Cameron 342edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 343edd16368SStephen M. Cameron 344303932fdSDon Brace /* Performant mode flags */ 345303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 346303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 347303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 348303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 349303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 350303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 351303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 352303932fdSDon Brace 353303932fdSDon Brace 354edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 355edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 356b66cc250SMike Miller 357b66cc250SMike Miller /* 358b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 359b66cc250SMike Miller */ 360b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 361b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 362b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 363b66cc250SMike Miller 364edd16368SStephen M. Cameron /* 365edd16368SStephen M. Cameron Send the command to the hardware 366edd16368SStephen M. Cameron */ 367edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 368edd16368SStephen M. Cameron struct CommandList *c) 369edd16368SStephen M. Cameron { 370edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 371fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 372edd16368SStephen M. Cameron } 373edd16368SStephen M. Cameron 374b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 375b3a52e79SStephen M. Cameron struct CommandList *c) 376b3a52e79SStephen M. Cameron { 377b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 378b3a52e79SStephen M. Cameron } 379b3a52e79SStephen M. Cameron 380c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 381c349775eSScott Teel struct CommandList *c) 382c349775eSScott Teel { 383c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 384c349775eSScott Teel } 385c349775eSScott Teel 386edd16368SStephen M. Cameron /* 387edd16368SStephen M. Cameron * This card is the opposite of the other cards. 388edd16368SStephen M. Cameron * 0 turns interrupts on... 389edd16368SStephen M. Cameron * 0x08 turns them off... 390edd16368SStephen M. Cameron */ 391edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 392edd16368SStephen M. Cameron { 393edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 394edd16368SStephen M. Cameron h->interrupts_enabled = 1; 395edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 3968cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 397edd16368SStephen M. Cameron } else { /* Turn them off */ 398edd16368SStephen M. Cameron h->interrupts_enabled = 0; 399edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 400edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4018cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 402edd16368SStephen M. Cameron } 403edd16368SStephen M. Cameron } 404303932fdSDon Brace 405303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 406303932fdSDon Brace { 407303932fdSDon Brace if (val) { /* turn on interrupts */ 408303932fdSDon Brace h->interrupts_enabled = 1; 409303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4108cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 411303932fdSDon Brace } else { 412303932fdSDon Brace h->interrupts_enabled = 0; 413303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 414303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4158cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 416303932fdSDon Brace } 417303932fdSDon Brace } 418303932fdSDon Brace 419254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 420303932fdSDon Brace { 421072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4220cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 423303932fdSDon Brace 4242c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 425bee266a6SDon Brace if (unlikely(!(h->msi_vector || h->msix_vector))) { 426303932fdSDon Brace /* flush the controller write of the reply queue by reading 427303932fdSDon Brace * outbound doorbell status register. 428303932fdSDon Brace */ 429bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 430303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 431303932fdSDon Brace /* Do a read in order to flush the write to the controller 432303932fdSDon Brace * (as per spec.) 433303932fdSDon Brace */ 434bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 435303932fdSDon Brace } 436303932fdSDon Brace 437bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 438254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 439254f796bSMatt Gates rq->current_entry++; 4400cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 441303932fdSDon Brace } else { 442303932fdSDon Brace register_value = FIFO_EMPTY; 443303932fdSDon Brace } 444303932fdSDon Brace /* Check for wraparound */ 445254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 446254f796bSMatt Gates rq->current_entry = 0; 447254f796bSMatt Gates rq->wraparound ^= 1; 448303932fdSDon Brace } 449303932fdSDon Brace return register_value; 450303932fdSDon Brace } 451303932fdSDon Brace 452edd16368SStephen M. Cameron /* 453edd16368SStephen M. Cameron * returns value read from hardware. 454edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 455edd16368SStephen M. Cameron */ 456254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 457254f796bSMatt Gates __attribute__((unused)) u8 q) 458edd16368SStephen M. Cameron { 459edd16368SStephen M. Cameron unsigned long register_value 460edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 461edd16368SStephen M. Cameron 4620cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 4630cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 464edd16368SStephen M. Cameron 465edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 466edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 46784ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 468edd16368SStephen M. Cameron register_value); 469edd16368SStephen M. Cameron else 470f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 471edd16368SStephen M. Cameron #endif 472edd16368SStephen M. Cameron 473edd16368SStephen M. Cameron return register_value; 474edd16368SStephen M. Cameron } 475edd16368SStephen M. Cameron /* 476edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 477edd16368SStephen M. Cameron */ 478900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 479edd16368SStephen M. Cameron { 480edd16368SStephen M. Cameron unsigned long register_value = 481edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 482900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 483edd16368SStephen M. Cameron } 484edd16368SStephen M. Cameron 485303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 486303932fdSDon Brace { 487303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 488303932fdSDon Brace 489303932fdSDon Brace if (!register_value) 490303932fdSDon Brace return false; 491303932fdSDon Brace 492303932fdSDon Brace /* Read outbound doorbell to flush */ 493303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 494303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 495303932fdSDon Brace } 496edd16368SStephen M. Cameron 497e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 498e1f7de0cSMatt Gates 499e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 500e1f7de0cSMatt Gates { 501e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 502e1f7de0cSMatt Gates 503e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 504e1f7de0cSMatt Gates true : false; 505e1f7de0cSMatt Gates } 506e1f7de0cSMatt Gates 507e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 508e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 509e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 510e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 511e1f7de0cSMatt Gates 512283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 513e1f7de0cSMatt Gates { 514e1f7de0cSMatt Gates u64 register_value; 515072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 516e1f7de0cSMatt Gates 517e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 518e1f7de0cSMatt Gates 519e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 520e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 521e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 522e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 523e1f7de0cSMatt Gates rq->current_entry = 0; 524283b4a9bSStephen M. Cameron /* 525283b4a9bSStephen M. Cameron * @todo 526283b4a9bSStephen M. Cameron * 527283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 528283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 529283b4a9bSStephen M. Cameron */ 530283b4a9bSStephen M. Cameron wmb(); 531283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 532283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5330cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 534e1f7de0cSMatt Gates } 535e1f7de0cSMatt Gates return (unsigned long) register_value; 536e1f7de0cSMatt Gates } 537e1f7de0cSMatt Gates 538edd16368SStephen M. Cameron static struct access_method SA5_access = { 539edd16368SStephen M. Cameron SA5_submit_command, 540edd16368SStephen M. Cameron SA5_intr_mask, 541edd16368SStephen M. Cameron SA5_intr_pending, 542edd16368SStephen M. Cameron SA5_completed, 543edd16368SStephen M. Cameron }; 544edd16368SStephen M. Cameron 545e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 546e1f7de0cSMatt Gates SA5_submit_command, 547e1f7de0cSMatt Gates SA5_performant_intr_mask, 548e1f7de0cSMatt Gates SA5_ioaccel_mode1_intr_pending, 549e1f7de0cSMatt Gates SA5_ioaccel_mode1_completed, 550e1f7de0cSMatt Gates }; 551e1f7de0cSMatt Gates 552c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 553c349775eSScott Teel SA5_submit_command_ioaccel2, 554c349775eSScott Teel SA5_performant_intr_mask, 555c349775eSScott Teel SA5_performant_intr_pending, 556c349775eSScott Teel SA5_performant_completed, 557c349775eSScott Teel }; 558c349775eSScott Teel 559303932fdSDon Brace static struct access_method SA5_performant_access = { 560303932fdSDon Brace SA5_submit_command, 561303932fdSDon Brace SA5_performant_intr_mask, 562303932fdSDon Brace SA5_performant_intr_pending, 563303932fdSDon Brace SA5_performant_completed, 564303932fdSDon Brace }; 565303932fdSDon Brace 566b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 567b3a52e79SStephen M. Cameron SA5_submit_command_no_read, 568b3a52e79SStephen M. Cameron SA5_performant_intr_mask, 569b3a52e79SStephen M. Cameron SA5_performant_intr_pending, 570b3a52e79SStephen M. Cameron SA5_performant_completed, 571b3a52e79SStephen M. Cameron }; 572b3a52e79SStephen M. Cameron 573edd16368SStephen M. Cameron struct board_type { 57401a02ffcSStephen M. Cameron u32 board_id; 575edd16368SStephen M. Cameron char *product_name; 576edd16368SStephen M. Cameron struct access_method *access; 577edd16368SStephen M. Cameron }; 578edd16368SStephen M. Cameron 579edd16368SStephen M. Cameron #endif /* HPSA_H */ 580edd16368SStephen M. Cameron 581