1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 394c7bc31SDon Brace * Copyright 2016 Microsemi Corporation 41358f6dcSDon Brace * Copyright 2014-2015 PMC-Sierra, Inc. 51358f6dcSDon Brace * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6edd16368SStephen M. Cameron * 7edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 8edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 9edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 10edd16368SStephen M. Cameron * 11edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 12edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 13edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 15edd16368SStephen M. Cameron * 1694c7bc31SDon Brace * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17edd16368SStephen M. Cameron * 18edd16368SStephen M. Cameron */ 19edd16368SStephen M. Cameron #ifndef HPSA_H 20edd16368SStephen M. Cameron #define HPSA_H 21edd16368SStephen M. Cameron 22edd16368SStephen M. Cameron #include <scsi/scsicam.h> 23edd16368SStephen M. Cameron 24edd16368SStephen M. Cameron #define IO_OK 0 25edd16368SStephen M. Cameron #define IO_ERROR 1 26edd16368SStephen M. Cameron 27edd16368SStephen M. Cameron struct ctlr_info; 28edd16368SStephen M. Cameron 29edd16368SStephen M. Cameron struct access_method { 30edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 31edd16368SStephen M. Cameron struct CommandList *c); 32edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 33900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 34254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 35edd16368SStephen M. Cameron }; 36edd16368SStephen M. Cameron 37d04e62b9SKevin Barnett /* for SAS hosts and SAS expanders */ 38d04e62b9SKevin Barnett struct hpsa_sas_node { 39d04e62b9SKevin Barnett struct device *parent_dev; 40d04e62b9SKevin Barnett struct list_head port_list_head; 41d04e62b9SKevin Barnett }; 42d04e62b9SKevin Barnett 43d04e62b9SKevin Barnett struct hpsa_sas_port { 44d04e62b9SKevin Barnett struct list_head port_list_entry; 45d04e62b9SKevin Barnett u64 sas_address; 46d04e62b9SKevin Barnett struct sas_port *port; 47d04e62b9SKevin Barnett int next_phy_index; 48d04e62b9SKevin Barnett struct list_head phy_list_head; 49d04e62b9SKevin Barnett struct hpsa_sas_node *parent_node; 50d04e62b9SKevin Barnett struct sas_rphy *rphy; 51d04e62b9SKevin Barnett }; 52d04e62b9SKevin Barnett 53d04e62b9SKevin Barnett struct hpsa_sas_phy { 54d04e62b9SKevin Barnett struct list_head phy_list_entry; 55d04e62b9SKevin Barnett struct sas_phy *phy; 56d04e62b9SKevin Barnett struct hpsa_sas_port *parent_port; 57d04e62b9SKevin Barnett bool added_to_port; 58d04e62b9SKevin Barnett }; 59d04e62b9SKevin Barnett 60edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 613ad7de6bSDon Brace unsigned int devtype; 62edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 63edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 6404fa2f44SKevin Barnett u8 physical_device : 1; 652a168208SKevin Barnett u8 expose_device; 66ba74fdc4SDon Brace u8 removed : 1; /* device is marked for death */ 67edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 68edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 69d04e62b9SKevin Barnett u64 sas_address; 70edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 71edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 727630b3a5SHannes Reinecke unsigned char rev; /* byte 2 of inquiry data */ 73edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 749846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 7503383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 76d604f533SWebb Scales atomic_t reset_cmds_out; /* Count of commands to-be affected */ 7703383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 7803383736SDon Brace * counts commands sent to physical 7903383736SDon Brace * device via "ioaccel" path. 8003383736SDon Brace */ 81e1f7de0cSMatt Gates u32 ioaccel_handle; 828270b862SJoe Handzik u8 active_path_index; 838270b862SJoe Handzik u8 path_map; 848270b862SJoe Handzik u8 bay; 858270b862SJoe Handzik u8 box[8]; 868270b862SJoe Handzik u16 phys_connector[8]; 87283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 88283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 8941ce4c35SStephen Cameron int offload_to_be_enabled; 90a3144e0bSJoe Handzik int hba_ioaccel_enabled; 91283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 92283b4a9bSStephen M. Cameron * offload request to mirror drive 93283b4a9bSStephen M. Cameron */ 94283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 95283b4a9bSStephen M. Cameron 9603383736SDon Brace /* 9703383736SDon Brace * Pointers from logical drive map indices to the phys drives that 9803383736SDon Brace * make those logical drives. Note, multiple logical drives may 9903383736SDon Brace * share physical drives. You can have for instance 5 physical 10003383736SDon Brace * drives with 3 logical drives each using those same 5 physical 10103383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 10203383736SDon Brace * devices in order to honor physical device queue depth limits. 10303383736SDon Brace */ 10403383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 105d604f533SWebb Scales int nphysical_disks; 1069b5c48c2SStephen Cameron int supports_aborts; 107d04e62b9SKevin Barnett struct hpsa_sas_port *sas_port; 10866749d0dSScott Teel int external; /* 1-from external array 0-not <0-unknown */ 109edd16368SStephen M. Cameron }; 110edd16368SStephen M. Cameron 111072b0518SStephen M. Cameron struct reply_queue_buffer { 112254f796bSMatt Gates u64 *head; 113254f796bSMatt Gates size_t size; 114254f796bSMatt Gates u8 wraparound; 115254f796bSMatt Gates u32 current_entry; 116072b0518SStephen M. Cameron dma_addr_t busaddr; 117254f796bSMatt Gates }; 118254f796bSMatt Gates 119316b221aSStephen M. Cameron #pragma pack(1) 120316b221aSStephen M. Cameron struct bmic_controller_parameters { 121316b221aSStephen M. Cameron u8 led_flags; 122316b221aSStephen M. Cameron u8 enable_command_list_verification; 123316b221aSStephen M. Cameron u8 backed_out_write_drives; 124316b221aSStephen M. Cameron u16 stripes_for_parity; 125316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 126316b221aSStephen M. Cameron u16 max_driver_requests; 127316b221aSStephen M. Cameron u16 elevator_trend_count; 128316b221aSStephen M. Cameron u8 disable_elevator; 129316b221aSStephen M. Cameron u8 force_scan_complete; 130316b221aSStephen M. Cameron u8 scsi_transfer_mode; 131316b221aSStephen M. Cameron u8 force_narrow; 132316b221aSStephen M. Cameron u8 rebuild_priority; 133316b221aSStephen M. Cameron u8 expand_priority; 134316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 135316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 136316b221aSStephen M. Cameron char software_name[64]; 137316b221aSStephen M. Cameron char hardware_name[32]; 138316b221aSStephen M. Cameron u8 bridge_revision; 139316b221aSStephen M. Cameron u8 snapshot_priority; 140316b221aSStephen M. Cameron u32 os_specific; 141316b221aSStephen M. Cameron u8 post_prompt_timeout; 142316b221aSStephen M. Cameron u8 automatic_drive_slamming; 143316b221aSStephen M. Cameron u8 reserved1; 144316b221aSStephen M. Cameron u8 nvram_flags; 145316b221aSStephen M. Cameron u8 cache_nvram_flags; 146316b221aSStephen M. Cameron u8 drive_config_flags; 147316b221aSStephen M. Cameron u16 reserved2; 148316b221aSStephen M. Cameron u8 temp_warning_level; 149316b221aSStephen M. Cameron u8 temp_shutdown_level; 150316b221aSStephen M. Cameron u8 temp_condition_reset; 151316b221aSStephen M. Cameron u8 max_coalesce_commands; 152316b221aSStephen M. Cameron u32 max_coalesce_delay; 153316b221aSStephen M. Cameron u8 orca_password[4]; 154316b221aSStephen M. Cameron u8 access_id[16]; 155316b221aSStephen M. Cameron u8 reserved[356]; 156316b221aSStephen M. Cameron }; 157316b221aSStephen M. Cameron #pragma pack() 158316b221aSStephen M. Cameron 159edd16368SStephen M. Cameron struct ctlr_info { 160edd16368SStephen M. Cameron int ctlr; 161edd16368SStephen M. Cameron char devname[8]; 162edd16368SStephen M. Cameron char *product_name; 163edd16368SStephen M. Cameron struct pci_dev *pdev; 16401a02ffcSStephen M. Cameron u32 board_id; 165d04e62b9SKevin Barnett u64 sas_address; 166edd16368SStephen M. Cameron void __iomem *vaddr; 167edd16368SStephen M. Cameron unsigned long paddr; 168edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 169d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 170d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 171edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 172edd16368SStephen M. Cameron int interrupts_enabled; 173edd16368SStephen M. Cameron int max_commands; 1740cbf768eSStephen M. Cameron atomic_t commands_outstanding; 175303932fdSDon Brace # define PERF_MODE_INT 0 176303932fdSDon Brace # define DOORBELL_INT 1 177edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 178edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 179bc2bb154SChristoph Hellwig unsigned int msix_vectors; 180a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 181edd16368SStephen M. Cameron struct access_method access; 182edd16368SStephen M. Cameron 183edd16368SStephen M. Cameron /* queue and queue Info */ 184edd16368SStephen M. Cameron unsigned int Qdepth; 185edd16368SStephen M. Cameron unsigned int maxSG; 186edd16368SStephen M. Cameron spinlock_t lock; 18733a2ffceSStephen M. Cameron int maxsgentries; 18833a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 18933a2ffceSStephen M. Cameron int chainsize; 19033a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 191d9a729f3SWebb Scales struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; 192edd16368SStephen M. Cameron 193edd16368SStephen M. Cameron /* pointers to command and error info pool */ 194edd16368SStephen M. Cameron struct CommandList *cmd_pool; 195edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 196e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 197e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 198aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 199aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 200edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 201edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 202edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 203a08a8471SStephen M. Cameron int scan_finished; 20487b9e6aaSDon Brace u8 scan_waiting : 1; 205a08a8471SStephen M. Cameron spinlock_t scan_lock; 206a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 207edd16368SStephen M. Cameron 208edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 209edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 210edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 211cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 212303932fdSDon Brace /* 213303932fdSDon Brace * Performant mode tables. 214303932fdSDon Brace */ 215303932fdSDon Brace u32 trans_support; 216303932fdSDon Brace u32 trans_offset; 21742a91641SDon Brace struct TransTable_struct __iomem *transtable; 218303932fdSDon Brace unsigned long transMethod; 219303932fdSDon Brace 2200390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 22145fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 22234f0c627SDon Brace atomic_t passthru_cmds_avail; 2230390f0c0SStephen M. Cameron 224303932fdSDon Brace /* 225254f796bSMatt Gates * Performant mode completion buffers 226303932fdSDon Brace */ 227072b0518SStephen M. Cameron size_t reply_queue_size; 228072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 229254f796bSMatt Gates u8 nreply_queues; 230303932fdSDon Brace u32 *blockFetchTable; 231e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 232aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 23342a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 234339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 235283b4a9bSStephen M. Cameron u32 driver_support; 236283b4a9bSStephen M. Cameron u32 fw_support; 237283b4a9bSStephen M. Cameron int ioaccel_support; 238283b4a9bSStephen M. Cameron int ioaccel_maxsg; 239a0c12413SStephen M. Cameron u64 last_intr_timestamp; 240a0c12413SStephen M. Cameron u32 last_heartbeat; 241a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 242e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 243e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 24442a91641SDon Brace u32 __percpu *lockup_detected; 2458a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2466636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2478a98db73SStephen M. Cameron int remove_in_progress; 248254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 249254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 2508b47004aSRobert Elliott char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ 25175167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 25275167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 25375167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 25475167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 25575167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 25675167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 25775167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 25875167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 25975167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 26075167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 26175167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 2628be986ccSStephen Cameron #define HPSATMF_IOACCEL_ENABLED (1 << 15) 26375167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 26475167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 26575167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 26675167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 26775167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 26875167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 26975167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 27075167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 27175167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 27275167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 27376438d08SStephen M. Cameron u32 events; 274faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 275faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 276faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 277faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 278faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 279faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 280faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 281faff6ee0SStephen M. Cameron 282faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2837b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 284faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 285faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 286faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 287faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2889846590eSStephen M. Cameron spinlock_t offline_device_lock; 2899846590eSStephen M. Cameron struct list_head offline_device_list; 290da0697bdSScott Teel int acciopath_status; 291853633e8SDon Brace int drv_req_rescan; 2922ba8bfc8SStephen M. Cameron int raid_offload_debug; 29334592254SScott Teel int discovery_polling; 29434592254SScott Teel struct ReportLUNdata *lastlogicals; 2959b5c48c2SStephen Cameron int needs_abort_tags_swizzled; 296080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 2976636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 2989b5c48c2SStephen Cameron atomic_t abort_cmds_available; 2999b5c48c2SStephen Cameron wait_queue_head_t abort_cmd_wait_queue; 300d604f533SWebb Scales wait_queue_head_t event_sync_wait_queue; 301d604f533SWebb Scales struct mutex reset_mutex; 302da03ded0SDon Brace u8 reset_in_progress; 303d04e62b9SKevin Barnett struct hpsa_sas_node *sas_host; 304edd16368SStephen M. Cameron }; 3059846590eSStephen M. Cameron 3069846590eSStephen M. Cameron struct offline_device_entry { 3079846590eSStephen M. Cameron unsigned char scsi3addr[8]; 3089846590eSStephen M. Cameron struct list_head offline_list; 3099846590eSStephen M. Cameron }; 3109846590eSStephen M. Cameron 311edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 312edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 31364670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 31464670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 31564670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 3160b9b7b6eSScott Teel #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ 317edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 318516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 319edd16368SStephen M. Cameron 320edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 321edd16368SStephen M. Cameron * when polling before giving up. 322edd16368SStephen M. Cameron */ 323edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 324edd16368SStephen M. Cameron 325edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 326edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 327edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 328edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 329edd16368SStephen M. Cameron * between sending TURs while waiting for a device 330edd16368SStephen M. Cameron * to become ready. 331edd16368SStephen M. Cameron */ 332edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 333edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 334edd16368SStephen M. Cameron 335edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 336edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 337edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 338edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 339edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 340edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 341edd16368SStephen M. Cameron */ 342edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3432ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 344edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 345edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 346edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 347edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 348edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 349edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 350fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 351fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 352fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 353edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 354edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 355edd16368SStephen M. Cameron 356edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 357edd16368SStephen M. Cameron /* 358edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 359edd16368SStephen M. Cameron */ 360edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 361edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 362281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 363281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 364edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 365edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 366edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 367edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 368edd16368SStephen M. Cameron 369edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 370edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 371edd16368SStephen M. Cameron 372edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 373edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 374edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 375edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 376edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 377edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 378edd16368SStephen M. Cameron 379edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 380edd16368SStephen M. Cameron 381303932fdSDon Brace /* Performant mode flags */ 382303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 383303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 384303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 385303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 386303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 387303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 388303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 389303932fdSDon Brace 390303932fdSDon Brace 391edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 392edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 393b66cc250SMike Miller 394b66cc250SMike Miller /* 395b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 396b66cc250SMike Miller */ 397b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 398b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 399b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 400b66cc250SMike Miller 401c795505aSKevin Barnett #define HPSA_PHYSICAL_DEVICE_BUS 0 402c795505aSKevin Barnett #define HPSA_RAID_VOLUME_BUS 1 403c795505aSKevin Barnett #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 40409371d62SDon Brace #define HPSA_HBA_BUS 0 4057630b3a5SHannes Reinecke #define HPSA_LEGACY_HBA_BUS 3 406c795505aSKevin Barnett 407edd16368SStephen M. Cameron /* 408edd16368SStephen M. Cameron Send the command to the hardware 409edd16368SStephen M. Cameron */ 410edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 411edd16368SStephen M. Cameron struct CommandList *c) 412edd16368SStephen M. Cameron { 413edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 414fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 415edd16368SStephen M. Cameron } 416edd16368SStephen M. Cameron 417b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 418b3a52e79SStephen M. Cameron struct CommandList *c) 419b3a52e79SStephen M. Cameron { 420b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 421b3a52e79SStephen M. Cameron } 422b3a52e79SStephen M. Cameron 423c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 424c349775eSScott Teel struct CommandList *c) 425c349775eSScott Teel { 426c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 427c349775eSScott Teel } 428c349775eSScott Teel 429edd16368SStephen M. Cameron /* 430edd16368SStephen M. Cameron * This card is the opposite of the other cards. 431edd16368SStephen M. Cameron * 0 turns interrupts on... 432edd16368SStephen M. Cameron * 0x08 turns them off... 433edd16368SStephen M. Cameron */ 434edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 435edd16368SStephen M. Cameron { 436edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 437edd16368SStephen M. Cameron h->interrupts_enabled = 1; 438edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4398cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 440edd16368SStephen M. Cameron } else { /* Turn them off */ 441edd16368SStephen M. Cameron h->interrupts_enabled = 0; 442edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 443edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4448cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 445edd16368SStephen M. Cameron } 446edd16368SStephen M. Cameron } 447303932fdSDon Brace 448303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 449303932fdSDon Brace { 450303932fdSDon Brace if (val) { /* turn on interrupts */ 451303932fdSDon Brace h->interrupts_enabled = 1; 452303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4538cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 454303932fdSDon Brace } else { 455303932fdSDon Brace h->interrupts_enabled = 0; 456303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 457303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4588cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 459303932fdSDon Brace } 460303932fdSDon Brace } 461303932fdSDon Brace 462254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 463303932fdSDon Brace { 464072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4650cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 466303932fdSDon Brace 4672c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 468bc2bb154SChristoph Hellwig if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) { 469303932fdSDon Brace /* flush the controller write of the reply queue by reading 470303932fdSDon Brace * outbound doorbell status register. 471303932fdSDon Brace */ 472bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 473303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 474303932fdSDon Brace /* Do a read in order to flush the write to the controller 475303932fdSDon Brace * (as per spec.) 476303932fdSDon Brace */ 477bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 478303932fdSDon Brace } 479303932fdSDon Brace 480bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 481254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 482254f796bSMatt Gates rq->current_entry++; 4830cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 484303932fdSDon Brace } else { 485303932fdSDon Brace register_value = FIFO_EMPTY; 486303932fdSDon Brace } 487303932fdSDon Brace /* Check for wraparound */ 488254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 489254f796bSMatt Gates rq->current_entry = 0; 490254f796bSMatt Gates rq->wraparound ^= 1; 491303932fdSDon Brace } 492303932fdSDon Brace return register_value; 493303932fdSDon Brace } 494303932fdSDon Brace 495edd16368SStephen M. Cameron /* 496edd16368SStephen M. Cameron * returns value read from hardware. 497edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 498edd16368SStephen M. Cameron */ 499254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 500254f796bSMatt Gates __attribute__((unused)) u8 q) 501edd16368SStephen M. Cameron { 502edd16368SStephen M. Cameron unsigned long register_value 503edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 504edd16368SStephen M. Cameron 5050cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 5060cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 507edd16368SStephen M. Cameron 508edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 509edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 51084ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 511edd16368SStephen M. Cameron register_value); 512edd16368SStephen M. Cameron else 513f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 514edd16368SStephen M. Cameron #endif 515edd16368SStephen M. Cameron 516edd16368SStephen M. Cameron return register_value; 517edd16368SStephen M. Cameron } 518edd16368SStephen M. Cameron /* 519edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 520edd16368SStephen M. Cameron */ 521900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 522edd16368SStephen M. Cameron { 523edd16368SStephen M. Cameron unsigned long register_value = 524edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 525900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 526edd16368SStephen M. Cameron } 527edd16368SStephen M. Cameron 528303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 529303932fdSDon Brace { 530303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 531303932fdSDon Brace 532303932fdSDon Brace if (!register_value) 533303932fdSDon Brace return false; 534303932fdSDon Brace 535303932fdSDon Brace /* Read outbound doorbell to flush */ 536303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 537303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 538303932fdSDon Brace } 539edd16368SStephen M. Cameron 540e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 541e1f7de0cSMatt Gates 542e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 543e1f7de0cSMatt Gates { 544e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 545e1f7de0cSMatt Gates 546e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 547e1f7de0cSMatt Gates true : false; 548e1f7de0cSMatt Gates } 549e1f7de0cSMatt Gates 550e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 551e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 552e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 553e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 554e1f7de0cSMatt Gates 555283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 556e1f7de0cSMatt Gates { 557e1f7de0cSMatt Gates u64 register_value; 558072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 559e1f7de0cSMatt Gates 560e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 561e1f7de0cSMatt Gates 562e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 563e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 564e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 565e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 566e1f7de0cSMatt Gates rq->current_entry = 0; 567283b4a9bSStephen M. Cameron /* 568283b4a9bSStephen M. Cameron * @todo 569283b4a9bSStephen M. Cameron * 570283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 571283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 572283b4a9bSStephen M. Cameron */ 573283b4a9bSStephen M. Cameron wmb(); 574283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 575283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5760cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 577e1f7de0cSMatt Gates } 578e1f7de0cSMatt Gates return (unsigned long) register_value; 579e1f7de0cSMatt Gates } 580e1f7de0cSMatt Gates 581edd16368SStephen M. Cameron static struct access_method SA5_access = { 58293380123SKees Cook .submit_command = SA5_submit_command, 58393380123SKees Cook .set_intr_mask = SA5_intr_mask, 58493380123SKees Cook .intr_pending = SA5_intr_pending, 58593380123SKees Cook .command_completed = SA5_completed, 586edd16368SStephen M. Cameron }; 587edd16368SStephen M. Cameron 588e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 58993380123SKees Cook .submit_command = SA5_submit_command, 59093380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 59193380123SKees Cook .intr_pending = SA5_ioaccel_mode1_intr_pending, 59293380123SKees Cook .command_completed = SA5_ioaccel_mode1_completed, 593e1f7de0cSMatt Gates }; 594e1f7de0cSMatt Gates 595c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 59693380123SKees Cook .submit_command = SA5_submit_command_ioaccel2, 59793380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 59893380123SKees Cook .intr_pending = SA5_performant_intr_pending, 59993380123SKees Cook .command_completed = SA5_performant_completed, 600c349775eSScott Teel }; 601c349775eSScott Teel 602303932fdSDon Brace static struct access_method SA5_performant_access = { 60393380123SKees Cook .submit_command = SA5_submit_command, 60493380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 60593380123SKees Cook .intr_pending = SA5_performant_intr_pending, 60693380123SKees Cook .command_completed = SA5_performant_completed, 607303932fdSDon Brace }; 608303932fdSDon Brace 609b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 61093380123SKees Cook .submit_command = SA5_submit_command_no_read, 61193380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 61293380123SKees Cook .intr_pending = SA5_performant_intr_pending, 61393380123SKees Cook .command_completed = SA5_performant_completed, 614b3a52e79SStephen M. Cameron }; 615b3a52e79SStephen M. Cameron 616edd16368SStephen M. Cameron struct board_type { 61701a02ffcSStephen M. Cameron u32 board_id; 618edd16368SStephen M. Cameron char *product_name; 619edd16368SStephen M. Cameron struct access_method *access; 620edd16368SStephen M. Cameron }; 621edd16368SStephen M. Cameron 622edd16368SStephen M. Cameron #endif /* HPSA_H */ 623edd16368SStephen M. Cameron 624