1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 394c7bc31SDon Brace * Copyright 2016 Microsemi Corporation 41358f6dcSDon Brace * Copyright 2014-2015 PMC-Sierra, Inc. 51358f6dcSDon Brace * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6edd16368SStephen M. Cameron * 7edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 8edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 9edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 10edd16368SStephen M. Cameron * 11edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 12edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 13edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 15edd16368SStephen M. Cameron * 1694c7bc31SDon Brace * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17edd16368SStephen M. Cameron * 18edd16368SStephen M. Cameron */ 19edd16368SStephen M. Cameron #ifndef HPSA_H 20edd16368SStephen M. Cameron #define HPSA_H 21edd16368SStephen M. Cameron 22edd16368SStephen M. Cameron #include <scsi/scsicam.h> 23edd16368SStephen M. Cameron 24edd16368SStephen M. Cameron #define IO_OK 0 25edd16368SStephen M. Cameron #define IO_ERROR 1 26edd16368SStephen M. Cameron 27edd16368SStephen M. Cameron struct ctlr_info; 28edd16368SStephen M. Cameron 29edd16368SStephen M. Cameron struct access_method { 30edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 31edd16368SStephen M. Cameron struct CommandList *c); 32edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 33900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 34254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 35edd16368SStephen M. Cameron }; 36edd16368SStephen M. Cameron 37d04e62b9SKevin Barnett /* for SAS hosts and SAS expanders */ 38d04e62b9SKevin Barnett struct hpsa_sas_node { 39d04e62b9SKevin Barnett struct device *parent_dev; 40d04e62b9SKevin Barnett struct list_head port_list_head; 41d04e62b9SKevin Barnett }; 42d04e62b9SKevin Barnett 43d04e62b9SKevin Barnett struct hpsa_sas_port { 44d04e62b9SKevin Barnett struct list_head port_list_entry; 45d04e62b9SKevin Barnett u64 sas_address; 46d04e62b9SKevin Barnett struct sas_port *port; 47d04e62b9SKevin Barnett int next_phy_index; 48d04e62b9SKevin Barnett struct list_head phy_list_head; 49d04e62b9SKevin Barnett struct hpsa_sas_node *parent_node; 50d04e62b9SKevin Barnett struct sas_rphy *rphy; 51d04e62b9SKevin Barnett }; 52d04e62b9SKevin Barnett 53d04e62b9SKevin Barnett struct hpsa_sas_phy { 54d04e62b9SKevin Barnett struct list_head phy_list_entry; 55d04e62b9SKevin Barnett struct sas_phy *phy; 56d04e62b9SKevin Barnett struct hpsa_sas_port *parent_port; 57d04e62b9SKevin Barnett bool added_to_port; 58d04e62b9SKevin Barnett }; 59d04e62b9SKevin Barnett 605086435eSDon Brace #define EXTERNAL_QD 7 61edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 623ad7de6bSDon Brace unsigned int devtype; 63edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 64edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 6504fa2f44SKevin Barnett u8 physical_device : 1; 662a168208SKevin Barnett u8 expose_device; 67ba74fdc4SDon Brace u8 removed : 1; /* device is marked for death */ 68edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 69edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 70d04e62b9SKevin Barnett u64 sas_address; 71edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 72edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 737630b3a5SHannes Reinecke unsigned char rev; /* byte 2 of inquiry data */ 74edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 759846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 7603383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 77d604f533SWebb Scales atomic_t reset_cmds_out; /* Count of commands to-be affected */ 7803383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 7903383736SDon Brace * counts commands sent to physical 8003383736SDon Brace * device via "ioaccel" path. 8103383736SDon Brace */ 82e1f7de0cSMatt Gates u32 ioaccel_handle; 838270b862SJoe Handzik u8 active_path_index; 848270b862SJoe Handzik u8 path_map; 858270b862SJoe Handzik u8 bay; 868270b862SJoe Handzik u8 box[8]; 878270b862SJoe Handzik u16 phys_connector[8]; 88283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 89283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 9041ce4c35SStephen Cameron int offload_to_be_enabled; 91a3144e0bSJoe Handzik int hba_ioaccel_enabled; 92283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 93283b4a9bSStephen M. Cameron * offload request to mirror drive 94283b4a9bSStephen M. Cameron */ 95283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 96283b4a9bSStephen M. Cameron 9703383736SDon Brace /* 9803383736SDon Brace * Pointers from logical drive map indices to the phys drives that 9903383736SDon Brace * make those logical drives. Note, multiple logical drives may 10003383736SDon Brace * share physical drives. You can have for instance 5 physical 10103383736SDon Brace * drives with 3 logical drives each using those same 5 physical 10203383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 10303383736SDon Brace * devices in order to honor physical device queue depth limits. 10403383736SDon Brace */ 10503383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 106d604f533SWebb Scales int nphysical_disks; 1079b5c48c2SStephen Cameron int supports_aborts; 108d04e62b9SKevin Barnett struct hpsa_sas_port *sas_port; 10966749d0dSScott Teel int external; /* 1-from external array 0-not <0-unknown */ 110edd16368SStephen M. Cameron }; 111edd16368SStephen M. Cameron 112072b0518SStephen M. Cameron struct reply_queue_buffer { 113254f796bSMatt Gates u64 *head; 114254f796bSMatt Gates size_t size; 115254f796bSMatt Gates u8 wraparound; 116254f796bSMatt Gates u32 current_entry; 117072b0518SStephen M. Cameron dma_addr_t busaddr; 118254f796bSMatt Gates }; 119254f796bSMatt Gates 120316b221aSStephen M. Cameron #pragma pack(1) 121316b221aSStephen M. Cameron struct bmic_controller_parameters { 122316b221aSStephen M. Cameron u8 led_flags; 123316b221aSStephen M. Cameron u8 enable_command_list_verification; 124316b221aSStephen M. Cameron u8 backed_out_write_drives; 125316b221aSStephen M. Cameron u16 stripes_for_parity; 126316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 127316b221aSStephen M. Cameron u16 max_driver_requests; 128316b221aSStephen M. Cameron u16 elevator_trend_count; 129316b221aSStephen M. Cameron u8 disable_elevator; 130316b221aSStephen M. Cameron u8 force_scan_complete; 131316b221aSStephen M. Cameron u8 scsi_transfer_mode; 132316b221aSStephen M. Cameron u8 force_narrow; 133316b221aSStephen M. Cameron u8 rebuild_priority; 134316b221aSStephen M. Cameron u8 expand_priority; 135316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 136316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 137316b221aSStephen M. Cameron char software_name[64]; 138316b221aSStephen M. Cameron char hardware_name[32]; 139316b221aSStephen M. Cameron u8 bridge_revision; 140316b221aSStephen M. Cameron u8 snapshot_priority; 141316b221aSStephen M. Cameron u32 os_specific; 142316b221aSStephen M. Cameron u8 post_prompt_timeout; 143316b221aSStephen M. Cameron u8 automatic_drive_slamming; 144316b221aSStephen M. Cameron u8 reserved1; 145316b221aSStephen M. Cameron u8 nvram_flags; 146316b221aSStephen M. Cameron u8 cache_nvram_flags; 147316b221aSStephen M. Cameron u8 drive_config_flags; 148316b221aSStephen M. Cameron u16 reserved2; 149316b221aSStephen M. Cameron u8 temp_warning_level; 150316b221aSStephen M. Cameron u8 temp_shutdown_level; 151316b221aSStephen M. Cameron u8 temp_condition_reset; 152316b221aSStephen M. Cameron u8 max_coalesce_commands; 153316b221aSStephen M. Cameron u32 max_coalesce_delay; 154316b221aSStephen M. Cameron u8 orca_password[4]; 155316b221aSStephen M. Cameron u8 access_id[16]; 156316b221aSStephen M. Cameron u8 reserved[356]; 157316b221aSStephen M. Cameron }; 158316b221aSStephen M. Cameron #pragma pack() 159316b221aSStephen M. Cameron 160edd16368SStephen M. Cameron struct ctlr_info { 161edd16368SStephen M. Cameron int ctlr; 162edd16368SStephen M. Cameron char devname[8]; 163edd16368SStephen M. Cameron char *product_name; 164edd16368SStephen M. Cameron struct pci_dev *pdev; 16501a02ffcSStephen M. Cameron u32 board_id; 166d04e62b9SKevin Barnett u64 sas_address; 167edd16368SStephen M. Cameron void __iomem *vaddr; 168edd16368SStephen M. Cameron unsigned long paddr; 169edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 170d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 171d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 172edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 173edd16368SStephen M. Cameron int interrupts_enabled; 174edd16368SStephen M. Cameron int max_commands; 1750cbf768eSStephen M. Cameron atomic_t commands_outstanding; 176303932fdSDon Brace # define PERF_MODE_INT 0 177303932fdSDon Brace # define DOORBELL_INT 1 178edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 179edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 180bc2bb154SChristoph Hellwig unsigned int msix_vectors; 181a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 182edd16368SStephen M. Cameron struct access_method access; 183edd16368SStephen M. Cameron 184edd16368SStephen M. Cameron /* queue and queue Info */ 185edd16368SStephen M. Cameron unsigned int Qdepth; 186edd16368SStephen M. Cameron unsigned int maxSG; 187edd16368SStephen M. Cameron spinlock_t lock; 18833a2ffceSStephen M. Cameron int maxsgentries; 18933a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 19033a2ffceSStephen M. Cameron int chainsize; 19133a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 192d9a729f3SWebb Scales struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; 193edd16368SStephen M. Cameron 194edd16368SStephen M. Cameron /* pointers to command and error info pool */ 195edd16368SStephen M. Cameron struct CommandList *cmd_pool; 196edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 197e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 198e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 199aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 200aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 201edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 202edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 203edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 204a08a8471SStephen M. Cameron int scan_finished; 20587b9e6aaSDon Brace u8 scan_waiting : 1; 206a08a8471SStephen M. Cameron spinlock_t scan_lock; 207a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 208edd16368SStephen M. Cameron 209edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 210edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 211edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 212cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 213303932fdSDon Brace /* 214303932fdSDon Brace * Performant mode tables. 215303932fdSDon Brace */ 216303932fdSDon Brace u32 trans_support; 217303932fdSDon Brace u32 trans_offset; 21842a91641SDon Brace struct TransTable_struct __iomem *transtable; 219303932fdSDon Brace unsigned long transMethod; 220303932fdSDon Brace 2210390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 22245fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 22334f0c627SDon Brace atomic_t passthru_cmds_avail; 2240390f0c0SStephen M. Cameron 225303932fdSDon Brace /* 226254f796bSMatt Gates * Performant mode completion buffers 227303932fdSDon Brace */ 228072b0518SStephen M. Cameron size_t reply_queue_size; 229072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 230254f796bSMatt Gates u8 nreply_queues; 231303932fdSDon Brace u32 *blockFetchTable; 232e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 233aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 23442a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 235339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 236283b4a9bSStephen M. Cameron u32 driver_support; 237283b4a9bSStephen M. Cameron u32 fw_support; 238283b4a9bSStephen M. Cameron int ioaccel_support; 239283b4a9bSStephen M. Cameron int ioaccel_maxsg; 240a0c12413SStephen M. Cameron u64 last_intr_timestamp; 241a0c12413SStephen M. Cameron u32 last_heartbeat; 242a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 243e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 244e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 24542a91641SDon Brace u32 __percpu *lockup_detected; 2468a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2476636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2488a98db73SStephen M. Cameron int remove_in_progress; 249254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 250254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 2518b47004aSRobert Elliott char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ 25275167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 25375167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 25475167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 25575167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 25675167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 25775167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 25875167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 25975167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 26075167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 26175167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 26275167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 2638be986ccSStephen Cameron #define HPSATMF_IOACCEL_ENABLED (1 << 15) 26475167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 26575167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 26675167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 26775167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 26875167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 26975167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 27075167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 27175167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 27275167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 27375167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 27476438d08SStephen M. Cameron u32 events; 275faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 276faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 277faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 278faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 279faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 280faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 281faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 282faff6ee0SStephen M. Cameron 283faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2847b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 285faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 286faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 287faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 288faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2899846590eSStephen M. Cameron spinlock_t offline_device_lock; 2909846590eSStephen M. Cameron struct list_head offline_device_list; 291da0697bdSScott Teel int acciopath_status; 292853633e8SDon Brace int drv_req_rescan; 2932ba8bfc8SStephen M. Cameron int raid_offload_debug; 29434592254SScott Teel int discovery_polling; 29534592254SScott Teel struct ReportLUNdata *lastlogicals; 2969b5c48c2SStephen Cameron int needs_abort_tags_swizzled; 297080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 2986636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 2999b5c48c2SStephen Cameron atomic_t abort_cmds_available; 3009b5c48c2SStephen Cameron wait_queue_head_t abort_cmd_wait_queue; 301d604f533SWebb Scales wait_queue_head_t event_sync_wait_queue; 302d604f533SWebb Scales struct mutex reset_mutex; 303da03ded0SDon Brace u8 reset_in_progress; 304d04e62b9SKevin Barnett struct hpsa_sas_node *sas_host; 305c59d04f3SDon Brace spinlock_t reset_lock; 306edd16368SStephen M. Cameron }; 3079846590eSStephen M. Cameron 3089846590eSStephen M. Cameron struct offline_device_entry { 3099846590eSStephen M. Cameron unsigned char scsi3addr[8]; 3109846590eSStephen M. Cameron struct list_head offline_list; 3119846590eSStephen M. Cameron }; 3129846590eSStephen M. Cameron 313edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 314edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 31564670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 31664670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 31764670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 3180b9b7b6eSScott Teel #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ 319edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 320516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 321edd16368SStephen M. Cameron 322edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 323edd16368SStephen M. Cameron * when polling before giving up. 324edd16368SStephen M. Cameron */ 325edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 326edd16368SStephen M. Cameron 327edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 328edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 329edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 330edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 331edd16368SStephen M. Cameron * between sending TURs while waiting for a device 332edd16368SStephen M. Cameron * to become ready. 333edd16368SStephen M. Cameron */ 334edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 335edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 336edd16368SStephen M. Cameron 337edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 338edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 339edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 340edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 341edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 342edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 343edd16368SStephen M. Cameron */ 344edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3452ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 346edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 347edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 348edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 349edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 350edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 351edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 352fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 353fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 354fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 355edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 356edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 357edd16368SStephen M. Cameron 358edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 359edd16368SStephen M. Cameron /* 360edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 361edd16368SStephen M. Cameron */ 362edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 363edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 364281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 365281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 366edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 367edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 368edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 369edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 370edd16368SStephen M. Cameron 371edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 372edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 373edd16368SStephen M. Cameron 374edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 375edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 376edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 377edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 378edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 379edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 380edd16368SStephen M. Cameron 381edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 382edd16368SStephen M. Cameron 383303932fdSDon Brace /* Performant mode flags */ 384303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 385303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 386303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 387303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 388303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 389303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 390303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 391303932fdSDon Brace 392303932fdSDon Brace 393edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 394edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 395b66cc250SMike Miller 396b66cc250SMike Miller /* 397b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 398b66cc250SMike Miller */ 399b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 400b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 401b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 402b66cc250SMike Miller 403c795505aSKevin Barnett #define HPSA_PHYSICAL_DEVICE_BUS 0 404c795505aSKevin Barnett #define HPSA_RAID_VOLUME_BUS 1 405c795505aSKevin Barnett #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 40609371d62SDon Brace #define HPSA_HBA_BUS 0 4077630b3a5SHannes Reinecke #define HPSA_LEGACY_HBA_BUS 3 408c795505aSKevin Barnett 409edd16368SStephen M. Cameron /* 410edd16368SStephen M. Cameron Send the command to the hardware 411edd16368SStephen M. Cameron */ 412edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 413edd16368SStephen M. Cameron struct CommandList *c) 414edd16368SStephen M. Cameron { 415edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 416fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 417edd16368SStephen M. Cameron } 418edd16368SStephen M. Cameron 419b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 420b3a52e79SStephen M. Cameron struct CommandList *c) 421b3a52e79SStephen M. Cameron { 422b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 423b3a52e79SStephen M. Cameron } 424b3a52e79SStephen M. Cameron 425c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 426c349775eSScott Teel struct CommandList *c) 427c349775eSScott Teel { 428c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 429c349775eSScott Teel } 430c349775eSScott Teel 431edd16368SStephen M. Cameron /* 432edd16368SStephen M. Cameron * This card is the opposite of the other cards. 433edd16368SStephen M. Cameron * 0 turns interrupts on... 434edd16368SStephen M. Cameron * 0x08 turns them off... 435edd16368SStephen M. Cameron */ 436edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 437edd16368SStephen M. Cameron { 438edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 439edd16368SStephen M. Cameron h->interrupts_enabled = 1; 440edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4418cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 442edd16368SStephen M. Cameron } else { /* Turn them off */ 443edd16368SStephen M. Cameron h->interrupts_enabled = 0; 444edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 445edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4468cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 447edd16368SStephen M. Cameron } 448edd16368SStephen M. Cameron } 449303932fdSDon Brace 450303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 451303932fdSDon Brace { 452303932fdSDon Brace if (val) { /* turn on interrupts */ 453303932fdSDon Brace h->interrupts_enabled = 1; 454303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4558cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 456303932fdSDon Brace } else { 457303932fdSDon Brace h->interrupts_enabled = 0; 458303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 459303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4608cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 461303932fdSDon Brace } 462303932fdSDon Brace } 463303932fdSDon Brace 464254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 465303932fdSDon Brace { 466072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4670cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 468303932fdSDon Brace 4692c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 470bc2bb154SChristoph Hellwig if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) { 471303932fdSDon Brace /* flush the controller write of the reply queue by reading 472303932fdSDon Brace * outbound doorbell status register. 473303932fdSDon Brace */ 474bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 475303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 476303932fdSDon Brace /* Do a read in order to flush the write to the controller 477303932fdSDon Brace * (as per spec.) 478303932fdSDon Brace */ 479bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 480303932fdSDon Brace } 481303932fdSDon Brace 482bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 483254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 484254f796bSMatt Gates rq->current_entry++; 4850cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 486303932fdSDon Brace } else { 487303932fdSDon Brace register_value = FIFO_EMPTY; 488303932fdSDon Brace } 489303932fdSDon Brace /* Check for wraparound */ 490254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 491254f796bSMatt Gates rq->current_entry = 0; 492254f796bSMatt Gates rq->wraparound ^= 1; 493303932fdSDon Brace } 494303932fdSDon Brace return register_value; 495303932fdSDon Brace } 496303932fdSDon Brace 497edd16368SStephen M. Cameron /* 498edd16368SStephen M. Cameron * returns value read from hardware. 499edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 500edd16368SStephen M. Cameron */ 501254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 502254f796bSMatt Gates __attribute__((unused)) u8 q) 503edd16368SStephen M. Cameron { 504edd16368SStephen M. Cameron unsigned long register_value 505edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 506edd16368SStephen M. Cameron 5070cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 5080cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 509edd16368SStephen M. Cameron 510edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 511edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 51284ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 513edd16368SStephen M. Cameron register_value); 514edd16368SStephen M. Cameron else 515f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 516edd16368SStephen M. Cameron #endif 517edd16368SStephen M. Cameron 518edd16368SStephen M. Cameron return register_value; 519edd16368SStephen M. Cameron } 520edd16368SStephen M. Cameron /* 521edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 522edd16368SStephen M. Cameron */ 523900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 524edd16368SStephen M. Cameron { 525edd16368SStephen M. Cameron unsigned long register_value = 526edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 527900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 528edd16368SStephen M. Cameron } 529edd16368SStephen M. Cameron 530303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 531303932fdSDon Brace { 532303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 533303932fdSDon Brace 534303932fdSDon Brace if (!register_value) 535303932fdSDon Brace return false; 536303932fdSDon Brace 537303932fdSDon Brace /* Read outbound doorbell to flush */ 538303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 539303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 540303932fdSDon Brace } 541edd16368SStephen M. Cameron 542e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 543e1f7de0cSMatt Gates 544e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 545e1f7de0cSMatt Gates { 546e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 547e1f7de0cSMatt Gates 548e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 549e1f7de0cSMatt Gates true : false; 550e1f7de0cSMatt Gates } 551e1f7de0cSMatt Gates 552e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 553e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 554e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 555e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 556e1f7de0cSMatt Gates 557283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 558e1f7de0cSMatt Gates { 559e1f7de0cSMatt Gates u64 register_value; 560072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 561e1f7de0cSMatt Gates 562e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 563e1f7de0cSMatt Gates 564e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 565e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 566e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 567e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 568e1f7de0cSMatt Gates rq->current_entry = 0; 569283b4a9bSStephen M. Cameron /* 570283b4a9bSStephen M. Cameron * @todo 571283b4a9bSStephen M. Cameron * 572283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 573283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 574283b4a9bSStephen M. Cameron */ 575283b4a9bSStephen M. Cameron wmb(); 576283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 577283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5780cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 579e1f7de0cSMatt Gates } 580e1f7de0cSMatt Gates return (unsigned long) register_value; 581e1f7de0cSMatt Gates } 582e1f7de0cSMatt Gates 583edd16368SStephen M. Cameron static struct access_method SA5_access = { 58493380123SKees Cook .submit_command = SA5_submit_command, 58593380123SKees Cook .set_intr_mask = SA5_intr_mask, 58693380123SKees Cook .intr_pending = SA5_intr_pending, 58793380123SKees Cook .command_completed = SA5_completed, 588edd16368SStephen M. Cameron }; 589edd16368SStephen M. Cameron 590e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 59193380123SKees Cook .submit_command = SA5_submit_command, 59293380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 59393380123SKees Cook .intr_pending = SA5_ioaccel_mode1_intr_pending, 59493380123SKees Cook .command_completed = SA5_ioaccel_mode1_completed, 595e1f7de0cSMatt Gates }; 596e1f7de0cSMatt Gates 597c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 59893380123SKees Cook .submit_command = SA5_submit_command_ioaccel2, 59993380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 60093380123SKees Cook .intr_pending = SA5_performant_intr_pending, 60193380123SKees Cook .command_completed = SA5_performant_completed, 602c349775eSScott Teel }; 603c349775eSScott Teel 604303932fdSDon Brace static struct access_method SA5_performant_access = { 60593380123SKees Cook .submit_command = SA5_submit_command, 60693380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 60793380123SKees Cook .intr_pending = SA5_performant_intr_pending, 60893380123SKees Cook .command_completed = SA5_performant_completed, 609303932fdSDon Brace }; 610303932fdSDon Brace 611b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 61293380123SKees Cook .submit_command = SA5_submit_command_no_read, 61393380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 61493380123SKees Cook .intr_pending = SA5_performant_intr_pending, 61593380123SKees Cook .command_completed = SA5_performant_completed, 616b3a52e79SStephen M. Cameron }; 617b3a52e79SStephen M. Cameron 618edd16368SStephen M. Cameron struct board_type { 61901a02ffcSStephen M. Cameron u32 board_id; 620edd16368SStephen M. Cameron char *product_name; 621edd16368SStephen M. Cameron struct access_method *access; 622edd16368SStephen M. Cameron }; 623edd16368SStephen M. Cameron 624edd16368SStephen M. Cameron #endif /* HPSA_H */ 625edd16368SStephen M. Cameron 626