1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 394c7bc31SDon Brace * Copyright 2016 Microsemi Corporation 41358f6dcSDon Brace * Copyright 2014-2015 PMC-Sierra, Inc. 51358f6dcSDon Brace * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6edd16368SStephen M. Cameron * 7edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 8edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 9edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 10edd16368SStephen M. Cameron * 11edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 12edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 13edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 15edd16368SStephen M. Cameron * 1694c7bc31SDon Brace * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17edd16368SStephen M. Cameron * 18edd16368SStephen M. Cameron */ 19edd16368SStephen M. Cameron #ifndef HPSA_H 20edd16368SStephen M. Cameron #define HPSA_H 21edd16368SStephen M. Cameron 22edd16368SStephen M. Cameron #include <scsi/scsicam.h> 23edd16368SStephen M. Cameron 24edd16368SStephen M. Cameron #define IO_OK 0 25edd16368SStephen M. Cameron #define IO_ERROR 1 26edd16368SStephen M. Cameron 27edd16368SStephen M. Cameron struct ctlr_info; 28edd16368SStephen M. Cameron 29edd16368SStephen M. Cameron struct access_method { 30edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 31edd16368SStephen M. Cameron struct CommandList *c); 32edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 33900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 34254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 35edd16368SStephen M. Cameron }; 36edd16368SStephen M. Cameron 37d04e62b9SKevin Barnett /* for SAS hosts and SAS expanders */ 38d04e62b9SKevin Barnett struct hpsa_sas_node { 39d04e62b9SKevin Barnett struct device *parent_dev; 40d04e62b9SKevin Barnett struct list_head port_list_head; 41d04e62b9SKevin Barnett }; 42d04e62b9SKevin Barnett 43d04e62b9SKevin Barnett struct hpsa_sas_port { 44d04e62b9SKevin Barnett struct list_head port_list_entry; 45d04e62b9SKevin Barnett u64 sas_address; 46d04e62b9SKevin Barnett struct sas_port *port; 47d04e62b9SKevin Barnett int next_phy_index; 48d04e62b9SKevin Barnett struct list_head phy_list_head; 49d04e62b9SKevin Barnett struct hpsa_sas_node *parent_node; 50d04e62b9SKevin Barnett struct sas_rphy *rphy; 51d04e62b9SKevin Barnett }; 52d04e62b9SKevin Barnett 53d04e62b9SKevin Barnett struct hpsa_sas_phy { 54d04e62b9SKevin Barnett struct list_head phy_list_entry; 55d04e62b9SKevin Barnett struct sas_phy *phy; 56d04e62b9SKevin Barnett struct hpsa_sas_port *parent_port; 57d04e62b9SKevin Barnett bool added_to_port; 58d04e62b9SKevin Barnett }; 59d04e62b9SKevin Barnett 605086435eSDon Brace #define EXTERNAL_QD 7 61edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 623ad7de6bSDon Brace unsigned int devtype; 63edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 64edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 6504fa2f44SKevin Barnett u8 physical_device : 1; 662a168208SKevin Barnett u8 expose_device; 67ba74fdc4SDon Brace u8 removed : 1; /* device is marked for death */ 68edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 69edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 70d04e62b9SKevin Barnett u64 sas_address; 7101d0e789SDon Brace u64 eli; /* from report diags. */ 72edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 73edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 747630b3a5SHannes Reinecke unsigned char rev; /* byte 2 of inquiry data */ 75edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 769846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 7703383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 78d604f533SWebb Scales atomic_t reset_cmds_out; /* Count of commands to-be affected */ 7903383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 8003383736SDon Brace * counts commands sent to physical 8103383736SDon Brace * device via "ioaccel" path. 8203383736SDon Brace */ 83e1f7de0cSMatt Gates u32 ioaccel_handle; 848270b862SJoe Handzik u8 active_path_index; 858270b862SJoe Handzik u8 path_map; 868270b862SJoe Handzik u8 bay; 878270b862SJoe Handzik u8 box[8]; 888270b862SJoe Handzik u16 phys_connector[8]; 89283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 90283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 9141ce4c35SStephen Cameron int offload_to_be_enabled; 92a3144e0bSJoe Handzik int hba_ioaccel_enabled; 93283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 94283b4a9bSStephen M. Cameron * offload request to mirror drive 95283b4a9bSStephen M. Cameron */ 96283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 97283b4a9bSStephen M. Cameron 9803383736SDon Brace /* 9903383736SDon Brace * Pointers from logical drive map indices to the phys drives that 10003383736SDon Brace * make those logical drives. Note, multiple logical drives may 10103383736SDon Brace * share physical drives. You can have for instance 5 physical 10203383736SDon Brace * drives with 3 logical drives each using those same 5 physical 10303383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 10403383736SDon Brace * devices in order to honor physical device queue depth limits. 10503383736SDon Brace */ 10603383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 107d604f533SWebb Scales int nphysical_disks; 1089b5c48c2SStephen Cameron int supports_aborts; 109d04e62b9SKevin Barnett struct hpsa_sas_port *sas_port; 11066749d0dSScott Teel int external; /* 1-from external array 0-not <0-unknown */ 111edd16368SStephen M. Cameron }; 112edd16368SStephen M. Cameron 113072b0518SStephen M. Cameron struct reply_queue_buffer { 114254f796bSMatt Gates u64 *head; 115254f796bSMatt Gates size_t size; 116254f796bSMatt Gates u8 wraparound; 117254f796bSMatt Gates u32 current_entry; 118072b0518SStephen M. Cameron dma_addr_t busaddr; 119254f796bSMatt Gates }; 120254f796bSMatt Gates 121316b221aSStephen M. Cameron #pragma pack(1) 122316b221aSStephen M. Cameron struct bmic_controller_parameters { 123316b221aSStephen M. Cameron u8 led_flags; 124316b221aSStephen M. Cameron u8 enable_command_list_verification; 125316b221aSStephen M. Cameron u8 backed_out_write_drives; 126316b221aSStephen M. Cameron u16 stripes_for_parity; 127316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 128316b221aSStephen M. Cameron u16 max_driver_requests; 129316b221aSStephen M. Cameron u16 elevator_trend_count; 130316b221aSStephen M. Cameron u8 disable_elevator; 131316b221aSStephen M. Cameron u8 force_scan_complete; 132316b221aSStephen M. Cameron u8 scsi_transfer_mode; 133316b221aSStephen M. Cameron u8 force_narrow; 134316b221aSStephen M. Cameron u8 rebuild_priority; 135316b221aSStephen M. Cameron u8 expand_priority; 136316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 137316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 138316b221aSStephen M. Cameron char software_name[64]; 139316b221aSStephen M. Cameron char hardware_name[32]; 140316b221aSStephen M. Cameron u8 bridge_revision; 141316b221aSStephen M. Cameron u8 snapshot_priority; 142316b221aSStephen M. Cameron u32 os_specific; 143316b221aSStephen M. Cameron u8 post_prompt_timeout; 144316b221aSStephen M. Cameron u8 automatic_drive_slamming; 145316b221aSStephen M. Cameron u8 reserved1; 146316b221aSStephen M. Cameron u8 nvram_flags; 147316b221aSStephen M. Cameron u8 cache_nvram_flags; 148316b221aSStephen M. Cameron u8 drive_config_flags; 149316b221aSStephen M. Cameron u16 reserved2; 150316b221aSStephen M. Cameron u8 temp_warning_level; 151316b221aSStephen M. Cameron u8 temp_shutdown_level; 152316b221aSStephen M. Cameron u8 temp_condition_reset; 153316b221aSStephen M. Cameron u8 max_coalesce_commands; 154316b221aSStephen M. Cameron u32 max_coalesce_delay; 155316b221aSStephen M. Cameron u8 orca_password[4]; 156316b221aSStephen M. Cameron u8 access_id[16]; 157316b221aSStephen M. Cameron u8 reserved[356]; 158316b221aSStephen M. Cameron }; 159316b221aSStephen M. Cameron #pragma pack() 160316b221aSStephen M. Cameron 161edd16368SStephen M. Cameron struct ctlr_info { 1628b834bffSMing Lei unsigned int *reply_map; 163edd16368SStephen M. Cameron int ctlr; 164edd16368SStephen M. Cameron char devname[8]; 165edd16368SStephen M. Cameron char *product_name; 166edd16368SStephen M. Cameron struct pci_dev *pdev; 16701a02ffcSStephen M. Cameron u32 board_id; 168d04e62b9SKevin Barnett u64 sas_address; 169edd16368SStephen M. Cameron void __iomem *vaddr; 170edd16368SStephen M. Cameron unsigned long paddr; 171edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 172d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 173d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 174edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 175edd16368SStephen M. Cameron int interrupts_enabled; 176edd16368SStephen M. Cameron int max_commands; 1774770e68dSDon Brace int last_collision_tag; /* tags are global */ 1780cbf768eSStephen M. Cameron atomic_t commands_outstanding; 179303932fdSDon Brace # define PERF_MODE_INT 0 180303932fdSDon Brace # define DOORBELL_INT 1 181edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 182edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 183bc2bb154SChristoph Hellwig unsigned int msix_vectors; 184a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 185edd16368SStephen M. Cameron struct access_method access; 186edd16368SStephen M. Cameron 187edd16368SStephen M. Cameron /* queue and queue Info */ 188edd16368SStephen M. Cameron unsigned int Qdepth; 189edd16368SStephen M. Cameron unsigned int maxSG; 190edd16368SStephen M. Cameron spinlock_t lock; 19133a2ffceSStephen M. Cameron int maxsgentries; 19233a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 19333a2ffceSStephen M. Cameron int chainsize; 19433a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 195d9a729f3SWebb Scales struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; 196edd16368SStephen M. Cameron 197edd16368SStephen M. Cameron /* pointers to command and error info pool */ 198edd16368SStephen M. Cameron struct CommandList *cmd_pool; 199edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 200e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 201e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 202aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 203aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 204edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 205edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 206edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 207a08a8471SStephen M. Cameron int scan_finished; 20887b9e6aaSDon Brace u8 scan_waiting : 1; 209a08a8471SStephen M. Cameron spinlock_t scan_lock; 210a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 211edd16368SStephen M. Cameron 212edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 213edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 214edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 215cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 216303932fdSDon Brace /* 217303932fdSDon Brace * Performant mode tables. 218303932fdSDon Brace */ 219303932fdSDon Brace u32 trans_support; 220303932fdSDon Brace u32 trans_offset; 22142a91641SDon Brace struct TransTable_struct __iomem *transtable; 222303932fdSDon Brace unsigned long transMethod; 223303932fdSDon Brace 2240390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 22545fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 22634f0c627SDon Brace atomic_t passthru_cmds_avail; 2270390f0c0SStephen M. Cameron 228303932fdSDon Brace /* 229254f796bSMatt Gates * Performant mode completion buffers 230303932fdSDon Brace */ 231072b0518SStephen M. Cameron size_t reply_queue_size; 232072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 233254f796bSMatt Gates u8 nreply_queues; 234303932fdSDon Brace u32 *blockFetchTable; 235e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 236aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 23742a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 238339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 239283b4a9bSStephen M. Cameron u32 driver_support; 240283b4a9bSStephen M. Cameron u32 fw_support; 241283b4a9bSStephen M. Cameron int ioaccel_support; 242283b4a9bSStephen M. Cameron int ioaccel_maxsg; 243a0c12413SStephen M. Cameron u64 last_intr_timestamp; 244a0c12413SStephen M. Cameron u32 last_heartbeat; 245a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 246e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 247e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 24842a91641SDon Brace u32 __percpu *lockup_detected; 2498a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2506636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2513d38f00cSScott Teel struct delayed_work event_monitor_work; 2528a98db73SStephen M. Cameron int remove_in_progress; 253254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 254254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 2558b47004aSRobert Elliott char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ 25675167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 25775167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 25875167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 25975167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 26075167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 26175167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 26275167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 26375167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 26475167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 26575167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 26675167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 2678be986ccSStephen Cameron #define HPSATMF_IOACCEL_ENABLED (1 << 15) 26875167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 26975167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 27075167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 27175167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 27275167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 27375167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 27475167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 27575167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 27675167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 27775167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 27876438d08SStephen M. Cameron u32 events; 279faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 280faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 281faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 282faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 283faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 284faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 285faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 286faff6ee0SStephen M. Cameron 287faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2887b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 289faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 290faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 291faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 292faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2939846590eSStephen M. Cameron spinlock_t offline_device_lock; 2949846590eSStephen M. Cameron struct list_head offline_device_list; 295da0697bdSScott Teel int acciopath_status; 296853633e8SDon Brace int drv_req_rescan; 2972ba8bfc8SStephen M. Cameron int raid_offload_debug; 29834592254SScott Teel int discovery_polling; 299135ae6edSHannes Reinecke int legacy_board; 30034592254SScott Teel struct ReportLUNdata *lastlogicals; 3019b5c48c2SStephen Cameron int needs_abort_tags_swizzled; 302080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 3036636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 30401192088SDon Brace struct workqueue_struct *monitor_ctlr_wq; 3059b5c48c2SStephen Cameron atomic_t abort_cmds_available; 306d604f533SWebb Scales wait_queue_head_t event_sync_wait_queue; 307d604f533SWebb Scales struct mutex reset_mutex; 308da03ded0SDon Brace u8 reset_in_progress; 309d04e62b9SKevin Barnett struct hpsa_sas_node *sas_host; 310c59d04f3SDon Brace spinlock_t reset_lock; 311edd16368SStephen M. Cameron }; 3129846590eSStephen M. Cameron 3139846590eSStephen M. Cameron struct offline_device_entry { 3149846590eSStephen M. Cameron unsigned char scsi3addr[8]; 3159846590eSStephen M. Cameron struct list_head offline_list; 3169846590eSStephen M. Cameron }; 3179846590eSStephen M. Cameron 318edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 319edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 32064670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 32164670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 32264670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 3230b9b7b6eSScott Teel #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ 324edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 325516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 326edd16368SStephen M. Cameron 327edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 328edd16368SStephen M. Cameron * when polling before giving up. 329edd16368SStephen M. Cameron */ 330edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 331edd16368SStephen M. Cameron 332edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 333edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 334edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 335edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 336edd16368SStephen M. Cameron * between sending TURs while waiting for a device 337edd16368SStephen M. Cameron * to become ready. 338edd16368SStephen M. Cameron */ 339edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 340edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 341edd16368SStephen M. Cameron 342edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 343edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 344edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 345edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 346edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 347edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 348edd16368SStephen M. Cameron */ 349edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3502ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 351edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 352edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 353edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 354edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 355edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 356edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 357fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 358fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 359fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 360edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 361edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 362edd16368SStephen M. Cameron 363edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 364edd16368SStephen M. Cameron /* 365edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 366edd16368SStephen M. Cameron */ 367edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 368edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 369281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 370281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 371edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 372edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 373edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 374edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 375edd16368SStephen M. Cameron 376edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 377edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 378edd16368SStephen M. Cameron 379edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 380edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 381edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 382edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 383edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 384edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 385edd16368SStephen M. Cameron 386edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 387edd16368SStephen M. Cameron 388303932fdSDon Brace /* Performant mode flags */ 389303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 390303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 391303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 392303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 393303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 394303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 395303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 396303932fdSDon Brace 397303932fdSDon Brace 398edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 399edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 400b66cc250SMike Miller 401b66cc250SMike Miller /* 402b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 403b66cc250SMike Miller */ 404b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 405b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 406b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 407b66cc250SMike Miller 408c795505aSKevin Barnett #define HPSA_PHYSICAL_DEVICE_BUS 0 409c795505aSKevin Barnett #define HPSA_RAID_VOLUME_BUS 1 410c795505aSKevin Barnett #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 41109371d62SDon Brace #define HPSA_HBA_BUS 0 4127630b3a5SHannes Reinecke #define HPSA_LEGACY_HBA_BUS 3 413c795505aSKevin Barnett 414edd16368SStephen M. Cameron /* 415edd16368SStephen M. Cameron Send the command to the hardware 416edd16368SStephen M. Cameron */ 417edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 418edd16368SStephen M. Cameron struct CommandList *c) 419edd16368SStephen M. Cameron { 420edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 421fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 422edd16368SStephen M. Cameron } 423edd16368SStephen M. Cameron 424b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 425b3a52e79SStephen M. Cameron struct CommandList *c) 426b3a52e79SStephen M. Cameron { 427b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 428b3a52e79SStephen M. Cameron } 429b3a52e79SStephen M. Cameron 430c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 431c349775eSScott Teel struct CommandList *c) 432c349775eSScott Teel { 433c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 434c349775eSScott Teel } 435c349775eSScott Teel 436edd16368SStephen M. Cameron /* 437edd16368SStephen M. Cameron * This card is the opposite of the other cards. 438edd16368SStephen M. Cameron * 0 turns interrupts on... 439edd16368SStephen M. Cameron * 0x08 turns them off... 440edd16368SStephen M. Cameron */ 441edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 442edd16368SStephen M. Cameron { 443edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 444edd16368SStephen M. Cameron h->interrupts_enabled = 1; 445edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4468cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 447edd16368SStephen M. Cameron } else { /* Turn them off */ 448edd16368SStephen M. Cameron h->interrupts_enabled = 0; 449edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 450edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4518cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 452edd16368SStephen M. Cameron } 453edd16368SStephen M. Cameron } 454303932fdSDon Brace 455135ae6edSHannes Reinecke /* 456135ae6edSHannes Reinecke * Variant of the above; 0x04 turns interrupts off... 457135ae6edSHannes Reinecke */ 458135ae6edSHannes Reinecke static void SA5B_intr_mask(struct ctlr_info *h, unsigned long val) 459135ae6edSHannes Reinecke { 460135ae6edSHannes Reinecke if (val) { /* Turn interrupts on */ 461135ae6edSHannes Reinecke h->interrupts_enabled = 1; 462135ae6edSHannes Reinecke writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 463135ae6edSHannes Reinecke (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 464135ae6edSHannes Reinecke } else { /* Turn them off */ 465135ae6edSHannes Reinecke h->interrupts_enabled = 0; 466135ae6edSHannes Reinecke writel(SA5B_INTR_OFF, 467135ae6edSHannes Reinecke h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 468135ae6edSHannes Reinecke (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 469135ae6edSHannes Reinecke } 470135ae6edSHannes Reinecke } 471135ae6edSHannes Reinecke 472303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 473303932fdSDon Brace { 474303932fdSDon Brace if (val) { /* turn on interrupts */ 475303932fdSDon Brace h->interrupts_enabled = 1; 476303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4778cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 478303932fdSDon Brace } else { 479303932fdSDon Brace h->interrupts_enabled = 0; 480303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 481303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4828cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 483303932fdSDon Brace } 484303932fdSDon Brace } 485303932fdSDon Brace 486254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 487303932fdSDon Brace { 488072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4890cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 490303932fdSDon Brace 4912c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 492bc2bb154SChristoph Hellwig if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) { 493303932fdSDon Brace /* flush the controller write of the reply queue by reading 494303932fdSDon Brace * outbound doorbell status register. 495303932fdSDon Brace */ 496bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 497303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 498303932fdSDon Brace /* Do a read in order to flush the write to the controller 499303932fdSDon Brace * (as per spec.) 500303932fdSDon Brace */ 501bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 502303932fdSDon Brace } 503303932fdSDon Brace 504bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 505254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 506254f796bSMatt Gates rq->current_entry++; 5070cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 508303932fdSDon Brace } else { 509303932fdSDon Brace register_value = FIFO_EMPTY; 510303932fdSDon Brace } 511303932fdSDon Brace /* Check for wraparound */ 512254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 513254f796bSMatt Gates rq->current_entry = 0; 514254f796bSMatt Gates rq->wraparound ^= 1; 515303932fdSDon Brace } 516303932fdSDon Brace return register_value; 517303932fdSDon Brace } 518303932fdSDon Brace 519edd16368SStephen M. Cameron /* 520edd16368SStephen M. Cameron * returns value read from hardware. 521edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 522edd16368SStephen M. Cameron */ 523254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 524254f796bSMatt Gates __attribute__((unused)) u8 q) 525edd16368SStephen M. Cameron { 526edd16368SStephen M. Cameron unsigned long register_value 527edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 528edd16368SStephen M. Cameron 5290cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 5300cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 531edd16368SStephen M. Cameron 532edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 533edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 53484ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 535edd16368SStephen M. Cameron register_value); 536edd16368SStephen M. Cameron else 537f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 538edd16368SStephen M. Cameron #endif 539edd16368SStephen M. Cameron 540edd16368SStephen M. Cameron return register_value; 541edd16368SStephen M. Cameron } 542edd16368SStephen M. Cameron /* 543edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 544edd16368SStephen M. Cameron */ 545900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 546edd16368SStephen M. Cameron { 547edd16368SStephen M. Cameron unsigned long register_value = 548edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 549900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 550edd16368SStephen M. Cameron } 551edd16368SStephen M. Cameron 552303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 553303932fdSDon Brace { 554303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 555303932fdSDon Brace 556303932fdSDon Brace if (!register_value) 557303932fdSDon Brace return false; 558303932fdSDon Brace 559303932fdSDon Brace /* Read outbound doorbell to flush */ 560303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 561303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 562303932fdSDon Brace } 563edd16368SStephen M. Cameron 564e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 565e1f7de0cSMatt Gates 566e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 567e1f7de0cSMatt Gates { 568e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 569e1f7de0cSMatt Gates 570e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 571e1f7de0cSMatt Gates true : false; 572e1f7de0cSMatt Gates } 573e1f7de0cSMatt Gates 574135ae6edSHannes Reinecke /* 575135ae6edSHannes Reinecke * Returns true if an interrupt is pending.. 576135ae6edSHannes Reinecke */ 577135ae6edSHannes Reinecke static bool SA5B_intr_pending(struct ctlr_info *h) 578135ae6edSHannes Reinecke { 579135ae6edSHannes Reinecke return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING; 580135ae6edSHannes Reinecke } 581135ae6edSHannes Reinecke 582e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 583e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 584e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 585e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 586e1f7de0cSMatt Gates 587283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 588e1f7de0cSMatt Gates { 589e1f7de0cSMatt Gates u64 register_value; 590072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 591e1f7de0cSMatt Gates 592e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 593e1f7de0cSMatt Gates 594e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 595e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 596e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 597e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 598e1f7de0cSMatt Gates rq->current_entry = 0; 599283b4a9bSStephen M. Cameron /* 600283b4a9bSStephen M. Cameron * @todo 601283b4a9bSStephen M. Cameron * 602283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 603283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 604283b4a9bSStephen M. Cameron */ 605283b4a9bSStephen M. Cameron wmb(); 606283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 607283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 6080cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 609e1f7de0cSMatt Gates } 610e1f7de0cSMatt Gates return (unsigned long) register_value; 611e1f7de0cSMatt Gates } 612e1f7de0cSMatt Gates 613edd16368SStephen M. Cameron static struct access_method SA5_access = { 61493380123SKees Cook .submit_command = SA5_submit_command, 61593380123SKees Cook .set_intr_mask = SA5_intr_mask, 61693380123SKees Cook .intr_pending = SA5_intr_pending, 61793380123SKees Cook .command_completed = SA5_completed, 618edd16368SStephen M. Cameron }; 619edd16368SStephen M. Cameron 620135ae6edSHannes Reinecke /* Duplicate entry of the above to mark unsupported boards */ 621135ae6edSHannes Reinecke static struct access_method SA5A_access = { 622135ae6edSHannes Reinecke .submit_command = SA5_submit_command, 623135ae6edSHannes Reinecke .set_intr_mask = SA5_intr_mask, 624135ae6edSHannes Reinecke .intr_pending = SA5_intr_pending, 625135ae6edSHannes Reinecke .command_completed = SA5_completed, 626135ae6edSHannes Reinecke }; 627135ae6edSHannes Reinecke 628135ae6edSHannes Reinecke static struct access_method SA5B_access = { 629135ae6edSHannes Reinecke .submit_command = SA5_submit_command, 630135ae6edSHannes Reinecke .set_intr_mask = SA5B_intr_mask, 631135ae6edSHannes Reinecke .intr_pending = SA5B_intr_pending, 632135ae6edSHannes Reinecke .command_completed = SA5_completed, 633135ae6edSHannes Reinecke }; 634135ae6edSHannes Reinecke 635e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 63693380123SKees Cook .submit_command = SA5_submit_command, 63793380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 63893380123SKees Cook .intr_pending = SA5_ioaccel_mode1_intr_pending, 63993380123SKees Cook .command_completed = SA5_ioaccel_mode1_completed, 640e1f7de0cSMatt Gates }; 641e1f7de0cSMatt Gates 642c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 64393380123SKees Cook .submit_command = SA5_submit_command_ioaccel2, 64493380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 64593380123SKees Cook .intr_pending = SA5_performant_intr_pending, 64693380123SKees Cook .command_completed = SA5_performant_completed, 647c349775eSScott Teel }; 648c349775eSScott Teel 649303932fdSDon Brace static struct access_method SA5_performant_access = { 65093380123SKees Cook .submit_command = SA5_submit_command, 65193380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 65293380123SKees Cook .intr_pending = SA5_performant_intr_pending, 65393380123SKees Cook .command_completed = SA5_performant_completed, 654303932fdSDon Brace }; 655303932fdSDon Brace 656b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 65793380123SKees Cook .submit_command = SA5_submit_command_no_read, 65893380123SKees Cook .set_intr_mask = SA5_performant_intr_mask, 65993380123SKees Cook .intr_pending = SA5_performant_intr_pending, 66093380123SKees Cook .command_completed = SA5_performant_completed, 661b3a52e79SStephen M. Cameron }; 662b3a52e79SStephen M. Cameron 663edd16368SStephen M. Cameron struct board_type { 66401a02ffcSStephen M. Cameron u32 board_id; 665edd16368SStephen M. Cameron char *product_name; 666edd16368SStephen M. Cameron struct access_method *access; 667edd16368SStephen M. Cameron }; 668edd16368SStephen M. Cameron 669edd16368SStephen M. Cameron #endif /* HPSA_H */ 670edd16368SStephen M. Cameron 671