1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 351c35139SScott Teel * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. 4edd16368SStephen M. Cameron * 5edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 6edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 7edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 8edd16368SStephen M. Cameron * 9edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 10edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 11edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 13edd16368SStephen M. Cameron * 14edd16368SStephen M. Cameron * You should have received a copy of the GNU General Public License 15edd16368SStephen M. Cameron * along with this program; if not, write to the Free Software 16edd16368SStephen M. Cameron * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17edd16368SStephen M. Cameron * 18edd16368SStephen M. Cameron * Questions/Comments/Bugfixes to iss_storagedev@hp.com 19edd16368SStephen M. Cameron * 20edd16368SStephen M. Cameron */ 21edd16368SStephen M. Cameron #ifndef HPSA_H 22edd16368SStephen M. Cameron #define HPSA_H 23edd16368SStephen M. Cameron 24edd16368SStephen M. Cameron #include <scsi/scsicam.h> 25edd16368SStephen M. Cameron 26edd16368SStephen M. Cameron #define IO_OK 0 27edd16368SStephen M. Cameron #define IO_ERROR 1 28edd16368SStephen M. Cameron 29edd16368SStephen M. Cameron struct ctlr_info; 30edd16368SStephen M. Cameron 31edd16368SStephen M. Cameron struct access_method { 32edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 33edd16368SStephen M. Cameron struct CommandList *c); 34edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 35900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 36254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 37edd16368SStephen M. Cameron }; 38edd16368SStephen M. Cameron 39edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 40edd16368SStephen M. Cameron int devtype; 41edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 42edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 43edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 44edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 45edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 46edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 47edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 489846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 4903383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 5003383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 5103383736SDon Brace * counts commands sent to physical 5203383736SDon Brace * device via "ioaccel" path. 5303383736SDon Brace */ 54e1f7de0cSMatt Gates u32 ioaccel_handle; 55283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 56283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 5741ce4c35SStephen Cameron int offload_to_be_enabled; 58283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 59283b4a9bSStephen M. Cameron * offload request to mirror drive 60283b4a9bSStephen M. Cameron */ 61283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 62283b4a9bSStephen M. Cameron 6303383736SDon Brace /* 6403383736SDon Brace * Pointers from logical drive map indices to the phys drives that 6503383736SDon Brace * make those logical drives. Note, multiple logical drives may 6603383736SDon Brace * share physical drives. You can have for instance 5 physical 6703383736SDon Brace * drives with 3 logical drives each using those same 5 physical 6803383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 6903383736SDon Brace * devices in order to honor physical device queue depth limits. 7003383736SDon Brace */ 7103383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 7241ce4c35SStephen Cameron #define HPSA_DO_NOT_EXPOSE 0x0 7341ce4c35SStephen Cameron #define HPSA_SG_ATTACH 0x1 7441ce4c35SStephen Cameron #define HPSA_ULD_ATTACH 0x2 7541ce4c35SStephen Cameron #define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH) 7641ce4c35SStephen Cameron u8 expose_state; 77edd16368SStephen M. Cameron }; 78edd16368SStephen M. Cameron 79072b0518SStephen M. Cameron struct reply_queue_buffer { 80254f796bSMatt Gates u64 *head; 81254f796bSMatt Gates size_t size; 82254f796bSMatt Gates u8 wraparound; 83254f796bSMatt Gates u32 current_entry; 84072b0518SStephen M. Cameron dma_addr_t busaddr; 85254f796bSMatt Gates }; 86254f796bSMatt Gates 87316b221aSStephen M. Cameron #pragma pack(1) 88316b221aSStephen M. Cameron struct bmic_controller_parameters { 89316b221aSStephen M. Cameron u8 led_flags; 90316b221aSStephen M. Cameron u8 enable_command_list_verification; 91316b221aSStephen M. Cameron u8 backed_out_write_drives; 92316b221aSStephen M. Cameron u16 stripes_for_parity; 93316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 94316b221aSStephen M. Cameron u16 max_driver_requests; 95316b221aSStephen M. Cameron u16 elevator_trend_count; 96316b221aSStephen M. Cameron u8 disable_elevator; 97316b221aSStephen M. Cameron u8 force_scan_complete; 98316b221aSStephen M. Cameron u8 scsi_transfer_mode; 99316b221aSStephen M. Cameron u8 force_narrow; 100316b221aSStephen M. Cameron u8 rebuild_priority; 101316b221aSStephen M. Cameron u8 expand_priority; 102316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 103316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 104316b221aSStephen M. Cameron char software_name[64]; 105316b221aSStephen M. Cameron char hardware_name[32]; 106316b221aSStephen M. Cameron u8 bridge_revision; 107316b221aSStephen M. Cameron u8 snapshot_priority; 108316b221aSStephen M. Cameron u32 os_specific; 109316b221aSStephen M. Cameron u8 post_prompt_timeout; 110316b221aSStephen M. Cameron u8 automatic_drive_slamming; 111316b221aSStephen M. Cameron u8 reserved1; 112316b221aSStephen M. Cameron u8 nvram_flags; 1136e8e8088SJoe Handzik #define HBA_MODE_ENABLED_FLAG (1 << 3) 114316b221aSStephen M. Cameron u8 cache_nvram_flags; 115316b221aSStephen M. Cameron u8 drive_config_flags; 116316b221aSStephen M. Cameron u16 reserved2; 117316b221aSStephen M. Cameron u8 temp_warning_level; 118316b221aSStephen M. Cameron u8 temp_shutdown_level; 119316b221aSStephen M. Cameron u8 temp_condition_reset; 120316b221aSStephen M. Cameron u8 max_coalesce_commands; 121316b221aSStephen M. Cameron u32 max_coalesce_delay; 122316b221aSStephen M. Cameron u8 orca_password[4]; 123316b221aSStephen M. Cameron u8 access_id[16]; 124316b221aSStephen M. Cameron u8 reserved[356]; 125316b221aSStephen M. Cameron }; 126316b221aSStephen M. Cameron #pragma pack() 127316b221aSStephen M. Cameron 128edd16368SStephen M. Cameron struct ctlr_info { 129edd16368SStephen M. Cameron int ctlr; 130edd16368SStephen M. Cameron char devname[8]; 131edd16368SStephen M. Cameron char *product_name; 132edd16368SStephen M. Cameron struct pci_dev *pdev; 13301a02ffcSStephen M. Cameron u32 board_id; 134edd16368SStephen M. Cameron void __iomem *vaddr; 135edd16368SStephen M. Cameron unsigned long paddr; 136edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 137d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 138d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 139edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 140edd16368SStephen M. Cameron int interrupts_enabled; 141edd16368SStephen M. Cameron int max_commands; 14233811026SRobert Elliott int last_allocation; 1430cbf768eSStephen M. Cameron atomic_t commands_outstanding; 144303932fdSDon Brace # define PERF_MODE_INT 0 145303932fdSDon Brace # define DOORBELL_INT 1 146edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 147edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 148254f796bSMatt Gates unsigned int intr[MAX_REPLY_QUEUES]; 149edd16368SStephen M. Cameron unsigned int msix_vector; 150edd16368SStephen M. Cameron unsigned int msi_vector; 151a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 152edd16368SStephen M. Cameron struct access_method access; 153316b221aSStephen M. Cameron char hba_mode_enabled; 154edd16368SStephen M. Cameron 155edd16368SStephen M. Cameron /* queue and queue Info */ 156edd16368SStephen M. Cameron unsigned int Qdepth; 157edd16368SStephen M. Cameron unsigned int maxSG; 158edd16368SStephen M. Cameron spinlock_t lock; 15933a2ffceSStephen M. Cameron int maxsgentries; 16033a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 16133a2ffceSStephen M. Cameron int chainsize; 16233a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 163edd16368SStephen M. Cameron 164edd16368SStephen M. Cameron /* pointers to command and error info pool */ 165edd16368SStephen M. Cameron struct CommandList *cmd_pool; 166edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 167e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 168e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 169aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 170aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 171edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 172edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 173edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 174a08a8471SStephen M. Cameron int scan_finished; 175a08a8471SStephen M. Cameron spinlock_t scan_lock; 176a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 177edd16368SStephen M. Cameron 178edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 179edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 180edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 181cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 182303932fdSDon Brace /* 183303932fdSDon Brace * Performant mode tables. 184303932fdSDon Brace */ 185303932fdSDon Brace u32 trans_support; 186303932fdSDon Brace u32 trans_offset; 18742a91641SDon Brace struct TransTable_struct __iomem *transtable; 188303932fdSDon Brace unsigned long transMethod; 189303932fdSDon Brace 1900390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 19145fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 19234f0c627SDon Brace atomic_t passthru_cmds_avail; 1930390f0c0SStephen M. Cameron 194303932fdSDon Brace /* 195254f796bSMatt Gates * Performant mode completion buffers 196303932fdSDon Brace */ 197072b0518SStephen M. Cameron size_t reply_queue_size; 198072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 199254f796bSMatt Gates u8 nreply_queues; 200303932fdSDon Brace u32 *blockFetchTable; 201e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 202aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 20342a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 204339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 205283b4a9bSStephen M. Cameron u32 driver_support; 206283b4a9bSStephen M. Cameron u32 fw_support; 207283b4a9bSStephen M. Cameron int ioaccel_support; 208283b4a9bSStephen M. Cameron int ioaccel_maxsg; 209a0c12413SStephen M. Cameron u64 last_intr_timestamp; 210a0c12413SStephen M. Cameron u32 last_heartbeat; 211a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 212e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 213e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 21442a91641SDon Brace u32 __percpu *lockup_detected; 2158a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2166636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2178a98db73SStephen M. Cameron int remove_in_progress; 218254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 219254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 22075167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 22175167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 22275167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 22375167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 22475167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 22575167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 22675167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 22775167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 22875167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 22975167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 23075167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 23175167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 23275167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 23375167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 23475167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 23575167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 23675167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 23775167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 23875167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 23975167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 24075167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 24176438d08SStephen M. Cameron u32 events; 242faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 243faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 244faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 245faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 246faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 247faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 248faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 249faff6ee0SStephen M. Cameron 250faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2517b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 252faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 253faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 254faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 255faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2569846590eSStephen M. Cameron spinlock_t offline_device_lock; 2579846590eSStephen M. Cameron struct list_head offline_device_list; 258da0697bdSScott Teel int acciopath_status; 2592ba8bfc8SStephen M. Cameron int raid_offload_debug; 260080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 2616636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 262edd16368SStephen M. Cameron }; 2639846590eSStephen M. Cameron 2649846590eSStephen M. Cameron struct offline_device_entry { 2659846590eSStephen M. Cameron unsigned char scsi3addr[8]; 2669846590eSStephen M. Cameron struct list_head offline_list; 2679846590eSStephen M. Cameron }; 2689846590eSStephen M. Cameron 269edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 270edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 27164670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 27264670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 27364670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_TARGET 0x03 27464670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 275edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 276516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 277edd16368SStephen M. Cameron 278edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 279edd16368SStephen M. Cameron * when polling before giving up. 280edd16368SStephen M. Cameron */ 281edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 282edd16368SStephen M. Cameron 283edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 284edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 285edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 286edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 287edd16368SStephen M. Cameron * between sending TURs while waiting for a device 288edd16368SStephen M. Cameron * to become ready. 289edd16368SStephen M. Cameron */ 290edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 291edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 292edd16368SStephen M. Cameron 293edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 294edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 295edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 296edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 297edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 298edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 299edd16368SStephen M. Cameron */ 300edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3012ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 302edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 303edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 304edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 305edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 306edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 307edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 308fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 309fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 310fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 311edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 312edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 313edd16368SStephen M. Cameron 314edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 315edd16368SStephen M. Cameron /* 316edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 317edd16368SStephen M. Cameron */ 318edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 319edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 320281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 321281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 322edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 323edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 324edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 325edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 326edd16368SStephen M. Cameron 327edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 328edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 329edd16368SStephen M. Cameron 330edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 331edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 332edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 333edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 334edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 335edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 336edd16368SStephen M. Cameron 337edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 338edd16368SStephen M. Cameron 339303932fdSDon Brace /* Performant mode flags */ 340303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 341303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 342303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 343303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 344303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 345303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 346303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 347303932fdSDon Brace 348303932fdSDon Brace 349edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 350edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 351b66cc250SMike Miller 352b66cc250SMike Miller /* 353b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 354b66cc250SMike Miller */ 355b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 356b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 357b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 358b66cc250SMike Miller 359edd16368SStephen M. Cameron /* 360edd16368SStephen M. Cameron Send the command to the hardware 361edd16368SStephen M. Cameron */ 362edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 363edd16368SStephen M. Cameron struct CommandList *c) 364edd16368SStephen M. Cameron { 365edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 366fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 367edd16368SStephen M. Cameron } 368edd16368SStephen M. Cameron 369b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 370b3a52e79SStephen M. Cameron struct CommandList *c) 371b3a52e79SStephen M. Cameron { 372b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 373b3a52e79SStephen M. Cameron } 374b3a52e79SStephen M. Cameron 375c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 376c349775eSScott Teel struct CommandList *c) 377c349775eSScott Teel { 378c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 379c349775eSScott Teel } 380c349775eSScott Teel 381edd16368SStephen M. Cameron /* 382edd16368SStephen M. Cameron * This card is the opposite of the other cards. 383edd16368SStephen M. Cameron * 0 turns interrupts on... 384edd16368SStephen M. Cameron * 0x08 turns them off... 385edd16368SStephen M. Cameron */ 386edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 387edd16368SStephen M. Cameron { 388edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 389edd16368SStephen M. Cameron h->interrupts_enabled = 1; 390edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 3918cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 392edd16368SStephen M. Cameron } else { /* Turn them off */ 393edd16368SStephen M. Cameron h->interrupts_enabled = 0; 394edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 395edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 3968cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 397edd16368SStephen M. Cameron } 398edd16368SStephen M. Cameron } 399303932fdSDon Brace 400303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 401303932fdSDon Brace { 402303932fdSDon Brace if (val) { /* turn on interrupts */ 403303932fdSDon Brace h->interrupts_enabled = 1; 404303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4058cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 406303932fdSDon Brace } else { 407303932fdSDon Brace h->interrupts_enabled = 0; 408303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 409303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4108cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 411303932fdSDon Brace } 412303932fdSDon Brace } 413303932fdSDon Brace 414254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 415303932fdSDon Brace { 416072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4170cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 418303932fdSDon Brace 4192c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 420bee266a6SDon Brace if (unlikely(!(h->msi_vector || h->msix_vector))) { 421303932fdSDon Brace /* flush the controller write of the reply queue by reading 422303932fdSDon Brace * outbound doorbell status register. 423303932fdSDon Brace */ 424bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 425303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 426303932fdSDon Brace /* Do a read in order to flush the write to the controller 427303932fdSDon Brace * (as per spec.) 428303932fdSDon Brace */ 429bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 430303932fdSDon Brace } 431303932fdSDon Brace 432bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 433254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 434254f796bSMatt Gates rq->current_entry++; 4350cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 436303932fdSDon Brace } else { 437303932fdSDon Brace register_value = FIFO_EMPTY; 438303932fdSDon Brace } 439303932fdSDon Brace /* Check for wraparound */ 440254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 441254f796bSMatt Gates rq->current_entry = 0; 442254f796bSMatt Gates rq->wraparound ^= 1; 443303932fdSDon Brace } 444303932fdSDon Brace return register_value; 445303932fdSDon Brace } 446303932fdSDon Brace 447edd16368SStephen M. Cameron /* 448edd16368SStephen M. Cameron * returns value read from hardware. 449edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 450edd16368SStephen M. Cameron */ 451254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 452254f796bSMatt Gates __attribute__((unused)) u8 q) 453edd16368SStephen M. Cameron { 454edd16368SStephen M. Cameron unsigned long register_value 455edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 456edd16368SStephen M. Cameron 4570cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 4580cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 459edd16368SStephen M. Cameron 460edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 461edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 46284ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 463edd16368SStephen M. Cameron register_value); 464edd16368SStephen M. Cameron else 465f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 466edd16368SStephen M. Cameron #endif 467edd16368SStephen M. Cameron 468edd16368SStephen M. Cameron return register_value; 469edd16368SStephen M. Cameron } 470edd16368SStephen M. Cameron /* 471edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 472edd16368SStephen M. Cameron */ 473900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 474edd16368SStephen M. Cameron { 475edd16368SStephen M. Cameron unsigned long register_value = 476edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 477900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 478edd16368SStephen M. Cameron } 479edd16368SStephen M. Cameron 480303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 481303932fdSDon Brace { 482303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 483303932fdSDon Brace 484303932fdSDon Brace if (!register_value) 485303932fdSDon Brace return false; 486303932fdSDon Brace 487303932fdSDon Brace /* Read outbound doorbell to flush */ 488303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 489303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 490303932fdSDon Brace } 491edd16368SStephen M. Cameron 492e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 493e1f7de0cSMatt Gates 494e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 495e1f7de0cSMatt Gates { 496e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 497e1f7de0cSMatt Gates 498e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 499e1f7de0cSMatt Gates true : false; 500e1f7de0cSMatt Gates } 501e1f7de0cSMatt Gates 502e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 503e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 504e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 505e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 506e1f7de0cSMatt Gates 507283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 508e1f7de0cSMatt Gates { 509e1f7de0cSMatt Gates u64 register_value; 510072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 511e1f7de0cSMatt Gates 512e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 513e1f7de0cSMatt Gates 514e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 515e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 516e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 517e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 518e1f7de0cSMatt Gates rq->current_entry = 0; 519283b4a9bSStephen M. Cameron /* 520283b4a9bSStephen M. Cameron * @todo 521283b4a9bSStephen M. Cameron * 522283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 523283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 524283b4a9bSStephen M. Cameron */ 525283b4a9bSStephen M. Cameron wmb(); 526283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 527283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5280cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 529e1f7de0cSMatt Gates } 530e1f7de0cSMatt Gates return (unsigned long) register_value; 531e1f7de0cSMatt Gates } 532e1f7de0cSMatt Gates 533edd16368SStephen M. Cameron static struct access_method SA5_access = { 534edd16368SStephen M. Cameron SA5_submit_command, 535edd16368SStephen M. Cameron SA5_intr_mask, 536edd16368SStephen M. Cameron SA5_intr_pending, 537edd16368SStephen M. Cameron SA5_completed, 538edd16368SStephen M. Cameron }; 539edd16368SStephen M. Cameron 540e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 541e1f7de0cSMatt Gates SA5_submit_command, 542e1f7de0cSMatt Gates SA5_performant_intr_mask, 543e1f7de0cSMatt Gates SA5_ioaccel_mode1_intr_pending, 544e1f7de0cSMatt Gates SA5_ioaccel_mode1_completed, 545e1f7de0cSMatt Gates }; 546e1f7de0cSMatt Gates 547c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 548c349775eSScott Teel SA5_submit_command_ioaccel2, 549c349775eSScott Teel SA5_performant_intr_mask, 550c349775eSScott Teel SA5_performant_intr_pending, 551c349775eSScott Teel SA5_performant_completed, 552c349775eSScott Teel }; 553c349775eSScott Teel 554303932fdSDon Brace static struct access_method SA5_performant_access = { 555303932fdSDon Brace SA5_submit_command, 556303932fdSDon Brace SA5_performant_intr_mask, 557303932fdSDon Brace SA5_performant_intr_pending, 558303932fdSDon Brace SA5_performant_completed, 559303932fdSDon Brace }; 560303932fdSDon Brace 561b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 562b3a52e79SStephen M. Cameron SA5_submit_command_no_read, 563b3a52e79SStephen M. Cameron SA5_performant_intr_mask, 564b3a52e79SStephen M. Cameron SA5_performant_intr_pending, 565b3a52e79SStephen M. Cameron SA5_performant_completed, 566b3a52e79SStephen M. Cameron }; 567b3a52e79SStephen M. Cameron 568edd16368SStephen M. Cameron struct board_type { 56901a02ffcSStephen M. Cameron u32 board_id; 570edd16368SStephen M. Cameron char *product_name; 571edd16368SStephen M. Cameron struct access_method *access; 572edd16368SStephen M. Cameron }; 573edd16368SStephen M. Cameron 574edd16368SStephen M. Cameron #endif /* HPSA_H */ 575edd16368SStephen M. Cameron 576