1edd16368SStephen M. Cameron /* 2edd16368SStephen M. Cameron * Disk Array driver for HP Smart Array SAS controllers 31358f6dcSDon Brace * Copyright 2014-2015 PMC-Sierra, Inc. 41358f6dcSDon Brace * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 5edd16368SStephen M. Cameron * 6edd16368SStephen M. Cameron * This program is free software; you can redistribute it and/or modify 7edd16368SStephen M. Cameron * it under the terms of the GNU General Public License as published by 8edd16368SStephen M. Cameron * the Free Software Foundation; version 2 of the License. 9edd16368SStephen M. Cameron * 10edd16368SStephen M. Cameron * This program is distributed in the hope that it will be useful, 11edd16368SStephen M. Cameron * but WITHOUT ANY WARRANTY; without even the implied warranty of 12edd16368SStephen M. Cameron * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13edd16368SStephen M. Cameron * NON INFRINGEMENT. See the GNU General Public License for more details. 14edd16368SStephen M. Cameron * 151358f6dcSDon Brace * Questions/Comments/Bugfixes to storagedev@pmcs.com 16edd16368SStephen M. Cameron * 17edd16368SStephen M. Cameron */ 18edd16368SStephen M. Cameron #ifndef HPSA_H 19edd16368SStephen M. Cameron #define HPSA_H 20edd16368SStephen M. Cameron 21edd16368SStephen M. Cameron #include <scsi/scsicam.h> 22edd16368SStephen M. Cameron 23edd16368SStephen M. Cameron #define IO_OK 0 24edd16368SStephen M. Cameron #define IO_ERROR 1 25edd16368SStephen M. Cameron 26edd16368SStephen M. Cameron struct ctlr_info; 27edd16368SStephen M. Cameron 28edd16368SStephen M. Cameron struct access_method { 29edd16368SStephen M. Cameron void (*submit_command)(struct ctlr_info *h, 30edd16368SStephen M. Cameron struct CommandList *c); 31edd16368SStephen M. Cameron void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); 32900c5440SStephen M. Cameron bool (*intr_pending)(struct ctlr_info *h); 33254f796bSMatt Gates unsigned long (*command_completed)(struct ctlr_info *h, u8 q); 34edd16368SStephen M. Cameron }; 35edd16368SStephen M. Cameron 36edd16368SStephen M. Cameron struct hpsa_scsi_dev_t { 37edd16368SStephen M. Cameron int devtype; 38edd16368SStephen M. Cameron int bus, target, lun; /* as presented to the OS */ 39edd16368SStephen M. Cameron unsigned char scsi3addr[8]; /* as presented to the HW */ 40edd16368SStephen M. Cameron #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" 41edd16368SStephen M. Cameron unsigned char device_id[16]; /* from inquiry pg. 0x83 */ 42edd16368SStephen M. Cameron unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ 43edd16368SStephen M. Cameron unsigned char model[16]; /* bytes 16-31 of inquiry data */ 44edd16368SStephen M. Cameron unsigned char raid_level; /* from inquiry page 0xC1 */ 459846590eSStephen M. Cameron unsigned char volume_offline; /* discovered via TUR or VPD */ 4603383736SDon Brace u16 queue_depth; /* max queue_depth for this device */ 47d604f533SWebb Scales atomic_t reset_cmds_out; /* Count of commands to-be affected */ 4803383736SDon Brace atomic_t ioaccel_cmds_out; /* Only used for physical devices 4903383736SDon Brace * counts commands sent to physical 5003383736SDon Brace * device via "ioaccel" path. 5103383736SDon Brace */ 52e1f7de0cSMatt Gates u32 ioaccel_handle; 53283b4a9bSStephen M. Cameron int offload_config; /* I/O accel RAID offload configured */ 54283b4a9bSStephen M. Cameron int offload_enabled; /* I/O accel RAID offload enabled */ 5541ce4c35SStephen Cameron int offload_to_be_enabled; 56a3144e0bSJoe Handzik int hba_ioaccel_enabled; 57283b4a9bSStephen M. Cameron int offload_to_mirror; /* Send next I/O accelerator RAID 58283b4a9bSStephen M. Cameron * offload request to mirror drive 59283b4a9bSStephen M. Cameron */ 60283b4a9bSStephen M. Cameron struct raid_map_data raid_map; /* I/O accelerator RAID map */ 61283b4a9bSStephen M. Cameron 6203383736SDon Brace /* 6303383736SDon Brace * Pointers from logical drive map indices to the phys drives that 6403383736SDon Brace * make those logical drives. Note, multiple logical drives may 6503383736SDon Brace * share physical drives. You can have for instance 5 physical 6603383736SDon Brace * drives with 3 logical drives each using those same 5 physical 6703383736SDon Brace * disks. We need these pointers for counting i/o's out to physical 6803383736SDon Brace * devices in order to honor physical device queue depth limits. 6903383736SDon Brace */ 7003383736SDon Brace struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; 71d604f533SWebb Scales int nphysical_disks; 729b5c48c2SStephen Cameron int supports_aborts; 7341ce4c35SStephen Cameron #define HPSA_DO_NOT_EXPOSE 0x0 7441ce4c35SStephen Cameron #define HPSA_SG_ATTACH 0x1 7541ce4c35SStephen Cameron #define HPSA_ULD_ATTACH 0x2 7641ce4c35SStephen Cameron #define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH) 7741ce4c35SStephen Cameron u8 expose_state; 78edd16368SStephen M. Cameron }; 79edd16368SStephen M. Cameron 80072b0518SStephen M. Cameron struct reply_queue_buffer { 81254f796bSMatt Gates u64 *head; 82254f796bSMatt Gates size_t size; 83254f796bSMatt Gates u8 wraparound; 84254f796bSMatt Gates u32 current_entry; 85072b0518SStephen M. Cameron dma_addr_t busaddr; 86254f796bSMatt Gates }; 87254f796bSMatt Gates 88316b221aSStephen M. Cameron #pragma pack(1) 89316b221aSStephen M. Cameron struct bmic_controller_parameters { 90316b221aSStephen M. Cameron u8 led_flags; 91316b221aSStephen M. Cameron u8 enable_command_list_verification; 92316b221aSStephen M. Cameron u8 backed_out_write_drives; 93316b221aSStephen M. Cameron u16 stripes_for_parity; 94316b221aSStephen M. Cameron u8 parity_distribution_mode_flags; 95316b221aSStephen M. Cameron u16 max_driver_requests; 96316b221aSStephen M. Cameron u16 elevator_trend_count; 97316b221aSStephen M. Cameron u8 disable_elevator; 98316b221aSStephen M. Cameron u8 force_scan_complete; 99316b221aSStephen M. Cameron u8 scsi_transfer_mode; 100316b221aSStephen M. Cameron u8 force_narrow; 101316b221aSStephen M. Cameron u8 rebuild_priority; 102316b221aSStephen M. Cameron u8 expand_priority; 103316b221aSStephen M. Cameron u8 host_sdb_asic_fix; 104316b221aSStephen M. Cameron u8 pdpi_burst_from_host_disabled; 105316b221aSStephen M. Cameron char software_name[64]; 106316b221aSStephen M. Cameron char hardware_name[32]; 107316b221aSStephen M. Cameron u8 bridge_revision; 108316b221aSStephen M. Cameron u8 snapshot_priority; 109316b221aSStephen M. Cameron u32 os_specific; 110316b221aSStephen M. Cameron u8 post_prompt_timeout; 111316b221aSStephen M. Cameron u8 automatic_drive_slamming; 112316b221aSStephen M. Cameron u8 reserved1; 113316b221aSStephen M. Cameron u8 nvram_flags; 1146e8e8088SJoe Handzik #define HBA_MODE_ENABLED_FLAG (1 << 3) 115316b221aSStephen M. Cameron u8 cache_nvram_flags; 116316b221aSStephen M. Cameron u8 drive_config_flags; 117316b221aSStephen M. Cameron u16 reserved2; 118316b221aSStephen M. Cameron u8 temp_warning_level; 119316b221aSStephen M. Cameron u8 temp_shutdown_level; 120316b221aSStephen M. Cameron u8 temp_condition_reset; 121316b221aSStephen M. Cameron u8 max_coalesce_commands; 122316b221aSStephen M. Cameron u32 max_coalesce_delay; 123316b221aSStephen M. Cameron u8 orca_password[4]; 124316b221aSStephen M. Cameron u8 access_id[16]; 125316b221aSStephen M. Cameron u8 reserved[356]; 126316b221aSStephen M. Cameron }; 127316b221aSStephen M. Cameron #pragma pack() 128316b221aSStephen M. Cameron 129edd16368SStephen M. Cameron struct ctlr_info { 130edd16368SStephen M. Cameron int ctlr; 131edd16368SStephen M. Cameron char devname[8]; 132edd16368SStephen M. Cameron char *product_name; 133edd16368SStephen M. Cameron struct pci_dev *pdev; 13401a02ffcSStephen M. Cameron u32 board_id; 135edd16368SStephen M. Cameron void __iomem *vaddr; 136edd16368SStephen M. Cameron unsigned long paddr; 137edd16368SStephen M. Cameron int nr_cmds; /* Number of commands allowed on this controller */ 138d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 139d54c5c24SStephen Cameron #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 140edd16368SStephen M. Cameron struct CfgTable __iomem *cfgtable; 141edd16368SStephen M. Cameron int interrupts_enabled; 142edd16368SStephen M. Cameron int max_commands; 1430cbf768eSStephen M. Cameron atomic_t commands_outstanding; 144303932fdSDon Brace # define PERF_MODE_INT 0 145303932fdSDon Brace # define DOORBELL_INT 1 146edd16368SStephen M. Cameron # define SIMPLE_MODE_INT 2 147edd16368SStephen M. Cameron # define MEMQ_MODE_INT 3 148254f796bSMatt Gates unsigned int intr[MAX_REPLY_QUEUES]; 149edd16368SStephen M. Cameron unsigned int msix_vector; 150edd16368SStephen M. Cameron unsigned int msi_vector; 151a9a3a273SStephen M. Cameron int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ 152edd16368SStephen M. Cameron struct access_method access; 153316b221aSStephen M. Cameron char hba_mode_enabled; 154edd16368SStephen M. Cameron 155edd16368SStephen M. Cameron /* queue and queue Info */ 156edd16368SStephen M. Cameron unsigned int Qdepth; 157edd16368SStephen M. Cameron unsigned int maxSG; 158edd16368SStephen M. Cameron spinlock_t lock; 15933a2ffceSStephen M. Cameron int maxsgentries; 16033a2ffceSStephen M. Cameron u8 max_cmd_sg_entries; 16133a2ffceSStephen M. Cameron int chainsize; 16233a2ffceSStephen M. Cameron struct SGDescriptor **cmd_sg_list; 163d9a729f3SWebb Scales struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; 164edd16368SStephen M. Cameron 165edd16368SStephen M. Cameron /* pointers to command and error info pool */ 166edd16368SStephen M. Cameron struct CommandList *cmd_pool; 167edd16368SStephen M. Cameron dma_addr_t cmd_pool_dhandle; 168e1f7de0cSMatt Gates struct io_accel1_cmd *ioaccel_cmd_pool; 169e1f7de0cSMatt Gates dma_addr_t ioaccel_cmd_pool_dhandle; 170aca9012aSStephen M. Cameron struct io_accel2_cmd *ioaccel2_cmd_pool; 171aca9012aSStephen M. Cameron dma_addr_t ioaccel2_cmd_pool_dhandle; 172edd16368SStephen M. Cameron struct ErrorInfo *errinfo_pool; 173edd16368SStephen M. Cameron dma_addr_t errinfo_pool_dhandle; 174edd16368SStephen M. Cameron unsigned long *cmd_pool_bits; 175a08a8471SStephen M. Cameron int scan_finished; 176a08a8471SStephen M. Cameron spinlock_t scan_lock; 177a08a8471SStephen M. Cameron wait_queue_head_t scan_wait_queue; 178edd16368SStephen M. Cameron 179edd16368SStephen M. Cameron struct Scsi_Host *scsi_host; 180edd16368SStephen M. Cameron spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ 181edd16368SStephen M. Cameron int ndevices; /* number of used elements in .dev[] array. */ 182cfe5badcSScott Teel struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; 183303932fdSDon Brace /* 184303932fdSDon Brace * Performant mode tables. 185303932fdSDon Brace */ 186303932fdSDon Brace u32 trans_support; 187303932fdSDon Brace u32 trans_offset; 18842a91641SDon Brace struct TransTable_struct __iomem *transtable; 189303932fdSDon Brace unsigned long transMethod; 190303932fdSDon Brace 1910390f0c0SStephen M. Cameron /* cap concurrent passthrus at some reasonable maximum */ 19245fcb86eSStephen Cameron #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) 19334f0c627SDon Brace atomic_t passthru_cmds_avail; 1940390f0c0SStephen M. Cameron 195303932fdSDon Brace /* 196254f796bSMatt Gates * Performant mode completion buffers 197303932fdSDon Brace */ 198072b0518SStephen M. Cameron size_t reply_queue_size; 199072b0518SStephen M. Cameron struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; 200254f796bSMatt Gates u8 nreply_queues; 201303932fdSDon Brace u32 *blockFetchTable; 202e1f7de0cSMatt Gates u32 *ioaccel1_blockFetchTable; 203aca9012aSStephen M. Cameron u32 *ioaccel2_blockFetchTable; 20442a91641SDon Brace u32 __iomem *ioaccel2_bft2_regs; 205339b2b14SStephen M. Cameron unsigned char *hba_inquiry_data; 206283b4a9bSStephen M. Cameron u32 driver_support; 207283b4a9bSStephen M. Cameron u32 fw_support; 208283b4a9bSStephen M. Cameron int ioaccel_support; 209283b4a9bSStephen M. Cameron int ioaccel_maxsg; 210a0c12413SStephen M. Cameron u64 last_intr_timestamp; 211a0c12413SStephen M. Cameron u32 last_heartbeat; 212a0c12413SStephen M. Cameron u64 last_heartbeat_timestamp; 213e85c5974SStephen M. Cameron u32 heartbeat_sample_interval; 214e85c5974SStephen M. Cameron atomic_t firmware_flash_in_progress; 21542a91641SDon Brace u32 __percpu *lockup_detected; 2168a98db73SStephen M. Cameron struct delayed_work monitor_ctlr_work; 2176636e7f4SDon Brace struct delayed_work rescan_ctlr_work; 2188a98db73SStephen M. Cameron int remove_in_progress; 219254f796bSMatt Gates /* Address of h->q[x] is passed to intr handler to know which queue */ 220254f796bSMatt Gates u8 q[MAX_REPLY_QUEUES]; 2218b47004aSRobert Elliott char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ 22275167d2cSStephen M. Cameron u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ 22375167d2cSStephen M. Cameron #define HPSATMF_BITS_SUPPORTED (1 << 0) 22475167d2cSStephen M. Cameron #define HPSATMF_PHYS_LUN_RESET (1 << 1) 22575167d2cSStephen M. Cameron #define HPSATMF_PHYS_NEX_RESET (1 << 2) 22675167d2cSStephen M. Cameron #define HPSATMF_PHYS_TASK_ABORT (1 << 3) 22775167d2cSStephen M. Cameron #define HPSATMF_PHYS_TSET_ABORT (1 << 4) 22875167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) 22975167d2cSStephen M. Cameron #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) 23075167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TASK (1 << 7) 23175167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_TSET (1 << 8) 23275167d2cSStephen M. Cameron #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) 2338be986ccSStephen Cameron #define HPSATMF_IOACCEL_ENABLED (1 << 15) 23475167d2cSStephen M. Cameron #define HPSATMF_MASK_SUPPORTED (1 << 16) 23575167d2cSStephen M. Cameron #define HPSATMF_LOG_LUN_RESET (1 << 17) 23675167d2cSStephen M. Cameron #define HPSATMF_LOG_NEX_RESET (1 << 18) 23775167d2cSStephen M. Cameron #define HPSATMF_LOG_TASK_ABORT (1 << 19) 23875167d2cSStephen M. Cameron #define HPSATMF_LOG_TSET_ABORT (1 << 20) 23975167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_ACA (1 << 21) 24075167d2cSStephen M. Cameron #define HPSATMF_LOG_CLEAR_TSET (1 << 22) 24175167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TASK (1 << 23) 24275167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_TSET (1 << 24) 24375167d2cSStephen M. Cameron #define HPSATMF_LOG_QRY_ASYNC (1 << 25) 24476438d08SStephen M. Cameron u32 events; 245faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT (1 << 0) 246faff6ee0SStephen M. Cameron #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) 247faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) 248faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) 249faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) 250faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) 251faff6ee0SStephen M. Cameron #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) 252faff6ee0SStephen M. Cameron 253faff6ee0SStephen M. Cameron #define RESCAN_REQUIRED_EVENT_BITS \ 2547b2c46eeSStephen M. Cameron (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ 255faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ 256faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ 257faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ 258faff6ee0SStephen M. Cameron CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) 2599846590eSStephen M. Cameron spinlock_t offline_device_lock; 2609846590eSStephen M. Cameron struct list_head offline_device_list; 261da0697bdSScott Teel int acciopath_status; 2622ba8bfc8SStephen M. Cameron int raid_offload_debug; 2639b5c48c2SStephen Cameron int needs_abort_tags_swizzled; 264080ef1ccSDon Brace struct workqueue_struct *resubmit_wq; 2656636e7f4SDon Brace struct workqueue_struct *rescan_ctlr_wq; 2669b5c48c2SStephen Cameron atomic_t abort_cmds_available; 2679b5c48c2SStephen Cameron wait_queue_head_t abort_cmd_wait_queue; 268d604f533SWebb Scales wait_queue_head_t event_sync_wait_queue; 269d604f533SWebb Scales struct mutex reset_mutex; 270edd16368SStephen M. Cameron }; 2719846590eSStephen M. Cameron 2729846590eSStephen M. Cameron struct offline_device_entry { 2739846590eSStephen M. Cameron unsigned char scsi3addr[8]; 2749846590eSStephen M. Cameron struct list_head offline_list; 2759846590eSStephen M. Cameron }; 2769846590eSStephen M. Cameron 277edd16368SStephen M. Cameron #define HPSA_ABORT_MSG 0 278edd16368SStephen M. Cameron #define HPSA_DEVICE_RESET_MSG 1 27964670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_CONTROLLER 0x00 28064670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_BUS 0x01 28164670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_TARGET 0x03 28264670ac8SStephen M. Cameron #define HPSA_RESET_TYPE_LUN 0x04 283edd16368SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_LIMIT 10 284516fda49SStephen M. Cameron #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) 285edd16368SStephen M. Cameron 286edd16368SStephen M. Cameron /* Maximum time in seconds driver will wait for command completions 287edd16368SStephen M. Cameron * when polling before giving up. 288edd16368SStephen M. Cameron */ 289edd16368SStephen M. Cameron #define HPSA_MAX_POLL_TIME_SECS (20) 290edd16368SStephen M. Cameron 291edd16368SStephen M. Cameron /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines 292edd16368SStephen M. Cameron * how many times to retry TEST UNIT READY on a device 293edd16368SStephen M. Cameron * while waiting for it to become ready before giving up. 294edd16368SStephen M. Cameron * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval 295edd16368SStephen M. Cameron * between sending TURs while waiting for a device 296edd16368SStephen M. Cameron * to become ready. 297edd16368SStephen M. Cameron */ 298edd16368SStephen M. Cameron #define HPSA_TUR_RETRY_LIMIT (20) 299edd16368SStephen M. Cameron #define HPSA_MAX_WAIT_INTERVAL_SECS (30) 300edd16368SStephen M. Cameron 301edd16368SStephen M. Cameron /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board 302edd16368SStephen M. Cameron * to become ready, in seconds, before giving up on it. 303edd16368SStephen M. Cameron * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait 304edd16368SStephen M. Cameron * between polling the board to see if it is ready, in 305edd16368SStephen M. Cameron * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and 306edd16368SStephen M. Cameron * HPSA_BOARD_READY_ITERATIONS are derived from those. 307edd16368SStephen M. Cameron */ 308edd16368SStephen M. Cameron #define HPSA_BOARD_READY_WAIT_SECS (120) 3092ed7127bSStephen M. Cameron #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) 310edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) 311edd16368SStephen M. Cameron #define HPSA_BOARD_READY_POLL_INTERVAL \ 312edd16368SStephen M. Cameron ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) 313edd16368SStephen M. Cameron #define HPSA_BOARD_READY_ITERATIONS \ 314edd16368SStephen M. Cameron ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ 315edd16368SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 316fe5389c8SStephen M. Cameron #define HPSA_BOARD_NOT_READY_ITERATIONS \ 317fe5389c8SStephen M. Cameron ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ 318fe5389c8SStephen M. Cameron HPSA_BOARD_READY_POLL_INTERVAL_MSECS) 319edd16368SStephen M. Cameron #define HPSA_POST_RESET_PAUSE_MSECS (3000) 320edd16368SStephen M. Cameron #define HPSA_POST_RESET_NOOP_RETRIES (12) 321edd16368SStephen M. Cameron 322edd16368SStephen M. Cameron /* Defining the diffent access_menthods */ 323edd16368SStephen M. Cameron /* 324edd16368SStephen M. Cameron * Memory mapped FIFO interface (SMART 53xx cards) 325edd16368SStephen M. Cameron */ 326edd16368SStephen M. Cameron #define SA5_DOORBELL 0x20 327edd16368SStephen M. Cameron #define SA5_REQUEST_PORT_OFFSET 0x40 328281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 329281a7fd0SWebb Scales #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 330edd16368SStephen M. Cameron #define SA5_REPLY_INTR_MASK_OFFSET 0x34 331edd16368SStephen M. Cameron #define SA5_REPLY_PORT_OFFSET 0x44 332edd16368SStephen M. Cameron #define SA5_INTR_STATUS 0x30 333edd16368SStephen M. Cameron #define SA5_SCRATCHPAD_OFFSET 0xB0 334edd16368SStephen M. Cameron 335edd16368SStephen M. Cameron #define SA5_CTCFG_OFFSET 0xB4 336edd16368SStephen M. Cameron #define SA5_CTMEM_OFFSET 0xB8 337edd16368SStephen M. Cameron 338edd16368SStephen M. Cameron #define SA5_INTR_OFF 0x08 339edd16368SStephen M. Cameron #define SA5B_INTR_OFF 0x04 340edd16368SStephen M. Cameron #define SA5_INTR_PENDING 0x08 341edd16368SStephen M. Cameron #define SA5B_INTR_PENDING 0x04 342edd16368SStephen M. Cameron #define FIFO_EMPTY 0xffffffff 343edd16368SStephen M. Cameron #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ 344edd16368SStephen M. Cameron 345edd16368SStephen M. Cameron #define HPSA_ERROR_BIT 0x02 346edd16368SStephen M. Cameron 347303932fdSDon Brace /* Performant mode flags */ 348303932fdSDon Brace #define SA5_PERF_INTR_PENDING 0x04 349303932fdSDon Brace #define SA5_PERF_INTR_OFF 0x05 350303932fdSDon Brace #define SA5_OUTDB_STATUS_PERF_BIT 0x01 351303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 352303932fdSDon Brace #define SA5_OUTDB_CLEAR 0xA0 353303932fdSDon Brace #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 354303932fdSDon Brace #define SA5_OUTDB_STATUS 0x9C 355303932fdSDon Brace 356303932fdSDon Brace 357edd16368SStephen M. Cameron #define HPSA_INTR_ON 1 358edd16368SStephen M. Cameron #define HPSA_INTR_OFF 0 359b66cc250SMike Miller 360b66cc250SMike Miller /* 361b66cc250SMike Miller * Inbound Post Queue offsets for IO Accelerator Mode 2 362b66cc250SMike Miller */ 363b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_32 0x48 364b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 365b66cc250SMike Miller #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 366b66cc250SMike Miller 367edd16368SStephen M. Cameron /* 368edd16368SStephen M. Cameron Send the command to the hardware 369edd16368SStephen M. Cameron */ 370edd16368SStephen M. Cameron static void SA5_submit_command(struct ctlr_info *h, 371edd16368SStephen M. Cameron struct CommandList *c) 372edd16368SStephen M. Cameron { 373edd16368SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 374fec62c36SStephen M. Cameron (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 375edd16368SStephen M. Cameron } 376edd16368SStephen M. Cameron 377b3a52e79SStephen M. Cameron static void SA5_submit_command_no_read(struct ctlr_info *h, 378b3a52e79SStephen M. Cameron struct CommandList *c) 379b3a52e79SStephen M. Cameron { 380b3a52e79SStephen M. Cameron writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 381b3a52e79SStephen M. Cameron } 382b3a52e79SStephen M. Cameron 383c349775eSScott Teel static void SA5_submit_command_ioaccel2(struct ctlr_info *h, 384c349775eSScott Teel struct CommandList *c) 385c349775eSScott Teel { 386c349775eSScott Teel writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 387c349775eSScott Teel } 388c349775eSScott Teel 389edd16368SStephen M. Cameron /* 390edd16368SStephen M. Cameron * This card is the opposite of the other cards. 391edd16368SStephen M. Cameron * 0 turns interrupts on... 392edd16368SStephen M. Cameron * 0x08 turns them off... 393edd16368SStephen M. Cameron */ 394edd16368SStephen M. Cameron static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) 395edd16368SStephen M. Cameron { 396edd16368SStephen M. Cameron if (val) { /* Turn interrupts on */ 397edd16368SStephen M. Cameron h->interrupts_enabled = 1; 398edd16368SStephen M. Cameron writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 3998cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 400edd16368SStephen M. Cameron } else { /* Turn them off */ 401edd16368SStephen M. Cameron h->interrupts_enabled = 0; 402edd16368SStephen M. Cameron writel(SA5_INTR_OFF, 403edd16368SStephen M. Cameron h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4048cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 405edd16368SStephen M. Cameron } 406edd16368SStephen M. Cameron } 407303932fdSDon Brace 408303932fdSDon Brace static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) 409303932fdSDon Brace { 410303932fdSDon Brace if (val) { /* turn on interrupts */ 411303932fdSDon Brace h->interrupts_enabled = 1; 412303932fdSDon Brace writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4138cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 414303932fdSDon Brace } else { 415303932fdSDon Brace h->interrupts_enabled = 0; 416303932fdSDon Brace writel(SA5_PERF_INTR_OFF, 417303932fdSDon Brace h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 4188cd21da7SStephen M. Cameron (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); 419303932fdSDon Brace } 420303932fdSDon Brace } 421303932fdSDon Brace 422254f796bSMatt Gates static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) 423303932fdSDon Brace { 424072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 4250cbf768eSStephen M. Cameron unsigned long register_value = FIFO_EMPTY; 426303932fdSDon Brace 4272c17d2daSStephen M. Cameron /* msi auto clears the interrupt pending bit. */ 428bee266a6SDon Brace if (unlikely(!(h->msi_vector || h->msix_vector))) { 429303932fdSDon Brace /* flush the controller write of the reply queue by reading 430303932fdSDon Brace * outbound doorbell status register. 431303932fdSDon Brace */ 432bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 433303932fdSDon Brace writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); 434303932fdSDon Brace /* Do a read in order to flush the write to the controller 435303932fdSDon Brace * (as per spec.) 436303932fdSDon Brace */ 437bee266a6SDon Brace (void) readl(h->vaddr + SA5_OUTDB_STATUS); 438303932fdSDon Brace } 439303932fdSDon Brace 440bee266a6SDon Brace if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { 441254f796bSMatt Gates register_value = rq->head[rq->current_entry]; 442254f796bSMatt Gates rq->current_entry++; 4430cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 444303932fdSDon Brace } else { 445303932fdSDon Brace register_value = FIFO_EMPTY; 446303932fdSDon Brace } 447303932fdSDon Brace /* Check for wraparound */ 448254f796bSMatt Gates if (rq->current_entry == h->max_commands) { 449254f796bSMatt Gates rq->current_entry = 0; 450254f796bSMatt Gates rq->wraparound ^= 1; 451303932fdSDon Brace } 452303932fdSDon Brace return register_value; 453303932fdSDon Brace } 454303932fdSDon Brace 455edd16368SStephen M. Cameron /* 456edd16368SStephen M. Cameron * returns value read from hardware. 457edd16368SStephen M. Cameron * returns FIFO_EMPTY if there is nothing to read 458edd16368SStephen M. Cameron */ 459254f796bSMatt Gates static unsigned long SA5_completed(struct ctlr_info *h, 460254f796bSMatt Gates __attribute__((unused)) u8 q) 461edd16368SStephen M. Cameron { 462edd16368SStephen M. Cameron unsigned long register_value 463edd16368SStephen M. Cameron = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); 464edd16368SStephen M. Cameron 4650cbf768eSStephen M. Cameron if (register_value != FIFO_EMPTY) 4660cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 467edd16368SStephen M. Cameron 468edd16368SStephen M. Cameron #ifdef HPSA_DEBUG 469edd16368SStephen M. Cameron if (register_value != FIFO_EMPTY) 47084ca0be2SStephen M. Cameron dev_dbg(&h->pdev->dev, "Read %lx back from board\n", 471edd16368SStephen M. Cameron register_value); 472edd16368SStephen M. Cameron else 473f79cfec6SStephen M. Cameron dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); 474edd16368SStephen M. Cameron #endif 475edd16368SStephen M. Cameron 476edd16368SStephen M. Cameron return register_value; 477edd16368SStephen M. Cameron } 478edd16368SStephen M. Cameron /* 479edd16368SStephen M. Cameron * Returns true if an interrupt is pending.. 480edd16368SStephen M. Cameron */ 481900c5440SStephen M. Cameron static bool SA5_intr_pending(struct ctlr_info *h) 482edd16368SStephen M. Cameron { 483edd16368SStephen M. Cameron unsigned long register_value = 484edd16368SStephen M. Cameron readl(h->vaddr + SA5_INTR_STATUS); 485900c5440SStephen M. Cameron return register_value & SA5_INTR_PENDING; 486edd16368SStephen M. Cameron } 487edd16368SStephen M. Cameron 488303932fdSDon Brace static bool SA5_performant_intr_pending(struct ctlr_info *h) 489303932fdSDon Brace { 490303932fdSDon Brace unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 491303932fdSDon Brace 492303932fdSDon Brace if (!register_value) 493303932fdSDon Brace return false; 494303932fdSDon Brace 495303932fdSDon Brace /* Read outbound doorbell to flush */ 496303932fdSDon Brace register_value = readl(h->vaddr + SA5_OUTDB_STATUS); 497303932fdSDon Brace return register_value & SA5_OUTDB_STATUS_PERF_BIT; 498303932fdSDon Brace } 499edd16368SStephen M. Cameron 500e1f7de0cSMatt Gates #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 501e1f7de0cSMatt Gates 502e1f7de0cSMatt Gates static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) 503e1f7de0cSMatt Gates { 504e1f7de0cSMatt Gates unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); 505e1f7de0cSMatt Gates 506e1f7de0cSMatt Gates return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? 507e1f7de0cSMatt Gates true : false; 508e1f7de0cSMatt Gates } 509e1f7de0cSMatt Gates 510e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 511e1f7de0cSMatt Gates #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 512e1f7de0cSMatt Gates #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC 513e1f7de0cSMatt Gates #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL 514e1f7de0cSMatt Gates 515283b4a9bSStephen M. Cameron static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) 516e1f7de0cSMatt Gates { 517e1f7de0cSMatt Gates u64 register_value; 518072b0518SStephen M. Cameron struct reply_queue_buffer *rq = &h->reply_queue[q]; 519e1f7de0cSMatt Gates 520e1f7de0cSMatt Gates BUG_ON(q >= h->nreply_queues); 521e1f7de0cSMatt Gates 522e1f7de0cSMatt Gates register_value = rq->head[rq->current_entry]; 523e1f7de0cSMatt Gates if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { 524e1f7de0cSMatt Gates rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; 525e1f7de0cSMatt Gates if (++rq->current_entry == rq->size) 526e1f7de0cSMatt Gates rq->current_entry = 0; 527283b4a9bSStephen M. Cameron /* 528283b4a9bSStephen M. Cameron * @todo 529283b4a9bSStephen M. Cameron * 530283b4a9bSStephen M. Cameron * Don't really need to write the new index after each command, 531283b4a9bSStephen M. Cameron * but with current driver design this is easiest. 532283b4a9bSStephen M. Cameron */ 533283b4a9bSStephen M. Cameron wmb(); 534283b4a9bSStephen M. Cameron writel((q << 24) | rq->current_entry, h->vaddr + 535283b4a9bSStephen M. Cameron IOACCEL_MODE1_CONSUMER_INDEX); 5360cbf768eSStephen M. Cameron atomic_dec(&h->commands_outstanding); 537e1f7de0cSMatt Gates } 538e1f7de0cSMatt Gates return (unsigned long) register_value; 539e1f7de0cSMatt Gates } 540e1f7de0cSMatt Gates 541edd16368SStephen M. Cameron static struct access_method SA5_access = { 542edd16368SStephen M. Cameron SA5_submit_command, 543edd16368SStephen M. Cameron SA5_intr_mask, 544edd16368SStephen M. Cameron SA5_intr_pending, 545edd16368SStephen M. Cameron SA5_completed, 546edd16368SStephen M. Cameron }; 547edd16368SStephen M. Cameron 548e1f7de0cSMatt Gates static struct access_method SA5_ioaccel_mode1_access = { 549e1f7de0cSMatt Gates SA5_submit_command, 550e1f7de0cSMatt Gates SA5_performant_intr_mask, 551e1f7de0cSMatt Gates SA5_ioaccel_mode1_intr_pending, 552e1f7de0cSMatt Gates SA5_ioaccel_mode1_completed, 553e1f7de0cSMatt Gates }; 554e1f7de0cSMatt Gates 555c349775eSScott Teel static struct access_method SA5_ioaccel_mode2_access = { 556c349775eSScott Teel SA5_submit_command_ioaccel2, 557c349775eSScott Teel SA5_performant_intr_mask, 558c349775eSScott Teel SA5_performant_intr_pending, 559c349775eSScott Teel SA5_performant_completed, 560c349775eSScott Teel }; 561c349775eSScott Teel 562303932fdSDon Brace static struct access_method SA5_performant_access = { 563303932fdSDon Brace SA5_submit_command, 564303932fdSDon Brace SA5_performant_intr_mask, 565303932fdSDon Brace SA5_performant_intr_pending, 566303932fdSDon Brace SA5_performant_completed, 567303932fdSDon Brace }; 568303932fdSDon Brace 569b3a52e79SStephen M. Cameron static struct access_method SA5_performant_access_no_read = { 570b3a52e79SStephen M. Cameron SA5_submit_command_no_read, 571b3a52e79SStephen M. Cameron SA5_performant_intr_mask, 572b3a52e79SStephen M. Cameron SA5_performant_intr_pending, 573b3a52e79SStephen M. Cameron SA5_performant_completed, 574b3a52e79SStephen M. Cameron }; 575b3a52e79SStephen M. Cameron 576edd16368SStephen M. Cameron struct board_type { 57701a02ffcSStephen M. Cameron u32 board_id; 578edd16368SStephen M. Cameron char *product_name; 579edd16368SStephen M. Cameron struct access_method *access; 580edd16368SStephen M. Cameron }; 581edd16368SStephen M. Cameron 582edd16368SStephen M. Cameron #endif /* HPSA_H */ 583edd16368SStephen M. Cameron 584