1 /* 2 * Disk Array driver for HP Smart Array SAS controllers 3 * Copyright 2016 Microsemi Corporation 4 * Copyright 2014-2015 PMC-Sierra, Inc. 5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 14 * NON INFRINGEMENT. See the GNU General Public License for more details. 15 * 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/interrupt.h> 22 #include <linux/types.h> 23 #include <linux/pci.h> 24 #include <linux/pci-aspm.h> 25 #include <linux/kernel.h> 26 #include <linux/slab.h> 27 #include <linux/delay.h> 28 #include <linux/fs.h> 29 #include <linux/timer.h> 30 #include <linux/init.h> 31 #include <linux/spinlock.h> 32 #include <linux/compat.h> 33 #include <linux/blktrace_api.h> 34 #include <linux/uaccess.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/completion.h> 38 #include <linux/moduleparam.h> 39 #include <scsi/scsi.h> 40 #include <scsi/scsi_cmnd.h> 41 #include <scsi/scsi_device.h> 42 #include <scsi/scsi_host.h> 43 #include <scsi/scsi_tcq.h> 44 #include <scsi/scsi_eh.h> 45 #include <scsi/scsi_transport_sas.h> 46 #include <scsi/scsi_dbg.h> 47 #include <linux/cciss_ioctl.h> 48 #include <linux/string.h> 49 #include <linux/bitmap.h> 50 #include <linux/atomic.h> 51 #include <linux/jiffies.h> 52 #include <linux/percpu-defs.h> 53 #include <linux/percpu.h> 54 #include <asm/unaligned.h> 55 #include <asm/div64.h> 56 #include "hpsa_cmd.h" 57 #include "hpsa.h" 58 59 /* 60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' 61 * with an optional trailing '-' followed by a byte value (0-255). 62 */ 63 #define HPSA_DRIVER_VERSION "3.4.20-0" 64 #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" 65 #define HPSA "hpsa" 66 67 /* How long to wait for CISS doorbell communication */ 68 #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */ 69 #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */ 70 #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */ 71 #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */ 72 #define MAX_IOCTL_CONFIG_WAIT 1000 73 74 /*define how many times we will try a command because of bus resets */ 75 #define MAX_CMD_RETRIES 3 76 77 /* Embedded module documentation macros - see modules.h */ 78 MODULE_AUTHOR("Hewlett-Packard Company"); 79 MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ 80 HPSA_DRIVER_VERSION); 81 MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); 82 MODULE_VERSION(HPSA_DRIVER_VERSION); 83 MODULE_LICENSE("GPL"); 84 MODULE_ALIAS("cciss"); 85 86 static int hpsa_simple_mode; 87 module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); 88 MODULE_PARM_DESC(hpsa_simple_mode, 89 "Use 'simple mode' rather than 'performant mode'"); 90 91 /* define the PCI info for the cards we can control */ 92 static const struct pci_device_id hpsa_pci_device_id[] = { 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, 105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, 107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920}, 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925}, 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, 116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, 117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, 118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, 119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, 121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, 129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, 130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, 131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, 132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, 133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, 134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, 135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580}, 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581}, 137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582}, 138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583}, 139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584}, 140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585}, 141 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, 142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, 143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, 144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, 145 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, 146 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 147 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 148 {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 149 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, 150 {0,} 151 }; 152 153 MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); 154 155 /* board_id = Subsystem Device ID & Vendor ID 156 * product = Marketing Name for the board 157 * access = Address of the struct of function pointers 158 */ 159 static struct board_type products[] = { 160 {0x40700E11, "Smart Array 5300", &SA5A_access}, 161 {0x40800E11, "Smart Array 5i", &SA5B_access}, 162 {0x40820E11, "Smart Array 532", &SA5B_access}, 163 {0x40830E11, "Smart Array 5312", &SA5B_access}, 164 {0x409A0E11, "Smart Array 641", &SA5A_access}, 165 {0x409B0E11, "Smart Array 642", &SA5A_access}, 166 {0x409C0E11, "Smart Array 6400", &SA5A_access}, 167 {0x409D0E11, "Smart Array 6400 EM", &SA5A_access}, 168 {0x40910E11, "Smart Array 6i", &SA5A_access}, 169 {0x3225103C, "Smart Array P600", &SA5A_access}, 170 {0x3223103C, "Smart Array P800", &SA5A_access}, 171 {0x3234103C, "Smart Array P400", &SA5A_access}, 172 {0x3235103C, "Smart Array P400i", &SA5A_access}, 173 {0x3211103C, "Smart Array E200i", &SA5A_access}, 174 {0x3212103C, "Smart Array E200", &SA5A_access}, 175 {0x3213103C, "Smart Array E200i", &SA5A_access}, 176 {0x3214103C, "Smart Array E200i", &SA5A_access}, 177 {0x3215103C, "Smart Array E200i", &SA5A_access}, 178 {0x3237103C, "Smart Array E500", &SA5A_access}, 179 {0x323D103C, "Smart Array P700m", &SA5A_access}, 180 {0x3241103C, "Smart Array P212", &SA5_access}, 181 {0x3243103C, "Smart Array P410", &SA5_access}, 182 {0x3245103C, "Smart Array P410i", &SA5_access}, 183 {0x3247103C, "Smart Array P411", &SA5_access}, 184 {0x3249103C, "Smart Array P812", &SA5_access}, 185 {0x324A103C, "Smart Array P712m", &SA5_access}, 186 {0x324B103C, "Smart Array P711m", &SA5_access}, 187 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ 188 {0x3350103C, "Smart Array P222", &SA5_access}, 189 {0x3351103C, "Smart Array P420", &SA5_access}, 190 {0x3352103C, "Smart Array P421", &SA5_access}, 191 {0x3353103C, "Smart Array P822", &SA5_access}, 192 {0x3354103C, "Smart Array P420i", &SA5_access}, 193 {0x3355103C, "Smart Array P220i", &SA5_access}, 194 {0x3356103C, "Smart Array P721m", &SA5_access}, 195 {0x1920103C, "Smart Array P430i", &SA5_access}, 196 {0x1921103C, "Smart Array P830i", &SA5_access}, 197 {0x1922103C, "Smart Array P430", &SA5_access}, 198 {0x1923103C, "Smart Array P431", &SA5_access}, 199 {0x1924103C, "Smart Array P830", &SA5_access}, 200 {0x1925103C, "Smart Array P831", &SA5_access}, 201 {0x1926103C, "Smart Array P731m", &SA5_access}, 202 {0x1928103C, "Smart Array P230i", &SA5_access}, 203 {0x1929103C, "Smart Array P530", &SA5_access}, 204 {0x21BD103C, "Smart Array P244br", &SA5_access}, 205 {0x21BE103C, "Smart Array P741m", &SA5_access}, 206 {0x21BF103C, "Smart HBA H240ar", &SA5_access}, 207 {0x21C0103C, "Smart Array P440ar", &SA5_access}, 208 {0x21C1103C, "Smart Array P840ar", &SA5_access}, 209 {0x21C2103C, "Smart Array P440", &SA5_access}, 210 {0x21C3103C, "Smart Array P441", &SA5_access}, 211 {0x21C4103C, "Smart Array", &SA5_access}, 212 {0x21C5103C, "Smart Array P841", &SA5_access}, 213 {0x21C6103C, "Smart HBA H244br", &SA5_access}, 214 {0x21C7103C, "Smart HBA H240", &SA5_access}, 215 {0x21C8103C, "Smart HBA H241", &SA5_access}, 216 {0x21C9103C, "Smart Array", &SA5_access}, 217 {0x21CA103C, "Smart Array P246br", &SA5_access}, 218 {0x21CB103C, "Smart Array P840", &SA5_access}, 219 {0x21CC103C, "Smart Array", &SA5_access}, 220 {0x21CD103C, "Smart Array", &SA5_access}, 221 {0x21CE103C, "Smart HBA", &SA5_access}, 222 {0x05809005, "SmartHBA-SA", &SA5_access}, 223 {0x05819005, "SmartHBA-SA 8i", &SA5_access}, 224 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access}, 225 {0x05839005, "SmartHBA-SA 8e", &SA5_access}, 226 {0x05849005, "SmartHBA-SA 16i", &SA5_access}, 227 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access}, 228 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, 229 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, 230 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, 231 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, 232 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, 233 {0xFFFF103C, "Unknown Smart Array", &SA5_access}, 234 }; 235 236 static struct scsi_transport_template *hpsa_sas_transport_template; 237 static int hpsa_add_sas_host(struct ctlr_info *h); 238 static void hpsa_delete_sas_host(struct ctlr_info *h); 239 static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, 240 struct hpsa_scsi_dev_t *device); 241 static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device); 242 static struct hpsa_scsi_dev_t 243 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, 244 struct sas_rphy *rphy); 245 246 #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy) 247 static const struct scsi_cmnd hpsa_cmd_busy; 248 #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle) 249 static const struct scsi_cmnd hpsa_cmd_idle; 250 static int number_of_controllers; 251 252 static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); 253 static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); 254 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg); 255 256 #ifdef CONFIG_COMPAT 257 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, 258 void __user *arg); 259 #endif 260 261 static void cmd_free(struct ctlr_info *h, struct CommandList *c); 262 static struct CommandList *cmd_alloc(struct ctlr_info *h); 263 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c); 264 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, 265 struct scsi_cmnd *scmd); 266 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, 267 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, 268 int cmd_type); 269 static void hpsa_free_cmd_pool(struct ctlr_info *h); 270 #define VPD_PAGE (1 << 8) 271 #define HPSA_SIMPLE_ERROR_BITS 0x03 272 273 static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 274 static void hpsa_scan_start(struct Scsi_Host *); 275 static int hpsa_scan_finished(struct Scsi_Host *sh, 276 unsigned long elapsed_time); 277 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); 278 279 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); 280 static int hpsa_slave_alloc(struct scsi_device *sdev); 281 static int hpsa_slave_configure(struct scsi_device *sdev); 282 static void hpsa_slave_destroy(struct scsi_device *sdev); 283 284 static void hpsa_update_scsi_devices(struct ctlr_info *h); 285 static int check_for_unit_attention(struct ctlr_info *h, 286 struct CommandList *c); 287 static void check_ioctl_unit_attention(struct ctlr_info *h, 288 struct CommandList *c); 289 /* performant mode helper functions */ 290 static void calc_bucket_map(int *bucket, int num_buckets, 291 int nsgs, int min_blocks, u32 *bucket_map); 292 static void hpsa_free_performant_mode(struct ctlr_info *h); 293 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); 294 static inline u32 next_command(struct ctlr_info *h, u8 q); 295 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, 296 u32 *cfg_base_addr, u64 *cfg_base_addr_index, 297 u64 *cfg_offset); 298 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, 299 unsigned long *memory_bar); 300 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, 301 bool *legacy_board); 302 static int wait_for_device_to_become_ready(struct ctlr_info *h, 303 unsigned char lunaddr[], 304 int reply_queue); 305 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, 306 int wait_for_ready); 307 static inline void finish_cmd(struct CommandList *c); 308 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h); 309 #define BOARD_NOT_READY 0 310 #define BOARD_READY 1 311 static void hpsa_drain_accel_commands(struct ctlr_info *h); 312 static void hpsa_flush_cache(struct ctlr_info *h); 313 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, 314 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 315 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); 316 static void hpsa_command_resubmit_worker(struct work_struct *work); 317 static u32 lockup_detected(struct ctlr_info *h); 318 static int detect_controller_lockup(struct ctlr_info *h); 319 static void hpsa_disable_rld_caching(struct ctlr_info *h); 320 static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, 321 struct ReportExtendedLUNdata *buf, int bufsize); 322 static bool hpsa_vpd_page_supported(struct ctlr_info *h, 323 unsigned char scsi3addr[], u8 page); 324 static int hpsa_luns_changed(struct ctlr_info *h); 325 static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, 326 struct hpsa_scsi_dev_t *dev, 327 unsigned char *scsi3addr); 328 329 static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) 330 { 331 unsigned long *priv = shost_priv(sdev->host); 332 return (struct ctlr_info *) *priv; 333 } 334 335 static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) 336 { 337 unsigned long *priv = shost_priv(sh); 338 return (struct ctlr_info *) *priv; 339 } 340 341 static inline bool hpsa_is_cmd_idle(struct CommandList *c) 342 { 343 return c->scsi_cmd == SCSI_CMD_IDLE; 344 } 345 346 static inline bool hpsa_is_pending_event(struct CommandList *c) 347 { 348 return c->reset_pending; 349 } 350 351 /* extract sense key, asc, and ascq from sense data. -1 means invalid. */ 352 static void decode_sense_data(const u8 *sense_data, int sense_data_len, 353 u8 *sense_key, u8 *asc, u8 *ascq) 354 { 355 struct scsi_sense_hdr sshdr; 356 bool rc; 357 358 *sense_key = -1; 359 *asc = -1; 360 *ascq = -1; 361 362 if (sense_data_len < 1) 363 return; 364 365 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr); 366 if (rc) { 367 *sense_key = sshdr.sense_key; 368 *asc = sshdr.asc; 369 *ascq = sshdr.ascq; 370 } 371 } 372 373 static int check_for_unit_attention(struct ctlr_info *h, 374 struct CommandList *c) 375 { 376 u8 sense_key, asc, ascq; 377 int sense_len; 378 379 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) 380 sense_len = sizeof(c->err_info->SenseInfo); 381 else 382 sense_len = c->err_info->SenseLen; 383 384 decode_sense_data(c->err_info->SenseInfo, sense_len, 385 &sense_key, &asc, &ascq); 386 if (sense_key != UNIT_ATTENTION || asc == 0xff) 387 return 0; 388 389 switch (asc) { 390 case STATE_CHANGED: 391 dev_warn(&h->pdev->dev, 392 "%s: a state change detected, command retried\n", 393 h->devname); 394 break; 395 case LUN_FAILED: 396 dev_warn(&h->pdev->dev, 397 "%s: LUN failure detected\n", h->devname); 398 break; 399 case REPORT_LUNS_CHANGED: 400 dev_warn(&h->pdev->dev, 401 "%s: report LUN data changed\n", h->devname); 402 /* 403 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external 404 * target (array) devices. 405 */ 406 break; 407 case POWER_OR_RESET: 408 dev_warn(&h->pdev->dev, 409 "%s: a power on or device reset detected\n", 410 h->devname); 411 break; 412 case UNIT_ATTENTION_CLEARED: 413 dev_warn(&h->pdev->dev, 414 "%s: unit attention cleared by another initiator\n", 415 h->devname); 416 break; 417 default: 418 dev_warn(&h->pdev->dev, 419 "%s: unknown unit attention detected\n", 420 h->devname); 421 break; 422 } 423 return 1; 424 } 425 426 static int check_for_busy(struct ctlr_info *h, struct CommandList *c) 427 { 428 if (c->err_info->CommandStatus != CMD_TARGET_STATUS || 429 (c->err_info->ScsiStatus != SAM_STAT_BUSY && 430 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) 431 return 0; 432 dev_warn(&h->pdev->dev, HPSA "device busy"); 433 return 1; 434 } 435 436 static u32 lockup_detected(struct ctlr_info *h); 437 static ssize_t host_show_lockup_detected(struct device *dev, 438 struct device_attribute *attr, char *buf) 439 { 440 int ld; 441 struct ctlr_info *h; 442 struct Scsi_Host *shost = class_to_shost(dev); 443 444 h = shost_to_hba(shost); 445 ld = lockup_detected(h); 446 447 return sprintf(buf, "ld=%d\n", ld); 448 } 449 450 static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, 451 struct device_attribute *attr, 452 const char *buf, size_t count) 453 { 454 int status, len; 455 struct ctlr_info *h; 456 struct Scsi_Host *shost = class_to_shost(dev); 457 char tmpbuf[10]; 458 459 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 460 return -EACCES; 461 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; 462 strncpy(tmpbuf, buf, len); 463 tmpbuf[len] = '\0'; 464 if (sscanf(tmpbuf, "%d", &status) != 1) 465 return -EINVAL; 466 h = shost_to_hba(shost); 467 h->acciopath_status = !!status; 468 dev_warn(&h->pdev->dev, 469 "hpsa: HP SSD Smart Path %s via sysfs update.\n", 470 h->acciopath_status ? "enabled" : "disabled"); 471 return count; 472 } 473 474 static ssize_t host_store_raid_offload_debug(struct device *dev, 475 struct device_attribute *attr, 476 const char *buf, size_t count) 477 { 478 int debug_level, len; 479 struct ctlr_info *h; 480 struct Scsi_Host *shost = class_to_shost(dev); 481 char tmpbuf[10]; 482 483 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) 484 return -EACCES; 485 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; 486 strncpy(tmpbuf, buf, len); 487 tmpbuf[len] = '\0'; 488 if (sscanf(tmpbuf, "%d", &debug_level) != 1) 489 return -EINVAL; 490 if (debug_level < 0) 491 debug_level = 0; 492 h = shost_to_hba(shost); 493 h->raid_offload_debug = debug_level; 494 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", 495 h->raid_offload_debug); 496 return count; 497 } 498 499 static ssize_t host_store_rescan(struct device *dev, 500 struct device_attribute *attr, 501 const char *buf, size_t count) 502 { 503 struct ctlr_info *h; 504 struct Scsi_Host *shost = class_to_shost(dev); 505 h = shost_to_hba(shost); 506 hpsa_scan_start(h->scsi_host); 507 return count; 508 } 509 510 static ssize_t host_show_firmware_revision(struct device *dev, 511 struct device_attribute *attr, char *buf) 512 { 513 struct ctlr_info *h; 514 struct Scsi_Host *shost = class_to_shost(dev); 515 unsigned char *fwrev; 516 517 h = shost_to_hba(shost); 518 if (!h->hba_inquiry_data) 519 return 0; 520 fwrev = &h->hba_inquiry_data[32]; 521 return snprintf(buf, 20, "%c%c%c%c\n", 522 fwrev[0], fwrev[1], fwrev[2], fwrev[3]); 523 } 524 525 static ssize_t host_show_commands_outstanding(struct device *dev, 526 struct device_attribute *attr, char *buf) 527 { 528 struct Scsi_Host *shost = class_to_shost(dev); 529 struct ctlr_info *h = shost_to_hba(shost); 530 531 return snprintf(buf, 20, "%d\n", 532 atomic_read(&h->commands_outstanding)); 533 } 534 535 static ssize_t host_show_transport_mode(struct device *dev, 536 struct device_attribute *attr, char *buf) 537 { 538 struct ctlr_info *h; 539 struct Scsi_Host *shost = class_to_shost(dev); 540 541 h = shost_to_hba(shost); 542 return snprintf(buf, 20, "%s\n", 543 h->transMethod & CFGTBL_Trans_Performant ? 544 "performant" : "simple"); 545 } 546 547 static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, 548 struct device_attribute *attr, char *buf) 549 { 550 struct ctlr_info *h; 551 struct Scsi_Host *shost = class_to_shost(dev); 552 553 h = shost_to_hba(shost); 554 return snprintf(buf, 30, "HP SSD Smart Path %s\n", 555 (h->acciopath_status == 1) ? "enabled" : "disabled"); 556 } 557 558 /* List of controllers which cannot be hard reset on kexec with reset_devices */ 559 static u32 unresettable_controller[] = { 560 0x324a103C, /* Smart Array P712m */ 561 0x324b103C, /* Smart Array P711m */ 562 0x3223103C, /* Smart Array P800 */ 563 0x3234103C, /* Smart Array P400 */ 564 0x3235103C, /* Smart Array P400i */ 565 0x3211103C, /* Smart Array E200i */ 566 0x3212103C, /* Smart Array E200 */ 567 0x3213103C, /* Smart Array E200i */ 568 0x3214103C, /* Smart Array E200i */ 569 0x3215103C, /* Smart Array E200i */ 570 0x3237103C, /* Smart Array E500 */ 571 0x323D103C, /* Smart Array P700m */ 572 0x40800E11, /* Smart Array 5i */ 573 0x409C0E11, /* Smart Array 6400 */ 574 0x409D0E11, /* Smart Array 6400 EM */ 575 0x40700E11, /* Smart Array 5300 */ 576 0x40820E11, /* Smart Array 532 */ 577 0x40830E11, /* Smart Array 5312 */ 578 0x409A0E11, /* Smart Array 641 */ 579 0x409B0E11, /* Smart Array 642 */ 580 0x40910E11, /* Smart Array 6i */ 581 }; 582 583 /* List of controllers which cannot even be soft reset */ 584 static u32 soft_unresettable_controller[] = { 585 0x40800E11, /* Smart Array 5i */ 586 0x40700E11, /* Smart Array 5300 */ 587 0x40820E11, /* Smart Array 532 */ 588 0x40830E11, /* Smart Array 5312 */ 589 0x409A0E11, /* Smart Array 641 */ 590 0x409B0E11, /* Smart Array 642 */ 591 0x40910E11, /* Smart Array 6i */ 592 /* Exclude 640x boards. These are two pci devices in one slot 593 * which share a battery backed cache module. One controls the 594 * cache, the other accesses the cache through the one that controls 595 * it. If we reset the one controlling the cache, the other will 596 * likely not be happy. Just forbid resetting this conjoined mess. 597 * The 640x isn't really supported by hpsa anyway. 598 */ 599 0x409C0E11, /* Smart Array 6400 */ 600 0x409D0E11, /* Smart Array 6400 EM */ 601 }; 602 603 static int board_id_in_array(u32 a[], int nelems, u32 board_id) 604 { 605 int i; 606 607 for (i = 0; i < nelems; i++) 608 if (a[i] == board_id) 609 return 1; 610 return 0; 611 } 612 613 static int ctlr_is_hard_resettable(u32 board_id) 614 { 615 return !board_id_in_array(unresettable_controller, 616 ARRAY_SIZE(unresettable_controller), board_id); 617 } 618 619 static int ctlr_is_soft_resettable(u32 board_id) 620 { 621 return !board_id_in_array(soft_unresettable_controller, 622 ARRAY_SIZE(soft_unresettable_controller), board_id); 623 } 624 625 static int ctlr_is_resettable(u32 board_id) 626 { 627 return ctlr_is_hard_resettable(board_id) || 628 ctlr_is_soft_resettable(board_id); 629 } 630 631 static ssize_t host_show_resettable(struct device *dev, 632 struct device_attribute *attr, char *buf) 633 { 634 struct ctlr_info *h; 635 struct Scsi_Host *shost = class_to_shost(dev); 636 637 h = shost_to_hba(shost); 638 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); 639 } 640 641 static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) 642 { 643 return (scsi3addr[3] & 0xC0) == 0x40; 644 } 645 646 static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", 647 "1(+0)ADM", "UNKNOWN", "PHYS DRV" 648 }; 649 #define HPSA_RAID_0 0 650 #define HPSA_RAID_4 1 651 #define HPSA_RAID_1 2 /* also used for RAID 10 */ 652 #define HPSA_RAID_5 3 /* also used for RAID 50 */ 653 #define HPSA_RAID_51 4 654 #define HPSA_RAID_6 5 /* also used for RAID 60 */ 655 #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ 656 #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2) 657 #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1) 658 659 static inline bool is_logical_device(struct hpsa_scsi_dev_t *device) 660 { 661 return !device->physical_device; 662 } 663 664 static ssize_t raid_level_show(struct device *dev, 665 struct device_attribute *attr, char *buf) 666 { 667 ssize_t l = 0; 668 unsigned char rlevel; 669 struct ctlr_info *h; 670 struct scsi_device *sdev; 671 struct hpsa_scsi_dev_t *hdev; 672 unsigned long flags; 673 674 sdev = to_scsi_device(dev); 675 h = sdev_to_hba(sdev); 676 spin_lock_irqsave(&h->lock, flags); 677 hdev = sdev->hostdata; 678 if (!hdev) { 679 spin_unlock_irqrestore(&h->lock, flags); 680 return -ENODEV; 681 } 682 683 /* Is this even a logical drive? */ 684 if (!is_logical_device(hdev)) { 685 spin_unlock_irqrestore(&h->lock, flags); 686 l = snprintf(buf, PAGE_SIZE, "N/A\n"); 687 return l; 688 } 689 690 rlevel = hdev->raid_level; 691 spin_unlock_irqrestore(&h->lock, flags); 692 if (rlevel > RAID_UNKNOWN) 693 rlevel = RAID_UNKNOWN; 694 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); 695 return l; 696 } 697 698 static ssize_t lunid_show(struct device *dev, 699 struct device_attribute *attr, char *buf) 700 { 701 struct ctlr_info *h; 702 struct scsi_device *sdev; 703 struct hpsa_scsi_dev_t *hdev; 704 unsigned long flags; 705 unsigned char lunid[8]; 706 707 sdev = to_scsi_device(dev); 708 h = sdev_to_hba(sdev); 709 spin_lock_irqsave(&h->lock, flags); 710 hdev = sdev->hostdata; 711 if (!hdev) { 712 spin_unlock_irqrestore(&h->lock, flags); 713 return -ENODEV; 714 } 715 memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); 716 spin_unlock_irqrestore(&h->lock, flags); 717 return snprintf(buf, 20, "0x%8phN\n", lunid); 718 } 719 720 static ssize_t unique_id_show(struct device *dev, 721 struct device_attribute *attr, char *buf) 722 { 723 struct ctlr_info *h; 724 struct scsi_device *sdev; 725 struct hpsa_scsi_dev_t *hdev; 726 unsigned long flags; 727 unsigned char sn[16]; 728 729 sdev = to_scsi_device(dev); 730 h = sdev_to_hba(sdev); 731 spin_lock_irqsave(&h->lock, flags); 732 hdev = sdev->hostdata; 733 if (!hdev) { 734 spin_unlock_irqrestore(&h->lock, flags); 735 return -ENODEV; 736 } 737 memcpy(sn, hdev->device_id, sizeof(sn)); 738 spin_unlock_irqrestore(&h->lock, flags); 739 return snprintf(buf, 16 * 2 + 2, 740 "%02X%02X%02X%02X%02X%02X%02X%02X" 741 "%02X%02X%02X%02X%02X%02X%02X%02X\n", 742 sn[0], sn[1], sn[2], sn[3], 743 sn[4], sn[5], sn[6], sn[7], 744 sn[8], sn[9], sn[10], sn[11], 745 sn[12], sn[13], sn[14], sn[15]); 746 } 747 748 static ssize_t sas_address_show(struct device *dev, 749 struct device_attribute *attr, char *buf) 750 { 751 struct ctlr_info *h; 752 struct scsi_device *sdev; 753 struct hpsa_scsi_dev_t *hdev; 754 unsigned long flags; 755 u64 sas_address; 756 757 sdev = to_scsi_device(dev); 758 h = sdev_to_hba(sdev); 759 spin_lock_irqsave(&h->lock, flags); 760 hdev = sdev->hostdata; 761 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) { 762 spin_unlock_irqrestore(&h->lock, flags); 763 return -ENODEV; 764 } 765 sas_address = hdev->sas_address; 766 spin_unlock_irqrestore(&h->lock, flags); 767 768 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address); 769 } 770 771 static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, 772 struct device_attribute *attr, char *buf) 773 { 774 struct ctlr_info *h; 775 struct scsi_device *sdev; 776 struct hpsa_scsi_dev_t *hdev; 777 unsigned long flags; 778 int offload_enabled; 779 780 sdev = to_scsi_device(dev); 781 h = sdev_to_hba(sdev); 782 spin_lock_irqsave(&h->lock, flags); 783 hdev = sdev->hostdata; 784 if (!hdev) { 785 spin_unlock_irqrestore(&h->lock, flags); 786 return -ENODEV; 787 } 788 offload_enabled = hdev->offload_enabled; 789 spin_unlock_irqrestore(&h->lock, flags); 790 return snprintf(buf, 20, "%d\n", offload_enabled); 791 } 792 793 #define MAX_PATHS 8 794 static ssize_t path_info_show(struct device *dev, 795 struct device_attribute *attr, char *buf) 796 { 797 struct ctlr_info *h; 798 struct scsi_device *sdev; 799 struct hpsa_scsi_dev_t *hdev; 800 unsigned long flags; 801 int i; 802 int output_len = 0; 803 u8 box; 804 u8 bay; 805 u8 path_map_index = 0; 806 char *active; 807 unsigned char phys_connector[2]; 808 809 sdev = to_scsi_device(dev); 810 h = sdev_to_hba(sdev); 811 spin_lock_irqsave(&h->devlock, flags); 812 hdev = sdev->hostdata; 813 if (!hdev) { 814 spin_unlock_irqrestore(&h->devlock, flags); 815 return -ENODEV; 816 } 817 818 bay = hdev->bay; 819 for (i = 0; i < MAX_PATHS; i++) { 820 path_map_index = 1<<i; 821 if (i == hdev->active_path_index) 822 active = "Active"; 823 else if (hdev->path_map & path_map_index) 824 active = "Inactive"; 825 else 826 continue; 827 828 output_len += scnprintf(buf + output_len, 829 PAGE_SIZE - output_len, 830 "[%d:%d:%d:%d] %20.20s ", 831 h->scsi_host->host_no, 832 hdev->bus, hdev->target, hdev->lun, 833 scsi_device_type(hdev->devtype)); 834 835 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) { 836 output_len += scnprintf(buf + output_len, 837 PAGE_SIZE - output_len, 838 "%s\n", active); 839 continue; 840 } 841 842 box = hdev->box[i]; 843 memcpy(&phys_connector, &hdev->phys_connector[i], 844 sizeof(phys_connector)); 845 if (phys_connector[0] < '0') 846 phys_connector[0] = '0'; 847 if (phys_connector[1] < '0') 848 phys_connector[1] = '0'; 849 output_len += scnprintf(buf + output_len, 850 PAGE_SIZE - output_len, 851 "PORT: %.2s ", 852 phys_connector); 853 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) && 854 hdev->expose_device) { 855 if (box == 0 || box == 0xFF) { 856 output_len += scnprintf(buf + output_len, 857 PAGE_SIZE - output_len, 858 "BAY: %hhu %s\n", 859 bay, active); 860 } else { 861 output_len += scnprintf(buf + output_len, 862 PAGE_SIZE - output_len, 863 "BOX: %hhu BAY: %hhu %s\n", 864 box, bay, active); 865 } 866 } else if (box != 0 && box != 0xFF) { 867 output_len += scnprintf(buf + output_len, 868 PAGE_SIZE - output_len, "BOX: %hhu %s\n", 869 box, active); 870 } else 871 output_len += scnprintf(buf + output_len, 872 PAGE_SIZE - output_len, "%s\n", active); 873 } 874 875 spin_unlock_irqrestore(&h->devlock, flags); 876 return output_len; 877 } 878 879 static ssize_t host_show_ctlr_num(struct device *dev, 880 struct device_attribute *attr, char *buf) 881 { 882 struct ctlr_info *h; 883 struct Scsi_Host *shost = class_to_shost(dev); 884 885 h = shost_to_hba(shost); 886 return snprintf(buf, 20, "%d\n", h->ctlr); 887 } 888 889 static ssize_t host_show_legacy_board(struct device *dev, 890 struct device_attribute *attr, char *buf) 891 { 892 struct ctlr_info *h; 893 struct Scsi_Host *shost = class_to_shost(dev); 894 895 h = shost_to_hba(shost); 896 return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0); 897 } 898 899 static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); 900 static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); 901 static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); 902 static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); 903 static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL); 904 static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, 905 host_show_hp_ssd_smart_path_enabled, NULL); 906 static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL); 907 static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, 908 host_show_hp_ssd_smart_path_status, 909 host_store_hp_ssd_smart_path_status); 910 static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, 911 host_store_raid_offload_debug); 912 static DEVICE_ATTR(firmware_revision, S_IRUGO, 913 host_show_firmware_revision, NULL); 914 static DEVICE_ATTR(commands_outstanding, S_IRUGO, 915 host_show_commands_outstanding, NULL); 916 static DEVICE_ATTR(transport_mode, S_IRUGO, 917 host_show_transport_mode, NULL); 918 static DEVICE_ATTR(resettable, S_IRUGO, 919 host_show_resettable, NULL); 920 static DEVICE_ATTR(lockup_detected, S_IRUGO, 921 host_show_lockup_detected, NULL); 922 static DEVICE_ATTR(ctlr_num, S_IRUGO, 923 host_show_ctlr_num, NULL); 924 static DEVICE_ATTR(legacy_board, S_IRUGO, 925 host_show_legacy_board, NULL); 926 927 static struct device_attribute *hpsa_sdev_attrs[] = { 928 &dev_attr_raid_level, 929 &dev_attr_lunid, 930 &dev_attr_unique_id, 931 &dev_attr_hp_ssd_smart_path_enabled, 932 &dev_attr_path_info, 933 &dev_attr_sas_address, 934 NULL, 935 }; 936 937 static struct device_attribute *hpsa_shost_attrs[] = { 938 &dev_attr_rescan, 939 &dev_attr_firmware_revision, 940 &dev_attr_commands_outstanding, 941 &dev_attr_transport_mode, 942 &dev_attr_resettable, 943 &dev_attr_hp_ssd_smart_path_status, 944 &dev_attr_raid_offload_debug, 945 &dev_attr_lockup_detected, 946 &dev_attr_ctlr_num, 947 &dev_attr_legacy_board, 948 NULL, 949 }; 950 951 #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\ 952 HPSA_MAX_CONCURRENT_PASSTHRUS) 953 954 static struct scsi_host_template hpsa_driver_template = { 955 .module = THIS_MODULE, 956 .name = HPSA, 957 .proc_name = HPSA, 958 .queuecommand = hpsa_scsi_queue_command, 959 .scan_start = hpsa_scan_start, 960 .scan_finished = hpsa_scan_finished, 961 .change_queue_depth = hpsa_change_queue_depth, 962 .this_id = -1, 963 .use_clustering = ENABLE_CLUSTERING, 964 .eh_device_reset_handler = hpsa_eh_device_reset_handler, 965 .ioctl = hpsa_ioctl, 966 .slave_alloc = hpsa_slave_alloc, 967 .slave_configure = hpsa_slave_configure, 968 .slave_destroy = hpsa_slave_destroy, 969 #ifdef CONFIG_COMPAT 970 .compat_ioctl = hpsa_compat_ioctl, 971 #endif 972 .sdev_attrs = hpsa_sdev_attrs, 973 .shost_attrs = hpsa_shost_attrs, 974 .max_sectors = 1024, 975 .no_write_same = 1, 976 }; 977 978 static inline u32 next_command(struct ctlr_info *h, u8 q) 979 { 980 u32 a; 981 struct reply_queue_buffer *rq = &h->reply_queue[q]; 982 983 if (h->transMethod & CFGTBL_Trans_io_accel1) 984 return h->access.command_completed(h, q); 985 986 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) 987 return h->access.command_completed(h, q); 988 989 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { 990 a = rq->head[rq->current_entry]; 991 rq->current_entry++; 992 atomic_dec(&h->commands_outstanding); 993 } else { 994 a = FIFO_EMPTY; 995 } 996 /* Check for wraparound */ 997 if (rq->current_entry == h->max_commands) { 998 rq->current_entry = 0; 999 rq->wraparound ^= 1; 1000 } 1001 return a; 1002 } 1003 1004 /* 1005 * There are some special bits in the bus address of the 1006 * command that we have to set for the controller to know 1007 * how to process the command: 1008 * 1009 * Normal performant mode: 1010 * bit 0: 1 means performant mode, 0 means simple mode. 1011 * bits 1-3 = block fetch table entry 1012 * bits 4-6 = command type (== 0) 1013 * 1014 * ioaccel1 mode: 1015 * bit 0 = "performant mode" bit. 1016 * bits 1-3 = block fetch table entry 1017 * bits 4-6 = command type (== 110) 1018 * (command type is needed because ioaccel1 mode 1019 * commands are submitted through the same register as normal 1020 * mode commands, so this is how the controller knows whether 1021 * the command is normal mode or ioaccel1 mode.) 1022 * 1023 * ioaccel2 mode: 1024 * bit 0 = "performant mode" bit. 1025 * bits 1-4 = block fetch table entry (note extra bit) 1026 * bits 4-6 = not needed, because ioaccel2 mode has 1027 * a separate special register for submitting commands. 1028 */ 1029 1030 /* 1031 * set_performant_mode: Modify the tag for cciss performant 1032 * set bit 0 for pull model, bits 3-1 for block fetch 1033 * register number 1034 */ 1035 #define DEFAULT_REPLY_QUEUE (-1) 1036 static void set_performant_mode(struct ctlr_info *h, struct CommandList *c, 1037 int reply_queue) 1038 { 1039 if (likely(h->transMethod & CFGTBL_Trans_Performant)) { 1040 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); 1041 if (unlikely(!h->msix_vectors)) 1042 return; 1043 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1044 c->Header.ReplyQueue = 1045 raw_smp_processor_id() % h->nreply_queues; 1046 else 1047 c->Header.ReplyQueue = reply_queue % h->nreply_queues; 1048 } 1049 } 1050 1051 static void set_ioaccel1_performant_mode(struct ctlr_info *h, 1052 struct CommandList *c, 1053 int reply_queue) 1054 { 1055 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; 1056 1057 /* 1058 * Tell the controller to post the reply to the queue for this 1059 * processor. This seems to give the best I/O throughput. 1060 */ 1061 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1062 cp->ReplyQueue = smp_processor_id() % h->nreply_queues; 1063 else 1064 cp->ReplyQueue = reply_queue % h->nreply_queues; 1065 /* 1066 * Set the bits in the address sent down to include: 1067 * - performant mode bit (bit 0) 1068 * - pull count (bits 1-3) 1069 * - command type (bits 4-6) 1070 */ 1071 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | 1072 IOACCEL1_BUSADDR_CMDTYPE; 1073 } 1074 1075 static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h, 1076 struct CommandList *c, 1077 int reply_queue) 1078 { 1079 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *) 1080 &h->ioaccel2_cmd_pool[c->cmdindex]; 1081 1082 /* Tell the controller to post the reply to the queue for this 1083 * processor. This seems to give the best I/O throughput. 1084 */ 1085 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1086 cp->reply_queue = smp_processor_id() % h->nreply_queues; 1087 else 1088 cp->reply_queue = reply_queue % h->nreply_queues; 1089 /* Set the bits in the address sent down to include: 1090 * - performant mode bit not used in ioaccel mode 2 1091 * - pull count (bits 0-3) 1092 * - command type isn't needed for ioaccel2 1093 */ 1094 c->busaddr |= h->ioaccel2_blockFetchTable[0]; 1095 } 1096 1097 static void set_ioaccel2_performant_mode(struct ctlr_info *h, 1098 struct CommandList *c, 1099 int reply_queue) 1100 { 1101 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; 1102 1103 /* 1104 * Tell the controller to post the reply to the queue for this 1105 * processor. This seems to give the best I/O throughput. 1106 */ 1107 if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) 1108 cp->reply_queue = smp_processor_id() % h->nreply_queues; 1109 else 1110 cp->reply_queue = reply_queue % h->nreply_queues; 1111 /* 1112 * Set the bits in the address sent down to include: 1113 * - performant mode bit not used in ioaccel mode 2 1114 * - pull count (bits 0-3) 1115 * - command type isn't needed for ioaccel2 1116 */ 1117 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); 1118 } 1119 1120 static int is_firmware_flash_cmd(u8 *cdb) 1121 { 1122 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; 1123 } 1124 1125 /* 1126 * During firmware flash, the heartbeat register may not update as frequently 1127 * as it should. So we dial down lockup detection during firmware flash. and 1128 * dial it back up when firmware flash completes. 1129 */ 1130 #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) 1131 #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) 1132 #define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ) 1133 static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, 1134 struct CommandList *c) 1135 { 1136 if (!is_firmware_flash_cmd(c->Request.CDB)) 1137 return; 1138 atomic_inc(&h->firmware_flash_in_progress); 1139 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; 1140 } 1141 1142 static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, 1143 struct CommandList *c) 1144 { 1145 if (is_firmware_flash_cmd(c->Request.CDB) && 1146 atomic_dec_and_test(&h->firmware_flash_in_progress)) 1147 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; 1148 } 1149 1150 static void __enqueue_cmd_and_start_io(struct ctlr_info *h, 1151 struct CommandList *c, int reply_queue) 1152 { 1153 dial_down_lockup_detection_during_fw_flash(h, c); 1154 atomic_inc(&h->commands_outstanding); 1155 switch (c->cmd_type) { 1156 case CMD_IOACCEL1: 1157 set_ioaccel1_performant_mode(h, c, reply_queue); 1158 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); 1159 break; 1160 case CMD_IOACCEL2: 1161 set_ioaccel2_performant_mode(h, c, reply_queue); 1162 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 1163 break; 1164 case IOACCEL2_TMF: 1165 set_ioaccel2_tmf_performant_mode(h, c, reply_queue); 1166 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); 1167 break; 1168 default: 1169 set_performant_mode(h, c, reply_queue); 1170 h->access.submit_command(h, c); 1171 } 1172 } 1173 1174 static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c) 1175 { 1176 if (unlikely(hpsa_is_pending_event(c))) 1177 return finish_cmd(c); 1178 1179 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE); 1180 } 1181 1182 static inline int is_hba_lunid(unsigned char scsi3addr[]) 1183 { 1184 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; 1185 } 1186 1187 static inline int is_scsi_rev_5(struct ctlr_info *h) 1188 { 1189 if (!h->hba_inquiry_data) 1190 return 0; 1191 if ((h->hba_inquiry_data[2] & 0x07) == 5) 1192 return 1; 1193 return 0; 1194 } 1195 1196 static int hpsa_find_target_lun(struct ctlr_info *h, 1197 unsigned char scsi3addr[], int bus, int *target, int *lun) 1198 { 1199 /* finds an unused bus, target, lun for a new physical device 1200 * assumes h->devlock is held 1201 */ 1202 int i, found = 0; 1203 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); 1204 1205 bitmap_zero(lun_taken, HPSA_MAX_DEVICES); 1206 1207 for (i = 0; i < h->ndevices; i++) { 1208 if (h->dev[i]->bus == bus && h->dev[i]->target != -1) 1209 __set_bit(h->dev[i]->target, lun_taken); 1210 } 1211 1212 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); 1213 if (i < HPSA_MAX_DEVICES) { 1214 /* *bus = 1; */ 1215 *target = i; 1216 *lun = 0; 1217 found = 1; 1218 } 1219 return !found; 1220 } 1221 1222 static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h, 1223 struct hpsa_scsi_dev_t *dev, char *description) 1224 { 1225 #define LABEL_SIZE 25 1226 char label[LABEL_SIZE]; 1227 1228 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL) 1229 return; 1230 1231 switch (dev->devtype) { 1232 case TYPE_RAID: 1233 snprintf(label, LABEL_SIZE, "controller"); 1234 break; 1235 case TYPE_ENCLOSURE: 1236 snprintf(label, LABEL_SIZE, "enclosure"); 1237 break; 1238 case TYPE_DISK: 1239 case TYPE_ZBC: 1240 if (dev->external) 1241 snprintf(label, LABEL_SIZE, "external"); 1242 else if (!is_logical_dev_addr_mode(dev->scsi3addr)) 1243 snprintf(label, LABEL_SIZE, "%s", 1244 raid_label[PHYSICAL_DRIVE]); 1245 else 1246 snprintf(label, LABEL_SIZE, "RAID-%s", 1247 dev->raid_level > RAID_UNKNOWN ? "?" : 1248 raid_label[dev->raid_level]); 1249 break; 1250 case TYPE_ROM: 1251 snprintf(label, LABEL_SIZE, "rom"); 1252 break; 1253 case TYPE_TAPE: 1254 snprintf(label, LABEL_SIZE, "tape"); 1255 break; 1256 case TYPE_MEDIUM_CHANGER: 1257 snprintf(label, LABEL_SIZE, "changer"); 1258 break; 1259 default: 1260 snprintf(label, LABEL_SIZE, "UNKNOWN"); 1261 break; 1262 } 1263 1264 dev_printk(level, &h->pdev->dev, 1265 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n", 1266 h->scsi_host->host_no, dev->bus, dev->target, dev->lun, 1267 description, 1268 scsi_device_type(dev->devtype), 1269 dev->vendor, 1270 dev->model, 1271 label, 1272 dev->offload_config ? '+' : '-', 1273 dev->offload_enabled ? '+' : '-', 1274 dev->expose_device); 1275 } 1276 1277 /* Add an entry into h->dev[] array. */ 1278 static int hpsa_scsi_add_entry(struct ctlr_info *h, 1279 struct hpsa_scsi_dev_t *device, 1280 struct hpsa_scsi_dev_t *added[], int *nadded) 1281 { 1282 /* assumes h->devlock is held */ 1283 int n = h->ndevices; 1284 int i; 1285 unsigned char addr1[8], addr2[8]; 1286 struct hpsa_scsi_dev_t *sd; 1287 1288 if (n >= HPSA_MAX_DEVICES) { 1289 dev_err(&h->pdev->dev, "too many devices, some will be " 1290 "inaccessible.\n"); 1291 return -1; 1292 } 1293 1294 /* physical devices do not have lun or target assigned until now. */ 1295 if (device->lun != -1) 1296 /* Logical device, lun is already assigned. */ 1297 goto lun_assigned; 1298 1299 /* If this device a non-zero lun of a multi-lun device 1300 * byte 4 of the 8-byte LUN addr will contain the logical 1301 * unit no, zero otherwise. 1302 */ 1303 if (device->scsi3addr[4] == 0) { 1304 /* This is not a non-zero lun of a multi-lun device */ 1305 if (hpsa_find_target_lun(h, device->scsi3addr, 1306 device->bus, &device->target, &device->lun) != 0) 1307 return -1; 1308 goto lun_assigned; 1309 } 1310 1311 /* This is a non-zero lun of a multi-lun device. 1312 * Search through our list and find the device which 1313 * has the same 8 byte LUN address, excepting byte 4 and 5. 1314 * Assign the same bus and target for this new LUN. 1315 * Use the logical unit number from the firmware. 1316 */ 1317 memcpy(addr1, device->scsi3addr, 8); 1318 addr1[4] = 0; 1319 addr1[5] = 0; 1320 for (i = 0; i < n; i++) { 1321 sd = h->dev[i]; 1322 memcpy(addr2, sd->scsi3addr, 8); 1323 addr2[4] = 0; 1324 addr2[5] = 0; 1325 /* differ only in byte 4 and 5? */ 1326 if (memcmp(addr1, addr2, 8) == 0) { 1327 device->bus = sd->bus; 1328 device->target = sd->target; 1329 device->lun = device->scsi3addr[4]; 1330 break; 1331 } 1332 } 1333 if (device->lun == -1) { 1334 dev_warn(&h->pdev->dev, "physical device with no LUN=0," 1335 " suspect firmware bug or unsupported hardware " 1336 "configuration.\n"); 1337 return -1; 1338 } 1339 1340 lun_assigned: 1341 1342 h->dev[n] = device; 1343 h->ndevices++; 1344 added[*nadded] = device; 1345 (*nadded)++; 1346 hpsa_show_dev_msg(KERN_INFO, h, device, 1347 device->expose_device ? "added" : "masked"); 1348 device->offload_to_be_enabled = device->offload_enabled; 1349 device->offload_enabled = 0; 1350 return 0; 1351 } 1352 1353 /* Update an entry in h->dev[] array. */ 1354 static void hpsa_scsi_update_entry(struct ctlr_info *h, 1355 int entry, struct hpsa_scsi_dev_t *new_entry) 1356 { 1357 int offload_enabled; 1358 /* assumes h->devlock is held */ 1359 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1360 1361 /* Raid level changed. */ 1362 h->dev[entry]->raid_level = new_entry->raid_level; 1363 1364 /* Raid offload parameters changed. Careful about the ordering. */ 1365 if (new_entry->offload_config && new_entry->offload_enabled) { 1366 /* 1367 * if drive is newly offload_enabled, we want to copy the 1368 * raid map data first. If previously offload_enabled and 1369 * offload_config were set, raid map data had better be 1370 * the same as it was before. if raid map data is changed 1371 * then it had better be the case that 1372 * h->dev[entry]->offload_enabled is currently 0. 1373 */ 1374 h->dev[entry]->raid_map = new_entry->raid_map; 1375 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 1376 } 1377 if (new_entry->hba_ioaccel_enabled) { 1378 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; 1379 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */ 1380 } 1381 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled; 1382 h->dev[entry]->offload_config = new_entry->offload_config; 1383 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; 1384 h->dev[entry]->queue_depth = new_entry->queue_depth; 1385 1386 /* 1387 * We can turn off ioaccel offload now, but need to delay turning 1388 * it on until we can update h->dev[entry]->phys_disk[], but we 1389 * can't do that until all the devices are updated. 1390 */ 1391 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled; 1392 if (!new_entry->offload_enabled) 1393 h->dev[entry]->offload_enabled = 0; 1394 1395 offload_enabled = h->dev[entry]->offload_enabled; 1396 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled; 1397 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated"); 1398 h->dev[entry]->offload_enabled = offload_enabled; 1399 } 1400 1401 /* Replace an entry from h->dev[] array. */ 1402 static void hpsa_scsi_replace_entry(struct ctlr_info *h, 1403 int entry, struct hpsa_scsi_dev_t *new_entry, 1404 struct hpsa_scsi_dev_t *added[], int *nadded, 1405 struct hpsa_scsi_dev_t *removed[], int *nremoved) 1406 { 1407 /* assumes h->devlock is held */ 1408 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1409 removed[*nremoved] = h->dev[entry]; 1410 (*nremoved)++; 1411 1412 /* 1413 * New physical devices won't have target/lun assigned yet 1414 * so we need to preserve the values in the slot we are replacing. 1415 */ 1416 if (new_entry->target == -1) { 1417 new_entry->target = h->dev[entry]->target; 1418 new_entry->lun = h->dev[entry]->lun; 1419 } 1420 1421 h->dev[entry] = new_entry; 1422 added[*nadded] = new_entry; 1423 (*nadded)++; 1424 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced"); 1425 new_entry->offload_to_be_enabled = new_entry->offload_enabled; 1426 new_entry->offload_enabled = 0; 1427 } 1428 1429 /* Remove an entry from h->dev[] array. */ 1430 static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry, 1431 struct hpsa_scsi_dev_t *removed[], int *nremoved) 1432 { 1433 /* assumes h->devlock is held */ 1434 int i; 1435 struct hpsa_scsi_dev_t *sd; 1436 1437 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); 1438 1439 sd = h->dev[entry]; 1440 removed[*nremoved] = h->dev[entry]; 1441 (*nremoved)++; 1442 1443 for (i = entry; i < h->ndevices-1; i++) 1444 h->dev[i] = h->dev[i+1]; 1445 h->ndevices--; 1446 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed"); 1447 } 1448 1449 #define SCSI3ADDR_EQ(a, b) ( \ 1450 (a)[7] == (b)[7] && \ 1451 (a)[6] == (b)[6] && \ 1452 (a)[5] == (b)[5] && \ 1453 (a)[4] == (b)[4] && \ 1454 (a)[3] == (b)[3] && \ 1455 (a)[2] == (b)[2] && \ 1456 (a)[1] == (b)[1] && \ 1457 (a)[0] == (b)[0]) 1458 1459 static void fixup_botched_add(struct ctlr_info *h, 1460 struct hpsa_scsi_dev_t *added) 1461 { 1462 /* called when scsi_add_device fails in order to re-adjust 1463 * h->dev[] to match the mid layer's view. 1464 */ 1465 unsigned long flags; 1466 int i, j; 1467 1468 spin_lock_irqsave(&h->lock, flags); 1469 for (i = 0; i < h->ndevices; i++) { 1470 if (h->dev[i] == added) { 1471 for (j = i; j < h->ndevices-1; j++) 1472 h->dev[j] = h->dev[j+1]; 1473 h->ndevices--; 1474 break; 1475 } 1476 } 1477 spin_unlock_irqrestore(&h->lock, flags); 1478 kfree(added); 1479 } 1480 1481 static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, 1482 struct hpsa_scsi_dev_t *dev2) 1483 { 1484 /* we compare everything except lun and target as these 1485 * are not yet assigned. Compare parts likely 1486 * to differ first 1487 */ 1488 if (memcmp(dev1->scsi3addr, dev2->scsi3addr, 1489 sizeof(dev1->scsi3addr)) != 0) 1490 return 0; 1491 if (memcmp(dev1->device_id, dev2->device_id, 1492 sizeof(dev1->device_id)) != 0) 1493 return 0; 1494 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) 1495 return 0; 1496 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) 1497 return 0; 1498 if (dev1->devtype != dev2->devtype) 1499 return 0; 1500 if (dev1->bus != dev2->bus) 1501 return 0; 1502 return 1; 1503 } 1504 1505 static inline int device_updated(struct hpsa_scsi_dev_t *dev1, 1506 struct hpsa_scsi_dev_t *dev2) 1507 { 1508 /* Device attributes that can change, but don't mean 1509 * that the device is a different device, nor that the OS 1510 * needs to be told anything about the change. 1511 */ 1512 if (dev1->raid_level != dev2->raid_level) 1513 return 1; 1514 if (dev1->offload_config != dev2->offload_config) 1515 return 1; 1516 if (dev1->offload_enabled != dev2->offload_enabled) 1517 return 1; 1518 if (!is_logical_dev_addr_mode(dev1->scsi3addr)) 1519 if (dev1->queue_depth != dev2->queue_depth) 1520 return 1; 1521 return 0; 1522 } 1523 1524 /* Find needle in haystack. If exact match found, return DEVICE_SAME, 1525 * and return needle location in *index. If scsi3addr matches, but not 1526 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle 1527 * location in *index. 1528 * In the case of a minor device attribute change, such as RAID level, just 1529 * return DEVICE_UPDATED, along with the updated device's location in index. 1530 * If needle not found, return DEVICE_NOT_FOUND. 1531 */ 1532 static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, 1533 struct hpsa_scsi_dev_t *haystack[], int haystack_size, 1534 int *index) 1535 { 1536 int i; 1537 #define DEVICE_NOT_FOUND 0 1538 #define DEVICE_CHANGED 1 1539 #define DEVICE_SAME 2 1540 #define DEVICE_UPDATED 3 1541 if (needle == NULL) 1542 return DEVICE_NOT_FOUND; 1543 1544 for (i = 0; i < haystack_size; i++) { 1545 if (haystack[i] == NULL) /* previously removed. */ 1546 continue; 1547 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { 1548 *index = i; 1549 if (device_is_the_same(needle, haystack[i])) { 1550 if (device_updated(needle, haystack[i])) 1551 return DEVICE_UPDATED; 1552 return DEVICE_SAME; 1553 } else { 1554 /* Keep offline devices offline */ 1555 if (needle->volume_offline) 1556 return DEVICE_NOT_FOUND; 1557 return DEVICE_CHANGED; 1558 } 1559 } 1560 } 1561 *index = -1; 1562 return DEVICE_NOT_FOUND; 1563 } 1564 1565 static void hpsa_monitor_offline_device(struct ctlr_info *h, 1566 unsigned char scsi3addr[]) 1567 { 1568 struct offline_device_entry *device; 1569 unsigned long flags; 1570 1571 /* Check to see if device is already on the list */ 1572 spin_lock_irqsave(&h->offline_device_lock, flags); 1573 list_for_each_entry(device, &h->offline_device_list, offline_list) { 1574 if (memcmp(device->scsi3addr, scsi3addr, 1575 sizeof(device->scsi3addr)) == 0) { 1576 spin_unlock_irqrestore(&h->offline_device_lock, flags); 1577 return; 1578 } 1579 } 1580 spin_unlock_irqrestore(&h->offline_device_lock, flags); 1581 1582 /* Device is not on the list, add it. */ 1583 device = kmalloc(sizeof(*device), GFP_KERNEL); 1584 if (!device) 1585 return; 1586 1587 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); 1588 spin_lock_irqsave(&h->offline_device_lock, flags); 1589 list_add_tail(&device->offline_list, &h->offline_device_list); 1590 spin_unlock_irqrestore(&h->offline_device_lock, flags); 1591 } 1592 1593 /* Print a message explaining various offline volume states */ 1594 static void hpsa_show_volume_status(struct ctlr_info *h, 1595 struct hpsa_scsi_dev_t *sd) 1596 { 1597 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) 1598 dev_info(&h->pdev->dev, 1599 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", 1600 h->scsi_host->host_no, 1601 sd->bus, sd->target, sd->lun); 1602 switch (sd->volume_offline) { 1603 case HPSA_LV_OK: 1604 break; 1605 case HPSA_LV_UNDERGOING_ERASE: 1606 dev_info(&h->pdev->dev, 1607 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", 1608 h->scsi_host->host_no, 1609 sd->bus, sd->target, sd->lun); 1610 break; 1611 case HPSA_LV_NOT_AVAILABLE: 1612 dev_info(&h->pdev->dev, 1613 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n", 1614 h->scsi_host->host_no, 1615 sd->bus, sd->target, sd->lun); 1616 break; 1617 case HPSA_LV_UNDERGOING_RPI: 1618 dev_info(&h->pdev->dev, 1619 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n", 1620 h->scsi_host->host_no, 1621 sd->bus, sd->target, sd->lun); 1622 break; 1623 case HPSA_LV_PENDING_RPI: 1624 dev_info(&h->pdev->dev, 1625 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", 1626 h->scsi_host->host_no, 1627 sd->bus, sd->target, sd->lun); 1628 break; 1629 case HPSA_LV_ENCRYPTED_NO_KEY: 1630 dev_info(&h->pdev->dev, 1631 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", 1632 h->scsi_host->host_no, 1633 sd->bus, sd->target, sd->lun); 1634 break; 1635 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: 1636 dev_info(&h->pdev->dev, 1637 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", 1638 h->scsi_host->host_no, 1639 sd->bus, sd->target, sd->lun); 1640 break; 1641 case HPSA_LV_UNDERGOING_ENCRYPTION: 1642 dev_info(&h->pdev->dev, 1643 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", 1644 h->scsi_host->host_no, 1645 sd->bus, sd->target, sd->lun); 1646 break; 1647 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: 1648 dev_info(&h->pdev->dev, 1649 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", 1650 h->scsi_host->host_no, 1651 sd->bus, sd->target, sd->lun); 1652 break; 1653 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: 1654 dev_info(&h->pdev->dev, 1655 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", 1656 h->scsi_host->host_no, 1657 sd->bus, sd->target, sd->lun); 1658 break; 1659 case HPSA_LV_PENDING_ENCRYPTION: 1660 dev_info(&h->pdev->dev, 1661 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", 1662 h->scsi_host->host_no, 1663 sd->bus, sd->target, sd->lun); 1664 break; 1665 case HPSA_LV_PENDING_ENCRYPTION_REKEYING: 1666 dev_info(&h->pdev->dev, 1667 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", 1668 h->scsi_host->host_no, 1669 sd->bus, sd->target, sd->lun); 1670 break; 1671 } 1672 } 1673 1674 /* 1675 * Figure the list of physical drive pointers for a logical drive with 1676 * raid offload configured. 1677 */ 1678 static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, 1679 struct hpsa_scsi_dev_t *dev[], int ndevices, 1680 struct hpsa_scsi_dev_t *logical_drive) 1681 { 1682 struct raid_map_data *map = &logical_drive->raid_map; 1683 struct raid_map_disk_data *dd = &map->data[0]; 1684 int i, j; 1685 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + 1686 le16_to_cpu(map->metadata_disks_per_row); 1687 int nraid_map_entries = le16_to_cpu(map->row_cnt) * 1688 le16_to_cpu(map->layout_map_count) * 1689 total_disks_per_row; 1690 int nphys_disk = le16_to_cpu(map->layout_map_count) * 1691 total_disks_per_row; 1692 int qdepth; 1693 1694 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) 1695 nraid_map_entries = RAID_MAP_MAX_ENTRIES; 1696 1697 logical_drive->nphysical_disks = nraid_map_entries; 1698 1699 qdepth = 0; 1700 for (i = 0; i < nraid_map_entries; i++) { 1701 logical_drive->phys_disk[i] = NULL; 1702 if (!logical_drive->offload_config) 1703 continue; 1704 for (j = 0; j < ndevices; j++) { 1705 if (dev[j] == NULL) 1706 continue; 1707 if (dev[j]->devtype != TYPE_DISK && 1708 dev[j]->devtype != TYPE_ZBC) 1709 continue; 1710 if (is_logical_device(dev[j])) 1711 continue; 1712 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) 1713 continue; 1714 1715 logical_drive->phys_disk[i] = dev[j]; 1716 if (i < nphys_disk) 1717 qdepth = min(h->nr_cmds, qdepth + 1718 logical_drive->phys_disk[i]->queue_depth); 1719 break; 1720 } 1721 1722 /* 1723 * This can happen if a physical drive is removed and 1724 * the logical drive is degraded. In that case, the RAID 1725 * map data will refer to a physical disk which isn't actually 1726 * present. And in that case offload_enabled should already 1727 * be 0, but we'll turn it off here just in case 1728 */ 1729 if (!logical_drive->phys_disk[i]) { 1730 logical_drive->offload_enabled = 0; 1731 logical_drive->offload_to_be_enabled = 0; 1732 logical_drive->queue_depth = 8; 1733 } 1734 } 1735 if (nraid_map_entries) 1736 /* 1737 * This is correct for reads, too high for full stripe writes, 1738 * way too high for partial stripe writes 1739 */ 1740 logical_drive->queue_depth = qdepth; 1741 else 1742 logical_drive->queue_depth = h->nr_cmds; 1743 } 1744 1745 static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, 1746 struct hpsa_scsi_dev_t *dev[], int ndevices) 1747 { 1748 int i; 1749 1750 for (i = 0; i < ndevices; i++) { 1751 if (dev[i] == NULL) 1752 continue; 1753 if (dev[i]->devtype != TYPE_DISK && 1754 dev[i]->devtype != TYPE_ZBC) 1755 continue; 1756 if (!is_logical_device(dev[i])) 1757 continue; 1758 1759 /* 1760 * If offload is currently enabled, the RAID map and 1761 * phys_disk[] assignment *better* not be changing 1762 * and since it isn't changing, we do not need to 1763 * update it. 1764 */ 1765 if (dev[i]->offload_enabled) 1766 continue; 1767 1768 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); 1769 } 1770 } 1771 1772 static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) 1773 { 1774 int rc = 0; 1775 1776 if (!h->scsi_host) 1777 return 1; 1778 1779 if (is_logical_device(device)) /* RAID */ 1780 rc = scsi_add_device(h->scsi_host, device->bus, 1781 device->target, device->lun); 1782 else /* HBA */ 1783 rc = hpsa_add_sas_device(h->sas_host, device); 1784 1785 return rc; 1786 } 1787 1788 static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h, 1789 struct hpsa_scsi_dev_t *dev) 1790 { 1791 int i; 1792 int count = 0; 1793 1794 for (i = 0; i < h->nr_cmds; i++) { 1795 struct CommandList *c = h->cmd_pool + i; 1796 int refcount = atomic_inc_return(&c->refcount); 1797 1798 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, 1799 dev->scsi3addr)) { 1800 unsigned long flags; 1801 1802 spin_lock_irqsave(&h->lock, flags); /* Implied MB */ 1803 if (!hpsa_is_cmd_idle(c)) 1804 ++count; 1805 spin_unlock_irqrestore(&h->lock, flags); 1806 } 1807 1808 cmd_free(h, c); 1809 } 1810 1811 return count; 1812 } 1813 1814 static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h, 1815 struct hpsa_scsi_dev_t *device) 1816 { 1817 int cmds = 0; 1818 int waits = 0; 1819 1820 while (1) { 1821 cmds = hpsa_find_outstanding_commands_for_dev(h, device); 1822 if (cmds == 0) 1823 break; 1824 if (++waits > 20) 1825 break; 1826 dev_warn(&h->pdev->dev, 1827 "%s: removing device with %d outstanding commands!\n", 1828 __func__, cmds); 1829 msleep(1000); 1830 } 1831 } 1832 1833 static void hpsa_remove_device(struct ctlr_info *h, 1834 struct hpsa_scsi_dev_t *device) 1835 { 1836 struct scsi_device *sdev = NULL; 1837 1838 if (!h->scsi_host) 1839 return; 1840 1841 if (is_logical_device(device)) { /* RAID */ 1842 sdev = scsi_device_lookup(h->scsi_host, device->bus, 1843 device->target, device->lun); 1844 if (sdev) { 1845 scsi_remove_device(sdev); 1846 scsi_device_put(sdev); 1847 } else { 1848 /* 1849 * We don't expect to get here. Future commands 1850 * to this device will get a selection timeout as 1851 * if the device were gone. 1852 */ 1853 hpsa_show_dev_msg(KERN_WARNING, h, device, 1854 "didn't find device for removal."); 1855 } 1856 } else { /* HBA */ 1857 1858 device->removed = 1; 1859 hpsa_wait_for_outstanding_commands_for_dev(h, device); 1860 1861 hpsa_remove_sas_device(device); 1862 } 1863 } 1864 1865 static void adjust_hpsa_scsi_table(struct ctlr_info *h, 1866 struct hpsa_scsi_dev_t *sd[], int nsds) 1867 { 1868 /* sd contains scsi3 addresses and devtypes, and inquiry 1869 * data. This function takes what's in sd to be the current 1870 * reality and updates h->dev[] to reflect that reality. 1871 */ 1872 int i, entry, device_change, changes = 0; 1873 struct hpsa_scsi_dev_t *csd; 1874 unsigned long flags; 1875 struct hpsa_scsi_dev_t **added, **removed; 1876 int nadded, nremoved; 1877 1878 /* 1879 * A reset can cause a device status to change 1880 * re-schedule the scan to see what happened. 1881 */ 1882 spin_lock_irqsave(&h->reset_lock, flags); 1883 if (h->reset_in_progress) { 1884 h->drv_req_rescan = 1; 1885 spin_unlock_irqrestore(&h->reset_lock, flags); 1886 return; 1887 } 1888 spin_unlock_irqrestore(&h->reset_lock, flags); 1889 1890 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); 1891 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); 1892 1893 if (!added || !removed) { 1894 dev_warn(&h->pdev->dev, "out of memory in " 1895 "adjust_hpsa_scsi_table\n"); 1896 goto free_and_out; 1897 } 1898 1899 spin_lock_irqsave(&h->devlock, flags); 1900 1901 /* find any devices in h->dev[] that are not in 1902 * sd[] and remove them from h->dev[], and for any 1903 * devices which have changed, remove the old device 1904 * info and add the new device info. 1905 * If minor device attributes change, just update 1906 * the existing device structure. 1907 */ 1908 i = 0; 1909 nremoved = 0; 1910 nadded = 0; 1911 while (i < h->ndevices) { 1912 csd = h->dev[i]; 1913 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); 1914 if (device_change == DEVICE_NOT_FOUND) { 1915 changes++; 1916 hpsa_scsi_remove_entry(h, i, removed, &nremoved); 1917 continue; /* remove ^^^, hence i not incremented */ 1918 } else if (device_change == DEVICE_CHANGED) { 1919 changes++; 1920 hpsa_scsi_replace_entry(h, i, sd[entry], 1921 added, &nadded, removed, &nremoved); 1922 /* Set it to NULL to prevent it from being freed 1923 * at the bottom of hpsa_update_scsi_devices() 1924 */ 1925 sd[entry] = NULL; 1926 } else if (device_change == DEVICE_UPDATED) { 1927 hpsa_scsi_update_entry(h, i, sd[entry]); 1928 } 1929 i++; 1930 } 1931 1932 /* Now, make sure every device listed in sd[] is also 1933 * listed in h->dev[], adding them if they aren't found 1934 */ 1935 1936 for (i = 0; i < nsds; i++) { 1937 if (!sd[i]) /* if already added above. */ 1938 continue; 1939 1940 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS 1941 * as the SCSI mid-layer does not handle such devices well. 1942 * It relentlessly loops sending TUR at 3Hz, then READ(10) 1943 * at 160Hz, and prevents the system from coming up. 1944 */ 1945 if (sd[i]->volume_offline) { 1946 hpsa_show_volume_status(h, sd[i]); 1947 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline"); 1948 continue; 1949 } 1950 1951 device_change = hpsa_scsi_find_entry(sd[i], h->dev, 1952 h->ndevices, &entry); 1953 if (device_change == DEVICE_NOT_FOUND) { 1954 changes++; 1955 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0) 1956 break; 1957 sd[i] = NULL; /* prevent from being freed later. */ 1958 } else if (device_change == DEVICE_CHANGED) { 1959 /* should never happen... */ 1960 changes++; 1961 dev_warn(&h->pdev->dev, 1962 "device unexpectedly changed.\n"); 1963 /* but if it does happen, we just ignore that device */ 1964 } 1965 } 1966 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices); 1967 1968 /* Now that h->dev[]->phys_disk[] is coherent, we can enable 1969 * any logical drives that need it enabled. 1970 */ 1971 for (i = 0; i < h->ndevices; i++) { 1972 if (h->dev[i] == NULL) 1973 continue; 1974 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled; 1975 } 1976 1977 spin_unlock_irqrestore(&h->devlock, flags); 1978 1979 /* Monitor devices which are in one of several NOT READY states to be 1980 * brought online later. This must be done without holding h->devlock, 1981 * so don't touch h->dev[] 1982 */ 1983 for (i = 0; i < nsds; i++) { 1984 if (!sd[i]) /* if already added above. */ 1985 continue; 1986 if (sd[i]->volume_offline) 1987 hpsa_monitor_offline_device(h, sd[i]->scsi3addr); 1988 } 1989 1990 /* Don't notify scsi mid layer of any changes the first time through 1991 * (or if there are no changes) scsi_scan_host will do it later the 1992 * first time through. 1993 */ 1994 if (!changes) 1995 goto free_and_out; 1996 1997 /* Notify scsi mid layer of any removed devices */ 1998 for (i = 0; i < nremoved; i++) { 1999 if (removed[i] == NULL) 2000 continue; 2001 if (removed[i]->expose_device) 2002 hpsa_remove_device(h, removed[i]); 2003 kfree(removed[i]); 2004 removed[i] = NULL; 2005 } 2006 2007 /* Notify scsi mid layer of any added devices */ 2008 for (i = 0; i < nadded; i++) { 2009 int rc = 0; 2010 2011 if (added[i] == NULL) 2012 continue; 2013 if (!(added[i]->expose_device)) 2014 continue; 2015 rc = hpsa_add_device(h, added[i]); 2016 if (!rc) 2017 continue; 2018 dev_warn(&h->pdev->dev, 2019 "addition failed %d, device not added.", rc); 2020 /* now we have to remove it from h->dev, 2021 * since it didn't get added to scsi mid layer 2022 */ 2023 fixup_botched_add(h, added[i]); 2024 h->drv_req_rescan = 1; 2025 } 2026 2027 free_and_out: 2028 kfree(added); 2029 kfree(removed); 2030 } 2031 2032 /* 2033 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * 2034 * Assume's h->devlock is held. 2035 */ 2036 static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, 2037 int bus, int target, int lun) 2038 { 2039 int i; 2040 struct hpsa_scsi_dev_t *sd; 2041 2042 for (i = 0; i < h->ndevices; i++) { 2043 sd = h->dev[i]; 2044 if (sd->bus == bus && sd->target == target && sd->lun == lun) 2045 return sd; 2046 } 2047 return NULL; 2048 } 2049 2050 static int hpsa_slave_alloc(struct scsi_device *sdev) 2051 { 2052 struct hpsa_scsi_dev_t *sd = NULL; 2053 unsigned long flags; 2054 struct ctlr_info *h; 2055 2056 h = sdev_to_hba(sdev); 2057 spin_lock_irqsave(&h->devlock, flags); 2058 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) { 2059 struct scsi_target *starget; 2060 struct sas_rphy *rphy; 2061 2062 starget = scsi_target(sdev); 2063 rphy = target_to_rphy(starget); 2064 sd = hpsa_find_device_by_sas_rphy(h, rphy); 2065 if (sd) { 2066 sd->target = sdev_id(sdev); 2067 sd->lun = sdev->lun; 2068 } 2069 } 2070 if (!sd) 2071 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), 2072 sdev_id(sdev), sdev->lun); 2073 2074 if (sd && sd->expose_device) { 2075 atomic_set(&sd->ioaccel_cmds_out, 0); 2076 sdev->hostdata = sd; 2077 } else 2078 sdev->hostdata = NULL; 2079 spin_unlock_irqrestore(&h->devlock, flags); 2080 return 0; 2081 } 2082 2083 /* configure scsi device based on internal per-device structure */ 2084 static int hpsa_slave_configure(struct scsi_device *sdev) 2085 { 2086 struct hpsa_scsi_dev_t *sd; 2087 int queue_depth; 2088 2089 sd = sdev->hostdata; 2090 sdev->no_uld_attach = !sd || !sd->expose_device; 2091 2092 if (sd) { 2093 if (sd->external) 2094 queue_depth = EXTERNAL_QD; 2095 else 2096 queue_depth = sd->queue_depth != 0 ? 2097 sd->queue_depth : sdev->host->can_queue; 2098 } else 2099 queue_depth = sdev->host->can_queue; 2100 2101 scsi_change_queue_depth(sdev, queue_depth); 2102 2103 return 0; 2104 } 2105 2106 static void hpsa_slave_destroy(struct scsi_device *sdev) 2107 { 2108 /* nothing to do. */ 2109 } 2110 2111 static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h) 2112 { 2113 int i; 2114 2115 if (!h->ioaccel2_cmd_sg_list) 2116 return; 2117 for (i = 0; i < h->nr_cmds; i++) { 2118 kfree(h->ioaccel2_cmd_sg_list[i]); 2119 h->ioaccel2_cmd_sg_list[i] = NULL; 2120 } 2121 kfree(h->ioaccel2_cmd_sg_list); 2122 h->ioaccel2_cmd_sg_list = NULL; 2123 } 2124 2125 static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h) 2126 { 2127 int i; 2128 2129 if (h->chainsize <= 0) 2130 return 0; 2131 2132 h->ioaccel2_cmd_sg_list = 2133 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds, 2134 GFP_KERNEL); 2135 if (!h->ioaccel2_cmd_sg_list) 2136 return -ENOMEM; 2137 for (i = 0; i < h->nr_cmds; i++) { 2138 h->ioaccel2_cmd_sg_list[i] = 2139 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) * 2140 h->maxsgentries, GFP_KERNEL); 2141 if (!h->ioaccel2_cmd_sg_list[i]) 2142 goto clean; 2143 } 2144 return 0; 2145 2146 clean: 2147 hpsa_free_ioaccel2_sg_chain_blocks(h); 2148 return -ENOMEM; 2149 } 2150 2151 static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) 2152 { 2153 int i; 2154 2155 if (!h->cmd_sg_list) 2156 return; 2157 for (i = 0; i < h->nr_cmds; i++) { 2158 kfree(h->cmd_sg_list[i]); 2159 h->cmd_sg_list[i] = NULL; 2160 } 2161 kfree(h->cmd_sg_list); 2162 h->cmd_sg_list = NULL; 2163 } 2164 2165 static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h) 2166 { 2167 int i; 2168 2169 if (h->chainsize <= 0) 2170 return 0; 2171 2172 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, 2173 GFP_KERNEL); 2174 if (!h->cmd_sg_list) 2175 return -ENOMEM; 2176 2177 for (i = 0; i < h->nr_cmds; i++) { 2178 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * 2179 h->chainsize, GFP_KERNEL); 2180 if (!h->cmd_sg_list[i]) 2181 goto clean; 2182 2183 } 2184 return 0; 2185 2186 clean: 2187 hpsa_free_sg_chain_blocks(h); 2188 return -ENOMEM; 2189 } 2190 2191 static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h, 2192 struct io_accel2_cmd *cp, struct CommandList *c) 2193 { 2194 struct ioaccel2_sg_element *chain_block; 2195 u64 temp64; 2196 u32 chain_size; 2197 2198 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex]; 2199 chain_size = le32_to_cpu(cp->sg[0].length); 2200 temp64 = pci_map_single(h->pdev, chain_block, chain_size, 2201 PCI_DMA_TODEVICE); 2202 if (dma_mapping_error(&h->pdev->dev, temp64)) { 2203 /* prevent subsequent unmapping */ 2204 cp->sg->address = 0; 2205 return -1; 2206 } 2207 cp->sg->address = cpu_to_le64(temp64); 2208 return 0; 2209 } 2210 2211 static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h, 2212 struct io_accel2_cmd *cp) 2213 { 2214 struct ioaccel2_sg_element *chain_sg; 2215 u64 temp64; 2216 u32 chain_size; 2217 2218 chain_sg = cp->sg; 2219 temp64 = le64_to_cpu(chain_sg->address); 2220 chain_size = le32_to_cpu(cp->sg[0].length); 2221 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE); 2222 } 2223 2224 static int hpsa_map_sg_chain_block(struct ctlr_info *h, 2225 struct CommandList *c) 2226 { 2227 struct SGDescriptor *chain_sg, *chain_block; 2228 u64 temp64; 2229 u32 chain_len; 2230 2231 chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; 2232 chain_block = h->cmd_sg_list[c->cmdindex]; 2233 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); 2234 chain_len = sizeof(*chain_sg) * 2235 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); 2236 chain_sg->Len = cpu_to_le32(chain_len); 2237 temp64 = pci_map_single(h->pdev, chain_block, chain_len, 2238 PCI_DMA_TODEVICE); 2239 if (dma_mapping_error(&h->pdev->dev, temp64)) { 2240 /* prevent subsequent unmapping */ 2241 chain_sg->Addr = cpu_to_le64(0); 2242 return -1; 2243 } 2244 chain_sg->Addr = cpu_to_le64(temp64); 2245 return 0; 2246 } 2247 2248 static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, 2249 struct CommandList *c) 2250 { 2251 struct SGDescriptor *chain_sg; 2252 2253 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) 2254 return; 2255 2256 chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; 2257 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr), 2258 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE); 2259 } 2260 2261 2262 /* Decode the various types of errors on ioaccel2 path. 2263 * Return 1 for any error that should generate a RAID path retry. 2264 * Return 0 for errors that don't require a RAID path retry. 2265 */ 2266 static int handle_ioaccel_mode2_error(struct ctlr_info *h, 2267 struct CommandList *c, 2268 struct scsi_cmnd *cmd, 2269 struct io_accel2_cmd *c2, 2270 struct hpsa_scsi_dev_t *dev) 2271 { 2272 int data_len; 2273 int retry = 0; 2274 u32 ioaccel2_resid = 0; 2275 2276 switch (c2->error_data.serv_response) { 2277 case IOACCEL2_SERV_RESPONSE_COMPLETE: 2278 switch (c2->error_data.status) { 2279 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: 2280 break; 2281 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: 2282 cmd->result |= SAM_STAT_CHECK_CONDITION; 2283 if (c2->error_data.data_present != 2284 IOACCEL2_SENSE_DATA_PRESENT) { 2285 memset(cmd->sense_buffer, 0, 2286 SCSI_SENSE_BUFFERSIZE); 2287 break; 2288 } 2289 /* copy the sense data */ 2290 data_len = c2->error_data.sense_data_len; 2291 if (data_len > SCSI_SENSE_BUFFERSIZE) 2292 data_len = SCSI_SENSE_BUFFERSIZE; 2293 if (data_len > sizeof(c2->error_data.sense_data_buff)) 2294 data_len = 2295 sizeof(c2->error_data.sense_data_buff); 2296 memcpy(cmd->sense_buffer, 2297 c2->error_data.sense_data_buff, data_len); 2298 retry = 1; 2299 break; 2300 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: 2301 retry = 1; 2302 break; 2303 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: 2304 retry = 1; 2305 break; 2306 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: 2307 retry = 1; 2308 break; 2309 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: 2310 retry = 1; 2311 break; 2312 default: 2313 retry = 1; 2314 break; 2315 } 2316 break; 2317 case IOACCEL2_SERV_RESPONSE_FAILURE: 2318 switch (c2->error_data.status) { 2319 case IOACCEL2_STATUS_SR_IO_ERROR: 2320 case IOACCEL2_STATUS_SR_IO_ABORTED: 2321 case IOACCEL2_STATUS_SR_OVERRUN: 2322 retry = 1; 2323 break; 2324 case IOACCEL2_STATUS_SR_UNDERRUN: 2325 cmd->result = (DID_OK << 16); /* host byte */ 2326 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ 2327 ioaccel2_resid = get_unaligned_le32( 2328 &c2->error_data.resid_cnt[0]); 2329 scsi_set_resid(cmd, ioaccel2_resid); 2330 break; 2331 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE: 2332 case IOACCEL2_STATUS_SR_INVALID_DEVICE: 2333 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED: 2334 /* 2335 * Did an HBA disk disappear? We will eventually 2336 * get a state change event from the controller but 2337 * in the meantime, we need to tell the OS that the 2338 * HBA disk is no longer there and stop I/O 2339 * from going down. This allows the potential re-insert 2340 * of the disk to get the same device node. 2341 */ 2342 if (dev->physical_device && dev->expose_device) { 2343 cmd->result = DID_NO_CONNECT << 16; 2344 dev->removed = 1; 2345 h->drv_req_rescan = 1; 2346 dev_warn(&h->pdev->dev, 2347 "%s: device is gone!\n", __func__); 2348 } else 2349 /* 2350 * Retry by sending down the RAID path. 2351 * We will get an event from ctlr to 2352 * trigger rescan regardless. 2353 */ 2354 retry = 1; 2355 break; 2356 default: 2357 retry = 1; 2358 } 2359 break; 2360 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: 2361 break; 2362 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: 2363 break; 2364 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: 2365 retry = 1; 2366 break; 2367 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: 2368 break; 2369 default: 2370 retry = 1; 2371 break; 2372 } 2373 2374 return retry; /* retry on raid path? */ 2375 } 2376 2377 static void hpsa_cmd_resolve_events(struct ctlr_info *h, 2378 struct CommandList *c) 2379 { 2380 bool do_wake = false; 2381 2382 /* 2383 * Reset c->scsi_cmd here so that the reset handler will know 2384 * this command has completed. Then, check to see if the handler is 2385 * waiting for this command, and, if so, wake it. 2386 */ 2387 c->scsi_cmd = SCSI_CMD_IDLE; 2388 mb(); /* Declare command idle before checking for pending events. */ 2389 if (c->reset_pending) { 2390 unsigned long flags; 2391 struct hpsa_scsi_dev_t *dev; 2392 2393 /* 2394 * There appears to be a reset pending; lock the lock and 2395 * reconfirm. If so, then decrement the count of outstanding 2396 * commands and wake the reset command if this is the last one. 2397 */ 2398 spin_lock_irqsave(&h->lock, flags); 2399 dev = c->reset_pending; /* Re-fetch under the lock. */ 2400 if (dev && atomic_dec_and_test(&dev->reset_cmds_out)) 2401 do_wake = true; 2402 c->reset_pending = NULL; 2403 spin_unlock_irqrestore(&h->lock, flags); 2404 } 2405 2406 if (do_wake) 2407 wake_up_all(&h->event_sync_wait_queue); 2408 } 2409 2410 static void hpsa_cmd_resolve_and_free(struct ctlr_info *h, 2411 struct CommandList *c) 2412 { 2413 hpsa_cmd_resolve_events(h, c); 2414 cmd_tagged_free(h, c); 2415 } 2416 2417 static void hpsa_cmd_free_and_done(struct ctlr_info *h, 2418 struct CommandList *c, struct scsi_cmnd *cmd) 2419 { 2420 hpsa_cmd_resolve_and_free(h, c); 2421 if (cmd && cmd->scsi_done) 2422 cmd->scsi_done(cmd); 2423 } 2424 2425 static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c) 2426 { 2427 INIT_WORK(&c->work, hpsa_command_resubmit_worker); 2428 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); 2429 } 2430 2431 static void process_ioaccel2_completion(struct ctlr_info *h, 2432 struct CommandList *c, struct scsi_cmnd *cmd, 2433 struct hpsa_scsi_dev_t *dev) 2434 { 2435 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 2436 2437 /* check for good status */ 2438 if (likely(c2->error_data.serv_response == 0 && 2439 c2->error_data.status == 0)) 2440 return hpsa_cmd_free_and_done(h, c, cmd); 2441 2442 /* 2443 * Any RAID offload error results in retry which will use 2444 * the normal I/O path so the controller can handle whatever's 2445 * wrong. 2446 */ 2447 if (is_logical_device(dev) && 2448 c2->error_data.serv_response == 2449 IOACCEL2_SERV_RESPONSE_FAILURE) { 2450 if (c2->error_data.status == 2451 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) { 2452 dev->offload_enabled = 0; 2453 dev->offload_to_be_enabled = 0; 2454 } 2455 2456 return hpsa_retry_cmd(h, c); 2457 } 2458 2459 if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev)) 2460 return hpsa_retry_cmd(h, c); 2461 2462 return hpsa_cmd_free_and_done(h, c, cmd); 2463 } 2464 2465 /* Returns 0 on success, < 0 otherwise. */ 2466 static int hpsa_evaluate_tmf_status(struct ctlr_info *h, 2467 struct CommandList *cp) 2468 { 2469 u8 tmf_status = cp->err_info->ScsiStatus; 2470 2471 switch (tmf_status) { 2472 case CISS_TMF_COMPLETE: 2473 /* 2474 * CISS_TMF_COMPLETE never happens, instead, 2475 * ei->CommandStatus == 0 for this case. 2476 */ 2477 case CISS_TMF_SUCCESS: 2478 return 0; 2479 case CISS_TMF_INVALID_FRAME: 2480 case CISS_TMF_NOT_SUPPORTED: 2481 case CISS_TMF_FAILED: 2482 case CISS_TMF_WRONG_LUN: 2483 case CISS_TMF_OVERLAPPED_TAG: 2484 break; 2485 default: 2486 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n", 2487 tmf_status); 2488 break; 2489 } 2490 return -tmf_status; 2491 } 2492 2493 static void complete_scsi_command(struct CommandList *cp) 2494 { 2495 struct scsi_cmnd *cmd; 2496 struct ctlr_info *h; 2497 struct ErrorInfo *ei; 2498 struct hpsa_scsi_dev_t *dev; 2499 struct io_accel2_cmd *c2; 2500 2501 u8 sense_key; 2502 u8 asc; /* additional sense code */ 2503 u8 ascq; /* additional sense code qualifier */ 2504 unsigned long sense_data_size; 2505 2506 ei = cp->err_info; 2507 cmd = cp->scsi_cmd; 2508 h = cp->h; 2509 2510 if (!cmd->device) { 2511 cmd->result = DID_NO_CONNECT << 16; 2512 return hpsa_cmd_free_and_done(h, cp, cmd); 2513 } 2514 2515 dev = cmd->device->hostdata; 2516 if (!dev) { 2517 cmd->result = DID_NO_CONNECT << 16; 2518 return hpsa_cmd_free_and_done(h, cp, cmd); 2519 } 2520 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex]; 2521 2522 scsi_dma_unmap(cmd); /* undo the DMA mappings */ 2523 if ((cp->cmd_type == CMD_SCSI) && 2524 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) 2525 hpsa_unmap_sg_chain_block(h, cp); 2526 2527 if ((cp->cmd_type == CMD_IOACCEL2) && 2528 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN)) 2529 hpsa_unmap_ioaccel2_sg_chain_block(h, c2); 2530 2531 cmd->result = (DID_OK << 16); /* host byte */ 2532 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ 2533 2534 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) { 2535 if (dev->physical_device && dev->expose_device && 2536 dev->removed) { 2537 cmd->result = DID_NO_CONNECT << 16; 2538 return hpsa_cmd_free_and_done(h, cp, cmd); 2539 } 2540 if (likely(cp->phys_disk != NULL)) 2541 atomic_dec(&cp->phys_disk->ioaccel_cmds_out); 2542 } 2543 2544 /* 2545 * We check for lockup status here as it may be set for 2546 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by 2547 * fail_all_oustanding_cmds() 2548 */ 2549 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) { 2550 /* DID_NO_CONNECT will prevent a retry */ 2551 cmd->result = DID_NO_CONNECT << 16; 2552 return hpsa_cmd_free_and_done(h, cp, cmd); 2553 } 2554 2555 if ((unlikely(hpsa_is_pending_event(cp)))) 2556 if (cp->reset_pending) 2557 return hpsa_cmd_free_and_done(h, cp, cmd); 2558 2559 if (cp->cmd_type == CMD_IOACCEL2) 2560 return process_ioaccel2_completion(h, cp, cmd, dev); 2561 2562 scsi_set_resid(cmd, ei->ResidualCnt); 2563 if (ei->CommandStatus == 0) 2564 return hpsa_cmd_free_and_done(h, cp, cmd); 2565 2566 /* For I/O accelerator commands, copy over some fields to the normal 2567 * CISS header used below for error handling. 2568 */ 2569 if (cp->cmd_type == CMD_IOACCEL1) { 2570 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; 2571 cp->Header.SGList = scsi_sg_count(cmd); 2572 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); 2573 cp->Request.CDBLen = le16_to_cpu(c->io_flags) & 2574 IOACCEL1_IOFLAGS_CDBLEN_MASK; 2575 cp->Header.tag = c->tag; 2576 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); 2577 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); 2578 2579 /* Any RAID offload error results in retry which will use 2580 * the normal I/O path so the controller can handle whatever's 2581 * wrong. 2582 */ 2583 if (is_logical_device(dev)) { 2584 if (ei->CommandStatus == CMD_IOACCEL_DISABLED) 2585 dev->offload_enabled = 0; 2586 return hpsa_retry_cmd(h, cp); 2587 } 2588 } 2589 2590 /* an error has occurred */ 2591 switch (ei->CommandStatus) { 2592 2593 case CMD_TARGET_STATUS: 2594 cmd->result |= ei->ScsiStatus; 2595 /* copy the sense data */ 2596 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) 2597 sense_data_size = SCSI_SENSE_BUFFERSIZE; 2598 else 2599 sense_data_size = sizeof(ei->SenseInfo); 2600 if (ei->SenseLen < sense_data_size) 2601 sense_data_size = ei->SenseLen; 2602 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); 2603 if (ei->ScsiStatus) 2604 decode_sense_data(ei->SenseInfo, sense_data_size, 2605 &sense_key, &asc, &ascq); 2606 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { 2607 if (sense_key == ABORTED_COMMAND) { 2608 cmd->result |= DID_SOFT_ERROR << 16; 2609 break; 2610 } 2611 break; 2612 } 2613 /* Problem was not a check condition 2614 * Pass it up to the upper layers... 2615 */ 2616 if (ei->ScsiStatus) { 2617 dev_warn(&h->pdev->dev, "cp %p has status 0x%x " 2618 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " 2619 "Returning result: 0x%x\n", 2620 cp, ei->ScsiStatus, 2621 sense_key, asc, ascq, 2622 cmd->result); 2623 } else { /* scsi status is zero??? How??? */ 2624 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " 2625 "Returning no connection.\n", cp), 2626 2627 /* Ordinarily, this case should never happen, 2628 * but there is a bug in some released firmware 2629 * revisions that allows it to happen if, for 2630 * example, a 4100 backplane loses power and 2631 * the tape drive is in it. We assume that 2632 * it's a fatal error of some kind because we 2633 * can't show that it wasn't. We will make it 2634 * look like selection timeout since that is 2635 * the most common reason for this to occur, 2636 * and it's severe enough. 2637 */ 2638 2639 cmd->result = DID_NO_CONNECT << 16; 2640 } 2641 break; 2642 2643 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ 2644 break; 2645 case CMD_DATA_OVERRUN: 2646 dev_warn(&h->pdev->dev, 2647 "CDB %16phN data overrun\n", cp->Request.CDB); 2648 break; 2649 case CMD_INVALID: { 2650 /* print_bytes(cp, sizeof(*cp), 1, 0); 2651 print_cmd(cp); */ 2652 /* We get CMD_INVALID if you address a non-existent device 2653 * instead of a selection timeout (no response). You will 2654 * see this if you yank out a drive, then try to access it. 2655 * This is kind of a shame because it means that any other 2656 * CMD_INVALID (e.g. driver bug) will get interpreted as a 2657 * missing target. */ 2658 cmd->result = DID_NO_CONNECT << 16; 2659 } 2660 break; 2661 case CMD_PROTOCOL_ERR: 2662 cmd->result = DID_ERROR << 16; 2663 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n", 2664 cp->Request.CDB); 2665 break; 2666 case CMD_HARDWARE_ERR: 2667 cmd->result = DID_ERROR << 16; 2668 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n", 2669 cp->Request.CDB); 2670 break; 2671 case CMD_CONNECTION_LOST: 2672 cmd->result = DID_ERROR << 16; 2673 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n", 2674 cp->Request.CDB); 2675 break; 2676 case CMD_ABORTED: 2677 cmd->result = DID_ABORT << 16; 2678 break; 2679 case CMD_ABORT_FAILED: 2680 cmd->result = DID_ERROR << 16; 2681 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n", 2682 cp->Request.CDB); 2683 break; 2684 case CMD_UNSOLICITED_ABORT: 2685 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ 2686 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n", 2687 cp->Request.CDB); 2688 break; 2689 case CMD_TIMEOUT: 2690 cmd->result = DID_TIME_OUT << 16; 2691 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n", 2692 cp->Request.CDB); 2693 break; 2694 case CMD_UNABORTABLE: 2695 cmd->result = DID_ERROR << 16; 2696 dev_warn(&h->pdev->dev, "Command unabortable\n"); 2697 break; 2698 case CMD_TMF_STATUS: 2699 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */ 2700 cmd->result = DID_ERROR << 16; 2701 break; 2702 case CMD_IOACCEL_DISABLED: 2703 /* This only handles the direct pass-through case since RAID 2704 * offload is handled above. Just attempt a retry. 2705 */ 2706 cmd->result = DID_SOFT_ERROR << 16; 2707 dev_warn(&h->pdev->dev, 2708 "cp %p had HP SSD Smart Path error\n", cp); 2709 break; 2710 default: 2711 cmd->result = DID_ERROR << 16; 2712 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", 2713 cp, ei->CommandStatus); 2714 } 2715 2716 return hpsa_cmd_free_and_done(h, cp, cmd); 2717 } 2718 2719 static void hpsa_pci_unmap(struct pci_dev *pdev, 2720 struct CommandList *c, int sg_used, int data_direction) 2721 { 2722 int i; 2723 2724 for (i = 0; i < sg_used; i++) 2725 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr), 2726 le32_to_cpu(c->SG[i].Len), 2727 data_direction); 2728 } 2729 2730 static int hpsa_map_one(struct pci_dev *pdev, 2731 struct CommandList *cp, 2732 unsigned char *buf, 2733 size_t buflen, 2734 int data_direction) 2735 { 2736 u64 addr64; 2737 2738 if (buflen == 0 || data_direction == PCI_DMA_NONE) { 2739 cp->Header.SGList = 0; 2740 cp->Header.SGTotal = cpu_to_le16(0); 2741 return 0; 2742 } 2743 2744 addr64 = pci_map_single(pdev, buf, buflen, data_direction); 2745 if (dma_mapping_error(&pdev->dev, addr64)) { 2746 /* Prevent subsequent unmap of something never mapped */ 2747 cp->Header.SGList = 0; 2748 cp->Header.SGTotal = cpu_to_le16(0); 2749 return -1; 2750 } 2751 cp->SG[0].Addr = cpu_to_le64(addr64); 2752 cp->SG[0].Len = cpu_to_le32(buflen); 2753 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ 2754 cp->Header.SGList = 1; /* no. SGs contig in this cmd */ 2755 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ 2756 return 0; 2757 } 2758 2759 #define NO_TIMEOUT ((unsigned long) -1) 2760 #define DEFAULT_TIMEOUT 30000 /* milliseconds */ 2761 static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, 2762 struct CommandList *c, int reply_queue, unsigned long timeout_msecs) 2763 { 2764 DECLARE_COMPLETION_ONSTACK(wait); 2765 2766 c->waiting = &wait; 2767 __enqueue_cmd_and_start_io(h, c, reply_queue); 2768 if (timeout_msecs == NO_TIMEOUT) { 2769 /* TODO: get rid of this no-timeout thing */ 2770 wait_for_completion_io(&wait); 2771 return IO_OK; 2772 } 2773 if (!wait_for_completion_io_timeout(&wait, 2774 msecs_to_jiffies(timeout_msecs))) { 2775 dev_warn(&h->pdev->dev, "Command timed out.\n"); 2776 return -ETIMEDOUT; 2777 } 2778 return IO_OK; 2779 } 2780 2781 static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c, 2782 int reply_queue, unsigned long timeout_msecs) 2783 { 2784 if (unlikely(lockup_detected(h))) { 2785 c->err_info->CommandStatus = CMD_CTLR_LOCKUP; 2786 return IO_OK; 2787 } 2788 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs); 2789 } 2790 2791 static u32 lockup_detected(struct ctlr_info *h) 2792 { 2793 int cpu; 2794 u32 rc, *lockup_detected; 2795 2796 cpu = get_cpu(); 2797 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); 2798 rc = *lockup_detected; 2799 put_cpu(); 2800 return rc; 2801 } 2802 2803 #define MAX_DRIVER_CMD_RETRIES 25 2804 static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, 2805 struct CommandList *c, int data_direction, unsigned long timeout_msecs) 2806 { 2807 int backoff_time = 10, retry_count = 0; 2808 int rc; 2809 2810 do { 2811 memset(c->err_info, 0, sizeof(*c->err_info)); 2812 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 2813 timeout_msecs); 2814 if (rc) 2815 break; 2816 retry_count++; 2817 if (retry_count > 3) { 2818 msleep(backoff_time); 2819 if (backoff_time < 1000) 2820 backoff_time *= 2; 2821 } 2822 } while ((check_for_unit_attention(h, c) || 2823 check_for_busy(h, c)) && 2824 retry_count <= MAX_DRIVER_CMD_RETRIES); 2825 hpsa_pci_unmap(h->pdev, c, 1, data_direction); 2826 if (retry_count > MAX_DRIVER_CMD_RETRIES) 2827 rc = -EIO; 2828 return rc; 2829 } 2830 2831 static void hpsa_print_cmd(struct ctlr_info *h, char *txt, 2832 struct CommandList *c) 2833 { 2834 const u8 *cdb = c->Request.CDB; 2835 const u8 *lun = c->Header.LUN.LunAddrBytes; 2836 2837 dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n", 2838 txt, lun, cdb); 2839 } 2840 2841 static void hpsa_scsi_interpret_error(struct ctlr_info *h, 2842 struct CommandList *cp) 2843 { 2844 const struct ErrorInfo *ei = cp->err_info; 2845 struct device *d = &cp->h->pdev->dev; 2846 u8 sense_key, asc, ascq; 2847 int sense_len; 2848 2849 switch (ei->CommandStatus) { 2850 case CMD_TARGET_STATUS: 2851 if (ei->SenseLen > sizeof(ei->SenseInfo)) 2852 sense_len = sizeof(ei->SenseInfo); 2853 else 2854 sense_len = ei->SenseLen; 2855 decode_sense_data(ei->SenseInfo, sense_len, 2856 &sense_key, &asc, &ascq); 2857 hpsa_print_cmd(h, "SCSI status", cp); 2858 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) 2859 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n", 2860 sense_key, asc, ascq); 2861 else 2862 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus); 2863 if (ei->ScsiStatus == 0) 2864 dev_warn(d, "SCSI status is abnormally zero. " 2865 "(probably indicates selection timeout " 2866 "reported incorrectly due to a known " 2867 "firmware bug, circa July, 2001.)\n"); 2868 break; 2869 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ 2870 break; 2871 case CMD_DATA_OVERRUN: 2872 hpsa_print_cmd(h, "overrun condition", cp); 2873 break; 2874 case CMD_INVALID: { 2875 /* controller unfortunately reports SCSI passthru's 2876 * to non-existent targets as invalid commands. 2877 */ 2878 hpsa_print_cmd(h, "invalid command", cp); 2879 dev_warn(d, "probably means device no longer present\n"); 2880 } 2881 break; 2882 case CMD_PROTOCOL_ERR: 2883 hpsa_print_cmd(h, "protocol error", cp); 2884 break; 2885 case CMD_HARDWARE_ERR: 2886 hpsa_print_cmd(h, "hardware error", cp); 2887 break; 2888 case CMD_CONNECTION_LOST: 2889 hpsa_print_cmd(h, "connection lost", cp); 2890 break; 2891 case CMD_ABORTED: 2892 hpsa_print_cmd(h, "aborted", cp); 2893 break; 2894 case CMD_ABORT_FAILED: 2895 hpsa_print_cmd(h, "abort failed", cp); 2896 break; 2897 case CMD_UNSOLICITED_ABORT: 2898 hpsa_print_cmd(h, "unsolicited abort", cp); 2899 break; 2900 case CMD_TIMEOUT: 2901 hpsa_print_cmd(h, "timed out", cp); 2902 break; 2903 case CMD_UNABORTABLE: 2904 hpsa_print_cmd(h, "unabortable", cp); 2905 break; 2906 case CMD_CTLR_LOCKUP: 2907 hpsa_print_cmd(h, "controller lockup detected", cp); 2908 break; 2909 default: 2910 hpsa_print_cmd(h, "unknown status", cp); 2911 dev_warn(d, "Unknown command status %x\n", 2912 ei->CommandStatus); 2913 } 2914 } 2915 2916 static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, 2917 u16 page, unsigned char *buf, 2918 unsigned char bufsize) 2919 { 2920 int rc = IO_OK; 2921 struct CommandList *c; 2922 struct ErrorInfo *ei; 2923 2924 c = cmd_alloc(h); 2925 2926 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, 2927 page, scsi3addr, TYPE_CMD)) { 2928 rc = -1; 2929 goto out; 2930 } 2931 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 2932 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 2933 if (rc) 2934 goto out; 2935 ei = c->err_info; 2936 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 2937 hpsa_scsi_interpret_error(h, c); 2938 rc = -1; 2939 } 2940 out: 2941 cmd_free(h, c); 2942 return rc; 2943 } 2944 2945 static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr, 2946 u8 reset_type, int reply_queue) 2947 { 2948 int rc = IO_OK; 2949 struct CommandList *c; 2950 struct ErrorInfo *ei; 2951 2952 c = cmd_alloc(h); 2953 2954 2955 /* fill_cmd can't fail here, no data buffer to map. */ 2956 (void) fill_cmd(c, reset_type, h, NULL, 0, 0, 2957 scsi3addr, TYPE_MSG); 2958 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); 2959 if (rc) { 2960 dev_warn(&h->pdev->dev, "Failed to send reset command\n"); 2961 goto out; 2962 } 2963 /* no unmap needed here because no data xfer. */ 2964 2965 ei = c->err_info; 2966 if (ei->CommandStatus != 0) { 2967 hpsa_scsi_interpret_error(h, c); 2968 rc = -1; 2969 } 2970 out: 2971 cmd_free(h, c); 2972 return rc; 2973 } 2974 2975 static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, 2976 struct hpsa_scsi_dev_t *dev, 2977 unsigned char *scsi3addr) 2978 { 2979 int i; 2980 bool match = false; 2981 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 2982 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; 2983 2984 if (hpsa_is_cmd_idle(c)) 2985 return false; 2986 2987 switch (c->cmd_type) { 2988 case CMD_SCSI: 2989 case CMD_IOCTL_PEND: 2990 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes, 2991 sizeof(c->Header.LUN.LunAddrBytes)); 2992 break; 2993 2994 case CMD_IOACCEL1: 2995 case CMD_IOACCEL2: 2996 if (c->phys_disk == dev) { 2997 /* HBA mode match */ 2998 match = true; 2999 } else { 3000 /* Possible RAID mode -- check each phys dev. */ 3001 /* FIXME: Do we need to take out a lock here? If 3002 * so, we could just call hpsa_get_pdisk_of_ioaccel2() 3003 * instead. */ 3004 for (i = 0; i < dev->nphysical_disks && !match; i++) { 3005 /* FIXME: an alternate test might be 3006 * 3007 * match = dev->phys_disk[i]->ioaccel_handle 3008 * == c2->scsi_nexus; */ 3009 match = dev->phys_disk[i] == c->phys_disk; 3010 } 3011 } 3012 break; 3013 3014 case IOACCEL2_TMF: 3015 for (i = 0; i < dev->nphysical_disks && !match; i++) { 3016 match = dev->phys_disk[i]->ioaccel_handle == 3017 le32_to_cpu(ac->it_nexus); 3018 } 3019 break; 3020 3021 case 0: /* The command is in the middle of being initialized. */ 3022 match = false; 3023 break; 3024 3025 default: 3026 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n", 3027 c->cmd_type); 3028 BUG(); 3029 } 3030 3031 return match; 3032 } 3033 3034 static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, 3035 unsigned char *scsi3addr, u8 reset_type, int reply_queue) 3036 { 3037 int i; 3038 int rc = 0; 3039 3040 /* We can really only handle one reset at a time */ 3041 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) { 3042 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n"); 3043 return -EINTR; 3044 } 3045 3046 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0); 3047 3048 for (i = 0; i < h->nr_cmds; i++) { 3049 struct CommandList *c = h->cmd_pool + i; 3050 int refcount = atomic_inc_return(&c->refcount); 3051 3052 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) { 3053 unsigned long flags; 3054 3055 /* 3056 * Mark the target command as having a reset pending, 3057 * then lock a lock so that the command cannot complete 3058 * while we're considering it. If the command is not 3059 * idle then count it; otherwise revoke the event. 3060 */ 3061 c->reset_pending = dev; 3062 spin_lock_irqsave(&h->lock, flags); /* Implied MB */ 3063 if (!hpsa_is_cmd_idle(c)) 3064 atomic_inc(&dev->reset_cmds_out); 3065 else 3066 c->reset_pending = NULL; 3067 spin_unlock_irqrestore(&h->lock, flags); 3068 } 3069 3070 cmd_free(h, c); 3071 } 3072 3073 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue); 3074 if (!rc) 3075 wait_event(h->event_sync_wait_queue, 3076 atomic_read(&dev->reset_cmds_out) == 0 || 3077 lockup_detected(h)); 3078 3079 if (unlikely(lockup_detected(h))) { 3080 dev_warn(&h->pdev->dev, 3081 "Controller lockup detected during reset wait\n"); 3082 rc = -ENODEV; 3083 } 3084 3085 if (unlikely(rc)) 3086 atomic_set(&dev->reset_cmds_out, 0); 3087 else 3088 rc = wait_for_device_to_become_ready(h, scsi3addr, 0); 3089 3090 mutex_unlock(&h->reset_mutex); 3091 return rc; 3092 } 3093 3094 static void hpsa_get_raid_level(struct ctlr_info *h, 3095 unsigned char *scsi3addr, unsigned char *raid_level) 3096 { 3097 int rc; 3098 unsigned char *buf; 3099 3100 *raid_level = RAID_UNKNOWN; 3101 buf = kzalloc(64, GFP_KERNEL); 3102 if (!buf) 3103 return; 3104 3105 if (!hpsa_vpd_page_supported(h, scsi3addr, 3106 HPSA_VPD_LV_DEVICE_GEOMETRY)) 3107 goto exit; 3108 3109 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 3110 HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64); 3111 3112 if (rc == 0) 3113 *raid_level = buf[8]; 3114 if (*raid_level > RAID_UNKNOWN) 3115 *raid_level = RAID_UNKNOWN; 3116 exit: 3117 kfree(buf); 3118 return; 3119 } 3120 3121 #define HPSA_MAP_DEBUG 3122 #ifdef HPSA_MAP_DEBUG 3123 static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, 3124 struct raid_map_data *map_buff) 3125 { 3126 struct raid_map_disk_data *dd = &map_buff->data[0]; 3127 int map, row, col; 3128 u16 map_cnt, row_cnt, disks_per_row; 3129 3130 if (rc != 0) 3131 return; 3132 3133 /* Show details only if debugging has been activated. */ 3134 if (h->raid_offload_debug < 2) 3135 return; 3136 3137 dev_info(&h->pdev->dev, "structure_size = %u\n", 3138 le32_to_cpu(map_buff->structure_size)); 3139 dev_info(&h->pdev->dev, "volume_blk_size = %u\n", 3140 le32_to_cpu(map_buff->volume_blk_size)); 3141 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", 3142 le64_to_cpu(map_buff->volume_blk_cnt)); 3143 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", 3144 map_buff->phys_blk_shift); 3145 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", 3146 map_buff->parity_rotation_shift); 3147 dev_info(&h->pdev->dev, "strip_size = %u\n", 3148 le16_to_cpu(map_buff->strip_size)); 3149 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", 3150 le64_to_cpu(map_buff->disk_starting_blk)); 3151 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", 3152 le64_to_cpu(map_buff->disk_blk_cnt)); 3153 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", 3154 le16_to_cpu(map_buff->data_disks_per_row)); 3155 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", 3156 le16_to_cpu(map_buff->metadata_disks_per_row)); 3157 dev_info(&h->pdev->dev, "row_cnt = %u\n", 3158 le16_to_cpu(map_buff->row_cnt)); 3159 dev_info(&h->pdev->dev, "layout_map_count = %u\n", 3160 le16_to_cpu(map_buff->layout_map_count)); 3161 dev_info(&h->pdev->dev, "flags = 0x%x\n", 3162 le16_to_cpu(map_buff->flags)); 3163 dev_info(&h->pdev->dev, "encryption = %s\n", 3164 le16_to_cpu(map_buff->flags) & 3165 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); 3166 dev_info(&h->pdev->dev, "dekindex = %u\n", 3167 le16_to_cpu(map_buff->dekindex)); 3168 map_cnt = le16_to_cpu(map_buff->layout_map_count); 3169 for (map = 0; map < map_cnt; map++) { 3170 dev_info(&h->pdev->dev, "Map%u:\n", map); 3171 row_cnt = le16_to_cpu(map_buff->row_cnt); 3172 for (row = 0; row < row_cnt; row++) { 3173 dev_info(&h->pdev->dev, " Row%u:\n", row); 3174 disks_per_row = 3175 le16_to_cpu(map_buff->data_disks_per_row); 3176 for (col = 0; col < disks_per_row; col++, dd++) 3177 dev_info(&h->pdev->dev, 3178 " D%02u: h=0x%04x xor=%u,%u\n", 3179 col, dd->ioaccel_handle, 3180 dd->xor_mult[0], dd->xor_mult[1]); 3181 disks_per_row = 3182 le16_to_cpu(map_buff->metadata_disks_per_row); 3183 for (col = 0; col < disks_per_row; col++, dd++) 3184 dev_info(&h->pdev->dev, 3185 " M%02u: h=0x%04x xor=%u,%u\n", 3186 col, dd->ioaccel_handle, 3187 dd->xor_mult[0], dd->xor_mult[1]); 3188 } 3189 } 3190 } 3191 #else 3192 static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, 3193 __attribute__((unused)) int rc, 3194 __attribute__((unused)) struct raid_map_data *map_buff) 3195 { 3196 } 3197 #endif 3198 3199 static int hpsa_get_raid_map(struct ctlr_info *h, 3200 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) 3201 { 3202 int rc = 0; 3203 struct CommandList *c; 3204 struct ErrorInfo *ei; 3205 3206 c = cmd_alloc(h); 3207 3208 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, 3209 sizeof(this_device->raid_map), 0, 3210 scsi3addr, TYPE_CMD)) { 3211 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n"); 3212 cmd_free(h, c); 3213 return -1; 3214 } 3215 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3216 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 3217 if (rc) 3218 goto out; 3219 ei = c->err_info; 3220 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3221 hpsa_scsi_interpret_error(h, c); 3222 rc = -1; 3223 goto out; 3224 } 3225 cmd_free(h, c); 3226 3227 /* @todo in the future, dynamically allocate RAID map memory */ 3228 if (le32_to_cpu(this_device->raid_map.structure_size) > 3229 sizeof(this_device->raid_map)) { 3230 dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); 3231 rc = -1; 3232 } 3233 hpsa_debug_map_buff(h, rc, &this_device->raid_map); 3234 return rc; 3235 out: 3236 cmd_free(h, c); 3237 return rc; 3238 } 3239 3240 static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h, 3241 unsigned char scsi3addr[], u16 bmic_device_index, 3242 struct bmic_sense_subsystem_info *buf, size_t bufsize) 3243 { 3244 int rc = IO_OK; 3245 struct CommandList *c; 3246 struct ErrorInfo *ei; 3247 3248 c = cmd_alloc(h); 3249 3250 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize, 3251 0, RAID_CTLR_LUNID, TYPE_CMD); 3252 if (rc) 3253 goto out; 3254 3255 c->Request.CDB[2] = bmic_device_index & 0xff; 3256 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; 3257 3258 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3259 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 3260 if (rc) 3261 goto out; 3262 ei = c->err_info; 3263 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3264 hpsa_scsi_interpret_error(h, c); 3265 rc = -1; 3266 } 3267 out: 3268 cmd_free(h, c); 3269 return rc; 3270 } 3271 3272 static int hpsa_bmic_id_controller(struct ctlr_info *h, 3273 struct bmic_identify_controller *buf, size_t bufsize) 3274 { 3275 int rc = IO_OK; 3276 struct CommandList *c; 3277 struct ErrorInfo *ei; 3278 3279 c = cmd_alloc(h); 3280 3281 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize, 3282 0, RAID_CTLR_LUNID, TYPE_CMD); 3283 if (rc) 3284 goto out; 3285 3286 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3287 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 3288 if (rc) 3289 goto out; 3290 ei = c->err_info; 3291 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3292 hpsa_scsi_interpret_error(h, c); 3293 rc = -1; 3294 } 3295 out: 3296 cmd_free(h, c); 3297 return rc; 3298 } 3299 3300 static int hpsa_bmic_id_physical_device(struct ctlr_info *h, 3301 unsigned char scsi3addr[], u16 bmic_device_index, 3302 struct bmic_identify_physical_device *buf, size_t bufsize) 3303 { 3304 int rc = IO_OK; 3305 struct CommandList *c; 3306 struct ErrorInfo *ei; 3307 3308 c = cmd_alloc(h); 3309 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, 3310 0, RAID_CTLR_LUNID, TYPE_CMD); 3311 if (rc) 3312 goto out; 3313 3314 c->Request.CDB[2] = bmic_device_index & 0xff; 3315 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; 3316 3317 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, 3318 DEFAULT_TIMEOUT); 3319 ei = c->err_info; 3320 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3321 hpsa_scsi_interpret_error(h, c); 3322 rc = -1; 3323 } 3324 out: 3325 cmd_free(h, c); 3326 3327 return rc; 3328 } 3329 3330 /* 3331 * get enclosure information 3332 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number 3333 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure 3334 * Uses id_physical_device to determine the box_index. 3335 */ 3336 static void hpsa_get_enclosure_info(struct ctlr_info *h, 3337 unsigned char *scsi3addr, 3338 struct ReportExtendedLUNdata *rlep, int rle_index, 3339 struct hpsa_scsi_dev_t *encl_dev) 3340 { 3341 int rc = -1; 3342 struct CommandList *c = NULL; 3343 struct ErrorInfo *ei = NULL; 3344 struct bmic_sense_storage_box_params *bssbp = NULL; 3345 struct bmic_identify_physical_device *id_phys = NULL; 3346 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; 3347 u16 bmic_device_index = 0; 3348 3349 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]); 3350 3351 if (encl_dev->target == -1 || encl_dev->lun == -1) { 3352 rc = IO_OK; 3353 goto out; 3354 } 3355 3356 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) { 3357 rc = IO_OK; 3358 goto out; 3359 } 3360 3361 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL); 3362 if (!bssbp) 3363 goto out; 3364 3365 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 3366 if (!id_phys) 3367 goto out; 3368 3369 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index, 3370 id_phys, sizeof(*id_phys)); 3371 if (rc) { 3372 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n", 3373 __func__, encl_dev->external, bmic_device_index); 3374 goto out; 3375 } 3376 3377 c = cmd_alloc(h); 3378 3379 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp, 3380 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD); 3381 3382 if (rc) 3383 goto out; 3384 3385 if (id_phys->phys_connector[1] == 'E') 3386 c->Request.CDB[5] = id_phys->box_index; 3387 else 3388 c->Request.CDB[5] = 0; 3389 3390 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, 3391 DEFAULT_TIMEOUT); 3392 if (rc) 3393 goto out; 3394 3395 ei = c->err_info; 3396 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { 3397 rc = -1; 3398 goto out; 3399 } 3400 3401 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port; 3402 memcpy(&encl_dev->phys_connector[id_phys->active_path_number], 3403 bssbp->phys_connector, sizeof(bssbp->phys_connector)); 3404 3405 rc = IO_OK; 3406 out: 3407 kfree(bssbp); 3408 kfree(id_phys); 3409 3410 if (c) 3411 cmd_free(h, c); 3412 3413 if (rc != IO_OK) 3414 hpsa_show_dev_msg(KERN_INFO, h, encl_dev, 3415 "Error, could not get enclosure information\n"); 3416 } 3417 3418 static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h, 3419 unsigned char *scsi3addr) 3420 { 3421 struct ReportExtendedLUNdata *physdev; 3422 u32 nphysicals; 3423 u64 sa = 0; 3424 int i; 3425 3426 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL); 3427 if (!physdev) 3428 return 0; 3429 3430 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { 3431 dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); 3432 kfree(physdev); 3433 return 0; 3434 } 3435 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24; 3436 3437 for (i = 0; i < nphysicals; i++) 3438 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) { 3439 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]); 3440 break; 3441 } 3442 3443 kfree(physdev); 3444 3445 return sa; 3446 } 3447 3448 static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr, 3449 struct hpsa_scsi_dev_t *dev) 3450 { 3451 int rc; 3452 u64 sa = 0; 3453 3454 if (is_hba_lunid(scsi3addr)) { 3455 struct bmic_sense_subsystem_info *ssi; 3456 3457 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); 3458 if (!ssi) 3459 return; 3460 3461 rc = hpsa_bmic_sense_subsystem_information(h, 3462 scsi3addr, 0, ssi, sizeof(*ssi)); 3463 if (rc == 0) { 3464 sa = get_unaligned_be64(ssi->primary_world_wide_id); 3465 h->sas_address = sa; 3466 } 3467 3468 kfree(ssi); 3469 } else 3470 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr); 3471 3472 dev->sas_address = sa; 3473 } 3474 3475 /* Get a device id from inquiry page 0x83 */ 3476 static bool hpsa_vpd_page_supported(struct ctlr_info *h, 3477 unsigned char scsi3addr[], u8 page) 3478 { 3479 int rc; 3480 int i; 3481 int pages; 3482 unsigned char *buf, bufsize; 3483 3484 buf = kzalloc(256, GFP_KERNEL); 3485 if (!buf) 3486 return false; 3487 3488 /* Get the size of the page list first */ 3489 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3490 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, 3491 buf, HPSA_VPD_HEADER_SZ); 3492 if (rc != 0) 3493 goto exit_unsupported; 3494 pages = buf[3]; 3495 if ((pages + HPSA_VPD_HEADER_SZ) <= 255) 3496 bufsize = pages + HPSA_VPD_HEADER_SZ; 3497 else 3498 bufsize = 255; 3499 3500 /* Get the whole VPD page list */ 3501 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3502 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, 3503 buf, bufsize); 3504 if (rc != 0) 3505 goto exit_unsupported; 3506 3507 pages = buf[3]; 3508 for (i = 1; i <= pages; i++) 3509 if (buf[3 + i] == page) 3510 goto exit_supported; 3511 exit_unsupported: 3512 kfree(buf); 3513 return false; 3514 exit_supported: 3515 kfree(buf); 3516 return true; 3517 } 3518 3519 static void hpsa_get_ioaccel_status(struct ctlr_info *h, 3520 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) 3521 { 3522 int rc; 3523 unsigned char *buf; 3524 u8 ioaccel_status; 3525 3526 this_device->offload_config = 0; 3527 this_device->offload_enabled = 0; 3528 this_device->offload_to_be_enabled = 0; 3529 3530 buf = kzalloc(64, GFP_KERNEL); 3531 if (!buf) 3532 return; 3533 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) 3534 goto out; 3535 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 3536 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); 3537 if (rc != 0) 3538 goto out; 3539 3540 #define IOACCEL_STATUS_BYTE 4 3541 #define OFFLOAD_CONFIGURED_BIT 0x01 3542 #define OFFLOAD_ENABLED_BIT 0x02 3543 ioaccel_status = buf[IOACCEL_STATUS_BYTE]; 3544 this_device->offload_config = 3545 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); 3546 if (this_device->offload_config) { 3547 this_device->offload_enabled = 3548 !!(ioaccel_status & OFFLOAD_ENABLED_BIT); 3549 if (hpsa_get_raid_map(h, scsi3addr, this_device)) 3550 this_device->offload_enabled = 0; 3551 } 3552 this_device->offload_to_be_enabled = this_device->offload_enabled; 3553 out: 3554 kfree(buf); 3555 return; 3556 } 3557 3558 /* Get the device id from inquiry page 0x83 */ 3559 static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, 3560 unsigned char *device_id, int index, int buflen) 3561 { 3562 int rc; 3563 unsigned char *buf; 3564 3565 /* Does controller have VPD for device id? */ 3566 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID)) 3567 return 1; /* not supported */ 3568 3569 buf = kzalloc(64, GFP_KERNEL); 3570 if (!buf) 3571 return -ENOMEM; 3572 3573 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 3574 HPSA_VPD_LV_DEVICE_ID, buf, 64); 3575 if (rc == 0) { 3576 if (buflen > 16) 3577 buflen = 16; 3578 memcpy(device_id, &buf[8], buflen); 3579 } 3580 3581 kfree(buf); 3582 3583 return rc; /*0 - got id, otherwise, didn't */ 3584 } 3585 3586 static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, 3587 void *buf, int bufsize, 3588 int extended_response) 3589 { 3590 int rc = IO_OK; 3591 struct CommandList *c; 3592 unsigned char scsi3addr[8]; 3593 struct ErrorInfo *ei; 3594 3595 c = cmd_alloc(h); 3596 3597 /* address the controller */ 3598 memset(scsi3addr, 0, sizeof(scsi3addr)); 3599 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, 3600 buf, bufsize, 0, scsi3addr, TYPE_CMD)) { 3601 rc = -EAGAIN; 3602 goto out; 3603 } 3604 if (extended_response) 3605 c->Request.CDB[1] = extended_response; 3606 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 3607 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 3608 if (rc) 3609 goto out; 3610 ei = c->err_info; 3611 if (ei->CommandStatus != 0 && 3612 ei->CommandStatus != CMD_DATA_UNDERRUN) { 3613 hpsa_scsi_interpret_error(h, c); 3614 rc = -EIO; 3615 } else { 3616 struct ReportLUNdata *rld = buf; 3617 3618 if (rld->extended_response_flag != extended_response) { 3619 if (!h->legacy_board) { 3620 dev_err(&h->pdev->dev, 3621 "report luns requested format %u, got %u\n", 3622 extended_response, 3623 rld->extended_response_flag); 3624 rc = -EINVAL; 3625 } else 3626 rc = -EOPNOTSUPP; 3627 } 3628 } 3629 out: 3630 cmd_free(h, c); 3631 return rc; 3632 } 3633 3634 static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, 3635 struct ReportExtendedLUNdata *buf, int bufsize) 3636 { 3637 int rc; 3638 struct ReportLUNdata *lbuf; 3639 3640 rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize, 3641 HPSA_REPORT_PHYS_EXTENDED); 3642 if (!rc || rc != -EOPNOTSUPP) 3643 return rc; 3644 3645 /* REPORT PHYS EXTENDED is not supported */ 3646 lbuf = kzalloc(sizeof(*lbuf), GFP_KERNEL); 3647 if (!lbuf) 3648 return -ENOMEM; 3649 3650 rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0); 3651 if (!rc) { 3652 int i; 3653 u32 nphys; 3654 3655 /* Copy ReportLUNdata header */ 3656 memcpy(buf, lbuf, 8); 3657 nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8; 3658 for (i = 0; i < nphys; i++) 3659 memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8); 3660 } 3661 kfree(lbuf); 3662 return rc; 3663 } 3664 3665 static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, 3666 struct ReportLUNdata *buf, int bufsize) 3667 { 3668 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); 3669 } 3670 3671 static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, 3672 int bus, int target, int lun) 3673 { 3674 device->bus = bus; 3675 device->target = target; 3676 device->lun = lun; 3677 } 3678 3679 /* Use VPD inquiry to get details of volume status */ 3680 static int hpsa_get_volume_status(struct ctlr_info *h, 3681 unsigned char scsi3addr[]) 3682 { 3683 int rc; 3684 int status; 3685 int size; 3686 unsigned char *buf; 3687 3688 buf = kzalloc(64, GFP_KERNEL); 3689 if (!buf) 3690 return HPSA_VPD_LV_STATUS_UNSUPPORTED; 3691 3692 /* Does controller have VPD for logical volume status? */ 3693 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) 3694 goto exit_failed; 3695 3696 /* Get the size of the VPD return buffer */ 3697 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, 3698 buf, HPSA_VPD_HEADER_SZ); 3699 if (rc != 0) 3700 goto exit_failed; 3701 size = buf[3]; 3702 3703 /* Now get the whole VPD buffer */ 3704 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, 3705 buf, size + HPSA_VPD_HEADER_SZ); 3706 if (rc != 0) 3707 goto exit_failed; 3708 status = buf[4]; /* status byte */ 3709 3710 kfree(buf); 3711 return status; 3712 exit_failed: 3713 kfree(buf); 3714 return HPSA_VPD_LV_STATUS_UNSUPPORTED; 3715 } 3716 3717 /* Determine offline status of a volume. 3718 * Return either: 3719 * 0 (not offline) 3720 * 0xff (offline for unknown reasons) 3721 * # (integer code indicating one of several NOT READY states 3722 * describing why a volume is to be kept offline) 3723 */ 3724 static unsigned char hpsa_volume_offline(struct ctlr_info *h, 3725 unsigned char scsi3addr[]) 3726 { 3727 struct CommandList *c; 3728 unsigned char *sense; 3729 u8 sense_key, asc, ascq; 3730 int sense_len; 3731 int rc, ldstat = 0; 3732 u16 cmd_status; 3733 u8 scsi_status; 3734 #define ASC_LUN_NOT_READY 0x04 3735 #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 3736 #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 3737 3738 c = cmd_alloc(h); 3739 3740 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); 3741 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 3742 DEFAULT_TIMEOUT); 3743 if (rc) { 3744 cmd_free(h, c); 3745 return HPSA_VPD_LV_STATUS_UNSUPPORTED; 3746 } 3747 sense = c->err_info->SenseInfo; 3748 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) 3749 sense_len = sizeof(c->err_info->SenseInfo); 3750 else 3751 sense_len = c->err_info->SenseLen; 3752 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq); 3753 cmd_status = c->err_info->CommandStatus; 3754 scsi_status = c->err_info->ScsiStatus; 3755 cmd_free(h, c); 3756 3757 /* Determine the reason for not ready state */ 3758 ldstat = hpsa_get_volume_status(h, scsi3addr); 3759 3760 /* Keep volume offline in certain cases: */ 3761 switch (ldstat) { 3762 case HPSA_LV_FAILED: 3763 case HPSA_LV_UNDERGOING_ERASE: 3764 case HPSA_LV_NOT_AVAILABLE: 3765 case HPSA_LV_UNDERGOING_RPI: 3766 case HPSA_LV_PENDING_RPI: 3767 case HPSA_LV_ENCRYPTED_NO_KEY: 3768 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: 3769 case HPSA_LV_UNDERGOING_ENCRYPTION: 3770 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: 3771 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: 3772 return ldstat; 3773 case HPSA_VPD_LV_STATUS_UNSUPPORTED: 3774 /* If VPD status page isn't available, 3775 * use ASC/ASCQ to determine state 3776 */ 3777 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || 3778 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) 3779 return ldstat; 3780 break; 3781 default: 3782 break; 3783 } 3784 return HPSA_LV_OK; 3785 } 3786 3787 static int hpsa_update_device_info(struct ctlr_info *h, 3788 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, 3789 unsigned char *is_OBDR_device) 3790 { 3791 3792 #define OBDR_SIG_OFFSET 43 3793 #define OBDR_TAPE_SIG "$DR-10" 3794 #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) 3795 #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) 3796 3797 unsigned char *inq_buff; 3798 unsigned char *obdr_sig; 3799 int rc = 0; 3800 3801 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); 3802 if (!inq_buff) { 3803 rc = -ENOMEM; 3804 goto bail_out; 3805 } 3806 3807 /* Do an inquiry to the device to see what it is. */ 3808 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, 3809 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { 3810 dev_err(&h->pdev->dev, 3811 "%s: inquiry failed, device will be skipped.\n", 3812 __func__); 3813 rc = HPSA_INQUIRY_FAILED; 3814 goto bail_out; 3815 } 3816 3817 scsi_sanitize_inquiry_string(&inq_buff[8], 8); 3818 scsi_sanitize_inquiry_string(&inq_buff[16], 16); 3819 3820 this_device->devtype = (inq_buff[0] & 0x1f); 3821 memcpy(this_device->scsi3addr, scsi3addr, 8); 3822 memcpy(this_device->vendor, &inq_buff[8], 3823 sizeof(this_device->vendor)); 3824 memcpy(this_device->model, &inq_buff[16], 3825 sizeof(this_device->model)); 3826 this_device->rev = inq_buff[2]; 3827 memset(this_device->device_id, 0, 3828 sizeof(this_device->device_id)); 3829 if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, 3830 sizeof(this_device->device_id)) < 0) 3831 dev_err(&h->pdev->dev, 3832 "hpsa%d: %s: can't get device id for host %d:C0:T%d:L%d\t%s\t%.16s\n", 3833 h->ctlr, __func__, 3834 h->scsi_host->host_no, 3835 this_device->target, this_device->lun, 3836 scsi_device_type(this_device->devtype), 3837 this_device->model); 3838 3839 if ((this_device->devtype == TYPE_DISK || 3840 this_device->devtype == TYPE_ZBC) && 3841 is_logical_dev_addr_mode(scsi3addr)) { 3842 unsigned char volume_offline; 3843 3844 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); 3845 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) 3846 hpsa_get_ioaccel_status(h, scsi3addr, this_device); 3847 volume_offline = hpsa_volume_offline(h, scsi3addr); 3848 if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED && 3849 h->legacy_board) { 3850 /* 3851 * Legacy boards might not support volume status 3852 */ 3853 dev_info(&h->pdev->dev, 3854 "C0:T%d:L%d Volume status not available, assuming online.\n", 3855 this_device->target, this_device->lun); 3856 volume_offline = 0; 3857 } 3858 this_device->volume_offline = volume_offline; 3859 if (volume_offline == HPSA_LV_FAILED) { 3860 rc = HPSA_LV_FAILED; 3861 dev_err(&h->pdev->dev, 3862 "%s: LV failed, device will be skipped.\n", 3863 __func__); 3864 goto bail_out; 3865 } 3866 } else { 3867 this_device->raid_level = RAID_UNKNOWN; 3868 this_device->offload_config = 0; 3869 this_device->offload_enabled = 0; 3870 this_device->offload_to_be_enabled = 0; 3871 this_device->hba_ioaccel_enabled = 0; 3872 this_device->volume_offline = 0; 3873 this_device->queue_depth = h->nr_cmds; 3874 } 3875 3876 if (this_device->external) 3877 this_device->queue_depth = EXTERNAL_QD; 3878 3879 if (is_OBDR_device) { 3880 /* See if this is a One-Button-Disaster-Recovery device 3881 * by looking for "$DR-10" at offset 43 in inquiry data. 3882 */ 3883 obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; 3884 *is_OBDR_device = (this_device->devtype == TYPE_ROM && 3885 strncmp(obdr_sig, OBDR_TAPE_SIG, 3886 OBDR_SIG_LEN) == 0); 3887 } 3888 kfree(inq_buff); 3889 return 0; 3890 3891 bail_out: 3892 kfree(inq_buff); 3893 return rc; 3894 } 3895 3896 /* 3897 * Helper function to assign bus, target, lun mapping of devices. 3898 * Logical drive target and lun are assigned at this time, but 3899 * physical device lun and target assignment are deferred (assigned 3900 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) 3901 */ 3902 static void figure_bus_target_lun(struct ctlr_info *h, 3903 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) 3904 { 3905 u32 lunid = get_unaligned_le32(lunaddrbytes); 3906 3907 if (!is_logical_dev_addr_mode(lunaddrbytes)) { 3908 /* physical device, target and lun filled in later */ 3909 if (is_hba_lunid(lunaddrbytes)) { 3910 int bus = HPSA_HBA_BUS; 3911 3912 if (!device->rev) 3913 bus = HPSA_LEGACY_HBA_BUS; 3914 hpsa_set_bus_target_lun(device, 3915 bus, 0, lunid & 0x3fff); 3916 } else 3917 /* defer target, lun assignment for physical devices */ 3918 hpsa_set_bus_target_lun(device, 3919 HPSA_PHYSICAL_DEVICE_BUS, -1, -1); 3920 return; 3921 } 3922 /* It's a logical device */ 3923 if (device->external) { 3924 hpsa_set_bus_target_lun(device, 3925 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff, 3926 lunid & 0x00ff); 3927 return; 3928 } 3929 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS, 3930 0, lunid & 0x3fff); 3931 } 3932 3933 static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position, 3934 int i, int nphysicals, int nlocal_logicals) 3935 { 3936 /* In report logicals, local logicals are listed first, 3937 * then any externals. 3938 */ 3939 int logicals_start = nphysicals + (raid_ctlr_position == 0); 3940 3941 if (i == raid_ctlr_position) 3942 return 0; 3943 3944 if (i < logicals_start) 3945 return 0; 3946 3947 /* i is in logicals range, but still within local logicals */ 3948 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals) 3949 return 0; 3950 3951 return 1; /* it's an external lun */ 3952 } 3953 3954 /* 3955 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, 3956 * logdev. The number of luns in physdev and logdev are returned in 3957 * *nphysicals and *nlogicals, respectively. 3958 * Returns 0 on success, -1 otherwise. 3959 */ 3960 static int hpsa_gather_lun_info(struct ctlr_info *h, 3961 struct ReportExtendedLUNdata *physdev, u32 *nphysicals, 3962 struct ReportLUNdata *logdev, u32 *nlogicals) 3963 { 3964 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { 3965 dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); 3966 return -1; 3967 } 3968 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; 3969 if (*nphysicals > HPSA_MAX_PHYS_LUN) { 3970 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", 3971 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); 3972 *nphysicals = HPSA_MAX_PHYS_LUN; 3973 } 3974 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { 3975 dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); 3976 return -1; 3977 } 3978 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; 3979 /* Reject Logicals in excess of our max capability. */ 3980 if (*nlogicals > HPSA_MAX_LUN) { 3981 dev_warn(&h->pdev->dev, 3982 "maximum logical LUNs (%d) exceeded. " 3983 "%d LUNs ignored.\n", HPSA_MAX_LUN, 3984 *nlogicals - HPSA_MAX_LUN); 3985 *nlogicals = HPSA_MAX_LUN; 3986 } 3987 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { 3988 dev_warn(&h->pdev->dev, 3989 "maximum logical + physical LUNs (%d) exceeded. " 3990 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, 3991 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); 3992 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; 3993 } 3994 return 0; 3995 } 3996 3997 static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, 3998 int i, int nphysicals, int nlogicals, 3999 struct ReportExtendedLUNdata *physdev_list, 4000 struct ReportLUNdata *logdev_list) 4001 { 4002 /* Helper function, figure out where the LUN ID info is coming from 4003 * given index i, lists of physical and logical devices, where in 4004 * the list the raid controller is supposed to appear (first or last) 4005 */ 4006 4007 int logicals_start = nphysicals + (raid_ctlr_position == 0); 4008 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); 4009 4010 if (i == raid_ctlr_position) 4011 return RAID_CTLR_LUNID; 4012 4013 if (i < logicals_start) 4014 return &physdev_list->LUN[i - 4015 (raid_ctlr_position == 0)].lunid[0]; 4016 4017 if (i < last_device) 4018 return &logdev_list->LUN[i - nphysicals - 4019 (raid_ctlr_position == 0)][0]; 4020 BUG(); 4021 return NULL; 4022 } 4023 4024 /* get physical drive ioaccel handle and queue depth */ 4025 static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, 4026 struct hpsa_scsi_dev_t *dev, 4027 struct ReportExtendedLUNdata *rlep, int rle_index, 4028 struct bmic_identify_physical_device *id_phys) 4029 { 4030 int rc; 4031 struct ext_report_lun_entry *rle; 4032 4033 rle = &rlep->LUN[rle_index]; 4034 4035 dev->ioaccel_handle = rle->ioaccel_handle; 4036 if ((rle->device_flags & 0x08) && dev->ioaccel_handle) 4037 dev->hba_ioaccel_enabled = 1; 4038 memset(id_phys, 0, sizeof(*id_phys)); 4039 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0], 4040 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys, 4041 sizeof(*id_phys)); 4042 if (!rc) 4043 /* Reserve space for FW operations */ 4044 #define DRIVE_CMDS_RESERVED_FOR_FW 2 4045 #define DRIVE_QUEUE_DEPTH 7 4046 dev->queue_depth = 4047 le16_to_cpu(id_phys->current_queue_depth_limit) - 4048 DRIVE_CMDS_RESERVED_FOR_FW; 4049 else 4050 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ 4051 } 4052 4053 static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device, 4054 struct ReportExtendedLUNdata *rlep, int rle_index, 4055 struct bmic_identify_physical_device *id_phys) 4056 { 4057 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; 4058 4059 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle) 4060 this_device->hba_ioaccel_enabled = 1; 4061 4062 memcpy(&this_device->active_path_index, 4063 &id_phys->active_path_number, 4064 sizeof(this_device->active_path_index)); 4065 memcpy(&this_device->path_map, 4066 &id_phys->redundant_path_present_map, 4067 sizeof(this_device->path_map)); 4068 memcpy(&this_device->box, 4069 &id_phys->alternate_paths_phys_box_on_port, 4070 sizeof(this_device->box)); 4071 memcpy(&this_device->phys_connector, 4072 &id_phys->alternate_paths_phys_connector, 4073 sizeof(this_device->phys_connector)); 4074 memcpy(&this_device->bay, 4075 &id_phys->phys_bay_in_box, 4076 sizeof(this_device->bay)); 4077 } 4078 4079 /* get number of local logical disks. */ 4080 static int hpsa_set_local_logical_count(struct ctlr_info *h, 4081 struct bmic_identify_controller *id_ctlr, 4082 u32 *nlocals) 4083 { 4084 int rc; 4085 4086 if (!id_ctlr) { 4087 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n", 4088 __func__); 4089 return -ENOMEM; 4090 } 4091 memset(id_ctlr, 0, sizeof(*id_ctlr)); 4092 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr)); 4093 if (!rc) 4094 if (id_ctlr->configured_logical_drive_count < 256) 4095 *nlocals = id_ctlr->configured_logical_drive_count; 4096 else 4097 *nlocals = le16_to_cpu( 4098 id_ctlr->extended_logical_unit_count); 4099 else 4100 *nlocals = -1; 4101 return rc; 4102 } 4103 4104 static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes) 4105 { 4106 struct bmic_identify_physical_device *id_phys; 4107 bool is_spare = false; 4108 int rc; 4109 4110 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 4111 if (!id_phys) 4112 return false; 4113 4114 rc = hpsa_bmic_id_physical_device(h, 4115 lunaddrbytes, 4116 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), 4117 id_phys, sizeof(*id_phys)); 4118 if (rc == 0) 4119 is_spare = (id_phys->more_flags >> 6) & 0x01; 4120 4121 kfree(id_phys); 4122 return is_spare; 4123 } 4124 4125 #define RPL_DEV_FLAG_NON_DISK 0x1 4126 #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2 4127 #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4 4128 4129 #define BMIC_DEVICE_TYPE_ENCLOSURE 6 4130 4131 static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes, 4132 struct ext_report_lun_entry *rle) 4133 { 4134 u8 device_flags; 4135 u8 device_type; 4136 4137 if (!MASKED_DEVICE(lunaddrbytes)) 4138 return false; 4139 4140 device_flags = rle->device_flags; 4141 device_type = rle->device_type; 4142 4143 if (device_flags & RPL_DEV_FLAG_NON_DISK) { 4144 if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE) 4145 return false; 4146 return true; 4147 } 4148 4149 if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED)) 4150 return false; 4151 4152 if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK) 4153 return false; 4154 4155 /* 4156 * Spares may be spun down, we do not want to 4157 * do an Inquiry to a RAID set spare drive as 4158 * that would have them spun up, that is a 4159 * performance hit because I/O to the RAID device 4160 * stops while the spin up occurs which can take 4161 * over 50 seconds. 4162 */ 4163 if (hpsa_is_disk_spare(h, lunaddrbytes)) 4164 return true; 4165 4166 return false; 4167 } 4168 4169 static void hpsa_update_scsi_devices(struct ctlr_info *h) 4170 { 4171 /* the idea here is we could get notified 4172 * that some devices have changed, so we do a report 4173 * physical luns and report logical luns cmd, and adjust 4174 * our list of devices accordingly. 4175 * 4176 * The scsi3addr's of devices won't change so long as the 4177 * adapter is not reset. That means we can rescan and 4178 * tell which devices we already know about, vs. new 4179 * devices, vs. disappearing devices. 4180 */ 4181 struct ReportExtendedLUNdata *physdev_list = NULL; 4182 struct ReportLUNdata *logdev_list = NULL; 4183 struct bmic_identify_physical_device *id_phys = NULL; 4184 struct bmic_identify_controller *id_ctlr = NULL; 4185 u32 nphysicals = 0; 4186 u32 nlogicals = 0; 4187 u32 nlocal_logicals = 0; 4188 u32 ndev_allocated = 0; 4189 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; 4190 int ncurrent = 0; 4191 int i, n_ext_target_devs, ndevs_to_allocate; 4192 int raid_ctlr_position; 4193 bool physical_device; 4194 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); 4195 4196 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); 4197 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); 4198 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); 4199 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); 4200 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); 4201 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL); 4202 4203 if (!currentsd || !physdev_list || !logdev_list || 4204 !tmpdevice || !id_phys || !id_ctlr) { 4205 dev_err(&h->pdev->dev, "out of memory\n"); 4206 goto out; 4207 } 4208 memset(lunzerobits, 0, sizeof(lunzerobits)); 4209 4210 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */ 4211 4212 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, 4213 logdev_list, &nlogicals)) { 4214 h->drv_req_rescan = 1; 4215 goto out; 4216 } 4217 4218 /* Set number of local logicals (non PTRAID) */ 4219 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) { 4220 dev_warn(&h->pdev->dev, 4221 "%s: Can't determine number of local logical devices.\n", 4222 __func__); 4223 } 4224 4225 /* We might see up to the maximum number of logical and physical disks 4226 * plus external target devices, and a device for the local RAID 4227 * controller. 4228 */ 4229 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; 4230 4231 /* Allocate the per device structures */ 4232 for (i = 0; i < ndevs_to_allocate; i++) { 4233 if (i >= HPSA_MAX_DEVICES) { 4234 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." 4235 " %d devices ignored.\n", HPSA_MAX_DEVICES, 4236 ndevs_to_allocate - HPSA_MAX_DEVICES); 4237 break; 4238 } 4239 4240 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); 4241 if (!currentsd[i]) { 4242 h->drv_req_rescan = 1; 4243 goto out; 4244 } 4245 ndev_allocated++; 4246 } 4247 4248 if (is_scsi_rev_5(h)) 4249 raid_ctlr_position = 0; 4250 else 4251 raid_ctlr_position = nphysicals + nlogicals; 4252 4253 /* adjust our table of devices */ 4254 n_ext_target_devs = 0; 4255 for (i = 0; i < nphysicals + nlogicals + 1; i++) { 4256 u8 *lunaddrbytes, is_OBDR = 0; 4257 int rc = 0; 4258 int phys_dev_index = i - (raid_ctlr_position == 0); 4259 bool skip_device = false; 4260 4261 physical_device = i < nphysicals + (raid_ctlr_position == 0); 4262 4263 /* Figure out where the LUN ID info is coming from */ 4264 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, 4265 i, nphysicals, nlogicals, physdev_list, logdev_list); 4266 4267 /* Determine if this is a lun from an external target array */ 4268 tmpdevice->external = 4269 figure_external_status(h, raid_ctlr_position, i, 4270 nphysicals, nlocal_logicals); 4271 4272 /* 4273 * Skip over some devices such as a spare. 4274 */ 4275 if (!tmpdevice->external && physical_device) { 4276 skip_device = hpsa_skip_device(h, lunaddrbytes, 4277 &physdev_list->LUN[phys_dev_index]); 4278 if (skip_device) 4279 continue; 4280 } 4281 4282 /* Get device type, vendor, model, device id */ 4283 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice, 4284 &is_OBDR); 4285 if (rc == -ENOMEM) { 4286 dev_warn(&h->pdev->dev, 4287 "Out of memory, rescan deferred.\n"); 4288 h->drv_req_rescan = 1; 4289 goto out; 4290 } 4291 if (rc) { 4292 h->drv_req_rescan = 1; 4293 continue; 4294 } 4295 4296 figure_bus_target_lun(h, lunaddrbytes, tmpdevice); 4297 this_device = currentsd[ncurrent]; 4298 4299 /* Turn on discovery_polling if there are ext target devices. 4300 * Event-based change notification is unreliable for those. 4301 */ 4302 if (!h->discovery_polling) { 4303 if (tmpdevice->external) { 4304 h->discovery_polling = 1; 4305 dev_info(&h->pdev->dev, 4306 "External target, activate discovery polling.\n"); 4307 } 4308 } 4309 4310 4311 *this_device = *tmpdevice; 4312 this_device->physical_device = physical_device; 4313 4314 /* 4315 * Expose all devices except for physical devices that 4316 * are masked. 4317 */ 4318 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device) 4319 this_device->expose_device = 0; 4320 else 4321 this_device->expose_device = 1; 4322 4323 4324 /* 4325 * Get the SAS address for physical devices that are exposed. 4326 */ 4327 if (this_device->physical_device && this_device->expose_device) 4328 hpsa_get_sas_address(h, lunaddrbytes, this_device); 4329 4330 switch (this_device->devtype) { 4331 case TYPE_ROM: 4332 /* We don't *really* support actual CD-ROM devices, 4333 * just "One Button Disaster Recovery" tape drive 4334 * which temporarily pretends to be a CD-ROM drive. 4335 * So we check that the device is really an OBDR tape 4336 * device by checking for "$DR-10" in bytes 43-48 of 4337 * the inquiry data. 4338 */ 4339 if (is_OBDR) 4340 ncurrent++; 4341 break; 4342 case TYPE_DISK: 4343 case TYPE_ZBC: 4344 if (this_device->physical_device) { 4345 /* The disk is in HBA mode. */ 4346 /* Never use RAID mapper in HBA mode. */ 4347 this_device->offload_enabled = 0; 4348 hpsa_get_ioaccel_drive_info(h, this_device, 4349 physdev_list, phys_dev_index, id_phys); 4350 hpsa_get_path_info(this_device, 4351 physdev_list, phys_dev_index, id_phys); 4352 } 4353 ncurrent++; 4354 break; 4355 case TYPE_TAPE: 4356 case TYPE_MEDIUM_CHANGER: 4357 ncurrent++; 4358 break; 4359 case TYPE_ENCLOSURE: 4360 if (!this_device->external) 4361 hpsa_get_enclosure_info(h, lunaddrbytes, 4362 physdev_list, phys_dev_index, 4363 this_device); 4364 ncurrent++; 4365 break; 4366 case TYPE_RAID: 4367 /* Only present the Smartarray HBA as a RAID controller. 4368 * If it's a RAID controller other than the HBA itself 4369 * (an external RAID controller, MSA500 or similar) 4370 * don't present it. 4371 */ 4372 if (!is_hba_lunid(lunaddrbytes)) 4373 break; 4374 ncurrent++; 4375 break; 4376 default: 4377 break; 4378 } 4379 if (ncurrent >= HPSA_MAX_DEVICES) 4380 break; 4381 } 4382 4383 if (h->sas_host == NULL) { 4384 int rc = 0; 4385 4386 rc = hpsa_add_sas_host(h); 4387 if (rc) { 4388 dev_warn(&h->pdev->dev, 4389 "Could not add sas host %d\n", rc); 4390 goto out; 4391 } 4392 } 4393 4394 adjust_hpsa_scsi_table(h, currentsd, ncurrent); 4395 out: 4396 kfree(tmpdevice); 4397 for (i = 0; i < ndev_allocated; i++) 4398 kfree(currentsd[i]); 4399 kfree(currentsd); 4400 kfree(physdev_list); 4401 kfree(logdev_list); 4402 kfree(id_ctlr); 4403 kfree(id_phys); 4404 } 4405 4406 static void hpsa_set_sg_descriptor(struct SGDescriptor *desc, 4407 struct scatterlist *sg) 4408 { 4409 u64 addr64 = (u64) sg_dma_address(sg); 4410 unsigned int len = sg_dma_len(sg); 4411 4412 desc->Addr = cpu_to_le64(addr64); 4413 desc->Len = cpu_to_le32(len); 4414 desc->Ext = 0; 4415 } 4416 4417 /* 4418 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci 4419 * dma mapping and fills in the scatter gather entries of the 4420 * hpsa command, cp. 4421 */ 4422 static int hpsa_scatter_gather(struct ctlr_info *h, 4423 struct CommandList *cp, 4424 struct scsi_cmnd *cmd) 4425 { 4426 struct scatterlist *sg; 4427 int use_sg, i, sg_limit, chained, last_sg; 4428 struct SGDescriptor *curr_sg; 4429 4430 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); 4431 4432 use_sg = scsi_dma_map(cmd); 4433 if (use_sg < 0) 4434 return use_sg; 4435 4436 if (!use_sg) 4437 goto sglist_finished; 4438 4439 /* 4440 * If the number of entries is greater than the max for a single list, 4441 * then we have a chained list; we will set up all but one entry in the 4442 * first list (the last entry is saved for link information); 4443 * otherwise, we don't have a chained list and we'll set up at each of 4444 * the entries in the one list. 4445 */ 4446 curr_sg = cp->SG; 4447 chained = use_sg > h->max_cmd_sg_entries; 4448 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg; 4449 last_sg = scsi_sg_count(cmd) - 1; 4450 scsi_for_each_sg(cmd, sg, sg_limit, i) { 4451 hpsa_set_sg_descriptor(curr_sg, sg); 4452 curr_sg++; 4453 } 4454 4455 if (chained) { 4456 /* 4457 * Continue with the chained list. Set curr_sg to the chained 4458 * list. Modify the limit to the total count less the entries 4459 * we've already set up. Resume the scan at the list entry 4460 * where the previous loop left off. 4461 */ 4462 curr_sg = h->cmd_sg_list[cp->cmdindex]; 4463 sg_limit = use_sg - sg_limit; 4464 for_each_sg(sg, sg, sg_limit, i) { 4465 hpsa_set_sg_descriptor(curr_sg, sg); 4466 curr_sg++; 4467 } 4468 } 4469 4470 /* Back the pointer up to the last entry and mark it as "last". */ 4471 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST); 4472 4473 if (use_sg + chained > h->maxSG) 4474 h->maxSG = use_sg + chained; 4475 4476 if (chained) { 4477 cp->Header.SGList = h->max_cmd_sg_entries; 4478 cp->Header.SGTotal = cpu_to_le16(use_sg + 1); 4479 if (hpsa_map_sg_chain_block(h, cp)) { 4480 scsi_dma_unmap(cmd); 4481 return -1; 4482 } 4483 return 0; 4484 } 4485 4486 sglist_finished: 4487 4488 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ 4489 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ 4490 return 0; 4491 } 4492 4493 #define BUFLEN 128 4494 static inline void warn_zero_length_transfer(struct ctlr_info *h, 4495 u8 *cdb, int cdb_len, 4496 const char *func) 4497 { 4498 char buf[BUFLEN]; 4499 int outlen; 4500 int i; 4501 4502 outlen = scnprintf(buf, BUFLEN, 4503 "%s: Blocking zero-length request: CDB:", func); 4504 for (i = 0; i < cdb_len; i++) 4505 outlen += scnprintf(buf+outlen, BUFLEN - outlen, 4506 "%02hhx", cdb[i]); 4507 dev_warn(&h->pdev->dev, "%s\n", buf); 4508 } 4509 4510 #define IO_ACCEL_INELIGIBLE 1 4511 /* zero-length transfers trigger hardware errors. */ 4512 static bool is_zero_length_transfer(u8 *cdb) 4513 { 4514 u32 block_cnt; 4515 4516 /* Block zero-length transfer sizes on certain commands. */ 4517 switch (cdb[0]) { 4518 case READ_10: 4519 case WRITE_10: 4520 case VERIFY: /* 0x2F */ 4521 case WRITE_VERIFY: /* 0x2E */ 4522 block_cnt = get_unaligned_be16(&cdb[7]); 4523 break; 4524 case READ_12: 4525 case WRITE_12: 4526 case VERIFY_12: /* 0xAF */ 4527 case WRITE_VERIFY_12: /* 0xAE */ 4528 block_cnt = get_unaligned_be32(&cdb[6]); 4529 break; 4530 case READ_16: 4531 case WRITE_16: 4532 case VERIFY_16: /* 0x8F */ 4533 block_cnt = get_unaligned_be32(&cdb[10]); 4534 break; 4535 default: 4536 return false; 4537 } 4538 4539 return block_cnt == 0; 4540 } 4541 4542 static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) 4543 { 4544 int is_write = 0; 4545 u32 block; 4546 u32 block_cnt; 4547 4548 /* Perform some CDB fixups if needed using 10 byte reads/writes only */ 4549 switch (cdb[0]) { 4550 case WRITE_6: 4551 case WRITE_12: 4552 is_write = 1; 4553 case READ_6: 4554 case READ_12: 4555 if (*cdb_len == 6) { 4556 block = (((cdb[1] & 0x1F) << 16) | 4557 (cdb[2] << 8) | 4558 cdb[3]); 4559 block_cnt = cdb[4]; 4560 if (block_cnt == 0) 4561 block_cnt = 256; 4562 } else { 4563 BUG_ON(*cdb_len != 12); 4564 block = get_unaligned_be32(&cdb[2]); 4565 block_cnt = get_unaligned_be32(&cdb[6]); 4566 } 4567 if (block_cnt > 0xffff) 4568 return IO_ACCEL_INELIGIBLE; 4569 4570 cdb[0] = is_write ? WRITE_10 : READ_10; 4571 cdb[1] = 0; 4572 cdb[2] = (u8) (block >> 24); 4573 cdb[3] = (u8) (block >> 16); 4574 cdb[4] = (u8) (block >> 8); 4575 cdb[5] = (u8) (block); 4576 cdb[6] = 0; 4577 cdb[7] = (u8) (block_cnt >> 8); 4578 cdb[8] = (u8) (block_cnt); 4579 cdb[9] = 0; 4580 *cdb_len = 10; 4581 break; 4582 } 4583 return 0; 4584 } 4585 4586 static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, 4587 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 4588 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4589 { 4590 struct scsi_cmnd *cmd = c->scsi_cmd; 4591 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; 4592 unsigned int len; 4593 unsigned int total_len = 0; 4594 struct scatterlist *sg; 4595 u64 addr64; 4596 int use_sg, i; 4597 struct SGDescriptor *curr_sg; 4598 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; 4599 4600 /* TODO: implement chaining support */ 4601 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { 4602 atomic_dec(&phys_disk->ioaccel_cmds_out); 4603 return IO_ACCEL_INELIGIBLE; 4604 } 4605 4606 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); 4607 4608 if (is_zero_length_transfer(cdb)) { 4609 warn_zero_length_transfer(h, cdb, cdb_len, __func__); 4610 atomic_dec(&phys_disk->ioaccel_cmds_out); 4611 return IO_ACCEL_INELIGIBLE; 4612 } 4613 4614 if (fixup_ioaccel_cdb(cdb, &cdb_len)) { 4615 atomic_dec(&phys_disk->ioaccel_cmds_out); 4616 return IO_ACCEL_INELIGIBLE; 4617 } 4618 4619 c->cmd_type = CMD_IOACCEL1; 4620 4621 /* Adjust the DMA address to point to the accelerated command buffer */ 4622 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + 4623 (c->cmdindex * sizeof(*cp)); 4624 BUG_ON(c->busaddr & 0x0000007F); 4625 4626 use_sg = scsi_dma_map(cmd); 4627 if (use_sg < 0) { 4628 atomic_dec(&phys_disk->ioaccel_cmds_out); 4629 return use_sg; 4630 } 4631 4632 if (use_sg) { 4633 curr_sg = cp->SG; 4634 scsi_for_each_sg(cmd, sg, use_sg, i) { 4635 addr64 = (u64) sg_dma_address(sg); 4636 len = sg_dma_len(sg); 4637 total_len += len; 4638 curr_sg->Addr = cpu_to_le64(addr64); 4639 curr_sg->Len = cpu_to_le32(len); 4640 curr_sg->Ext = cpu_to_le32(0); 4641 curr_sg++; 4642 } 4643 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); 4644 4645 switch (cmd->sc_data_direction) { 4646 case DMA_TO_DEVICE: 4647 control |= IOACCEL1_CONTROL_DATA_OUT; 4648 break; 4649 case DMA_FROM_DEVICE: 4650 control |= IOACCEL1_CONTROL_DATA_IN; 4651 break; 4652 case DMA_NONE: 4653 control |= IOACCEL1_CONTROL_NODATAXFER; 4654 break; 4655 default: 4656 dev_err(&h->pdev->dev, "unknown data direction: %d\n", 4657 cmd->sc_data_direction); 4658 BUG(); 4659 break; 4660 } 4661 } else { 4662 control |= IOACCEL1_CONTROL_NODATAXFER; 4663 } 4664 4665 c->Header.SGList = use_sg; 4666 /* Fill out the command structure to submit */ 4667 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); 4668 cp->transfer_len = cpu_to_le32(total_len); 4669 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | 4670 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); 4671 cp->control = cpu_to_le32(control); 4672 memcpy(cp->CDB, cdb, cdb_len); 4673 memcpy(cp->CISS_LUN, scsi3addr, 8); 4674 /* Tag was already set at init time. */ 4675 enqueue_cmd_and_start_io(h, c); 4676 return 0; 4677 } 4678 4679 /* 4680 * Queue a command directly to a device behind the controller using the 4681 * I/O accelerator path. 4682 */ 4683 static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, 4684 struct CommandList *c) 4685 { 4686 struct scsi_cmnd *cmd = c->scsi_cmd; 4687 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4688 4689 if (!dev) 4690 return -1; 4691 4692 c->phys_disk = dev; 4693 4694 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, 4695 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); 4696 } 4697 4698 /* 4699 * Set encryption parameters for the ioaccel2 request 4700 */ 4701 static void set_encrypt_ioaccel2(struct ctlr_info *h, 4702 struct CommandList *c, struct io_accel2_cmd *cp) 4703 { 4704 struct scsi_cmnd *cmd = c->scsi_cmd; 4705 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4706 struct raid_map_data *map = &dev->raid_map; 4707 u64 first_block; 4708 4709 /* Are we doing encryption on this device */ 4710 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) 4711 return; 4712 /* Set the data encryption key index. */ 4713 cp->dekindex = map->dekindex; 4714 4715 /* Set the encryption enable flag, encoded into direction field. */ 4716 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; 4717 4718 /* Set encryption tweak values based on logical block address 4719 * If block size is 512, tweak value is LBA. 4720 * For other block sizes, tweak is (LBA * block size)/ 512) 4721 */ 4722 switch (cmd->cmnd[0]) { 4723 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ 4724 case READ_6: 4725 case WRITE_6: 4726 first_block = (((cmd->cmnd[1] & 0x1F) << 16) | 4727 (cmd->cmnd[2] << 8) | 4728 cmd->cmnd[3]); 4729 break; 4730 case WRITE_10: 4731 case READ_10: 4732 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ 4733 case WRITE_12: 4734 case READ_12: 4735 first_block = get_unaligned_be32(&cmd->cmnd[2]); 4736 break; 4737 case WRITE_16: 4738 case READ_16: 4739 first_block = get_unaligned_be64(&cmd->cmnd[2]); 4740 break; 4741 default: 4742 dev_err(&h->pdev->dev, 4743 "ERROR: %s: size (0x%x) not supported for encryption\n", 4744 __func__, cmd->cmnd[0]); 4745 BUG(); 4746 break; 4747 } 4748 4749 if (le32_to_cpu(map->volume_blk_size) != 512) 4750 first_block = first_block * 4751 le32_to_cpu(map->volume_blk_size)/512; 4752 4753 cp->tweak_lower = cpu_to_le32(first_block); 4754 cp->tweak_upper = cpu_to_le32(first_block >> 32); 4755 } 4756 4757 static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, 4758 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 4759 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4760 { 4761 struct scsi_cmnd *cmd = c->scsi_cmd; 4762 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; 4763 struct ioaccel2_sg_element *curr_sg; 4764 int use_sg, i; 4765 struct scatterlist *sg; 4766 u64 addr64; 4767 u32 len; 4768 u32 total_len = 0; 4769 4770 if (!cmd->device) 4771 return -1; 4772 4773 if (!cmd->device->hostdata) 4774 return -1; 4775 4776 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); 4777 4778 if (is_zero_length_transfer(cdb)) { 4779 warn_zero_length_transfer(h, cdb, cdb_len, __func__); 4780 atomic_dec(&phys_disk->ioaccel_cmds_out); 4781 return IO_ACCEL_INELIGIBLE; 4782 } 4783 4784 if (fixup_ioaccel_cdb(cdb, &cdb_len)) { 4785 atomic_dec(&phys_disk->ioaccel_cmds_out); 4786 return IO_ACCEL_INELIGIBLE; 4787 } 4788 4789 c->cmd_type = CMD_IOACCEL2; 4790 /* Adjust the DMA address to point to the accelerated command buffer */ 4791 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + 4792 (c->cmdindex * sizeof(*cp)); 4793 BUG_ON(c->busaddr & 0x0000007F); 4794 4795 memset(cp, 0, sizeof(*cp)); 4796 cp->IU_type = IOACCEL2_IU_TYPE; 4797 4798 use_sg = scsi_dma_map(cmd); 4799 if (use_sg < 0) { 4800 atomic_dec(&phys_disk->ioaccel_cmds_out); 4801 return use_sg; 4802 } 4803 4804 if (use_sg) { 4805 curr_sg = cp->sg; 4806 if (use_sg > h->ioaccel_maxsg) { 4807 addr64 = le64_to_cpu( 4808 h->ioaccel2_cmd_sg_list[c->cmdindex]->address); 4809 curr_sg->address = cpu_to_le64(addr64); 4810 curr_sg->length = 0; 4811 curr_sg->reserved[0] = 0; 4812 curr_sg->reserved[1] = 0; 4813 curr_sg->reserved[2] = 0; 4814 curr_sg->chain_indicator = 0x80; 4815 4816 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex]; 4817 } 4818 scsi_for_each_sg(cmd, sg, use_sg, i) { 4819 addr64 = (u64) sg_dma_address(sg); 4820 len = sg_dma_len(sg); 4821 total_len += len; 4822 curr_sg->address = cpu_to_le64(addr64); 4823 curr_sg->length = cpu_to_le32(len); 4824 curr_sg->reserved[0] = 0; 4825 curr_sg->reserved[1] = 0; 4826 curr_sg->reserved[2] = 0; 4827 curr_sg->chain_indicator = 0; 4828 curr_sg++; 4829 } 4830 4831 switch (cmd->sc_data_direction) { 4832 case DMA_TO_DEVICE: 4833 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4834 cp->direction |= IOACCEL2_DIR_DATA_OUT; 4835 break; 4836 case DMA_FROM_DEVICE: 4837 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4838 cp->direction |= IOACCEL2_DIR_DATA_IN; 4839 break; 4840 case DMA_NONE: 4841 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4842 cp->direction |= IOACCEL2_DIR_NO_DATA; 4843 break; 4844 default: 4845 dev_err(&h->pdev->dev, "unknown data direction: %d\n", 4846 cmd->sc_data_direction); 4847 BUG(); 4848 break; 4849 } 4850 } else { 4851 cp->direction &= ~IOACCEL2_DIRECTION_MASK; 4852 cp->direction |= IOACCEL2_DIR_NO_DATA; 4853 } 4854 4855 /* Set encryption parameters, if necessary */ 4856 set_encrypt_ioaccel2(h, c, cp); 4857 4858 cp->scsi_nexus = cpu_to_le32(ioaccel_handle); 4859 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); 4860 memcpy(cp->cdb, cdb, sizeof(cp->cdb)); 4861 4862 cp->data_len = cpu_to_le32(total_len); 4863 cp->err_ptr = cpu_to_le64(c->busaddr + 4864 offsetof(struct io_accel2_cmd, error_data)); 4865 cp->err_len = cpu_to_le32(sizeof(cp->error_data)); 4866 4867 /* fill in sg elements */ 4868 if (use_sg > h->ioaccel_maxsg) { 4869 cp->sg_count = 1; 4870 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0])); 4871 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) { 4872 atomic_dec(&phys_disk->ioaccel_cmds_out); 4873 scsi_dma_unmap(cmd); 4874 return -1; 4875 } 4876 } else 4877 cp->sg_count = (u8) use_sg; 4878 4879 enqueue_cmd_and_start_io(h, c); 4880 return 0; 4881 } 4882 4883 /* 4884 * Queue a command to the correct I/O accelerator path. 4885 */ 4886 static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, 4887 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, 4888 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) 4889 { 4890 if (!c->scsi_cmd->device) 4891 return -1; 4892 4893 if (!c->scsi_cmd->device->hostdata) 4894 return -1; 4895 4896 /* Try to honor the device's queue depth */ 4897 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > 4898 phys_disk->queue_depth) { 4899 atomic_dec(&phys_disk->ioaccel_cmds_out); 4900 return IO_ACCEL_INELIGIBLE; 4901 } 4902 if (h->transMethod & CFGTBL_Trans_io_accel1) 4903 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, 4904 cdb, cdb_len, scsi3addr, 4905 phys_disk); 4906 else 4907 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, 4908 cdb, cdb_len, scsi3addr, 4909 phys_disk); 4910 } 4911 4912 static void raid_map_helper(struct raid_map_data *map, 4913 int offload_to_mirror, u32 *map_index, u32 *current_group) 4914 { 4915 if (offload_to_mirror == 0) { 4916 /* use physical disk in the first mirrored group. */ 4917 *map_index %= le16_to_cpu(map->data_disks_per_row); 4918 return; 4919 } 4920 do { 4921 /* determine mirror group that *map_index indicates */ 4922 *current_group = *map_index / 4923 le16_to_cpu(map->data_disks_per_row); 4924 if (offload_to_mirror == *current_group) 4925 continue; 4926 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { 4927 /* select map index from next group */ 4928 *map_index += le16_to_cpu(map->data_disks_per_row); 4929 (*current_group)++; 4930 } else { 4931 /* select map index from first group */ 4932 *map_index %= le16_to_cpu(map->data_disks_per_row); 4933 *current_group = 0; 4934 } 4935 } while (offload_to_mirror != *current_group); 4936 } 4937 4938 /* 4939 * Attempt to perform offload RAID mapping for a logical volume I/O. 4940 */ 4941 static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, 4942 struct CommandList *c) 4943 { 4944 struct scsi_cmnd *cmd = c->scsi_cmd; 4945 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 4946 struct raid_map_data *map = &dev->raid_map; 4947 struct raid_map_disk_data *dd = &map->data[0]; 4948 int is_write = 0; 4949 u32 map_index; 4950 u64 first_block, last_block; 4951 u32 block_cnt; 4952 u32 blocks_per_row; 4953 u64 first_row, last_row; 4954 u32 first_row_offset, last_row_offset; 4955 u32 first_column, last_column; 4956 u64 r0_first_row, r0_last_row; 4957 u32 r5or6_blocks_per_row; 4958 u64 r5or6_first_row, r5or6_last_row; 4959 u32 r5or6_first_row_offset, r5or6_last_row_offset; 4960 u32 r5or6_first_column, r5or6_last_column; 4961 u32 total_disks_per_row; 4962 u32 stripesize; 4963 u32 first_group, last_group, current_group; 4964 u32 map_row; 4965 u32 disk_handle; 4966 u64 disk_block; 4967 u32 disk_block_cnt; 4968 u8 cdb[16]; 4969 u8 cdb_len; 4970 u16 strip_size; 4971 #if BITS_PER_LONG == 32 4972 u64 tmpdiv; 4973 #endif 4974 int offload_to_mirror; 4975 4976 if (!dev) 4977 return -1; 4978 4979 /* check for valid opcode, get LBA and block count */ 4980 switch (cmd->cmnd[0]) { 4981 case WRITE_6: 4982 is_write = 1; 4983 case READ_6: 4984 first_block = (((cmd->cmnd[1] & 0x1F) << 16) | 4985 (cmd->cmnd[2] << 8) | 4986 cmd->cmnd[3]); 4987 block_cnt = cmd->cmnd[4]; 4988 if (block_cnt == 0) 4989 block_cnt = 256; 4990 break; 4991 case WRITE_10: 4992 is_write = 1; 4993 case READ_10: 4994 first_block = 4995 (((u64) cmd->cmnd[2]) << 24) | 4996 (((u64) cmd->cmnd[3]) << 16) | 4997 (((u64) cmd->cmnd[4]) << 8) | 4998 cmd->cmnd[5]; 4999 block_cnt = 5000 (((u32) cmd->cmnd[7]) << 8) | 5001 cmd->cmnd[8]; 5002 break; 5003 case WRITE_12: 5004 is_write = 1; 5005 case READ_12: 5006 first_block = 5007 (((u64) cmd->cmnd[2]) << 24) | 5008 (((u64) cmd->cmnd[3]) << 16) | 5009 (((u64) cmd->cmnd[4]) << 8) | 5010 cmd->cmnd[5]; 5011 block_cnt = 5012 (((u32) cmd->cmnd[6]) << 24) | 5013 (((u32) cmd->cmnd[7]) << 16) | 5014 (((u32) cmd->cmnd[8]) << 8) | 5015 cmd->cmnd[9]; 5016 break; 5017 case WRITE_16: 5018 is_write = 1; 5019 case READ_16: 5020 first_block = 5021 (((u64) cmd->cmnd[2]) << 56) | 5022 (((u64) cmd->cmnd[3]) << 48) | 5023 (((u64) cmd->cmnd[4]) << 40) | 5024 (((u64) cmd->cmnd[5]) << 32) | 5025 (((u64) cmd->cmnd[6]) << 24) | 5026 (((u64) cmd->cmnd[7]) << 16) | 5027 (((u64) cmd->cmnd[8]) << 8) | 5028 cmd->cmnd[9]; 5029 block_cnt = 5030 (((u32) cmd->cmnd[10]) << 24) | 5031 (((u32) cmd->cmnd[11]) << 16) | 5032 (((u32) cmd->cmnd[12]) << 8) | 5033 cmd->cmnd[13]; 5034 break; 5035 default: 5036 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ 5037 } 5038 last_block = first_block + block_cnt - 1; 5039 5040 /* check for write to non-RAID-0 */ 5041 if (is_write && dev->raid_level != 0) 5042 return IO_ACCEL_INELIGIBLE; 5043 5044 /* check for invalid block or wraparound */ 5045 if (last_block >= le64_to_cpu(map->volume_blk_cnt) || 5046 last_block < first_block) 5047 return IO_ACCEL_INELIGIBLE; 5048 5049 /* calculate stripe information for the request */ 5050 blocks_per_row = le16_to_cpu(map->data_disks_per_row) * 5051 le16_to_cpu(map->strip_size); 5052 strip_size = le16_to_cpu(map->strip_size); 5053 #if BITS_PER_LONG == 32 5054 tmpdiv = first_block; 5055 (void) do_div(tmpdiv, blocks_per_row); 5056 first_row = tmpdiv; 5057 tmpdiv = last_block; 5058 (void) do_div(tmpdiv, blocks_per_row); 5059 last_row = tmpdiv; 5060 first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); 5061 last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); 5062 tmpdiv = first_row_offset; 5063 (void) do_div(tmpdiv, strip_size); 5064 first_column = tmpdiv; 5065 tmpdiv = last_row_offset; 5066 (void) do_div(tmpdiv, strip_size); 5067 last_column = tmpdiv; 5068 #else 5069 first_row = first_block / blocks_per_row; 5070 last_row = last_block / blocks_per_row; 5071 first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); 5072 last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); 5073 first_column = first_row_offset / strip_size; 5074 last_column = last_row_offset / strip_size; 5075 #endif 5076 5077 /* if this isn't a single row/column then give to the controller */ 5078 if ((first_row != last_row) || (first_column != last_column)) 5079 return IO_ACCEL_INELIGIBLE; 5080 5081 /* proceeding with driver mapping */ 5082 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + 5083 le16_to_cpu(map->metadata_disks_per_row); 5084 map_row = ((u32)(first_row >> map->parity_rotation_shift)) % 5085 le16_to_cpu(map->row_cnt); 5086 map_index = (map_row * total_disks_per_row) + first_column; 5087 5088 switch (dev->raid_level) { 5089 case HPSA_RAID_0: 5090 break; /* nothing special to do */ 5091 case HPSA_RAID_1: 5092 /* Handles load balance across RAID 1 members. 5093 * (2-drive R1 and R10 with even # of drives.) 5094 * Appropriate for SSDs, not optimal for HDDs 5095 */ 5096 BUG_ON(le16_to_cpu(map->layout_map_count) != 2); 5097 if (dev->offload_to_mirror) 5098 map_index += le16_to_cpu(map->data_disks_per_row); 5099 dev->offload_to_mirror = !dev->offload_to_mirror; 5100 break; 5101 case HPSA_RAID_ADM: 5102 /* Handles N-way mirrors (R1-ADM) 5103 * and R10 with # of drives divisible by 3.) 5104 */ 5105 BUG_ON(le16_to_cpu(map->layout_map_count) != 3); 5106 5107 offload_to_mirror = dev->offload_to_mirror; 5108 raid_map_helper(map, offload_to_mirror, 5109 &map_index, ¤t_group); 5110 /* set mirror group to use next time */ 5111 offload_to_mirror = 5112 (offload_to_mirror >= 5113 le16_to_cpu(map->layout_map_count) - 1) 5114 ? 0 : offload_to_mirror + 1; 5115 dev->offload_to_mirror = offload_to_mirror; 5116 /* Avoid direct use of dev->offload_to_mirror within this 5117 * function since multiple threads might simultaneously 5118 * increment it beyond the range of dev->layout_map_count -1. 5119 */ 5120 break; 5121 case HPSA_RAID_5: 5122 case HPSA_RAID_6: 5123 if (le16_to_cpu(map->layout_map_count) <= 1) 5124 break; 5125 5126 /* Verify first and last block are in same RAID group */ 5127 r5or6_blocks_per_row = 5128 le16_to_cpu(map->strip_size) * 5129 le16_to_cpu(map->data_disks_per_row); 5130 BUG_ON(r5or6_blocks_per_row == 0); 5131 stripesize = r5or6_blocks_per_row * 5132 le16_to_cpu(map->layout_map_count); 5133 #if BITS_PER_LONG == 32 5134 tmpdiv = first_block; 5135 first_group = do_div(tmpdiv, stripesize); 5136 tmpdiv = first_group; 5137 (void) do_div(tmpdiv, r5or6_blocks_per_row); 5138 first_group = tmpdiv; 5139 tmpdiv = last_block; 5140 last_group = do_div(tmpdiv, stripesize); 5141 tmpdiv = last_group; 5142 (void) do_div(tmpdiv, r5or6_blocks_per_row); 5143 last_group = tmpdiv; 5144 #else 5145 first_group = (first_block % stripesize) / r5or6_blocks_per_row; 5146 last_group = (last_block % stripesize) / r5or6_blocks_per_row; 5147 #endif 5148 if (first_group != last_group) 5149 return IO_ACCEL_INELIGIBLE; 5150 5151 /* Verify request is in a single row of RAID 5/6 */ 5152 #if BITS_PER_LONG == 32 5153 tmpdiv = first_block; 5154 (void) do_div(tmpdiv, stripesize); 5155 first_row = r5or6_first_row = r0_first_row = tmpdiv; 5156 tmpdiv = last_block; 5157 (void) do_div(tmpdiv, stripesize); 5158 r5or6_last_row = r0_last_row = tmpdiv; 5159 #else 5160 first_row = r5or6_first_row = r0_first_row = 5161 first_block / stripesize; 5162 r5or6_last_row = r0_last_row = last_block / stripesize; 5163 #endif 5164 if (r5or6_first_row != r5or6_last_row) 5165 return IO_ACCEL_INELIGIBLE; 5166 5167 5168 /* Verify request is in a single column */ 5169 #if BITS_PER_LONG == 32 5170 tmpdiv = first_block; 5171 first_row_offset = do_div(tmpdiv, stripesize); 5172 tmpdiv = first_row_offset; 5173 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); 5174 r5or6_first_row_offset = first_row_offset; 5175 tmpdiv = last_block; 5176 r5or6_last_row_offset = do_div(tmpdiv, stripesize); 5177 tmpdiv = r5or6_last_row_offset; 5178 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); 5179 tmpdiv = r5or6_first_row_offset; 5180 (void) do_div(tmpdiv, map->strip_size); 5181 first_column = r5or6_first_column = tmpdiv; 5182 tmpdiv = r5or6_last_row_offset; 5183 (void) do_div(tmpdiv, map->strip_size); 5184 r5or6_last_column = tmpdiv; 5185 #else 5186 first_row_offset = r5or6_first_row_offset = 5187 (u32)((first_block % stripesize) % 5188 r5or6_blocks_per_row); 5189 5190 r5or6_last_row_offset = 5191 (u32)((last_block % stripesize) % 5192 r5or6_blocks_per_row); 5193 5194 first_column = r5or6_first_column = 5195 r5or6_first_row_offset / le16_to_cpu(map->strip_size); 5196 r5or6_last_column = 5197 r5or6_last_row_offset / le16_to_cpu(map->strip_size); 5198 #endif 5199 if (r5or6_first_column != r5or6_last_column) 5200 return IO_ACCEL_INELIGIBLE; 5201 5202 /* Request is eligible */ 5203 map_row = ((u32)(first_row >> map->parity_rotation_shift)) % 5204 le16_to_cpu(map->row_cnt); 5205 5206 map_index = (first_group * 5207 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + 5208 (map_row * total_disks_per_row) + first_column; 5209 break; 5210 default: 5211 return IO_ACCEL_INELIGIBLE; 5212 } 5213 5214 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) 5215 return IO_ACCEL_INELIGIBLE; 5216 5217 c->phys_disk = dev->phys_disk[map_index]; 5218 if (!c->phys_disk) 5219 return IO_ACCEL_INELIGIBLE; 5220 5221 disk_handle = dd[map_index].ioaccel_handle; 5222 disk_block = le64_to_cpu(map->disk_starting_blk) + 5223 first_row * le16_to_cpu(map->strip_size) + 5224 (first_row_offset - first_column * 5225 le16_to_cpu(map->strip_size)); 5226 disk_block_cnt = block_cnt; 5227 5228 /* handle differing logical/physical block sizes */ 5229 if (map->phys_blk_shift) { 5230 disk_block <<= map->phys_blk_shift; 5231 disk_block_cnt <<= map->phys_blk_shift; 5232 } 5233 BUG_ON(disk_block_cnt > 0xffff); 5234 5235 /* build the new CDB for the physical disk I/O */ 5236 if (disk_block > 0xffffffff) { 5237 cdb[0] = is_write ? WRITE_16 : READ_16; 5238 cdb[1] = 0; 5239 cdb[2] = (u8) (disk_block >> 56); 5240 cdb[3] = (u8) (disk_block >> 48); 5241 cdb[4] = (u8) (disk_block >> 40); 5242 cdb[5] = (u8) (disk_block >> 32); 5243 cdb[6] = (u8) (disk_block >> 24); 5244 cdb[7] = (u8) (disk_block >> 16); 5245 cdb[8] = (u8) (disk_block >> 8); 5246 cdb[9] = (u8) (disk_block); 5247 cdb[10] = (u8) (disk_block_cnt >> 24); 5248 cdb[11] = (u8) (disk_block_cnt >> 16); 5249 cdb[12] = (u8) (disk_block_cnt >> 8); 5250 cdb[13] = (u8) (disk_block_cnt); 5251 cdb[14] = 0; 5252 cdb[15] = 0; 5253 cdb_len = 16; 5254 } else { 5255 cdb[0] = is_write ? WRITE_10 : READ_10; 5256 cdb[1] = 0; 5257 cdb[2] = (u8) (disk_block >> 24); 5258 cdb[3] = (u8) (disk_block >> 16); 5259 cdb[4] = (u8) (disk_block >> 8); 5260 cdb[5] = (u8) (disk_block); 5261 cdb[6] = 0; 5262 cdb[7] = (u8) (disk_block_cnt >> 8); 5263 cdb[8] = (u8) (disk_block_cnt); 5264 cdb[9] = 0; 5265 cdb_len = 10; 5266 } 5267 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, 5268 dev->scsi3addr, 5269 dev->phys_disk[map_index]); 5270 } 5271 5272 /* 5273 * Submit commands down the "normal" RAID stack path 5274 * All callers to hpsa_ciss_submit must check lockup_detected 5275 * beforehand, before (opt.) and after calling cmd_alloc 5276 */ 5277 static int hpsa_ciss_submit(struct ctlr_info *h, 5278 struct CommandList *c, struct scsi_cmnd *cmd, 5279 unsigned char scsi3addr[]) 5280 { 5281 cmd->host_scribble = (unsigned char *) c; 5282 c->cmd_type = CMD_SCSI; 5283 c->scsi_cmd = cmd; 5284 c->Header.ReplyQueue = 0; /* unused in simple mode */ 5285 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); 5286 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); 5287 5288 /* Fill in the request block... */ 5289 5290 c->Request.Timeout = 0; 5291 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); 5292 c->Request.CDBLen = cmd->cmd_len; 5293 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); 5294 switch (cmd->sc_data_direction) { 5295 case DMA_TO_DEVICE: 5296 c->Request.type_attr_dir = 5297 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); 5298 break; 5299 case DMA_FROM_DEVICE: 5300 c->Request.type_attr_dir = 5301 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); 5302 break; 5303 case DMA_NONE: 5304 c->Request.type_attr_dir = 5305 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); 5306 break; 5307 case DMA_BIDIRECTIONAL: 5308 /* This can happen if a buggy application does a scsi passthru 5309 * and sets both inlen and outlen to non-zero. ( see 5310 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) 5311 */ 5312 5313 c->Request.type_attr_dir = 5314 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); 5315 /* This is technically wrong, and hpsa controllers should 5316 * reject it with CMD_INVALID, which is the most correct 5317 * response, but non-fibre backends appear to let it 5318 * slide by, and give the same results as if this field 5319 * were set correctly. Either way is acceptable for 5320 * our purposes here. 5321 */ 5322 5323 break; 5324 5325 default: 5326 dev_err(&h->pdev->dev, "unknown data direction: %d\n", 5327 cmd->sc_data_direction); 5328 BUG(); 5329 break; 5330 } 5331 5332 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ 5333 hpsa_cmd_resolve_and_free(h, c); 5334 return SCSI_MLQUEUE_HOST_BUSY; 5335 } 5336 enqueue_cmd_and_start_io(h, c); 5337 /* the cmd'll come back via intr handler in complete_scsi_command() */ 5338 return 0; 5339 } 5340 5341 static void hpsa_cmd_init(struct ctlr_info *h, int index, 5342 struct CommandList *c) 5343 { 5344 dma_addr_t cmd_dma_handle, err_dma_handle; 5345 5346 /* Zero out all of commandlist except the last field, refcount */ 5347 memset(c, 0, offsetof(struct CommandList, refcount)); 5348 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT)); 5349 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); 5350 c->err_info = h->errinfo_pool + index; 5351 memset(c->err_info, 0, sizeof(*c->err_info)); 5352 err_dma_handle = h->errinfo_pool_dhandle 5353 + index * sizeof(*c->err_info); 5354 c->cmdindex = index; 5355 c->busaddr = (u32) cmd_dma_handle; 5356 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); 5357 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); 5358 c->h = h; 5359 c->scsi_cmd = SCSI_CMD_IDLE; 5360 } 5361 5362 static void hpsa_preinitialize_commands(struct ctlr_info *h) 5363 { 5364 int i; 5365 5366 for (i = 0; i < h->nr_cmds; i++) { 5367 struct CommandList *c = h->cmd_pool + i; 5368 5369 hpsa_cmd_init(h, i, c); 5370 atomic_set(&c->refcount, 0); 5371 } 5372 } 5373 5374 static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index, 5375 struct CommandList *c) 5376 { 5377 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); 5378 5379 BUG_ON(c->cmdindex != index); 5380 5381 memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); 5382 memset(c->err_info, 0, sizeof(*c->err_info)); 5383 c->busaddr = (u32) cmd_dma_handle; 5384 } 5385 5386 static int hpsa_ioaccel_submit(struct ctlr_info *h, 5387 struct CommandList *c, struct scsi_cmnd *cmd, 5388 unsigned char *scsi3addr) 5389 { 5390 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; 5391 int rc = IO_ACCEL_INELIGIBLE; 5392 5393 if (!dev) 5394 return SCSI_MLQUEUE_HOST_BUSY; 5395 5396 cmd->host_scribble = (unsigned char *) c; 5397 5398 if (dev->offload_enabled) { 5399 hpsa_cmd_init(h, c->cmdindex, c); 5400 c->cmd_type = CMD_SCSI; 5401 c->scsi_cmd = cmd; 5402 rc = hpsa_scsi_ioaccel_raid_map(h, c); 5403 if (rc < 0) /* scsi_dma_map failed. */ 5404 rc = SCSI_MLQUEUE_HOST_BUSY; 5405 } else if (dev->hba_ioaccel_enabled) { 5406 hpsa_cmd_init(h, c->cmdindex, c); 5407 c->cmd_type = CMD_SCSI; 5408 c->scsi_cmd = cmd; 5409 rc = hpsa_scsi_ioaccel_direct_map(h, c); 5410 if (rc < 0) /* scsi_dma_map failed. */ 5411 rc = SCSI_MLQUEUE_HOST_BUSY; 5412 } 5413 return rc; 5414 } 5415 5416 static void hpsa_command_resubmit_worker(struct work_struct *work) 5417 { 5418 struct scsi_cmnd *cmd; 5419 struct hpsa_scsi_dev_t *dev; 5420 struct CommandList *c = container_of(work, struct CommandList, work); 5421 5422 cmd = c->scsi_cmd; 5423 dev = cmd->device->hostdata; 5424 if (!dev) { 5425 cmd->result = DID_NO_CONNECT << 16; 5426 return hpsa_cmd_free_and_done(c->h, c, cmd); 5427 } 5428 if (c->reset_pending) 5429 return hpsa_cmd_free_and_done(c->h, c, cmd); 5430 if (c->cmd_type == CMD_IOACCEL2) { 5431 struct ctlr_info *h = c->h; 5432 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; 5433 int rc; 5434 5435 if (c2->error_data.serv_response == 5436 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) { 5437 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr); 5438 if (rc == 0) 5439 return; 5440 if (rc == SCSI_MLQUEUE_HOST_BUSY) { 5441 /* 5442 * If we get here, it means dma mapping failed. 5443 * Try again via scsi mid layer, which will 5444 * then get SCSI_MLQUEUE_HOST_BUSY. 5445 */ 5446 cmd->result = DID_IMM_RETRY << 16; 5447 return hpsa_cmd_free_and_done(h, c, cmd); 5448 } 5449 /* else, fall thru and resubmit down CISS path */ 5450 } 5451 } 5452 hpsa_cmd_partial_init(c->h, c->cmdindex, c); 5453 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) { 5454 /* 5455 * If we get here, it means dma mapping failed. Try 5456 * again via scsi mid layer, which will then get 5457 * SCSI_MLQUEUE_HOST_BUSY. 5458 * 5459 * hpsa_ciss_submit will have already freed c 5460 * if it encountered a dma mapping failure. 5461 */ 5462 cmd->result = DID_IMM_RETRY << 16; 5463 cmd->scsi_done(cmd); 5464 } 5465 } 5466 5467 /* Running in struct Scsi_Host->host_lock less mode */ 5468 static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) 5469 { 5470 struct ctlr_info *h; 5471 struct hpsa_scsi_dev_t *dev; 5472 unsigned char scsi3addr[8]; 5473 struct CommandList *c; 5474 int rc = 0; 5475 5476 /* Get the ptr to our adapter structure out of cmd->host. */ 5477 h = sdev_to_hba(cmd->device); 5478 5479 BUG_ON(cmd->request->tag < 0); 5480 5481 dev = cmd->device->hostdata; 5482 if (!dev) { 5483 cmd->result = DID_NO_CONNECT << 16; 5484 cmd->scsi_done(cmd); 5485 return 0; 5486 } 5487 5488 if (dev->removed) { 5489 cmd->result = DID_NO_CONNECT << 16; 5490 cmd->scsi_done(cmd); 5491 return 0; 5492 } 5493 5494 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); 5495 5496 if (unlikely(lockup_detected(h))) { 5497 cmd->result = DID_NO_CONNECT << 16; 5498 cmd->scsi_done(cmd); 5499 return 0; 5500 } 5501 c = cmd_tagged_alloc(h, cmd); 5502 5503 /* 5504 * Call alternate submit routine for I/O accelerated commands. 5505 * Retries always go down the normal I/O path. 5506 */ 5507 if (likely(cmd->retries == 0 && 5508 !blk_rq_is_passthrough(cmd->request) && 5509 h->acciopath_status)) { 5510 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr); 5511 if (rc == 0) 5512 return 0; 5513 if (rc == SCSI_MLQUEUE_HOST_BUSY) { 5514 hpsa_cmd_resolve_and_free(h, c); 5515 return SCSI_MLQUEUE_HOST_BUSY; 5516 } 5517 } 5518 return hpsa_ciss_submit(h, c, cmd, scsi3addr); 5519 } 5520 5521 static void hpsa_scan_complete(struct ctlr_info *h) 5522 { 5523 unsigned long flags; 5524 5525 spin_lock_irqsave(&h->scan_lock, flags); 5526 h->scan_finished = 1; 5527 wake_up(&h->scan_wait_queue); 5528 spin_unlock_irqrestore(&h->scan_lock, flags); 5529 } 5530 5531 static void hpsa_scan_start(struct Scsi_Host *sh) 5532 { 5533 struct ctlr_info *h = shost_to_hba(sh); 5534 unsigned long flags; 5535 5536 /* 5537 * Don't let rescans be initiated on a controller known to be locked 5538 * up. If the controller locks up *during* a rescan, that thread is 5539 * probably hosed, but at least we can prevent new rescan threads from 5540 * piling up on a locked up controller. 5541 */ 5542 if (unlikely(lockup_detected(h))) 5543 return hpsa_scan_complete(h); 5544 5545 /* 5546 * If a scan is already waiting to run, no need to add another 5547 */ 5548 spin_lock_irqsave(&h->scan_lock, flags); 5549 if (h->scan_waiting) { 5550 spin_unlock_irqrestore(&h->scan_lock, flags); 5551 return; 5552 } 5553 5554 spin_unlock_irqrestore(&h->scan_lock, flags); 5555 5556 /* wait until any scan already in progress is finished. */ 5557 while (1) { 5558 spin_lock_irqsave(&h->scan_lock, flags); 5559 if (h->scan_finished) 5560 break; 5561 h->scan_waiting = 1; 5562 spin_unlock_irqrestore(&h->scan_lock, flags); 5563 wait_event(h->scan_wait_queue, h->scan_finished); 5564 /* Note: We don't need to worry about a race between this 5565 * thread and driver unload because the midlayer will 5566 * have incremented the reference count, so unload won't 5567 * happen if we're in here. 5568 */ 5569 } 5570 h->scan_finished = 0; /* mark scan as in progress */ 5571 h->scan_waiting = 0; 5572 spin_unlock_irqrestore(&h->scan_lock, flags); 5573 5574 if (unlikely(lockup_detected(h))) 5575 return hpsa_scan_complete(h); 5576 5577 /* 5578 * Do the scan after a reset completion 5579 */ 5580 spin_lock_irqsave(&h->reset_lock, flags); 5581 if (h->reset_in_progress) { 5582 h->drv_req_rescan = 1; 5583 spin_unlock_irqrestore(&h->reset_lock, flags); 5584 hpsa_scan_complete(h); 5585 return; 5586 } 5587 spin_unlock_irqrestore(&h->reset_lock, flags); 5588 5589 hpsa_update_scsi_devices(h); 5590 5591 hpsa_scan_complete(h); 5592 } 5593 5594 static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) 5595 { 5596 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; 5597 5598 if (!logical_drive) 5599 return -ENODEV; 5600 5601 if (qdepth < 1) 5602 qdepth = 1; 5603 else if (qdepth > logical_drive->queue_depth) 5604 qdepth = logical_drive->queue_depth; 5605 5606 return scsi_change_queue_depth(sdev, qdepth); 5607 } 5608 5609 static int hpsa_scan_finished(struct Scsi_Host *sh, 5610 unsigned long elapsed_time) 5611 { 5612 struct ctlr_info *h = shost_to_hba(sh); 5613 unsigned long flags; 5614 int finished; 5615 5616 spin_lock_irqsave(&h->scan_lock, flags); 5617 finished = h->scan_finished; 5618 spin_unlock_irqrestore(&h->scan_lock, flags); 5619 return finished; 5620 } 5621 5622 static int hpsa_scsi_host_alloc(struct ctlr_info *h) 5623 { 5624 struct Scsi_Host *sh; 5625 5626 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); 5627 if (sh == NULL) { 5628 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n"); 5629 return -ENOMEM; 5630 } 5631 5632 sh->io_port = 0; 5633 sh->n_io_port = 0; 5634 sh->this_id = -1; 5635 sh->max_channel = 3; 5636 sh->max_cmd_len = MAX_COMMAND_SIZE; 5637 sh->max_lun = HPSA_MAX_LUN; 5638 sh->max_id = HPSA_MAX_LUN; 5639 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS; 5640 sh->cmd_per_lun = sh->can_queue; 5641 sh->sg_tablesize = h->maxsgentries; 5642 sh->transportt = hpsa_sas_transport_template; 5643 sh->hostdata[0] = (unsigned long) h; 5644 sh->irq = pci_irq_vector(h->pdev, 0); 5645 sh->unique_id = sh->irq; 5646 5647 h->scsi_host = sh; 5648 return 0; 5649 } 5650 5651 static int hpsa_scsi_add_host(struct ctlr_info *h) 5652 { 5653 int rv; 5654 5655 rv = scsi_add_host(h->scsi_host, &h->pdev->dev); 5656 if (rv) { 5657 dev_err(&h->pdev->dev, "scsi_add_host failed\n"); 5658 return rv; 5659 } 5660 scsi_scan_host(h->scsi_host); 5661 return 0; 5662 } 5663 5664 /* 5665 * The block layer has already gone to the trouble of picking out a unique, 5666 * small-integer tag for this request. We use an offset from that value as 5667 * an index to select our command block. (The offset allows us to reserve the 5668 * low-numbered entries for our own uses.) 5669 */ 5670 static int hpsa_get_cmd_index(struct scsi_cmnd *scmd) 5671 { 5672 int idx = scmd->request->tag; 5673 5674 if (idx < 0) 5675 return idx; 5676 5677 /* Offset to leave space for internal cmds. */ 5678 return idx += HPSA_NRESERVED_CMDS; 5679 } 5680 5681 /* 5682 * Send a TEST_UNIT_READY command to the specified LUN using the specified 5683 * reply queue; returns zero if the unit is ready, and non-zero otherwise. 5684 */ 5685 static int hpsa_send_test_unit_ready(struct ctlr_info *h, 5686 struct CommandList *c, unsigned char lunaddr[], 5687 int reply_queue) 5688 { 5689 int rc; 5690 5691 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ 5692 (void) fill_cmd(c, TEST_UNIT_READY, h, 5693 NULL, 0, 0, lunaddr, TYPE_CMD); 5694 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT); 5695 if (rc) 5696 return rc; 5697 /* no unmap needed here because no data xfer. */ 5698 5699 /* Check if the unit is already ready. */ 5700 if (c->err_info->CommandStatus == CMD_SUCCESS) 5701 return 0; 5702 5703 /* 5704 * The first command sent after reset will receive "unit attention" to 5705 * indicate that the LUN has been reset...this is actually what we're 5706 * looking for (but, success is good too). 5707 */ 5708 if (c->err_info->CommandStatus == CMD_TARGET_STATUS && 5709 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && 5710 (c->err_info->SenseInfo[2] == NO_SENSE || 5711 c->err_info->SenseInfo[2] == UNIT_ATTENTION)) 5712 return 0; 5713 5714 return 1; 5715 } 5716 5717 /* 5718 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary; 5719 * returns zero when the unit is ready, and non-zero when giving up. 5720 */ 5721 static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h, 5722 struct CommandList *c, 5723 unsigned char lunaddr[], int reply_queue) 5724 { 5725 int rc; 5726 int count = 0; 5727 int waittime = 1; /* seconds */ 5728 5729 /* Send test unit ready until device ready, or give up. */ 5730 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) { 5731 5732 /* 5733 * Wait for a bit. do this first, because if we send 5734 * the TUR right away, the reset will just abort it. 5735 */ 5736 msleep(1000 * waittime); 5737 5738 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue); 5739 if (!rc) 5740 break; 5741 5742 /* Increase wait time with each try, up to a point. */ 5743 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) 5744 waittime *= 2; 5745 5746 dev_warn(&h->pdev->dev, 5747 "waiting %d secs for device to become ready.\n", 5748 waittime); 5749 } 5750 5751 return rc; 5752 } 5753 5754 static int wait_for_device_to_become_ready(struct ctlr_info *h, 5755 unsigned char lunaddr[], 5756 int reply_queue) 5757 { 5758 int first_queue; 5759 int last_queue; 5760 int rq; 5761 int rc = 0; 5762 struct CommandList *c; 5763 5764 c = cmd_alloc(h); 5765 5766 /* 5767 * If no specific reply queue was requested, then send the TUR 5768 * repeatedly, requesting a reply on each reply queue; otherwise execute 5769 * the loop exactly once using only the specified queue. 5770 */ 5771 if (reply_queue == DEFAULT_REPLY_QUEUE) { 5772 first_queue = 0; 5773 last_queue = h->nreply_queues - 1; 5774 } else { 5775 first_queue = reply_queue; 5776 last_queue = reply_queue; 5777 } 5778 5779 for (rq = first_queue; rq <= last_queue; rq++) { 5780 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq); 5781 if (rc) 5782 break; 5783 } 5784 5785 if (rc) 5786 dev_warn(&h->pdev->dev, "giving up on device.\n"); 5787 else 5788 dev_warn(&h->pdev->dev, "device is ready.\n"); 5789 5790 cmd_free(h, c); 5791 return rc; 5792 } 5793 5794 /* Need at least one of these error handlers to keep ../scsi/hosts.c from 5795 * complaining. Doing a host- or bus-reset can't do anything good here. 5796 */ 5797 static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) 5798 { 5799 int rc = SUCCESS; 5800 struct ctlr_info *h; 5801 struct hpsa_scsi_dev_t *dev; 5802 u8 reset_type; 5803 char msg[48]; 5804 unsigned long flags; 5805 5806 /* find the controller to which the command to be aborted was sent */ 5807 h = sdev_to_hba(scsicmd->device); 5808 if (h == NULL) /* paranoia */ 5809 return FAILED; 5810 5811 spin_lock_irqsave(&h->reset_lock, flags); 5812 h->reset_in_progress = 1; 5813 spin_unlock_irqrestore(&h->reset_lock, flags); 5814 5815 if (lockup_detected(h)) { 5816 rc = FAILED; 5817 goto return_reset_status; 5818 } 5819 5820 dev = scsicmd->device->hostdata; 5821 if (!dev) { 5822 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__); 5823 rc = FAILED; 5824 goto return_reset_status; 5825 } 5826 5827 if (dev->devtype == TYPE_ENCLOSURE) { 5828 rc = SUCCESS; 5829 goto return_reset_status; 5830 } 5831 5832 /* if controller locked up, we can guarantee command won't complete */ 5833 if (lockup_detected(h)) { 5834 snprintf(msg, sizeof(msg), 5835 "cmd %d RESET FAILED, lockup detected", 5836 hpsa_get_cmd_index(scsicmd)); 5837 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5838 rc = FAILED; 5839 goto return_reset_status; 5840 } 5841 5842 /* this reset request might be the result of a lockup; check */ 5843 if (detect_controller_lockup(h)) { 5844 snprintf(msg, sizeof(msg), 5845 "cmd %d RESET FAILED, new lockup detected", 5846 hpsa_get_cmd_index(scsicmd)); 5847 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5848 rc = FAILED; 5849 goto return_reset_status; 5850 } 5851 5852 /* Do not attempt on controller */ 5853 if (is_hba_lunid(dev->scsi3addr)) { 5854 rc = SUCCESS; 5855 goto return_reset_status; 5856 } 5857 5858 if (is_logical_dev_addr_mode(dev->scsi3addr)) 5859 reset_type = HPSA_DEVICE_RESET_MSG; 5860 else 5861 reset_type = HPSA_PHYS_TARGET_RESET; 5862 5863 sprintf(msg, "resetting %s", 5864 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical "); 5865 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5866 5867 /* send a reset to the SCSI LUN which the command was sent to */ 5868 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type, 5869 DEFAULT_REPLY_QUEUE); 5870 if (rc == 0) 5871 rc = SUCCESS; 5872 else 5873 rc = FAILED; 5874 5875 sprintf(msg, "reset %s %s", 5876 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ", 5877 rc == SUCCESS ? "completed successfully" : "failed"); 5878 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); 5879 5880 return_reset_status: 5881 spin_lock_irqsave(&h->reset_lock, flags); 5882 h->reset_in_progress = 0; 5883 spin_unlock_irqrestore(&h->reset_lock, flags); 5884 return rc; 5885 } 5886 5887 /* 5888 * For operations with an associated SCSI command, a command block is allocated 5889 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the 5890 * block request tag as an index into a table of entries. cmd_tagged_free() is 5891 * the complement, although cmd_free() may be called instead. 5892 */ 5893 static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, 5894 struct scsi_cmnd *scmd) 5895 { 5896 int idx = hpsa_get_cmd_index(scmd); 5897 struct CommandList *c = h->cmd_pool + idx; 5898 5899 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) { 5900 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n", 5901 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1); 5902 /* The index value comes from the block layer, so if it's out of 5903 * bounds, it's probably not our bug. 5904 */ 5905 BUG(); 5906 } 5907 5908 atomic_inc(&c->refcount); 5909 if (unlikely(!hpsa_is_cmd_idle(c))) { 5910 /* 5911 * We expect that the SCSI layer will hand us a unique tag 5912 * value. Thus, there should never be a collision here between 5913 * two requests...because if the selected command isn't idle 5914 * then someone is going to be very disappointed. 5915 */ 5916 dev_err(&h->pdev->dev, 5917 "tag collision (tag=%d) in cmd_tagged_alloc().\n", 5918 idx); 5919 if (c->scsi_cmd != NULL) 5920 scsi_print_command(c->scsi_cmd); 5921 scsi_print_command(scmd); 5922 } 5923 5924 hpsa_cmd_partial_init(h, idx, c); 5925 return c; 5926 } 5927 5928 static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c) 5929 { 5930 /* 5931 * Release our reference to the block. We don't need to do anything 5932 * else to free it, because it is accessed by index. 5933 */ 5934 (void)atomic_dec(&c->refcount); 5935 } 5936 5937 /* 5938 * For operations that cannot sleep, a command block is allocated at init, 5939 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track 5940 * which ones are free or in use. Lock must be held when calling this. 5941 * cmd_free() is the complement. 5942 * This function never gives up and returns NULL. If it hangs, 5943 * another thread must call cmd_free() to free some tags. 5944 */ 5945 5946 static struct CommandList *cmd_alloc(struct ctlr_info *h) 5947 { 5948 struct CommandList *c; 5949 int refcount, i; 5950 int offset = 0; 5951 5952 /* 5953 * There is some *extremely* small but non-zero chance that that 5954 * multiple threads could get in here, and one thread could 5955 * be scanning through the list of bits looking for a free 5956 * one, but the free ones are always behind him, and other 5957 * threads sneak in behind him and eat them before he can 5958 * get to them, so that while there is always a free one, a 5959 * very unlucky thread might be starved anyway, never able to 5960 * beat the other threads. In reality, this happens so 5961 * infrequently as to be indistinguishable from never. 5962 * 5963 * Note that we start allocating commands before the SCSI host structure 5964 * is initialized. Since the search starts at bit zero, this 5965 * all works, since we have at least one command structure available; 5966 * however, it means that the structures with the low indexes have to be 5967 * reserved for driver-initiated requests, while requests from the block 5968 * layer will use the higher indexes. 5969 */ 5970 5971 for (;;) { 5972 i = find_next_zero_bit(h->cmd_pool_bits, 5973 HPSA_NRESERVED_CMDS, 5974 offset); 5975 if (unlikely(i >= HPSA_NRESERVED_CMDS)) { 5976 offset = 0; 5977 continue; 5978 } 5979 c = h->cmd_pool + i; 5980 refcount = atomic_inc_return(&c->refcount); 5981 if (unlikely(refcount > 1)) { 5982 cmd_free(h, c); /* already in use */ 5983 offset = (i + 1) % HPSA_NRESERVED_CMDS; 5984 continue; 5985 } 5986 set_bit(i & (BITS_PER_LONG - 1), 5987 h->cmd_pool_bits + (i / BITS_PER_LONG)); 5988 break; /* it's ours now. */ 5989 } 5990 hpsa_cmd_partial_init(h, i, c); 5991 return c; 5992 } 5993 5994 /* 5995 * This is the complementary operation to cmd_alloc(). Note, however, in some 5996 * corner cases it may also be used to free blocks allocated by 5997 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and 5998 * the clear-bit is harmless. 5999 */ 6000 static void cmd_free(struct ctlr_info *h, struct CommandList *c) 6001 { 6002 if (atomic_dec_and_test(&c->refcount)) { 6003 int i; 6004 6005 i = c - h->cmd_pool; 6006 clear_bit(i & (BITS_PER_LONG - 1), 6007 h->cmd_pool_bits + (i / BITS_PER_LONG)); 6008 } 6009 } 6010 6011 #ifdef CONFIG_COMPAT 6012 6013 static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, 6014 void __user *arg) 6015 { 6016 IOCTL32_Command_struct __user *arg32 = 6017 (IOCTL32_Command_struct __user *) arg; 6018 IOCTL_Command_struct arg64; 6019 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); 6020 int err; 6021 u32 cp; 6022 6023 memset(&arg64, 0, sizeof(arg64)); 6024 err = 0; 6025 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, 6026 sizeof(arg64.LUN_info)); 6027 err |= copy_from_user(&arg64.Request, &arg32->Request, 6028 sizeof(arg64.Request)); 6029 err |= copy_from_user(&arg64.error_info, &arg32->error_info, 6030 sizeof(arg64.error_info)); 6031 err |= get_user(arg64.buf_size, &arg32->buf_size); 6032 err |= get_user(cp, &arg32->buf); 6033 arg64.buf = compat_ptr(cp); 6034 err |= copy_to_user(p, &arg64, sizeof(arg64)); 6035 6036 if (err) 6037 return -EFAULT; 6038 6039 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p); 6040 if (err) 6041 return err; 6042 err |= copy_in_user(&arg32->error_info, &p->error_info, 6043 sizeof(arg32->error_info)); 6044 if (err) 6045 return -EFAULT; 6046 return err; 6047 } 6048 6049 static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, 6050 int cmd, void __user *arg) 6051 { 6052 BIG_IOCTL32_Command_struct __user *arg32 = 6053 (BIG_IOCTL32_Command_struct __user *) arg; 6054 BIG_IOCTL_Command_struct arg64; 6055 BIG_IOCTL_Command_struct __user *p = 6056 compat_alloc_user_space(sizeof(arg64)); 6057 int err; 6058 u32 cp; 6059 6060 memset(&arg64, 0, sizeof(arg64)); 6061 err = 0; 6062 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, 6063 sizeof(arg64.LUN_info)); 6064 err |= copy_from_user(&arg64.Request, &arg32->Request, 6065 sizeof(arg64.Request)); 6066 err |= copy_from_user(&arg64.error_info, &arg32->error_info, 6067 sizeof(arg64.error_info)); 6068 err |= get_user(arg64.buf_size, &arg32->buf_size); 6069 err |= get_user(arg64.malloc_size, &arg32->malloc_size); 6070 err |= get_user(cp, &arg32->buf); 6071 arg64.buf = compat_ptr(cp); 6072 err |= copy_to_user(p, &arg64, sizeof(arg64)); 6073 6074 if (err) 6075 return -EFAULT; 6076 6077 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p); 6078 if (err) 6079 return err; 6080 err |= copy_in_user(&arg32->error_info, &p->error_info, 6081 sizeof(arg32->error_info)); 6082 if (err) 6083 return -EFAULT; 6084 return err; 6085 } 6086 6087 static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg) 6088 { 6089 switch (cmd) { 6090 case CCISS_GETPCIINFO: 6091 case CCISS_GETINTINFO: 6092 case CCISS_SETINTINFO: 6093 case CCISS_GETNODENAME: 6094 case CCISS_SETNODENAME: 6095 case CCISS_GETHEARTBEAT: 6096 case CCISS_GETBUSTYPES: 6097 case CCISS_GETFIRMVER: 6098 case CCISS_GETDRIVVER: 6099 case CCISS_REVALIDVOLS: 6100 case CCISS_DEREGDISK: 6101 case CCISS_REGNEWDISK: 6102 case CCISS_REGNEWD: 6103 case CCISS_RESCANDISK: 6104 case CCISS_GETLUNINFO: 6105 return hpsa_ioctl(dev, cmd, arg); 6106 6107 case CCISS_PASSTHRU32: 6108 return hpsa_ioctl32_passthru(dev, cmd, arg); 6109 case CCISS_BIG_PASSTHRU32: 6110 return hpsa_ioctl32_big_passthru(dev, cmd, arg); 6111 6112 default: 6113 return -ENOIOCTLCMD; 6114 } 6115 } 6116 #endif 6117 6118 static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) 6119 { 6120 struct hpsa_pci_info pciinfo; 6121 6122 if (!argp) 6123 return -EINVAL; 6124 pciinfo.domain = pci_domain_nr(h->pdev->bus); 6125 pciinfo.bus = h->pdev->bus->number; 6126 pciinfo.dev_fn = h->pdev->devfn; 6127 pciinfo.board_id = h->board_id; 6128 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) 6129 return -EFAULT; 6130 return 0; 6131 } 6132 6133 static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) 6134 { 6135 DriverVer_type DriverVer; 6136 unsigned char vmaj, vmin, vsubmin; 6137 int rc; 6138 6139 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", 6140 &vmaj, &vmin, &vsubmin); 6141 if (rc != 3) { 6142 dev_info(&h->pdev->dev, "driver version string '%s' " 6143 "unrecognized.", HPSA_DRIVER_VERSION); 6144 vmaj = 0; 6145 vmin = 0; 6146 vsubmin = 0; 6147 } 6148 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; 6149 if (!argp) 6150 return -EINVAL; 6151 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) 6152 return -EFAULT; 6153 return 0; 6154 } 6155 6156 static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) 6157 { 6158 IOCTL_Command_struct iocommand; 6159 struct CommandList *c; 6160 char *buff = NULL; 6161 u64 temp64; 6162 int rc = 0; 6163 6164 if (!argp) 6165 return -EINVAL; 6166 if (!capable(CAP_SYS_RAWIO)) 6167 return -EPERM; 6168 if (copy_from_user(&iocommand, argp, sizeof(iocommand))) 6169 return -EFAULT; 6170 if ((iocommand.buf_size < 1) && 6171 (iocommand.Request.Type.Direction != XFER_NONE)) { 6172 return -EINVAL; 6173 } 6174 if (iocommand.buf_size > 0) { 6175 buff = kmalloc(iocommand.buf_size, GFP_KERNEL); 6176 if (buff == NULL) 6177 return -ENOMEM; 6178 if (iocommand.Request.Type.Direction & XFER_WRITE) { 6179 /* Copy the data into the buffer we created */ 6180 if (copy_from_user(buff, iocommand.buf, 6181 iocommand.buf_size)) { 6182 rc = -EFAULT; 6183 goto out_kfree; 6184 } 6185 } else { 6186 memset(buff, 0, iocommand.buf_size); 6187 } 6188 } 6189 c = cmd_alloc(h); 6190 6191 /* Fill in the command type */ 6192 c->cmd_type = CMD_IOCTL_PEND; 6193 c->scsi_cmd = SCSI_CMD_BUSY; 6194 /* Fill in Command Header */ 6195 c->Header.ReplyQueue = 0; /* unused in simple mode */ 6196 if (iocommand.buf_size > 0) { /* buffer to fill */ 6197 c->Header.SGList = 1; 6198 c->Header.SGTotal = cpu_to_le16(1); 6199 } else { /* no buffers to fill */ 6200 c->Header.SGList = 0; 6201 c->Header.SGTotal = cpu_to_le16(0); 6202 } 6203 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); 6204 6205 /* Fill in Request block */ 6206 memcpy(&c->Request, &iocommand.Request, 6207 sizeof(c->Request)); 6208 6209 /* Fill in the scatter gather information */ 6210 if (iocommand.buf_size > 0) { 6211 temp64 = pci_map_single(h->pdev, buff, 6212 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); 6213 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { 6214 c->SG[0].Addr = cpu_to_le64(0); 6215 c->SG[0].Len = cpu_to_le32(0); 6216 rc = -ENOMEM; 6217 goto out; 6218 } 6219 c->SG[0].Addr = cpu_to_le64(temp64); 6220 c->SG[0].Len = cpu_to_le32(iocommand.buf_size); 6221 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ 6222 } 6223 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 6224 NO_TIMEOUT); 6225 if (iocommand.buf_size > 0) 6226 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); 6227 check_ioctl_unit_attention(h, c); 6228 if (rc) { 6229 rc = -EIO; 6230 goto out; 6231 } 6232 6233 /* Copy the error information out */ 6234 memcpy(&iocommand.error_info, c->err_info, 6235 sizeof(iocommand.error_info)); 6236 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { 6237 rc = -EFAULT; 6238 goto out; 6239 } 6240 if ((iocommand.Request.Type.Direction & XFER_READ) && 6241 iocommand.buf_size > 0) { 6242 /* Copy the data out of the buffer we created */ 6243 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { 6244 rc = -EFAULT; 6245 goto out; 6246 } 6247 } 6248 out: 6249 cmd_free(h, c); 6250 out_kfree: 6251 kfree(buff); 6252 return rc; 6253 } 6254 6255 static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) 6256 { 6257 BIG_IOCTL_Command_struct *ioc; 6258 struct CommandList *c; 6259 unsigned char **buff = NULL; 6260 int *buff_size = NULL; 6261 u64 temp64; 6262 BYTE sg_used = 0; 6263 int status = 0; 6264 u32 left; 6265 u32 sz; 6266 BYTE __user *data_ptr; 6267 6268 if (!argp) 6269 return -EINVAL; 6270 if (!capable(CAP_SYS_RAWIO)) 6271 return -EPERM; 6272 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL); 6273 if (!ioc) { 6274 status = -ENOMEM; 6275 goto cleanup1; 6276 } 6277 if (copy_from_user(ioc, argp, sizeof(*ioc))) { 6278 status = -EFAULT; 6279 goto cleanup1; 6280 } 6281 if ((ioc->buf_size < 1) && 6282 (ioc->Request.Type.Direction != XFER_NONE)) { 6283 status = -EINVAL; 6284 goto cleanup1; 6285 } 6286 /* Check kmalloc limits using all SGs */ 6287 if (ioc->malloc_size > MAX_KMALLOC_SIZE) { 6288 status = -EINVAL; 6289 goto cleanup1; 6290 } 6291 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { 6292 status = -EINVAL; 6293 goto cleanup1; 6294 } 6295 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); 6296 if (!buff) { 6297 status = -ENOMEM; 6298 goto cleanup1; 6299 } 6300 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); 6301 if (!buff_size) { 6302 status = -ENOMEM; 6303 goto cleanup1; 6304 } 6305 left = ioc->buf_size; 6306 data_ptr = ioc->buf; 6307 while (left) { 6308 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; 6309 buff_size[sg_used] = sz; 6310 buff[sg_used] = kmalloc(sz, GFP_KERNEL); 6311 if (buff[sg_used] == NULL) { 6312 status = -ENOMEM; 6313 goto cleanup1; 6314 } 6315 if (ioc->Request.Type.Direction & XFER_WRITE) { 6316 if (copy_from_user(buff[sg_used], data_ptr, sz)) { 6317 status = -EFAULT; 6318 goto cleanup1; 6319 } 6320 } else 6321 memset(buff[sg_used], 0, sz); 6322 left -= sz; 6323 data_ptr += sz; 6324 sg_used++; 6325 } 6326 c = cmd_alloc(h); 6327 6328 c->cmd_type = CMD_IOCTL_PEND; 6329 c->scsi_cmd = SCSI_CMD_BUSY; 6330 c->Header.ReplyQueue = 0; 6331 c->Header.SGList = (u8) sg_used; 6332 c->Header.SGTotal = cpu_to_le16(sg_used); 6333 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); 6334 memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); 6335 if (ioc->buf_size > 0) { 6336 int i; 6337 for (i = 0; i < sg_used; i++) { 6338 temp64 = pci_map_single(h->pdev, buff[i], 6339 buff_size[i], PCI_DMA_BIDIRECTIONAL); 6340 if (dma_mapping_error(&h->pdev->dev, 6341 (dma_addr_t) temp64)) { 6342 c->SG[i].Addr = cpu_to_le64(0); 6343 c->SG[i].Len = cpu_to_le32(0); 6344 hpsa_pci_unmap(h->pdev, c, i, 6345 PCI_DMA_BIDIRECTIONAL); 6346 status = -ENOMEM; 6347 goto cleanup0; 6348 } 6349 c->SG[i].Addr = cpu_to_le64(temp64); 6350 c->SG[i].Len = cpu_to_le32(buff_size[i]); 6351 c->SG[i].Ext = cpu_to_le32(0); 6352 } 6353 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); 6354 } 6355 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, 6356 NO_TIMEOUT); 6357 if (sg_used) 6358 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); 6359 check_ioctl_unit_attention(h, c); 6360 if (status) { 6361 status = -EIO; 6362 goto cleanup0; 6363 } 6364 6365 /* Copy the error information out */ 6366 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); 6367 if (copy_to_user(argp, ioc, sizeof(*ioc))) { 6368 status = -EFAULT; 6369 goto cleanup0; 6370 } 6371 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { 6372 int i; 6373 6374 /* Copy the data out of the buffer we created */ 6375 BYTE __user *ptr = ioc->buf; 6376 for (i = 0; i < sg_used; i++) { 6377 if (copy_to_user(ptr, buff[i], buff_size[i])) { 6378 status = -EFAULT; 6379 goto cleanup0; 6380 } 6381 ptr += buff_size[i]; 6382 } 6383 } 6384 status = 0; 6385 cleanup0: 6386 cmd_free(h, c); 6387 cleanup1: 6388 if (buff) { 6389 int i; 6390 6391 for (i = 0; i < sg_used; i++) 6392 kfree(buff[i]); 6393 kfree(buff); 6394 } 6395 kfree(buff_size); 6396 kfree(ioc); 6397 return status; 6398 } 6399 6400 static void check_ioctl_unit_attention(struct ctlr_info *h, 6401 struct CommandList *c) 6402 { 6403 if (c->err_info->CommandStatus == CMD_TARGET_STATUS && 6404 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) 6405 (void) check_for_unit_attention(h, c); 6406 } 6407 6408 /* 6409 * ioctl 6410 */ 6411 static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg) 6412 { 6413 struct ctlr_info *h; 6414 void __user *argp = (void __user *)arg; 6415 int rc; 6416 6417 h = sdev_to_hba(dev); 6418 6419 switch (cmd) { 6420 case CCISS_DEREGDISK: 6421 case CCISS_REGNEWDISK: 6422 case CCISS_REGNEWD: 6423 hpsa_scan_start(h->scsi_host); 6424 return 0; 6425 case CCISS_GETPCIINFO: 6426 return hpsa_getpciinfo_ioctl(h, argp); 6427 case CCISS_GETDRIVVER: 6428 return hpsa_getdrivver_ioctl(h, argp); 6429 case CCISS_PASSTHRU: 6430 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 6431 return -EAGAIN; 6432 rc = hpsa_passthru_ioctl(h, argp); 6433 atomic_inc(&h->passthru_cmds_avail); 6434 return rc; 6435 case CCISS_BIG_PASSTHRU: 6436 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) 6437 return -EAGAIN; 6438 rc = hpsa_big_passthru_ioctl(h, argp); 6439 atomic_inc(&h->passthru_cmds_avail); 6440 return rc; 6441 default: 6442 return -ENOTTY; 6443 } 6444 } 6445 6446 static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, 6447 u8 reset_type) 6448 { 6449 struct CommandList *c; 6450 6451 c = cmd_alloc(h); 6452 6453 /* fill_cmd can't fail here, no data buffer to map */ 6454 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, 6455 RAID_CTLR_LUNID, TYPE_MSG); 6456 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ 6457 c->waiting = NULL; 6458 enqueue_cmd_and_start_io(h, c); 6459 /* Don't wait for completion, the reset won't complete. Don't free 6460 * the command either. This is the last command we will send before 6461 * re-initializing everything, so it doesn't matter and won't leak. 6462 */ 6463 return; 6464 } 6465 6466 static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, 6467 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, 6468 int cmd_type) 6469 { 6470 int pci_dir = XFER_NONE; 6471 6472 c->cmd_type = CMD_IOCTL_PEND; 6473 c->scsi_cmd = SCSI_CMD_BUSY; 6474 c->Header.ReplyQueue = 0; 6475 if (buff != NULL && size > 0) { 6476 c->Header.SGList = 1; 6477 c->Header.SGTotal = cpu_to_le16(1); 6478 } else { 6479 c->Header.SGList = 0; 6480 c->Header.SGTotal = cpu_to_le16(0); 6481 } 6482 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); 6483 6484 if (cmd_type == TYPE_CMD) { 6485 switch (cmd) { 6486 case HPSA_INQUIRY: 6487 /* are we trying to read a vital product page */ 6488 if (page_code & VPD_PAGE) { 6489 c->Request.CDB[1] = 0x01; 6490 c->Request.CDB[2] = (page_code & 0xff); 6491 } 6492 c->Request.CDBLen = 6; 6493 c->Request.type_attr_dir = 6494 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6495 c->Request.Timeout = 0; 6496 c->Request.CDB[0] = HPSA_INQUIRY; 6497 c->Request.CDB[4] = size & 0xFF; 6498 break; 6499 case HPSA_REPORT_LOG: 6500 case HPSA_REPORT_PHYS: 6501 /* Talking to controller so It's a physical command 6502 mode = 00 target = 0. Nothing to write. 6503 */ 6504 c->Request.CDBLen = 12; 6505 c->Request.type_attr_dir = 6506 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6507 c->Request.Timeout = 0; 6508 c->Request.CDB[0] = cmd; 6509 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ 6510 c->Request.CDB[7] = (size >> 16) & 0xFF; 6511 c->Request.CDB[8] = (size >> 8) & 0xFF; 6512 c->Request.CDB[9] = size & 0xFF; 6513 break; 6514 case BMIC_SENSE_DIAG_OPTIONS: 6515 c->Request.CDBLen = 16; 6516 c->Request.type_attr_dir = 6517 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6518 c->Request.Timeout = 0; 6519 /* Spec says this should be BMIC_WRITE */ 6520 c->Request.CDB[0] = BMIC_READ; 6521 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS; 6522 break; 6523 case BMIC_SET_DIAG_OPTIONS: 6524 c->Request.CDBLen = 16; 6525 c->Request.type_attr_dir = 6526 TYPE_ATTR_DIR(cmd_type, 6527 ATTR_SIMPLE, XFER_WRITE); 6528 c->Request.Timeout = 0; 6529 c->Request.CDB[0] = BMIC_WRITE; 6530 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS; 6531 break; 6532 case HPSA_CACHE_FLUSH: 6533 c->Request.CDBLen = 12; 6534 c->Request.type_attr_dir = 6535 TYPE_ATTR_DIR(cmd_type, 6536 ATTR_SIMPLE, XFER_WRITE); 6537 c->Request.Timeout = 0; 6538 c->Request.CDB[0] = BMIC_WRITE; 6539 c->Request.CDB[6] = BMIC_CACHE_FLUSH; 6540 c->Request.CDB[7] = (size >> 8) & 0xFF; 6541 c->Request.CDB[8] = size & 0xFF; 6542 break; 6543 case TEST_UNIT_READY: 6544 c->Request.CDBLen = 6; 6545 c->Request.type_attr_dir = 6546 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6547 c->Request.Timeout = 0; 6548 break; 6549 case HPSA_GET_RAID_MAP: 6550 c->Request.CDBLen = 12; 6551 c->Request.type_attr_dir = 6552 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6553 c->Request.Timeout = 0; 6554 c->Request.CDB[0] = HPSA_CISS_READ; 6555 c->Request.CDB[1] = cmd; 6556 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ 6557 c->Request.CDB[7] = (size >> 16) & 0xFF; 6558 c->Request.CDB[8] = (size >> 8) & 0xFF; 6559 c->Request.CDB[9] = size & 0xFF; 6560 break; 6561 case BMIC_SENSE_CONTROLLER_PARAMETERS: 6562 c->Request.CDBLen = 10; 6563 c->Request.type_attr_dir = 6564 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6565 c->Request.Timeout = 0; 6566 c->Request.CDB[0] = BMIC_READ; 6567 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; 6568 c->Request.CDB[7] = (size >> 16) & 0xFF; 6569 c->Request.CDB[8] = (size >> 8) & 0xFF; 6570 break; 6571 case BMIC_IDENTIFY_PHYSICAL_DEVICE: 6572 c->Request.CDBLen = 10; 6573 c->Request.type_attr_dir = 6574 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6575 c->Request.Timeout = 0; 6576 c->Request.CDB[0] = BMIC_READ; 6577 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; 6578 c->Request.CDB[7] = (size >> 16) & 0xFF; 6579 c->Request.CDB[8] = (size >> 8) & 0XFF; 6580 break; 6581 case BMIC_SENSE_SUBSYSTEM_INFORMATION: 6582 c->Request.CDBLen = 10; 6583 c->Request.type_attr_dir = 6584 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6585 c->Request.Timeout = 0; 6586 c->Request.CDB[0] = BMIC_READ; 6587 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION; 6588 c->Request.CDB[7] = (size >> 16) & 0xFF; 6589 c->Request.CDB[8] = (size >> 8) & 0XFF; 6590 break; 6591 case BMIC_SENSE_STORAGE_BOX_PARAMS: 6592 c->Request.CDBLen = 10; 6593 c->Request.type_attr_dir = 6594 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6595 c->Request.Timeout = 0; 6596 c->Request.CDB[0] = BMIC_READ; 6597 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS; 6598 c->Request.CDB[7] = (size >> 16) & 0xFF; 6599 c->Request.CDB[8] = (size >> 8) & 0XFF; 6600 break; 6601 case BMIC_IDENTIFY_CONTROLLER: 6602 c->Request.CDBLen = 10; 6603 c->Request.type_attr_dir = 6604 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); 6605 c->Request.Timeout = 0; 6606 c->Request.CDB[0] = BMIC_READ; 6607 c->Request.CDB[1] = 0; 6608 c->Request.CDB[2] = 0; 6609 c->Request.CDB[3] = 0; 6610 c->Request.CDB[4] = 0; 6611 c->Request.CDB[5] = 0; 6612 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER; 6613 c->Request.CDB[7] = (size >> 16) & 0xFF; 6614 c->Request.CDB[8] = (size >> 8) & 0XFF; 6615 c->Request.CDB[9] = 0; 6616 break; 6617 default: 6618 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); 6619 BUG(); 6620 } 6621 } else if (cmd_type == TYPE_MSG) { 6622 switch (cmd) { 6623 6624 case HPSA_PHYS_TARGET_RESET: 6625 c->Request.CDBLen = 16; 6626 c->Request.type_attr_dir = 6627 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6628 c->Request.Timeout = 0; /* Don't time out */ 6629 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); 6630 c->Request.CDB[0] = HPSA_RESET; 6631 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE; 6632 /* Physical target reset needs no control bytes 4-7*/ 6633 c->Request.CDB[4] = 0x00; 6634 c->Request.CDB[5] = 0x00; 6635 c->Request.CDB[6] = 0x00; 6636 c->Request.CDB[7] = 0x00; 6637 break; 6638 case HPSA_DEVICE_RESET_MSG: 6639 c->Request.CDBLen = 16; 6640 c->Request.type_attr_dir = 6641 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); 6642 c->Request.Timeout = 0; /* Don't time out */ 6643 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); 6644 c->Request.CDB[0] = cmd; 6645 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; 6646 /* If bytes 4-7 are zero, it means reset the */ 6647 /* LunID device */ 6648 c->Request.CDB[4] = 0x00; 6649 c->Request.CDB[5] = 0x00; 6650 c->Request.CDB[6] = 0x00; 6651 c->Request.CDB[7] = 0x00; 6652 break; 6653 default: 6654 dev_warn(&h->pdev->dev, "unknown message type %d\n", 6655 cmd); 6656 BUG(); 6657 } 6658 } else { 6659 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); 6660 BUG(); 6661 } 6662 6663 switch (GET_DIR(c->Request.type_attr_dir)) { 6664 case XFER_READ: 6665 pci_dir = PCI_DMA_FROMDEVICE; 6666 break; 6667 case XFER_WRITE: 6668 pci_dir = PCI_DMA_TODEVICE; 6669 break; 6670 case XFER_NONE: 6671 pci_dir = PCI_DMA_NONE; 6672 break; 6673 default: 6674 pci_dir = PCI_DMA_BIDIRECTIONAL; 6675 } 6676 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) 6677 return -1; 6678 return 0; 6679 } 6680 6681 /* 6682 * Map (physical) PCI mem into (virtual) kernel space 6683 */ 6684 static void __iomem *remap_pci_mem(ulong base, ulong size) 6685 { 6686 ulong page_base = ((ulong) base) & PAGE_MASK; 6687 ulong page_offs = ((ulong) base) - page_base; 6688 void __iomem *page_remapped = ioremap_nocache(page_base, 6689 page_offs + size); 6690 6691 return page_remapped ? (page_remapped + page_offs) : NULL; 6692 } 6693 6694 static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) 6695 { 6696 return h->access.command_completed(h, q); 6697 } 6698 6699 static inline bool interrupt_pending(struct ctlr_info *h) 6700 { 6701 return h->access.intr_pending(h); 6702 } 6703 6704 static inline long interrupt_not_for_us(struct ctlr_info *h) 6705 { 6706 return (h->access.intr_pending(h) == 0) || 6707 (h->interrupts_enabled == 0); 6708 } 6709 6710 static inline int bad_tag(struct ctlr_info *h, u32 tag_index, 6711 u32 raw_tag) 6712 { 6713 if (unlikely(tag_index >= h->nr_cmds)) { 6714 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); 6715 return 1; 6716 } 6717 return 0; 6718 } 6719 6720 static inline void finish_cmd(struct CommandList *c) 6721 { 6722 dial_up_lockup_detection_on_fw_flash_complete(c->h, c); 6723 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI 6724 || c->cmd_type == CMD_IOACCEL2)) 6725 complete_scsi_command(c); 6726 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF) 6727 complete(c->waiting); 6728 } 6729 6730 /* process completion of an indexed ("direct lookup") command */ 6731 static inline void process_indexed_cmd(struct ctlr_info *h, 6732 u32 raw_tag) 6733 { 6734 u32 tag_index; 6735 struct CommandList *c; 6736 6737 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; 6738 if (!bad_tag(h, tag_index, raw_tag)) { 6739 c = h->cmd_pool + tag_index; 6740 finish_cmd(c); 6741 } 6742 } 6743 6744 /* Some controllers, like p400, will give us one interrupt 6745 * after a soft reset, even if we turned interrupts off. 6746 * Only need to check for this in the hpsa_xxx_discard_completions 6747 * functions. 6748 */ 6749 static int ignore_bogus_interrupt(struct ctlr_info *h) 6750 { 6751 if (likely(!reset_devices)) 6752 return 0; 6753 6754 if (likely(h->interrupts_enabled)) 6755 return 0; 6756 6757 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " 6758 "(known firmware bug.) Ignoring.\n"); 6759 6760 return 1; 6761 } 6762 6763 /* 6764 * Convert &h->q[x] (passed to interrupt handlers) back to h. 6765 * Relies on (h-q[x] == x) being true for x such that 6766 * 0 <= x < MAX_REPLY_QUEUES. 6767 */ 6768 static struct ctlr_info *queue_to_hba(u8 *queue) 6769 { 6770 return container_of((queue - *queue), struct ctlr_info, q[0]); 6771 } 6772 6773 static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) 6774 { 6775 struct ctlr_info *h = queue_to_hba(queue); 6776 u8 q = *(u8 *) queue; 6777 u32 raw_tag; 6778 6779 if (ignore_bogus_interrupt(h)) 6780 return IRQ_NONE; 6781 6782 if (interrupt_not_for_us(h)) 6783 return IRQ_NONE; 6784 h->last_intr_timestamp = get_jiffies_64(); 6785 while (interrupt_pending(h)) { 6786 raw_tag = get_next_completion(h, q); 6787 while (raw_tag != FIFO_EMPTY) 6788 raw_tag = next_command(h, q); 6789 } 6790 return IRQ_HANDLED; 6791 } 6792 6793 static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) 6794 { 6795 struct ctlr_info *h = queue_to_hba(queue); 6796 u32 raw_tag; 6797 u8 q = *(u8 *) queue; 6798 6799 if (ignore_bogus_interrupt(h)) 6800 return IRQ_NONE; 6801 6802 h->last_intr_timestamp = get_jiffies_64(); 6803 raw_tag = get_next_completion(h, q); 6804 while (raw_tag != FIFO_EMPTY) 6805 raw_tag = next_command(h, q); 6806 return IRQ_HANDLED; 6807 } 6808 6809 static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) 6810 { 6811 struct ctlr_info *h = queue_to_hba((u8 *) queue); 6812 u32 raw_tag; 6813 u8 q = *(u8 *) queue; 6814 6815 if (interrupt_not_for_us(h)) 6816 return IRQ_NONE; 6817 h->last_intr_timestamp = get_jiffies_64(); 6818 while (interrupt_pending(h)) { 6819 raw_tag = get_next_completion(h, q); 6820 while (raw_tag != FIFO_EMPTY) { 6821 process_indexed_cmd(h, raw_tag); 6822 raw_tag = next_command(h, q); 6823 } 6824 } 6825 return IRQ_HANDLED; 6826 } 6827 6828 static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) 6829 { 6830 struct ctlr_info *h = queue_to_hba(queue); 6831 u32 raw_tag; 6832 u8 q = *(u8 *) queue; 6833 6834 h->last_intr_timestamp = get_jiffies_64(); 6835 raw_tag = get_next_completion(h, q); 6836 while (raw_tag != FIFO_EMPTY) { 6837 process_indexed_cmd(h, raw_tag); 6838 raw_tag = next_command(h, q); 6839 } 6840 return IRQ_HANDLED; 6841 } 6842 6843 /* Send a message CDB to the firmware. Careful, this only works 6844 * in simple mode, not performant mode due to the tag lookup. 6845 * We only ever use this immediately after a controller reset. 6846 */ 6847 static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, 6848 unsigned char type) 6849 { 6850 struct Command { 6851 struct CommandListHeader CommandHeader; 6852 struct RequestBlock Request; 6853 struct ErrDescriptor ErrorDescriptor; 6854 }; 6855 struct Command *cmd; 6856 static const size_t cmd_sz = sizeof(*cmd) + 6857 sizeof(cmd->ErrorDescriptor); 6858 dma_addr_t paddr64; 6859 __le32 paddr32; 6860 u32 tag; 6861 void __iomem *vaddr; 6862 int i, err; 6863 6864 vaddr = pci_ioremap_bar(pdev, 0); 6865 if (vaddr == NULL) 6866 return -ENOMEM; 6867 6868 /* The Inbound Post Queue only accepts 32-bit physical addresses for the 6869 * CCISS commands, so they must be allocated from the lower 4GiB of 6870 * memory. 6871 */ 6872 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 6873 if (err) { 6874 iounmap(vaddr); 6875 return err; 6876 } 6877 6878 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); 6879 if (cmd == NULL) { 6880 iounmap(vaddr); 6881 return -ENOMEM; 6882 } 6883 6884 /* This must fit, because of the 32-bit consistent DMA mask. Also, 6885 * although there's no guarantee, we assume that the address is at 6886 * least 4-byte aligned (most likely, it's page-aligned). 6887 */ 6888 paddr32 = cpu_to_le32(paddr64); 6889 6890 cmd->CommandHeader.ReplyQueue = 0; 6891 cmd->CommandHeader.SGList = 0; 6892 cmd->CommandHeader.SGTotal = cpu_to_le16(0); 6893 cmd->CommandHeader.tag = cpu_to_le64(paddr64); 6894 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); 6895 6896 cmd->Request.CDBLen = 16; 6897 cmd->Request.type_attr_dir = 6898 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); 6899 cmd->Request.Timeout = 0; /* Don't time out */ 6900 cmd->Request.CDB[0] = opcode; 6901 cmd->Request.CDB[1] = type; 6902 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ 6903 cmd->ErrorDescriptor.Addr = 6904 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); 6905 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); 6906 6907 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); 6908 6909 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { 6910 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); 6911 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) 6912 break; 6913 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); 6914 } 6915 6916 iounmap(vaddr); 6917 6918 /* we leak the DMA buffer here ... no choice since the controller could 6919 * still complete the command. 6920 */ 6921 if (i == HPSA_MSG_SEND_RETRY_LIMIT) { 6922 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", 6923 opcode, type); 6924 return -ETIMEDOUT; 6925 } 6926 6927 pci_free_consistent(pdev, cmd_sz, cmd, paddr64); 6928 6929 if (tag & HPSA_ERROR_BIT) { 6930 dev_err(&pdev->dev, "controller message %02x:%02x failed\n", 6931 opcode, type); 6932 return -EIO; 6933 } 6934 6935 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", 6936 opcode, type); 6937 return 0; 6938 } 6939 6940 #define hpsa_noop(p) hpsa_message(p, 3, 0) 6941 6942 static int hpsa_controller_hard_reset(struct pci_dev *pdev, 6943 void __iomem *vaddr, u32 use_doorbell) 6944 { 6945 6946 if (use_doorbell) { 6947 /* For everything after the P600, the PCI power state method 6948 * of resetting the controller doesn't work, so we have this 6949 * other way using the doorbell register. 6950 */ 6951 dev_info(&pdev->dev, "using doorbell to reset controller\n"); 6952 writel(use_doorbell, vaddr + SA5_DOORBELL); 6953 6954 /* PMC hardware guys tell us we need a 10 second delay after 6955 * doorbell reset and before any attempt to talk to the board 6956 * at all to ensure that this actually works and doesn't fall 6957 * over in some weird corner cases. 6958 */ 6959 msleep(10000); 6960 } else { /* Try to do it the PCI power state way */ 6961 6962 /* Quoting from the Open CISS Specification: "The Power 6963 * Management Control/Status Register (CSR) controls the power 6964 * state of the device. The normal operating state is D0, 6965 * CSR=00h. The software off state is D3, CSR=03h. To reset 6966 * the controller, place the interface device in D3 then to D0, 6967 * this causes a secondary PCI reset which will reset the 6968 * controller." */ 6969 6970 int rc = 0; 6971 6972 dev_info(&pdev->dev, "using PCI PM to reset controller\n"); 6973 6974 /* enter the D3hot power management state */ 6975 rc = pci_set_power_state(pdev, PCI_D3hot); 6976 if (rc) 6977 return rc; 6978 6979 msleep(500); 6980 6981 /* enter the D0 power management state */ 6982 rc = pci_set_power_state(pdev, PCI_D0); 6983 if (rc) 6984 return rc; 6985 6986 /* 6987 * The P600 requires a small delay when changing states. 6988 * Otherwise we may think the board did not reset and we bail. 6989 * This for kdump only and is particular to the P600. 6990 */ 6991 msleep(500); 6992 } 6993 return 0; 6994 } 6995 6996 static void init_driver_version(char *driver_version, int len) 6997 { 6998 memset(driver_version, 0, len); 6999 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); 7000 } 7001 7002 static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) 7003 { 7004 char *driver_version; 7005 int i, size = sizeof(cfgtable->driver_version); 7006 7007 driver_version = kmalloc(size, GFP_KERNEL); 7008 if (!driver_version) 7009 return -ENOMEM; 7010 7011 init_driver_version(driver_version, size); 7012 for (i = 0; i < size; i++) 7013 writeb(driver_version[i], &cfgtable->driver_version[i]); 7014 kfree(driver_version); 7015 return 0; 7016 } 7017 7018 static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, 7019 unsigned char *driver_ver) 7020 { 7021 int i; 7022 7023 for (i = 0; i < sizeof(cfgtable->driver_version); i++) 7024 driver_ver[i] = readb(&cfgtable->driver_version[i]); 7025 } 7026 7027 static int controller_reset_failed(struct CfgTable __iomem *cfgtable) 7028 { 7029 7030 char *driver_ver, *old_driver_ver; 7031 int rc, size = sizeof(cfgtable->driver_version); 7032 7033 old_driver_ver = kmalloc(2 * size, GFP_KERNEL); 7034 if (!old_driver_ver) 7035 return -ENOMEM; 7036 driver_ver = old_driver_ver + size; 7037 7038 /* After a reset, the 32 bytes of "driver version" in the cfgtable 7039 * should have been changed, otherwise we know the reset failed. 7040 */ 7041 init_driver_version(old_driver_ver, size); 7042 read_driver_ver_from_cfgtable(cfgtable, driver_ver); 7043 rc = !memcmp(driver_ver, old_driver_ver, size); 7044 kfree(old_driver_ver); 7045 return rc; 7046 } 7047 /* This does a hard reset of the controller using PCI power management 7048 * states or the using the doorbell register. 7049 */ 7050 static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id) 7051 { 7052 u64 cfg_offset; 7053 u32 cfg_base_addr; 7054 u64 cfg_base_addr_index; 7055 void __iomem *vaddr; 7056 unsigned long paddr; 7057 u32 misc_fw_support; 7058 int rc; 7059 struct CfgTable __iomem *cfgtable; 7060 u32 use_doorbell; 7061 u16 command_register; 7062 7063 /* For controllers as old as the P600, this is very nearly 7064 * the same thing as 7065 * 7066 * pci_save_state(pci_dev); 7067 * pci_set_power_state(pci_dev, PCI_D3hot); 7068 * pci_set_power_state(pci_dev, PCI_D0); 7069 * pci_restore_state(pci_dev); 7070 * 7071 * For controllers newer than the P600, the pci power state 7072 * method of resetting doesn't work so we have another way 7073 * using the doorbell register. 7074 */ 7075 7076 if (!ctlr_is_resettable(board_id)) { 7077 dev_warn(&pdev->dev, "Controller not resettable\n"); 7078 return -ENODEV; 7079 } 7080 7081 /* if controller is soft- but not hard resettable... */ 7082 if (!ctlr_is_hard_resettable(board_id)) 7083 return -ENOTSUPP; /* try soft reset later. */ 7084 7085 /* Save the PCI command register */ 7086 pci_read_config_word(pdev, 4, &command_register); 7087 pci_save_state(pdev); 7088 7089 /* find the first memory BAR, so we can find the cfg table */ 7090 rc = hpsa_pci_find_memory_BAR(pdev, &paddr); 7091 if (rc) 7092 return rc; 7093 vaddr = remap_pci_mem(paddr, 0x250); 7094 if (!vaddr) 7095 return -ENOMEM; 7096 7097 /* find cfgtable in order to check if reset via doorbell is supported */ 7098 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, 7099 &cfg_base_addr_index, &cfg_offset); 7100 if (rc) 7101 goto unmap_vaddr; 7102 cfgtable = remap_pci_mem(pci_resource_start(pdev, 7103 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); 7104 if (!cfgtable) { 7105 rc = -ENOMEM; 7106 goto unmap_vaddr; 7107 } 7108 rc = write_driver_ver_to_cfgtable(cfgtable); 7109 if (rc) 7110 goto unmap_cfgtable; 7111 7112 /* If reset via doorbell register is supported, use that. 7113 * There are two such methods. Favor the newest method. 7114 */ 7115 misc_fw_support = readl(&cfgtable->misc_fw_support); 7116 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; 7117 if (use_doorbell) { 7118 use_doorbell = DOORBELL_CTLR_RESET2; 7119 } else { 7120 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; 7121 if (use_doorbell) { 7122 dev_warn(&pdev->dev, 7123 "Soft reset not supported. Firmware update is required.\n"); 7124 rc = -ENOTSUPP; /* try soft reset */ 7125 goto unmap_cfgtable; 7126 } 7127 } 7128 7129 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); 7130 if (rc) 7131 goto unmap_cfgtable; 7132 7133 pci_restore_state(pdev); 7134 pci_write_config_word(pdev, 4, command_register); 7135 7136 /* Some devices (notably the HP Smart Array 5i Controller) 7137 need a little pause here */ 7138 msleep(HPSA_POST_RESET_PAUSE_MSECS); 7139 7140 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); 7141 if (rc) { 7142 dev_warn(&pdev->dev, 7143 "Failed waiting for board to become ready after hard reset\n"); 7144 goto unmap_cfgtable; 7145 } 7146 7147 rc = controller_reset_failed(vaddr); 7148 if (rc < 0) 7149 goto unmap_cfgtable; 7150 if (rc) { 7151 dev_warn(&pdev->dev, "Unable to successfully reset " 7152 "controller. Will try soft reset.\n"); 7153 rc = -ENOTSUPP; 7154 } else { 7155 dev_info(&pdev->dev, "board ready after hard reset.\n"); 7156 } 7157 7158 unmap_cfgtable: 7159 iounmap(cfgtable); 7160 7161 unmap_vaddr: 7162 iounmap(vaddr); 7163 return rc; 7164 } 7165 7166 /* 7167 * We cannot read the structure directly, for portability we must use 7168 * the io functions. 7169 * This is for debug only. 7170 */ 7171 static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) 7172 { 7173 #ifdef HPSA_DEBUG 7174 int i; 7175 char temp_name[17]; 7176 7177 dev_info(dev, "Controller Configuration information\n"); 7178 dev_info(dev, "------------------------------------\n"); 7179 for (i = 0; i < 4; i++) 7180 temp_name[i] = readb(&(tb->Signature[i])); 7181 temp_name[4] = '\0'; 7182 dev_info(dev, " Signature = %s\n", temp_name); 7183 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); 7184 dev_info(dev, " Transport methods supported = 0x%x\n", 7185 readl(&(tb->TransportSupport))); 7186 dev_info(dev, " Transport methods active = 0x%x\n", 7187 readl(&(tb->TransportActive))); 7188 dev_info(dev, " Requested transport Method = 0x%x\n", 7189 readl(&(tb->HostWrite.TransportRequest))); 7190 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", 7191 readl(&(tb->HostWrite.CoalIntDelay))); 7192 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", 7193 readl(&(tb->HostWrite.CoalIntCount))); 7194 dev_info(dev, " Max outstanding commands = %d\n", 7195 readl(&(tb->CmdsOutMax))); 7196 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); 7197 for (i = 0; i < 16; i++) 7198 temp_name[i] = readb(&(tb->ServerName[i])); 7199 temp_name[16] = '\0'; 7200 dev_info(dev, " Server Name = %s\n", temp_name); 7201 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", 7202 readl(&(tb->HeartBeat))); 7203 #endif /* HPSA_DEBUG */ 7204 } 7205 7206 static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) 7207 { 7208 int i, offset, mem_type, bar_type; 7209 7210 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ 7211 return 0; 7212 offset = 0; 7213 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 7214 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; 7215 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) 7216 offset += 4; 7217 else { 7218 mem_type = pci_resource_flags(pdev, i) & 7219 PCI_BASE_ADDRESS_MEM_TYPE_MASK; 7220 switch (mem_type) { 7221 case PCI_BASE_ADDRESS_MEM_TYPE_32: 7222 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 7223 offset += 4; /* 32 bit */ 7224 break; 7225 case PCI_BASE_ADDRESS_MEM_TYPE_64: 7226 offset += 8; 7227 break; 7228 default: /* reserved in PCI 2.2 */ 7229 dev_warn(&pdev->dev, 7230 "base address is invalid\n"); 7231 return -1; 7232 break; 7233 } 7234 } 7235 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) 7236 return i + 1; 7237 } 7238 return -1; 7239 } 7240 7241 static void hpsa_disable_interrupt_mode(struct ctlr_info *h) 7242 { 7243 pci_free_irq_vectors(h->pdev); 7244 h->msix_vectors = 0; 7245 } 7246 7247 /* If MSI/MSI-X is supported by the kernel we will try to enable it on 7248 * controllers that are capable. If not, we use legacy INTx mode. 7249 */ 7250 static int hpsa_interrupt_mode(struct ctlr_info *h) 7251 { 7252 unsigned int flags = PCI_IRQ_LEGACY; 7253 int ret; 7254 7255 /* Some boards advertise MSI but don't really support it */ 7256 switch (h->board_id) { 7257 case 0x40700E11: 7258 case 0x40800E11: 7259 case 0x40820E11: 7260 case 0x40830E11: 7261 break; 7262 default: 7263 ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES, 7264 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY); 7265 if (ret > 0) { 7266 h->msix_vectors = ret; 7267 return 0; 7268 } 7269 7270 flags |= PCI_IRQ_MSI; 7271 break; 7272 } 7273 7274 ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags); 7275 if (ret < 0) 7276 return ret; 7277 return 0; 7278 } 7279 7280 static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, 7281 bool *legacy_board) 7282 { 7283 int i; 7284 u32 subsystem_vendor_id, subsystem_device_id; 7285 7286 subsystem_vendor_id = pdev->subsystem_vendor; 7287 subsystem_device_id = pdev->subsystem_device; 7288 *board_id = ((subsystem_device_id << 16) & 0xffff0000) | 7289 subsystem_vendor_id; 7290 7291 if (legacy_board) 7292 *legacy_board = false; 7293 for (i = 0; i < ARRAY_SIZE(products); i++) 7294 if (*board_id == products[i].board_id) { 7295 if (products[i].access != &SA5A_access && 7296 products[i].access != &SA5B_access) 7297 return i; 7298 dev_warn(&pdev->dev, 7299 "legacy board ID: 0x%08x\n", 7300 *board_id); 7301 if (legacy_board) 7302 *legacy_board = true; 7303 return i; 7304 } 7305 7306 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id); 7307 if (legacy_board) 7308 *legacy_board = true; 7309 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ 7310 } 7311 7312 static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, 7313 unsigned long *memory_bar) 7314 { 7315 int i; 7316 7317 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) 7318 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { 7319 /* addressing mode bits already removed */ 7320 *memory_bar = pci_resource_start(pdev, i); 7321 dev_dbg(&pdev->dev, "memory BAR = %lx\n", 7322 *memory_bar); 7323 return 0; 7324 } 7325 dev_warn(&pdev->dev, "no memory BAR found\n"); 7326 return -ENODEV; 7327 } 7328 7329 static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, 7330 int wait_for_ready) 7331 { 7332 int i, iterations; 7333 u32 scratchpad; 7334 if (wait_for_ready) 7335 iterations = HPSA_BOARD_READY_ITERATIONS; 7336 else 7337 iterations = HPSA_BOARD_NOT_READY_ITERATIONS; 7338 7339 for (i = 0; i < iterations; i++) { 7340 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); 7341 if (wait_for_ready) { 7342 if (scratchpad == HPSA_FIRMWARE_READY) 7343 return 0; 7344 } else { 7345 if (scratchpad != HPSA_FIRMWARE_READY) 7346 return 0; 7347 } 7348 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); 7349 } 7350 dev_warn(&pdev->dev, "board not ready, timed out.\n"); 7351 return -ENODEV; 7352 } 7353 7354 static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, 7355 u32 *cfg_base_addr, u64 *cfg_base_addr_index, 7356 u64 *cfg_offset) 7357 { 7358 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); 7359 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); 7360 *cfg_base_addr &= (u32) 0x0000ffff; 7361 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); 7362 if (*cfg_base_addr_index == -1) { 7363 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); 7364 return -ENODEV; 7365 } 7366 return 0; 7367 } 7368 7369 static void hpsa_free_cfgtables(struct ctlr_info *h) 7370 { 7371 if (h->transtable) { 7372 iounmap(h->transtable); 7373 h->transtable = NULL; 7374 } 7375 if (h->cfgtable) { 7376 iounmap(h->cfgtable); 7377 h->cfgtable = NULL; 7378 } 7379 } 7380 7381 /* Find and map CISS config table and transfer table 7382 + * several items must be unmapped (freed) later 7383 + * */ 7384 static int hpsa_find_cfgtables(struct ctlr_info *h) 7385 { 7386 u64 cfg_offset; 7387 u32 cfg_base_addr; 7388 u64 cfg_base_addr_index; 7389 u32 trans_offset; 7390 int rc; 7391 7392 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, 7393 &cfg_base_addr_index, &cfg_offset); 7394 if (rc) 7395 return rc; 7396 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, 7397 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); 7398 if (!h->cfgtable) { 7399 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); 7400 return -ENOMEM; 7401 } 7402 rc = write_driver_ver_to_cfgtable(h->cfgtable); 7403 if (rc) 7404 return rc; 7405 /* Find performant mode table. */ 7406 trans_offset = readl(&h->cfgtable->TransMethodOffset); 7407 h->transtable = remap_pci_mem(pci_resource_start(h->pdev, 7408 cfg_base_addr_index)+cfg_offset+trans_offset, 7409 sizeof(*h->transtable)); 7410 if (!h->transtable) { 7411 dev_err(&h->pdev->dev, "Failed mapping transfer table\n"); 7412 hpsa_free_cfgtables(h); 7413 return -ENOMEM; 7414 } 7415 return 0; 7416 } 7417 7418 static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) 7419 { 7420 #define MIN_MAX_COMMANDS 16 7421 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS); 7422 7423 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands); 7424 7425 /* Limit commands in memory limited kdump scenario. */ 7426 if (reset_devices && h->max_commands > 32) 7427 h->max_commands = 32; 7428 7429 if (h->max_commands < MIN_MAX_COMMANDS) { 7430 dev_warn(&h->pdev->dev, 7431 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n", 7432 h->max_commands, 7433 MIN_MAX_COMMANDS); 7434 h->max_commands = MIN_MAX_COMMANDS; 7435 } 7436 } 7437 7438 /* If the controller reports that the total max sg entries is greater than 512, 7439 * then we know that chained SG blocks work. (Original smart arrays did not 7440 * support chained SG blocks and would return zero for max sg entries.) 7441 */ 7442 static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) 7443 { 7444 return h->maxsgentries > 512; 7445 } 7446 7447 /* Interrogate the hardware for some limits: 7448 * max commands, max SG elements without chaining, and with chaining, 7449 * SG chain block size, etc. 7450 */ 7451 static void hpsa_find_board_params(struct ctlr_info *h) 7452 { 7453 hpsa_get_max_perf_mode_cmds(h); 7454 h->nr_cmds = h->max_commands; 7455 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); 7456 h->fw_support = readl(&(h->cfgtable->misc_fw_support)); 7457 if (hpsa_supports_chained_sg_blocks(h)) { 7458 /* Limit in-command s/g elements to 32 save dma'able memory. */ 7459 h->max_cmd_sg_entries = 32; 7460 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; 7461 h->maxsgentries--; /* save one for chain pointer */ 7462 } else { 7463 /* 7464 * Original smart arrays supported at most 31 s/g entries 7465 * embedded inline in the command (trying to use more 7466 * would lock up the controller) 7467 */ 7468 h->max_cmd_sg_entries = 31; 7469 h->maxsgentries = 31; /* default to traditional values */ 7470 h->chainsize = 0; 7471 } 7472 7473 /* Find out what task management functions are supported and cache */ 7474 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); 7475 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) 7476 dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); 7477 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) 7478 dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); 7479 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)) 7480 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n"); 7481 } 7482 7483 static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) 7484 { 7485 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { 7486 dev_err(&h->pdev->dev, "not a valid CISS config table\n"); 7487 return false; 7488 } 7489 return true; 7490 } 7491 7492 static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) 7493 { 7494 u32 driver_support; 7495 7496 driver_support = readl(&(h->cfgtable->driver_support)); 7497 /* Need to enable prefetch in the SCSI core for 6400 in x86 */ 7498 #ifdef CONFIG_X86 7499 driver_support |= ENABLE_SCSI_PREFETCH; 7500 #endif 7501 driver_support |= ENABLE_UNIT_ATTN; 7502 writel(driver_support, &(h->cfgtable->driver_support)); 7503 } 7504 7505 /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result 7506 * in a prefetch beyond physical memory. 7507 */ 7508 static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) 7509 { 7510 u32 dma_prefetch; 7511 7512 if (h->board_id != 0x3225103C) 7513 return; 7514 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); 7515 dma_prefetch |= 0x8000; 7516 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); 7517 } 7518 7519 static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) 7520 { 7521 int i; 7522 u32 doorbell_value; 7523 unsigned long flags; 7524 /* wait until the clear_event_notify bit 6 is cleared by controller. */ 7525 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) { 7526 spin_lock_irqsave(&h->lock, flags); 7527 doorbell_value = readl(h->vaddr + SA5_DOORBELL); 7528 spin_unlock_irqrestore(&h->lock, flags); 7529 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) 7530 goto done; 7531 /* delay and try again */ 7532 msleep(CLEAR_EVENT_WAIT_INTERVAL); 7533 } 7534 return -ENODEV; 7535 done: 7536 return 0; 7537 } 7538 7539 static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h) 7540 { 7541 int i; 7542 u32 doorbell_value; 7543 unsigned long flags; 7544 7545 /* under certain very rare conditions, this can take awhile. 7546 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right 7547 * as we enter this code.) 7548 */ 7549 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) { 7550 if (h->remove_in_progress) 7551 goto done; 7552 spin_lock_irqsave(&h->lock, flags); 7553 doorbell_value = readl(h->vaddr + SA5_DOORBELL); 7554 spin_unlock_irqrestore(&h->lock, flags); 7555 if (!(doorbell_value & CFGTBL_ChangeReq)) 7556 goto done; 7557 /* delay and try again */ 7558 msleep(MODE_CHANGE_WAIT_INTERVAL); 7559 } 7560 return -ENODEV; 7561 done: 7562 return 0; 7563 } 7564 7565 /* return -ENODEV or other reason on error, 0 on success */ 7566 static int hpsa_enter_simple_mode(struct ctlr_info *h) 7567 { 7568 u32 trans_support; 7569 7570 trans_support = readl(&(h->cfgtable->TransportSupport)); 7571 if (!(trans_support & SIMPLE_MODE)) 7572 return -ENOTSUPP; 7573 7574 h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); 7575 7576 /* Update the field, and then ring the doorbell */ 7577 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); 7578 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); 7579 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 7580 if (hpsa_wait_for_mode_change_ack(h)) 7581 goto error; 7582 print_cfg_table(&h->pdev->dev, h->cfgtable); 7583 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) 7584 goto error; 7585 h->transMethod = CFGTBL_Trans_Simple; 7586 return 0; 7587 error: 7588 dev_err(&h->pdev->dev, "failed to enter simple mode\n"); 7589 return -ENODEV; 7590 } 7591 7592 /* free items allocated or mapped by hpsa_pci_init */ 7593 static void hpsa_free_pci_init(struct ctlr_info *h) 7594 { 7595 hpsa_free_cfgtables(h); /* pci_init 4 */ 7596 iounmap(h->vaddr); /* pci_init 3 */ 7597 h->vaddr = NULL; 7598 hpsa_disable_interrupt_mode(h); /* pci_init 2 */ 7599 /* 7600 * call pci_disable_device before pci_release_regions per 7601 * Documentation/PCI/pci.txt 7602 */ 7603 pci_disable_device(h->pdev); /* pci_init 1 */ 7604 pci_release_regions(h->pdev); /* pci_init 2 */ 7605 } 7606 7607 /* several items must be freed later */ 7608 static int hpsa_pci_init(struct ctlr_info *h) 7609 { 7610 int prod_index, err; 7611 bool legacy_board; 7612 7613 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board); 7614 if (prod_index < 0) 7615 return prod_index; 7616 h->product_name = products[prod_index].product_name; 7617 h->access = *(products[prod_index].access); 7618 h->legacy_board = legacy_board; 7619 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | 7620 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); 7621 7622 err = pci_enable_device(h->pdev); 7623 if (err) { 7624 dev_err(&h->pdev->dev, "failed to enable PCI device\n"); 7625 pci_disable_device(h->pdev); 7626 return err; 7627 } 7628 7629 err = pci_request_regions(h->pdev, HPSA); 7630 if (err) { 7631 dev_err(&h->pdev->dev, 7632 "failed to obtain PCI resources\n"); 7633 pci_disable_device(h->pdev); 7634 return err; 7635 } 7636 7637 pci_set_master(h->pdev); 7638 7639 err = hpsa_interrupt_mode(h); 7640 if (err) 7641 goto clean1; 7642 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); 7643 if (err) 7644 goto clean2; /* intmode+region, pci */ 7645 h->vaddr = remap_pci_mem(h->paddr, 0x250); 7646 if (!h->vaddr) { 7647 dev_err(&h->pdev->dev, "failed to remap PCI mem\n"); 7648 err = -ENOMEM; 7649 goto clean2; /* intmode+region, pci */ 7650 } 7651 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); 7652 if (err) 7653 goto clean3; /* vaddr, intmode+region, pci */ 7654 err = hpsa_find_cfgtables(h); 7655 if (err) 7656 goto clean3; /* vaddr, intmode+region, pci */ 7657 hpsa_find_board_params(h); 7658 7659 if (!hpsa_CISS_signature_present(h)) { 7660 err = -ENODEV; 7661 goto clean4; /* cfgtables, vaddr, intmode+region, pci */ 7662 } 7663 hpsa_set_driver_support_bits(h); 7664 hpsa_p600_dma_prefetch_quirk(h); 7665 err = hpsa_enter_simple_mode(h); 7666 if (err) 7667 goto clean4; /* cfgtables, vaddr, intmode+region, pci */ 7668 return 0; 7669 7670 clean4: /* cfgtables, vaddr, intmode+region, pci */ 7671 hpsa_free_cfgtables(h); 7672 clean3: /* vaddr, intmode+region, pci */ 7673 iounmap(h->vaddr); 7674 h->vaddr = NULL; 7675 clean2: /* intmode+region, pci */ 7676 hpsa_disable_interrupt_mode(h); 7677 clean1: 7678 /* 7679 * call pci_disable_device before pci_release_regions per 7680 * Documentation/PCI/pci.txt 7681 */ 7682 pci_disable_device(h->pdev); 7683 pci_release_regions(h->pdev); 7684 return err; 7685 } 7686 7687 static void hpsa_hba_inquiry(struct ctlr_info *h) 7688 { 7689 int rc; 7690 7691 #define HBA_INQUIRY_BYTE_COUNT 64 7692 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); 7693 if (!h->hba_inquiry_data) 7694 return; 7695 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, 7696 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); 7697 if (rc != 0) { 7698 kfree(h->hba_inquiry_data); 7699 h->hba_inquiry_data = NULL; 7700 } 7701 } 7702 7703 static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id) 7704 { 7705 int rc, i; 7706 void __iomem *vaddr; 7707 7708 if (!reset_devices) 7709 return 0; 7710 7711 /* kdump kernel is loading, we don't know in which state is 7712 * the pci interface. The dev->enable_cnt is equal zero 7713 * so we call enable+disable, wait a while and switch it on. 7714 */ 7715 rc = pci_enable_device(pdev); 7716 if (rc) { 7717 dev_warn(&pdev->dev, "Failed to enable PCI device\n"); 7718 return -ENODEV; 7719 } 7720 pci_disable_device(pdev); 7721 msleep(260); /* a randomly chosen number */ 7722 rc = pci_enable_device(pdev); 7723 if (rc) { 7724 dev_warn(&pdev->dev, "failed to enable device.\n"); 7725 return -ENODEV; 7726 } 7727 7728 pci_set_master(pdev); 7729 7730 vaddr = pci_ioremap_bar(pdev, 0); 7731 if (vaddr == NULL) { 7732 rc = -ENOMEM; 7733 goto out_disable; 7734 } 7735 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); 7736 iounmap(vaddr); 7737 7738 /* Reset the controller with a PCI power-cycle or via doorbell */ 7739 rc = hpsa_kdump_hard_reset_controller(pdev, board_id); 7740 7741 /* -ENOTSUPP here means we cannot reset the controller 7742 * but it's already (and still) up and running in 7743 * "performant mode". Or, it might be 640x, which can't reset 7744 * due to concerns about shared bbwc between 6402/6404 pair. 7745 */ 7746 if (rc) 7747 goto out_disable; 7748 7749 /* Now try to get the controller to respond to a no-op */ 7750 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); 7751 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { 7752 if (hpsa_noop(pdev) == 0) 7753 break; 7754 else 7755 dev_warn(&pdev->dev, "no-op failed%s\n", 7756 (i < 11 ? "; re-trying" : "")); 7757 } 7758 7759 out_disable: 7760 7761 pci_disable_device(pdev); 7762 return rc; 7763 } 7764 7765 static void hpsa_free_cmd_pool(struct ctlr_info *h) 7766 { 7767 kfree(h->cmd_pool_bits); 7768 h->cmd_pool_bits = NULL; 7769 if (h->cmd_pool) { 7770 pci_free_consistent(h->pdev, 7771 h->nr_cmds * sizeof(struct CommandList), 7772 h->cmd_pool, 7773 h->cmd_pool_dhandle); 7774 h->cmd_pool = NULL; 7775 h->cmd_pool_dhandle = 0; 7776 } 7777 if (h->errinfo_pool) { 7778 pci_free_consistent(h->pdev, 7779 h->nr_cmds * sizeof(struct ErrorInfo), 7780 h->errinfo_pool, 7781 h->errinfo_pool_dhandle); 7782 h->errinfo_pool = NULL; 7783 h->errinfo_pool_dhandle = 0; 7784 } 7785 } 7786 7787 static int hpsa_alloc_cmd_pool(struct ctlr_info *h) 7788 { 7789 h->cmd_pool_bits = kzalloc( 7790 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * 7791 sizeof(unsigned long), GFP_KERNEL); 7792 h->cmd_pool = pci_alloc_consistent(h->pdev, 7793 h->nr_cmds * sizeof(*h->cmd_pool), 7794 &(h->cmd_pool_dhandle)); 7795 h->errinfo_pool = pci_alloc_consistent(h->pdev, 7796 h->nr_cmds * sizeof(*h->errinfo_pool), 7797 &(h->errinfo_pool_dhandle)); 7798 if ((h->cmd_pool_bits == NULL) 7799 || (h->cmd_pool == NULL) 7800 || (h->errinfo_pool == NULL)) { 7801 dev_err(&h->pdev->dev, "out of memory in %s", __func__); 7802 goto clean_up; 7803 } 7804 hpsa_preinitialize_commands(h); 7805 return 0; 7806 clean_up: 7807 hpsa_free_cmd_pool(h); 7808 return -ENOMEM; 7809 } 7810 7811 /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ 7812 static void hpsa_free_irqs(struct ctlr_info *h) 7813 { 7814 int i; 7815 7816 if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) { 7817 /* Single reply queue, only one irq to free */ 7818 free_irq(pci_irq_vector(h->pdev, 0), &h->q[h->intr_mode]); 7819 h->q[h->intr_mode] = 0; 7820 return; 7821 } 7822 7823 for (i = 0; i < h->msix_vectors; i++) { 7824 free_irq(pci_irq_vector(h->pdev, i), &h->q[i]); 7825 h->q[i] = 0; 7826 } 7827 for (; i < MAX_REPLY_QUEUES; i++) 7828 h->q[i] = 0; 7829 } 7830 7831 /* returns 0 on success; cleans up and returns -Enn on error */ 7832 static int hpsa_request_irqs(struct ctlr_info *h, 7833 irqreturn_t (*msixhandler)(int, void *), 7834 irqreturn_t (*intxhandler)(int, void *)) 7835 { 7836 int rc, i; 7837 7838 /* 7839 * initialize h->q[x] = x so that interrupt handlers know which 7840 * queue to process. 7841 */ 7842 for (i = 0; i < MAX_REPLY_QUEUES; i++) 7843 h->q[i] = (u8) i; 7844 7845 if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) { 7846 /* If performant mode and MSI-X, use multiple reply queues */ 7847 for (i = 0; i < h->msix_vectors; i++) { 7848 sprintf(h->intrname[i], "%s-msix%d", h->devname, i); 7849 rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler, 7850 0, h->intrname[i], 7851 &h->q[i]); 7852 if (rc) { 7853 int j; 7854 7855 dev_err(&h->pdev->dev, 7856 "failed to get irq %d for %s\n", 7857 pci_irq_vector(h->pdev, i), h->devname); 7858 for (j = 0; j < i; j++) { 7859 free_irq(pci_irq_vector(h->pdev, j), &h->q[j]); 7860 h->q[j] = 0; 7861 } 7862 for (; j < MAX_REPLY_QUEUES; j++) 7863 h->q[j] = 0; 7864 return rc; 7865 } 7866 } 7867 } else { 7868 /* Use single reply pool */ 7869 if (h->msix_vectors > 0 || h->pdev->msi_enabled) { 7870 sprintf(h->intrname[0], "%s-msi%s", h->devname, 7871 h->msix_vectors ? "x" : ""); 7872 rc = request_irq(pci_irq_vector(h->pdev, 0), 7873 msixhandler, 0, 7874 h->intrname[0], 7875 &h->q[h->intr_mode]); 7876 } else { 7877 sprintf(h->intrname[h->intr_mode], 7878 "%s-intx", h->devname); 7879 rc = request_irq(pci_irq_vector(h->pdev, 0), 7880 intxhandler, IRQF_SHARED, 7881 h->intrname[0], 7882 &h->q[h->intr_mode]); 7883 } 7884 } 7885 if (rc) { 7886 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n", 7887 pci_irq_vector(h->pdev, 0), h->devname); 7888 hpsa_free_irqs(h); 7889 return -ENODEV; 7890 } 7891 return 0; 7892 } 7893 7894 static int hpsa_kdump_soft_reset(struct ctlr_info *h) 7895 { 7896 int rc; 7897 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER); 7898 7899 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); 7900 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY); 7901 if (rc) { 7902 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); 7903 return rc; 7904 } 7905 7906 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); 7907 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); 7908 if (rc) { 7909 dev_warn(&h->pdev->dev, "Board failed to become ready " 7910 "after soft reset.\n"); 7911 return rc; 7912 } 7913 7914 return 0; 7915 } 7916 7917 static void hpsa_free_reply_queues(struct ctlr_info *h) 7918 { 7919 int i; 7920 7921 for (i = 0; i < h->nreply_queues; i++) { 7922 if (!h->reply_queue[i].head) 7923 continue; 7924 pci_free_consistent(h->pdev, 7925 h->reply_queue_size, 7926 h->reply_queue[i].head, 7927 h->reply_queue[i].busaddr); 7928 h->reply_queue[i].head = NULL; 7929 h->reply_queue[i].busaddr = 0; 7930 } 7931 h->reply_queue_size = 0; 7932 } 7933 7934 static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) 7935 { 7936 hpsa_free_performant_mode(h); /* init_one 7 */ 7937 hpsa_free_sg_chain_blocks(h); /* init_one 6 */ 7938 hpsa_free_cmd_pool(h); /* init_one 5 */ 7939 hpsa_free_irqs(h); /* init_one 4 */ 7940 scsi_host_put(h->scsi_host); /* init_one 3 */ 7941 h->scsi_host = NULL; /* init_one 3 */ 7942 hpsa_free_pci_init(h); /* init_one 2_5 */ 7943 free_percpu(h->lockup_detected); /* init_one 2 */ 7944 h->lockup_detected = NULL; /* init_one 2 */ 7945 if (h->resubmit_wq) { 7946 destroy_workqueue(h->resubmit_wq); /* init_one 1 */ 7947 h->resubmit_wq = NULL; 7948 } 7949 if (h->rescan_ctlr_wq) { 7950 destroy_workqueue(h->rescan_ctlr_wq); 7951 h->rescan_ctlr_wq = NULL; 7952 } 7953 kfree(h); /* init_one 1 */ 7954 } 7955 7956 /* Called when controller lockup detected. */ 7957 static void fail_all_outstanding_cmds(struct ctlr_info *h) 7958 { 7959 int i, refcount; 7960 struct CommandList *c; 7961 int failcount = 0; 7962 7963 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ 7964 for (i = 0; i < h->nr_cmds; i++) { 7965 c = h->cmd_pool + i; 7966 refcount = atomic_inc_return(&c->refcount); 7967 if (refcount > 1) { 7968 c->err_info->CommandStatus = CMD_CTLR_LOCKUP; 7969 finish_cmd(c); 7970 atomic_dec(&h->commands_outstanding); 7971 failcount++; 7972 } 7973 cmd_free(h, c); 7974 } 7975 dev_warn(&h->pdev->dev, 7976 "failed %d commands in fail_all\n", failcount); 7977 } 7978 7979 static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) 7980 { 7981 int cpu; 7982 7983 for_each_online_cpu(cpu) { 7984 u32 *lockup_detected; 7985 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); 7986 *lockup_detected = value; 7987 } 7988 wmb(); /* be sure the per-cpu variables are out to memory */ 7989 } 7990 7991 static void controller_lockup_detected(struct ctlr_info *h) 7992 { 7993 unsigned long flags; 7994 u32 lockup_detected; 7995 7996 h->access.set_intr_mask(h, HPSA_INTR_OFF); 7997 spin_lock_irqsave(&h->lock, flags); 7998 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); 7999 if (!lockup_detected) { 8000 /* no heartbeat, but controller gave us a zero. */ 8001 dev_warn(&h->pdev->dev, 8002 "lockup detected after %d but scratchpad register is zero\n", 8003 h->heartbeat_sample_interval / HZ); 8004 lockup_detected = 0xffffffff; 8005 } 8006 set_lockup_detected_for_all_cpus(h, lockup_detected); 8007 spin_unlock_irqrestore(&h->lock, flags); 8008 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n", 8009 lockup_detected, h->heartbeat_sample_interval / HZ); 8010 pci_disable_device(h->pdev); 8011 fail_all_outstanding_cmds(h); 8012 } 8013 8014 static int detect_controller_lockup(struct ctlr_info *h) 8015 { 8016 u64 now; 8017 u32 heartbeat; 8018 unsigned long flags; 8019 8020 now = get_jiffies_64(); 8021 /* If we've received an interrupt recently, we're ok. */ 8022 if (time_after64(h->last_intr_timestamp + 8023 (h->heartbeat_sample_interval), now)) 8024 return false; 8025 8026 /* 8027 * If we've already checked the heartbeat recently, we're ok. 8028 * This could happen if someone sends us a signal. We 8029 * otherwise don't care about signals in this thread. 8030 */ 8031 if (time_after64(h->last_heartbeat_timestamp + 8032 (h->heartbeat_sample_interval), now)) 8033 return false; 8034 8035 /* If heartbeat has not changed since we last looked, we're not ok. */ 8036 spin_lock_irqsave(&h->lock, flags); 8037 heartbeat = readl(&h->cfgtable->HeartBeat); 8038 spin_unlock_irqrestore(&h->lock, flags); 8039 if (h->last_heartbeat == heartbeat) { 8040 controller_lockup_detected(h); 8041 return true; 8042 } 8043 8044 /* We're ok. */ 8045 h->last_heartbeat = heartbeat; 8046 h->last_heartbeat_timestamp = now; 8047 return false; 8048 } 8049 8050 static void hpsa_ack_ctlr_events(struct ctlr_info *h) 8051 { 8052 int i; 8053 char *event_type; 8054 8055 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) 8056 return; 8057 8058 /* Ask the controller to clear the events we're handling. */ 8059 if ((h->transMethod & (CFGTBL_Trans_io_accel1 8060 | CFGTBL_Trans_io_accel2)) && 8061 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || 8062 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { 8063 8064 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) 8065 event_type = "state change"; 8066 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) 8067 event_type = "configuration change"; 8068 /* Stop sending new RAID offload reqs via the IO accelerator */ 8069 scsi_block_requests(h->scsi_host); 8070 for (i = 0; i < h->ndevices; i++) { 8071 h->dev[i]->offload_enabled = 0; 8072 h->dev[i]->offload_to_be_enabled = 0; 8073 } 8074 hpsa_drain_accel_commands(h); 8075 /* Set 'accelerator path config change' bit */ 8076 dev_warn(&h->pdev->dev, 8077 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", 8078 h->events, event_type); 8079 writel(h->events, &(h->cfgtable->clear_event_notify)); 8080 /* Set the "clear event notify field update" bit 6 */ 8081 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); 8082 /* Wait until ctlr clears 'clear event notify field', bit 6 */ 8083 hpsa_wait_for_clear_event_notify_ack(h); 8084 scsi_unblock_requests(h->scsi_host); 8085 } else { 8086 /* Acknowledge controller notification events. */ 8087 writel(h->events, &(h->cfgtable->clear_event_notify)); 8088 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); 8089 hpsa_wait_for_clear_event_notify_ack(h); 8090 #if 0 8091 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 8092 hpsa_wait_for_mode_change_ack(h); 8093 #endif 8094 } 8095 return; 8096 } 8097 8098 /* Check a register on the controller to see if there are configuration 8099 * changes (added/changed/removed logical drives, etc.) which mean that 8100 * we should rescan the controller for devices. 8101 * Also check flag for driver-initiated rescan. 8102 */ 8103 static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) 8104 { 8105 if (h->drv_req_rescan) { 8106 h->drv_req_rescan = 0; 8107 return 1; 8108 } 8109 8110 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) 8111 return 0; 8112 8113 h->events = readl(&(h->cfgtable->event_notify)); 8114 return h->events & RESCAN_REQUIRED_EVENT_BITS; 8115 } 8116 8117 /* 8118 * Check if any of the offline devices have become ready 8119 */ 8120 static int hpsa_offline_devices_ready(struct ctlr_info *h) 8121 { 8122 unsigned long flags; 8123 struct offline_device_entry *d; 8124 struct list_head *this, *tmp; 8125 8126 spin_lock_irqsave(&h->offline_device_lock, flags); 8127 list_for_each_safe(this, tmp, &h->offline_device_list) { 8128 d = list_entry(this, struct offline_device_entry, 8129 offline_list); 8130 spin_unlock_irqrestore(&h->offline_device_lock, flags); 8131 if (!hpsa_volume_offline(h, d->scsi3addr)) { 8132 spin_lock_irqsave(&h->offline_device_lock, flags); 8133 list_del(&d->offline_list); 8134 spin_unlock_irqrestore(&h->offline_device_lock, flags); 8135 return 1; 8136 } 8137 spin_lock_irqsave(&h->offline_device_lock, flags); 8138 } 8139 spin_unlock_irqrestore(&h->offline_device_lock, flags); 8140 return 0; 8141 } 8142 8143 static int hpsa_luns_changed(struct ctlr_info *h) 8144 { 8145 int rc = 1; /* assume there are changes */ 8146 struct ReportLUNdata *logdev = NULL; 8147 8148 /* if we can't find out if lun data has changed, 8149 * assume that it has. 8150 */ 8151 8152 if (!h->lastlogicals) 8153 return rc; 8154 8155 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL); 8156 if (!logdev) 8157 return rc; 8158 8159 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) { 8160 dev_warn(&h->pdev->dev, 8161 "report luns failed, can't track lun changes.\n"); 8162 goto out; 8163 } 8164 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) { 8165 dev_info(&h->pdev->dev, 8166 "Lun changes detected.\n"); 8167 memcpy(h->lastlogicals, logdev, sizeof(*logdev)); 8168 goto out; 8169 } else 8170 rc = 0; /* no changes detected. */ 8171 out: 8172 kfree(logdev); 8173 return rc; 8174 } 8175 8176 static void hpsa_perform_rescan(struct ctlr_info *h) 8177 { 8178 struct Scsi_Host *sh = NULL; 8179 unsigned long flags; 8180 8181 /* 8182 * Do the scan after the reset 8183 */ 8184 spin_lock_irqsave(&h->reset_lock, flags); 8185 if (h->reset_in_progress) { 8186 h->drv_req_rescan = 1; 8187 spin_unlock_irqrestore(&h->reset_lock, flags); 8188 return; 8189 } 8190 spin_unlock_irqrestore(&h->reset_lock, flags); 8191 8192 sh = scsi_host_get(h->scsi_host); 8193 if (sh != NULL) { 8194 hpsa_scan_start(sh); 8195 scsi_host_put(sh); 8196 h->drv_req_rescan = 0; 8197 } 8198 } 8199 8200 /* 8201 * watch for controller events 8202 */ 8203 static void hpsa_event_monitor_worker(struct work_struct *work) 8204 { 8205 struct ctlr_info *h = container_of(to_delayed_work(work), 8206 struct ctlr_info, event_monitor_work); 8207 unsigned long flags; 8208 8209 spin_lock_irqsave(&h->lock, flags); 8210 if (h->remove_in_progress) { 8211 spin_unlock_irqrestore(&h->lock, flags); 8212 return; 8213 } 8214 spin_unlock_irqrestore(&h->lock, flags); 8215 8216 if (hpsa_ctlr_needs_rescan(h)) { 8217 hpsa_ack_ctlr_events(h); 8218 hpsa_perform_rescan(h); 8219 } 8220 8221 spin_lock_irqsave(&h->lock, flags); 8222 if (!h->remove_in_progress) 8223 schedule_delayed_work(&h->event_monitor_work, 8224 HPSA_EVENT_MONITOR_INTERVAL); 8225 spin_unlock_irqrestore(&h->lock, flags); 8226 } 8227 8228 static void hpsa_rescan_ctlr_worker(struct work_struct *work) 8229 { 8230 unsigned long flags; 8231 struct ctlr_info *h = container_of(to_delayed_work(work), 8232 struct ctlr_info, rescan_ctlr_work); 8233 8234 spin_lock_irqsave(&h->lock, flags); 8235 if (h->remove_in_progress) { 8236 spin_unlock_irqrestore(&h->lock, flags); 8237 return; 8238 } 8239 spin_unlock_irqrestore(&h->lock, flags); 8240 8241 if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) { 8242 hpsa_perform_rescan(h); 8243 } else if (h->discovery_polling) { 8244 hpsa_disable_rld_caching(h); 8245 if (hpsa_luns_changed(h)) { 8246 dev_info(&h->pdev->dev, 8247 "driver discovery polling rescan.\n"); 8248 hpsa_perform_rescan(h); 8249 } 8250 } 8251 spin_lock_irqsave(&h->lock, flags); 8252 if (!h->remove_in_progress) 8253 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, 8254 h->heartbeat_sample_interval); 8255 spin_unlock_irqrestore(&h->lock, flags); 8256 } 8257 8258 static void hpsa_monitor_ctlr_worker(struct work_struct *work) 8259 { 8260 unsigned long flags; 8261 struct ctlr_info *h = container_of(to_delayed_work(work), 8262 struct ctlr_info, monitor_ctlr_work); 8263 8264 detect_controller_lockup(h); 8265 if (lockup_detected(h)) 8266 return; 8267 8268 spin_lock_irqsave(&h->lock, flags); 8269 if (!h->remove_in_progress) 8270 schedule_delayed_work(&h->monitor_ctlr_work, 8271 h->heartbeat_sample_interval); 8272 spin_unlock_irqrestore(&h->lock, flags); 8273 } 8274 8275 static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h, 8276 char *name) 8277 { 8278 struct workqueue_struct *wq = NULL; 8279 8280 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr); 8281 if (!wq) 8282 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name); 8283 8284 return wq; 8285 } 8286 8287 static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 8288 { 8289 int dac, rc; 8290 struct ctlr_info *h; 8291 int try_soft_reset = 0; 8292 unsigned long flags; 8293 u32 board_id; 8294 8295 if (number_of_controllers == 0) 8296 printk(KERN_INFO DRIVER_NAME "\n"); 8297 8298 rc = hpsa_lookup_board_id(pdev, &board_id, NULL); 8299 if (rc < 0) { 8300 dev_warn(&pdev->dev, "Board ID not found\n"); 8301 return rc; 8302 } 8303 8304 rc = hpsa_init_reset_devices(pdev, board_id); 8305 if (rc) { 8306 if (rc != -ENOTSUPP) 8307 return rc; 8308 /* If the reset fails in a particular way (it has no way to do 8309 * a proper hard reset, so returns -ENOTSUPP) we can try to do 8310 * a soft reset once we get the controller configured up to the 8311 * point that it can accept a command. 8312 */ 8313 try_soft_reset = 1; 8314 rc = 0; 8315 } 8316 8317 reinit_after_soft_reset: 8318 8319 /* Command structures must be aligned on a 32-byte boundary because 8320 * the 5 lower bits of the address are used by the hardware. and by 8321 * the driver. See comments in hpsa.h for more info. 8322 */ 8323 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); 8324 h = kzalloc(sizeof(*h), GFP_KERNEL); 8325 if (!h) { 8326 dev_err(&pdev->dev, "Failed to allocate controller head\n"); 8327 return -ENOMEM; 8328 } 8329 8330 h->pdev = pdev; 8331 8332 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; 8333 INIT_LIST_HEAD(&h->offline_device_list); 8334 spin_lock_init(&h->lock); 8335 spin_lock_init(&h->offline_device_lock); 8336 spin_lock_init(&h->scan_lock); 8337 spin_lock_init(&h->reset_lock); 8338 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); 8339 8340 /* Allocate and clear per-cpu variable lockup_detected */ 8341 h->lockup_detected = alloc_percpu(u32); 8342 if (!h->lockup_detected) { 8343 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n"); 8344 rc = -ENOMEM; 8345 goto clean1; /* aer/h */ 8346 } 8347 set_lockup_detected_for_all_cpus(h, 0); 8348 8349 rc = hpsa_pci_init(h); 8350 if (rc) 8351 goto clean2; /* lu, aer/h */ 8352 8353 /* relies on h-> settings made by hpsa_pci_init, including 8354 * interrupt_mode h->intr */ 8355 rc = hpsa_scsi_host_alloc(h); 8356 if (rc) 8357 goto clean2_5; /* pci, lu, aer/h */ 8358 8359 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no); 8360 h->ctlr = number_of_controllers; 8361 number_of_controllers++; 8362 8363 /* configure PCI DMA stuff */ 8364 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 8365 if (rc == 0) { 8366 dac = 1; 8367 } else { 8368 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 8369 if (rc == 0) { 8370 dac = 0; 8371 } else { 8372 dev_err(&pdev->dev, "no suitable DMA available\n"); 8373 goto clean3; /* shost, pci, lu, aer/h */ 8374 } 8375 } 8376 8377 /* make sure the board interrupts are off */ 8378 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8379 8380 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx); 8381 if (rc) 8382 goto clean3; /* shost, pci, lu, aer/h */ 8383 rc = hpsa_alloc_cmd_pool(h); 8384 if (rc) 8385 goto clean4; /* irq, shost, pci, lu, aer/h */ 8386 rc = hpsa_alloc_sg_chain_blocks(h); 8387 if (rc) 8388 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */ 8389 init_waitqueue_head(&h->scan_wait_queue); 8390 init_waitqueue_head(&h->event_sync_wait_queue); 8391 mutex_init(&h->reset_mutex); 8392 h->scan_finished = 1; /* no scan currently in progress */ 8393 h->scan_waiting = 0; 8394 8395 pci_set_drvdata(pdev, h); 8396 h->ndevices = 0; 8397 8398 spin_lock_init(&h->devlock); 8399 rc = hpsa_put_ctlr_into_performant_mode(h); 8400 if (rc) 8401 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */ 8402 8403 /* create the resubmit workqueue */ 8404 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan"); 8405 if (!h->rescan_ctlr_wq) { 8406 rc = -ENOMEM; 8407 goto clean7; 8408 } 8409 8410 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit"); 8411 if (!h->resubmit_wq) { 8412 rc = -ENOMEM; 8413 goto clean7; /* aer/h */ 8414 } 8415 8416 /* 8417 * At this point, the controller is ready to take commands. 8418 * Now, if reset_devices and the hard reset didn't work, try 8419 * the soft reset and see if that works. 8420 */ 8421 if (try_soft_reset) { 8422 8423 /* This is kind of gross. We may or may not get a completion 8424 * from the soft reset command, and if we do, then the value 8425 * from the fifo may or may not be valid. So, we wait 10 secs 8426 * after the reset throwing away any completions we get during 8427 * that time. Unregister the interrupt handler and register 8428 * fake ones to scoop up any residual completions. 8429 */ 8430 spin_lock_irqsave(&h->lock, flags); 8431 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8432 spin_unlock_irqrestore(&h->lock, flags); 8433 hpsa_free_irqs(h); 8434 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, 8435 hpsa_intx_discard_completions); 8436 if (rc) { 8437 dev_warn(&h->pdev->dev, 8438 "Failed to request_irq after soft reset.\n"); 8439 /* 8440 * cannot goto clean7 or free_irqs will be called 8441 * again. Instead, do its work 8442 */ 8443 hpsa_free_performant_mode(h); /* clean7 */ 8444 hpsa_free_sg_chain_blocks(h); /* clean6 */ 8445 hpsa_free_cmd_pool(h); /* clean5 */ 8446 /* 8447 * skip hpsa_free_irqs(h) clean4 since that 8448 * was just called before request_irqs failed 8449 */ 8450 goto clean3; 8451 } 8452 8453 rc = hpsa_kdump_soft_reset(h); 8454 if (rc) 8455 /* Neither hard nor soft reset worked, we're hosed. */ 8456 goto clean7; 8457 8458 dev_info(&h->pdev->dev, "Board READY.\n"); 8459 dev_info(&h->pdev->dev, 8460 "Waiting for stale completions to drain.\n"); 8461 h->access.set_intr_mask(h, HPSA_INTR_ON); 8462 msleep(10000); 8463 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8464 8465 rc = controller_reset_failed(h->cfgtable); 8466 if (rc) 8467 dev_info(&h->pdev->dev, 8468 "Soft reset appears to have failed.\n"); 8469 8470 /* since the controller's reset, we have to go back and re-init 8471 * everything. Easiest to just forget what we've done and do it 8472 * all over again. 8473 */ 8474 hpsa_undo_allocations_after_kdump_soft_reset(h); 8475 try_soft_reset = 0; 8476 if (rc) 8477 /* don't goto clean, we already unallocated */ 8478 return -ENODEV; 8479 8480 goto reinit_after_soft_reset; 8481 } 8482 8483 /* Enable Accelerated IO path at driver layer */ 8484 h->acciopath_status = 1; 8485 /* Disable discovery polling.*/ 8486 h->discovery_polling = 0; 8487 8488 8489 /* Turn the interrupts on so we can service requests */ 8490 h->access.set_intr_mask(h, HPSA_INTR_ON); 8491 8492 hpsa_hba_inquiry(h); 8493 8494 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL); 8495 if (!h->lastlogicals) 8496 dev_info(&h->pdev->dev, 8497 "Can't track change to report lun data\n"); 8498 8499 /* hook into SCSI subsystem */ 8500 rc = hpsa_scsi_add_host(h); 8501 if (rc) 8502 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8503 8504 /* Monitor the controller for firmware lockups */ 8505 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; 8506 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); 8507 schedule_delayed_work(&h->monitor_ctlr_work, 8508 h->heartbeat_sample_interval); 8509 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker); 8510 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, 8511 h->heartbeat_sample_interval); 8512 INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker); 8513 schedule_delayed_work(&h->event_monitor_work, 8514 HPSA_EVENT_MONITOR_INTERVAL); 8515 return 0; 8516 8517 clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ 8518 hpsa_free_performant_mode(h); 8519 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8520 clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */ 8521 hpsa_free_sg_chain_blocks(h); 8522 clean5: /* cmd, irq, shost, pci, lu, aer/h */ 8523 hpsa_free_cmd_pool(h); 8524 clean4: /* irq, shost, pci, lu, aer/h */ 8525 hpsa_free_irqs(h); 8526 clean3: /* shost, pci, lu, aer/h */ 8527 scsi_host_put(h->scsi_host); 8528 h->scsi_host = NULL; 8529 clean2_5: /* pci, lu, aer/h */ 8530 hpsa_free_pci_init(h); 8531 clean2: /* lu, aer/h */ 8532 if (h->lockup_detected) { 8533 free_percpu(h->lockup_detected); 8534 h->lockup_detected = NULL; 8535 } 8536 clean1: /* wq/aer/h */ 8537 if (h->resubmit_wq) { 8538 destroy_workqueue(h->resubmit_wq); 8539 h->resubmit_wq = NULL; 8540 } 8541 if (h->rescan_ctlr_wq) { 8542 destroy_workqueue(h->rescan_ctlr_wq); 8543 h->rescan_ctlr_wq = NULL; 8544 } 8545 kfree(h); 8546 return rc; 8547 } 8548 8549 static void hpsa_flush_cache(struct ctlr_info *h) 8550 { 8551 char *flush_buf; 8552 struct CommandList *c; 8553 int rc; 8554 8555 if (unlikely(lockup_detected(h))) 8556 return; 8557 flush_buf = kzalloc(4, GFP_KERNEL); 8558 if (!flush_buf) 8559 return; 8560 8561 c = cmd_alloc(h); 8562 8563 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, 8564 RAID_CTLR_LUNID, TYPE_CMD)) { 8565 goto out; 8566 } 8567 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8568 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT); 8569 if (rc) 8570 goto out; 8571 if (c->err_info->CommandStatus != 0) 8572 out: 8573 dev_warn(&h->pdev->dev, 8574 "error flushing cache on controller\n"); 8575 cmd_free(h, c); 8576 kfree(flush_buf); 8577 } 8578 8579 /* Make controller gather fresh report lun data each time we 8580 * send down a report luns request 8581 */ 8582 static void hpsa_disable_rld_caching(struct ctlr_info *h) 8583 { 8584 u32 *options; 8585 struct CommandList *c; 8586 int rc; 8587 8588 /* Don't bother trying to set diag options if locked up */ 8589 if (unlikely(h->lockup_detected)) 8590 return; 8591 8592 options = kzalloc(sizeof(*options), GFP_KERNEL); 8593 if (!options) 8594 return; 8595 8596 c = cmd_alloc(h); 8597 8598 /* first, get the current diag options settings */ 8599 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, 8600 RAID_CTLR_LUNID, TYPE_CMD)) 8601 goto errout; 8602 8603 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8604 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 8605 if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8606 goto errout; 8607 8608 /* Now, set the bit for disabling the RLD caching */ 8609 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING; 8610 8611 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0, 8612 RAID_CTLR_LUNID, TYPE_CMD)) 8613 goto errout; 8614 8615 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8616 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT); 8617 if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8618 goto errout; 8619 8620 /* Now verify that it got set: */ 8621 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, 8622 RAID_CTLR_LUNID, TYPE_CMD)) 8623 goto errout; 8624 8625 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, 8626 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); 8627 if ((rc != 0) || (c->err_info->CommandStatus != 0)) 8628 goto errout; 8629 8630 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING) 8631 goto out; 8632 8633 errout: 8634 dev_err(&h->pdev->dev, 8635 "Error: failed to disable report lun data caching.\n"); 8636 out: 8637 cmd_free(h, c); 8638 kfree(options); 8639 } 8640 8641 static void hpsa_shutdown(struct pci_dev *pdev) 8642 { 8643 struct ctlr_info *h; 8644 8645 h = pci_get_drvdata(pdev); 8646 /* Turn board interrupts off and send the flush cache command 8647 * sendcmd will turn off interrupt, and send the flush... 8648 * To write all data in the battery backed cache to disks 8649 */ 8650 hpsa_flush_cache(h); 8651 h->access.set_intr_mask(h, HPSA_INTR_OFF); 8652 hpsa_free_irqs(h); /* init_one 4 */ 8653 hpsa_disable_interrupt_mode(h); /* pci_init 2 */ 8654 } 8655 8656 static void hpsa_free_device_info(struct ctlr_info *h) 8657 { 8658 int i; 8659 8660 for (i = 0; i < h->ndevices; i++) { 8661 kfree(h->dev[i]); 8662 h->dev[i] = NULL; 8663 } 8664 } 8665 8666 static void hpsa_remove_one(struct pci_dev *pdev) 8667 { 8668 struct ctlr_info *h; 8669 unsigned long flags; 8670 8671 if (pci_get_drvdata(pdev) == NULL) { 8672 dev_err(&pdev->dev, "unable to remove device\n"); 8673 return; 8674 } 8675 h = pci_get_drvdata(pdev); 8676 8677 /* Get rid of any controller monitoring work items */ 8678 spin_lock_irqsave(&h->lock, flags); 8679 h->remove_in_progress = 1; 8680 spin_unlock_irqrestore(&h->lock, flags); 8681 cancel_delayed_work_sync(&h->monitor_ctlr_work); 8682 cancel_delayed_work_sync(&h->rescan_ctlr_work); 8683 cancel_delayed_work_sync(&h->event_monitor_work); 8684 destroy_workqueue(h->rescan_ctlr_wq); 8685 destroy_workqueue(h->resubmit_wq); 8686 8687 /* 8688 * Call before disabling interrupts. 8689 * scsi_remove_host can trigger I/O operations especially 8690 * when multipath is enabled. There can be SYNCHRONIZE CACHE 8691 * operations which cannot complete and will hang the system. 8692 */ 8693 if (h->scsi_host) 8694 scsi_remove_host(h->scsi_host); /* init_one 8 */ 8695 /* includes hpsa_free_irqs - init_one 4 */ 8696 /* includes hpsa_disable_interrupt_mode - pci_init 2 */ 8697 hpsa_shutdown(pdev); 8698 8699 hpsa_free_device_info(h); /* scan */ 8700 8701 kfree(h->hba_inquiry_data); /* init_one 10 */ 8702 h->hba_inquiry_data = NULL; /* init_one 10 */ 8703 hpsa_free_ioaccel2_sg_chain_blocks(h); 8704 hpsa_free_performant_mode(h); /* init_one 7 */ 8705 hpsa_free_sg_chain_blocks(h); /* init_one 6 */ 8706 hpsa_free_cmd_pool(h); /* init_one 5 */ 8707 kfree(h->lastlogicals); 8708 8709 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */ 8710 8711 scsi_host_put(h->scsi_host); /* init_one 3 */ 8712 h->scsi_host = NULL; /* init_one 3 */ 8713 8714 /* includes hpsa_disable_interrupt_mode - pci_init 2 */ 8715 hpsa_free_pci_init(h); /* init_one 2.5 */ 8716 8717 free_percpu(h->lockup_detected); /* init_one 2 */ 8718 h->lockup_detected = NULL; /* init_one 2 */ 8719 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */ 8720 8721 hpsa_delete_sas_host(h); 8722 8723 kfree(h); /* init_one 1 */ 8724 } 8725 8726 static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, 8727 __attribute__((unused)) pm_message_t state) 8728 { 8729 return -ENOSYS; 8730 } 8731 8732 static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) 8733 { 8734 return -ENOSYS; 8735 } 8736 8737 static struct pci_driver hpsa_pci_driver = { 8738 .name = HPSA, 8739 .probe = hpsa_init_one, 8740 .remove = hpsa_remove_one, 8741 .id_table = hpsa_pci_device_id, /* id_table */ 8742 .shutdown = hpsa_shutdown, 8743 .suspend = hpsa_suspend, 8744 .resume = hpsa_resume, 8745 }; 8746 8747 /* Fill in bucket_map[], given nsgs (the max number of 8748 * scatter gather elements supported) and bucket[], 8749 * which is an array of 8 integers. The bucket[] array 8750 * contains 8 different DMA transfer sizes (in 16 8751 * byte increments) which the controller uses to fetch 8752 * commands. This function fills in bucket_map[], which 8753 * maps a given number of scatter gather elements to one of 8754 * the 8 DMA transfer sizes. The point of it is to allow the 8755 * controller to only do as much DMA as needed to fetch the 8756 * command, with the DMA transfer size encoded in the lower 8757 * bits of the command address. 8758 */ 8759 static void calc_bucket_map(int bucket[], int num_buckets, 8760 int nsgs, int min_blocks, u32 *bucket_map) 8761 { 8762 int i, j, b, size; 8763 8764 /* Note, bucket_map must have nsgs+1 entries. */ 8765 for (i = 0; i <= nsgs; i++) { 8766 /* Compute size of a command with i SG entries */ 8767 size = i + min_blocks; 8768 b = num_buckets; /* Assume the biggest bucket */ 8769 /* Find the bucket that is just big enough */ 8770 for (j = 0; j < num_buckets; j++) { 8771 if (bucket[j] >= size) { 8772 b = j; 8773 break; 8774 } 8775 } 8776 /* for a command with i SG entries, use bucket b. */ 8777 bucket_map[i] = b; 8778 } 8779 } 8780 8781 /* 8782 * return -ENODEV on err, 0 on success (or no action) 8783 * allocates numerous items that must be freed later 8784 */ 8785 static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) 8786 { 8787 int i; 8788 unsigned long register_value; 8789 unsigned long transMethod = CFGTBL_Trans_Performant | 8790 (trans_support & CFGTBL_Trans_use_short_tags) | 8791 CFGTBL_Trans_enable_directed_msix | 8792 (trans_support & (CFGTBL_Trans_io_accel1 | 8793 CFGTBL_Trans_io_accel2)); 8794 struct access_method access = SA5_performant_access; 8795 8796 /* This is a bit complicated. There are 8 registers on 8797 * the controller which we write to to tell it 8 different 8798 * sizes of commands which there may be. It's a way of 8799 * reducing the DMA done to fetch each command. Encoded into 8800 * each command's tag are 3 bits which communicate to the controller 8801 * which of the eight sizes that command fits within. The size of 8802 * each command depends on how many scatter gather entries there are. 8803 * Each SG entry requires 16 bytes. The eight registers are programmed 8804 * with the number of 16-byte blocks a command of that size requires. 8805 * The smallest command possible requires 5 such 16 byte blocks. 8806 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte 8807 * blocks. Note, this only extends to the SG entries contained 8808 * within the command block, and does not extend to chained blocks 8809 * of SG elements. bft[] contains the eight values we write to 8810 * the registers. They are not evenly distributed, but have more 8811 * sizes for small commands, and fewer sizes for larger commands. 8812 */ 8813 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; 8814 #define MIN_IOACCEL2_BFT_ENTRY 5 8815 #define HPSA_IOACCEL2_HEADER_SZ 4 8816 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, 8817 13, 14, 15, 16, 17, 18, 19, 8818 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; 8819 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); 8820 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); 8821 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > 8822 16 * MIN_IOACCEL2_BFT_ENTRY); 8823 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); 8824 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); 8825 /* 5 = 1 s/g entry or 4k 8826 * 6 = 2 s/g entry or 8k 8827 * 8 = 4 s/g entry or 16k 8828 * 10 = 6 s/g entry or 24k 8829 */ 8830 8831 /* If the controller supports either ioaccel method then 8832 * we can also use the RAID stack submit path that does not 8833 * perform the superfluous readl() after each command submission. 8834 */ 8835 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) 8836 access = SA5_performant_access_no_read; 8837 8838 /* Controller spec: zero out this buffer. */ 8839 for (i = 0; i < h->nreply_queues; i++) 8840 memset(h->reply_queue[i].head, 0, h->reply_queue_size); 8841 8842 bft[7] = SG_ENTRIES_IN_CMD + 4; 8843 calc_bucket_map(bft, ARRAY_SIZE(bft), 8844 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); 8845 for (i = 0; i < 8; i++) 8846 writel(bft[i], &h->transtable->BlockFetch[i]); 8847 8848 /* size of controller ring buffer */ 8849 writel(h->max_commands, &h->transtable->RepQSize); 8850 writel(h->nreply_queues, &h->transtable->RepQCount); 8851 writel(0, &h->transtable->RepQCtrAddrLow32); 8852 writel(0, &h->transtable->RepQCtrAddrHigh32); 8853 8854 for (i = 0; i < h->nreply_queues; i++) { 8855 writel(0, &h->transtable->RepQAddr[i].upper); 8856 writel(h->reply_queue[i].busaddr, 8857 &h->transtable->RepQAddr[i].lower); 8858 } 8859 8860 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); 8861 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); 8862 /* 8863 * enable outbound interrupt coalescing in accelerator mode; 8864 */ 8865 if (trans_support & CFGTBL_Trans_io_accel1) { 8866 access = SA5_ioaccel_mode1_access; 8867 writel(10, &h->cfgtable->HostWrite.CoalIntDelay); 8868 writel(4, &h->cfgtable->HostWrite.CoalIntCount); 8869 } else 8870 if (trans_support & CFGTBL_Trans_io_accel2) 8871 access = SA5_ioaccel_mode2_access; 8872 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 8873 if (hpsa_wait_for_mode_change_ack(h)) { 8874 dev_err(&h->pdev->dev, 8875 "performant mode problem - doorbell timeout\n"); 8876 return -ENODEV; 8877 } 8878 register_value = readl(&(h->cfgtable->TransportActive)); 8879 if (!(register_value & CFGTBL_Trans_Performant)) { 8880 dev_err(&h->pdev->dev, 8881 "performant mode problem - transport not active\n"); 8882 return -ENODEV; 8883 } 8884 /* Change the access methods to the performant access methods */ 8885 h->access = access; 8886 h->transMethod = transMethod; 8887 8888 if (!((trans_support & CFGTBL_Trans_io_accel1) || 8889 (trans_support & CFGTBL_Trans_io_accel2))) 8890 return 0; 8891 8892 if (trans_support & CFGTBL_Trans_io_accel1) { 8893 /* Set up I/O accelerator mode */ 8894 for (i = 0; i < h->nreply_queues; i++) { 8895 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); 8896 h->reply_queue[i].current_entry = 8897 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); 8898 } 8899 bft[7] = h->ioaccel_maxsg + 8; 8900 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, 8901 h->ioaccel1_blockFetchTable); 8902 8903 /* initialize all reply queue entries to unused */ 8904 for (i = 0; i < h->nreply_queues; i++) 8905 memset(h->reply_queue[i].head, 8906 (u8) IOACCEL_MODE1_REPLY_UNUSED, 8907 h->reply_queue_size); 8908 8909 /* set all the constant fields in the accelerator command 8910 * frames once at init time to save CPU cycles later. 8911 */ 8912 for (i = 0; i < h->nr_cmds; i++) { 8913 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; 8914 8915 cp->function = IOACCEL1_FUNCTION_SCSIIO; 8916 cp->err_info = (u32) (h->errinfo_pool_dhandle + 8917 (i * sizeof(struct ErrorInfo))); 8918 cp->err_info_len = sizeof(struct ErrorInfo); 8919 cp->sgl_offset = IOACCEL1_SGLOFFSET; 8920 cp->host_context_flags = 8921 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); 8922 cp->timeout_sec = 0; 8923 cp->ReplyQueue = 0; 8924 cp->tag = 8925 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); 8926 cp->host_addr = 8927 cpu_to_le64(h->ioaccel_cmd_pool_dhandle + 8928 (i * sizeof(struct io_accel1_cmd))); 8929 } 8930 } else if (trans_support & CFGTBL_Trans_io_accel2) { 8931 u64 cfg_offset, cfg_base_addr_index; 8932 u32 bft2_offset, cfg_base_addr; 8933 int rc; 8934 8935 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, 8936 &cfg_base_addr_index, &cfg_offset); 8937 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); 8938 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; 8939 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, 8940 4, h->ioaccel2_blockFetchTable); 8941 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); 8942 BUILD_BUG_ON(offsetof(struct CfgTable, 8943 io_accel_request_size_offset) != 0xb8); 8944 h->ioaccel2_bft2_regs = 8945 remap_pci_mem(pci_resource_start(h->pdev, 8946 cfg_base_addr_index) + 8947 cfg_offset + bft2_offset, 8948 ARRAY_SIZE(bft2) * 8949 sizeof(*h->ioaccel2_bft2_regs)); 8950 for (i = 0; i < ARRAY_SIZE(bft2); i++) 8951 writel(bft2[i], &h->ioaccel2_bft2_regs[i]); 8952 } 8953 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); 8954 if (hpsa_wait_for_mode_change_ack(h)) { 8955 dev_err(&h->pdev->dev, 8956 "performant mode problem - enabling ioaccel mode\n"); 8957 return -ENODEV; 8958 } 8959 return 0; 8960 } 8961 8962 /* Free ioaccel1 mode command blocks and block fetch table */ 8963 static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h) 8964 { 8965 if (h->ioaccel_cmd_pool) { 8966 pci_free_consistent(h->pdev, 8967 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), 8968 h->ioaccel_cmd_pool, 8969 h->ioaccel_cmd_pool_dhandle); 8970 h->ioaccel_cmd_pool = NULL; 8971 h->ioaccel_cmd_pool_dhandle = 0; 8972 } 8973 kfree(h->ioaccel1_blockFetchTable); 8974 h->ioaccel1_blockFetchTable = NULL; 8975 } 8976 8977 /* Allocate ioaccel1 mode command blocks and block fetch table */ 8978 static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h) 8979 { 8980 h->ioaccel_maxsg = 8981 readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); 8982 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) 8983 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; 8984 8985 /* Command structures must be aligned on a 128-byte boundary 8986 * because the 7 lower bits of the address are used by the 8987 * hardware. 8988 */ 8989 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % 8990 IOACCEL1_COMMANDLIST_ALIGNMENT); 8991 h->ioaccel_cmd_pool = 8992 pci_alloc_consistent(h->pdev, 8993 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), 8994 &(h->ioaccel_cmd_pool_dhandle)); 8995 8996 h->ioaccel1_blockFetchTable = 8997 kmalloc(((h->ioaccel_maxsg + 1) * 8998 sizeof(u32)), GFP_KERNEL); 8999 9000 if ((h->ioaccel_cmd_pool == NULL) || 9001 (h->ioaccel1_blockFetchTable == NULL)) 9002 goto clean_up; 9003 9004 memset(h->ioaccel_cmd_pool, 0, 9005 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); 9006 return 0; 9007 9008 clean_up: 9009 hpsa_free_ioaccel1_cmd_and_bft(h); 9010 return -ENOMEM; 9011 } 9012 9013 /* Free ioaccel2 mode command blocks and block fetch table */ 9014 static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h) 9015 { 9016 hpsa_free_ioaccel2_sg_chain_blocks(h); 9017 9018 if (h->ioaccel2_cmd_pool) { 9019 pci_free_consistent(h->pdev, 9020 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), 9021 h->ioaccel2_cmd_pool, 9022 h->ioaccel2_cmd_pool_dhandle); 9023 h->ioaccel2_cmd_pool = NULL; 9024 h->ioaccel2_cmd_pool_dhandle = 0; 9025 } 9026 kfree(h->ioaccel2_blockFetchTable); 9027 h->ioaccel2_blockFetchTable = NULL; 9028 } 9029 9030 /* Allocate ioaccel2 mode command blocks and block fetch table */ 9031 static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h) 9032 { 9033 int rc; 9034 9035 /* Allocate ioaccel2 mode command blocks and block fetch table */ 9036 9037 h->ioaccel_maxsg = 9038 readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); 9039 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) 9040 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; 9041 9042 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % 9043 IOACCEL2_COMMANDLIST_ALIGNMENT); 9044 h->ioaccel2_cmd_pool = 9045 pci_alloc_consistent(h->pdev, 9046 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), 9047 &(h->ioaccel2_cmd_pool_dhandle)); 9048 9049 h->ioaccel2_blockFetchTable = 9050 kmalloc(((h->ioaccel_maxsg + 1) * 9051 sizeof(u32)), GFP_KERNEL); 9052 9053 if ((h->ioaccel2_cmd_pool == NULL) || 9054 (h->ioaccel2_blockFetchTable == NULL)) { 9055 rc = -ENOMEM; 9056 goto clean_up; 9057 } 9058 9059 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h); 9060 if (rc) 9061 goto clean_up; 9062 9063 memset(h->ioaccel2_cmd_pool, 0, 9064 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); 9065 return 0; 9066 9067 clean_up: 9068 hpsa_free_ioaccel2_cmd_and_bft(h); 9069 return rc; 9070 } 9071 9072 /* Free items allocated by hpsa_put_ctlr_into_performant_mode */ 9073 static void hpsa_free_performant_mode(struct ctlr_info *h) 9074 { 9075 kfree(h->blockFetchTable); 9076 h->blockFetchTable = NULL; 9077 hpsa_free_reply_queues(h); 9078 hpsa_free_ioaccel1_cmd_and_bft(h); 9079 hpsa_free_ioaccel2_cmd_and_bft(h); 9080 } 9081 9082 /* return -ENODEV on error, 0 on success (or no action) 9083 * allocates numerous items that must be freed later 9084 */ 9085 static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) 9086 { 9087 u32 trans_support; 9088 unsigned long transMethod = CFGTBL_Trans_Performant | 9089 CFGTBL_Trans_use_short_tags; 9090 int i, rc; 9091 9092 if (hpsa_simple_mode) 9093 return 0; 9094 9095 trans_support = readl(&(h->cfgtable->TransportSupport)); 9096 if (!(trans_support & PERFORMANT_MODE)) 9097 return 0; 9098 9099 /* Check for I/O accelerator mode support */ 9100 if (trans_support & CFGTBL_Trans_io_accel1) { 9101 transMethod |= CFGTBL_Trans_io_accel1 | 9102 CFGTBL_Trans_enable_directed_msix; 9103 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h); 9104 if (rc) 9105 return rc; 9106 } else if (trans_support & CFGTBL_Trans_io_accel2) { 9107 transMethod |= CFGTBL_Trans_io_accel2 | 9108 CFGTBL_Trans_enable_directed_msix; 9109 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h); 9110 if (rc) 9111 return rc; 9112 } 9113 9114 h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1; 9115 hpsa_get_max_perf_mode_cmds(h); 9116 /* Performant mode ring buffer and supporting data structures */ 9117 h->reply_queue_size = h->max_commands * sizeof(u64); 9118 9119 for (i = 0; i < h->nreply_queues; i++) { 9120 h->reply_queue[i].head = pci_alloc_consistent(h->pdev, 9121 h->reply_queue_size, 9122 &(h->reply_queue[i].busaddr)); 9123 if (!h->reply_queue[i].head) { 9124 rc = -ENOMEM; 9125 goto clean1; /* rq, ioaccel */ 9126 } 9127 h->reply_queue[i].size = h->max_commands; 9128 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ 9129 h->reply_queue[i].current_entry = 0; 9130 } 9131 9132 /* Need a block fetch table for performant mode */ 9133 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * 9134 sizeof(u32)), GFP_KERNEL); 9135 if (!h->blockFetchTable) { 9136 rc = -ENOMEM; 9137 goto clean1; /* rq, ioaccel */ 9138 } 9139 9140 rc = hpsa_enter_performant_mode(h, trans_support); 9141 if (rc) 9142 goto clean2; /* bft, rq, ioaccel */ 9143 return 0; 9144 9145 clean2: /* bft, rq, ioaccel */ 9146 kfree(h->blockFetchTable); 9147 h->blockFetchTable = NULL; 9148 clean1: /* rq, ioaccel */ 9149 hpsa_free_reply_queues(h); 9150 hpsa_free_ioaccel1_cmd_and_bft(h); 9151 hpsa_free_ioaccel2_cmd_and_bft(h); 9152 return rc; 9153 } 9154 9155 static int is_accelerated_cmd(struct CommandList *c) 9156 { 9157 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; 9158 } 9159 9160 static void hpsa_drain_accel_commands(struct ctlr_info *h) 9161 { 9162 struct CommandList *c = NULL; 9163 int i, accel_cmds_out; 9164 int refcount; 9165 9166 do { /* wait for all outstanding ioaccel commands to drain out */ 9167 accel_cmds_out = 0; 9168 for (i = 0; i < h->nr_cmds; i++) { 9169 c = h->cmd_pool + i; 9170 refcount = atomic_inc_return(&c->refcount); 9171 if (refcount > 1) /* Command is allocated */ 9172 accel_cmds_out += is_accelerated_cmd(c); 9173 cmd_free(h, c); 9174 } 9175 if (accel_cmds_out <= 0) 9176 break; 9177 msleep(100); 9178 } while (1); 9179 } 9180 9181 static struct hpsa_sas_phy *hpsa_alloc_sas_phy( 9182 struct hpsa_sas_port *hpsa_sas_port) 9183 { 9184 struct hpsa_sas_phy *hpsa_sas_phy; 9185 struct sas_phy *phy; 9186 9187 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL); 9188 if (!hpsa_sas_phy) 9189 return NULL; 9190 9191 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev, 9192 hpsa_sas_port->next_phy_index); 9193 if (!phy) { 9194 kfree(hpsa_sas_phy); 9195 return NULL; 9196 } 9197 9198 hpsa_sas_port->next_phy_index++; 9199 hpsa_sas_phy->phy = phy; 9200 hpsa_sas_phy->parent_port = hpsa_sas_port; 9201 9202 return hpsa_sas_phy; 9203 } 9204 9205 static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy) 9206 { 9207 struct sas_phy *phy = hpsa_sas_phy->phy; 9208 9209 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy); 9210 sas_phy_free(phy); 9211 if (hpsa_sas_phy->added_to_port) 9212 list_del(&hpsa_sas_phy->phy_list_entry); 9213 kfree(hpsa_sas_phy); 9214 } 9215 9216 static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy) 9217 { 9218 int rc; 9219 struct hpsa_sas_port *hpsa_sas_port; 9220 struct sas_phy *phy; 9221 struct sas_identify *identify; 9222 9223 hpsa_sas_port = hpsa_sas_phy->parent_port; 9224 phy = hpsa_sas_phy->phy; 9225 9226 identify = &phy->identify; 9227 memset(identify, 0, sizeof(*identify)); 9228 identify->sas_address = hpsa_sas_port->sas_address; 9229 identify->device_type = SAS_END_DEVICE; 9230 identify->initiator_port_protocols = SAS_PROTOCOL_STP; 9231 identify->target_port_protocols = SAS_PROTOCOL_STP; 9232 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; 9233 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; 9234 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN; 9235 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN; 9236 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN; 9237 9238 rc = sas_phy_add(hpsa_sas_phy->phy); 9239 if (rc) 9240 return rc; 9241 9242 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy); 9243 list_add_tail(&hpsa_sas_phy->phy_list_entry, 9244 &hpsa_sas_port->phy_list_head); 9245 hpsa_sas_phy->added_to_port = true; 9246 9247 return 0; 9248 } 9249 9250 static int 9251 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port, 9252 struct sas_rphy *rphy) 9253 { 9254 struct sas_identify *identify; 9255 9256 identify = &rphy->identify; 9257 identify->sas_address = hpsa_sas_port->sas_address; 9258 identify->initiator_port_protocols = SAS_PROTOCOL_STP; 9259 identify->target_port_protocols = SAS_PROTOCOL_STP; 9260 9261 return sas_rphy_add(rphy); 9262 } 9263 9264 static struct hpsa_sas_port 9265 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node, 9266 u64 sas_address) 9267 { 9268 int rc; 9269 struct hpsa_sas_port *hpsa_sas_port; 9270 struct sas_port *port; 9271 9272 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL); 9273 if (!hpsa_sas_port) 9274 return NULL; 9275 9276 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head); 9277 hpsa_sas_port->parent_node = hpsa_sas_node; 9278 9279 port = sas_port_alloc_num(hpsa_sas_node->parent_dev); 9280 if (!port) 9281 goto free_hpsa_port; 9282 9283 rc = sas_port_add(port); 9284 if (rc) 9285 goto free_sas_port; 9286 9287 hpsa_sas_port->port = port; 9288 hpsa_sas_port->sas_address = sas_address; 9289 list_add_tail(&hpsa_sas_port->port_list_entry, 9290 &hpsa_sas_node->port_list_head); 9291 9292 return hpsa_sas_port; 9293 9294 free_sas_port: 9295 sas_port_free(port); 9296 free_hpsa_port: 9297 kfree(hpsa_sas_port); 9298 9299 return NULL; 9300 } 9301 9302 static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port) 9303 { 9304 struct hpsa_sas_phy *hpsa_sas_phy; 9305 struct hpsa_sas_phy *next; 9306 9307 list_for_each_entry_safe(hpsa_sas_phy, next, 9308 &hpsa_sas_port->phy_list_head, phy_list_entry) 9309 hpsa_free_sas_phy(hpsa_sas_phy); 9310 9311 sas_port_delete(hpsa_sas_port->port); 9312 list_del(&hpsa_sas_port->port_list_entry); 9313 kfree(hpsa_sas_port); 9314 } 9315 9316 static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev) 9317 { 9318 struct hpsa_sas_node *hpsa_sas_node; 9319 9320 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL); 9321 if (hpsa_sas_node) { 9322 hpsa_sas_node->parent_dev = parent_dev; 9323 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head); 9324 } 9325 9326 return hpsa_sas_node; 9327 } 9328 9329 static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node) 9330 { 9331 struct hpsa_sas_port *hpsa_sas_port; 9332 struct hpsa_sas_port *next; 9333 9334 if (!hpsa_sas_node) 9335 return; 9336 9337 list_for_each_entry_safe(hpsa_sas_port, next, 9338 &hpsa_sas_node->port_list_head, port_list_entry) 9339 hpsa_free_sas_port(hpsa_sas_port); 9340 9341 kfree(hpsa_sas_node); 9342 } 9343 9344 static struct hpsa_scsi_dev_t 9345 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, 9346 struct sas_rphy *rphy) 9347 { 9348 int i; 9349 struct hpsa_scsi_dev_t *device; 9350 9351 for (i = 0; i < h->ndevices; i++) { 9352 device = h->dev[i]; 9353 if (!device->sas_port) 9354 continue; 9355 if (device->sas_port->rphy == rphy) 9356 return device; 9357 } 9358 9359 return NULL; 9360 } 9361 9362 static int hpsa_add_sas_host(struct ctlr_info *h) 9363 { 9364 int rc; 9365 struct device *parent_dev; 9366 struct hpsa_sas_node *hpsa_sas_node; 9367 struct hpsa_sas_port *hpsa_sas_port; 9368 struct hpsa_sas_phy *hpsa_sas_phy; 9369 9370 parent_dev = &h->scsi_host->shost_gendev; 9371 9372 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev); 9373 if (!hpsa_sas_node) 9374 return -ENOMEM; 9375 9376 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address); 9377 if (!hpsa_sas_port) { 9378 rc = -ENODEV; 9379 goto free_sas_node; 9380 } 9381 9382 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port); 9383 if (!hpsa_sas_phy) { 9384 rc = -ENODEV; 9385 goto free_sas_port; 9386 } 9387 9388 rc = hpsa_sas_port_add_phy(hpsa_sas_phy); 9389 if (rc) 9390 goto free_sas_phy; 9391 9392 h->sas_host = hpsa_sas_node; 9393 9394 return 0; 9395 9396 free_sas_phy: 9397 hpsa_free_sas_phy(hpsa_sas_phy); 9398 free_sas_port: 9399 hpsa_free_sas_port(hpsa_sas_port); 9400 free_sas_node: 9401 hpsa_free_sas_node(hpsa_sas_node); 9402 9403 return rc; 9404 } 9405 9406 static void hpsa_delete_sas_host(struct ctlr_info *h) 9407 { 9408 hpsa_free_sas_node(h->sas_host); 9409 } 9410 9411 static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, 9412 struct hpsa_scsi_dev_t *device) 9413 { 9414 int rc; 9415 struct hpsa_sas_port *hpsa_sas_port; 9416 struct sas_rphy *rphy; 9417 9418 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address); 9419 if (!hpsa_sas_port) 9420 return -ENOMEM; 9421 9422 rphy = sas_end_device_alloc(hpsa_sas_port->port); 9423 if (!rphy) { 9424 rc = -ENODEV; 9425 goto free_sas_port; 9426 } 9427 9428 hpsa_sas_port->rphy = rphy; 9429 device->sas_port = hpsa_sas_port; 9430 9431 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy); 9432 if (rc) 9433 goto free_sas_port; 9434 9435 return 0; 9436 9437 free_sas_port: 9438 hpsa_free_sas_port(hpsa_sas_port); 9439 device->sas_port = NULL; 9440 9441 return rc; 9442 } 9443 9444 static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device) 9445 { 9446 if (device->sas_port) { 9447 hpsa_free_sas_port(device->sas_port); 9448 device->sas_port = NULL; 9449 } 9450 } 9451 9452 static int 9453 hpsa_sas_get_linkerrors(struct sas_phy *phy) 9454 { 9455 return 0; 9456 } 9457 9458 static int 9459 hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) 9460 { 9461 *identifier = 0; 9462 return 0; 9463 } 9464 9465 static int 9466 hpsa_sas_get_bay_identifier(struct sas_rphy *rphy) 9467 { 9468 return -ENXIO; 9469 } 9470 9471 static int 9472 hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset) 9473 { 9474 return 0; 9475 } 9476 9477 static int 9478 hpsa_sas_phy_enable(struct sas_phy *phy, int enable) 9479 { 9480 return 0; 9481 } 9482 9483 static int 9484 hpsa_sas_phy_setup(struct sas_phy *phy) 9485 { 9486 return 0; 9487 } 9488 9489 static void 9490 hpsa_sas_phy_release(struct sas_phy *phy) 9491 { 9492 } 9493 9494 static int 9495 hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates) 9496 { 9497 return -EINVAL; 9498 } 9499 9500 static struct sas_function_template hpsa_sas_transport_functions = { 9501 .get_linkerrors = hpsa_sas_get_linkerrors, 9502 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier, 9503 .get_bay_identifier = hpsa_sas_get_bay_identifier, 9504 .phy_reset = hpsa_sas_phy_reset, 9505 .phy_enable = hpsa_sas_phy_enable, 9506 .phy_setup = hpsa_sas_phy_setup, 9507 .phy_release = hpsa_sas_phy_release, 9508 .set_phy_speed = hpsa_sas_phy_speed, 9509 }; 9510 9511 /* 9512 * This is it. Register the PCI driver information for the cards we control 9513 * the OS will call our registered routines when it finds one of our cards. 9514 */ 9515 static int __init hpsa_init(void) 9516 { 9517 int rc; 9518 9519 hpsa_sas_transport_template = 9520 sas_attach_transport(&hpsa_sas_transport_functions); 9521 if (!hpsa_sas_transport_template) 9522 return -ENODEV; 9523 9524 rc = pci_register_driver(&hpsa_pci_driver); 9525 9526 if (rc) 9527 sas_release_transport(hpsa_sas_transport_template); 9528 9529 return rc; 9530 } 9531 9532 static void __exit hpsa_cleanup(void) 9533 { 9534 pci_unregister_driver(&hpsa_pci_driver); 9535 sas_release_transport(hpsa_sas_transport_template); 9536 } 9537 9538 static void __attribute__((unused)) verify_offsets(void) 9539 { 9540 #define VERIFY_OFFSET(member, offset) \ 9541 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) 9542 9543 VERIFY_OFFSET(structure_size, 0); 9544 VERIFY_OFFSET(volume_blk_size, 4); 9545 VERIFY_OFFSET(volume_blk_cnt, 8); 9546 VERIFY_OFFSET(phys_blk_shift, 16); 9547 VERIFY_OFFSET(parity_rotation_shift, 17); 9548 VERIFY_OFFSET(strip_size, 18); 9549 VERIFY_OFFSET(disk_starting_blk, 20); 9550 VERIFY_OFFSET(disk_blk_cnt, 28); 9551 VERIFY_OFFSET(data_disks_per_row, 36); 9552 VERIFY_OFFSET(metadata_disks_per_row, 38); 9553 VERIFY_OFFSET(row_cnt, 40); 9554 VERIFY_OFFSET(layout_map_count, 42); 9555 VERIFY_OFFSET(flags, 44); 9556 VERIFY_OFFSET(dekindex, 46); 9557 /* VERIFY_OFFSET(reserved, 48 */ 9558 VERIFY_OFFSET(data, 64); 9559 9560 #undef VERIFY_OFFSET 9561 9562 #define VERIFY_OFFSET(member, offset) \ 9563 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) 9564 9565 VERIFY_OFFSET(IU_type, 0); 9566 VERIFY_OFFSET(direction, 1); 9567 VERIFY_OFFSET(reply_queue, 2); 9568 /* VERIFY_OFFSET(reserved1, 3); */ 9569 VERIFY_OFFSET(scsi_nexus, 4); 9570 VERIFY_OFFSET(Tag, 8); 9571 VERIFY_OFFSET(cdb, 16); 9572 VERIFY_OFFSET(cciss_lun, 32); 9573 VERIFY_OFFSET(data_len, 40); 9574 VERIFY_OFFSET(cmd_priority_task_attr, 44); 9575 VERIFY_OFFSET(sg_count, 45); 9576 /* VERIFY_OFFSET(reserved3 */ 9577 VERIFY_OFFSET(err_ptr, 48); 9578 VERIFY_OFFSET(err_len, 56); 9579 /* VERIFY_OFFSET(reserved4 */ 9580 VERIFY_OFFSET(sg, 64); 9581 9582 #undef VERIFY_OFFSET 9583 9584 #define VERIFY_OFFSET(member, offset) \ 9585 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) 9586 9587 VERIFY_OFFSET(dev_handle, 0x00); 9588 VERIFY_OFFSET(reserved1, 0x02); 9589 VERIFY_OFFSET(function, 0x03); 9590 VERIFY_OFFSET(reserved2, 0x04); 9591 VERIFY_OFFSET(err_info, 0x0C); 9592 VERIFY_OFFSET(reserved3, 0x10); 9593 VERIFY_OFFSET(err_info_len, 0x12); 9594 VERIFY_OFFSET(reserved4, 0x13); 9595 VERIFY_OFFSET(sgl_offset, 0x14); 9596 VERIFY_OFFSET(reserved5, 0x15); 9597 VERIFY_OFFSET(transfer_len, 0x1C); 9598 VERIFY_OFFSET(reserved6, 0x20); 9599 VERIFY_OFFSET(io_flags, 0x24); 9600 VERIFY_OFFSET(reserved7, 0x26); 9601 VERIFY_OFFSET(LUN, 0x34); 9602 VERIFY_OFFSET(control, 0x3C); 9603 VERIFY_OFFSET(CDB, 0x40); 9604 VERIFY_OFFSET(reserved8, 0x50); 9605 VERIFY_OFFSET(host_context_flags, 0x60); 9606 VERIFY_OFFSET(timeout_sec, 0x62); 9607 VERIFY_OFFSET(ReplyQueue, 0x64); 9608 VERIFY_OFFSET(reserved9, 0x65); 9609 VERIFY_OFFSET(tag, 0x68); 9610 VERIFY_OFFSET(host_addr, 0x70); 9611 VERIFY_OFFSET(CISS_LUN, 0x78); 9612 VERIFY_OFFSET(SG, 0x78 + 8); 9613 #undef VERIFY_OFFSET 9614 } 9615 9616 module_init(hpsa_init); 9617 module_exit(hpsa_cleanup); 9618