1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init */ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PHY_CFG_PHY_RST_OFF 3 125 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 126 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 127 #define PHY_CTRL (PORT_BASE + 0x14) 128 #define PHY_CTRL_RESET_OFF 0 129 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 130 #define CMD_HDR_PIR_OFF 8 131 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 132 #define SL_CFG (PORT_BASE + 0x84) 133 #define AIP_LIMIT (PORT_BASE + 0x90) 134 #define SL_CONTROL (PORT_BASE + 0x94) 135 #define SL_CONTROL_NOTIFY_EN_OFF 0 136 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 137 #define SL_CTA_OFF 17 138 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 139 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 140 #define RX_BCAST_CHG_OFF 1 141 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 142 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 143 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 144 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 145 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 146 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 147 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 148 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 149 #define TXID_AUTO (PORT_BASE + 0xb8) 150 #define CT3_OFF 1 151 #define CT3_MSK (0x1 << CT3_OFF) 152 #define TX_HARDRST_OFF 2 153 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 154 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 155 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 156 #define STP_LINK_TIMER (PORT_BASE + 0x120) 157 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 158 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 159 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 160 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 161 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 162 #define CHL_INT0 (PORT_BASE + 0x1b4) 163 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 164 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 165 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 166 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 167 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 168 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 169 #define CHL_INT0_NOT_RDY_OFF 4 170 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 171 #define CHL_INT0_PHY_RDY_OFF 5 172 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 173 #define CHL_INT1 (PORT_BASE + 0x1b8) 174 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 175 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 176 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 177 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 178 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 179 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 180 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 181 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 182 #define CHL_INT2 (PORT_BASE + 0x1bc) 183 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 184 #define CHL_INT2_RX_INVLD_DW_OFF 30 185 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 186 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 189 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 190 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 191 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 192 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 193 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 194 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 195 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 196 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 197 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 198 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 199 #define DMA_TX_STATUS_BUSY_OFF 0 200 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 201 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 202 #define DMA_RX_STATUS_BUSY_OFF 0 203 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 204 205 #define COARSETUNE_TIME (PORT_BASE + 0x304) 206 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 207 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 208 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 209 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 210 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 211 212 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 213 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 214 #error Max ITCT exceeded 215 #endif 216 217 #define AXI_MASTER_CFG_BASE (0x5000) 218 #define AM_CTRL_GLOBAL (0x0) 219 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 220 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 221 #define AM_CURR_TRANS_RETURN (0x150) 222 223 #define AM_CFG_MAX_TRANS (0x5010) 224 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 225 #define AXI_CFG (0x5100) 226 #define AM_ROB_ECC_ERR_ADDR (0x510c) 227 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 228 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 229 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 230 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 231 232 /* RAS registers need init */ 233 #define RAS_BASE (0x6000) 234 #define SAS_RAS_INTR0 (RAS_BASE) 235 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 236 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 237 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 238 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 239 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 240 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 241 242 /* HW dma structures */ 243 /* Delivery queue header */ 244 /* dw0 */ 245 #define CMD_HDR_ABORT_FLAG_OFF 0 246 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 247 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 248 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 249 #define CMD_HDR_RESP_REPORT_OFF 5 250 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 251 #define CMD_HDR_TLR_CTRL_OFF 6 252 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 253 #define CMD_HDR_PORT_OFF 18 254 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 255 #define CMD_HDR_PRIORITY_OFF 27 256 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 257 #define CMD_HDR_CMD_OFF 29 258 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 259 /* dw1 */ 260 #define CMD_HDR_UNCON_CMD_OFF 3 261 #define CMD_HDR_DIR_OFF 5 262 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 263 #define CMD_HDR_RESET_OFF 7 264 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 265 #define CMD_HDR_VDTL_OFF 10 266 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 267 #define CMD_HDR_FRAME_TYPE_OFF 11 268 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 269 #define CMD_HDR_DEV_ID_OFF 16 270 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 271 /* dw2 */ 272 #define CMD_HDR_CFL_OFF 0 273 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 274 #define CMD_HDR_NCQ_TAG_OFF 10 275 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 276 #define CMD_HDR_MRFL_OFF 15 277 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 278 #define CMD_HDR_SG_MOD_OFF 24 279 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 280 /* dw3 */ 281 #define CMD_HDR_IPTT_OFF 0 282 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 283 /* dw6 */ 284 #define CMD_HDR_DIF_SGL_LEN_OFF 0 285 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 286 #define CMD_HDR_DATA_SGL_LEN_OFF 16 287 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 288 /* dw7 */ 289 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 290 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 291 #define CMD_HDR_ABORT_IPTT_OFF 16 292 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 293 294 /* Completion header */ 295 /* dw0 */ 296 #define CMPLT_HDR_CMPLT_OFF 0 297 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 298 #define CMPLT_HDR_ERROR_PHASE_OFF 2 299 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 300 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 301 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 302 #define CMPLT_HDR_ERX_OFF 12 303 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 304 #define CMPLT_HDR_ABORT_STAT_OFF 13 305 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 306 /* abort_stat */ 307 #define STAT_IO_NOT_VALID 0x1 308 #define STAT_IO_NO_DEVICE 0x2 309 #define STAT_IO_COMPLETE 0x3 310 #define STAT_IO_ABORTED 0x4 311 /* dw1 */ 312 #define CMPLT_HDR_IPTT_OFF 0 313 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 314 #define CMPLT_HDR_DEV_ID_OFF 16 315 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 316 /* dw3 */ 317 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 318 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 319 320 /* ITCT header */ 321 /* qw0 */ 322 #define ITCT_HDR_DEV_TYPE_OFF 0 323 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 324 #define ITCT_HDR_VALID_OFF 2 325 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 326 #define ITCT_HDR_MCR_OFF 5 327 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 328 #define ITCT_HDR_VLN_OFF 9 329 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 330 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 331 #define ITCT_HDR_AWT_CONTINUE_OFF 25 332 #define ITCT_HDR_PORT_ID_OFF 28 333 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 334 /* qw2 */ 335 #define ITCT_HDR_INLT_OFF 0 336 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 337 #define ITCT_HDR_RTOLT_OFF 48 338 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 339 340 struct hisi_sas_protect_iu_v3_hw { 341 u32 dw0; 342 u32 lbrtcv; 343 u32 lbrtgv; 344 u32 dw3; 345 u32 dw4; 346 u32 dw5; 347 u32 rsv; 348 }; 349 350 struct hisi_sas_complete_v3_hdr { 351 __le32 dw0; 352 __le32 dw1; 353 __le32 act; 354 __le32 dw3; 355 }; 356 357 struct hisi_sas_err_record_v3 { 358 /* dw0 */ 359 __le32 trans_tx_fail_type; 360 361 /* dw1 */ 362 __le32 trans_rx_fail_type; 363 364 /* dw2 */ 365 __le16 dma_tx_err_type; 366 __le16 sipc_rx_err_type; 367 368 /* dw3 */ 369 __le32 dma_rx_err_type; 370 }; 371 372 #define RX_DATA_LEN_UNDERFLOW_OFF 6 373 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 374 375 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 376 #define HISI_SAS_MSI_COUNT_V3_HW 32 377 378 #define DIR_NO_DATA 0 379 #define DIR_TO_INI 1 380 #define DIR_TO_DEVICE 2 381 #define DIR_RESERVED 3 382 383 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 384 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 385 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 386 ((fis.command == ATA_CMD_DEV_RESET) && \ 387 ((fis.control & ATA_SRST) != 0))) 388 389 #define T10_INSRT_EN_OFF 0 390 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 391 #define T10_RMV_EN_OFF 1 392 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 393 #define T10_RPLC_EN_OFF 2 394 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 395 #define T10_CHK_EN_OFF 3 396 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 397 #define INCR_LBRT_OFF 5 398 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 399 #define USR_DATA_BLOCK_SZ_OFF 20 400 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 401 #define T10_CHK_MSK_OFF 16 402 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 403 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 404 405 #define BASE_VECTORS_V3_HW 16 406 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) 407 408 static bool hisi_sas_intr_conv; 409 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 410 411 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 412 static int prot_mask; 413 module_param(prot_mask, int, 0); 414 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 415 416 static bool auto_affine_msi_experimental; 417 module_param(auto_affine_msi_experimental, bool, 0444); 418 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n" 419 "default is off"); 420 421 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 422 { 423 void __iomem *regs = hisi_hba->regs + off; 424 425 return readl(regs); 426 } 427 428 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 429 { 430 void __iomem *regs = hisi_hba->regs + off; 431 432 return readl_relaxed(regs); 433 } 434 435 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 436 { 437 void __iomem *regs = hisi_hba->regs + off; 438 439 writel(val, regs); 440 } 441 442 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 443 u32 off, u32 val) 444 { 445 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 446 447 writel(val, regs); 448 } 449 450 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 451 int phy_no, u32 off) 452 { 453 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 454 455 return readl(regs); 456 } 457 458 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 459 timeout_us) \ 460 ({ \ 461 void __iomem *regs = hisi_hba->regs + off; \ 462 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 463 }) 464 465 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 466 timeout_us) \ 467 ({ \ 468 void __iomem *regs = hisi_hba->regs + off; \ 469 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 470 }) 471 472 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 473 { 474 struct pci_dev *pdev = hisi_hba->pci_dev; 475 int i; 476 477 /* Global registers init */ 478 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 479 (u32)((1ULL << hisi_hba->queue_count) - 1)); 480 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 481 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 482 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 483 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 484 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 485 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 486 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 487 hisi_sas_intr_conv); 488 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 489 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 490 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 491 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 492 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 493 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 494 if (pdev->revision >= 0x21) 495 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff); 496 else 497 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 498 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 499 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 500 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 501 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 502 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 503 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 504 for (i = 0; i < hisi_hba->queue_count; i++) 505 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 506 507 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 508 509 for (i = 0; i < hisi_hba->n_phy; i++) { 510 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 511 struct asd_sas_phy *sas_phy = &phy->sas_phy; 512 u32 prog_phy_link_rate = 0x800; 513 514 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 515 SAS_LINK_RATE_1_5_GBPS)) { 516 prog_phy_link_rate = 0x855; 517 } else { 518 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 519 520 prog_phy_link_rate = 521 hisi_sas_get_prog_phy_linkrate_mask(max) | 522 0x800; 523 } 524 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 525 prog_phy_link_rate); 526 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 527 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 528 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 529 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 530 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 531 if (pdev->revision >= 0x21) 532 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 533 0xffffffff); 534 else 535 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 536 0xff87ffff); 537 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 538 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 539 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 540 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 541 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 542 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 543 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 544 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 545 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 546 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 547 /* used for 12G negotiate */ 548 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 549 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 550 } 551 552 for (i = 0; i < hisi_hba->queue_count; i++) { 553 /* Delivery queue */ 554 hisi_sas_write32(hisi_hba, 555 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 556 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 557 558 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 559 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 560 561 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 562 HISI_SAS_QUEUE_SLOTS); 563 564 /* Completion queue */ 565 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 566 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 567 568 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 569 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 570 571 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 572 HISI_SAS_QUEUE_SLOTS); 573 } 574 575 /* itct */ 576 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 577 lower_32_bits(hisi_hba->itct_dma)); 578 579 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 580 upper_32_bits(hisi_hba->itct_dma)); 581 582 /* iost */ 583 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 584 lower_32_bits(hisi_hba->iost_dma)); 585 586 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 587 upper_32_bits(hisi_hba->iost_dma)); 588 589 /* breakpoint */ 590 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 591 lower_32_bits(hisi_hba->breakpoint_dma)); 592 593 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 594 upper_32_bits(hisi_hba->breakpoint_dma)); 595 596 /* SATA broken msg */ 597 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 598 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 599 600 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 601 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 602 603 /* SATA initial fis */ 604 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 605 lower_32_bits(hisi_hba->initial_fis_dma)); 606 607 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 608 upper_32_bits(hisi_hba->initial_fis_dma)); 609 610 /* RAS registers init */ 611 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 612 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 613 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 614 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 615 616 /* LED registers init */ 617 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 618 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 619 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 620 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 621 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 622 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 623 } 624 625 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 626 { 627 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 628 629 cfg &= ~PHY_CFG_DC_OPT_MSK; 630 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 631 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 632 } 633 634 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 635 { 636 struct sas_identify_frame identify_frame; 637 u32 *identify_buffer; 638 639 memset(&identify_frame, 0, sizeof(identify_frame)); 640 identify_frame.dev_type = SAS_END_DEVICE; 641 identify_frame.frame_type = 0; 642 identify_frame._un1 = 1; 643 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 644 identify_frame.target_bits = SAS_PROTOCOL_NONE; 645 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 646 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 647 identify_frame.phy_id = phy_no; 648 identify_buffer = (u32 *)(&identify_frame); 649 650 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 651 __swab32(identify_buffer[0])); 652 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 653 __swab32(identify_buffer[1])); 654 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 655 __swab32(identify_buffer[2])); 656 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 657 __swab32(identify_buffer[3])); 658 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 659 __swab32(identify_buffer[4])); 660 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 661 __swab32(identify_buffer[5])); 662 } 663 664 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 665 struct hisi_sas_device *sas_dev) 666 { 667 struct domain_device *device = sas_dev->sas_device; 668 struct device *dev = hisi_hba->dev; 669 u64 qw0, device_id = sas_dev->device_id; 670 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 671 struct domain_device *parent_dev = device->parent; 672 struct asd_sas_port *sas_port = device->port; 673 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 674 u64 sas_addr; 675 676 memset(itct, 0, sizeof(*itct)); 677 678 /* qw0 */ 679 qw0 = 0; 680 switch (sas_dev->dev_type) { 681 case SAS_END_DEVICE: 682 case SAS_EDGE_EXPANDER_DEVICE: 683 case SAS_FANOUT_EXPANDER_DEVICE: 684 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 685 break; 686 case SAS_SATA_DEV: 687 case SAS_SATA_PENDING: 688 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 689 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 690 else 691 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 692 break; 693 default: 694 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 695 sas_dev->dev_type); 696 } 697 698 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 699 (device->linkrate << ITCT_HDR_MCR_OFF) | 700 (1 << ITCT_HDR_VLN_OFF) | 701 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 702 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 703 (port->id << ITCT_HDR_PORT_ID_OFF)); 704 itct->qw0 = cpu_to_le64(qw0); 705 706 /* qw1 */ 707 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 708 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 709 710 /* qw2 */ 711 if (!dev_is_sata(device)) 712 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 713 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 714 } 715 716 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 717 struct hisi_sas_device *sas_dev) 718 { 719 DECLARE_COMPLETION_ONSTACK(completion); 720 u64 dev_id = sas_dev->device_id; 721 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 722 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 723 724 sas_dev->completion = &completion; 725 726 /* clear the itct interrupt state */ 727 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 728 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 729 ENT_INT_SRC3_ITC_INT_MSK); 730 731 /* clear the itct table */ 732 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 733 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 734 735 wait_for_completion(sas_dev->completion); 736 memset(itct, 0, sizeof(struct hisi_sas_itct)); 737 } 738 739 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 740 struct domain_device *device) 741 { 742 struct hisi_sas_slot *slot, *slot2; 743 struct hisi_sas_device *sas_dev = device->lldd_dev; 744 u32 cfg_abt_set_query_iptt; 745 746 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 747 CFG_ABT_SET_QUERY_IPTT); 748 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 749 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 750 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 751 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 752 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 753 cfg_abt_set_query_iptt); 754 } 755 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 756 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 757 cfg_abt_set_query_iptt); 758 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 759 1 << CFG_ABT_SET_IPTT_DONE_OFF); 760 } 761 762 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 763 { 764 struct device *dev = hisi_hba->dev; 765 int ret; 766 u32 val; 767 768 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 769 770 /* Disable all of the PHYs */ 771 hisi_sas_stop_phys(hisi_hba); 772 udelay(50); 773 774 /* Ensure axi bus idle */ 775 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 776 20000, 1000000); 777 if (ret) { 778 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 779 return -EIO; 780 } 781 782 if (ACPI_HANDLE(dev)) { 783 acpi_status s; 784 785 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 786 if (ACPI_FAILURE(s)) { 787 dev_err(dev, "Reset failed\n"); 788 return -EIO; 789 } 790 } else { 791 dev_err(dev, "no reset method!\n"); 792 return -EINVAL; 793 } 794 795 return 0; 796 } 797 798 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 799 { 800 struct device *dev = hisi_hba->dev; 801 int rc; 802 803 rc = reset_hw_v3_hw(hisi_hba); 804 if (rc) { 805 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 806 return rc; 807 } 808 809 msleep(100); 810 init_reg_v3_hw(hisi_hba); 811 812 return 0; 813 } 814 815 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 816 { 817 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 818 819 cfg |= PHY_CFG_ENA_MSK; 820 cfg &= ~PHY_CFG_PHY_RST_MSK; 821 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 822 } 823 824 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 825 { 826 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 827 u32 state; 828 829 cfg &= ~PHY_CFG_ENA_MSK; 830 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 831 832 mdelay(50); 833 834 state = hisi_sas_read32(hisi_hba, PHY_STATE); 835 if (state & BIT(phy_no)) { 836 cfg |= PHY_CFG_PHY_RST_MSK; 837 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 838 } 839 } 840 841 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 842 { 843 config_id_frame_v3_hw(hisi_hba, phy_no); 844 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 845 enable_phy_v3_hw(hisi_hba, phy_no); 846 } 847 848 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 849 { 850 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 851 u32 txid_auto; 852 853 disable_phy_v3_hw(hisi_hba, phy_no); 854 if (phy->identify.device_type == SAS_END_DEVICE) { 855 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 856 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 857 txid_auto | TX_HARDRST_MSK); 858 } 859 msleep(100); 860 start_phy_v3_hw(hisi_hba, phy_no); 861 } 862 863 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 864 { 865 return SAS_LINK_RATE_12_0_GBPS; 866 } 867 868 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 869 { 870 int i; 871 872 for (i = 0; i < hisi_hba->n_phy; i++) { 873 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 874 struct asd_sas_phy *sas_phy = &phy->sas_phy; 875 876 if (!sas_phy->phy->enabled) 877 continue; 878 879 start_phy_v3_hw(hisi_hba, i); 880 } 881 } 882 883 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 884 { 885 u32 sl_control; 886 887 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 888 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 889 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 890 msleep(1); 891 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 892 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 893 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 894 } 895 896 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 897 { 898 int i, bitmap = 0; 899 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 900 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 901 902 for (i = 0; i < hisi_hba->n_phy; i++) 903 if (phy_state & BIT(i)) 904 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 905 bitmap |= BIT(i); 906 907 return bitmap; 908 } 909 910 /** 911 * The callpath to this function and upto writing the write 912 * queue pointer should be safe from interruption. 913 */ 914 static int 915 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 916 { 917 struct device *dev = hisi_hba->dev; 918 int queue = dq->id; 919 u32 r, w; 920 921 w = dq->wr_point; 922 r = hisi_sas_read32_relaxed(hisi_hba, 923 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 924 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 925 dev_warn(dev, "full queue=%d r=%d w=%d\n", 926 queue, r, w); 927 return -EAGAIN; 928 } 929 930 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 931 932 return w; 933 } 934 935 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 936 { 937 struct hisi_hba *hisi_hba = dq->hisi_hba; 938 struct hisi_sas_slot *s, *s1, *s2 = NULL; 939 int dlvry_queue = dq->id; 940 int wp; 941 942 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 943 if (!s->ready) 944 break; 945 s2 = s; 946 list_del(&s->delivery); 947 } 948 949 if (!s2) 950 return; 951 952 /* 953 * Ensure that memories for slots built on other CPUs is observed. 954 */ 955 smp_rmb(); 956 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 957 958 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 959 } 960 961 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 962 struct hisi_sas_slot *slot, 963 struct hisi_sas_cmd_hdr *hdr, 964 struct scatterlist *scatter, 965 int n_elem) 966 { 967 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 968 struct scatterlist *sg; 969 int i; 970 971 for_each_sg(scatter, sg, n_elem, i) { 972 struct hisi_sas_sge *entry = &sge_page->sge[i]; 973 974 entry->addr = cpu_to_le64(sg_dma_address(sg)); 975 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 976 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 977 entry->data_off = 0; 978 } 979 980 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 981 982 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 983 } 984 985 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 986 struct hisi_sas_slot *slot, 987 struct hisi_sas_cmd_hdr *hdr, 988 struct scatterlist *scatter, 989 int n_elem) 990 { 991 struct hisi_sas_sge_dif_page *sge_dif_page; 992 struct scatterlist *sg; 993 int i; 994 995 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 996 997 for_each_sg(scatter, sg, n_elem, i) { 998 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 999 1000 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1001 entry->page_ctrl_0 = 0; 1002 entry->page_ctrl_1 = 0; 1003 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1004 entry->data_off = 0; 1005 } 1006 1007 hdr->dif_prd_table_addr = 1008 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1009 1010 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1011 } 1012 1013 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1014 { 1015 unsigned char prot_flags = scsi_cmnd->prot_flags; 1016 1017 if (prot_flags & SCSI_PROT_REF_CHECK) 1018 return T10_CHK_APP_TAG_MSK; 1019 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1020 } 1021 1022 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1023 struct hisi_sas_protect_iu_v3_hw *prot) 1024 { 1025 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1026 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1027 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1028 1029 switch (prot_op) { 1030 case SCSI_PROT_READ_INSERT: 1031 prot->dw0 |= T10_INSRT_EN_MSK; 1032 prot->lbrtgv = lbrt_chk_val; 1033 break; 1034 case SCSI_PROT_READ_STRIP: 1035 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1036 prot->lbrtcv = lbrt_chk_val; 1037 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1038 break; 1039 case SCSI_PROT_READ_PASS: 1040 prot->dw0 |= T10_CHK_EN_MSK; 1041 prot->lbrtcv = lbrt_chk_val; 1042 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1043 break; 1044 case SCSI_PROT_WRITE_INSERT: 1045 prot->dw0 |= T10_INSRT_EN_MSK; 1046 prot->lbrtgv = lbrt_chk_val; 1047 break; 1048 case SCSI_PROT_WRITE_STRIP: 1049 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1050 prot->lbrtcv = lbrt_chk_val; 1051 break; 1052 case SCSI_PROT_WRITE_PASS: 1053 prot->dw0 |= T10_CHK_EN_MSK; 1054 prot->lbrtcv = lbrt_chk_val; 1055 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1056 break; 1057 default: 1058 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1059 break; 1060 } 1061 1062 switch (interval) { 1063 case 512: 1064 break; 1065 case 4096: 1066 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1067 break; 1068 case 520: 1069 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1070 break; 1071 default: 1072 WARN(1, "protection interval (0x%x) invalid\n", 1073 interval); 1074 break; 1075 } 1076 1077 prot->dw0 |= INCR_LBRT_MSK; 1078 } 1079 1080 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1081 struct hisi_sas_slot *slot) 1082 { 1083 struct sas_task *task = slot->task; 1084 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1085 struct domain_device *device = task->dev; 1086 struct hisi_sas_device *sas_dev = device->lldd_dev; 1087 struct hisi_sas_port *port = slot->port; 1088 struct sas_ssp_task *ssp_task = &task->ssp_task; 1089 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1090 struct hisi_sas_tmf_task *tmf = slot->tmf; 1091 int has_data = 0, priority = !!tmf; 1092 unsigned char prot_op; 1093 u8 *buf_cmd; 1094 u32 dw1 = 0, dw2 = 0, len = 0; 1095 1096 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1097 (2 << CMD_HDR_TLR_CTRL_OFF) | 1098 (port->id << CMD_HDR_PORT_OFF) | 1099 (priority << CMD_HDR_PRIORITY_OFF) | 1100 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1101 1102 dw1 = 1 << CMD_HDR_VDTL_OFF; 1103 if (tmf) { 1104 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1105 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1106 } else { 1107 prot_op = scsi_get_prot_op(scsi_cmnd); 1108 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1109 switch (scsi_cmnd->sc_data_direction) { 1110 case DMA_TO_DEVICE: 1111 has_data = 1; 1112 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1113 break; 1114 case DMA_FROM_DEVICE: 1115 has_data = 1; 1116 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1117 break; 1118 default: 1119 dw1 &= ~CMD_HDR_DIR_MSK; 1120 } 1121 } 1122 1123 /* map itct entry */ 1124 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1125 1126 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1127 + 3) / 4) << CMD_HDR_CFL_OFF) | 1128 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1129 (2 << CMD_HDR_SG_MOD_OFF); 1130 hdr->dw2 = cpu_to_le32(dw2); 1131 hdr->transfer_tags = cpu_to_le32(slot->idx); 1132 1133 if (has_data) { 1134 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1135 slot->n_elem); 1136 1137 if (scsi_prot_sg_count(scsi_cmnd)) 1138 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1139 scsi_prot_sglist(scsi_cmnd), 1140 slot->n_elem_dif); 1141 } 1142 1143 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1144 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1145 1146 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1147 sizeof(struct ssp_frame_hdr); 1148 1149 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1150 if (!tmf) { 1151 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1152 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1153 } else { 1154 buf_cmd[10] = tmf->tmf; 1155 switch (tmf->tmf) { 1156 case TMF_ABORT_TASK: 1157 case TMF_QUERY_TASK: 1158 buf_cmd[12] = 1159 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1160 buf_cmd[13] = 1161 tmf->tag_of_task_to_be_managed & 0xff; 1162 break; 1163 default: 1164 break; 1165 } 1166 } 1167 1168 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1169 struct hisi_sas_protect_iu_v3_hw prot; 1170 u8 *buf_cmd_prot; 1171 1172 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1173 dw1 |= CMD_HDR_PIR_MSK; 1174 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1175 sizeof(struct ssp_frame_hdr) + 1176 sizeof(struct ssp_command_iu); 1177 1178 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1179 fill_prot_v3_hw(scsi_cmnd, &prot); 1180 memcpy(buf_cmd_prot, &prot, 1181 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1182 /* 1183 * For READ, we need length of info read to memory, while for 1184 * WRITE we need length of data written to the disk. 1185 */ 1186 if (prot_op == SCSI_PROT_WRITE_INSERT || 1187 prot_op == SCSI_PROT_READ_INSERT || 1188 prot_op == SCSI_PROT_WRITE_PASS || 1189 prot_op == SCSI_PROT_READ_PASS) { 1190 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1191 unsigned int ilog2_interval = ilog2(interval); 1192 1193 len = (task->total_xfer_len >> ilog2_interval) * 8; 1194 } 1195 } 1196 1197 hdr->dw1 = cpu_to_le32(dw1); 1198 1199 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1200 } 1201 1202 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1203 struct hisi_sas_slot *slot) 1204 { 1205 struct sas_task *task = slot->task; 1206 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1207 struct domain_device *device = task->dev; 1208 struct hisi_sas_port *port = slot->port; 1209 struct scatterlist *sg_req; 1210 struct hisi_sas_device *sas_dev = device->lldd_dev; 1211 dma_addr_t req_dma_addr; 1212 unsigned int req_len; 1213 1214 /* req */ 1215 sg_req = &task->smp_task.smp_req; 1216 req_len = sg_dma_len(sg_req); 1217 req_dma_addr = sg_dma_address(sg_req); 1218 1219 /* create header */ 1220 /* dw0 */ 1221 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1222 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1223 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1224 1225 /* map itct entry */ 1226 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1227 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1228 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1229 1230 /* dw2 */ 1231 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1232 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1233 CMD_HDR_MRFL_OFF)); 1234 1235 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1236 1237 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1238 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1239 1240 } 1241 1242 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1243 struct hisi_sas_slot *slot) 1244 { 1245 struct sas_task *task = slot->task; 1246 struct domain_device *device = task->dev; 1247 struct domain_device *parent_dev = device->parent; 1248 struct hisi_sas_device *sas_dev = device->lldd_dev; 1249 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1250 struct asd_sas_port *sas_port = device->port; 1251 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1252 u8 *buf_cmd; 1253 int has_data = 0, hdr_tag = 0; 1254 u32 dw1 = 0, dw2 = 0; 1255 1256 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1257 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1258 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1259 else 1260 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1261 1262 switch (task->data_dir) { 1263 case DMA_TO_DEVICE: 1264 has_data = 1; 1265 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1266 break; 1267 case DMA_FROM_DEVICE: 1268 has_data = 1; 1269 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1270 break; 1271 default: 1272 dw1 &= ~CMD_HDR_DIR_MSK; 1273 } 1274 1275 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1276 (task->ata_task.fis.control & ATA_SRST)) 1277 dw1 |= 1 << CMD_HDR_RESET_OFF; 1278 1279 dw1 |= (hisi_sas_get_ata_protocol( 1280 &task->ata_task.fis, task->data_dir)) 1281 << CMD_HDR_FRAME_TYPE_OFF; 1282 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1283 1284 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1285 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1286 1287 hdr->dw1 = cpu_to_le32(dw1); 1288 1289 /* dw2 */ 1290 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1291 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1292 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1293 } 1294 1295 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1296 2 << CMD_HDR_SG_MOD_OFF; 1297 hdr->dw2 = cpu_to_le32(dw2); 1298 1299 /* dw3 */ 1300 hdr->transfer_tags = cpu_to_le32(slot->idx); 1301 1302 if (has_data) 1303 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1304 slot->n_elem); 1305 1306 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1307 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1308 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1309 1310 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1311 1312 if (likely(!task->ata_task.device_control_reg_update)) 1313 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1314 /* fill in command FIS */ 1315 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1316 } 1317 1318 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1319 struct hisi_sas_slot *slot, 1320 int device_id, int abort_flag, int tag_to_abort) 1321 { 1322 struct sas_task *task = slot->task; 1323 struct domain_device *dev = task->dev; 1324 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1325 struct hisi_sas_port *port = slot->port; 1326 1327 /* dw0 */ 1328 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1329 (port->id << CMD_HDR_PORT_OFF) | 1330 (dev_is_sata(dev) 1331 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1332 (abort_flag 1333 << CMD_HDR_ABORT_FLAG_OFF)); 1334 1335 /* dw1 */ 1336 hdr->dw1 = cpu_to_le32(device_id 1337 << CMD_HDR_DEV_ID_OFF); 1338 1339 /* dw7 */ 1340 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1341 hdr->transfer_tags = cpu_to_le32(slot->idx); 1342 1343 } 1344 1345 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1346 { 1347 int i; 1348 irqreturn_t res; 1349 u32 context, port_id, link_rate; 1350 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1351 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1352 struct device *dev = hisi_hba->dev; 1353 unsigned long flags; 1354 1355 del_timer(&phy->timer); 1356 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1357 1358 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1359 port_id = (port_id >> (4 * phy_no)) & 0xf; 1360 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1361 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1362 1363 if (port_id == 0xf) { 1364 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1365 res = IRQ_NONE; 1366 goto end; 1367 } 1368 sas_phy->linkrate = link_rate; 1369 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1370 1371 /* Check for SATA dev */ 1372 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1373 if (context & (1 << phy_no)) { 1374 struct hisi_sas_initial_fis *initial_fis; 1375 struct dev_to_host_fis *fis; 1376 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1377 1378 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1379 initial_fis = &hisi_hba->initial_fis[phy_no]; 1380 fis = &initial_fis->fis; 1381 1382 /* check ERR bit of Status Register */ 1383 if (fis->status & ATA_ERR) { 1384 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1385 phy_no, fis->status); 1386 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1387 res = IRQ_NONE; 1388 goto end; 1389 } 1390 1391 sas_phy->oob_mode = SATA_OOB_MODE; 1392 attached_sas_addr[0] = 0x50; 1393 attached_sas_addr[7] = phy_no; 1394 memcpy(sas_phy->attached_sas_addr, 1395 attached_sas_addr, 1396 SAS_ADDR_SIZE); 1397 memcpy(sas_phy->frame_rcvd, fis, 1398 sizeof(struct dev_to_host_fis)); 1399 phy->phy_type |= PORT_TYPE_SATA; 1400 phy->identify.device_type = SAS_SATA_DEV; 1401 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1402 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1403 } else { 1404 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1405 struct sas_identify_frame *id = 1406 (struct sas_identify_frame *)frame_rcvd; 1407 1408 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1409 for (i = 0; i < 6; i++) { 1410 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1411 RX_IDAF_DWORD0 + (i * 4)); 1412 frame_rcvd[i] = __swab32(idaf); 1413 } 1414 sas_phy->oob_mode = SAS_OOB_MODE; 1415 memcpy(sas_phy->attached_sas_addr, 1416 &id->sas_addr, 1417 SAS_ADDR_SIZE); 1418 phy->phy_type |= PORT_TYPE_SAS; 1419 phy->identify.device_type = id->dev_type; 1420 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1421 if (phy->identify.device_type == SAS_END_DEVICE) 1422 phy->identify.target_port_protocols = 1423 SAS_PROTOCOL_SSP; 1424 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1425 phy->identify.target_port_protocols = 1426 SAS_PROTOCOL_SMP; 1427 } 1428 1429 phy->port_id = port_id; 1430 phy->phy_attached = 1; 1431 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1432 res = IRQ_HANDLED; 1433 spin_lock_irqsave(&phy->lock, flags); 1434 if (phy->reset_completion) { 1435 phy->in_reset = 0; 1436 complete(phy->reset_completion); 1437 } 1438 spin_unlock_irqrestore(&phy->lock, flags); 1439 end: 1440 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1441 CHL_INT0_SL_PHY_ENABLE_MSK); 1442 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1443 1444 return res; 1445 } 1446 1447 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1448 { 1449 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1450 u32 phy_state, sl_ctrl, txid_auto; 1451 struct device *dev = hisi_hba->dev; 1452 1453 del_timer(&phy->timer); 1454 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1455 1456 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1457 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1458 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1459 1460 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1461 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1462 sl_ctrl&(~SL_CTA_MSK)); 1463 1464 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1465 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1466 txid_auto | CT3_MSK); 1467 1468 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1469 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1470 1471 return IRQ_HANDLED; 1472 } 1473 1474 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1475 { 1476 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1477 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1478 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1479 u32 bcast_status; 1480 1481 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1482 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1483 if ((bcast_status & RX_BCAST_CHG_MSK) && 1484 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1485 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1486 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1487 CHL_INT0_SL_RX_BCST_ACK_MSK); 1488 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1489 1490 return IRQ_HANDLED; 1491 } 1492 1493 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1494 { 1495 struct hisi_hba *hisi_hba = p; 1496 u32 irq_msk; 1497 int phy_no = 0; 1498 irqreturn_t res = IRQ_NONE; 1499 1500 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1501 & 0x11111111; 1502 while (irq_msk) { 1503 if (irq_msk & 1) { 1504 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1505 CHL_INT0); 1506 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1507 int rdy = phy_state & (1 << phy_no); 1508 1509 if (rdy) { 1510 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1511 /* phy up */ 1512 if (phy_up_v3_hw(phy_no, hisi_hba) 1513 == IRQ_HANDLED) 1514 res = IRQ_HANDLED; 1515 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1516 /* phy bcast */ 1517 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1518 == IRQ_HANDLED) 1519 res = IRQ_HANDLED; 1520 } else { 1521 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1522 /* phy down */ 1523 if (phy_down_v3_hw(phy_no, hisi_hba) 1524 == IRQ_HANDLED) 1525 res = IRQ_HANDLED; 1526 } 1527 } 1528 irq_msk >>= 4; 1529 phy_no++; 1530 } 1531 1532 return res; 1533 } 1534 1535 static const struct hisi_sas_hw_error port_axi_error[] = { 1536 { 1537 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1538 .msg = "dma_tx_axi_wr_err", 1539 }, 1540 { 1541 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1542 .msg = "dma_tx_axi_rd_err", 1543 }, 1544 { 1545 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1546 .msg = "dma_rx_axi_wr_err", 1547 }, 1548 { 1549 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1550 .msg = "dma_rx_axi_rd_err", 1551 }, 1552 }; 1553 1554 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1555 { 1556 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1557 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1558 struct device *dev = hisi_hba->dev; 1559 int i; 1560 1561 irq_value &= ~irq_msk; 1562 if (!irq_value) 1563 return; 1564 1565 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1566 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1567 1568 if (!(irq_value & error->irq_msk)) 1569 continue; 1570 1571 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1572 error->msg, phy_no, irq_value); 1573 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1574 } 1575 1576 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1577 } 1578 1579 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1580 { 1581 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1582 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1583 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1584 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1585 struct device *dev = hisi_hba->dev; 1586 1587 irq_value &= ~irq_msk; 1588 if (!irq_value) 1589 return; 1590 1591 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1592 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1593 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1594 } 1595 1596 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1597 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1598 STP_LINK_TIMEOUT_STATE); 1599 1600 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1601 phy_no, reg_value); 1602 if (reg_value & BIT(4)) 1603 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1604 } 1605 1606 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1607 (pci_dev->revision == 0x20)) { 1608 u32 reg_value; 1609 int rc; 1610 1611 rc = hisi_sas_read32_poll_timeout_atomic( 1612 HILINK_ERR_DFX, reg_value, 1613 !((reg_value >> 8) & BIT(phy_no)), 1614 1000, 10000); 1615 if (rc) 1616 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1617 } 1618 1619 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1620 } 1621 1622 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1623 { 1624 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1625 1626 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1627 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1628 1629 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1630 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1631 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1632 & (~CHL_INT0_NOT_RDY_MSK)); 1633 } 1634 1635 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1636 { 1637 struct hisi_hba *hisi_hba = p; 1638 u32 irq_msk; 1639 int phy_no = 0; 1640 1641 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1642 & 0xeeeeeeee; 1643 1644 while (irq_msk) { 1645 if (irq_msk & (2 << (phy_no * 4))) 1646 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1647 1648 if (irq_msk & (4 << (phy_no * 4))) 1649 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1650 1651 if (irq_msk & (8 << (phy_no * 4))) 1652 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1653 1654 irq_msk &= ~(0xe << (phy_no * 4)); 1655 phy_no++; 1656 } 1657 1658 return IRQ_HANDLED; 1659 } 1660 1661 static const struct hisi_sas_hw_error axi_error[] = { 1662 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1663 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1664 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1665 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1666 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1667 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1668 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1669 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1670 {}, 1671 }; 1672 1673 static const struct hisi_sas_hw_error fifo_error[] = { 1674 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1675 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1676 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1677 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1678 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1679 {}, 1680 }; 1681 1682 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1683 { 1684 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1685 .msg = "write pointer and depth", 1686 }, 1687 { 1688 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1689 .msg = "iptt no match slot", 1690 }, 1691 { 1692 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1693 .msg = "read pointer and depth", 1694 }, 1695 { 1696 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1697 .reg = HGC_AXI_FIFO_ERR_INFO, 1698 .sub = axi_error, 1699 }, 1700 { 1701 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1702 .reg = HGC_AXI_FIFO_ERR_INFO, 1703 .sub = fifo_error, 1704 }, 1705 { 1706 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1707 .msg = "LM add/fetch list", 1708 }, 1709 { 1710 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1711 .msg = "SAS_HGC_ABT fetch LM list", 1712 }, 1713 }; 1714 1715 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1716 { 1717 u32 irq_value, irq_msk; 1718 struct hisi_hba *hisi_hba = p; 1719 struct device *dev = hisi_hba->dev; 1720 struct pci_dev *pdev = hisi_hba->pci_dev; 1721 int i; 1722 1723 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1724 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1725 1726 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1727 irq_value &= ~irq_msk; 1728 1729 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1730 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1731 1732 if (!(irq_value & error->irq_msk)) 1733 continue; 1734 1735 if (error->sub) { 1736 const struct hisi_sas_hw_error *sub = error->sub; 1737 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1738 1739 for (; sub->msk || sub->msg; sub++) { 1740 if (!(err_value & sub->msk)) 1741 continue; 1742 1743 dev_err(dev, "%s error (0x%x) found!\n", 1744 sub->msg, irq_value); 1745 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1746 } 1747 } else { 1748 dev_err(dev, "%s error (0x%x) found!\n", 1749 error->msg, irq_value); 1750 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1751 } 1752 1753 if (pdev->revision < 0x21) { 1754 u32 reg_val; 1755 1756 reg_val = hisi_sas_read32(hisi_hba, 1757 AXI_MASTER_CFG_BASE + 1758 AM_CTRL_GLOBAL); 1759 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 1760 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 1761 AM_CTRL_GLOBAL, reg_val); 1762 } 1763 } 1764 1765 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1766 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1767 u32 dev_id = reg_val & ITCT_DEV_MSK; 1768 struct hisi_sas_device *sas_dev = 1769 &hisi_hba->devices[dev_id]; 1770 1771 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1772 dev_dbg(dev, "clear ITCT ok\n"); 1773 complete(sas_dev->completion); 1774 } 1775 1776 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1777 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1778 1779 return IRQ_HANDLED; 1780 } 1781 1782 static void 1783 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1784 struct hisi_sas_slot *slot) 1785 { 1786 struct task_status_struct *ts = &task->task_status; 1787 struct hisi_sas_complete_v3_hdr *complete_queue = 1788 hisi_hba->complete_hdr[slot->cmplt_queue]; 1789 struct hisi_sas_complete_v3_hdr *complete_hdr = 1790 &complete_queue[slot->cmplt_queue_slot]; 1791 struct hisi_sas_err_record_v3 *record = 1792 hisi_sas_status_buf_addr_mem(slot); 1793 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 1794 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 1795 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 1796 1797 switch (task->task_proto) { 1798 case SAS_PROTOCOL_SSP: 1799 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1800 ts->residual = trans_tx_fail_type; 1801 ts->stat = SAS_DATA_UNDERRUN; 1802 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1803 ts->stat = SAS_QUEUE_FULL; 1804 slot->abort = 1; 1805 } else { 1806 ts->stat = SAS_OPEN_REJECT; 1807 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1808 } 1809 break; 1810 case SAS_PROTOCOL_SATA: 1811 case SAS_PROTOCOL_STP: 1812 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1813 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1814 ts->residual = trans_tx_fail_type; 1815 ts->stat = SAS_DATA_UNDERRUN; 1816 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1817 ts->stat = SAS_PHY_DOWN; 1818 slot->abort = 1; 1819 } else { 1820 ts->stat = SAS_OPEN_REJECT; 1821 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1822 } 1823 hisi_sas_sata_done(task, slot); 1824 break; 1825 case SAS_PROTOCOL_SMP: 1826 ts->stat = SAM_STAT_CHECK_CONDITION; 1827 break; 1828 default: 1829 break; 1830 } 1831 } 1832 1833 static int 1834 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1835 { 1836 struct sas_task *task = slot->task; 1837 struct hisi_sas_device *sas_dev; 1838 struct device *dev = hisi_hba->dev; 1839 struct task_status_struct *ts; 1840 struct domain_device *device; 1841 struct sas_ha_struct *ha; 1842 enum exec_status sts; 1843 struct hisi_sas_complete_v3_hdr *complete_queue = 1844 hisi_hba->complete_hdr[slot->cmplt_queue]; 1845 struct hisi_sas_complete_v3_hdr *complete_hdr = 1846 &complete_queue[slot->cmplt_queue_slot]; 1847 unsigned long flags; 1848 bool is_internal = slot->is_internal; 1849 u32 dw0, dw1, dw3; 1850 1851 if (unlikely(!task || !task->lldd_task || !task->dev)) 1852 return -EINVAL; 1853 1854 ts = &task->task_status; 1855 device = task->dev; 1856 ha = device->port->ha; 1857 sas_dev = device->lldd_dev; 1858 1859 spin_lock_irqsave(&task->task_state_lock, flags); 1860 task->task_state_flags &= 1861 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1862 spin_unlock_irqrestore(&task->task_state_lock, flags); 1863 1864 memset(ts, 0, sizeof(*ts)); 1865 ts->resp = SAS_TASK_COMPLETE; 1866 1867 if (unlikely(!sas_dev)) { 1868 dev_dbg(dev, "slot complete: port has not device\n"); 1869 ts->stat = SAS_PHY_DOWN; 1870 goto out; 1871 } 1872 1873 dw0 = le32_to_cpu(complete_hdr->dw0); 1874 dw1 = le32_to_cpu(complete_hdr->dw1); 1875 dw3 = le32_to_cpu(complete_hdr->dw3); 1876 1877 /* 1878 * Use SAS+TMF status codes 1879 */ 1880 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 1881 case STAT_IO_ABORTED: 1882 /* this IO has been aborted by abort command */ 1883 ts->stat = SAS_ABORTED_TASK; 1884 goto out; 1885 case STAT_IO_COMPLETE: 1886 /* internal abort command complete */ 1887 ts->stat = TMF_RESP_FUNC_SUCC; 1888 goto out; 1889 case STAT_IO_NO_DEVICE: 1890 ts->stat = TMF_RESP_FUNC_COMPLETE; 1891 goto out; 1892 case STAT_IO_NOT_VALID: 1893 /* 1894 * abort single IO, the controller can't find the IO 1895 */ 1896 ts->stat = TMF_RESP_FUNC_FAILED; 1897 goto out; 1898 default: 1899 break; 1900 } 1901 1902 /* check for erroneous completion */ 1903 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1904 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1905 1906 slot_err_v3_hw(hisi_hba, task, slot); 1907 if (ts->stat != SAS_DATA_UNDERRUN) 1908 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1909 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1910 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1911 slot->idx, task, sas_dev->device_id, 1912 dw0, dw1, complete_hdr->act, dw3, 1913 error_info[0], error_info[1], 1914 error_info[2], error_info[3]); 1915 if (unlikely(slot->abort)) 1916 return ts->stat; 1917 goto out; 1918 } 1919 1920 switch (task->task_proto) { 1921 case SAS_PROTOCOL_SSP: { 1922 struct ssp_response_iu *iu = 1923 hisi_sas_status_buf_addr_mem(slot) + 1924 sizeof(struct hisi_sas_err_record); 1925 1926 sas_ssp_task_response(dev, task, iu); 1927 break; 1928 } 1929 case SAS_PROTOCOL_SMP: { 1930 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1931 void *to; 1932 1933 ts->stat = SAM_STAT_GOOD; 1934 to = kmap_atomic(sg_page(sg_resp)); 1935 1936 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1937 DMA_FROM_DEVICE); 1938 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1939 DMA_TO_DEVICE); 1940 memcpy(to + sg_resp->offset, 1941 hisi_sas_status_buf_addr_mem(slot) + 1942 sizeof(struct hisi_sas_err_record), 1943 sg_dma_len(sg_resp)); 1944 kunmap_atomic(to); 1945 break; 1946 } 1947 case SAS_PROTOCOL_SATA: 1948 case SAS_PROTOCOL_STP: 1949 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1950 ts->stat = SAM_STAT_GOOD; 1951 hisi_sas_sata_done(task, slot); 1952 break; 1953 default: 1954 ts->stat = SAM_STAT_CHECK_CONDITION; 1955 break; 1956 } 1957 1958 if (!slot->port->port_attached) { 1959 dev_warn(dev, "slot complete: port %d has removed\n", 1960 slot->port->sas_port.id); 1961 ts->stat = SAS_PHY_DOWN; 1962 } 1963 1964 out: 1965 sts = ts->stat; 1966 spin_lock_irqsave(&task->task_state_lock, flags); 1967 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1968 spin_unlock_irqrestore(&task->task_state_lock, flags); 1969 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1970 return SAS_ABORTED_TASK; 1971 } 1972 task->task_state_flags |= SAS_TASK_STATE_DONE; 1973 spin_unlock_irqrestore(&task->task_state_lock, flags); 1974 hisi_sas_slot_task_free(hisi_hba, task, slot); 1975 1976 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1977 spin_lock_irqsave(&device->done_lock, flags); 1978 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1979 spin_unlock_irqrestore(&device->done_lock, flags); 1980 dev_info(dev, "slot complete: task(%p) ignored\n ", 1981 task); 1982 return sts; 1983 } 1984 spin_unlock_irqrestore(&device->done_lock, flags); 1985 } 1986 1987 if (task->task_done) 1988 task->task_done(task); 1989 1990 return sts; 1991 } 1992 1993 static void cq_tasklet_v3_hw(unsigned long val) 1994 { 1995 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1996 struct hisi_hba *hisi_hba = cq->hisi_hba; 1997 struct hisi_sas_slot *slot; 1998 struct hisi_sas_complete_v3_hdr *complete_queue; 1999 u32 rd_point = cq->rd_point, wr_point; 2000 int queue = cq->id; 2001 2002 complete_queue = hisi_hba->complete_hdr[queue]; 2003 2004 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2005 (0x14 * queue)); 2006 2007 while (rd_point != wr_point) { 2008 struct hisi_sas_complete_v3_hdr *complete_hdr; 2009 struct device *dev = hisi_hba->dev; 2010 u32 dw1; 2011 int iptt; 2012 2013 complete_hdr = &complete_queue[rd_point]; 2014 dw1 = le32_to_cpu(complete_hdr->dw1); 2015 2016 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2017 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2018 slot = &hisi_hba->slot_info[iptt]; 2019 slot->cmplt_queue_slot = rd_point; 2020 slot->cmplt_queue = queue; 2021 slot_complete_v3_hw(hisi_hba, slot); 2022 } else 2023 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2024 2025 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2026 rd_point = 0; 2027 } 2028 2029 /* update rd_point */ 2030 cq->rd_point = rd_point; 2031 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2032 } 2033 2034 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2035 { 2036 struct hisi_sas_cq *cq = p; 2037 struct hisi_hba *hisi_hba = cq->hisi_hba; 2038 int queue = cq->id; 2039 2040 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2041 2042 tasklet_schedule(&cq->tasklet); 2043 2044 return IRQ_HANDLED; 2045 } 2046 2047 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) 2048 { 2049 const struct cpumask *mask; 2050 int queue, cpu; 2051 2052 for (queue = 0; queue < nvecs; queue++) { 2053 struct hisi_sas_cq *cq = &hisi_hba->cq[queue]; 2054 2055 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + 2056 BASE_VECTORS_V3_HW); 2057 if (!mask) 2058 goto fallback; 2059 cq->pci_irq_mask = mask; 2060 for_each_cpu(cpu, mask) 2061 hisi_hba->reply_map[cpu] = queue; 2062 } 2063 return; 2064 2065 fallback: 2066 for_each_possible_cpu(cpu) 2067 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count; 2068 /* Don't clean all CQ masks */ 2069 } 2070 2071 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2072 { 2073 struct device *dev = hisi_hba->dev; 2074 struct pci_dev *pdev = hisi_hba->pci_dev; 2075 int vectors, rc; 2076 int i, k; 2077 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; 2078 2079 if (auto_affine_msi_experimental) { 2080 struct irq_affinity desc = { 2081 .pre_vectors = BASE_VECTORS_V3_HW, 2082 }; 2083 2084 min_msi = MIN_AFFINE_VECTORS_V3_HW; 2085 2086 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids, 2087 sizeof(unsigned int), 2088 GFP_KERNEL); 2089 if (!hisi_hba->reply_map) 2090 return -ENOMEM; 2091 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev, 2092 min_msi, max_msi, 2093 PCI_IRQ_MSI | 2094 PCI_IRQ_AFFINITY, 2095 &desc); 2096 if (vectors < 0) 2097 return -ENOENT; 2098 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW); 2099 } else { 2100 min_msi = max_msi; 2101 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi, 2102 max_msi, PCI_IRQ_MSI); 2103 if (vectors < 0) 2104 return vectors; 2105 } 2106 2107 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; 2108 2109 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2110 int_phy_up_down_bcast_v3_hw, 0, 2111 DRV_NAME " phy", hisi_hba); 2112 if (rc) { 2113 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2114 rc = -ENOENT; 2115 goto free_irq_vectors; 2116 } 2117 2118 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2119 int_chnl_int_v3_hw, 0, 2120 DRV_NAME " channel", hisi_hba); 2121 if (rc) { 2122 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2123 rc = -ENOENT; 2124 goto free_phy_irq; 2125 } 2126 2127 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2128 fatal_axi_int_v3_hw, 0, 2129 DRV_NAME " fatal", hisi_hba); 2130 if (rc) { 2131 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2132 rc = -ENOENT; 2133 goto free_chnl_interrupt; 2134 } 2135 2136 /* Init tasklets for cq only */ 2137 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2138 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2139 struct tasklet_struct *t = &cq->tasklet; 2140 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2141 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2142 2143 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2144 cq_interrupt_v3_hw, irqflags, 2145 DRV_NAME " cq", cq); 2146 if (rc) { 2147 dev_err(dev, 2148 "could not request cq%d interrupt, rc=%d\n", 2149 i, rc); 2150 rc = -ENOENT; 2151 goto free_cq_irqs; 2152 } 2153 2154 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2155 } 2156 2157 return 0; 2158 2159 free_cq_irqs: 2160 for (k = 0; k < i; k++) { 2161 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2162 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2163 2164 free_irq(pci_irq_vector(pdev, nr), cq); 2165 } 2166 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2167 free_chnl_interrupt: 2168 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2169 free_phy_irq: 2170 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2171 free_irq_vectors: 2172 pci_free_irq_vectors(pdev); 2173 return rc; 2174 } 2175 2176 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2177 { 2178 int rc; 2179 2180 rc = hw_init_v3_hw(hisi_hba); 2181 if (rc) 2182 return rc; 2183 2184 rc = interrupt_init_v3_hw(hisi_hba); 2185 if (rc) 2186 return rc; 2187 2188 return 0; 2189 } 2190 2191 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2192 struct sas_phy_linkrates *r) 2193 { 2194 enum sas_linkrate max = r->maximum_linkrate; 2195 u32 prog_phy_link_rate = 0x800; 2196 2197 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2198 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2199 prog_phy_link_rate); 2200 } 2201 2202 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2203 { 2204 struct pci_dev *pdev = hisi_hba->pci_dev; 2205 int i; 2206 2207 synchronize_irq(pci_irq_vector(pdev, 1)); 2208 synchronize_irq(pci_irq_vector(pdev, 2)); 2209 synchronize_irq(pci_irq_vector(pdev, 11)); 2210 for (i = 0; i < hisi_hba->queue_count; i++) { 2211 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2212 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2213 } 2214 2215 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2216 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2217 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2218 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2219 2220 for (i = 0; i < hisi_hba->n_phy; i++) { 2221 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2222 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2223 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2224 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2225 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2226 } 2227 } 2228 2229 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2230 { 2231 return hisi_sas_read32(hisi_hba, PHY_STATE); 2232 } 2233 2234 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 2235 { 2236 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2237 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2238 struct sas_phy *sphy = sas_phy->phy; 2239 u32 reg_value; 2240 2241 /* loss dword sync */ 2242 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 2243 sphy->loss_of_dword_sync_count += reg_value; 2244 2245 /* phy reset problem */ 2246 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 2247 sphy->phy_reset_problem_count += reg_value; 2248 2249 /* invalid dword */ 2250 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 2251 sphy->invalid_dword_count += reg_value; 2252 2253 /* disparity err */ 2254 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 2255 sphy->running_disparity_error_count += reg_value; 2256 2257 } 2258 2259 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2260 { 2261 struct device *dev = hisi_hba->dev; 2262 u32 status, reg_val; 2263 int rc; 2264 2265 interrupt_disable_v3_hw(hisi_hba); 2266 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2267 hisi_sas_kill_tasklets(hisi_hba); 2268 2269 hisi_sas_stop_phys(hisi_hba); 2270 2271 mdelay(10); 2272 2273 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2274 AM_CTRL_GLOBAL); 2275 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2276 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2277 AM_CTRL_GLOBAL, reg_val); 2278 2279 /* wait until bus idle */ 2280 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2281 AM_CURR_TRANS_RETURN, status, 2282 status == 0x3, 10, 100); 2283 if (rc) { 2284 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2285 return rc; 2286 } 2287 2288 return 0; 2289 } 2290 2291 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2292 { 2293 struct device *dev = hisi_hba->dev; 2294 int rc; 2295 2296 rc = disable_host_v3_hw(hisi_hba); 2297 if (rc) { 2298 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2299 return rc; 2300 } 2301 2302 hisi_sas_init_mem(hisi_hba); 2303 2304 return hw_init_v3_hw(hisi_hba); 2305 } 2306 2307 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2308 u8 reg_index, u8 reg_count, u8 *write_data) 2309 { 2310 struct device *dev = hisi_hba->dev; 2311 u32 *data = (u32 *)write_data; 2312 int i; 2313 2314 switch (reg_type) { 2315 case SAS_GPIO_REG_TX: 2316 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2317 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2318 reg_index, reg_index + reg_count - 1); 2319 return -EINVAL; 2320 } 2321 2322 for (i = 0; i < reg_count; i++) 2323 hisi_sas_write32(hisi_hba, 2324 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2325 data[i]); 2326 break; 2327 default: 2328 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2329 reg_type); 2330 return -EINVAL; 2331 } 2332 2333 return 0; 2334 } 2335 2336 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2337 int delay_ms, int timeout_ms) 2338 { 2339 struct device *dev = hisi_hba->dev; 2340 int entries, entries_old = 0, time; 2341 2342 for (time = 0; time < timeout_ms; time += delay_ms) { 2343 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2344 if (entries == entries_old) 2345 break; 2346 2347 entries_old = entries; 2348 msleep(delay_ms); 2349 } 2350 2351 if (time >= timeout_ms) 2352 return -ETIMEDOUT; 2353 2354 dev_dbg(dev, "wait commands complete %dms\n", time); 2355 2356 return 0; 2357 } 2358 2359 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2360 struct device_attribute *attr, char *buf) 2361 { 2362 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2363 } 2364 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2365 2366 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2367 { 2368 /* config those registers between enable and disable PHYs */ 2369 hisi_sas_stop_phys(hisi_hba); 2370 2371 if (hisi_hba->intr_coal_ticks == 0 || 2372 hisi_hba->intr_coal_count == 0) { 2373 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2374 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2375 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2376 } else { 2377 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2378 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2379 hisi_hba->intr_coal_ticks); 2380 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2381 hisi_hba->intr_coal_count); 2382 } 2383 phys_init_v3_hw(hisi_hba); 2384 } 2385 2386 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2387 struct device_attribute *attr, 2388 char *buf) 2389 { 2390 struct Scsi_Host *shost = class_to_shost(dev); 2391 struct hisi_hba *hisi_hba = shost_priv(shost); 2392 2393 return scnprintf(buf, PAGE_SIZE, "%u\n", 2394 hisi_hba->intr_coal_ticks); 2395 } 2396 2397 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2398 struct device_attribute *attr, 2399 const char *buf, size_t count) 2400 { 2401 struct Scsi_Host *shost = class_to_shost(dev); 2402 struct hisi_hba *hisi_hba = shost_priv(shost); 2403 u32 intr_coal_ticks; 2404 int ret; 2405 2406 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2407 if (ret) { 2408 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2409 return -EINVAL; 2410 } 2411 2412 if (intr_coal_ticks >= BIT(24)) { 2413 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2414 return -EINVAL; 2415 } 2416 2417 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2418 2419 config_intr_coal_v3_hw(hisi_hba); 2420 2421 return count; 2422 } 2423 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2424 2425 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2426 struct device_attribute 2427 *attr, char *buf) 2428 { 2429 struct Scsi_Host *shost = class_to_shost(dev); 2430 struct hisi_hba *hisi_hba = shost_priv(shost); 2431 2432 return scnprintf(buf, PAGE_SIZE, "%u\n", 2433 hisi_hba->intr_coal_count); 2434 } 2435 2436 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2437 struct device_attribute 2438 *attr, const char *buf, size_t count) 2439 { 2440 struct Scsi_Host *shost = class_to_shost(dev); 2441 struct hisi_hba *hisi_hba = shost_priv(shost); 2442 u32 intr_coal_count; 2443 int ret; 2444 2445 ret = kstrtou32(buf, 10, &intr_coal_count); 2446 if (ret) { 2447 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2448 return -EINVAL; 2449 } 2450 2451 if (intr_coal_count >= BIT(8)) { 2452 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2453 return -EINVAL; 2454 } 2455 2456 hisi_hba->intr_coal_count = intr_coal_count; 2457 2458 config_intr_coal_v3_hw(hisi_hba); 2459 2460 return count; 2461 } 2462 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2463 2464 static struct device_attribute *host_attrs_v3_hw[] = { 2465 &dev_attr_phy_event_threshold, 2466 &dev_attr_intr_conv_v3_hw, 2467 &dev_attr_intr_coal_ticks_v3_hw, 2468 &dev_attr_intr_coal_count_v3_hw, 2469 NULL 2470 }; 2471 2472 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2473 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2474 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2475 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2476 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2477 HISI_SAS_DEBUGFS_REG(SL_CFG), 2478 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2479 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2480 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2481 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2482 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2483 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2484 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2485 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2486 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2487 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2488 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2489 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2490 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2491 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2492 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2493 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2494 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2495 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2496 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2497 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2498 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2499 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2500 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2501 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2502 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2503 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2504 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2505 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2506 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2507 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2508 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2509 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2510 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2511 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2512 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2513 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2514 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2515 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2516 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2517 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2518 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2519 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2520 {} 2521 }; 2522 2523 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2524 .lu = debugfs_port_reg_lu, 2525 .count = 0x100, 2526 .base_off = PORT_BASE, 2527 .read_port_reg = hisi_sas_phy_read32, 2528 }; 2529 2530 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2531 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2532 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2533 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2534 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2535 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2536 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2537 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2538 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2539 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2540 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2541 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2542 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2543 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2544 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2545 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2546 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2547 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2548 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2549 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2550 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2551 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2552 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2553 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2554 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2555 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2556 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2557 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2558 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2559 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2560 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2561 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2562 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2563 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2564 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2565 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2566 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2567 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2568 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2569 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2570 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2571 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2572 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2573 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2574 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2575 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2576 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2577 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2578 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2579 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2580 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2581 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2582 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2583 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2584 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2585 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2586 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2587 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2588 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2589 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2590 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2591 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2592 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2593 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2594 {} 2595 }; 2596 2597 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2598 .lu = debugfs_global_reg_lu, 2599 .count = 0x800, 2600 .read_global_reg = hisi_sas_read32, 2601 }; 2602 2603 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2604 { 2605 struct device *dev = hisi_hba->dev; 2606 2607 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2608 2609 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2610 2611 if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT) 2612 dev_dbg(dev, "Wait commands complete timeout!\n"); 2613 2614 hisi_sas_kill_tasklets(hisi_hba); 2615 } 2616 2617 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2618 { 2619 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2620 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2621 2622 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2623 } 2624 2625 static struct scsi_host_template sht_v3_hw = { 2626 .name = DRV_NAME, 2627 .module = THIS_MODULE, 2628 .queuecommand = sas_queuecommand, 2629 .target_alloc = sas_target_alloc, 2630 .slave_configure = hisi_sas_slave_configure, 2631 .scan_finished = hisi_sas_scan_finished, 2632 .scan_start = hisi_sas_scan_start, 2633 .change_queue_depth = sas_change_queue_depth, 2634 .bios_param = sas_bios_param, 2635 .this_id = -1, 2636 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2637 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2638 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2639 .eh_device_reset_handler = sas_eh_device_reset_handler, 2640 .eh_target_reset_handler = sas_eh_target_reset_handler, 2641 .target_destroy = sas_target_destroy, 2642 .ioctl = sas_ioctl, 2643 .shost_attrs = host_attrs_v3_hw, 2644 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2645 }; 2646 2647 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2648 .hw_init = hisi_sas_v3_init, 2649 .setup_itct = setup_itct_v3_hw, 2650 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2651 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2652 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2653 .clear_itct = clear_itct_v3_hw, 2654 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2655 .prep_ssp = prep_ssp_v3_hw, 2656 .prep_smp = prep_smp_v3_hw, 2657 .prep_stp = prep_ata_v3_hw, 2658 .prep_abort = prep_abort_v3_hw, 2659 .get_free_slot = get_free_slot_v3_hw, 2660 .start_delivery = start_delivery_v3_hw, 2661 .slot_complete = slot_complete_v3_hw, 2662 .phys_init = phys_init_v3_hw, 2663 .phy_start = start_phy_v3_hw, 2664 .phy_disable = disable_phy_v3_hw, 2665 .phy_hard_reset = phy_hard_reset_v3_hw, 2666 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2667 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2668 .dereg_device = dereg_device_v3_hw, 2669 .soft_reset = soft_reset_v3_hw, 2670 .get_phys_state = get_phys_state_v3_hw, 2671 .get_events = phy_get_events_v3_hw, 2672 .write_gpio = write_gpio_v3_hw, 2673 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2674 .debugfs_reg_global = &debugfs_global_reg, 2675 .debugfs_reg_port = &debugfs_port_reg, 2676 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2677 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2678 }; 2679 2680 static struct Scsi_Host * 2681 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2682 { 2683 struct Scsi_Host *shost; 2684 struct hisi_hba *hisi_hba; 2685 struct device *dev = &pdev->dev; 2686 2687 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2688 if (!shost) { 2689 dev_err(dev, "shost alloc failed\n"); 2690 return NULL; 2691 } 2692 hisi_hba = shost_priv(shost); 2693 2694 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2695 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2696 hisi_hba->hw = &hisi_sas_v3_hw; 2697 hisi_hba->pci_dev = pdev; 2698 hisi_hba->dev = dev; 2699 hisi_hba->shost = shost; 2700 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2701 2702 if (prot_mask & ~HISI_SAS_PROT_MASK) 2703 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2704 prot_mask); 2705 else 2706 hisi_hba->prot_mask = prot_mask; 2707 2708 timer_setup(&hisi_hba->timer, NULL, 0); 2709 2710 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2711 goto err_out; 2712 2713 if (hisi_sas_alloc(hisi_hba)) { 2714 hisi_sas_free(hisi_hba); 2715 goto err_out; 2716 } 2717 2718 return shost; 2719 err_out: 2720 scsi_host_put(shost); 2721 dev_err(dev, "shost alloc failed\n"); 2722 return NULL; 2723 } 2724 2725 static int 2726 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2727 { 2728 struct Scsi_Host *shost; 2729 struct hisi_hba *hisi_hba; 2730 struct device *dev = &pdev->dev; 2731 struct asd_sas_phy **arr_phy; 2732 struct asd_sas_port **arr_port; 2733 struct sas_ha_struct *sha; 2734 int rc, phy_nr, port_nr, i; 2735 2736 rc = pci_enable_device(pdev); 2737 if (rc) 2738 goto err_out; 2739 2740 pci_set_master(pdev); 2741 2742 rc = pci_request_regions(pdev, DRV_NAME); 2743 if (rc) 2744 goto err_out_disable_device; 2745 2746 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) || 2747 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { 2748 dev_err(dev, "No usable DMA addressing method\n"); 2749 rc = -EIO; 2750 goto err_out_regions; 2751 } 2752 2753 shost = hisi_sas_shost_alloc_pci(pdev); 2754 if (!shost) { 2755 rc = -ENOMEM; 2756 goto err_out_regions; 2757 } 2758 2759 sha = SHOST_TO_SAS_HA(shost); 2760 hisi_hba = shost_priv(shost); 2761 dev_set_drvdata(dev, sha); 2762 2763 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2764 if (!hisi_hba->regs) { 2765 dev_err(dev, "cannot map register.\n"); 2766 rc = -ENOMEM; 2767 goto err_out_ha; 2768 } 2769 2770 phy_nr = port_nr = hisi_hba->n_phy; 2771 2772 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2773 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2774 if (!arr_phy || !arr_port) { 2775 rc = -ENOMEM; 2776 goto err_out_ha; 2777 } 2778 2779 sha->sas_phy = arr_phy; 2780 sha->sas_port = arr_port; 2781 sha->core.shost = shost; 2782 sha->lldd_ha = hisi_hba; 2783 2784 shost->transportt = hisi_sas_stt; 2785 shost->max_id = HISI_SAS_MAX_DEVICES; 2786 shost->max_lun = ~0; 2787 shost->max_channel = 1; 2788 shost->max_cmd_len = 16; 2789 shost->can_queue = hisi_hba->hw->max_command_entries - 2790 HISI_SAS_RESERVED_IPTT_CNT; 2791 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 2792 HISI_SAS_RESERVED_IPTT_CNT; 2793 2794 sha->sas_ha_name = DRV_NAME; 2795 sha->dev = dev; 2796 sha->lldd_module = THIS_MODULE; 2797 sha->sas_addr = &hisi_hba->sas_addr[0]; 2798 sha->num_phys = hisi_hba->n_phy; 2799 sha->core.shost = hisi_hba->shost; 2800 2801 for (i = 0; i < hisi_hba->n_phy; i++) { 2802 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2803 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2804 } 2805 2806 if (hisi_sas_debugfs_enable) 2807 hisi_sas_debugfs_init(hisi_hba); 2808 2809 rc = scsi_add_host(shost, dev); 2810 if (rc) 2811 goto err_out_ha; 2812 2813 rc = sas_register_ha(sha); 2814 if (rc) 2815 goto err_out_register_ha; 2816 2817 rc = hisi_hba->hw->hw_init(hisi_hba); 2818 if (rc) 2819 goto err_out_register_ha; 2820 2821 if (hisi_hba->prot_mask) { 2822 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 2823 prot_mask); 2824 scsi_host_set_prot(hisi_hba->shost, prot_mask); 2825 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 2826 scsi_host_set_guard(hisi_hba->shost, 2827 SHOST_DIX_GUARD_CRC); 2828 } 2829 2830 scsi_scan_host(shost); 2831 2832 return 0; 2833 2834 err_out_register_ha: 2835 scsi_remove_host(shost); 2836 err_out_ha: 2837 scsi_host_put(shost); 2838 err_out_regions: 2839 pci_release_regions(pdev); 2840 err_out_disable_device: 2841 pci_disable_device(pdev); 2842 err_out: 2843 return rc; 2844 } 2845 2846 static void 2847 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2848 { 2849 int i; 2850 2851 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2852 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2853 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2854 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2855 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2856 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2857 2858 free_irq(pci_irq_vector(pdev, nr), cq); 2859 } 2860 pci_free_irq_vectors(pdev); 2861 } 2862 2863 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2864 { 2865 struct device *dev = &pdev->dev; 2866 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2867 struct hisi_hba *hisi_hba = sha->lldd_ha; 2868 struct Scsi_Host *shost = sha->core.shost; 2869 2870 hisi_sas_debugfs_exit(hisi_hba); 2871 2872 if (timer_pending(&hisi_hba->timer)) 2873 del_timer(&hisi_hba->timer); 2874 2875 sas_unregister_ha(sha); 2876 sas_remove_host(sha->core.shost); 2877 2878 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2879 hisi_sas_kill_tasklets(hisi_hba); 2880 pci_release_regions(pdev); 2881 pci_disable_device(pdev); 2882 hisi_sas_free(hisi_hba); 2883 scsi_host_put(shost); 2884 } 2885 2886 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2887 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2888 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2889 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2890 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2891 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2892 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2893 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2894 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2895 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2896 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2897 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2898 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2899 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2900 }; 2901 2902 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2903 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2904 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2905 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2906 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2907 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2908 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2909 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2910 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2911 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2912 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2913 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2914 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2915 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2916 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2917 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2918 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2919 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2920 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2921 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2922 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2923 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2924 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2925 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2926 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2927 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2928 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2929 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2930 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2931 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2932 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2933 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2934 }; 2935 2936 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2937 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2938 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2939 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2940 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2941 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2942 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2943 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2944 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2945 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2946 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2947 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2948 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2949 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2950 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2951 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2952 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2953 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2954 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2955 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2956 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2957 }; 2958 2959 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2960 { 2961 struct device *dev = hisi_hba->dev; 2962 const struct hisi_sas_hw_error *ras_error; 2963 bool need_reset = false; 2964 u32 irq_value; 2965 int i; 2966 2967 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2968 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2969 ras_error = &sas_ras_intr0_nfe[i]; 2970 if (ras_error->irq_msk & irq_value) { 2971 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2972 ras_error->msg, irq_value); 2973 need_reset = true; 2974 } 2975 } 2976 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2977 2978 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2979 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2980 ras_error = &sas_ras_intr1_nfe[i]; 2981 if (ras_error->irq_msk & irq_value) { 2982 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2983 ras_error->msg, irq_value); 2984 need_reset = true; 2985 } 2986 } 2987 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2988 2989 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2990 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2991 ras_error = &sas_ras_intr2_nfe[i]; 2992 if (ras_error->irq_msk & irq_value) { 2993 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2994 ras_error->msg, irq_value); 2995 need_reset = true; 2996 } 2997 } 2998 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2999 3000 return need_reset; 3001 } 3002 3003 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 3004 pci_channel_state_t state) 3005 { 3006 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3007 struct hisi_hba *hisi_hba = sha->lldd_ha; 3008 struct device *dev = hisi_hba->dev; 3009 3010 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 3011 if (state == pci_channel_io_perm_failure) 3012 return PCI_ERS_RESULT_DISCONNECT; 3013 3014 if (process_non_fatal_error_v3_hw(hisi_hba)) 3015 return PCI_ERS_RESULT_NEED_RESET; 3016 3017 return PCI_ERS_RESULT_CAN_RECOVER; 3018 } 3019 3020 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 3021 { 3022 return PCI_ERS_RESULT_RECOVERED; 3023 } 3024 3025 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 3026 { 3027 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3028 struct hisi_hba *hisi_hba = sha->lldd_ha; 3029 struct device *dev = hisi_hba->dev; 3030 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 3031 3032 dev_info(dev, "PCI error: slot reset callback!!\n"); 3033 queue_work(hisi_hba->wq, &r.work); 3034 wait_for_completion(r.completion); 3035 if (r.done) 3036 return PCI_ERS_RESULT_RECOVERED; 3037 3038 return PCI_ERS_RESULT_DISCONNECT; 3039 } 3040 3041 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 3042 { 3043 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3044 struct hisi_hba *hisi_hba = sha->lldd_ha; 3045 struct device *dev = hisi_hba->dev; 3046 int rc; 3047 3048 dev_info(dev, "FLR prepare\n"); 3049 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3050 hisi_sas_controller_reset_prepare(hisi_hba); 3051 3052 rc = disable_host_v3_hw(hisi_hba); 3053 if (rc) 3054 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 3055 } 3056 3057 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3058 { 3059 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3060 struct hisi_hba *hisi_hba = sha->lldd_ha; 3061 struct device *dev = hisi_hba->dev; 3062 int rc; 3063 3064 hisi_sas_init_mem(hisi_hba); 3065 3066 rc = hw_init_v3_hw(hisi_hba); 3067 if (rc) { 3068 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3069 return; 3070 } 3071 3072 hisi_sas_controller_reset_done(hisi_hba); 3073 dev_info(dev, "FLR done\n"); 3074 } 3075 3076 enum { 3077 /* instances of the controller */ 3078 hip08, 3079 }; 3080 3081 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3082 { 3083 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3084 struct hisi_hba *hisi_hba = sha->lldd_ha; 3085 struct device *dev = hisi_hba->dev; 3086 struct Scsi_Host *shost = hisi_hba->shost; 3087 pci_power_t device_state; 3088 int rc; 3089 3090 if (!pdev->pm_cap) { 3091 dev_err(dev, "PCI PM not supported\n"); 3092 return -ENODEV; 3093 } 3094 3095 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3096 return -1; 3097 3098 scsi_block_requests(shost); 3099 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3100 flush_workqueue(hisi_hba->wq); 3101 3102 rc = disable_host_v3_hw(hisi_hba); 3103 if (rc) { 3104 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3105 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3106 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3107 scsi_unblock_requests(shost); 3108 return rc; 3109 } 3110 3111 hisi_sas_init_mem(hisi_hba); 3112 3113 device_state = pci_choose_state(pdev, state); 3114 dev_warn(dev, "entering operating state [D%d]\n", 3115 device_state); 3116 pci_save_state(pdev); 3117 pci_disable_device(pdev); 3118 pci_set_power_state(pdev, device_state); 3119 3120 hisi_sas_release_tasks(hisi_hba); 3121 3122 sas_suspend_ha(sha); 3123 return 0; 3124 } 3125 3126 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3127 { 3128 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3129 struct hisi_hba *hisi_hba = sha->lldd_ha; 3130 struct Scsi_Host *shost = hisi_hba->shost; 3131 struct device *dev = hisi_hba->dev; 3132 unsigned int rc; 3133 pci_power_t device_state = pdev->current_state; 3134 3135 dev_warn(dev, "resuming from operating state [D%d]\n", 3136 device_state); 3137 pci_set_power_state(pdev, PCI_D0); 3138 pci_enable_wake(pdev, PCI_D0, 0); 3139 pci_restore_state(pdev); 3140 rc = pci_enable_device(pdev); 3141 if (rc) 3142 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3143 3144 pci_set_master(pdev); 3145 scsi_unblock_requests(shost); 3146 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3147 3148 sas_prep_resume_ha(sha); 3149 init_reg_v3_hw(hisi_hba); 3150 hisi_hba->hw->phys_init(hisi_hba); 3151 sas_resume_ha(sha); 3152 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3153 3154 return 0; 3155 } 3156 3157 static const struct pci_device_id sas_v3_pci_table[] = { 3158 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3159 {} 3160 }; 3161 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3162 3163 static const struct pci_error_handlers hisi_sas_err_handler = { 3164 .error_detected = hisi_sas_error_detected_v3_hw, 3165 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 3166 .slot_reset = hisi_sas_slot_reset_v3_hw, 3167 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3168 .reset_done = hisi_sas_reset_done_v3_hw, 3169 }; 3170 3171 static struct pci_driver sas_v3_pci_driver = { 3172 .name = DRV_NAME, 3173 .id_table = sas_v3_pci_table, 3174 .probe = hisi_sas_v3_probe, 3175 .remove = hisi_sas_v3_remove, 3176 .suspend = hisi_sas_v3_suspend, 3177 .resume = hisi_sas_v3_resume, 3178 .err_handler = &hisi_sas_err_handler, 3179 }; 3180 3181 module_pci_driver(sas_v3_pci_driver); 3182 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3183 3184 MODULE_LICENSE("GPL"); 3185 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3186 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3187 MODULE_ALIAS("pci:" DRV_NAME); 3188