1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init */ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define HGC_LM_DFX_STATUS2 0x128 56 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 57 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ 58 HGC_LM_DFX_STATUS2_IOSTLIST_OFF) 59 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 60 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ 61 HGC_LM_DFX_STATUS2_ITCTLIST_OFF) 62 #define HGC_CQE_ECC_ADDR 0x13c 63 #define HGC_CQE_ECC_1B_ADDR_OFF 0 64 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) 65 #define HGC_CQE_ECC_MB_ADDR_OFF 8 66 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) 67 #define HGC_IOST_ECC_ADDR 0x140 68 #define HGC_IOST_ECC_1B_ADDR_OFF 0 69 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) 70 #define HGC_IOST_ECC_MB_ADDR_OFF 16 71 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) 72 #define HGC_DQE_ECC_ADDR 0x144 73 #define HGC_DQE_ECC_1B_ADDR_OFF 0 74 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) 75 #define HGC_DQE_ECC_MB_ADDR_OFF 16 76 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) 77 #define CHNL_INT_STATUS 0x148 78 #define HGC_ITCT_ECC_ADDR 0x150 79 #define HGC_ITCT_ECC_1B_ADDR_OFF 0 80 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ 81 HGC_ITCT_ECC_1B_ADDR_OFF) 82 #define HGC_ITCT_ECC_MB_ADDR_OFF 16 83 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ 84 HGC_ITCT_ECC_MB_ADDR_OFF) 85 #define HGC_AXI_FIFO_ERR_INFO 0x154 86 #define AXI_ERR_INFO_OFF 0 87 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 88 #define FIFO_ERR_INFO_OFF 8 89 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 90 #define INT_COAL_EN 0x19c 91 #define OQ_INT_COAL_TIME 0x1a0 92 #define OQ_INT_COAL_CNT 0x1a4 93 #define ENT_INT_COAL_TIME 0x1a8 94 #define ENT_INT_COAL_CNT 0x1ac 95 #define OQ_INT_SRC 0x1b0 96 #define OQ_INT_SRC_MSK 0x1b4 97 #define ENT_INT_SRC1 0x1b8 98 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 99 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 100 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 101 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 102 #define ENT_INT_SRC2 0x1bc 103 #define ENT_INT_SRC3 0x1c0 104 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 105 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 106 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 107 #define ENT_INT_SRC3_AXI_OFF 11 108 #define ENT_INT_SRC3_FIFO_OFF 12 109 #define ENT_INT_SRC3_LM_OFF 14 110 #define ENT_INT_SRC3_ITC_INT_OFF 15 111 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 112 #define ENT_INT_SRC3_ABT_OFF 16 113 #define ENT_INT_SRC3_DQE_POISON_OFF 18 114 #define ENT_INT_SRC3_IOST_POISON_OFF 19 115 #define ENT_INT_SRC3_ITCT_POISON_OFF 20 116 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21 117 #define ENT_INT_SRC_MSK1 0x1c4 118 #define ENT_INT_SRC_MSK2 0x1c8 119 #define ENT_INT_SRC_MSK3 0x1cc 120 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 121 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 122 #define CHNL_ENT_INT_MSK 0x1d4 123 #define HGC_COM_INT_MSK 0x1d8 124 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 125 #define SAS_ECC_INTR 0x1e8 126 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 127 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 128 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 129 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4 131 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5 132 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6 133 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7 134 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8 135 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9 136 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 137 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12 139 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14 141 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16 143 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18 145 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19 146 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20 147 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21 148 #define SAS_ECC_INTR_MSK 0x1ec 149 #define HGC_ERR_STAT_EN 0x238 150 #define CQE_SEND_CNT 0x248 151 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 152 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 153 #define DLVRY_Q_0_DEPTH 0x268 154 #define DLVRY_Q_0_WR_PTR 0x26c 155 #define DLVRY_Q_0_RD_PTR 0x270 156 #define HYPER_STREAM_ID_EN_CFG 0xc80 157 #define OQ0_INT_SRC_MSK 0xc90 158 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 159 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 160 #define COMPL_Q_0_DEPTH 0x4e8 161 #define COMPL_Q_0_WR_PTR 0x4ec 162 #define COMPL_Q_0_RD_PTR 0x4f0 163 #define HGC_RXM_DFX_STATUS14 0xae8 164 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 165 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ 166 HGC_RXM_DFX_STATUS14_MEM0_OFF) 167 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 168 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ 169 HGC_RXM_DFX_STATUS14_MEM1_OFF) 170 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 171 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ 172 HGC_RXM_DFX_STATUS14_MEM2_OFF) 173 #define HGC_RXM_DFX_STATUS15 0xaec 174 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 175 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ 176 HGC_RXM_DFX_STATUS15_MEM3_OFF) 177 #define AWQOS_AWCACHE_CFG 0xc84 178 #define ARQOS_ARCACHE_CFG 0xc88 179 #define HILINK_ERR_DFX 0xe04 180 #define SAS_GPIO_CFG_0 0x1000 181 #define SAS_GPIO_CFG_1 0x1004 182 #define SAS_GPIO_TX_0_1 0x1040 183 #define SAS_CFG_DRIVE_VLD 0x1070 184 185 /* phy registers requiring init */ 186 #define PORT_BASE (0x2000) 187 #define PHY_CFG (PORT_BASE + 0x0) 188 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 189 #define PHY_CFG_ENA_OFF 0 190 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 191 #define PHY_CFG_DC_OPT_OFF 2 192 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 193 #define PHY_CFG_PHY_RST_OFF 3 194 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 195 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 196 #define PHY_CTRL (PORT_BASE + 0x14) 197 #define PHY_CTRL_RESET_OFF 0 198 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 199 #define CMD_HDR_PIR_OFF 8 200 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 201 #define SERDES_CFG (PORT_BASE + 0x1c) 202 #define SL_CFG (PORT_BASE + 0x84) 203 #define AIP_LIMIT (PORT_BASE + 0x90) 204 #define SL_CONTROL (PORT_BASE + 0x94) 205 #define SL_CONTROL_NOTIFY_EN_OFF 0 206 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 207 #define SL_CTA_OFF 17 208 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 209 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 210 #define RX_BCAST_CHG_OFF 1 211 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 212 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 213 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 214 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 215 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 216 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 217 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 218 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 219 #define TXID_AUTO (PORT_BASE + 0xb8) 220 #define CT3_OFF 1 221 #define CT3_MSK (0x1 << CT3_OFF) 222 #define TX_HARDRST_OFF 2 223 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 224 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 225 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 226 #define STP_LINK_TIMER (PORT_BASE + 0x120) 227 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 228 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 229 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 230 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 231 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 232 #define CHL_INT0 (PORT_BASE + 0x1b4) 233 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 234 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 235 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 236 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 237 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 238 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 239 #define CHL_INT0_NOT_RDY_OFF 4 240 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 241 #define CHL_INT0_PHY_RDY_OFF 5 242 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 243 #define CHL_INT1 (PORT_BASE + 0x1b8) 244 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15 245 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16 246 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17 247 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18 248 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 249 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 250 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 251 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 252 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23 253 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24 254 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26 255 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27 256 #define CHL_INT2 (PORT_BASE + 0x1bc) 257 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 258 #define CHL_INT2_RX_DISP_ERR_OFF 28 259 #define CHL_INT2_RX_CODE_ERR_OFF 29 260 #define CHL_INT2_RX_INVLD_DW_OFF 30 261 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 262 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 263 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 264 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 265 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 266 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 267 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 268 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 269 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 270 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 271 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 272 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 273 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 274 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 275 #define DMA_TX_STATUS_BUSY_OFF 0 276 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 277 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 278 #define DMA_RX_STATUS_BUSY_OFF 0 279 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 280 281 #define COARSETUNE_TIME (PORT_BASE + 0x304) 282 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 283 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 284 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 285 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 286 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 287 288 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 289 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 290 #error Max ITCT exceeded 291 #endif 292 293 #define AXI_MASTER_CFG_BASE (0x5000) 294 #define AM_CTRL_GLOBAL (0x0) 295 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 296 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 297 #define AM_CURR_TRANS_RETURN (0x150) 298 299 #define AM_CFG_MAX_TRANS (0x5010) 300 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 301 #define AXI_CFG (0x5100) 302 #define AM_ROB_ECC_ERR_ADDR (0x510c) 303 #define AM_ROB_ECC_ERR_ADDR_OFF 0 304 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff 305 306 /* RAS registers need init */ 307 #define RAS_BASE (0x6000) 308 #define SAS_RAS_INTR0 (RAS_BASE) 309 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 310 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 311 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 312 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 313 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 314 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 315 316 /* HW dma structures */ 317 /* Delivery queue header */ 318 /* dw0 */ 319 #define CMD_HDR_ABORT_FLAG_OFF 0 320 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 321 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 322 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 323 #define CMD_HDR_RESP_REPORT_OFF 5 324 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 325 #define CMD_HDR_TLR_CTRL_OFF 6 326 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 327 #define CMD_HDR_PORT_OFF 18 328 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 329 #define CMD_HDR_PRIORITY_OFF 27 330 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 331 #define CMD_HDR_CMD_OFF 29 332 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 333 /* dw1 */ 334 #define CMD_HDR_UNCON_CMD_OFF 3 335 #define CMD_HDR_DIR_OFF 5 336 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 337 #define CMD_HDR_RESET_OFF 7 338 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 339 #define CMD_HDR_VDTL_OFF 10 340 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 341 #define CMD_HDR_FRAME_TYPE_OFF 11 342 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 343 #define CMD_HDR_DEV_ID_OFF 16 344 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 345 /* dw2 */ 346 #define CMD_HDR_CFL_OFF 0 347 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 348 #define CMD_HDR_NCQ_TAG_OFF 10 349 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 350 #define CMD_HDR_MRFL_OFF 15 351 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 352 #define CMD_HDR_SG_MOD_OFF 24 353 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 354 /* dw3 */ 355 #define CMD_HDR_IPTT_OFF 0 356 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 357 /* dw6 */ 358 #define CMD_HDR_DIF_SGL_LEN_OFF 0 359 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 360 #define CMD_HDR_DATA_SGL_LEN_OFF 16 361 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 362 /* dw7 */ 363 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 364 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 365 #define CMD_HDR_ABORT_IPTT_OFF 16 366 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 367 368 /* Completion header */ 369 /* dw0 */ 370 #define CMPLT_HDR_CMPLT_OFF 0 371 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 372 #define CMPLT_HDR_ERROR_PHASE_OFF 2 373 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 374 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 375 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 376 #define CMPLT_HDR_ERX_OFF 12 377 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 378 #define CMPLT_HDR_ABORT_STAT_OFF 13 379 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 380 /* abort_stat */ 381 #define STAT_IO_NOT_VALID 0x1 382 #define STAT_IO_NO_DEVICE 0x2 383 #define STAT_IO_COMPLETE 0x3 384 #define STAT_IO_ABORTED 0x4 385 /* dw1 */ 386 #define CMPLT_HDR_IPTT_OFF 0 387 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 388 #define CMPLT_HDR_DEV_ID_OFF 16 389 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 390 /* dw3 */ 391 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 392 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 393 394 /* ITCT header */ 395 /* qw0 */ 396 #define ITCT_HDR_DEV_TYPE_OFF 0 397 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 398 #define ITCT_HDR_VALID_OFF 2 399 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 400 #define ITCT_HDR_MCR_OFF 5 401 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 402 #define ITCT_HDR_VLN_OFF 9 403 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 404 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 405 #define ITCT_HDR_AWT_CONTINUE_OFF 25 406 #define ITCT_HDR_PORT_ID_OFF 28 407 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 408 /* qw2 */ 409 #define ITCT_HDR_INLT_OFF 0 410 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 411 #define ITCT_HDR_RTOLT_OFF 48 412 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 413 414 struct hisi_sas_protect_iu_v3_hw { 415 u32 dw0; 416 u32 lbrtcv; 417 u32 lbrtgv; 418 u32 dw3; 419 u32 dw4; 420 u32 dw5; 421 u32 rsv; 422 }; 423 424 struct hisi_sas_complete_v3_hdr { 425 __le32 dw0; 426 __le32 dw1; 427 __le32 act; 428 __le32 dw3; 429 }; 430 431 struct hisi_sas_err_record_v3 { 432 /* dw0 */ 433 __le32 trans_tx_fail_type; 434 435 /* dw1 */ 436 __le32 trans_rx_fail_type; 437 438 /* dw2 */ 439 __le16 dma_tx_err_type; 440 __le16 sipc_rx_err_type; 441 442 /* dw3 */ 443 __le32 dma_rx_err_type; 444 }; 445 446 #define RX_DATA_LEN_UNDERFLOW_OFF 6 447 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 448 449 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 450 #define HISI_SAS_MSI_COUNT_V3_HW 32 451 452 #define DIR_NO_DATA 0 453 #define DIR_TO_INI 1 454 #define DIR_TO_DEVICE 2 455 #define DIR_RESERVED 3 456 457 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 458 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 459 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 460 ((fis.command == ATA_CMD_DEV_RESET) && \ 461 ((fis.control & ATA_SRST) != 0))) 462 463 #define T10_INSRT_EN_OFF 0 464 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 465 #define T10_RMV_EN_OFF 1 466 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 467 #define T10_RPLC_EN_OFF 2 468 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 469 #define T10_CHK_EN_OFF 3 470 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 471 #define INCR_LBRT_OFF 5 472 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 473 #define USR_DATA_BLOCK_SZ_OFF 20 474 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 475 #define T10_CHK_MSK_OFF 16 476 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 477 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 478 479 #define BASE_VECTORS_V3_HW 16 480 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) 481 482 enum { 483 DSM_FUNC_ERR_HANDLE_MSI = 0, 484 }; 485 486 static bool hisi_sas_intr_conv; 487 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 488 489 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 490 static int prot_mask; 491 module_param(prot_mask, int, 0); 492 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 493 494 static bool auto_affine_msi_experimental; 495 module_param(auto_affine_msi_experimental, bool, 0444); 496 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n" 497 "default is off"); 498 499 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 500 { 501 void __iomem *regs = hisi_hba->regs + off; 502 503 return readl(regs); 504 } 505 506 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 507 { 508 void __iomem *regs = hisi_hba->regs + off; 509 510 return readl_relaxed(regs); 511 } 512 513 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 514 { 515 void __iomem *regs = hisi_hba->regs + off; 516 517 writel(val, regs); 518 } 519 520 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 521 u32 off, u32 val) 522 { 523 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 524 525 writel(val, regs); 526 } 527 528 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 529 int phy_no, u32 off) 530 { 531 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 532 533 return readl(regs); 534 } 535 536 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 537 timeout_us) \ 538 ({ \ 539 void __iomem *regs = hisi_hba->regs + off; \ 540 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 541 }) 542 543 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 544 timeout_us) \ 545 ({ \ 546 void __iomem *regs = hisi_hba->regs + off; \ 547 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 548 }) 549 550 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 551 { 552 int i; 553 554 /* Global registers init */ 555 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 556 (u32)((1ULL << hisi_hba->queue_count) - 1)); 557 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 558 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 559 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 560 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 561 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 562 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 563 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 564 hisi_sas_intr_conv); 565 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 566 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 567 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 568 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 569 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 570 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 571 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff); 572 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 573 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 574 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 575 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555); 576 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 577 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 578 for (i = 0; i < hisi_hba->queue_count; i++) 579 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 580 581 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 582 583 for (i = 0; i < hisi_hba->n_phy; i++) { 584 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 585 struct asd_sas_phy *sas_phy = &phy->sas_phy; 586 u32 prog_phy_link_rate = 0x800; 587 588 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 589 SAS_LINK_RATE_1_5_GBPS)) { 590 prog_phy_link_rate = 0x855; 591 } else { 592 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 593 594 prog_phy_link_rate = 595 hisi_sas_get_prog_phy_linkrate_mask(max) | 596 0x800; 597 } 598 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 599 prog_phy_link_rate); 600 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); 601 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 602 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 603 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 604 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 605 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 606 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff); 607 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 608 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 609 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 610 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 611 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 612 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 613 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 614 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 615 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 616 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 617 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME, 618 0x30f4240); 619 /* used for 12G negotiate */ 620 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 621 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 622 } 623 624 for (i = 0; i < hisi_hba->queue_count; i++) { 625 /* Delivery queue */ 626 hisi_sas_write32(hisi_hba, 627 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 628 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 629 630 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 631 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 632 633 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 634 HISI_SAS_QUEUE_SLOTS); 635 636 /* Completion queue */ 637 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 638 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 639 640 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 641 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 642 643 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 644 HISI_SAS_QUEUE_SLOTS); 645 } 646 647 /* itct */ 648 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 649 lower_32_bits(hisi_hba->itct_dma)); 650 651 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 652 upper_32_bits(hisi_hba->itct_dma)); 653 654 /* iost */ 655 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 656 lower_32_bits(hisi_hba->iost_dma)); 657 658 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 659 upper_32_bits(hisi_hba->iost_dma)); 660 661 /* breakpoint */ 662 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 663 lower_32_bits(hisi_hba->breakpoint_dma)); 664 665 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 666 upper_32_bits(hisi_hba->breakpoint_dma)); 667 668 /* SATA broken msg */ 669 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 670 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 671 672 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 673 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 674 675 /* SATA initial fis */ 676 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 677 lower_32_bits(hisi_hba->initial_fis_dma)); 678 679 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 680 upper_32_bits(hisi_hba->initial_fis_dma)); 681 682 /* RAS registers init */ 683 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 684 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 685 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 686 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 687 688 /* LED registers init */ 689 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 690 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 691 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 692 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 693 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 694 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 695 } 696 697 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 698 { 699 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 700 701 cfg &= ~PHY_CFG_DC_OPT_MSK; 702 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 703 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 704 } 705 706 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 707 { 708 struct sas_identify_frame identify_frame; 709 u32 *identify_buffer; 710 711 memset(&identify_frame, 0, sizeof(identify_frame)); 712 identify_frame.dev_type = SAS_END_DEVICE; 713 identify_frame.frame_type = 0; 714 identify_frame._un1 = 1; 715 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 716 identify_frame.target_bits = SAS_PROTOCOL_NONE; 717 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 718 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 719 identify_frame.phy_id = phy_no; 720 identify_buffer = (u32 *)(&identify_frame); 721 722 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 723 __swab32(identify_buffer[0])); 724 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 725 __swab32(identify_buffer[1])); 726 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 727 __swab32(identify_buffer[2])); 728 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 729 __swab32(identify_buffer[3])); 730 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 731 __swab32(identify_buffer[4])); 732 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 733 __swab32(identify_buffer[5])); 734 } 735 736 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 737 struct hisi_sas_device *sas_dev) 738 { 739 struct domain_device *device = sas_dev->sas_device; 740 struct device *dev = hisi_hba->dev; 741 u64 qw0, device_id = sas_dev->device_id; 742 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 743 struct domain_device *parent_dev = device->parent; 744 struct asd_sas_port *sas_port = device->port; 745 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 746 u64 sas_addr; 747 748 memset(itct, 0, sizeof(*itct)); 749 750 /* qw0 */ 751 qw0 = 0; 752 switch (sas_dev->dev_type) { 753 case SAS_END_DEVICE: 754 case SAS_EDGE_EXPANDER_DEVICE: 755 case SAS_FANOUT_EXPANDER_DEVICE: 756 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 757 break; 758 case SAS_SATA_DEV: 759 case SAS_SATA_PENDING: 760 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 761 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 762 else 763 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 764 break; 765 default: 766 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 767 sas_dev->dev_type); 768 } 769 770 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 771 (device->linkrate << ITCT_HDR_MCR_OFF) | 772 (1 << ITCT_HDR_VLN_OFF) | 773 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 774 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 775 (port->id << ITCT_HDR_PORT_ID_OFF)); 776 itct->qw0 = cpu_to_le64(qw0); 777 778 /* qw1 */ 779 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 780 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 781 782 /* qw2 */ 783 if (!dev_is_sata(device)) 784 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 785 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 786 } 787 788 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 789 struct hisi_sas_device *sas_dev) 790 { 791 DECLARE_COMPLETION_ONSTACK(completion); 792 u64 dev_id = sas_dev->device_id; 793 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 794 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 795 796 sas_dev->completion = &completion; 797 798 /* clear the itct interrupt state */ 799 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 800 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 801 ENT_INT_SRC3_ITC_INT_MSK); 802 803 /* clear the itct table */ 804 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 805 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 806 807 wait_for_completion(sas_dev->completion); 808 memset(itct, 0, sizeof(struct hisi_sas_itct)); 809 } 810 811 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 812 struct domain_device *device) 813 { 814 struct hisi_sas_slot *slot, *slot2; 815 struct hisi_sas_device *sas_dev = device->lldd_dev; 816 u32 cfg_abt_set_query_iptt; 817 818 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 819 CFG_ABT_SET_QUERY_IPTT); 820 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 821 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 822 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 823 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 824 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 825 cfg_abt_set_query_iptt); 826 } 827 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 828 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 829 cfg_abt_set_query_iptt); 830 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 831 1 << CFG_ABT_SET_IPTT_DONE_OFF); 832 } 833 834 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 835 { 836 struct device *dev = hisi_hba->dev; 837 int ret; 838 u32 val; 839 840 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 841 842 /* Disable all of the PHYs */ 843 hisi_sas_stop_phys(hisi_hba); 844 udelay(50); 845 846 /* Ensure axi bus idle */ 847 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 848 20000, 1000000); 849 if (ret) { 850 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 851 return -EIO; 852 } 853 854 if (ACPI_HANDLE(dev)) { 855 acpi_status s; 856 857 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 858 if (ACPI_FAILURE(s)) { 859 dev_err(dev, "Reset failed\n"); 860 return -EIO; 861 } 862 } else { 863 dev_err(dev, "no reset method!\n"); 864 return -EINVAL; 865 } 866 867 return 0; 868 } 869 870 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 871 { 872 struct device *dev = hisi_hba->dev; 873 union acpi_object *obj; 874 guid_t guid; 875 int rc; 876 877 rc = reset_hw_v3_hw(hisi_hba); 878 if (rc) { 879 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 880 return rc; 881 } 882 883 msleep(100); 884 init_reg_v3_hw(hisi_hba); 885 886 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) { 887 dev_err(dev, "Parse GUID failed\n"); 888 return -EINVAL; 889 } 890 891 /* Switch over to MSI handling , from PCI AER default */ 892 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, 893 DSM_FUNC_ERR_HANDLE_MSI, NULL); 894 if (!obj) 895 dev_warn(dev, "Switch over to MSI handling failed\n"); 896 else 897 ACPI_FREE(obj); 898 899 return 0; 900 } 901 902 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 903 { 904 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 905 906 cfg |= PHY_CFG_ENA_MSK; 907 cfg &= ~PHY_CFG_PHY_RST_MSK; 908 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 909 } 910 911 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 912 { 913 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 914 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 915 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 916 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 917 BIT(CHL_INT2_RX_INVLD_DW_OFF); 918 u32 state; 919 920 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); 921 922 cfg &= ~PHY_CFG_ENA_MSK; 923 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 924 925 mdelay(50); 926 927 state = hisi_sas_read32(hisi_hba, PHY_STATE); 928 if (state & BIT(phy_no)) { 929 cfg |= PHY_CFG_PHY_RST_MSK; 930 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 931 } 932 933 udelay(1); 934 935 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 936 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 937 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 938 939 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); 940 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); 941 } 942 943 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 944 { 945 config_id_frame_v3_hw(hisi_hba, phy_no); 946 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 947 enable_phy_v3_hw(hisi_hba, phy_no); 948 } 949 950 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 951 { 952 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 953 u32 txid_auto; 954 955 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 956 if (phy->identify.device_type == SAS_END_DEVICE) { 957 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 958 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 959 txid_auto | TX_HARDRST_MSK); 960 } 961 msleep(100); 962 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 963 } 964 965 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 966 { 967 return SAS_LINK_RATE_12_0_GBPS; 968 } 969 970 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 971 { 972 int i; 973 974 for (i = 0; i < hisi_hba->n_phy; i++) { 975 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 976 struct asd_sas_phy *sas_phy = &phy->sas_phy; 977 978 if (!sas_phy->phy->enabled) 979 continue; 980 981 hisi_sas_phy_enable(hisi_hba, i, 1); 982 } 983 } 984 985 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 986 { 987 u32 sl_control; 988 989 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 990 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 991 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 992 msleep(1); 993 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 994 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 995 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 996 } 997 998 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 999 { 1000 int i, bitmap = 0; 1001 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1002 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1003 1004 for (i = 0; i < hisi_hba->n_phy; i++) 1005 if (phy_state & BIT(i)) 1006 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 1007 bitmap |= BIT(i); 1008 1009 return bitmap; 1010 } 1011 1012 /** 1013 * The callpath to this function and upto writing the write 1014 * queue pointer should be safe from interruption. 1015 */ 1016 static int 1017 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 1018 { 1019 struct device *dev = hisi_hba->dev; 1020 int queue = dq->id; 1021 u32 r, w; 1022 1023 w = dq->wr_point; 1024 r = hisi_sas_read32_relaxed(hisi_hba, 1025 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 1026 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 1027 dev_warn(dev, "full queue=%d r=%d w=%d\n", 1028 queue, r, w); 1029 return -EAGAIN; 1030 } 1031 1032 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 1033 1034 return w; 1035 } 1036 1037 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 1038 { 1039 struct hisi_hba *hisi_hba = dq->hisi_hba; 1040 struct hisi_sas_slot *s, *s1, *s2 = NULL; 1041 int dlvry_queue = dq->id; 1042 int wp; 1043 1044 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 1045 if (!s->ready) 1046 break; 1047 s2 = s; 1048 list_del(&s->delivery); 1049 } 1050 1051 if (!s2) 1052 return; 1053 1054 /* 1055 * Ensure that memories for slots built on other CPUs is observed. 1056 */ 1057 smp_rmb(); 1058 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 1059 1060 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 1061 } 1062 1063 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 1064 struct hisi_sas_slot *slot, 1065 struct hisi_sas_cmd_hdr *hdr, 1066 struct scatterlist *scatter, 1067 int n_elem) 1068 { 1069 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 1070 struct scatterlist *sg; 1071 int i; 1072 1073 for_each_sg(scatter, sg, n_elem, i) { 1074 struct hisi_sas_sge *entry = &sge_page->sge[i]; 1075 1076 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1077 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1078 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1079 entry->data_off = 0; 1080 } 1081 1082 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 1083 1084 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1085 } 1086 1087 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 1088 struct hisi_sas_slot *slot, 1089 struct hisi_sas_cmd_hdr *hdr, 1090 struct scatterlist *scatter, 1091 int n_elem) 1092 { 1093 struct hisi_sas_sge_dif_page *sge_dif_page; 1094 struct scatterlist *sg; 1095 int i; 1096 1097 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 1098 1099 for_each_sg(scatter, sg, n_elem, i) { 1100 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 1101 1102 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1103 entry->page_ctrl_0 = 0; 1104 entry->page_ctrl_1 = 0; 1105 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1106 entry->data_off = 0; 1107 } 1108 1109 hdr->dif_prd_table_addr = 1110 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1111 1112 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1113 } 1114 1115 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1116 { 1117 unsigned char prot_flags = scsi_cmnd->prot_flags; 1118 1119 if (prot_flags & SCSI_PROT_REF_CHECK) 1120 return T10_CHK_APP_TAG_MSK; 1121 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1122 } 1123 1124 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1125 struct hisi_sas_protect_iu_v3_hw *prot) 1126 { 1127 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1128 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1129 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1130 1131 switch (prot_op) { 1132 case SCSI_PROT_READ_INSERT: 1133 prot->dw0 |= T10_INSRT_EN_MSK; 1134 prot->lbrtgv = lbrt_chk_val; 1135 break; 1136 case SCSI_PROT_READ_STRIP: 1137 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1138 prot->lbrtcv = lbrt_chk_val; 1139 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1140 break; 1141 case SCSI_PROT_READ_PASS: 1142 prot->dw0 |= T10_CHK_EN_MSK; 1143 prot->lbrtcv = lbrt_chk_val; 1144 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1145 break; 1146 case SCSI_PROT_WRITE_INSERT: 1147 prot->dw0 |= T10_INSRT_EN_MSK; 1148 prot->lbrtgv = lbrt_chk_val; 1149 break; 1150 case SCSI_PROT_WRITE_STRIP: 1151 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1152 prot->lbrtcv = lbrt_chk_val; 1153 break; 1154 case SCSI_PROT_WRITE_PASS: 1155 prot->dw0 |= T10_CHK_EN_MSK; 1156 prot->lbrtcv = lbrt_chk_val; 1157 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1158 break; 1159 default: 1160 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1161 break; 1162 } 1163 1164 switch (interval) { 1165 case 512: 1166 break; 1167 case 4096: 1168 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1169 break; 1170 case 520: 1171 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1172 break; 1173 default: 1174 WARN(1, "protection interval (0x%x) invalid\n", 1175 interval); 1176 break; 1177 } 1178 1179 prot->dw0 |= INCR_LBRT_MSK; 1180 } 1181 1182 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1183 struct hisi_sas_slot *slot) 1184 { 1185 struct sas_task *task = slot->task; 1186 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1187 struct domain_device *device = task->dev; 1188 struct hisi_sas_device *sas_dev = device->lldd_dev; 1189 struct hisi_sas_port *port = slot->port; 1190 struct sas_ssp_task *ssp_task = &task->ssp_task; 1191 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1192 struct hisi_sas_tmf_task *tmf = slot->tmf; 1193 int has_data = 0, priority = !!tmf; 1194 unsigned char prot_op; 1195 u8 *buf_cmd; 1196 u32 dw1 = 0, dw2 = 0, len = 0; 1197 1198 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1199 (2 << CMD_HDR_TLR_CTRL_OFF) | 1200 (port->id << CMD_HDR_PORT_OFF) | 1201 (priority << CMD_HDR_PRIORITY_OFF) | 1202 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1203 1204 dw1 = 1 << CMD_HDR_VDTL_OFF; 1205 if (tmf) { 1206 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1207 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1208 } else { 1209 prot_op = scsi_get_prot_op(scsi_cmnd); 1210 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1211 switch (scsi_cmnd->sc_data_direction) { 1212 case DMA_TO_DEVICE: 1213 has_data = 1; 1214 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1215 break; 1216 case DMA_FROM_DEVICE: 1217 has_data = 1; 1218 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1219 break; 1220 default: 1221 dw1 &= ~CMD_HDR_DIR_MSK; 1222 } 1223 } 1224 1225 /* map itct entry */ 1226 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1227 1228 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1229 + 3) / 4) << CMD_HDR_CFL_OFF) | 1230 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1231 (2 << CMD_HDR_SG_MOD_OFF); 1232 hdr->dw2 = cpu_to_le32(dw2); 1233 hdr->transfer_tags = cpu_to_le32(slot->idx); 1234 1235 if (has_data) { 1236 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1237 slot->n_elem); 1238 1239 if (scsi_prot_sg_count(scsi_cmnd)) 1240 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1241 scsi_prot_sglist(scsi_cmnd), 1242 slot->n_elem_dif); 1243 } 1244 1245 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1246 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1247 1248 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1249 sizeof(struct ssp_frame_hdr); 1250 1251 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1252 if (!tmf) { 1253 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1254 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1255 } else { 1256 buf_cmd[10] = tmf->tmf; 1257 switch (tmf->tmf) { 1258 case TMF_ABORT_TASK: 1259 case TMF_QUERY_TASK: 1260 buf_cmd[12] = 1261 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1262 buf_cmd[13] = 1263 tmf->tag_of_task_to_be_managed & 0xff; 1264 break; 1265 default: 1266 break; 1267 } 1268 } 1269 1270 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1271 struct hisi_sas_protect_iu_v3_hw prot; 1272 u8 *buf_cmd_prot; 1273 1274 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1275 dw1 |= CMD_HDR_PIR_MSK; 1276 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1277 sizeof(struct ssp_frame_hdr) + 1278 sizeof(struct ssp_command_iu); 1279 1280 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1281 fill_prot_v3_hw(scsi_cmnd, &prot); 1282 memcpy(buf_cmd_prot, &prot, 1283 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1284 /* 1285 * For READ, we need length of info read to memory, while for 1286 * WRITE we need length of data written to the disk. 1287 */ 1288 if (prot_op == SCSI_PROT_WRITE_INSERT || 1289 prot_op == SCSI_PROT_READ_INSERT || 1290 prot_op == SCSI_PROT_WRITE_PASS || 1291 prot_op == SCSI_PROT_READ_PASS) { 1292 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1293 unsigned int ilog2_interval = ilog2(interval); 1294 1295 len = (task->total_xfer_len >> ilog2_interval) * 8; 1296 } 1297 } 1298 1299 hdr->dw1 = cpu_to_le32(dw1); 1300 1301 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1302 } 1303 1304 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1305 struct hisi_sas_slot *slot) 1306 { 1307 struct sas_task *task = slot->task; 1308 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1309 struct domain_device *device = task->dev; 1310 struct hisi_sas_port *port = slot->port; 1311 struct scatterlist *sg_req; 1312 struct hisi_sas_device *sas_dev = device->lldd_dev; 1313 dma_addr_t req_dma_addr; 1314 unsigned int req_len; 1315 1316 /* req */ 1317 sg_req = &task->smp_task.smp_req; 1318 req_len = sg_dma_len(sg_req); 1319 req_dma_addr = sg_dma_address(sg_req); 1320 1321 /* create header */ 1322 /* dw0 */ 1323 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1324 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1325 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1326 1327 /* map itct entry */ 1328 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1329 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1330 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1331 1332 /* dw2 */ 1333 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1334 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1335 CMD_HDR_MRFL_OFF)); 1336 1337 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1338 1339 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1340 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1341 1342 } 1343 1344 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1345 struct hisi_sas_slot *slot) 1346 { 1347 struct sas_task *task = slot->task; 1348 struct domain_device *device = task->dev; 1349 struct domain_device *parent_dev = device->parent; 1350 struct hisi_sas_device *sas_dev = device->lldd_dev; 1351 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1352 struct asd_sas_port *sas_port = device->port; 1353 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1354 u8 *buf_cmd; 1355 int has_data = 0, hdr_tag = 0; 1356 u32 dw1 = 0, dw2 = 0; 1357 1358 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1359 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1360 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1361 else 1362 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF); 1363 1364 switch (task->data_dir) { 1365 case DMA_TO_DEVICE: 1366 has_data = 1; 1367 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1368 break; 1369 case DMA_FROM_DEVICE: 1370 has_data = 1; 1371 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1372 break; 1373 default: 1374 dw1 &= ~CMD_HDR_DIR_MSK; 1375 } 1376 1377 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1378 (task->ata_task.fis.control & ATA_SRST)) 1379 dw1 |= 1 << CMD_HDR_RESET_OFF; 1380 1381 dw1 |= (hisi_sas_get_ata_protocol( 1382 &task->ata_task.fis, task->data_dir)) 1383 << CMD_HDR_FRAME_TYPE_OFF; 1384 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1385 1386 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1387 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1388 1389 hdr->dw1 = cpu_to_le32(dw1); 1390 1391 /* dw2 */ 1392 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1393 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1394 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1395 } 1396 1397 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1398 2 << CMD_HDR_SG_MOD_OFF; 1399 hdr->dw2 = cpu_to_le32(dw2); 1400 1401 /* dw3 */ 1402 hdr->transfer_tags = cpu_to_le32(slot->idx); 1403 1404 if (has_data) 1405 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1406 slot->n_elem); 1407 1408 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1409 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1410 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1411 1412 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1413 1414 if (likely(!task->ata_task.device_control_reg_update)) 1415 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1416 /* fill in command FIS */ 1417 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1418 } 1419 1420 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1421 struct hisi_sas_slot *slot, 1422 int device_id, int abort_flag, int tag_to_abort) 1423 { 1424 struct sas_task *task = slot->task; 1425 struct domain_device *dev = task->dev; 1426 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1427 struct hisi_sas_port *port = slot->port; 1428 1429 /* dw0 */ 1430 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/ 1431 (port->id << CMD_HDR_PORT_OFF) | 1432 (dev_is_sata(dev) 1433 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1434 (abort_flag 1435 << CMD_HDR_ABORT_FLAG_OFF)); 1436 1437 /* dw1 */ 1438 hdr->dw1 = cpu_to_le32(device_id 1439 << CMD_HDR_DEV_ID_OFF); 1440 1441 /* dw7 */ 1442 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1443 hdr->transfer_tags = cpu_to_le32(slot->idx); 1444 1445 } 1446 1447 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1448 { 1449 int i; 1450 irqreturn_t res; 1451 u32 context, port_id, link_rate; 1452 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1453 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1454 struct device *dev = hisi_hba->dev; 1455 unsigned long flags; 1456 1457 del_timer(&phy->timer); 1458 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1459 1460 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1461 port_id = (port_id >> (4 * phy_no)) & 0xf; 1462 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1463 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1464 1465 if (port_id == 0xf) { 1466 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1467 res = IRQ_NONE; 1468 goto end; 1469 } 1470 sas_phy->linkrate = link_rate; 1471 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1472 1473 /* Check for SATA dev */ 1474 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1475 if (context & (1 << phy_no)) { 1476 struct hisi_sas_initial_fis *initial_fis; 1477 struct dev_to_host_fis *fis; 1478 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1479 struct Scsi_Host *shost = hisi_hba->shost; 1480 1481 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1482 initial_fis = &hisi_hba->initial_fis[phy_no]; 1483 fis = &initial_fis->fis; 1484 1485 /* check ERR bit of Status Register */ 1486 if (fis->status & ATA_ERR) { 1487 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1488 phy_no, fis->status); 1489 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1490 res = IRQ_NONE; 1491 goto end; 1492 } 1493 1494 sas_phy->oob_mode = SATA_OOB_MODE; 1495 attached_sas_addr[0] = 0x50; 1496 attached_sas_addr[6] = shost->host_no; 1497 attached_sas_addr[7] = phy_no; 1498 memcpy(sas_phy->attached_sas_addr, 1499 attached_sas_addr, 1500 SAS_ADDR_SIZE); 1501 memcpy(sas_phy->frame_rcvd, fis, 1502 sizeof(struct dev_to_host_fis)); 1503 phy->phy_type |= PORT_TYPE_SATA; 1504 phy->identify.device_type = SAS_SATA_DEV; 1505 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1506 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1507 } else { 1508 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1509 struct sas_identify_frame *id = 1510 (struct sas_identify_frame *)frame_rcvd; 1511 1512 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1513 for (i = 0; i < 6; i++) { 1514 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1515 RX_IDAF_DWORD0 + (i * 4)); 1516 frame_rcvd[i] = __swab32(idaf); 1517 } 1518 sas_phy->oob_mode = SAS_OOB_MODE; 1519 memcpy(sas_phy->attached_sas_addr, 1520 &id->sas_addr, 1521 SAS_ADDR_SIZE); 1522 phy->phy_type |= PORT_TYPE_SAS; 1523 phy->identify.device_type = id->dev_type; 1524 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1525 if (phy->identify.device_type == SAS_END_DEVICE) 1526 phy->identify.target_port_protocols = 1527 SAS_PROTOCOL_SSP; 1528 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1529 phy->identify.target_port_protocols = 1530 SAS_PROTOCOL_SMP; 1531 } 1532 1533 phy->port_id = port_id; 1534 phy->phy_attached = 1; 1535 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1536 res = IRQ_HANDLED; 1537 spin_lock_irqsave(&phy->lock, flags); 1538 if (phy->reset_completion) { 1539 phy->in_reset = 0; 1540 complete(phy->reset_completion); 1541 } 1542 spin_unlock_irqrestore(&phy->lock, flags); 1543 end: 1544 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1545 CHL_INT0_SL_PHY_ENABLE_MSK); 1546 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1547 1548 return res; 1549 } 1550 1551 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1552 { 1553 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1554 u32 phy_state, sl_ctrl, txid_auto; 1555 struct device *dev = hisi_hba->dev; 1556 1557 del_timer(&phy->timer); 1558 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1559 1560 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1561 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1562 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1563 1564 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1565 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1566 sl_ctrl&(~SL_CTA_MSK)); 1567 1568 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1569 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1570 txid_auto | CT3_MSK); 1571 1572 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1573 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1574 1575 return IRQ_HANDLED; 1576 } 1577 1578 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1579 { 1580 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1581 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1582 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1583 u32 bcast_status; 1584 1585 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1586 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1587 if ((bcast_status & RX_BCAST_CHG_MSK) && 1588 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1589 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1590 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1591 CHL_INT0_SL_RX_BCST_ACK_MSK); 1592 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1593 1594 return IRQ_HANDLED; 1595 } 1596 1597 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1598 { 1599 struct hisi_hba *hisi_hba = p; 1600 u32 irq_msk; 1601 int phy_no = 0; 1602 irqreturn_t res = IRQ_NONE; 1603 1604 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1605 & 0x11111111; 1606 while (irq_msk) { 1607 if (irq_msk & 1) { 1608 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1609 CHL_INT0); 1610 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1611 int rdy = phy_state & (1 << phy_no); 1612 1613 if (rdy) { 1614 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1615 /* phy up */ 1616 if (phy_up_v3_hw(phy_no, hisi_hba) 1617 == IRQ_HANDLED) 1618 res = IRQ_HANDLED; 1619 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1620 /* phy bcast */ 1621 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1622 == IRQ_HANDLED) 1623 res = IRQ_HANDLED; 1624 } else { 1625 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1626 /* phy down */ 1627 if (phy_down_v3_hw(phy_no, hisi_hba) 1628 == IRQ_HANDLED) 1629 res = IRQ_HANDLED; 1630 } 1631 } 1632 irq_msk >>= 4; 1633 phy_no++; 1634 } 1635 1636 return res; 1637 } 1638 1639 static const struct hisi_sas_hw_error port_axi_error[] = { 1640 { 1641 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF), 1642 .msg = "dmac_tx_ecc_bad_err", 1643 }, 1644 { 1645 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF), 1646 .msg = "dmac_rx_ecc_bad_err", 1647 }, 1648 { 1649 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1650 .msg = "dma_tx_axi_wr_err", 1651 }, 1652 { 1653 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1654 .msg = "dma_tx_axi_rd_err", 1655 }, 1656 { 1657 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1658 .msg = "dma_rx_axi_wr_err", 1659 }, 1660 { 1661 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1662 .msg = "dma_rx_axi_rd_err", 1663 }, 1664 { 1665 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF), 1666 .msg = "dma_tx_fifo_err", 1667 }, 1668 { 1669 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF), 1670 .msg = "dma_rx_fifo_err", 1671 }, 1672 { 1673 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF), 1674 .msg = "dma_tx_axi_ruser_err", 1675 }, 1676 { 1677 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF), 1678 .msg = "dma_rx_axi_ruser_err", 1679 }, 1680 }; 1681 1682 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1683 { 1684 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1685 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1686 struct device *dev = hisi_hba->dev; 1687 int i; 1688 1689 irq_value &= ~irq_msk; 1690 if (!irq_value) 1691 return; 1692 1693 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1694 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1695 1696 if (!(irq_value & error->irq_msk)) 1697 continue; 1698 1699 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1700 error->msg, phy_no, irq_value); 1701 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1702 } 1703 1704 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1705 } 1706 1707 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1708 { 1709 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1710 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1711 struct sas_phy *sphy = sas_phy->phy; 1712 unsigned long flags; 1713 u32 reg_value; 1714 1715 spin_lock_irqsave(&phy->lock, flags); 1716 1717 /* loss dword sync */ 1718 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1719 sphy->loss_of_dword_sync_count += reg_value; 1720 1721 /* phy reset problem */ 1722 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1723 sphy->phy_reset_problem_count += reg_value; 1724 1725 /* invalid dword */ 1726 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1727 sphy->invalid_dword_count += reg_value; 1728 1729 /* disparity err */ 1730 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1731 sphy->running_disparity_error_count += reg_value; 1732 1733 /* code violation error */ 1734 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 1735 phy->code_violation_err_count += reg_value; 1736 1737 spin_unlock_irqrestore(&phy->lock, flags); 1738 } 1739 1740 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1741 { 1742 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1743 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1744 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1745 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1746 struct device *dev = hisi_hba->dev; 1747 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 1748 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 1749 BIT(CHL_INT2_RX_INVLD_DW_OFF); 1750 1751 irq_value &= ~irq_msk; 1752 if (!irq_value) 1753 return; 1754 1755 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1756 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1757 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1758 } 1759 1760 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1761 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1762 STP_LINK_TIMEOUT_STATE); 1763 1764 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1765 phy_no, reg_value); 1766 if (reg_value & BIT(4)) 1767 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1768 } 1769 1770 if (pci_dev->revision > 0x20 && (irq_value & msk)) { 1771 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1772 struct sas_phy *sphy = sas_phy->phy; 1773 1774 phy_get_events_v3_hw(hisi_hba, phy_no); 1775 1776 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) 1777 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no, 1778 sphy->invalid_dword_count); 1779 1780 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF)) 1781 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no, 1782 phy->code_violation_err_count); 1783 1784 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF)) 1785 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no, 1786 sphy->running_disparity_error_count); 1787 } 1788 1789 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1790 (pci_dev->revision == 0x20)) { 1791 u32 reg_value; 1792 int rc; 1793 1794 rc = hisi_sas_read32_poll_timeout_atomic( 1795 HILINK_ERR_DFX, reg_value, 1796 !((reg_value >> 8) & BIT(phy_no)), 1797 1000, 10000); 1798 if (rc) 1799 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1800 } 1801 1802 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1803 } 1804 1805 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1806 { 1807 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1808 1809 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1810 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1811 1812 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1813 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1814 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1815 & (~CHL_INT0_NOT_RDY_MSK)); 1816 } 1817 1818 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1819 { 1820 struct hisi_hba *hisi_hba = p; 1821 u32 irq_msk; 1822 int phy_no = 0; 1823 1824 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1825 & 0xeeeeeeee; 1826 1827 while (irq_msk) { 1828 if (irq_msk & (2 << (phy_no * 4))) 1829 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1830 1831 if (irq_msk & (4 << (phy_no * 4))) 1832 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1833 1834 if (irq_msk & (8 << (phy_no * 4))) 1835 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1836 1837 irq_msk &= ~(0xe << (phy_no * 4)); 1838 phy_no++; 1839 } 1840 1841 return IRQ_HANDLED; 1842 } 1843 1844 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { 1845 { 1846 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), 1847 .msk = HGC_DQE_ECC_MB_ADDR_MSK, 1848 .shift = HGC_DQE_ECC_MB_ADDR_OFF, 1849 .msg = "hgc_dqe_eccbad_intr", 1850 .reg = HGC_DQE_ECC_ADDR, 1851 }, 1852 { 1853 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), 1854 .msk = HGC_IOST_ECC_MB_ADDR_MSK, 1855 .shift = HGC_IOST_ECC_MB_ADDR_OFF, 1856 .msg = "hgc_iost_eccbad_intr", 1857 .reg = HGC_IOST_ECC_ADDR, 1858 }, 1859 { 1860 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), 1861 .msk = HGC_ITCT_ECC_MB_ADDR_MSK, 1862 .shift = HGC_ITCT_ECC_MB_ADDR_OFF, 1863 .msg = "hgc_itct_eccbad_intr", 1864 .reg = HGC_ITCT_ECC_ADDR, 1865 }, 1866 { 1867 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), 1868 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, 1869 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, 1870 .msg = "hgc_iostl_eccbad_intr", 1871 .reg = HGC_LM_DFX_STATUS2, 1872 }, 1873 { 1874 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), 1875 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, 1876 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, 1877 .msg = "hgc_itctl_eccbad_intr", 1878 .reg = HGC_LM_DFX_STATUS2, 1879 }, 1880 { 1881 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), 1882 .msk = HGC_CQE_ECC_MB_ADDR_MSK, 1883 .shift = HGC_CQE_ECC_MB_ADDR_OFF, 1884 .msg = "hgc_cqe_eccbad_intr", 1885 .reg = HGC_CQE_ECC_ADDR, 1886 }, 1887 { 1888 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), 1889 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, 1890 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, 1891 .msg = "rxm_mem0_eccbad_intr", 1892 .reg = HGC_RXM_DFX_STATUS14, 1893 }, 1894 { 1895 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), 1896 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, 1897 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, 1898 .msg = "rxm_mem1_eccbad_intr", 1899 .reg = HGC_RXM_DFX_STATUS14, 1900 }, 1901 { 1902 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), 1903 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, 1904 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, 1905 .msg = "rxm_mem2_eccbad_intr", 1906 .reg = HGC_RXM_DFX_STATUS14, 1907 }, 1908 { 1909 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), 1910 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, 1911 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, 1912 .msg = "rxm_mem3_eccbad_intr", 1913 .reg = HGC_RXM_DFX_STATUS15, 1914 }, 1915 { 1916 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), 1917 .msk = AM_ROB_ECC_ERR_ADDR_MSK, 1918 .shift = AM_ROB_ECC_ERR_ADDR_OFF, 1919 .msg = "ooo_ram_eccbad_intr", 1920 .reg = AM_ROB_ECC_ERR_ADDR, 1921 }, 1922 }; 1923 1924 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, 1925 u32 irq_value) 1926 { 1927 struct device *dev = hisi_hba->dev; 1928 const struct hisi_sas_hw_error *ecc_error; 1929 u32 val; 1930 int i; 1931 1932 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { 1933 ecc_error = &multi_bit_ecc_errors[i]; 1934 if (irq_value & ecc_error->irq_msk) { 1935 val = hisi_sas_read32(hisi_hba, ecc_error->reg); 1936 val &= ecc_error->msk; 1937 val >>= ecc_error->shift; 1938 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", 1939 ecc_error->msg, irq_value, val); 1940 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1941 } 1942 } 1943 } 1944 1945 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba) 1946 { 1947 u32 irq_value, irq_msk; 1948 1949 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); 1950 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff); 1951 1952 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1953 if (irq_value) 1954 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); 1955 1956 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); 1957 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); 1958 } 1959 1960 static const struct hisi_sas_hw_error axi_error[] = { 1961 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1962 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1963 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1964 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1965 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1966 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1967 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1968 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1969 {} 1970 }; 1971 1972 static const struct hisi_sas_hw_error fifo_error[] = { 1973 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1974 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1975 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1976 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1977 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1978 {} 1979 }; 1980 1981 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1982 { 1983 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1984 .msg = "write pointer and depth", 1985 }, 1986 { 1987 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1988 .msg = "iptt no match slot", 1989 }, 1990 { 1991 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1992 .msg = "read pointer and depth", 1993 }, 1994 { 1995 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1996 .reg = HGC_AXI_FIFO_ERR_INFO, 1997 .sub = axi_error, 1998 }, 1999 { 2000 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 2001 .reg = HGC_AXI_FIFO_ERR_INFO, 2002 .sub = fifo_error, 2003 }, 2004 { 2005 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 2006 .msg = "LM add/fetch list", 2007 }, 2008 { 2009 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 2010 .msg = "SAS_HGC_ABT fetch LM list", 2011 }, 2012 { 2013 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF), 2014 .msg = "read dqe poison", 2015 }, 2016 { 2017 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF), 2018 .msg = "read iost poison", 2019 }, 2020 { 2021 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF), 2022 .msg = "read itct poison", 2023 }, 2024 { 2025 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF), 2026 .msg = "read itct ncq poison", 2027 }, 2028 2029 }; 2030 2031 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 2032 { 2033 u32 irq_value, irq_msk; 2034 struct hisi_hba *hisi_hba = p; 2035 struct device *dev = hisi_hba->dev; 2036 struct pci_dev *pdev = hisi_hba->pci_dev; 2037 int i; 2038 2039 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2040 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 2041 2042 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 2043 irq_value &= ~irq_msk; 2044 2045 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 2046 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 2047 2048 if (!(irq_value & error->irq_msk)) 2049 continue; 2050 2051 if (error->sub) { 2052 const struct hisi_sas_hw_error *sub = error->sub; 2053 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 2054 2055 for (; sub->msk || sub->msg; sub++) { 2056 if (!(err_value & sub->msk)) 2057 continue; 2058 2059 dev_err(dev, "%s error (0x%x) found!\n", 2060 sub->msg, irq_value); 2061 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2062 } 2063 } else { 2064 dev_err(dev, "%s error (0x%x) found!\n", 2065 error->msg, irq_value); 2066 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2067 } 2068 2069 if (pdev->revision < 0x21) { 2070 u32 reg_val; 2071 2072 reg_val = hisi_sas_read32(hisi_hba, 2073 AXI_MASTER_CFG_BASE + 2074 AM_CTRL_GLOBAL); 2075 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2076 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2077 AM_CTRL_GLOBAL, reg_val); 2078 } 2079 } 2080 2081 fatal_ecc_int_v3_hw(hisi_hba); 2082 2083 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 2084 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 2085 u32 dev_id = reg_val & ITCT_DEV_MSK; 2086 struct hisi_sas_device *sas_dev = 2087 &hisi_hba->devices[dev_id]; 2088 2089 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 2090 dev_dbg(dev, "clear ITCT ok\n"); 2091 complete(sas_dev->completion); 2092 } 2093 2094 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 2095 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 2096 2097 return IRQ_HANDLED; 2098 } 2099 2100 static void 2101 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 2102 struct hisi_sas_slot *slot) 2103 { 2104 struct task_status_struct *ts = &task->task_status; 2105 struct hisi_sas_complete_v3_hdr *complete_queue = 2106 hisi_hba->complete_hdr[slot->cmplt_queue]; 2107 struct hisi_sas_complete_v3_hdr *complete_hdr = 2108 &complete_queue[slot->cmplt_queue_slot]; 2109 struct hisi_sas_err_record_v3 *record = 2110 hisi_sas_status_buf_addr_mem(slot); 2111 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 2112 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 2113 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 2114 2115 switch (task->task_proto) { 2116 case SAS_PROTOCOL_SSP: 2117 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2118 ts->residual = trans_tx_fail_type; 2119 ts->stat = SAS_DATA_UNDERRUN; 2120 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2121 ts->stat = SAS_QUEUE_FULL; 2122 slot->abort = 1; 2123 } else { 2124 ts->stat = SAS_OPEN_REJECT; 2125 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2126 } 2127 break; 2128 case SAS_PROTOCOL_SATA: 2129 case SAS_PROTOCOL_STP: 2130 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2131 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2132 ts->residual = trans_tx_fail_type; 2133 ts->stat = SAS_DATA_UNDERRUN; 2134 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2135 ts->stat = SAS_PHY_DOWN; 2136 slot->abort = 1; 2137 } else { 2138 ts->stat = SAS_OPEN_REJECT; 2139 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2140 } 2141 hisi_sas_sata_done(task, slot); 2142 break; 2143 case SAS_PROTOCOL_SMP: 2144 ts->stat = SAM_STAT_CHECK_CONDITION; 2145 break; 2146 default: 2147 break; 2148 } 2149 } 2150 2151 static int 2152 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 2153 { 2154 struct sas_task *task = slot->task; 2155 struct hisi_sas_device *sas_dev; 2156 struct device *dev = hisi_hba->dev; 2157 struct task_status_struct *ts; 2158 struct domain_device *device; 2159 struct sas_ha_struct *ha; 2160 enum exec_status sts; 2161 struct hisi_sas_complete_v3_hdr *complete_queue = 2162 hisi_hba->complete_hdr[slot->cmplt_queue]; 2163 struct hisi_sas_complete_v3_hdr *complete_hdr = 2164 &complete_queue[slot->cmplt_queue_slot]; 2165 unsigned long flags; 2166 bool is_internal = slot->is_internal; 2167 u32 dw0, dw1, dw3; 2168 2169 if (unlikely(!task || !task->lldd_task || !task->dev)) 2170 return -EINVAL; 2171 2172 ts = &task->task_status; 2173 device = task->dev; 2174 ha = device->port->ha; 2175 sas_dev = device->lldd_dev; 2176 2177 spin_lock_irqsave(&task->task_state_lock, flags); 2178 task->task_state_flags &= 2179 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 2180 spin_unlock_irqrestore(&task->task_state_lock, flags); 2181 2182 memset(ts, 0, sizeof(*ts)); 2183 ts->resp = SAS_TASK_COMPLETE; 2184 2185 if (unlikely(!sas_dev)) { 2186 dev_dbg(dev, "slot complete: port has not device\n"); 2187 ts->stat = SAS_PHY_DOWN; 2188 goto out; 2189 } 2190 2191 dw0 = le32_to_cpu(complete_hdr->dw0); 2192 dw1 = le32_to_cpu(complete_hdr->dw1); 2193 dw3 = le32_to_cpu(complete_hdr->dw3); 2194 2195 /* 2196 * Use SAS+TMF status codes 2197 */ 2198 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 2199 case STAT_IO_ABORTED: 2200 /* this IO has been aborted by abort command */ 2201 ts->stat = SAS_ABORTED_TASK; 2202 goto out; 2203 case STAT_IO_COMPLETE: 2204 /* internal abort command complete */ 2205 ts->stat = TMF_RESP_FUNC_SUCC; 2206 goto out; 2207 case STAT_IO_NO_DEVICE: 2208 ts->stat = TMF_RESP_FUNC_COMPLETE; 2209 goto out; 2210 case STAT_IO_NOT_VALID: 2211 /* 2212 * abort single IO, the controller can't find the IO 2213 */ 2214 ts->stat = TMF_RESP_FUNC_FAILED; 2215 goto out; 2216 default: 2217 break; 2218 } 2219 2220 /* check for erroneous completion */ 2221 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 2222 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 2223 2224 slot_err_v3_hw(hisi_hba, task, slot); 2225 if (ts->stat != SAS_DATA_UNDERRUN) 2226 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n", 2227 slot->idx, task, sas_dev->device_id, 2228 dw0, dw1, complete_hdr->act, dw3, 2229 error_info[0], error_info[1], 2230 error_info[2], error_info[3]); 2231 if (unlikely(slot->abort)) 2232 return ts->stat; 2233 goto out; 2234 } 2235 2236 switch (task->task_proto) { 2237 case SAS_PROTOCOL_SSP: { 2238 struct ssp_response_iu *iu = 2239 hisi_sas_status_buf_addr_mem(slot) + 2240 sizeof(struct hisi_sas_err_record); 2241 2242 sas_ssp_task_response(dev, task, iu); 2243 break; 2244 } 2245 case SAS_PROTOCOL_SMP: { 2246 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 2247 void *to; 2248 2249 ts->stat = SAM_STAT_GOOD; 2250 to = kmap_atomic(sg_page(sg_resp)); 2251 2252 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 2253 DMA_FROM_DEVICE); 2254 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 2255 DMA_TO_DEVICE); 2256 memcpy(to + sg_resp->offset, 2257 hisi_sas_status_buf_addr_mem(slot) + 2258 sizeof(struct hisi_sas_err_record), 2259 sg_dma_len(sg_resp)); 2260 kunmap_atomic(to); 2261 break; 2262 } 2263 case SAS_PROTOCOL_SATA: 2264 case SAS_PROTOCOL_STP: 2265 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2266 ts->stat = SAM_STAT_GOOD; 2267 hisi_sas_sata_done(task, slot); 2268 break; 2269 default: 2270 ts->stat = SAM_STAT_CHECK_CONDITION; 2271 break; 2272 } 2273 2274 if (!slot->port->port_attached) { 2275 dev_warn(dev, "slot complete: port %d has removed\n", 2276 slot->port->sas_port.id); 2277 ts->stat = SAS_PHY_DOWN; 2278 } 2279 2280 out: 2281 sts = ts->stat; 2282 spin_lock_irqsave(&task->task_state_lock, flags); 2283 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 2284 spin_unlock_irqrestore(&task->task_state_lock, flags); 2285 dev_info(dev, "slot complete: task(%p) aborted\n", task); 2286 return SAS_ABORTED_TASK; 2287 } 2288 task->task_state_flags |= SAS_TASK_STATE_DONE; 2289 spin_unlock_irqrestore(&task->task_state_lock, flags); 2290 hisi_sas_slot_task_free(hisi_hba, task, slot); 2291 2292 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 2293 spin_lock_irqsave(&device->done_lock, flags); 2294 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 2295 spin_unlock_irqrestore(&device->done_lock, flags); 2296 dev_info(dev, "slot complete: task(%p) ignored\n ", 2297 task); 2298 return sts; 2299 } 2300 spin_unlock_irqrestore(&device->done_lock, flags); 2301 } 2302 2303 if (task->task_done) 2304 task->task_done(task); 2305 2306 return sts; 2307 } 2308 2309 static void cq_tasklet_v3_hw(unsigned long val) 2310 { 2311 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 2312 struct hisi_hba *hisi_hba = cq->hisi_hba; 2313 struct hisi_sas_slot *slot; 2314 struct hisi_sas_complete_v3_hdr *complete_queue; 2315 u32 rd_point = cq->rd_point, wr_point; 2316 int queue = cq->id; 2317 2318 complete_queue = hisi_hba->complete_hdr[queue]; 2319 2320 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2321 (0x14 * queue)); 2322 2323 while (rd_point != wr_point) { 2324 struct hisi_sas_complete_v3_hdr *complete_hdr; 2325 struct device *dev = hisi_hba->dev; 2326 u32 dw1; 2327 int iptt; 2328 2329 complete_hdr = &complete_queue[rd_point]; 2330 dw1 = le32_to_cpu(complete_hdr->dw1); 2331 2332 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2333 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2334 slot = &hisi_hba->slot_info[iptt]; 2335 slot->cmplt_queue_slot = rd_point; 2336 slot->cmplt_queue = queue; 2337 slot_complete_v3_hw(hisi_hba, slot); 2338 } else 2339 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2340 2341 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2342 rd_point = 0; 2343 } 2344 2345 /* update rd_point */ 2346 cq->rd_point = rd_point; 2347 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2348 } 2349 2350 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2351 { 2352 struct hisi_sas_cq *cq = p; 2353 struct hisi_hba *hisi_hba = cq->hisi_hba; 2354 int queue = cq->id; 2355 2356 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2357 2358 tasklet_schedule(&cq->tasklet); 2359 2360 return IRQ_HANDLED; 2361 } 2362 2363 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) 2364 { 2365 const struct cpumask *mask; 2366 int queue, cpu; 2367 2368 for (queue = 0; queue < nvecs; queue++) { 2369 struct hisi_sas_cq *cq = &hisi_hba->cq[queue]; 2370 2371 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + 2372 BASE_VECTORS_V3_HW); 2373 if (!mask) 2374 goto fallback; 2375 cq->pci_irq_mask = mask; 2376 for_each_cpu(cpu, mask) 2377 hisi_hba->reply_map[cpu] = queue; 2378 } 2379 return; 2380 2381 fallback: 2382 for_each_possible_cpu(cpu) 2383 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count; 2384 /* Don't clean all CQ masks */ 2385 } 2386 2387 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2388 { 2389 struct device *dev = hisi_hba->dev; 2390 struct pci_dev *pdev = hisi_hba->pci_dev; 2391 int vectors, rc; 2392 int i, k; 2393 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; 2394 2395 if (auto_affine_msi_experimental) { 2396 struct irq_affinity desc = { 2397 .pre_vectors = BASE_VECTORS_V3_HW, 2398 }; 2399 2400 min_msi = MIN_AFFINE_VECTORS_V3_HW; 2401 2402 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids, 2403 sizeof(unsigned int), 2404 GFP_KERNEL); 2405 if (!hisi_hba->reply_map) 2406 return -ENOMEM; 2407 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev, 2408 min_msi, max_msi, 2409 PCI_IRQ_MSI | 2410 PCI_IRQ_AFFINITY, 2411 &desc); 2412 if (vectors < 0) 2413 return -ENOENT; 2414 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW); 2415 } else { 2416 min_msi = max_msi; 2417 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi, 2418 max_msi, PCI_IRQ_MSI); 2419 if (vectors < 0) 2420 return vectors; 2421 } 2422 2423 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; 2424 2425 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2426 int_phy_up_down_bcast_v3_hw, 0, 2427 DRV_NAME " phy", hisi_hba); 2428 if (rc) { 2429 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2430 rc = -ENOENT; 2431 goto free_irq_vectors; 2432 } 2433 2434 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2435 int_chnl_int_v3_hw, 0, 2436 DRV_NAME " channel", hisi_hba); 2437 if (rc) { 2438 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2439 rc = -ENOENT; 2440 goto free_phy_irq; 2441 } 2442 2443 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2444 fatal_axi_int_v3_hw, 0, 2445 DRV_NAME " fatal", hisi_hba); 2446 if (rc) { 2447 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2448 rc = -ENOENT; 2449 goto free_chnl_interrupt; 2450 } 2451 2452 /* Init tasklets for cq only */ 2453 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2454 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2455 struct tasklet_struct *t = &cq->tasklet; 2456 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2457 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2458 2459 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2460 cq_interrupt_v3_hw, irqflags, 2461 DRV_NAME " cq", cq); 2462 if (rc) { 2463 dev_err(dev, "could not request cq%d interrupt, rc=%d\n", 2464 i, rc); 2465 rc = -ENOENT; 2466 goto free_cq_irqs; 2467 } 2468 2469 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2470 } 2471 2472 return 0; 2473 2474 free_cq_irqs: 2475 for (k = 0; k < i; k++) { 2476 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2477 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2478 2479 free_irq(pci_irq_vector(pdev, nr), cq); 2480 } 2481 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2482 free_chnl_interrupt: 2483 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2484 free_phy_irq: 2485 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2486 free_irq_vectors: 2487 pci_free_irq_vectors(pdev); 2488 return rc; 2489 } 2490 2491 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2492 { 2493 int rc; 2494 2495 rc = hw_init_v3_hw(hisi_hba); 2496 if (rc) 2497 return rc; 2498 2499 rc = interrupt_init_v3_hw(hisi_hba); 2500 if (rc) 2501 return rc; 2502 2503 return 0; 2504 } 2505 2506 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2507 struct sas_phy_linkrates *r) 2508 { 2509 enum sas_linkrate max = r->maximum_linkrate; 2510 u32 prog_phy_link_rate = 0x800; 2511 2512 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2513 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2514 prog_phy_link_rate); 2515 } 2516 2517 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2518 { 2519 struct pci_dev *pdev = hisi_hba->pci_dev; 2520 int i; 2521 2522 synchronize_irq(pci_irq_vector(pdev, 1)); 2523 synchronize_irq(pci_irq_vector(pdev, 2)); 2524 synchronize_irq(pci_irq_vector(pdev, 11)); 2525 for (i = 0; i < hisi_hba->queue_count; i++) { 2526 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2527 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2528 } 2529 2530 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2531 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2532 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2533 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2534 2535 for (i = 0; i < hisi_hba->n_phy; i++) { 2536 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2537 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2538 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2539 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2540 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2541 } 2542 } 2543 2544 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2545 { 2546 return hisi_sas_read32(hisi_hba, PHY_STATE); 2547 } 2548 2549 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2550 { 2551 struct device *dev = hisi_hba->dev; 2552 u32 status, reg_val; 2553 int rc; 2554 2555 interrupt_disable_v3_hw(hisi_hba); 2556 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2557 hisi_sas_kill_tasklets(hisi_hba); 2558 2559 hisi_sas_stop_phys(hisi_hba); 2560 2561 mdelay(10); 2562 2563 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2564 AM_CTRL_GLOBAL); 2565 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2566 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2567 AM_CTRL_GLOBAL, reg_val); 2568 2569 /* wait until bus idle */ 2570 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2571 AM_CURR_TRANS_RETURN, status, 2572 status == 0x3, 10, 100); 2573 if (rc) { 2574 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2575 return rc; 2576 } 2577 2578 return 0; 2579 } 2580 2581 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2582 { 2583 struct device *dev = hisi_hba->dev; 2584 int rc; 2585 2586 rc = disable_host_v3_hw(hisi_hba); 2587 if (rc) { 2588 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2589 return rc; 2590 } 2591 2592 hisi_sas_init_mem(hisi_hba); 2593 2594 return hw_init_v3_hw(hisi_hba); 2595 } 2596 2597 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2598 u8 reg_index, u8 reg_count, u8 *write_data) 2599 { 2600 struct device *dev = hisi_hba->dev; 2601 u32 *data = (u32 *)write_data; 2602 int i; 2603 2604 switch (reg_type) { 2605 case SAS_GPIO_REG_TX: 2606 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2607 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2608 reg_index, reg_index + reg_count - 1); 2609 return -EINVAL; 2610 } 2611 2612 for (i = 0; i < reg_count; i++) 2613 hisi_sas_write32(hisi_hba, 2614 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2615 data[i]); 2616 break; 2617 default: 2618 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2619 reg_type); 2620 return -EINVAL; 2621 } 2622 2623 return 0; 2624 } 2625 2626 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2627 int delay_ms, int timeout_ms) 2628 { 2629 struct device *dev = hisi_hba->dev; 2630 int entries, entries_old = 0, time; 2631 2632 for (time = 0; time < timeout_ms; time += delay_ms) { 2633 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2634 if (entries == entries_old) 2635 break; 2636 2637 entries_old = entries; 2638 msleep(delay_ms); 2639 } 2640 2641 if (time >= timeout_ms) 2642 return -ETIMEDOUT; 2643 2644 dev_dbg(dev, "wait commands complete %dms\n", time); 2645 2646 return 0; 2647 } 2648 2649 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2650 struct device_attribute *attr, char *buf) 2651 { 2652 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2653 } 2654 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2655 2656 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2657 { 2658 /* config those registers between enable and disable PHYs */ 2659 hisi_sas_stop_phys(hisi_hba); 2660 2661 if (hisi_hba->intr_coal_ticks == 0 || 2662 hisi_hba->intr_coal_count == 0) { 2663 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2664 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2665 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2666 } else { 2667 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2668 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2669 hisi_hba->intr_coal_ticks); 2670 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2671 hisi_hba->intr_coal_count); 2672 } 2673 phys_init_v3_hw(hisi_hba); 2674 } 2675 2676 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2677 struct device_attribute *attr, 2678 char *buf) 2679 { 2680 struct Scsi_Host *shost = class_to_shost(dev); 2681 struct hisi_hba *hisi_hba = shost_priv(shost); 2682 2683 return scnprintf(buf, PAGE_SIZE, "%u\n", 2684 hisi_hba->intr_coal_ticks); 2685 } 2686 2687 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2688 struct device_attribute *attr, 2689 const char *buf, size_t count) 2690 { 2691 struct Scsi_Host *shost = class_to_shost(dev); 2692 struct hisi_hba *hisi_hba = shost_priv(shost); 2693 u32 intr_coal_ticks; 2694 int ret; 2695 2696 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2697 if (ret) { 2698 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2699 return -EINVAL; 2700 } 2701 2702 if (intr_coal_ticks >= BIT(24)) { 2703 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2704 return -EINVAL; 2705 } 2706 2707 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2708 2709 config_intr_coal_v3_hw(hisi_hba); 2710 2711 return count; 2712 } 2713 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2714 2715 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2716 struct device_attribute 2717 *attr, char *buf) 2718 { 2719 struct Scsi_Host *shost = class_to_shost(dev); 2720 struct hisi_hba *hisi_hba = shost_priv(shost); 2721 2722 return scnprintf(buf, PAGE_SIZE, "%u\n", 2723 hisi_hba->intr_coal_count); 2724 } 2725 2726 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2727 struct device_attribute 2728 *attr, const char *buf, size_t count) 2729 { 2730 struct Scsi_Host *shost = class_to_shost(dev); 2731 struct hisi_hba *hisi_hba = shost_priv(shost); 2732 u32 intr_coal_count; 2733 int ret; 2734 2735 ret = kstrtou32(buf, 10, &intr_coal_count); 2736 if (ret) { 2737 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2738 return -EINVAL; 2739 } 2740 2741 if (intr_coal_count >= BIT(8)) { 2742 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2743 return -EINVAL; 2744 } 2745 2746 hisi_hba->intr_coal_count = intr_coal_count; 2747 2748 config_intr_coal_v3_hw(hisi_hba); 2749 2750 return count; 2751 } 2752 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2753 2754 static struct device_attribute *host_attrs_v3_hw[] = { 2755 &dev_attr_phy_event_threshold, 2756 &dev_attr_intr_conv_v3_hw, 2757 &dev_attr_intr_coal_ticks_v3_hw, 2758 &dev_attr_intr_coal_count_v3_hw, 2759 NULL 2760 }; 2761 2762 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2763 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2764 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2765 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2766 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2767 HISI_SAS_DEBUGFS_REG(SL_CFG), 2768 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2769 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2770 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2771 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2772 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2773 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2774 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2775 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2776 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2777 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2778 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2779 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2780 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2781 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2782 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2783 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2784 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2785 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2786 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2787 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2788 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2789 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2790 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2791 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2792 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2793 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2794 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2795 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2796 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2797 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2798 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2799 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2800 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2801 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2802 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2803 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2804 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2805 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2806 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2807 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2808 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2809 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2810 {} 2811 }; 2812 2813 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2814 .lu = debugfs_port_reg_lu, 2815 .count = 0x100, 2816 .base_off = PORT_BASE, 2817 .read_port_reg = hisi_sas_phy_read32, 2818 }; 2819 2820 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2821 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2822 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2823 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2824 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2825 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2826 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2827 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2828 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2829 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2830 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2831 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2832 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2833 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2834 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2835 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2836 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2837 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2838 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2839 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2840 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2841 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2842 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2843 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2844 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2845 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2846 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2847 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2848 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2849 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2850 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2851 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2852 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2853 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2854 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2855 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2856 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2857 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2858 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2859 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2860 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2861 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2862 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2863 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2864 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2865 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2866 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2867 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2868 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2869 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2870 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2871 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2872 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2873 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2874 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2875 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2876 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2877 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2878 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2879 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2880 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2881 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2882 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2883 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2884 {} 2885 }; 2886 2887 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2888 .lu = debugfs_global_reg_lu, 2889 .count = 0x800, 2890 .read_global_reg = hisi_sas_read32, 2891 }; 2892 2893 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2894 { 2895 struct device *dev = hisi_hba->dev; 2896 2897 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2898 2899 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2900 2901 if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT) 2902 dev_dbg(dev, "Wait commands complete timeout!\n"); 2903 2904 hisi_sas_kill_tasklets(hisi_hba); 2905 } 2906 2907 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2908 { 2909 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2910 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2911 2912 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2913 } 2914 2915 static struct scsi_host_template sht_v3_hw = { 2916 .name = DRV_NAME, 2917 .module = THIS_MODULE, 2918 .queuecommand = sas_queuecommand, 2919 .target_alloc = sas_target_alloc, 2920 .slave_configure = hisi_sas_slave_configure, 2921 .scan_finished = hisi_sas_scan_finished, 2922 .scan_start = hisi_sas_scan_start, 2923 .change_queue_depth = sas_change_queue_depth, 2924 .bios_param = sas_bios_param, 2925 .this_id = -1, 2926 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2927 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2928 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2929 .eh_device_reset_handler = sas_eh_device_reset_handler, 2930 .eh_target_reset_handler = sas_eh_target_reset_handler, 2931 .target_destroy = sas_target_destroy, 2932 .ioctl = sas_ioctl, 2933 .shost_attrs = host_attrs_v3_hw, 2934 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2935 .host_reset = hisi_sas_host_reset, 2936 }; 2937 2938 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2939 .hw_init = hisi_sas_v3_init, 2940 .setup_itct = setup_itct_v3_hw, 2941 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2942 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2943 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2944 .clear_itct = clear_itct_v3_hw, 2945 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2946 .prep_ssp = prep_ssp_v3_hw, 2947 .prep_smp = prep_smp_v3_hw, 2948 .prep_stp = prep_ata_v3_hw, 2949 .prep_abort = prep_abort_v3_hw, 2950 .get_free_slot = get_free_slot_v3_hw, 2951 .start_delivery = start_delivery_v3_hw, 2952 .slot_complete = slot_complete_v3_hw, 2953 .phys_init = phys_init_v3_hw, 2954 .phy_start = start_phy_v3_hw, 2955 .phy_disable = disable_phy_v3_hw, 2956 .phy_hard_reset = phy_hard_reset_v3_hw, 2957 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2958 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2959 .dereg_device = dereg_device_v3_hw, 2960 .soft_reset = soft_reset_v3_hw, 2961 .get_phys_state = get_phys_state_v3_hw, 2962 .get_events = phy_get_events_v3_hw, 2963 .write_gpio = write_gpio_v3_hw, 2964 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2965 .debugfs_reg_global = &debugfs_global_reg, 2966 .debugfs_reg_port = &debugfs_port_reg, 2967 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2968 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2969 }; 2970 2971 static struct Scsi_Host * 2972 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2973 { 2974 struct Scsi_Host *shost; 2975 struct hisi_hba *hisi_hba; 2976 struct device *dev = &pdev->dev; 2977 2978 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2979 if (!shost) { 2980 dev_err(dev, "shost alloc failed\n"); 2981 return NULL; 2982 } 2983 hisi_hba = shost_priv(shost); 2984 2985 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2986 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2987 hisi_hba->hw = &hisi_sas_v3_hw; 2988 hisi_hba->pci_dev = pdev; 2989 hisi_hba->dev = dev; 2990 hisi_hba->shost = shost; 2991 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2992 2993 if (prot_mask & ~HISI_SAS_PROT_MASK) 2994 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2995 prot_mask); 2996 else 2997 hisi_hba->prot_mask = prot_mask; 2998 2999 timer_setup(&hisi_hba->timer, NULL, 0); 3000 3001 if (hisi_sas_get_fw_info(hisi_hba) < 0) 3002 goto err_out; 3003 3004 if (hisi_sas_alloc(hisi_hba)) { 3005 hisi_sas_free(hisi_hba); 3006 goto err_out; 3007 } 3008 3009 return shost; 3010 err_out: 3011 scsi_host_put(shost); 3012 dev_err(dev, "shost alloc failed\n"); 3013 return NULL; 3014 } 3015 3016 static int 3017 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3018 { 3019 struct Scsi_Host *shost; 3020 struct hisi_hba *hisi_hba; 3021 struct device *dev = &pdev->dev; 3022 struct asd_sas_phy **arr_phy; 3023 struct asd_sas_port **arr_port; 3024 struct sas_ha_struct *sha; 3025 int rc, phy_nr, port_nr, i; 3026 3027 rc = pci_enable_device(pdev); 3028 if (rc) 3029 goto err_out; 3030 3031 pci_set_master(pdev); 3032 3033 rc = pci_request_regions(pdev, DRV_NAME); 3034 if (rc) 3035 goto err_out_disable_device; 3036 3037 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3038 if (rc) 3039 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3040 if (rc) { 3041 dev_err(dev, "No usable DMA addressing method\n"); 3042 rc = -ENODEV; 3043 goto err_out_regions; 3044 } 3045 3046 shost = hisi_sas_shost_alloc_pci(pdev); 3047 if (!shost) { 3048 rc = -ENOMEM; 3049 goto err_out_regions; 3050 } 3051 3052 sha = SHOST_TO_SAS_HA(shost); 3053 hisi_hba = shost_priv(shost); 3054 dev_set_drvdata(dev, sha); 3055 3056 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 3057 if (!hisi_hba->regs) { 3058 dev_err(dev, "cannot map register\n"); 3059 rc = -ENOMEM; 3060 goto err_out_ha; 3061 } 3062 3063 phy_nr = port_nr = hisi_hba->n_phy; 3064 3065 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 3066 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 3067 if (!arr_phy || !arr_port) { 3068 rc = -ENOMEM; 3069 goto err_out_ha; 3070 } 3071 3072 sha->sas_phy = arr_phy; 3073 sha->sas_port = arr_port; 3074 sha->core.shost = shost; 3075 sha->lldd_ha = hisi_hba; 3076 3077 shost->transportt = hisi_sas_stt; 3078 shost->max_id = HISI_SAS_MAX_DEVICES; 3079 shost->max_lun = ~0; 3080 shost->max_channel = 1; 3081 shost->max_cmd_len = 16; 3082 shost->can_queue = hisi_hba->hw->max_command_entries - 3083 HISI_SAS_RESERVED_IPTT_CNT; 3084 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 3085 HISI_SAS_RESERVED_IPTT_CNT; 3086 3087 sha->sas_ha_name = DRV_NAME; 3088 sha->dev = dev; 3089 sha->lldd_module = THIS_MODULE; 3090 sha->sas_addr = &hisi_hba->sas_addr[0]; 3091 sha->num_phys = hisi_hba->n_phy; 3092 sha->core.shost = hisi_hba->shost; 3093 3094 for (i = 0; i < hisi_hba->n_phy; i++) { 3095 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 3096 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 3097 } 3098 3099 if (hisi_hba->prot_mask) { 3100 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 3101 prot_mask); 3102 scsi_host_set_prot(hisi_hba->shost, prot_mask); 3103 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 3104 scsi_host_set_guard(hisi_hba->shost, 3105 SHOST_DIX_GUARD_CRC); 3106 } 3107 3108 if (hisi_sas_debugfs_enable) 3109 hisi_sas_debugfs_init(hisi_hba); 3110 3111 rc = scsi_add_host(shost, dev); 3112 if (rc) 3113 goto err_out_ha; 3114 3115 rc = sas_register_ha(sha); 3116 if (rc) 3117 goto err_out_register_ha; 3118 3119 rc = hisi_hba->hw->hw_init(hisi_hba); 3120 if (rc) 3121 goto err_out_register_ha; 3122 3123 scsi_scan_host(shost); 3124 3125 return 0; 3126 3127 err_out_register_ha: 3128 scsi_remove_host(shost); 3129 err_out_ha: 3130 scsi_host_put(shost); 3131 err_out_regions: 3132 pci_release_regions(pdev); 3133 err_out_disable_device: 3134 pci_disable_device(pdev); 3135 err_out: 3136 return rc; 3137 } 3138 3139 static void 3140 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 3141 { 3142 int i; 3143 3144 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 3145 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 3146 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 3147 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 3148 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 3149 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 3150 3151 free_irq(pci_irq_vector(pdev, nr), cq); 3152 } 3153 pci_free_irq_vectors(pdev); 3154 } 3155 3156 static void hisi_sas_v3_remove(struct pci_dev *pdev) 3157 { 3158 struct device *dev = &pdev->dev; 3159 struct sas_ha_struct *sha = dev_get_drvdata(dev); 3160 struct hisi_hba *hisi_hba = sha->lldd_ha; 3161 struct Scsi_Host *shost = sha->core.shost; 3162 3163 hisi_sas_debugfs_exit(hisi_hba); 3164 3165 if (timer_pending(&hisi_hba->timer)) 3166 del_timer(&hisi_hba->timer); 3167 3168 sas_unregister_ha(sha); 3169 sas_remove_host(sha->core.shost); 3170 3171 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 3172 hisi_sas_kill_tasklets(hisi_hba); 3173 pci_release_regions(pdev); 3174 pci_disable_device(pdev); 3175 hisi_sas_free(hisi_hba); 3176 scsi_host_put(shost); 3177 } 3178 3179 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 3180 { 3181 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3182 struct hisi_hba *hisi_hba = sha->lldd_ha; 3183 struct device *dev = hisi_hba->dev; 3184 int rc; 3185 3186 dev_info(dev, "FLR prepare\n"); 3187 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3188 hisi_sas_controller_reset_prepare(hisi_hba); 3189 3190 rc = disable_host_v3_hw(hisi_hba); 3191 if (rc) 3192 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 3193 } 3194 3195 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3196 { 3197 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3198 struct hisi_hba *hisi_hba = sha->lldd_ha; 3199 struct device *dev = hisi_hba->dev; 3200 int rc; 3201 3202 hisi_sas_init_mem(hisi_hba); 3203 3204 rc = hw_init_v3_hw(hisi_hba); 3205 if (rc) { 3206 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3207 return; 3208 } 3209 3210 hisi_sas_controller_reset_done(hisi_hba); 3211 dev_info(dev, "FLR done\n"); 3212 } 3213 3214 enum { 3215 /* instances of the controller */ 3216 hip08, 3217 }; 3218 3219 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3220 { 3221 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3222 struct hisi_hba *hisi_hba = sha->lldd_ha; 3223 struct device *dev = hisi_hba->dev; 3224 struct Scsi_Host *shost = hisi_hba->shost; 3225 pci_power_t device_state; 3226 int rc; 3227 3228 if (!pdev->pm_cap) { 3229 dev_err(dev, "PCI PM not supported\n"); 3230 return -ENODEV; 3231 } 3232 3233 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3234 return -1; 3235 3236 scsi_block_requests(shost); 3237 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3238 flush_workqueue(hisi_hba->wq); 3239 3240 rc = disable_host_v3_hw(hisi_hba); 3241 if (rc) { 3242 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3243 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3244 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3245 scsi_unblock_requests(shost); 3246 return rc; 3247 } 3248 3249 hisi_sas_init_mem(hisi_hba); 3250 3251 device_state = pci_choose_state(pdev, state); 3252 dev_warn(dev, "entering operating state [D%d]\n", 3253 device_state); 3254 pci_save_state(pdev); 3255 pci_disable_device(pdev); 3256 pci_set_power_state(pdev, device_state); 3257 3258 hisi_sas_release_tasks(hisi_hba); 3259 3260 sas_suspend_ha(sha); 3261 return 0; 3262 } 3263 3264 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3265 { 3266 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3267 struct hisi_hba *hisi_hba = sha->lldd_ha; 3268 struct Scsi_Host *shost = hisi_hba->shost; 3269 struct device *dev = hisi_hba->dev; 3270 unsigned int rc; 3271 pci_power_t device_state = pdev->current_state; 3272 3273 dev_warn(dev, "resuming from operating state [D%d]\n", 3274 device_state); 3275 pci_set_power_state(pdev, PCI_D0); 3276 pci_enable_wake(pdev, PCI_D0, 0); 3277 pci_restore_state(pdev); 3278 rc = pci_enable_device(pdev); 3279 if (rc) 3280 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3281 3282 pci_set_master(pdev); 3283 scsi_unblock_requests(shost); 3284 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3285 3286 sas_prep_resume_ha(sha); 3287 init_reg_v3_hw(hisi_hba); 3288 hisi_hba->hw->phys_init(hisi_hba); 3289 sas_resume_ha(sha); 3290 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3291 3292 return 0; 3293 } 3294 3295 static const struct pci_device_id sas_v3_pci_table[] = { 3296 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3297 {} 3298 }; 3299 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3300 3301 static const struct pci_error_handlers hisi_sas_err_handler = { 3302 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3303 .reset_done = hisi_sas_reset_done_v3_hw, 3304 }; 3305 3306 static struct pci_driver sas_v3_pci_driver = { 3307 .name = DRV_NAME, 3308 .id_table = sas_v3_pci_table, 3309 .probe = hisi_sas_v3_probe, 3310 .remove = hisi_sas_v3_remove, 3311 .suspend = hisi_sas_v3_suspend, 3312 .resume = hisi_sas_v3_resume, 3313 .err_handler = &hisi_sas_err_handler, 3314 }; 3315 3316 module_pci_driver(sas_v3_pci_driver); 3317 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3318 3319 MODULE_LICENSE("GPL"); 3320 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3321 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3322 MODULE_ALIAS("pci:" DRV_NAME); 3323