1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PHY_CFG_PHY_RST_OFF 3 125 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 126 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 127 #define PHY_CTRL (PORT_BASE + 0x14) 128 #define PHY_CTRL_RESET_OFF 0 129 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 130 #define CMD_HDR_PIR_OFF 8 131 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 132 #define SL_CFG (PORT_BASE + 0x84) 133 #define AIP_LIMIT (PORT_BASE + 0x90) 134 #define SL_CONTROL (PORT_BASE + 0x94) 135 #define SL_CONTROL_NOTIFY_EN_OFF 0 136 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 137 #define SL_CTA_OFF 17 138 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 139 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 140 #define RX_BCAST_CHG_OFF 1 141 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 142 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 143 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 144 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 145 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 146 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 147 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 148 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 149 #define TXID_AUTO (PORT_BASE + 0xb8) 150 #define CT3_OFF 1 151 #define CT3_MSK (0x1 << CT3_OFF) 152 #define TX_HARDRST_OFF 2 153 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 154 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 155 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 156 #define STP_LINK_TIMER (PORT_BASE + 0x120) 157 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 158 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 159 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 160 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 161 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 162 #define CHL_INT0 (PORT_BASE + 0x1b4) 163 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 164 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 165 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 166 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 167 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 168 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 169 #define CHL_INT0_NOT_RDY_OFF 4 170 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 171 #define CHL_INT0_PHY_RDY_OFF 5 172 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 173 #define CHL_INT1 (PORT_BASE + 0x1b8) 174 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 175 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 176 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 177 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 178 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 179 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 180 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 181 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 182 #define CHL_INT2 (PORT_BASE + 0x1bc) 183 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 184 #define CHL_INT2_RX_INVLD_DW_OFF 30 185 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 186 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 189 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 190 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 191 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 192 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 193 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 194 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 195 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 196 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 197 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 198 #define DMA_TX_STATUS_BUSY_OFF 0 199 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 200 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 201 #define DMA_RX_STATUS_BUSY_OFF 0 202 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 203 204 #define COARSETUNE_TIME (PORT_BASE + 0x304) 205 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 206 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 207 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 208 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 209 210 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 211 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 212 #error Max ITCT exceeded 213 #endif 214 215 #define AXI_MASTER_CFG_BASE (0x5000) 216 #define AM_CTRL_GLOBAL (0x0) 217 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 218 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 219 #define AM_CURR_TRANS_RETURN (0x150) 220 221 #define AM_CFG_MAX_TRANS (0x5010) 222 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 223 #define AXI_CFG (0x5100) 224 #define AM_ROB_ECC_ERR_ADDR (0x510c) 225 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 226 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 227 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 228 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 229 230 /* RAS registers need init */ 231 #define RAS_BASE (0x6000) 232 #define SAS_RAS_INTR0 (RAS_BASE) 233 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 234 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 235 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 236 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 237 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 238 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 239 240 /* HW dma structures */ 241 /* Delivery queue header */ 242 /* dw0 */ 243 #define CMD_HDR_ABORT_FLAG_OFF 0 244 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 245 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 246 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 247 #define CMD_HDR_RESP_REPORT_OFF 5 248 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 249 #define CMD_HDR_TLR_CTRL_OFF 6 250 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 251 #define CMD_HDR_PORT_OFF 18 252 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 253 #define CMD_HDR_PRIORITY_OFF 27 254 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 255 #define CMD_HDR_CMD_OFF 29 256 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 257 /* dw1 */ 258 #define CMD_HDR_UNCON_CMD_OFF 3 259 #define CMD_HDR_DIR_OFF 5 260 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 261 #define CMD_HDR_RESET_OFF 7 262 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 263 #define CMD_HDR_VDTL_OFF 10 264 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 265 #define CMD_HDR_FRAME_TYPE_OFF 11 266 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 267 #define CMD_HDR_DEV_ID_OFF 16 268 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 269 /* dw2 */ 270 #define CMD_HDR_CFL_OFF 0 271 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 272 #define CMD_HDR_NCQ_TAG_OFF 10 273 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 274 #define CMD_HDR_MRFL_OFF 15 275 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 276 #define CMD_HDR_SG_MOD_OFF 24 277 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 278 /* dw3 */ 279 #define CMD_HDR_IPTT_OFF 0 280 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 281 /* dw6 */ 282 #define CMD_HDR_DIF_SGL_LEN_OFF 0 283 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 284 #define CMD_HDR_DATA_SGL_LEN_OFF 16 285 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 286 /* dw7 */ 287 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 288 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 289 #define CMD_HDR_ABORT_IPTT_OFF 16 290 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 291 292 /* Completion header */ 293 /* dw0 */ 294 #define CMPLT_HDR_CMPLT_OFF 0 295 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 296 #define CMPLT_HDR_ERROR_PHASE_OFF 2 297 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 298 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 299 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 300 #define CMPLT_HDR_ERX_OFF 12 301 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 302 #define CMPLT_HDR_ABORT_STAT_OFF 13 303 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 304 /* abort_stat */ 305 #define STAT_IO_NOT_VALID 0x1 306 #define STAT_IO_NO_DEVICE 0x2 307 #define STAT_IO_COMPLETE 0x3 308 #define STAT_IO_ABORTED 0x4 309 /* dw1 */ 310 #define CMPLT_HDR_IPTT_OFF 0 311 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 312 #define CMPLT_HDR_DEV_ID_OFF 16 313 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 314 /* dw3 */ 315 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 316 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 317 318 /* ITCT header */ 319 /* qw0 */ 320 #define ITCT_HDR_DEV_TYPE_OFF 0 321 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 322 #define ITCT_HDR_VALID_OFF 2 323 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 324 #define ITCT_HDR_MCR_OFF 5 325 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 326 #define ITCT_HDR_VLN_OFF 9 327 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 328 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 329 #define ITCT_HDR_AWT_CONTINUE_OFF 25 330 #define ITCT_HDR_PORT_ID_OFF 28 331 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 332 /* qw2 */ 333 #define ITCT_HDR_INLT_OFF 0 334 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 335 #define ITCT_HDR_RTOLT_OFF 48 336 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 337 338 struct hisi_sas_protect_iu_v3_hw { 339 u32 dw0; 340 u32 lbrtcv; 341 u32 lbrtgv; 342 u32 dw3; 343 u32 dw4; 344 u32 dw5; 345 u32 rsv; 346 }; 347 348 struct hisi_sas_complete_v3_hdr { 349 __le32 dw0; 350 __le32 dw1; 351 __le32 act; 352 __le32 dw3; 353 }; 354 355 struct hisi_sas_err_record_v3 { 356 /* dw0 */ 357 __le32 trans_tx_fail_type; 358 359 /* dw1 */ 360 __le32 trans_rx_fail_type; 361 362 /* dw2 */ 363 __le16 dma_tx_err_type; 364 __le16 sipc_rx_err_type; 365 366 /* dw3 */ 367 __le32 dma_rx_err_type; 368 }; 369 370 #define RX_DATA_LEN_UNDERFLOW_OFF 6 371 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 372 373 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 374 #define HISI_SAS_MSI_COUNT_V3_HW 32 375 376 #define DIR_NO_DATA 0 377 #define DIR_TO_INI 1 378 #define DIR_TO_DEVICE 2 379 #define DIR_RESERVED 3 380 381 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 382 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 383 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 384 ((fis.command == ATA_CMD_DEV_RESET) && \ 385 ((fis.control & ATA_SRST) != 0))) 386 387 #define T10_INSRT_EN_OFF 0 388 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 389 #define T10_RMV_EN_OFF 1 390 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 391 #define T10_RPLC_EN_OFF 2 392 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 393 #define T10_CHK_EN_OFF 3 394 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 395 #define INCR_LBRT_OFF 5 396 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 397 #define USR_DATA_BLOCK_SZ_OFF 20 398 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 399 #define T10_CHK_MSK_OFF 16 400 401 static bool hisi_sas_intr_conv; 402 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 403 404 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 405 static int prot_mask; 406 module_param(prot_mask, int, 0); 407 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 408 409 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 410 { 411 void __iomem *regs = hisi_hba->regs + off; 412 413 return readl(regs); 414 } 415 416 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 417 { 418 void __iomem *regs = hisi_hba->regs + off; 419 420 return readl_relaxed(regs); 421 } 422 423 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 424 { 425 void __iomem *regs = hisi_hba->regs + off; 426 427 writel(val, regs); 428 } 429 430 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 431 u32 off, u32 val) 432 { 433 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 434 435 writel(val, regs); 436 } 437 438 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 439 int phy_no, u32 off) 440 { 441 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 442 443 return readl(regs); 444 } 445 446 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 447 timeout_us) \ 448 ({ \ 449 void __iomem *regs = hisi_hba->regs + off; \ 450 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 451 }) 452 453 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 454 timeout_us) \ 455 ({ \ 456 void __iomem *regs = hisi_hba->regs + off; \ 457 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 458 }) 459 460 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 461 { 462 struct pci_dev *pdev = hisi_hba->pci_dev; 463 int i; 464 465 /* Global registers init */ 466 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 467 (u32)((1ULL << hisi_hba->queue_count) - 1)); 468 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 469 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 470 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 471 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 472 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 473 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 474 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 475 hisi_sas_intr_conv); 476 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 477 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 478 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 479 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 480 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 481 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 482 if (pdev->revision >= 0x21) 483 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff); 484 else 485 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 486 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 487 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 488 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 489 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 490 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 491 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 492 for (i = 0; i < hisi_hba->queue_count; i++) 493 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 494 495 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 496 497 for (i = 0; i < hisi_hba->n_phy; i++) { 498 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 499 struct asd_sas_phy *sas_phy = &phy->sas_phy; 500 u32 prog_phy_link_rate = 0x800; 501 502 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 503 SAS_LINK_RATE_1_5_GBPS)) { 504 prog_phy_link_rate = 0x855; 505 } else { 506 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 507 508 prog_phy_link_rate = 509 hisi_sas_get_prog_phy_linkrate_mask(max) | 510 0x800; 511 } 512 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 513 prog_phy_link_rate); 514 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 515 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 516 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 517 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 518 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 519 if (pdev->revision >= 0x21) 520 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 521 0xffffffff); 522 else 523 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 524 0xff87ffff); 525 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 526 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 527 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 528 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 529 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 530 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 531 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 532 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 533 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 534 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 535 /* used for 12G negotiate */ 536 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 537 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 538 } 539 540 for (i = 0; i < hisi_hba->queue_count; i++) { 541 /* Delivery queue */ 542 hisi_sas_write32(hisi_hba, 543 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 544 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 545 546 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 547 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 548 549 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 550 HISI_SAS_QUEUE_SLOTS); 551 552 /* Completion queue */ 553 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 554 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 555 556 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 557 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 558 559 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 560 HISI_SAS_QUEUE_SLOTS); 561 } 562 563 /* itct */ 564 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 565 lower_32_bits(hisi_hba->itct_dma)); 566 567 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 568 upper_32_bits(hisi_hba->itct_dma)); 569 570 /* iost */ 571 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 572 lower_32_bits(hisi_hba->iost_dma)); 573 574 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 575 upper_32_bits(hisi_hba->iost_dma)); 576 577 /* breakpoint */ 578 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 579 lower_32_bits(hisi_hba->breakpoint_dma)); 580 581 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 582 upper_32_bits(hisi_hba->breakpoint_dma)); 583 584 /* SATA broken msg */ 585 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 586 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 587 588 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 589 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 590 591 /* SATA initial fis */ 592 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 593 lower_32_bits(hisi_hba->initial_fis_dma)); 594 595 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 596 upper_32_bits(hisi_hba->initial_fis_dma)); 597 598 /* RAS registers init */ 599 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 600 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 601 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 602 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 603 604 /* LED registers init */ 605 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 606 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 607 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 608 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 609 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 610 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 611 } 612 613 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 614 { 615 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 616 617 cfg &= ~PHY_CFG_DC_OPT_MSK; 618 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 619 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 620 } 621 622 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 623 { 624 struct sas_identify_frame identify_frame; 625 u32 *identify_buffer; 626 627 memset(&identify_frame, 0, sizeof(identify_frame)); 628 identify_frame.dev_type = SAS_END_DEVICE; 629 identify_frame.frame_type = 0; 630 identify_frame._un1 = 1; 631 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 632 identify_frame.target_bits = SAS_PROTOCOL_NONE; 633 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 634 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 635 identify_frame.phy_id = phy_no; 636 identify_buffer = (u32 *)(&identify_frame); 637 638 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 639 __swab32(identify_buffer[0])); 640 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 641 __swab32(identify_buffer[1])); 642 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 643 __swab32(identify_buffer[2])); 644 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 645 __swab32(identify_buffer[3])); 646 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 647 __swab32(identify_buffer[4])); 648 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 649 __swab32(identify_buffer[5])); 650 } 651 652 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 653 struct hisi_sas_device *sas_dev) 654 { 655 struct domain_device *device = sas_dev->sas_device; 656 struct device *dev = hisi_hba->dev; 657 u64 qw0, device_id = sas_dev->device_id; 658 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 659 struct domain_device *parent_dev = device->parent; 660 struct asd_sas_port *sas_port = device->port; 661 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 662 u64 sas_addr; 663 664 memset(itct, 0, sizeof(*itct)); 665 666 /* qw0 */ 667 qw0 = 0; 668 switch (sas_dev->dev_type) { 669 case SAS_END_DEVICE: 670 case SAS_EDGE_EXPANDER_DEVICE: 671 case SAS_FANOUT_EXPANDER_DEVICE: 672 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 673 break; 674 case SAS_SATA_DEV: 675 case SAS_SATA_PENDING: 676 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 677 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 678 else 679 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 680 break; 681 default: 682 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 683 sas_dev->dev_type); 684 } 685 686 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 687 (device->linkrate << ITCT_HDR_MCR_OFF) | 688 (1 << ITCT_HDR_VLN_OFF) | 689 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 690 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 691 (port->id << ITCT_HDR_PORT_ID_OFF)); 692 itct->qw0 = cpu_to_le64(qw0); 693 694 /* qw1 */ 695 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 696 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 697 698 /* qw2 */ 699 if (!dev_is_sata(device)) 700 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 701 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 702 } 703 704 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 705 struct hisi_sas_device *sas_dev) 706 { 707 DECLARE_COMPLETION_ONSTACK(completion); 708 u64 dev_id = sas_dev->device_id; 709 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 710 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 711 712 sas_dev->completion = &completion; 713 714 /* clear the itct interrupt state */ 715 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 716 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 717 ENT_INT_SRC3_ITC_INT_MSK); 718 719 /* clear the itct table*/ 720 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 721 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 722 723 wait_for_completion(sas_dev->completion); 724 memset(itct, 0, sizeof(struct hisi_sas_itct)); 725 } 726 727 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 728 struct domain_device *device) 729 { 730 struct hisi_sas_slot *slot, *slot2; 731 struct hisi_sas_device *sas_dev = device->lldd_dev; 732 u32 cfg_abt_set_query_iptt; 733 734 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 735 CFG_ABT_SET_QUERY_IPTT); 736 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 737 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 738 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 739 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 740 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 741 cfg_abt_set_query_iptt); 742 } 743 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 744 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 745 cfg_abt_set_query_iptt); 746 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 747 1 << CFG_ABT_SET_IPTT_DONE_OFF); 748 } 749 750 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 751 { 752 struct device *dev = hisi_hba->dev; 753 int ret; 754 u32 val; 755 756 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 757 758 /* Disable all of the PHYs */ 759 hisi_sas_stop_phys(hisi_hba); 760 udelay(50); 761 762 /* Ensure axi bus idle */ 763 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 764 20000, 1000000); 765 if (ret) { 766 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 767 return -EIO; 768 } 769 770 if (ACPI_HANDLE(dev)) { 771 acpi_status s; 772 773 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 774 if (ACPI_FAILURE(s)) { 775 dev_err(dev, "Reset failed\n"); 776 return -EIO; 777 } 778 } else { 779 dev_err(dev, "no reset method!\n"); 780 return -EINVAL; 781 } 782 783 return 0; 784 } 785 786 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 787 { 788 struct device *dev = hisi_hba->dev; 789 int rc; 790 791 rc = reset_hw_v3_hw(hisi_hba); 792 if (rc) { 793 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 794 return rc; 795 } 796 797 msleep(100); 798 init_reg_v3_hw(hisi_hba); 799 800 return 0; 801 } 802 803 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 804 { 805 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 806 807 cfg |= PHY_CFG_ENA_MSK; 808 cfg &= ~PHY_CFG_PHY_RST_MSK; 809 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 810 } 811 812 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 813 { 814 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 815 u32 state; 816 817 cfg &= ~PHY_CFG_ENA_MSK; 818 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 819 820 mdelay(50); 821 822 state = hisi_sas_read32(hisi_hba, PHY_STATE); 823 if (state & BIT(phy_no)) { 824 cfg |= PHY_CFG_PHY_RST_MSK; 825 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 826 } 827 } 828 829 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 830 { 831 config_id_frame_v3_hw(hisi_hba, phy_no); 832 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 833 enable_phy_v3_hw(hisi_hba, phy_no); 834 } 835 836 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 837 { 838 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 839 u32 txid_auto; 840 841 disable_phy_v3_hw(hisi_hba, phy_no); 842 if (phy->identify.device_type == SAS_END_DEVICE) { 843 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 844 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 845 txid_auto | TX_HARDRST_MSK); 846 } 847 msleep(100); 848 start_phy_v3_hw(hisi_hba, phy_no); 849 } 850 851 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 852 { 853 return SAS_LINK_RATE_12_0_GBPS; 854 } 855 856 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 857 { 858 int i; 859 860 for (i = 0; i < hisi_hba->n_phy; i++) { 861 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 862 struct asd_sas_phy *sas_phy = &phy->sas_phy; 863 864 if (!sas_phy->phy->enabled) 865 continue; 866 867 start_phy_v3_hw(hisi_hba, i); 868 } 869 } 870 871 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 872 { 873 u32 sl_control; 874 875 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 876 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 877 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 878 msleep(1); 879 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 880 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 881 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 882 } 883 884 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 885 { 886 int i, bitmap = 0; 887 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 888 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 889 890 for (i = 0; i < hisi_hba->n_phy; i++) 891 if (phy_state & BIT(i)) 892 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 893 bitmap |= BIT(i); 894 895 return bitmap; 896 } 897 898 /** 899 * The callpath to this function and upto writing the write 900 * queue pointer should be safe from interruption. 901 */ 902 static int 903 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 904 { 905 struct device *dev = hisi_hba->dev; 906 int queue = dq->id; 907 u32 r, w; 908 909 w = dq->wr_point; 910 r = hisi_sas_read32_relaxed(hisi_hba, 911 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 912 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 913 dev_warn(dev, "full queue=%d r=%d w=%d\n", 914 queue, r, w); 915 return -EAGAIN; 916 } 917 918 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 919 920 return w; 921 } 922 923 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 924 { 925 struct hisi_hba *hisi_hba = dq->hisi_hba; 926 struct hisi_sas_slot *s, *s1, *s2 = NULL; 927 struct list_head *dq_list; 928 int dlvry_queue = dq->id; 929 int wp; 930 931 dq_list = &dq->list; 932 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 933 if (!s->ready) 934 break; 935 s2 = s; 936 list_del(&s->delivery); 937 } 938 939 if (!s2) 940 return; 941 942 /* 943 * Ensure that memories for slots built on other CPUs is observed. 944 */ 945 smp_rmb(); 946 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 947 948 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 949 } 950 951 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 952 struct hisi_sas_slot *slot, 953 struct hisi_sas_cmd_hdr *hdr, 954 struct scatterlist *scatter, 955 int n_elem) 956 { 957 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 958 struct scatterlist *sg; 959 int i; 960 961 for_each_sg(scatter, sg, n_elem, i) { 962 struct hisi_sas_sge *entry = &sge_page->sge[i]; 963 964 entry->addr = cpu_to_le64(sg_dma_address(sg)); 965 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 966 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 967 entry->data_off = 0; 968 } 969 970 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 971 972 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 973 } 974 975 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 976 { 977 unsigned char prot_flags = scsi_cmnd->prot_flags; 978 979 if (prot_flags & SCSI_PROT_TRANSFER_PI) { 980 if (prot_flags & SCSI_PROT_REF_CHECK) 981 return 0xc << 16; 982 return 0xfc << 16; 983 } 984 return 0; 985 } 986 987 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 988 struct hisi_sas_protect_iu_v3_hw *prot) 989 { 990 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 991 unsigned int interval = scsi_prot_interval(scsi_cmnd); 992 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 993 994 switch (prot_op) { 995 case SCSI_PROT_READ_STRIP: 996 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 997 prot->lbrtcv = lbrt_chk_val; 998 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 999 break; 1000 case SCSI_PROT_WRITE_INSERT: 1001 prot->dw0 |= T10_INSRT_EN_MSK; 1002 prot->lbrtgv = lbrt_chk_val; 1003 break; 1004 default: 1005 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1006 break; 1007 } 1008 1009 switch (interval) { 1010 case 512: 1011 break; 1012 case 4096: 1013 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1014 break; 1015 case 520: 1016 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1017 break; 1018 default: 1019 WARN(1, "protection interval (0x%x) invalid\n", 1020 interval); 1021 break; 1022 } 1023 1024 prot->dw0 |= INCR_LBRT_MSK; 1025 } 1026 1027 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1028 struct hisi_sas_slot *slot) 1029 { 1030 struct sas_task *task = slot->task; 1031 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1032 struct domain_device *device = task->dev; 1033 struct hisi_sas_device *sas_dev = device->lldd_dev; 1034 struct hisi_sas_port *port = slot->port; 1035 struct sas_ssp_task *ssp_task = &task->ssp_task; 1036 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1037 struct hisi_sas_tmf_task *tmf = slot->tmf; 1038 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1039 int has_data = 0, priority = !!tmf; 1040 u8 *buf_cmd; 1041 u32 dw1 = 0, dw2 = 0, len = 0; 1042 1043 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1044 (2 << CMD_HDR_TLR_CTRL_OFF) | 1045 (port->id << CMD_HDR_PORT_OFF) | 1046 (priority << CMD_HDR_PRIORITY_OFF) | 1047 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1048 1049 dw1 = 1 << CMD_HDR_VDTL_OFF; 1050 if (tmf) { 1051 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1052 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1053 } else { 1054 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1055 switch (scsi_cmnd->sc_data_direction) { 1056 case DMA_TO_DEVICE: 1057 has_data = 1; 1058 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1059 break; 1060 case DMA_FROM_DEVICE: 1061 has_data = 1; 1062 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1063 break; 1064 default: 1065 dw1 &= ~CMD_HDR_DIR_MSK; 1066 } 1067 } 1068 1069 /* map itct entry */ 1070 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1071 1072 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1073 + 3) / 4) << CMD_HDR_CFL_OFF) | 1074 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1075 (2 << CMD_HDR_SG_MOD_OFF); 1076 hdr->dw2 = cpu_to_le32(dw2); 1077 hdr->transfer_tags = cpu_to_le32(slot->idx); 1078 1079 if (has_data) 1080 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1081 slot->n_elem); 1082 1083 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1084 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1085 1086 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1087 sizeof(struct ssp_frame_hdr); 1088 1089 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1090 if (!tmf) { 1091 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1092 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1093 } else { 1094 buf_cmd[10] = tmf->tmf; 1095 switch (tmf->tmf) { 1096 case TMF_ABORT_TASK: 1097 case TMF_QUERY_TASK: 1098 buf_cmd[12] = 1099 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1100 buf_cmd[13] = 1101 tmf->tag_of_task_to_be_managed & 0xff; 1102 break; 1103 default: 1104 break; 1105 } 1106 } 1107 1108 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1109 struct hisi_sas_protect_iu_v3_hw prot; 1110 u8 *buf_cmd_prot; 1111 1112 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1113 dw1 |= CMD_HDR_PIR_MSK; 1114 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1115 sizeof(struct ssp_frame_hdr) + 1116 sizeof(struct ssp_command_iu); 1117 1118 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1119 fill_prot_v3_hw(scsi_cmnd, &prot); 1120 memcpy(buf_cmd_prot, &prot, 1121 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1122 1123 /* 1124 * For READ, we need length of info read to memory, while for 1125 * WRITE we need length of data written to the disk. 1126 */ 1127 if (prot_op == SCSI_PROT_WRITE_INSERT) { 1128 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1129 unsigned int ilog2_interval = ilog2(interval); 1130 1131 len = (task->total_xfer_len >> ilog2_interval) * 8; 1132 } 1133 1134 } 1135 1136 hdr->dw1 = cpu_to_le32(dw1); 1137 1138 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1139 } 1140 1141 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1142 struct hisi_sas_slot *slot) 1143 { 1144 struct sas_task *task = slot->task; 1145 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1146 struct domain_device *device = task->dev; 1147 struct hisi_sas_port *port = slot->port; 1148 struct scatterlist *sg_req; 1149 struct hisi_sas_device *sas_dev = device->lldd_dev; 1150 dma_addr_t req_dma_addr; 1151 unsigned int req_len; 1152 1153 /* req */ 1154 sg_req = &task->smp_task.smp_req; 1155 req_len = sg_dma_len(sg_req); 1156 req_dma_addr = sg_dma_address(sg_req); 1157 1158 /* create header */ 1159 /* dw0 */ 1160 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1161 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1162 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1163 1164 /* map itct entry */ 1165 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1166 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1167 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1168 1169 /* dw2 */ 1170 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1171 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1172 CMD_HDR_MRFL_OFF)); 1173 1174 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1175 1176 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1177 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1178 1179 } 1180 1181 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1182 struct hisi_sas_slot *slot) 1183 { 1184 struct sas_task *task = slot->task; 1185 struct domain_device *device = task->dev; 1186 struct domain_device *parent_dev = device->parent; 1187 struct hisi_sas_device *sas_dev = device->lldd_dev; 1188 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1189 struct asd_sas_port *sas_port = device->port; 1190 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1191 u8 *buf_cmd; 1192 int has_data = 0, hdr_tag = 0; 1193 u32 dw1 = 0, dw2 = 0; 1194 1195 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1196 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1197 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1198 else 1199 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1200 1201 switch (task->data_dir) { 1202 case DMA_TO_DEVICE: 1203 has_data = 1; 1204 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1205 break; 1206 case DMA_FROM_DEVICE: 1207 has_data = 1; 1208 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1209 break; 1210 default: 1211 dw1 &= ~CMD_HDR_DIR_MSK; 1212 } 1213 1214 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1215 (task->ata_task.fis.control & ATA_SRST)) 1216 dw1 |= 1 << CMD_HDR_RESET_OFF; 1217 1218 dw1 |= (hisi_sas_get_ata_protocol( 1219 &task->ata_task.fis, task->data_dir)) 1220 << CMD_HDR_FRAME_TYPE_OFF; 1221 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1222 1223 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1224 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1225 1226 hdr->dw1 = cpu_to_le32(dw1); 1227 1228 /* dw2 */ 1229 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1230 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1231 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1232 } 1233 1234 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1235 2 << CMD_HDR_SG_MOD_OFF; 1236 hdr->dw2 = cpu_to_le32(dw2); 1237 1238 /* dw3 */ 1239 hdr->transfer_tags = cpu_to_le32(slot->idx); 1240 1241 if (has_data) 1242 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1243 slot->n_elem); 1244 1245 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1246 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1247 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1248 1249 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1250 1251 if (likely(!task->ata_task.device_control_reg_update)) 1252 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1253 /* fill in command FIS */ 1254 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1255 } 1256 1257 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1258 struct hisi_sas_slot *slot, 1259 int device_id, int abort_flag, int tag_to_abort) 1260 { 1261 struct sas_task *task = slot->task; 1262 struct domain_device *dev = task->dev; 1263 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1264 struct hisi_sas_port *port = slot->port; 1265 1266 /* dw0 */ 1267 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1268 (port->id << CMD_HDR_PORT_OFF) | 1269 (dev_is_sata(dev) 1270 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1271 (abort_flag 1272 << CMD_HDR_ABORT_FLAG_OFF)); 1273 1274 /* dw1 */ 1275 hdr->dw1 = cpu_to_le32(device_id 1276 << CMD_HDR_DEV_ID_OFF); 1277 1278 /* dw7 */ 1279 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1280 hdr->transfer_tags = cpu_to_le32(slot->idx); 1281 1282 } 1283 1284 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1285 { 1286 int i, res; 1287 u32 context, port_id, link_rate; 1288 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1289 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1290 struct device *dev = hisi_hba->dev; 1291 unsigned long flags; 1292 1293 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1294 1295 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1296 port_id = (port_id >> (4 * phy_no)) & 0xf; 1297 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1298 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1299 1300 if (port_id == 0xf) { 1301 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1302 res = IRQ_NONE; 1303 goto end; 1304 } 1305 sas_phy->linkrate = link_rate; 1306 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1307 1308 /* Check for SATA dev */ 1309 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1310 if (context & (1 << phy_no)) { 1311 struct hisi_sas_initial_fis *initial_fis; 1312 struct dev_to_host_fis *fis; 1313 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1314 1315 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1316 initial_fis = &hisi_hba->initial_fis[phy_no]; 1317 fis = &initial_fis->fis; 1318 1319 /* check ERR bit of Status Register */ 1320 if (fis->status & ATA_ERR) { 1321 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1322 phy_no, fis->status); 1323 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1324 res = IRQ_NONE; 1325 goto end; 1326 } 1327 1328 sas_phy->oob_mode = SATA_OOB_MODE; 1329 attached_sas_addr[0] = 0x50; 1330 attached_sas_addr[7] = phy_no; 1331 memcpy(sas_phy->attached_sas_addr, 1332 attached_sas_addr, 1333 SAS_ADDR_SIZE); 1334 memcpy(sas_phy->frame_rcvd, fis, 1335 sizeof(struct dev_to_host_fis)); 1336 phy->phy_type |= PORT_TYPE_SATA; 1337 phy->identify.device_type = SAS_SATA_DEV; 1338 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1339 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1340 } else { 1341 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1342 struct sas_identify_frame *id = 1343 (struct sas_identify_frame *)frame_rcvd; 1344 1345 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1346 for (i = 0; i < 6; i++) { 1347 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1348 RX_IDAF_DWORD0 + (i * 4)); 1349 frame_rcvd[i] = __swab32(idaf); 1350 } 1351 sas_phy->oob_mode = SAS_OOB_MODE; 1352 memcpy(sas_phy->attached_sas_addr, 1353 &id->sas_addr, 1354 SAS_ADDR_SIZE); 1355 phy->phy_type |= PORT_TYPE_SAS; 1356 phy->identify.device_type = id->dev_type; 1357 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1358 if (phy->identify.device_type == SAS_END_DEVICE) 1359 phy->identify.target_port_protocols = 1360 SAS_PROTOCOL_SSP; 1361 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1362 phy->identify.target_port_protocols = 1363 SAS_PROTOCOL_SMP; 1364 } 1365 1366 phy->port_id = port_id; 1367 phy->phy_attached = 1; 1368 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1369 res = IRQ_HANDLED; 1370 spin_lock_irqsave(&phy->lock, flags); 1371 if (phy->reset_completion) { 1372 phy->in_reset = 0; 1373 complete(phy->reset_completion); 1374 } 1375 spin_unlock_irqrestore(&phy->lock, flags); 1376 end: 1377 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1378 CHL_INT0_SL_PHY_ENABLE_MSK); 1379 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1380 1381 return res; 1382 } 1383 1384 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1385 { 1386 u32 phy_state, sl_ctrl, txid_auto; 1387 struct device *dev = hisi_hba->dev; 1388 1389 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1390 1391 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1392 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1393 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1394 1395 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1396 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1397 sl_ctrl&(~SL_CTA_MSK)); 1398 1399 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1400 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1401 txid_auto | CT3_MSK); 1402 1403 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1404 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1405 1406 return IRQ_HANDLED; 1407 } 1408 1409 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1410 { 1411 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1412 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1413 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1414 u32 bcast_status; 1415 1416 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1417 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1418 if ((bcast_status & RX_BCAST_CHG_MSK) && 1419 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1420 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1421 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1422 CHL_INT0_SL_RX_BCST_ACK_MSK); 1423 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1424 1425 return IRQ_HANDLED; 1426 } 1427 1428 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1429 { 1430 struct hisi_hba *hisi_hba = p; 1431 u32 irq_msk; 1432 int phy_no = 0; 1433 irqreturn_t res = IRQ_NONE; 1434 1435 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1436 & 0x11111111; 1437 while (irq_msk) { 1438 if (irq_msk & 1) { 1439 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1440 CHL_INT0); 1441 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1442 int rdy = phy_state & (1 << phy_no); 1443 1444 if (rdy) { 1445 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1446 /* phy up */ 1447 if (phy_up_v3_hw(phy_no, hisi_hba) 1448 == IRQ_HANDLED) 1449 res = IRQ_HANDLED; 1450 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1451 /* phy bcast */ 1452 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1453 == IRQ_HANDLED) 1454 res = IRQ_HANDLED; 1455 } else { 1456 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1457 /* phy down */ 1458 if (phy_down_v3_hw(phy_no, hisi_hba) 1459 == IRQ_HANDLED) 1460 res = IRQ_HANDLED; 1461 } 1462 } 1463 irq_msk >>= 4; 1464 phy_no++; 1465 } 1466 1467 return res; 1468 } 1469 1470 static const struct hisi_sas_hw_error port_axi_error[] = { 1471 { 1472 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1473 .msg = "dma_tx_axi_wr_err", 1474 }, 1475 { 1476 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1477 .msg = "dma_tx_axi_rd_err", 1478 }, 1479 { 1480 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1481 .msg = "dma_rx_axi_wr_err", 1482 }, 1483 { 1484 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1485 .msg = "dma_rx_axi_rd_err", 1486 }, 1487 }; 1488 1489 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1490 { 1491 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1492 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1493 struct device *dev = hisi_hba->dev; 1494 int i; 1495 1496 irq_value &= ~irq_msk; 1497 if (!irq_value) 1498 return; 1499 1500 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1501 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1502 1503 if (!(irq_value & error->irq_msk)) 1504 continue; 1505 1506 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1507 error->msg, phy_no, irq_value); 1508 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1509 } 1510 1511 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1512 } 1513 1514 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1515 { 1516 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1517 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1518 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1519 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1520 struct device *dev = hisi_hba->dev; 1521 1522 irq_value &= ~irq_msk; 1523 if (!irq_value) 1524 return; 1525 1526 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1527 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1528 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1529 } 1530 1531 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1532 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1533 STP_LINK_TIMEOUT_STATE); 1534 1535 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1536 phy_no, reg_value); 1537 if (reg_value & BIT(4)) 1538 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1539 } 1540 1541 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1542 (pci_dev->revision == 0x20)) { 1543 u32 reg_value; 1544 int rc; 1545 1546 rc = hisi_sas_read32_poll_timeout_atomic( 1547 HILINK_ERR_DFX, reg_value, 1548 !((reg_value >> 8) & BIT(phy_no)), 1549 1000, 10000); 1550 if (rc) 1551 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1552 } 1553 1554 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1555 } 1556 1557 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1558 { 1559 struct hisi_hba *hisi_hba = p; 1560 u32 irq_msk; 1561 int phy_no = 0; 1562 1563 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1564 & 0xeeeeeeee; 1565 1566 while (irq_msk) { 1567 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1568 CHL_INT0); 1569 1570 if (irq_msk & (4 << (phy_no * 4))) 1571 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1572 1573 if (irq_msk & (8 << (phy_no * 4))) 1574 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1575 1576 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1577 hisi_sas_phy_write32(hisi_hba, phy_no, 1578 CHL_INT0, irq_value0 1579 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1580 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1581 & (~CHL_INT0_NOT_RDY_MSK)); 1582 } 1583 irq_msk &= ~(0xe << (phy_no * 4)); 1584 phy_no++; 1585 } 1586 1587 return IRQ_HANDLED; 1588 } 1589 1590 static const struct hisi_sas_hw_error axi_error[] = { 1591 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1592 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1593 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1594 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1595 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1596 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1597 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1598 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1599 {}, 1600 }; 1601 1602 static const struct hisi_sas_hw_error fifo_error[] = { 1603 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1604 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1605 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1606 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1607 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1608 {}, 1609 }; 1610 1611 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1612 { 1613 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1614 .msg = "write pointer and depth", 1615 }, 1616 { 1617 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1618 .msg = "iptt no match slot", 1619 }, 1620 { 1621 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1622 .msg = "read pointer and depth", 1623 }, 1624 { 1625 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1626 .reg = HGC_AXI_FIFO_ERR_INFO, 1627 .sub = axi_error, 1628 }, 1629 { 1630 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1631 .reg = HGC_AXI_FIFO_ERR_INFO, 1632 .sub = fifo_error, 1633 }, 1634 { 1635 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1636 .msg = "LM add/fetch list", 1637 }, 1638 { 1639 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1640 .msg = "SAS_HGC_ABT fetch LM list", 1641 }, 1642 }; 1643 1644 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1645 { 1646 u32 irq_value, irq_msk; 1647 struct hisi_hba *hisi_hba = p; 1648 struct device *dev = hisi_hba->dev; 1649 int i; 1650 1651 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1652 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1653 1654 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1655 irq_value &= ~irq_msk; 1656 1657 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1658 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1659 1660 if (!(irq_value & error->irq_msk)) 1661 continue; 1662 1663 if (error->sub) { 1664 const struct hisi_sas_hw_error *sub = error->sub; 1665 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1666 1667 for (; sub->msk || sub->msg; sub++) { 1668 if (!(err_value & sub->msk)) 1669 continue; 1670 1671 dev_err(dev, "%s error (0x%x) found!\n", 1672 sub->msg, irq_value); 1673 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1674 } 1675 } else { 1676 dev_err(dev, "%s error (0x%x) found!\n", 1677 error->msg, irq_value); 1678 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1679 } 1680 } 1681 1682 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1683 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1684 u32 dev_id = reg_val & ITCT_DEV_MSK; 1685 struct hisi_sas_device *sas_dev = 1686 &hisi_hba->devices[dev_id]; 1687 1688 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1689 dev_dbg(dev, "clear ITCT ok\n"); 1690 complete(sas_dev->completion); 1691 } 1692 1693 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1694 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1695 1696 return IRQ_HANDLED; 1697 } 1698 1699 static void 1700 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1701 struct hisi_sas_slot *slot) 1702 { 1703 struct task_status_struct *ts = &task->task_status; 1704 struct hisi_sas_complete_v3_hdr *complete_queue = 1705 hisi_hba->complete_hdr[slot->cmplt_queue]; 1706 struct hisi_sas_complete_v3_hdr *complete_hdr = 1707 &complete_queue[slot->cmplt_queue_slot]; 1708 struct hisi_sas_err_record_v3 *record = 1709 hisi_sas_status_buf_addr_mem(slot); 1710 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 1711 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 1712 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 1713 1714 switch (task->task_proto) { 1715 case SAS_PROTOCOL_SSP: 1716 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1717 ts->residual = trans_tx_fail_type; 1718 ts->stat = SAS_DATA_UNDERRUN; 1719 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1720 ts->stat = SAS_QUEUE_FULL; 1721 slot->abort = 1; 1722 } else { 1723 ts->stat = SAS_OPEN_REJECT; 1724 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1725 } 1726 break; 1727 case SAS_PROTOCOL_SATA: 1728 case SAS_PROTOCOL_STP: 1729 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1730 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1731 ts->residual = trans_tx_fail_type; 1732 ts->stat = SAS_DATA_UNDERRUN; 1733 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1734 ts->stat = SAS_PHY_DOWN; 1735 slot->abort = 1; 1736 } else { 1737 ts->stat = SAS_OPEN_REJECT; 1738 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1739 } 1740 hisi_sas_sata_done(task, slot); 1741 break; 1742 case SAS_PROTOCOL_SMP: 1743 ts->stat = SAM_STAT_CHECK_CONDITION; 1744 break; 1745 default: 1746 break; 1747 } 1748 } 1749 1750 static int 1751 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1752 { 1753 struct sas_task *task = slot->task; 1754 struct hisi_sas_device *sas_dev; 1755 struct device *dev = hisi_hba->dev; 1756 struct task_status_struct *ts; 1757 struct domain_device *device; 1758 struct sas_ha_struct *ha; 1759 enum exec_status sts; 1760 struct hisi_sas_complete_v3_hdr *complete_queue = 1761 hisi_hba->complete_hdr[slot->cmplt_queue]; 1762 struct hisi_sas_complete_v3_hdr *complete_hdr = 1763 &complete_queue[slot->cmplt_queue_slot]; 1764 unsigned long flags; 1765 bool is_internal = slot->is_internal; 1766 u32 dw0, dw1, dw3; 1767 1768 if (unlikely(!task || !task->lldd_task || !task->dev)) 1769 return -EINVAL; 1770 1771 ts = &task->task_status; 1772 device = task->dev; 1773 ha = device->port->ha; 1774 sas_dev = device->lldd_dev; 1775 1776 spin_lock_irqsave(&task->task_state_lock, flags); 1777 task->task_state_flags &= 1778 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1779 spin_unlock_irqrestore(&task->task_state_lock, flags); 1780 1781 memset(ts, 0, sizeof(*ts)); 1782 ts->resp = SAS_TASK_COMPLETE; 1783 1784 if (unlikely(!sas_dev)) { 1785 dev_dbg(dev, "slot complete: port has not device\n"); 1786 ts->stat = SAS_PHY_DOWN; 1787 goto out; 1788 } 1789 1790 dw0 = le32_to_cpu(complete_hdr->dw0); 1791 dw1 = le32_to_cpu(complete_hdr->dw1); 1792 dw3 = le32_to_cpu(complete_hdr->dw3); 1793 1794 /* 1795 * Use SAS+TMF status codes 1796 */ 1797 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 1798 case STAT_IO_ABORTED: 1799 /* this IO has been aborted by abort command */ 1800 ts->stat = SAS_ABORTED_TASK; 1801 goto out; 1802 case STAT_IO_COMPLETE: 1803 /* internal abort command complete */ 1804 ts->stat = TMF_RESP_FUNC_SUCC; 1805 goto out; 1806 case STAT_IO_NO_DEVICE: 1807 ts->stat = TMF_RESP_FUNC_COMPLETE; 1808 goto out; 1809 case STAT_IO_NOT_VALID: 1810 /* 1811 * abort single IO, the controller can't find the IO 1812 */ 1813 ts->stat = TMF_RESP_FUNC_FAILED; 1814 goto out; 1815 default: 1816 break; 1817 } 1818 1819 /* check for erroneous completion */ 1820 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1821 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1822 1823 slot_err_v3_hw(hisi_hba, task, slot); 1824 if (ts->stat != SAS_DATA_UNDERRUN) 1825 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1826 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1827 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1828 slot->idx, task, sas_dev->device_id, 1829 dw0, dw1, complete_hdr->act, dw3, 1830 error_info[0], error_info[1], 1831 error_info[2], error_info[3]); 1832 if (unlikely(slot->abort)) 1833 return ts->stat; 1834 goto out; 1835 } 1836 1837 switch (task->task_proto) { 1838 case SAS_PROTOCOL_SSP: { 1839 struct ssp_response_iu *iu = 1840 hisi_sas_status_buf_addr_mem(slot) + 1841 sizeof(struct hisi_sas_err_record); 1842 1843 sas_ssp_task_response(dev, task, iu); 1844 break; 1845 } 1846 case SAS_PROTOCOL_SMP: { 1847 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1848 void *to; 1849 1850 ts->stat = SAM_STAT_GOOD; 1851 to = kmap_atomic(sg_page(sg_resp)); 1852 1853 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1854 DMA_FROM_DEVICE); 1855 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1856 DMA_TO_DEVICE); 1857 memcpy(to + sg_resp->offset, 1858 hisi_sas_status_buf_addr_mem(slot) + 1859 sizeof(struct hisi_sas_err_record), 1860 sg_dma_len(sg_resp)); 1861 kunmap_atomic(to); 1862 break; 1863 } 1864 case SAS_PROTOCOL_SATA: 1865 case SAS_PROTOCOL_STP: 1866 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1867 ts->stat = SAM_STAT_GOOD; 1868 hisi_sas_sata_done(task, slot); 1869 break; 1870 default: 1871 ts->stat = SAM_STAT_CHECK_CONDITION; 1872 break; 1873 } 1874 1875 if (!slot->port->port_attached) { 1876 dev_warn(dev, "slot complete: port %d has removed\n", 1877 slot->port->sas_port.id); 1878 ts->stat = SAS_PHY_DOWN; 1879 } 1880 1881 out: 1882 sts = ts->stat; 1883 spin_lock_irqsave(&task->task_state_lock, flags); 1884 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1885 spin_unlock_irqrestore(&task->task_state_lock, flags); 1886 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1887 return SAS_ABORTED_TASK; 1888 } 1889 task->task_state_flags |= SAS_TASK_STATE_DONE; 1890 spin_unlock_irqrestore(&task->task_state_lock, flags); 1891 hisi_sas_slot_task_free(hisi_hba, task, slot); 1892 1893 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1894 spin_lock_irqsave(&device->done_lock, flags); 1895 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1896 spin_unlock_irqrestore(&device->done_lock, flags); 1897 dev_info(dev, "slot complete: task(%p) ignored\n ", 1898 task); 1899 return sts; 1900 } 1901 spin_unlock_irqrestore(&device->done_lock, flags); 1902 } 1903 1904 if (task->task_done) 1905 task->task_done(task); 1906 1907 return sts; 1908 } 1909 1910 static void cq_tasklet_v3_hw(unsigned long val) 1911 { 1912 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1913 struct hisi_hba *hisi_hba = cq->hisi_hba; 1914 struct hisi_sas_slot *slot; 1915 struct hisi_sas_complete_v3_hdr *complete_queue; 1916 u32 rd_point = cq->rd_point, wr_point; 1917 int queue = cq->id; 1918 1919 complete_queue = hisi_hba->complete_hdr[queue]; 1920 1921 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1922 (0x14 * queue)); 1923 1924 while (rd_point != wr_point) { 1925 struct hisi_sas_complete_v3_hdr *complete_hdr; 1926 struct device *dev = hisi_hba->dev; 1927 u32 dw1; 1928 int iptt; 1929 1930 complete_hdr = &complete_queue[rd_point]; 1931 dw1 = le32_to_cpu(complete_hdr->dw1); 1932 1933 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 1934 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 1935 slot = &hisi_hba->slot_info[iptt]; 1936 slot->cmplt_queue_slot = rd_point; 1937 slot->cmplt_queue = queue; 1938 slot_complete_v3_hw(hisi_hba, slot); 1939 } else 1940 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 1941 1942 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1943 rd_point = 0; 1944 } 1945 1946 /* update rd_point */ 1947 cq->rd_point = rd_point; 1948 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1949 } 1950 1951 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1952 { 1953 struct hisi_sas_cq *cq = p; 1954 struct hisi_hba *hisi_hba = cq->hisi_hba; 1955 int queue = cq->id; 1956 1957 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1958 1959 tasklet_schedule(&cq->tasklet); 1960 1961 return IRQ_HANDLED; 1962 } 1963 1964 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1965 { 1966 struct device *dev = hisi_hba->dev; 1967 struct pci_dev *pdev = hisi_hba->pci_dev; 1968 int vectors, rc; 1969 int i, k; 1970 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1971 1972 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1973 max_msi, PCI_IRQ_MSI); 1974 if (vectors < max_msi) { 1975 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1976 return -ENOENT; 1977 } 1978 1979 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1980 int_phy_up_down_bcast_v3_hw, 0, 1981 DRV_NAME " phy", hisi_hba); 1982 if (rc) { 1983 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1984 rc = -ENOENT; 1985 goto free_irq_vectors; 1986 } 1987 1988 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1989 int_chnl_int_v3_hw, 0, 1990 DRV_NAME " channel", hisi_hba); 1991 if (rc) { 1992 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1993 rc = -ENOENT; 1994 goto free_phy_irq; 1995 } 1996 1997 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1998 fatal_axi_int_v3_hw, 0, 1999 DRV_NAME " fatal", hisi_hba); 2000 if (rc) { 2001 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2002 rc = -ENOENT; 2003 goto free_chnl_interrupt; 2004 } 2005 2006 /* Init tasklets for cq only */ 2007 for (i = 0; i < hisi_hba->queue_count; i++) { 2008 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2009 struct tasklet_struct *t = &cq->tasklet; 2010 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2011 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2012 2013 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2014 cq_interrupt_v3_hw, irqflags, 2015 DRV_NAME " cq", cq); 2016 if (rc) { 2017 dev_err(dev, 2018 "could not request cq%d interrupt, rc=%d\n", 2019 i, rc); 2020 rc = -ENOENT; 2021 goto free_cq_irqs; 2022 } 2023 2024 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2025 } 2026 2027 return 0; 2028 2029 free_cq_irqs: 2030 for (k = 0; k < i; k++) { 2031 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2032 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2033 2034 free_irq(pci_irq_vector(pdev, nr), cq); 2035 } 2036 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2037 free_chnl_interrupt: 2038 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2039 free_phy_irq: 2040 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2041 free_irq_vectors: 2042 pci_free_irq_vectors(pdev); 2043 return rc; 2044 } 2045 2046 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2047 { 2048 int rc; 2049 2050 rc = hw_init_v3_hw(hisi_hba); 2051 if (rc) 2052 return rc; 2053 2054 rc = interrupt_init_v3_hw(hisi_hba); 2055 if (rc) 2056 return rc; 2057 2058 return 0; 2059 } 2060 2061 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2062 struct sas_phy_linkrates *r) 2063 { 2064 enum sas_linkrate max = r->maximum_linkrate; 2065 u32 prog_phy_link_rate = 0x800; 2066 2067 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2068 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2069 prog_phy_link_rate); 2070 } 2071 2072 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2073 { 2074 struct pci_dev *pdev = hisi_hba->pci_dev; 2075 int i; 2076 2077 synchronize_irq(pci_irq_vector(pdev, 1)); 2078 synchronize_irq(pci_irq_vector(pdev, 2)); 2079 synchronize_irq(pci_irq_vector(pdev, 11)); 2080 for (i = 0; i < hisi_hba->queue_count; i++) { 2081 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2082 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2083 } 2084 2085 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2086 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2087 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2088 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2089 2090 for (i = 0; i < hisi_hba->n_phy; i++) { 2091 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2092 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2093 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2094 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2095 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2096 } 2097 } 2098 2099 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2100 { 2101 return hisi_sas_read32(hisi_hba, PHY_STATE); 2102 } 2103 2104 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 2105 { 2106 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2107 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2108 struct sas_phy *sphy = sas_phy->phy; 2109 u32 reg_value; 2110 2111 /* loss dword sync */ 2112 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 2113 sphy->loss_of_dword_sync_count += reg_value; 2114 2115 /* phy reset problem */ 2116 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 2117 sphy->phy_reset_problem_count += reg_value; 2118 2119 /* invalid dword */ 2120 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 2121 sphy->invalid_dword_count += reg_value; 2122 2123 /* disparity err */ 2124 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 2125 sphy->running_disparity_error_count += reg_value; 2126 2127 } 2128 2129 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2130 { 2131 struct device *dev = hisi_hba->dev; 2132 u32 status, reg_val; 2133 int rc; 2134 2135 interrupt_disable_v3_hw(hisi_hba); 2136 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2137 hisi_sas_kill_tasklets(hisi_hba); 2138 2139 hisi_sas_stop_phys(hisi_hba); 2140 2141 mdelay(10); 2142 2143 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2144 AM_CTRL_GLOBAL); 2145 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2146 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2147 AM_CTRL_GLOBAL, reg_val); 2148 2149 /* wait until bus idle */ 2150 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2151 AM_CURR_TRANS_RETURN, status, 2152 status == 0x3, 10, 100); 2153 if (rc) { 2154 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2155 return rc; 2156 } 2157 2158 return 0; 2159 } 2160 2161 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2162 { 2163 struct device *dev = hisi_hba->dev; 2164 int rc; 2165 2166 rc = disable_host_v3_hw(hisi_hba); 2167 if (rc) { 2168 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2169 return rc; 2170 } 2171 2172 hisi_sas_init_mem(hisi_hba); 2173 2174 return hw_init_v3_hw(hisi_hba); 2175 } 2176 2177 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2178 u8 reg_index, u8 reg_count, u8 *write_data) 2179 { 2180 struct device *dev = hisi_hba->dev; 2181 u32 *data = (u32 *)write_data; 2182 int i; 2183 2184 switch (reg_type) { 2185 case SAS_GPIO_REG_TX: 2186 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2187 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2188 reg_index, reg_index + reg_count - 1); 2189 return -EINVAL; 2190 } 2191 2192 for (i = 0; i < reg_count; i++) 2193 hisi_sas_write32(hisi_hba, 2194 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2195 data[i]); 2196 break; 2197 default: 2198 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2199 reg_type); 2200 return -EINVAL; 2201 } 2202 2203 return 0; 2204 } 2205 2206 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2207 int delay_ms, int timeout_ms) 2208 { 2209 struct device *dev = hisi_hba->dev; 2210 int entries, entries_old = 0, time; 2211 2212 for (time = 0; time < timeout_ms; time += delay_ms) { 2213 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2214 if (entries == entries_old) 2215 break; 2216 2217 entries_old = entries; 2218 msleep(delay_ms); 2219 } 2220 2221 dev_dbg(dev, "wait commands complete %dms\n", time); 2222 } 2223 2224 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2225 struct device_attribute *attr, char *buf) 2226 { 2227 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2228 } 2229 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2230 2231 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2232 { 2233 /* config those registers between enable and disable PHYs */ 2234 hisi_sas_stop_phys(hisi_hba); 2235 2236 if (hisi_hba->intr_coal_ticks == 0 || 2237 hisi_hba->intr_coal_count == 0) { 2238 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2239 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2240 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2241 } else { 2242 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2243 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2244 hisi_hba->intr_coal_ticks); 2245 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2246 hisi_hba->intr_coal_count); 2247 } 2248 phys_init_v3_hw(hisi_hba); 2249 } 2250 2251 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2252 struct device_attribute *attr, 2253 char *buf) 2254 { 2255 struct Scsi_Host *shost = class_to_shost(dev); 2256 struct hisi_hba *hisi_hba = shost_priv(shost); 2257 2258 return scnprintf(buf, PAGE_SIZE, "%u\n", 2259 hisi_hba->intr_coal_ticks); 2260 } 2261 2262 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2263 struct device_attribute *attr, 2264 const char *buf, size_t count) 2265 { 2266 struct Scsi_Host *shost = class_to_shost(dev); 2267 struct hisi_hba *hisi_hba = shost_priv(shost); 2268 u32 intr_coal_ticks; 2269 int ret; 2270 2271 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2272 if (ret) { 2273 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2274 return -EINVAL; 2275 } 2276 2277 if (intr_coal_ticks >= BIT(24)) { 2278 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2279 return -EINVAL; 2280 } 2281 2282 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2283 2284 config_intr_coal_v3_hw(hisi_hba); 2285 2286 return count; 2287 } 2288 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2289 2290 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2291 struct device_attribute 2292 *attr, char *buf) 2293 { 2294 struct Scsi_Host *shost = class_to_shost(dev); 2295 struct hisi_hba *hisi_hba = shost_priv(shost); 2296 2297 return scnprintf(buf, PAGE_SIZE, "%u\n", 2298 hisi_hba->intr_coal_count); 2299 } 2300 2301 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2302 struct device_attribute 2303 *attr, const char *buf, size_t count) 2304 { 2305 struct Scsi_Host *shost = class_to_shost(dev); 2306 struct hisi_hba *hisi_hba = shost_priv(shost); 2307 u32 intr_coal_count; 2308 int ret; 2309 2310 ret = kstrtou32(buf, 10, &intr_coal_count); 2311 if (ret) { 2312 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2313 return -EINVAL; 2314 } 2315 2316 if (intr_coal_count >= BIT(8)) { 2317 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2318 return -EINVAL; 2319 } 2320 2321 hisi_hba->intr_coal_count = intr_coal_count; 2322 2323 config_intr_coal_v3_hw(hisi_hba); 2324 2325 return count; 2326 } 2327 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2328 2329 static struct device_attribute *host_attrs_v3_hw[] = { 2330 &dev_attr_phy_event_threshold, 2331 &dev_attr_intr_conv_v3_hw, 2332 &dev_attr_intr_coal_ticks_v3_hw, 2333 &dev_attr_intr_coal_count_v3_hw, 2334 NULL 2335 }; 2336 2337 static struct scsi_host_template sht_v3_hw = { 2338 .name = DRV_NAME, 2339 .module = THIS_MODULE, 2340 .queuecommand = sas_queuecommand, 2341 .target_alloc = sas_target_alloc, 2342 .slave_configure = hisi_sas_slave_configure, 2343 .scan_finished = hisi_sas_scan_finished, 2344 .scan_start = hisi_sas_scan_start, 2345 .change_queue_depth = sas_change_queue_depth, 2346 .bios_param = sas_bios_param, 2347 .this_id = -1, 2348 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2349 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2350 .eh_device_reset_handler = sas_eh_device_reset_handler, 2351 .eh_target_reset_handler = sas_eh_target_reset_handler, 2352 .target_destroy = sas_target_destroy, 2353 .ioctl = sas_ioctl, 2354 .shost_attrs = host_attrs_v3_hw, 2355 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2356 }; 2357 2358 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2359 .hw_init = hisi_sas_v3_init, 2360 .setup_itct = setup_itct_v3_hw, 2361 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2362 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2363 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2364 .clear_itct = clear_itct_v3_hw, 2365 .sl_notify = sl_notify_v3_hw, 2366 .prep_ssp = prep_ssp_v3_hw, 2367 .prep_smp = prep_smp_v3_hw, 2368 .prep_stp = prep_ata_v3_hw, 2369 .prep_abort = prep_abort_v3_hw, 2370 .get_free_slot = get_free_slot_v3_hw, 2371 .start_delivery = start_delivery_v3_hw, 2372 .slot_complete = slot_complete_v3_hw, 2373 .phys_init = phys_init_v3_hw, 2374 .phy_start = start_phy_v3_hw, 2375 .phy_disable = disable_phy_v3_hw, 2376 .phy_hard_reset = phy_hard_reset_v3_hw, 2377 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2378 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2379 .dereg_device = dereg_device_v3_hw, 2380 .soft_reset = soft_reset_v3_hw, 2381 .get_phys_state = get_phys_state_v3_hw, 2382 .get_events = phy_get_events_v3_hw, 2383 .write_gpio = write_gpio_v3_hw, 2384 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2385 }; 2386 2387 static struct Scsi_Host * 2388 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2389 { 2390 struct Scsi_Host *shost; 2391 struct hisi_hba *hisi_hba; 2392 struct device *dev = &pdev->dev; 2393 2394 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2395 if (!shost) { 2396 dev_err(dev, "shost alloc failed\n"); 2397 return NULL; 2398 } 2399 hisi_hba = shost_priv(shost); 2400 2401 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2402 hisi_hba->hw = &hisi_sas_v3_hw; 2403 hisi_hba->pci_dev = pdev; 2404 hisi_hba->dev = dev; 2405 hisi_hba->shost = shost; 2406 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2407 2408 if (prot_mask & ~HISI_SAS_PROT_MASK) 2409 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2410 prot_mask); 2411 else 2412 hisi_hba->prot_mask = prot_mask; 2413 2414 timer_setup(&hisi_hba->timer, NULL, 0); 2415 2416 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2417 goto err_out; 2418 2419 if (hisi_sas_alloc(hisi_hba, shost)) { 2420 hisi_sas_free(hisi_hba); 2421 goto err_out; 2422 } 2423 2424 return shost; 2425 err_out: 2426 scsi_host_put(shost); 2427 dev_err(dev, "shost alloc failed\n"); 2428 return NULL; 2429 } 2430 2431 static int 2432 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2433 { 2434 struct Scsi_Host *shost; 2435 struct hisi_hba *hisi_hba; 2436 struct device *dev = &pdev->dev; 2437 struct asd_sas_phy **arr_phy; 2438 struct asd_sas_port **arr_port; 2439 struct sas_ha_struct *sha; 2440 int rc, phy_nr, port_nr, i; 2441 2442 rc = pci_enable_device(pdev); 2443 if (rc) 2444 goto err_out; 2445 2446 pci_set_master(pdev); 2447 2448 rc = pci_request_regions(pdev, DRV_NAME); 2449 if (rc) 2450 goto err_out_disable_device; 2451 2452 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) || 2453 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { 2454 dev_err(dev, "No usable DMA addressing method\n"); 2455 rc = -EIO; 2456 goto err_out_regions; 2457 } 2458 2459 shost = hisi_sas_shost_alloc_pci(pdev); 2460 if (!shost) { 2461 rc = -ENOMEM; 2462 goto err_out_regions; 2463 } 2464 2465 sha = SHOST_TO_SAS_HA(shost); 2466 hisi_hba = shost_priv(shost); 2467 dev_set_drvdata(dev, sha); 2468 2469 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2470 if (!hisi_hba->regs) { 2471 dev_err(dev, "cannot map register.\n"); 2472 rc = -ENOMEM; 2473 goto err_out_ha; 2474 } 2475 2476 phy_nr = port_nr = hisi_hba->n_phy; 2477 2478 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2479 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2480 if (!arr_phy || !arr_port) { 2481 rc = -ENOMEM; 2482 goto err_out_ha; 2483 } 2484 2485 sha->sas_phy = arr_phy; 2486 sha->sas_port = arr_port; 2487 sha->core.shost = shost; 2488 sha->lldd_ha = hisi_hba; 2489 2490 shost->transportt = hisi_sas_stt; 2491 shost->max_id = HISI_SAS_MAX_DEVICES; 2492 shost->max_lun = ~0; 2493 shost->max_channel = 1; 2494 shost->max_cmd_len = 16; 2495 shost->can_queue = hisi_hba->hw->max_command_entries - 2496 HISI_SAS_RESERVED_IPTT_CNT; 2497 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 2498 HISI_SAS_RESERVED_IPTT_CNT; 2499 2500 sha->sas_ha_name = DRV_NAME; 2501 sha->dev = dev; 2502 sha->lldd_module = THIS_MODULE; 2503 sha->sas_addr = &hisi_hba->sas_addr[0]; 2504 sha->num_phys = hisi_hba->n_phy; 2505 sha->core.shost = hisi_hba->shost; 2506 2507 for (i = 0; i < hisi_hba->n_phy; i++) { 2508 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2509 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2510 } 2511 2512 rc = scsi_add_host(shost, dev); 2513 if (rc) 2514 goto err_out_ha; 2515 2516 rc = sas_register_ha(sha); 2517 if (rc) 2518 goto err_out_register_ha; 2519 2520 rc = hisi_hba->hw->hw_init(hisi_hba); 2521 if (rc) 2522 goto err_out_register_ha; 2523 2524 if (hisi_hba->prot_mask) { 2525 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 2526 prot_mask); 2527 scsi_host_set_prot(hisi_hba->shost, prot_mask); 2528 } 2529 2530 scsi_scan_host(shost); 2531 2532 return 0; 2533 2534 err_out_register_ha: 2535 scsi_remove_host(shost); 2536 err_out_ha: 2537 scsi_host_put(shost); 2538 err_out_regions: 2539 pci_release_regions(pdev); 2540 err_out_disable_device: 2541 pci_disable_device(pdev); 2542 err_out: 2543 return rc; 2544 } 2545 2546 static void 2547 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2548 { 2549 int i; 2550 2551 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2552 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2553 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2554 for (i = 0; i < hisi_hba->queue_count; i++) { 2555 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2556 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2557 2558 free_irq(pci_irq_vector(pdev, nr), cq); 2559 } 2560 pci_free_irq_vectors(pdev); 2561 } 2562 2563 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2564 { 2565 struct device *dev = &pdev->dev; 2566 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2567 struct hisi_hba *hisi_hba = sha->lldd_ha; 2568 struct Scsi_Host *shost = sha->core.shost; 2569 2570 if (timer_pending(&hisi_hba->timer)) 2571 del_timer(&hisi_hba->timer); 2572 2573 sas_unregister_ha(sha); 2574 sas_remove_host(sha->core.shost); 2575 2576 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2577 hisi_sas_kill_tasklets(hisi_hba); 2578 pci_release_regions(pdev); 2579 pci_disable_device(pdev); 2580 hisi_sas_free(hisi_hba); 2581 scsi_host_put(shost); 2582 } 2583 2584 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2585 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2586 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2587 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2588 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2589 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2590 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2591 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2592 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2593 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2594 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2595 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2596 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2597 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2598 }; 2599 2600 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2601 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2602 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2603 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2604 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2605 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2606 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2607 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2608 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2609 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2610 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2611 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2612 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2613 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2614 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2615 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2616 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2617 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2618 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2619 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2620 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2621 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2622 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2623 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2624 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2625 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2626 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2627 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2628 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2629 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2630 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2631 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2632 }; 2633 2634 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2635 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2636 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2637 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2638 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2639 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2640 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2641 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2642 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2643 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2644 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2645 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2646 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2647 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2648 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2649 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2650 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2651 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2652 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2653 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2654 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2655 }; 2656 2657 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2658 { 2659 struct device *dev = hisi_hba->dev; 2660 const struct hisi_sas_hw_error *ras_error; 2661 bool need_reset = false; 2662 u32 irq_value; 2663 int i; 2664 2665 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2666 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2667 ras_error = &sas_ras_intr0_nfe[i]; 2668 if (ras_error->irq_msk & irq_value) { 2669 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2670 ras_error->msg, irq_value); 2671 need_reset = true; 2672 } 2673 } 2674 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2675 2676 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2677 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2678 ras_error = &sas_ras_intr1_nfe[i]; 2679 if (ras_error->irq_msk & irq_value) { 2680 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2681 ras_error->msg, irq_value); 2682 need_reset = true; 2683 } 2684 } 2685 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2686 2687 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2688 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2689 ras_error = &sas_ras_intr2_nfe[i]; 2690 if (ras_error->irq_msk & irq_value) { 2691 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2692 ras_error->msg, irq_value); 2693 need_reset = true; 2694 } 2695 } 2696 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2697 2698 return need_reset; 2699 } 2700 2701 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2702 pci_channel_state_t state) 2703 { 2704 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2705 struct hisi_hba *hisi_hba = sha->lldd_ha; 2706 struct device *dev = hisi_hba->dev; 2707 2708 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2709 if (state == pci_channel_io_perm_failure) 2710 return PCI_ERS_RESULT_DISCONNECT; 2711 2712 if (process_non_fatal_error_v3_hw(hisi_hba)) 2713 return PCI_ERS_RESULT_NEED_RESET; 2714 2715 return PCI_ERS_RESULT_CAN_RECOVER; 2716 } 2717 2718 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2719 { 2720 return PCI_ERS_RESULT_RECOVERED; 2721 } 2722 2723 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2724 { 2725 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2726 struct hisi_hba *hisi_hba = sha->lldd_ha; 2727 struct device *dev = hisi_hba->dev; 2728 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2729 2730 dev_info(dev, "PCI error: slot reset callback!!\n"); 2731 queue_work(hisi_hba->wq, &r.work); 2732 wait_for_completion(r.completion); 2733 if (r.done) 2734 return PCI_ERS_RESULT_RECOVERED; 2735 2736 return PCI_ERS_RESULT_DISCONNECT; 2737 } 2738 2739 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 2740 { 2741 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2742 struct hisi_hba *hisi_hba = sha->lldd_ha; 2743 struct device *dev = hisi_hba->dev; 2744 int rc; 2745 2746 dev_info(dev, "FLR prepare\n"); 2747 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2748 hisi_sas_controller_reset_prepare(hisi_hba); 2749 2750 rc = disable_host_v3_hw(hisi_hba); 2751 if (rc) 2752 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 2753 } 2754 2755 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 2756 { 2757 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2758 struct hisi_hba *hisi_hba = sha->lldd_ha; 2759 struct device *dev = hisi_hba->dev; 2760 int rc; 2761 2762 hisi_sas_init_mem(hisi_hba); 2763 2764 rc = hw_init_v3_hw(hisi_hba); 2765 if (rc) { 2766 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 2767 return; 2768 } 2769 2770 hisi_sas_controller_reset_done(hisi_hba); 2771 dev_info(dev, "FLR done\n"); 2772 } 2773 2774 enum { 2775 /* instances of the controller */ 2776 hip08, 2777 }; 2778 2779 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2780 { 2781 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2782 struct hisi_hba *hisi_hba = sha->lldd_ha; 2783 struct device *dev = hisi_hba->dev; 2784 struct Scsi_Host *shost = hisi_hba->shost; 2785 pci_power_t device_state; 2786 int rc; 2787 2788 if (!pdev->pm_cap) { 2789 dev_err(dev, "PCI PM not supported\n"); 2790 return -ENODEV; 2791 } 2792 2793 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 2794 return -1; 2795 2796 scsi_block_requests(shost); 2797 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2798 flush_workqueue(hisi_hba->wq); 2799 2800 rc = disable_host_v3_hw(hisi_hba); 2801 if (rc) { 2802 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 2803 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2804 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2805 scsi_unblock_requests(shost); 2806 return rc; 2807 } 2808 2809 hisi_sas_init_mem(hisi_hba); 2810 2811 device_state = pci_choose_state(pdev, state); 2812 dev_warn(dev, "entering operating state [D%d]\n", 2813 device_state); 2814 pci_save_state(pdev); 2815 pci_disable_device(pdev); 2816 pci_set_power_state(pdev, device_state); 2817 2818 hisi_sas_release_tasks(hisi_hba); 2819 2820 sas_suspend_ha(sha); 2821 return 0; 2822 } 2823 2824 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2825 { 2826 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2827 struct hisi_hba *hisi_hba = sha->lldd_ha; 2828 struct Scsi_Host *shost = hisi_hba->shost; 2829 struct device *dev = hisi_hba->dev; 2830 unsigned int rc; 2831 pci_power_t device_state = pdev->current_state; 2832 2833 dev_warn(dev, "resuming from operating state [D%d]\n", 2834 device_state); 2835 pci_set_power_state(pdev, PCI_D0); 2836 pci_enable_wake(pdev, PCI_D0, 0); 2837 pci_restore_state(pdev); 2838 rc = pci_enable_device(pdev); 2839 if (rc) 2840 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2841 2842 pci_set_master(pdev); 2843 scsi_unblock_requests(shost); 2844 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2845 2846 sas_prep_resume_ha(sha); 2847 init_reg_v3_hw(hisi_hba); 2848 hisi_hba->hw->phys_init(hisi_hba); 2849 sas_resume_ha(sha); 2850 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2851 2852 return 0; 2853 } 2854 2855 static const struct pci_device_id sas_v3_pci_table[] = { 2856 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2857 {} 2858 }; 2859 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 2860 2861 static const struct pci_error_handlers hisi_sas_err_handler = { 2862 .error_detected = hisi_sas_error_detected_v3_hw, 2863 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2864 .slot_reset = hisi_sas_slot_reset_v3_hw, 2865 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 2866 .reset_done = hisi_sas_reset_done_v3_hw, 2867 }; 2868 2869 static struct pci_driver sas_v3_pci_driver = { 2870 .name = DRV_NAME, 2871 .id_table = sas_v3_pci_table, 2872 .probe = hisi_sas_v3_probe, 2873 .remove = hisi_sas_v3_remove, 2874 .suspend = hisi_sas_v3_suspend, 2875 .resume = hisi_sas_v3_resume, 2876 .err_handler = &hisi_sas_err_handler, 2877 }; 2878 2879 module_pci_driver(sas_v3_pci_driver); 2880 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 2881 2882 MODULE_LICENSE("GPL"); 2883 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2884 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2885 MODULE_ALIAS("pci:" DRV_NAME); 2886