1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2017 Hisilicon Limited.
4  */
5 
6 #include <linux/sched/clock.h>
7 #include "hisi_sas.h"
8 #define DRV_NAME "hisi_sas_v3_hw"
9 
10 /* global registers need init */
11 #define DLVRY_QUEUE_ENABLE		0x0
12 #define IOST_BASE_ADDR_LO		0x8
13 #define IOST_BASE_ADDR_HI		0xc
14 #define ITCT_BASE_ADDR_LO		0x10
15 #define ITCT_BASE_ADDR_HI		0x14
16 #define IO_BROKEN_MSG_ADDR_LO		0x18
17 #define IO_BROKEN_MSG_ADDR_HI		0x1c
18 #define PHY_CONTEXT			0x20
19 #define PHY_STATE			0x24
20 #define PHY_PORT_NUM_MA			0x28
21 #define PHY_CONN_RATE			0x30
22 #define ITCT_CLR			0x44
23 #define ITCT_CLR_EN_OFF			16
24 #define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)
25 #define ITCT_DEV_OFF			0
26 #define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)
27 #define SAS_AXI_USER3			0x50
28 #define IO_SATA_BROKEN_MSG_ADDR_LO	0x58
29 #define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c
30 #define SATA_INITI_D2H_STORE_ADDR_LO	0x60
31 #define SATA_INITI_D2H_STORE_ADDR_HI	0x64
32 #define CFG_MAX_TAG			0x68
33 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84
34 #define HGC_SAS_TXFAIL_RETRY_CTRL	0x88
35 #define HGC_GET_ITV_TIME		0x90
36 #define DEVICE_MSG_WORK_MODE		0x94
37 #define OPENA_WT_CONTI_TIME		0x9c
38 #define I_T_NEXUS_LOSS_TIME		0xa0
39 #define MAX_CON_TIME_LIMIT_TIME		0xa4
40 #define BUS_INACTIVE_LIMIT_TIME		0xa8
41 #define REJECT_TO_OPEN_LIMIT_TIME	0xac
42 #define CQ_INT_CONVERGE_EN		0xb0
43 #define CFG_AGING_TIME			0xbc
44 #define HGC_DFX_CFG2			0xc0
45 #define CFG_ABT_SET_QUERY_IPTT	0xd4
46 #define CFG_SET_ABORTED_IPTT_OFF	0
47 #define CFG_SET_ABORTED_IPTT_MSK	(0xfff << CFG_SET_ABORTED_IPTT_OFF)
48 #define CFG_SET_ABORTED_EN_OFF	12
49 #define CFG_ABT_SET_IPTT_DONE	0xd8
50 #define CFG_ABT_SET_IPTT_DONE_OFF	0
51 #define HGC_IOMB_PROC1_STATUS	0x104
52 #define HGC_LM_DFX_STATUS2		0x128
53 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF		0
54 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK	(0xfff << \
55 					 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
56 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF		12
57 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK	(0x7ff << \
58 					 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
59 #define HGC_CQE_ECC_ADDR		0x13c
60 #define HGC_CQE_ECC_1B_ADDR_OFF	0
61 #define HGC_CQE_ECC_1B_ADDR_MSK	(0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
62 #define HGC_CQE_ECC_MB_ADDR_OFF	8
63 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
64 #define HGC_IOST_ECC_ADDR		0x140
65 #define HGC_IOST_ECC_1B_ADDR_OFF	0
66 #define HGC_IOST_ECC_1B_ADDR_MSK	(0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
67 #define HGC_IOST_ECC_MB_ADDR_OFF	16
68 #define HGC_IOST_ECC_MB_ADDR_MSK	(0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
69 #define HGC_DQE_ECC_ADDR		0x144
70 #define HGC_DQE_ECC_1B_ADDR_OFF	0
71 #define HGC_DQE_ECC_1B_ADDR_MSK	(0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
72 #define HGC_DQE_ECC_MB_ADDR_OFF	16
73 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
74 #define CHNL_INT_STATUS			0x148
75 #define TAB_DFX				0x14c
76 #define HGC_ITCT_ECC_ADDR		0x150
77 #define HGC_ITCT_ECC_1B_ADDR_OFF		0
78 #define HGC_ITCT_ECC_1B_ADDR_MSK		(0x3ff << \
79 						 HGC_ITCT_ECC_1B_ADDR_OFF)
80 #define HGC_ITCT_ECC_MB_ADDR_OFF		16
81 #define HGC_ITCT_ECC_MB_ADDR_MSK		(0x3ff << \
82 						 HGC_ITCT_ECC_MB_ADDR_OFF)
83 #define HGC_AXI_FIFO_ERR_INFO  0x154
84 #define AXI_ERR_INFO_OFF               0
85 #define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
86 #define FIFO_ERR_INFO_OFF              8
87 #define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
88 #define TAB_RD_TYPE			0x15c
89 #define INT_COAL_EN			0x19c
90 #define OQ_INT_COAL_TIME		0x1a0
91 #define OQ_INT_COAL_CNT			0x1a4
92 #define ENT_INT_COAL_TIME		0x1a8
93 #define ENT_INT_COAL_CNT		0x1ac
94 #define OQ_INT_SRC			0x1b0
95 #define OQ_INT_SRC_MSK			0x1b4
96 #define ENT_INT_SRC1			0x1b8
97 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0
98 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
99 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8
100 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
101 #define ENT_INT_SRC2			0x1bc
102 #define ENT_INT_SRC3			0x1c0
103 #define ENT_INT_SRC3_WP_DEPTH_OFF		8
104 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF	9
105 #define ENT_INT_SRC3_RP_DEPTH_OFF		10
106 #define ENT_INT_SRC3_AXI_OFF			11
107 #define ENT_INT_SRC3_FIFO_OFF			12
108 #define ENT_INT_SRC3_LM_OFF				14
109 #define ENT_INT_SRC3_ITC_INT_OFF	15
110 #define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)
111 #define ENT_INT_SRC3_ABT_OFF		16
112 #define ENT_INT_SRC3_DQE_POISON_OFF	18
113 #define ENT_INT_SRC3_IOST_POISON_OFF	19
114 #define ENT_INT_SRC3_ITCT_POISON_OFF	20
115 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF	21
116 #define ENT_INT_SRC_MSK1		0x1c4
117 #define ENT_INT_SRC_MSK2		0x1c8
118 #define ENT_INT_SRC_MSK3		0x1cc
119 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31
120 #define CHNL_PHYUPDOWN_INT_MSK		0x1d0
121 #define CHNL_ENT_INT_MSK			0x1d4
122 #define HGC_COM_INT_MSK				0x1d8
123 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
124 #define SAS_ECC_INTR			0x1e8
125 #define SAS_ECC_INTR_DQE_ECC_1B_OFF		0
126 #define SAS_ECC_INTR_DQE_ECC_MB_OFF		1
127 #define SAS_ECC_INTR_IOST_ECC_1B_OFF	2
128 #define SAS_ECC_INTR_IOST_ECC_MB_OFF	3
129 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF	4
130 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF	5
131 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF	6
132 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF	7
133 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF	8
134 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF	9
135 #define SAS_ECC_INTR_CQE_ECC_1B_OFF		10
136 #define SAS_ECC_INTR_CQE_ECC_MB_OFF		11
137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF	12
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF	13
139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF	14
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF	15
141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF	16
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF	17
143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF	18
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF	19
145 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF		20
146 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF		21
147 #define SAS_ECC_INTR_MSK		0x1ec
148 #define HGC_ERR_STAT_EN			0x238
149 #define CQE_SEND_CNT			0x248
150 #define DLVRY_Q_0_BASE_ADDR_LO		0x260
151 #define DLVRY_Q_0_BASE_ADDR_HI		0x264
152 #define DLVRY_Q_0_DEPTH			0x268
153 #define DLVRY_Q_0_WR_PTR		0x26c
154 #define DLVRY_Q_0_RD_PTR		0x270
155 #define HYPER_STREAM_ID_EN_CFG		0xc80
156 #define OQ0_INT_SRC_MSK			0xc90
157 #define COMPL_Q_0_BASE_ADDR_LO		0x4e0
158 #define COMPL_Q_0_BASE_ADDR_HI		0x4e4
159 #define COMPL_Q_0_DEPTH			0x4e8
160 #define COMPL_Q_0_WR_PTR		0x4ec
161 #define COMPL_Q_0_RD_PTR		0x4f0
162 #define HGC_RXM_DFX_STATUS14		0xae8
163 #define HGC_RXM_DFX_STATUS14_MEM0_OFF	0
164 #define HGC_RXM_DFX_STATUS14_MEM0_MSK	(0x1ff << \
165 					 HGC_RXM_DFX_STATUS14_MEM0_OFF)
166 #define HGC_RXM_DFX_STATUS14_MEM1_OFF	9
167 #define HGC_RXM_DFX_STATUS14_MEM1_MSK	(0x1ff << \
168 					 HGC_RXM_DFX_STATUS14_MEM1_OFF)
169 #define HGC_RXM_DFX_STATUS14_MEM2_OFF	18
170 #define HGC_RXM_DFX_STATUS14_MEM2_MSK	(0x1ff << \
171 					 HGC_RXM_DFX_STATUS14_MEM2_OFF)
172 #define HGC_RXM_DFX_STATUS15		0xaec
173 #define HGC_RXM_DFX_STATUS15_MEM3_OFF	0
174 #define HGC_RXM_DFX_STATUS15_MEM3_MSK	(0x1ff << \
175 					 HGC_RXM_DFX_STATUS15_MEM3_OFF)
176 #define AWQOS_AWCACHE_CFG	0xc84
177 #define ARQOS_ARCACHE_CFG	0xc88
178 #define HILINK_ERR_DFX		0xe04
179 #define SAS_GPIO_CFG_0		0x1000
180 #define SAS_GPIO_CFG_1		0x1004
181 #define SAS_GPIO_TX_0_1	0x1040
182 #define SAS_CFG_DRIVE_VLD	0x1070
183 
184 /* phy registers requiring init */
185 #define PORT_BASE			(0x2000)
186 #define PHY_CFG				(PORT_BASE + 0x0)
187 #define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)
188 #define PHY_CFG_ENA_OFF			0
189 #define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
190 #define PHY_CFG_DC_OPT_OFF		2
191 #define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
192 #define PHY_CFG_PHY_RST_OFF		3
193 #define PHY_CFG_PHY_RST_MSK		(0x1 << PHY_CFG_PHY_RST_OFF)
194 #define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)
195 #define CFG_PROG_PHY_LINK_RATE_OFF	0
196 #define CFG_PROG_PHY_LINK_RATE_MSK	(0xff << CFG_PROG_PHY_LINK_RATE_OFF)
197 #define CFG_PROG_OOB_PHY_LINK_RATE_OFF	8
198 #define CFG_PROG_OOB_PHY_LINK_RATE_MSK	(0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
199 #define PHY_CTRL			(PORT_BASE + 0x14)
200 #define PHY_CTRL_RESET_OFF		0
201 #define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
202 #define CMD_HDR_PIR_OFF			8
203 #define CMD_HDR_PIR_MSK			(0x1 << CMD_HDR_PIR_OFF)
204 #define SERDES_CFG			(PORT_BASE + 0x1c)
205 #define CFG_ALOS_CHK_DISABLE_OFF	9
206 #define CFG_ALOS_CHK_DISABLE_MSK	(0x1 << CFG_ALOS_CHK_DISABLE_OFF)
207 #define SAS_PHY_BIST_CTRL		(PORT_BASE + 0x2c)
208 #define CFG_BIST_MODE_SEL_OFF		0
209 #define CFG_BIST_MODE_SEL_MSK		(0xf << CFG_BIST_MODE_SEL_OFF)
210 #define CFG_LOOP_TEST_MODE_OFF		14
211 #define CFG_LOOP_TEST_MODE_MSK		(0x3 << CFG_LOOP_TEST_MODE_OFF)
212 #define CFG_RX_BIST_EN_OFF		16
213 #define CFG_RX_BIST_EN_MSK		(0x1 << CFG_RX_BIST_EN_OFF)
214 #define CFG_TX_BIST_EN_OFF		17
215 #define CFG_TX_BIST_EN_MSK		(0x1 << CFG_TX_BIST_EN_OFF)
216 #define CFG_BIST_TEST_OFF		18
217 #define CFG_BIST_TEST_MSK		(0x1 << CFG_BIST_TEST_OFF)
218 #define SAS_PHY_BIST_CODE		(PORT_BASE + 0x30)
219 #define SAS_PHY_BIST_CODE1		(PORT_BASE + 0x34)
220 #define SAS_BIST_ERR_CNT		(PORT_BASE + 0x38)
221 #define SL_CFG				(PORT_BASE + 0x84)
222 #define AIP_LIMIT			(PORT_BASE + 0x90)
223 #define SL_CONTROL			(PORT_BASE + 0x94)
224 #define SL_CONTROL_NOTIFY_EN_OFF	0
225 #define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
226 #define SL_CTA_OFF		17
227 #define SL_CTA_MSK		(0x1 << SL_CTA_OFF)
228 #define RX_PRIMS_STATUS			(PORT_BASE + 0x98)
229 #define RX_BCAST_CHG_OFF		1
230 #define RX_BCAST_CHG_MSK		(0x1 << RX_BCAST_CHG_OFF)
231 #define TX_ID_DWORD0			(PORT_BASE + 0x9c)
232 #define TX_ID_DWORD1			(PORT_BASE + 0xa0)
233 #define TX_ID_DWORD2			(PORT_BASE + 0xa4)
234 #define TX_ID_DWORD3			(PORT_BASE + 0xa8)
235 #define TX_ID_DWORD4			(PORT_BASE + 0xaC)
236 #define TX_ID_DWORD5			(PORT_BASE + 0xb0)
237 #define TX_ID_DWORD6			(PORT_BASE + 0xb4)
238 #define TXID_AUTO				(PORT_BASE + 0xb8)
239 #define CT3_OFF		1
240 #define CT3_MSK		(0x1 << CT3_OFF)
241 #define TX_HARDRST_OFF          2
242 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
243 #define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
244 #define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
245 #define STP_LINK_TIMER			(PORT_BASE + 0x120)
246 #define STP_LINK_TIMEOUT_STATE		(PORT_BASE + 0x124)
247 #define CON_CFG_DRIVER			(PORT_BASE + 0x130)
248 #define SAS_SSP_CON_TIMER_CFG		(PORT_BASE + 0x134)
249 #define SAS_SMP_CON_TIMER_CFG		(PORT_BASE + 0x138)
250 #define SAS_STP_CON_TIMER_CFG		(PORT_BASE + 0x13c)
251 #define CHL_INT0			(PORT_BASE + 0x1b4)
252 #define CHL_INT0_HOTPLUG_TOUT_OFF	0
253 #define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
254 #define CHL_INT0_SL_RX_BCST_ACK_OFF	1
255 #define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
256 #define CHL_INT0_SL_PHY_ENABLE_OFF	2
257 #define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
258 #define CHL_INT0_NOT_RDY_OFF		4
259 #define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)
260 #define CHL_INT0_PHY_RDY_OFF		5
261 #define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)
262 #define CHL_INT1			(PORT_BASE + 0x1b8)
263 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF	15
264 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF	16
265 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF	17
266 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF	18
267 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF	19
268 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF	20
269 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF	21
270 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF	22
271 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF	23
272 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF	24
273 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF	26
274 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF	27
275 #define CHL_INT2			(PORT_BASE + 0x1bc)
276 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF	0
277 #define CHL_INT2_RX_DISP_ERR_OFF	28
278 #define CHL_INT2_RX_CODE_ERR_OFF	29
279 #define CHL_INT2_RX_INVLD_DW_OFF	30
280 #define CHL_INT2_STP_LINK_TIMEOUT_OFF	31
281 #define CHL_INT0_MSK			(PORT_BASE + 0x1c0)
282 #define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
283 #define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
284 #define SAS_EC_INT_COAL_TIME		(PORT_BASE + 0x1cc)
285 #define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
286 #define SAS_RX_TRAIN_TIMER		(PORT_BASE + 0x2a4)
287 #define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
288 #define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
289 #define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
290 #define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)
291 #define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)
292 #define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)
293 #define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
294 #define DMA_TX_STATUS_BUSY_OFF		0
295 #define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
296 #define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
297 #define DMA_RX_STATUS_BUSY_OFF		0
298 #define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)
299 
300 #define COARSETUNE_TIME			(PORT_BASE + 0x304)
301 #define TXDEEMPH_G1			(PORT_BASE + 0x350)
302 #define ERR_CNT_DWS_LOST		(PORT_BASE + 0x380)
303 #define ERR_CNT_RESET_PROB		(PORT_BASE + 0x384)
304 #define ERR_CNT_INVLD_DW		(PORT_BASE + 0x390)
305 #define ERR_CNT_CODE_ERR		(PORT_BASE + 0x394)
306 #define ERR_CNT_DISP_ERR		(PORT_BASE + 0x398)
307 #define DFX_FIFO_CTRL			(PORT_BASE + 0x3a0)
308 #define DFX_FIFO_CTRL_TRIGGER_MODE_OFF	0
309 #define DFX_FIFO_CTRL_TRIGGER_MODE_MSK	(0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
310 #define DFX_FIFO_CTRL_DUMP_MODE_OFF	3
311 #define DFX_FIFO_CTRL_DUMP_MODE_MSK	(0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
312 #define DFX_FIFO_CTRL_SIGNAL_SEL_OFF	6
313 #define DFX_FIFO_CTRL_SIGNAL_SEL_MSK	(0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
314 #define DFX_FIFO_CTRL_DUMP_DISABLE_OFF	10
315 #define DFX_FIFO_CTRL_DUMP_DISABLE_MSK	(0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
316 #define DFX_FIFO_TRIGGER		(PORT_BASE + 0x3a4)
317 #define DFX_FIFO_TRIGGER_MSK		(PORT_BASE + 0x3a8)
318 #define DFX_FIFO_DUMP_MSK		(PORT_BASE + 0x3aC)
319 #define DFX_FIFO_RD_DATA		(PORT_BASE + 0x3b0)
320 
321 #define DEFAULT_ITCT_HW		2048 /* reset value, not reprogrammed */
322 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
323 #error Max ITCT exceeded
324 #endif
325 
326 #define AXI_MASTER_CFG_BASE		(0x5000)
327 #define AM_CTRL_GLOBAL			(0x0)
328 #define AM_CTRL_SHUTDOWN_REQ_OFF	0
329 #define AM_CTRL_SHUTDOWN_REQ_MSK	(0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
330 #define AM_CURR_TRANS_RETURN	(0x150)
331 
332 #define AM_CFG_MAX_TRANS		(0x5010)
333 #define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)
334 #define AXI_CFG					(0x5100)
335 #define AM_ROB_ECC_ERR_ADDR		(0x510c)
336 #define AM_ROB_ECC_ERR_ADDR_OFF	0
337 #define AM_ROB_ECC_ERR_ADDR_MSK	0xffffffff
338 
339 /* RAS registers need init */
340 #define RAS_BASE		(0x6000)
341 #define SAS_RAS_INTR0			(RAS_BASE)
342 #define SAS_RAS_INTR1			(RAS_BASE + 0x04)
343 #define SAS_RAS_INTR0_MASK		(RAS_BASE + 0x08)
344 #define SAS_RAS_INTR1_MASK		(RAS_BASE + 0x0c)
345 #define CFG_SAS_RAS_INTR_MASK		(RAS_BASE + 0x1c)
346 #define SAS_RAS_INTR2			(RAS_BASE + 0x20)
347 #define SAS_RAS_INTR2_MASK		(RAS_BASE + 0x24)
348 
349 /* HW dma structures */
350 /* Delivery queue header */
351 /* dw0 */
352 #define CMD_HDR_ABORT_FLAG_OFF		0
353 #define CMD_HDR_ABORT_FLAG_MSK		(0x3 << CMD_HDR_ABORT_FLAG_OFF)
354 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF	2
355 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK	(0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
356 #define CMD_HDR_RESP_REPORT_OFF		5
357 #define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)
358 #define CMD_HDR_TLR_CTRL_OFF		6
359 #define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)
360 #define CMD_HDR_PORT_OFF		18
361 #define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)
362 #define CMD_HDR_PRIORITY_OFF		27
363 #define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)
364 #define CMD_HDR_CMD_OFF			29
365 #define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)
366 /* dw1 */
367 #define CMD_HDR_UNCON_CMD_OFF	3
368 #define CMD_HDR_DIR_OFF			5
369 #define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)
370 #define CMD_HDR_RESET_OFF		7
371 #define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)
372 #define CMD_HDR_VDTL_OFF		10
373 #define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)
374 #define CMD_HDR_FRAME_TYPE_OFF		11
375 #define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)
376 #define CMD_HDR_DEV_ID_OFF		16
377 #define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)
378 /* dw2 */
379 #define CMD_HDR_CFL_OFF			0
380 #define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)
381 #define CMD_HDR_NCQ_TAG_OFF		10
382 #define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)
383 #define CMD_HDR_MRFL_OFF		15
384 #define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)
385 #define CMD_HDR_SG_MOD_OFF		24
386 #define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)
387 /* dw3 */
388 #define CMD_HDR_IPTT_OFF		0
389 #define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)
390 /* dw6 */
391 #define CMD_HDR_DIF_SGL_LEN_OFF		0
392 #define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
393 #define CMD_HDR_DATA_SGL_LEN_OFF	16
394 #define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
395 /* dw7 */
396 #define CMD_HDR_ADDR_MODE_SEL_OFF		15
397 #define CMD_HDR_ADDR_MODE_SEL_MSK		(1 << CMD_HDR_ADDR_MODE_SEL_OFF)
398 #define CMD_HDR_ABORT_IPTT_OFF		16
399 #define CMD_HDR_ABORT_IPTT_MSK		(0xffff << CMD_HDR_ABORT_IPTT_OFF)
400 
401 /* Completion header */
402 /* dw0 */
403 #define CMPLT_HDR_CMPLT_OFF		0
404 #define CMPLT_HDR_CMPLT_MSK		(0x3 << CMPLT_HDR_CMPLT_OFF)
405 #define CMPLT_HDR_ERROR_PHASE_OFF   2
406 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
407 #define CMPLT_HDR_RSPNS_XFRD_OFF	10
408 #define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
409 #define CMPLT_HDR_RSPNS_GOOD_OFF	11
410 #define CMPLT_HDR_RSPNS_GOOD_MSK	(0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
411 #define CMPLT_HDR_ERX_OFF		12
412 #define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)
413 #define CMPLT_HDR_ABORT_STAT_OFF	13
414 #define CMPLT_HDR_ABORT_STAT_MSK	(0x7 << CMPLT_HDR_ABORT_STAT_OFF)
415 /* abort_stat */
416 #define STAT_IO_NOT_VALID		0x1
417 #define STAT_IO_NO_DEVICE		0x2
418 #define STAT_IO_COMPLETE		0x3
419 #define STAT_IO_ABORTED			0x4
420 /* dw1 */
421 #define CMPLT_HDR_IPTT_OFF		0
422 #define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
423 #define CMPLT_HDR_DEV_ID_OFF		16
424 #define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)
425 /* dw3 */
426 #define CMPLT_HDR_IO_IN_TARGET_OFF	17
427 #define CMPLT_HDR_IO_IN_TARGET_MSK	(0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
428 
429 /* ITCT header */
430 /* qw0 */
431 #define ITCT_HDR_DEV_TYPE_OFF		0
432 #define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
433 #define ITCT_HDR_VALID_OFF		2
434 #define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
435 #define ITCT_HDR_MCR_OFF		5
436 #define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)
437 #define ITCT_HDR_VLN_OFF		9
438 #define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)
439 #define ITCT_HDR_SMP_TIMEOUT_OFF	16
440 #define ITCT_HDR_AWT_CONTINUE_OFF	25
441 #define ITCT_HDR_PORT_ID_OFF		28
442 #define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)
443 /* qw2 */
444 #define ITCT_HDR_INLT_OFF		0
445 #define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)
446 #define ITCT_HDR_RTOLT_OFF		48
447 #define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)
448 
449 struct hisi_sas_protect_iu_v3_hw {
450 	u32 dw0;
451 	u32 lbrtcv;
452 	u32 lbrtgv;
453 	u32 dw3;
454 	u32 dw4;
455 	u32 dw5;
456 	u32 rsv;
457 };
458 
459 struct hisi_sas_complete_v3_hdr {
460 	__le32 dw0;
461 	__le32 dw1;
462 	__le32 act;
463 	__le32 dw3;
464 };
465 
466 struct hisi_sas_err_record_v3 {
467 	/* dw0 */
468 	__le32 trans_tx_fail_type;
469 
470 	/* dw1 */
471 	__le32 trans_rx_fail_type;
472 
473 	/* dw2 */
474 	__le16 dma_tx_err_type;
475 	__le16 sipc_rx_err_type;
476 
477 	/* dw3 */
478 	__le32 dma_rx_err_type;
479 };
480 
481 #define RX_DATA_LEN_UNDERFLOW_OFF	6
482 #define RX_DATA_LEN_UNDERFLOW_MSK	(1 << RX_DATA_LEN_UNDERFLOW_OFF)
483 
484 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
485 #define HISI_SAS_MSI_COUNT_V3_HW 32
486 
487 #define DIR_NO_DATA 0
488 #define DIR_TO_INI 1
489 #define DIR_TO_DEVICE 2
490 #define DIR_RESERVED 3
491 
492 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
493 	((fis.command == ATA_CMD_READ_LOG_EXT) || \
494 	(fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
495 	((fis.command == ATA_CMD_DEV_RESET) && \
496 	((fis.control & ATA_SRST) != 0)))
497 
498 #define T10_INSRT_EN_OFF    0
499 #define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
500 #define T10_RMV_EN_OFF	    1
501 #define T10_RMV_EN_MSK	    (1 << T10_RMV_EN_OFF)
502 #define T10_RPLC_EN_OFF	    2
503 #define T10_RPLC_EN_MSK	    (1 << T10_RPLC_EN_OFF)
504 #define T10_CHK_EN_OFF	    3
505 #define T10_CHK_EN_MSK	    (1 << T10_CHK_EN_OFF)
506 #define INCR_LBRT_OFF	    5
507 #define INCR_LBRT_MSK	    (1 << INCR_LBRT_OFF)
508 #define USR_DATA_BLOCK_SZ_OFF	20
509 #define USR_DATA_BLOCK_SZ_MSK	(0x3 << USR_DATA_BLOCK_SZ_OFF)
510 #define T10_CHK_MSK_OFF	    16
511 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
512 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
513 
514 #define BASE_VECTORS_V3_HW  16
515 #define MIN_AFFINE_VECTORS_V3_HW  (BASE_VECTORS_V3_HW + 1)
516 
517 #define CHNL_INT_STS_MSK	0xeeeeeeee
518 #define CHNL_INT_STS_PHY_MSK	0xe
519 #define CHNL_INT_STS_INT0_MSK BIT(1)
520 #define CHNL_INT_STS_INT1_MSK BIT(2)
521 #define CHNL_INT_STS_INT2_MSK BIT(3)
522 #define CHNL_WIDTH 4
523 
524 #define BAR_NO_V3_HW	5
525 
526 enum {
527 	DSM_FUNC_ERR_HANDLE_MSI = 0,
528 };
529 
530 static bool hisi_sas_intr_conv;
531 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
532 
533 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
534 static int prot_mask;
535 module_param(prot_mask, int, 0444);
536 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
537 
538 static void debugfs_work_handler_v3_hw(struct work_struct *work);
539 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
540 
541 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
542 {
543 	void __iomem *regs = hisi_hba->regs + off;
544 
545 	return readl(regs);
546 }
547 
548 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
549 {
550 	void __iomem *regs = hisi_hba->regs + off;
551 
552 	writel(val, regs);
553 }
554 
555 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
556 				 u32 off, u32 val)
557 {
558 	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
559 
560 	writel(val, regs);
561 }
562 
563 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
564 				      int phy_no, u32 off)
565 {
566 	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
567 
568 	return readl(regs);
569 }
570 
571 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,		\
572 				     timeout_us)			\
573 ({									\
574 	void __iomem *regs = hisi_hba->regs + off;			\
575 	readl_poll_timeout(regs, val, cond, delay_us, timeout_us);	\
576 })
577 
578 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,	\
579 					    timeout_us)			\
580 ({									\
581 	void __iomem *regs = hisi_hba->regs + off;			\
582 	readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
583 })
584 
585 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
586 {
587 	int i, j;
588 
589 	/* Global registers init */
590 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
591 			 (u32)((1ULL << hisi_hba->queue_count) - 1));
592 	hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
593 	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
594 	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
595 	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
596 	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
597 	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
598 	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
599 	hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
600 			 hisi_sas_intr_conv);
601 	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
602 	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
603 	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
604 	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
605 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
606 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
607 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
608 	hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
609 	hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
610 	hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
611 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
612 	hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
613 	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
614 	for (i = 0; i < hisi_hba->queue_count; i++)
615 		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
616 
617 	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
618 
619 	for (i = 0; i < hisi_hba->n_phy; i++) {
620 		enum sas_linkrate max;
621 		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
622 		struct asd_sas_phy *sas_phy = &phy->sas_phy;
623 		u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
624 							   PROG_PHY_LINK_RATE);
625 
626 		prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
627 		if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
628 				SAS_LINK_RATE_1_5_GBPS))
629 			max = SAS_LINK_RATE_12_0_GBPS;
630 		else
631 			max = sas_phy->phy->maximum_linkrate;
632 		prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
633 		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
634 			prog_phy_link_rate);
635 		hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
636 		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
637 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
638 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
639 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
640 		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
641 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
642 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
643 		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
644 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
645 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
646 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
647 		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
648 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
649 		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
650 		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
651 		hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
652 		hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
653 				     0x30f4240);
654 		/* used for 12G negotiate */
655 		hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
656 		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
657 
658 		/* get default FFE configuration for BIST */
659 		for (j = 0; j < FFE_CFG_MAX; j++) {
660 			u32 val = hisi_sas_phy_read32(hisi_hba, i,
661 						      TXDEEMPH_G1 + (j * 0x4));
662 			hisi_hba->debugfs_bist_ffe[i][j] = val;
663 		}
664 	}
665 
666 	for (i = 0; i < hisi_hba->queue_count; i++) {
667 		/* Delivery queue */
668 		hisi_sas_write32(hisi_hba,
669 				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
670 				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
671 
672 		hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
673 				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
674 
675 		hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
676 				 HISI_SAS_QUEUE_SLOTS);
677 
678 		/* Completion queue */
679 		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
680 				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
681 
682 		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
683 				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
684 
685 		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
686 				 HISI_SAS_QUEUE_SLOTS);
687 	}
688 
689 	/* itct */
690 	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
691 			 lower_32_bits(hisi_hba->itct_dma));
692 
693 	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
694 			 upper_32_bits(hisi_hba->itct_dma));
695 
696 	/* iost */
697 	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
698 			 lower_32_bits(hisi_hba->iost_dma));
699 
700 	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
701 			 upper_32_bits(hisi_hba->iost_dma));
702 
703 	/* breakpoint */
704 	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
705 			 lower_32_bits(hisi_hba->breakpoint_dma));
706 
707 	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
708 			 upper_32_bits(hisi_hba->breakpoint_dma));
709 
710 	/* SATA broken msg */
711 	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
712 			 lower_32_bits(hisi_hba->sata_breakpoint_dma));
713 
714 	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
715 			 upper_32_bits(hisi_hba->sata_breakpoint_dma));
716 
717 	/* SATA initial fis */
718 	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
719 			 lower_32_bits(hisi_hba->initial_fis_dma));
720 
721 	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
722 			 upper_32_bits(hisi_hba->initial_fis_dma));
723 
724 	/* RAS registers init */
725 	hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
726 	hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
727 	hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
728 	hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
729 
730 	/* LED registers init */
731 	hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
732 	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
733 	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
734 	/* Configure blink generator rate A to 1Hz and B to 4Hz */
735 	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
736 	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
737 }
738 
739 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
740 {
741 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
742 
743 	cfg &= ~PHY_CFG_DC_OPT_MSK;
744 	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
745 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
746 }
747 
748 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
749 {
750 	struct sas_identify_frame identify_frame;
751 	u32 *identify_buffer;
752 
753 	memset(&identify_frame, 0, sizeof(identify_frame));
754 	identify_frame.dev_type = SAS_END_DEVICE;
755 	identify_frame.frame_type = 0;
756 	identify_frame._un1 = 1;
757 	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
758 	identify_frame.target_bits = SAS_PROTOCOL_NONE;
759 	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
760 	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr,	SAS_ADDR_SIZE);
761 	identify_frame.phy_id = phy_no;
762 	identify_buffer = (u32 *)(&identify_frame);
763 
764 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
765 			__swab32(identify_buffer[0]));
766 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
767 			__swab32(identify_buffer[1]));
768 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
769 			__swab32(identify_buffer[2]));
770 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
771 			__swab32(identify_buffer[3]));
772 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
773 			__swab32(identify_buffer[4]));
774 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
775 			__swab32(identify_buffer[5]));
776 }
777 
778 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
779 			     struct hisi_sas_device *sas_dev)
780 {
781 	struct domain_device *device = sas_dev->sas_device;
782 	struct device *dev = hisi_hba->dev;
783 	u64 qw0, device_id = sas_dev->device_id;
784 	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
785 	struct domain_device *parent_dev = device->parent;
786 	struct asd_sas_port *sas_port = device->port;
787 	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
788 	u64 sas_addr;
789 
790 	memset(itct, 0, sizeof(*itct));
791 
792 	/* qw0 */
793 	qw0 = 0;
794 	switch (sas_dev->dev_type) {
795 	case SAS_END_DEVICE:
796 	case SAS_EDGE_EXPANDER_DEVICE:
797 	case SAS_FANOUT_EXPANDER_DEVICE:
798 		qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
799 		break;
800 	case SAS_SATA_DEV:
801 	case SAS_SATA_PENDING:
802 		if (parent_dev && dev_is_expander(parent_dev->dev_type))
803 			qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
804 		else
805 			qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
806 		break;
807 	default:
808 		dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
809 			 sas_dev->dev_type);
810 	}
811 
812 	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
813 		(device->linkrate << ITCT_HDR_MCR_OFF) |
814 		(1 << ITCT_HDR_VLN_OFF) |
815 		(0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
816 		(1 << ITCT_HDR_AWT_CONTINUE_OFF) |
817 		(port->id << ITCT_HDR_PORT_ID_OFF));
818 	itct->qw0 = cpu_to_le64(qw0);
819 
820 	/* qw1 */
821 	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
822 	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
823 
824 	/* qw2 */
825 	if (!dev_is_sata(device))
826 		itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
827 					(0x1ULL << ITCT_HDR_RTOLT_OFF));
828 }
829 
830 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
831 			    struct hisi_sas_device *sas_dev)
832 {
833 	DECLARE_COMPLETION_ONSTACK(completion);
834 	u64 dev_id = sas_dev->device_id;
835 	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
836 	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
837 	struct device *dev = hisi_hba->dev;
838 
839 	sas_dev->completion = &completion;
840 
841 	/* clear the itct interrupt state */
842 	if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
843 		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
844 				 ENT_INT_SRC3_ITC_INT_MSK);
845 
846 	/* clear the itct table */
847 	reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
848 	hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
849 
850 	if (!wait_for_completion_timeout(sas_dev->completion,
851 					 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
852 		dev_warn(dev, "failed to clear ITCT\n");
853 		return -ETIMEDOUT;
854 	}
855 
856 	memset(itct, 0, sizeof(struct hisi_sas_itct));
857 	return 0;
858 }
859 
860 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
861 				struct domain_device *device)
862 {
863 	struct hisi_sas_slot *slot, *slot2;
864 	struct hisi_sas_device *sas_dev = device->lldd_dev;
865 	u32 cfg_abt_set_query_iptt;
866 
867 	cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
868 		CFG_ABT_SET_QUERY_IPTT);
869 	list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
870 		cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
871 		cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
872 			(slot->idx << CFG_SET_ABORTED_IPTT_OFF);
873 		hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
874 			cfg_abt_set_query_iptt);
875 	}
876 	cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
877 	hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
878 		cfg_abt_set_query_iptt);
879 	hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
880 					1 << CFG_ABT_SET_IPTT_DONE_OFF);
881 }
882 
883 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
884 {
885 	struct device *dev = hisi_hba->dev;
886 	int ret;
887 	u32 val;
888 
889 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
890 
891 	/* Disable all of the PHYs */
892 	hisi_sas_stop_phys(hisi_hba);
893 	udelay(50);
894 
895 	/* Ensure axi bus idle */
896 	ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
897 					   20000, 1000000);
898 	if (ret) {
899 		dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
900 		return -EIO;
901 	}
902 
903 	if (ACPI_HANDLE(dev)) {
904 		acpi_status s;
905 
906 		s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
907 		if (ACPI_FAILURE(s)) {
908 			dev_err(dev, "Reset failed\n");
909 			return -EIO;
910 		}
911 	} else {
912 		dev_err(dev, "no reset method!\n");
913 		return -EINVAL;
914 	}
915 
916 	return 0;
917 }
918 
919 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
920 {
921 	struct device *dev = hisi_hba->dev;
922 	struct acpi_device *acpi_dev;
923 	union acpi_object *obj;
924 	guid_t guid;
925 	int rc;
926 
927 	rc = reset_hw_v3_hw(hisi_hba);
928 	if (rc) {
929 		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
930 		return rc;
931 	}
932 
933 	msleep(100);
934 	init_reg_v3_hw(hisi_hba);
935 
936 	if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
937 		dev_err(dev, "Parse GUID failed\n");
938 		return -EINVAL;
939 	}
940 
941 	/*
942 	 * This DSM handles some hardware-related configurations:
943 	 * 1. Switch over to MSI error handling in kernel
944 	 * 2. BIOS *may* reset some register values through this method
945 	 */
946 	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
947 				DSM_FUNC_ERR_HANDLE_MSI, NULL);
948 	if (!obj)
949 		dev_warn(dev, "can not find DSM method, ignore\n");
950 	else
951 		ACPI_FREE(obj);
952 
953 	acpi_dev = ACPI_COMPANION(dev);
954 	if (!acpi_device_power_manageable(acpi_dev))
955 		dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
956 	return 0;
957 }
958 
959 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
960 {
961 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
962 
963 	cfg |= PHY_CFG_ENA_MSK;
964 	cfg &= ~PHY_CFG_PHY_RST_MSK;
965 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
966 }
967 
968 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
969 {
970 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
971 	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
972 	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
973 			       BIT(CHL_INT2_RX_CODE_ERR_OFF) |
974 			       BIT(CHL_INT2_RX_INVLD_DW_OFF);
975 	u32 state;
976 
977 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
978 
979 	cfg &= ~PHY_CFG_ENA_MSK;
980 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
981 
982 	mdelay(50);
983 
984 	state = hisi_sas_read32(hisi_hba, PHY_STATE);
985 	if (state & BIT(phy_no)) {
986 		cfg |= PHY_CFG_PHY_RST_MSK;
987 		hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
988 	}
989 
990 	udelay(1);
991 
992 	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
993 	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
994 	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
995 
996 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
997 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
998 }
999 
1000 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1001 {
1002 	config_id_frame_v3_hw(hisi_hba, phy_no);
1003 	config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
1004 	enable_phy_v3_hw(hisi_hba, phy_no);
1005 }
1006 
1007 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1008 {
1009 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1010 	u32 txid_auto;
1011 
1012 	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1013 	if (phy->identify.device_type == SAS_END_DEVICE) {
1014 		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1015 		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1016 					txid_auto | TX_HARDRST_MSK);
1017 	}
1018 	msleep(100);
1019 	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1020 }
1021 
1022 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1023 {
1024 	return SAS_LINK_RATE_12_0_GBPS;
1025 }
1026 
1027 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1028 {
1029 	int i;
1030 
1031 	for (i = 0; i < hisi_hba->n_phy; i++) {
1032 		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1033 		struct asd_sas_phy *sas_phy = &phy->sas_phy;
1034 
1035 		if (!sas_phy->phy->enabled)
1036 			continue;
1037 
1038 		hisi_sas_phy_enable(hisi_hba, i, 1);
1039 	}
1040 }
1041 
1042 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1043 {
1044 	u32 sl_control;
1045 
1046 	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1047 	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1048 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1049 	msleep(1);
1050 	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1051 	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1052 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1053 }
1054 
1055 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1056 {
1057 	int i, bitmap = 0;
1058 	u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1059 	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1060 
1061 	for (i = 0; i < hisi_hba->n_phy; i++)
1062 		if (phy_state & BIT(i))
1063 			if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1064 				bitmap |= BIT(i);
1065 
1066 	return bitmap;
1067 }
1068 
1069 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1070 {
1071 	struct hisi_hba *hisi_hba = dq->hisi_hba;
1072 	struct hisi_sas_slot *s, *s1, *s2 = NULL;
1073 	int dlvry_queue = dq->id;
1074 	int wp;
1075 
1076 	list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1077 		if (!s->ready)
1078 			break;
1079 		s2 = s;
1080 		list_del(&s->delivery);
1081 	}
1082 
1083 	if (!s2)
1084 		return;
1085 
1086 	/*
1087 	 * Ensure that memories for slots built on other CPUs is observed.
1088 	 */
1089 	smp_rmb();
1090 	wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1091 
1092 	hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1093 }
1094 
1095 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1096 			      struct hisi_sas_slot *slot,
1097 			      struct hisi_sas_cmd_hdr *hdr,
1098 			      struct scatterlist *scatter,
1099 			      int n_elem)
1100 {
1101 	struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1102 	struct scatterlist *sg;
1103 	int i;
1104 
1105 	for_each_sg(scatter, sg, n_elem, i) {
1106 		struct hisi_sas_sge *entry = &sge_page->sge[i];
1107 
1108 		entry->addr = cpu_to_le64(sg_dma_address(sg));
1109 		entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1110 		entry->data_len = cpu_to_le32(sg_dma_len(sg));
1111 		entry->data_off = 0;
1112 	}
1113 
1114 	hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1115 
1116 	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1117 }
1118 
1119 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1120 				   struct hisi_sas_slot *slot,
1121 				   struct hisi_sas_cmd_hdr *hdr,
1122 				   struct scatterlist *scatter,
1123 				   int n_elem)
1124 {
1125 	struct hisi_sas_sge_dif_page *sge_dif_page;
1126 	struct scatterlist *sg;
1127 	int i;
1128 
1129 	sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1130 
1131 	for_each_sg(scatter, sg, n_elem, i) {
1132 		struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1133 
1134 		entry->addr = cpu_to_le64(sg_dma_address(sg));
1135 		entry->page_ctrl_0 = 0;
1136 		entry->page_ctrl_1 = 0;
1137 		entry->data_len = cpu_to_le32(sg_dma_len(sg));
1138 		entry->data_off = 0;
1139 	}
1140 
1141 	hdr->dif_prd_table_addr =
1142 		cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1143 
1144 	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1145 }
1146 
1147 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1148 {
1149 	unsigned char prot_flags = scsi_cmnd->prot_flags;
1150 
1151 	if (prot_flags & SCSI_PROT_REF_CHECK)
1152 		return T10_CHK_APP_TAG_MSK;
1153 	return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1154 }
1155 
1156 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1157 			    struct hisi_sas_protect_iu_v3_hw *prot)
1158 {
1159 	unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1160 	unsigned int interval = scsi_prot_interval(scsi_cmnd);
1161 	u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmd_to_rq(scsi_cmnd));
1162 
1163 	switch (prot_op) {
1164 	case SCSI_PROT_READ_INSERT:
1165 		prot->dw0 |= T10_INSRT_EN_MSK;
1166 		prot->lbrtgv = lbrt_chk_val;
1167 		break;
1168 	case SCSI_PROT_READ_STRIP:
1169 		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1170 		prot->lbrtcv = lbrt_chk_val;
1171 		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1172 		break;
1173 	case SCSI_PROT_READ_PASS:
1174 		prot->dw0 |= T10_CHK_EN_MSK;
1175 		prot->lbrtcv = lbrt_chk_val;
1176 		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1177 		break;
1178 	case SCSI_PROT_WRITE_INSERT:
1179 		prot->dw0 |= T10_INSRT_EN_MSK;
1180 		prot->lbrtgv = lbrt_chk_val;
1181 		break;
1182 	case SCSI_PROT_WRITE_STRIP:
1183 		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1184 		prot->lbrtcv = lbrt_chk_val;
1185 		break;
1186 	case SCSI_PROT_WRITE_PASS:
1187 		prot->dw0 |= T10_CHK_EN_MSK;
1188 		prot->lbrtcv = lbrt_chk_val;
1189 		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1190 		break;
1191 	default:
1192 		WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1193 		break;
1194 	}
1195 
1196 	switch (interval) {
1197 	case 512:
1198 		break;
1199 	case 4096:
1200 		prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1201 		break;
1202 	case 520:
1203 		prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1204 		break;
1205 	default:
1206 		WARN(1, "protection interval (0x%x) invalid\n",
1207 		     interval);
1208 		break;
1209 	}
1210 
1211 	prot->dw0 |= INCR_LBRT_MSK;
1212 }
1213 
1214 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1215 			  struct hisi_sas_slot *slot)
1216 {
1217 	struct sas_task *task = slot->task;
1218 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1219 	struct domain_device *device = task->dev;
1220 	struct hisi_sas_device *sas_dev = device->lldd_dev;
1221 	struct hisi_sas_port *port = slot->port;
1222 	struct sas_ssp_task *ssp_task = &task->ssp_task;
1223 	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1224 	struct sas_tmf_task *tmf = slot->tmf;
1225 	int has_data = 0, priority = !!tmf;
1226 	unsigned char prot_op;
1227 	u8 *buf_cmd;
1228 	u32 dw1 = 0, dw2 = 0, len = 0;
1229 
1230 	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1231 			       (2 << CMD_HDR_TLR_CTRL_OFF) |
1232 			       (port->id << CMD_HDR_PORT_OFF) |
1233 			       (priority << CMD_HDR_PRIORITY_OFF) |
1234 			       (1 << CMD_HDR_CMD_OFF)); /* ssp */
1235 
1236 	dw1 = 1 << CMD_HDR_VDTL_OFF;
1237 	if (tmf) {
1238 		dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1239 		dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1240 	} else {
1241 		prot_op = scsi_get_prot_op(scsi_cmnd);
1242 		dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1243 		switch (scsi_cmnd->sc_data_direction) {
1244 		case DMA_TO_DEVICE:
1245 			has_data = 1;
1246 			dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1247 			break;
1248 		case DMA_FROM_DEVICE:
1249 			has_data = 1;
1250 			dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1251 			break;
1252 		default:
1253 			dw1 &= ~CMD_HDR_DIR_MSK;
1254 		}
1255 	}
1256 
1257 	/* map itct entry */
1258 	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1259 
1260 	dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1261 	      + 3) / 4) << CMD_HDR_CFL_OFF) |
1262 	      ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1263 	      (2 << CMD_HDR_SG_MOD_OFF);
1264 	hdr->dw2 = cpu_to_le32(dw2);
1265 	hdr->transfer_tags = cpu_to_le32(slot->idx);
1266 
1267 	if (has_data) {
1268 		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1269 				   slot->n_elem);
1270 
1271 		if (scsi_prot_sg_count(scsi_cmnd))
1272 			prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1273 					       scsi_prot_sglist(scsi_cmnd),
1274 					       slot->n_elem_dif);
1275 	}
1276 
1277 	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1278 	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1279 
1280 	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1281 		sizeof(struct ssp_frame_hdr);
1282 
1283 	memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1284 	if (!tmf) {
1285 		buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
1286 		memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1287 	} else {
1288 		buf_cmd[10] = tmf->tmf;
1289 		switch (tmf->tmf) {
1290 		case TMF_ABORT_TASK:
1291 		case TMF_QUERY_TASK:
1292 			buf_cmd[12] =
1293 				(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1294 			buf_cmd[13] =
1295 				tmf->tag_of_task_to_be_managed & 0xff;
1296 			break;
1297 		default:
1298 			break;
1299 		}
1300 	}
1301 
1302 	if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1303 		struct hisi_sas_protect_iu_v3_hw prot;
1304 		u8 *buf_cmd_prot;
1305 
1306 		hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1307 		dw1 |= CMD_HDR_PIR_MSK;
1308 		buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1309 			       sizeof(struct ssp_frame_hdr) +
1310 			       sizeof(struct ssp_command_iu);
1311 
1312 		memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1313 		fill_prot_v3_hw(scsi_cmnd, &prot);
1314 		memcpy(buf_cmd_prot, &prot,
1315 		       sizeof(struct hisi_sas_protect_iu_v3_hw));
1316 		/*
1317 		 * For READ, we need length of info read to memory, while for
1318 		 * WRITE we need length of data written to the disk.
1319 		 */
1320 		if (prot_op == SCSI_PROT_WRITE_INSERT ||
1321 		    prot_op == SCSI_PROT_READ_INSERT ||
1322 		    prot_op == SCSI_PROT_WRITE_PASS ||
1323 		    prot_op == SCSI_PROT_READ_PASS) {
1324 			unsigned int interval = scsi_prot_interval(scsi_cmnd);
1325 			unsigned int ilog2_interval = ilog2(interval);
1326 
1327 			len = (task->total_xfer_len >> ilog2_interval) * 8;
1328 		}
1329 	}
1330 
1331 	hdr->dw1 = cpu_to_le32(dw1);
1332 
1333 	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1334 }
1335 
1336 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1337 			  struct hisi_sas_slot *slot)
1338 {
1339 	struct sas_task *task = slot->task;
1340 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1341 	struct domain_device *device = task->dev;
1342 	struct hisi_sas_port *port = slot->port;
1343 	struct scatterlist *sg_req;
1344 	struct hisi_sas_device *sas_dev = device->lldd_dev;
1345 	dma_addr_t req_dma_addr;
1346 	unsigned int req_len;
1347 
1348 	/* req */
1349 	sg_req = &task->smp_task.smp_req;
1350 	req_len = sg_dma_len(sg_req);
1351 	req_dma_addr = sg_dma_address(sg_req);
1352 
1353 	/* create header */
1354 	/* dw0 */
1355 	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1356 			       (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1357 			       (2 << CMD_HDR_CMD_OFF)); /* smp */
1358 
1359 	/* map itct entry */
1360 	hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1361 			       (1 << CMD_HDR_FRAME_TYPE_OFF) |
1362 			       (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1363 
1364 	/* dw2 */
1365 	hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1366 			       (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1367 			       CMD_HDR_MRFL_OFF));
1368 
1369 	hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1370 
1371 	hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1372 	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1373 }
1374 
1375 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1376 			  struct hisi_sas_slot *slot)
1377 {
1378 	struct sas_task *task = slot->task;
1379 	struct domain_device *device = task->dev;
1380 	struct domain_device *parent_dev = device->parent;
1381 	struct hisi_sas_device *sas_dev = device->lldd_dev;
1382 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1383 	struct asd_sas_port *sas_port = device->port;
1384 	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1385 	u8 *buf_cmd;
1386 	int has_data = 0, hdr_tag = 0;
1387 	u32 dw1 = 0, dw2 = 0;
1388 
1389 	hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1390 	if (parent_dev && dev_is_expander(parent_dev->dev_type))
1391 		hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1392 	else
1393 		hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1394 
1395 	switch (task->data_dir) {
1396 	case DMA_TO_DEVICE:
1397 		has_data = 1;
1398 		dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1399 		break;
1400 	case DMA_FROM_DEVICE:
1401 		has_data = 1;
1402 		dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1403 		break;
1404 	default:
1405 		dw1 &= ~CMD_HDR_DIR_MSK;
1406 	}
1407 
1408 	if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1409 			(task->ata_task.fis.control & ATA_SRST))
1410 		dw1 |= 1 << CMD_HDR_RESET_OFF;
1411 
1412 	dw1 |= (hisi_sas_get_ata_protocol(
1413 		&task->ata_task.fis, task->data_dir))
1414 		<< CMD_HDR_FRAME_TYPE_OFF;
1415 	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1416 
1417 	if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1418 		dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1419 
1420 	hdr->dw1 = cpu_to_le32(dw1);
1421 
1422 	/* dw2 */
1423 	if (task->ata_task.use_ncq) {
1424 		struct ata_queued_cmd *qc = task->uldd_task;
1425 
1426 		hdr_tag = qc->tag;
1427 		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1428 		dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1429 	}
1430 
1431 	dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1432 			2 << CMD_HDR_SG_MOD_OFF;
1433 	hdr->dw2 = cpu_to_le32(dw2);
1434 
1435 	/* dw3 */
1436 	hdr->transfer_tags = cpu_to_le32(slot->idx);
1437 
1438 	if (has_data)
1439 		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1440 					slot->n_elem);
1441 
1442 	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1443 	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1444 	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1445 
1446 	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1447 
1448 	if (likely(!task->ata_task.device_control_reg_update))
1449 		task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1450 	/* fill in command FIS */
1451 	memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1452 }
1453 
1454 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1455 			     struct hisi_sas_slot *slot)
1456 {
1457 	struct sas_task *task = slot->task;
1458 	struct sas_internal_abort_task *abort = &task->abort_task;
1459 	struct domain_device *dev = task->dev;
1460 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1461 	struct hisi_sas_port *port = slot->port;
1462 	struct hisi_sas_device *sas_dev = dev->lldd_dev;
1463 	bool sata = dev_is_sata(dev);
1464 
1465 	/* dw0 */
1466 	hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
1467 			       (port->id << CMD_HDR_PORT_OFF) |
1468 				(sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1469 				(abort->type << CMD_HDR_ABORT_FLAG_OFF));
1470 
1471 	/* dw1 */
1472 	hdr->dw1 = cpu_to_le32(sas_dev->device_id
1473 			<< CMD_HDR_DEV_ID_OFF);
1474 
1475 	/* dw7 */
1476 	hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
1477 	hdr->transfer_tags = cpu_to_le32(slot->idx);
1478 }
1479 
1480 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1481 {
1482 	int i;
1483 	irqreturn_t res;
1484 	u32 context, port_id, link_rate;
1485 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1486 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1487 	struct device *dev = hisi_hba->dev;
1488 
1489 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1490 
1491 	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1492 	port_id = (port_id >> (4 * phy_no)) & 0xf;
1493 	link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1494 	link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1495 
1496 	if (port_id == 0xf) {
1497 		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1498 		res = IRQ_NONE;
1499 		goto end;
1500 	}
1501 	sas_phy->linkrate = link_rate;
1502 	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1503 
1504 	/* Check for SATA dev */
1505 	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1506 	if (context & (1 << phy_no)) {
1507 		struct hisi_sas_initial_fis *initial_fis;
1508 		struct dev_to_host_fis *fis;
1509 		u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1510 		struct Scsi_Host *shost = hisi_hba->shost;
1511 
1512 		dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1513 		initial_fis = &hisi_hba->initial_fis[phy_no];
1514 		fis = &initial_fis->fis;
1515 
1516 		/* check ERR bit of Status Register */
1517 		if (fis->status & ATA_ERR) {
1518 			dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1519 				 phy_no, fis->status);
1520 			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1521 			res = IRQ_NONE;
1522 			goto end;
1523 		}
1524 
1525 		sas_phy->oob_mode = SATA_OOB_MODE;
1526 		attached_sas_addr[0] = 0x50;
1527 		attached_sas_addr[6] = shost->host_no;
1528 		attached_sas_addr[7] = phy_no;
1529 		memcpy(sas_phy->attached_sas_addr,
1530 		       attached_sas_addr,
1531 		       SAS_ADDR_SIZE);
1532 		memcpy(sas_phy->frame_rcvd, fis,
1533 		       sizeof(struct dev_to_host_fis));
1534 		phy->phy_type |= PORT_TYPE_SATA;
1535 		phy->identify.device_type = SAS_SATA_DEV;
1536 		phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1537 		phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1538 	} else {
1539 		u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1540 		struct sas_identify_frame *id =
1541 			(struct sas_identify_frame *)frame_rcvd;
1542 
1543 		dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1544 		for (i = 0; i < 6; i++) {
1545 			u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1546 					       RX_IDAF_DWORD0 + (i * 4));
1547 			frame_rcvd[i] = __swab32(idaf);
1548 		}
1549 		sas_phy->oob_mode = SAS_OOB_MODE;
1550 		memcpy(sas_phy->attached_sas_addr,
1551 		       &id->sas_addr,
1552 		       SAS_ADDR_SIZE);
1553 		phy->phy_type |= PORT_TYPE_SAS;
1554 		phy->identify.device_type = id->dev_type;
1555 		phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1556 		if (phy->identify.device_type == SAS_END_DEVICE)
1557 			phy->identify.target_port_protocols =
1558 				SAS_PROTOCOL_SSP;
1559 		else if (phy->identify.device_type != SAS_PHY_UNUSED)
1560 			phy->identify.target_port_protocols =
1561 				SAS_PROTOCOL_SMP;
1562 	}
1563 
1564 	phy->port_id = port_id;
1565 
1566 	/* Call pm_runtime_put_sync() with pairs in hisi_sas_phyup_pm_work() */
1567 	pm_runtime_get_noresume(dev);
1568 	hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
1569 
1570 	res = IRQ_HANDLED;
1571 
1572 	spin_lock(&phy->lock);
1573 	/* Delete timer and set phy_attached atomically */
1574 	del_timer(&phy->timer);
1575 	phy->phy_attached = 1;
1576 	spin_unlock(&phy->lock);
1577 end:
1578 	if (phy->reset_completion)
1579 		complete(phy->reset_completion);
1580 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1581 			     CHL_INT0_SL_PHY_ENABLE_MSK);
1582 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1583 
1584 	return res;
1585 }
1586 
1587 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1588 {
1589 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1590 	u32 phy_state, sl_ctrl, txid_auto;
1591 	struct device *dev = hisi_hba->dev;
1592 
1593 	atomic_inc(&phy->down_cnt);
1594 
1595 	del_timer(&phy->timer);
1596 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1597 
1598 	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1599 	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1600 	hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
1601 			  GFP_ATOMIC);
1602 
1603 	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1604 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1605 						sl_ctrl&(~SL_CTA_MSK));
1606 
1607 	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1608 	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1609 						txid_auto | CT3_MSK);
1610 
1611 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1612 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1613 
1614 	return IRQ_HANDLED;
1615 }
1616 
1617 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1618 {
1619 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1620 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1621 	u32 bcast_status;
1622 
1623 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1624 	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1625 	if ((bcast_status & RX_BCAST_CHG_MSK) &&
1626 	    !test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
1627 		sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
1628 				      GFP_ATOMIC);
1629 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1630 			     CHL_INT0_SL_RX_BCST_ACK_MSK);
1631 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1632 
1633 	return IRQ_HANDLED;
1634 }
1635 
1636 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1637 {
1638 	struct hisi_hba *hisi_hba = p;
1639 	u32 irq_msk;
1640 	int phy_no = 0;
1641 	irqreturn_t res = IRQ_NONE;
1642 
1643 	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1644 				& 0x11111111;
1645 	while (irq_msk) {
1646 		if (irq_msk  & 1) {
1647 			u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1648 							    CHL_INT0);
1649 			u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1650 			int rdy = phy_state & (1 << phy_no);
1651 
1652 			if (rdy) {
1653 				if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1654 					/* phy up */
1655 					if (phy_up_v3_hw(phy_no, hisi_hba)
1656 							== IRQ_HANDLED)
1657 						res = IRQ_HANDLED;
1658 				if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1659 					/* phy bcast */
1660 					if (phy_bcast_v3_hw(phy_no, hisi_hba)
1661 							== IRQ_HANDLED)
1662 						res = IRQ_HANDLED;
1663 			} else {
1664 				if (irq_value & CHL_INT0_NOT_RDY_MSK)
1665 					/* phy down */
1666 					if (phy_down_v3_hw(phy_no, hisi_hba)
1667 							== IRQ_HANDLED)
1668 						res = IRQ_HANDLED;
1669 			}
1670 		}
1671 		irq_msk >>= 4;
1672 		phy_no++;
1673 	}
1674 
1675 	return res;
1676 }
1677 
1678 static const struct hisi_sas_hw_error port_axi_error[] = {
1679 	{
1680 		.irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1681 		.msg = "dmac_tx_ecc_bad_err",
1682 	},
1683 	{
1684 		.irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1685 		.msg = "dmac_rx_ecc_bad_err",
1686 	},
1687 	{
1688 		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1689 		.msg = "dma_tx_axi_wr_err",
1690 	},
1691 	{
1692 		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1693 		.msg = "dma_tx_axi_rd_err",
1694 	},
1695 	{
1696 		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1697 		.msg = "dma_rx_axi_wr_err",
1698 	},
1699 	{
1700 		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1701 		.msg = "dma_rx_axi_rd_err",
1702 	},
1703 	{
1704 		.irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1705 		.msg = "dma_tx_fifo_err",
1706 	},
1707 	{
1708 		.irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1709 		.msg = "dma_rx_fifo_err",
1710 	},
1711 	{
1712 		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1713 		.msg = "dma_tx_axi_ruser_err",
1714 	},
1715 	{
1716 		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1717 		.msg = "dma_rx_axi_ruser_err",
1718 	},
1719 };
1720 
1721 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1722 {
1723 	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1724 	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1725 	struct device *dev = hisi_hba->dev;
1726 	int i;
1727 
1728 	irq_value &= ~irq_msk;
1729 	if (!irq_value) {
1730 		dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1731 			 phy_no);
1732 		return;
1733 	}
1734 
1735 	for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1736 		const struct hisi_sas_hw_error *error = &port_axi_error[i];
1737 
1738 		if (!(irq_value & error->irq_msk))
1739 			continue;
1740 
1741 		dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1742 			error->msg, phy_no, irq_value);
1743 		queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1744 	}
1745 
1746 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1747 }
1748 
1749 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1750 {
1751 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1752 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1753 	struct sas_phy *sphy = sas_phy->phy;
1754 	unsigned long flags;
1755 	u32 reg_value;
1756 
1757 	spin_lock_irqsave(&phy->lock, flags);
1758 
1759 	/* loss dword sync */
1760 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1761 	sphy->loss_of_dword_sync_count += reg_value;
1762 
1763 	/* phy reset problem */
1764 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1765 	sphy->phy_reset_problem_count += reg_value;
1766 
1767 	/* invalid dword */
1768 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1769 	sphy->invalid_dword_count += reg_value;
1770 
1771 	/* disparity err */
1772 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1773 	sphy->running_disparity_error_count += reg_value;
1774 
1775 	/* code violation error */
1776 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1777 	phy->code_violation_err_count += reg_value;
1778 
1779 	spin_unlock_irqrestore(&phy->lock, flags);
1780 }
1781 
1782 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1783 {
1784 	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1785 	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1786 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1787 	struct pci_dev *pci_dev = hisi_hba->pci_dev;
1788 	struct device *dev = hisi_hba->dev;
1789 	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1790 			BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1791 			BIT(CHL_INT2_RX_INVLD_DW_OFF);
1792 
1793 	irq_value &= ~irq_msk;
1794 	if (!irq_value) {
1795 		dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1796 			 phy_no);
1797 		return;
1798 	}
1799 
1800 	if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1801 		dev_warn(dev, "phy%d identify timeout\n", phy_no);
1802 		hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1803 	}
1804 
1805 	if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1806 		u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1807 				STP_LINK_TIMEOUT_STATE);
1808 
1809 		dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1810 			 phy_no, reg_value);
1811 		if (reg_value & BIT(4))
1812 			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1813 	}
1814 
1815 	if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1816 		struct asd_sas_phy *sas_phy = &phy->sas_phy;
1817 		struct sas_phy *sphy = sas_phy->phy;
1818 
1819 		phy_get_events_v3_hw(hisi_hba, phy_no);
1820 
1821 		if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1822 			dev_info(dev, "phy%d invalid dword cnt:   %u\n", phy_no,
1823 				 sphy->invalid_dword_count);
1824 
1825 		if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1826 			dev_info(dev, "phy%d code violation cnt:  %u\n", phy_no,
1827 				 phy->code_violation_err_count);
1828 
1829 		if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1830 			dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1831 				 sphy->running_disparity_error_count);
1832 	}
1833 
1834 	if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1835 	    (pci_dev->revision == 0x20)) {
1836 		u32 reg_value;
1837 		int rc;
1838 
1839 		rc = hisi_sas_read32_poll_timeout_atomic(
1840 				HILINK_ERR_DFX, reg_value,
1841 				!((reg_value >> 8) & BIT(phy_no)),
1842 				1000, 10000);
1843 		if (rc)
1844 			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1845 	}
1846 
1847 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1848 }
1849 
1850 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1851 {
1852 	u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1853 
1854 	if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1855 		hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1856 
1857 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1858 			     irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1859 			     & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1860 			     & (~CHL_INT0_NOT_RDY_MSK));
1861 }
1862 
1863 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1864 {
1865 	struct hisi_hba *hisi_hba = p;
1866 	u32 irq_msk;
1867 	int phy_no = 0;
1868 
1869 	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1870 		  & CHNL_INT_STS_MSK;
1871 
1872 	while (irq_msk) {
1873 		if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1874 			handle_chl_int0_v3_hw(hisi_hba, phy_no);
1875 
1876 		if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1877 			handle_chl_int1_v3_hw(hisi_hba, phy_no);
1878 
1879 		if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1880 			handle_chl_int2_v3_hw(hisi_hba, phy_no);
1881 
1882 		irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1883 		phy_no++;
1884 	}
1885 
1886 	return IRQ_HANDLED;
1887 }
1888 
1889 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1890 	{
1891 		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1892 		.msk = HGC_DQE_ECC_MB_ADDR_MSK,
1893 		.shift = HGC_DQE_ECC_MB_ADDR_OFF,
1894 		.msg = "hgc_dqe_eccbad_intr",
1895 		.reg = HGC_DQE_ECC_ADDR,
1896 	},
1897 	{
1898 		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1899 		.msk = HGC_IOST_ECC_MB_ADDR_MSK,
1900 		.shift = HGC_IOST_ECC_MB_ADDR_OFF,
1901 		.msg = "hgc_iost_eccbad_intr",
1902 		.reg = HGC_IOST_ECC_ADDR,
1903 	},
1904 	{
1905 		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1906 		.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1907 		.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1908 		.msg = "hgc_itct_eccbad_intr",
1909 		.reg = HGC_ITCT_ECC_ADDR,
1910 	},
1911 	{
1912 		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1913 		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1914 		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1915 		.msg = "hgc_iostl_eccbad_intr",
1916 		.reg = HGC_LM_DFX_STATUS2,
1917 	},
1918 	{
1919 		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1920 		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1921 		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1922 		.msg = "hgc_itctl_eccbad_intr",
1923 		.reg = HGC_LM_DFX_STATUS2,
1924 	},
1925 	{
1926 		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1927 		.msk = HGC_CQE_ECC_MB_ADDR_MSK,
1928 		.shift = HGC_CQE_ECC_MB_ADDR_OFF,
1929 		.msg = "hgc_cqe_eccbad_intr",
1930 		.reg = HGC_CQE_ECC_ADDR,
1931 	},
1932 	{
1933 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1934 		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1935 		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1936 		.msg = "rxm_mem0_eccbad_intr",
1937 		.reg = HGC_RXM_DFX_STATUS14,
1938 	},
1939 	{
1940 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1941 		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1942 		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1943 		.msg = "rxm_mem1_eccbad_intr",
1944 		.reg = HGC_RXM_DFX_STATUS14,
1945 	},
1946 	{
1947 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1948 		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1949 		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1950 		.msg = "rxm_mem2_eccbad_intr",
1951 		.reg = HGC_RXM_DFX_STATUS14,
1952 	},
1953 	{
1954 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
1955 		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
1956 		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
1957 		.msg = "rxm_mem3_eccbad_intr",
1958 		.reg = HGC_RXM_DFX_STATUS15,
1959 	},
1960 	{
1961 		.irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
1962 		.msk = AM_ROB_ECC_ERR_ADDR_MSK,
1963 		.shift = AM_ROB_ECC_ERR_ADDR_OFF,
1964 		.msg = "ooo_ram_eccbad_intr",
1965 		.reg = AM_ROB_ECC_ERR_ADDR,
1966 	},
1967 };
1968 
1969 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
1970 					      u32 irq_value)
1971 {
1972 	struct device *dev = hisi_hba->dev;
1973 	const struct hisi_sas_hw_error *ecc_error;
1974 	u32 val;
1975 	int i;
1976 
1977 	for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
1978 		ecc_error = &multi_bit_ecc_errors[i];
1979 		if (irq_value & ecc_error->irq_msk) {
1980 			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
1981 			val &= ecc_error->msk;
1982 			val >>= ecc_error->shift;
1983 			dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
1984 				ecc_error->msg, irq_value, val);
1985 			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1986 		}
1987 	}
1988 }
1989 
1990 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
1991 {
1992 	u32 irq_value, irq_msk;
1993 
1994 	irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
1995 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1996 
1997 	irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
1998 	if (irq_value)
1999 		multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
2000 
2001 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2002 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2003 }
2004 
2005 static const struct hisi_sas_hw_error axi_error[] = {
2006 	{ .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2007 	{ .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2008 	{ .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2009 	{ .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2010 	{ .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2011 	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2012 	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2013 	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2014 	{}
2015 };
2016 
2017 static const struct hisi_sas_hw_error fifo_error[] = {
2018 	{ .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
2019 	{ .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
2020 	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
2021 	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
2022 	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2023 	{}
2024 };
2025 
2026 static const struct hisi_sas_hw_error fatal_axi_error[] = {
2027 	{
2028 		.irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2029 		.msg = "write pointer and depth",
2030 	},
2031 	{
2032 		.irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2033 		.msg = "iptt no match slot",
2034 	},
2035 	{
2036 		.irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2037 		.msg = "read pointer and depth",
2038 	},
2039 	{
2040 		.irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2041 		.reg = HGC_AXI_FIFO_ERR_INFO,
2042 		.sub = axi_error,
2043 	},
2044 	{
2045 		.irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2046 		.reg = HGC_AXI_FIFO_ERR_INFO,
2047 		.sub = fifo_error,
2048 	},
2049 	{
2050 		.irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2051 		.msg = "LM add/fetch list",
2052 	},
2053 	{
2054 		.irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2055 		.msg = "SAS_HGC_ABT fetch LM list",
2056 	},
2057 	{
2058 		.irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2059 		.msg = "read dqe poison",
2060 	},
2061 	{
2062 		.irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2063 		.msg = "read iost poison",
2064 	},
2065 	{
2066 		.irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2067 		.msg = "read itct poison",
2068 	},
2069 	{
2070 		.irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2071 		.msg = "read itct ncq poison",
2072 	},
2073 
2074 };
2075 
2076 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2077 {
2078 	u32 irq_value, irq_msk;
2079 	struct hisi_hba *hisi_hba = p;
2080 	struct device *dev = hisi_hba->dev;
2081 	struct pci_dev *pdev = hisi_hba->pci_dev;
2082 	int i;
2083 
2084 	irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2085 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2086 
2087 	irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2088 	irq_value &= ~irq_msk;
2089 
2090 	for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2091 		const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2092 
2093 		if (!(irq_value & error->irq_msk))
2094 			continue;
2095 
2096 		if (error->sub) {
2097 			const struct hisi_sas_hw_error *sub = error->sub;
2098 			u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2099 
2100 			for (; sub->msk || sub->msg; sub++) {
2101 				if (!(err_value & sub->msk))
2102 					continue;
2103 
2104 				dev_err(dev, "%s error (0x%x) found!\n",
2105 					sub->msg, irq_value);
2106 				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2107 			}
2108 		} else {
2109 			dev_err(dev, "%s error (0x%x) found!\n",
2110 				error->msg, irq_value);
2111 			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2112 		}
2113 
2114 		if (pdev->revision < 0x21) {
2115 			u32 reg_val;
2116 
2117 			reg_val = hisi_sas_read32(hisi_hba,
2118 						  AXI_MASTER_CFG_BASE +
2119 						  AM_CTRL_GLOBAL);
2120 			reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2121 			hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2122 					 AM_CTRL_GLOBAL, reg_val);
2123 		}
2124 	}
2125 
2126 	fatal_ecc_int_v3_hw(hisi_hba);
2127 
2128 	if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2129 		u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2130 		u32 dev_id = reg_val & ITCT_DEV_MSK;
2131 		struct hisi_sas_device *sas_dev =
2132 				&hisi_hba->devices[dev_id];
2133 
2134 		hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2135 		dev_dbg(dev, "clear ITCT ok\n");
2136 		complete(sas_dev->completion);
2137 	}
2138 
2139 	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2140 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2141 
2142 	return IRQ_HANDLED;
2143 }
2144 
2145 static bool
2146 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2147 	       struct hisi_sas_slot *slot)
2148 {
2149 	struct task_status_struct *ts = &task->task_status;
2150 	struct hisi_sas_complete_v3_hdr *complete_queue =
2151 			hisi_hba->complete_hdr[slot->cmplt_queue];
2152 	struct hisi_sas_complete_v3_hdr *complete_hdr =
2153 			&complete_queue[slot->cmplt_queue_slot];
2154 	struct hisi_sas_err_record_v3 *record =
2155 			hisi_sas_status_buf_addr_mem(slot);
2156 	u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2157 	u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2158 	u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2159 
2160 	switch (task->task_proto) {
2161 	case SAS_PROTOCOL_SSP:
2162 		if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2163 			/*
2164 			 * If returned response frame is incorrect because of data underflow,
2165 			 * but I/O information has been written to the host memory, we examine
2166 			 * response IU.
2167 			 */
2168 			if (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2169 				(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2170 				return false;
2171 
2172 			ts->residual = trans_tx_fail_type;
2173 			ts->stat = SAS_DATA_UNDERRUN;
2174 		} else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2175 			ts->stat = SAS_QUEUE_FULL;
2176 			slot->abort = 1;
2177 		} else {
2178 			ts->stat = SAS_OPEN_REJECT;
2179 			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2180 		}
2181 		break;
2182 	case SAS_PROTOCOL_SATA:
2183 	case SAS_PROTOCOL_STP:
2184 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2185 		if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2186 			ts->residual = trans_tx_fail_type;
2187 			ts->stat = SAS_DATA_UNDERRUN;
2188 		} else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2189 			ts->stat = SAS_PHY_DOWN;
2190 			slot->abort = 1;
2191 		} else {
2192 			ts->stat = SAS_OPEN_REJECT;
2193 			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2194 		}
2195 		hisi_sas_sata_done(task, slot);
2196 		break;
2197 	case SAS_PROTOCOL_SMP:
2198 		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2199 		break;
2200 	default:
2201 		break;
2202 	}
2203 	return true;
2204 }
2205 
2206 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2207 				struct hisi_sas_slot *slot)
2208 {
2209 	struct sas_task *task = slot->task;
2210 	struct hisi_sas_device *sas_dev;
2211 	struct device *dev = hisi_hba->dev;
2212 	struct task_status_struct *ts;
2213 	struct domain_device *device;
2214 	struct sas_ha_struct *ha;
2215 	struct hisi_sas_complete_v3_hdr *complete_queue =
2216 			hisi_hba->complete_hdr[slot->cmplt_queue];
2217 	struct hisi_sas_complete_v3_hdr *complete_hdr =
2218 			&complete_queue[slot->cmplt_queue_slot];
2219 	unsigned long flags;
2220 	bool is_internal = slot->is_internal;
2221 	u32 dw0, dw1, dw3;
2222 
2223 	if (unlikely(!task || !task->lldd_task || !task->dev))
2224 		return;
2225 
2226 	ts = &task->task_status;
2227 	device = task->dev;
2228 	ha = device->port->ha;
2229 	sas_dev = device->lldd_dev;
2230 
2231 	spin_lock_irqsave(&task->task_state_lock, flags);
2232 	task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2233 	spin_unlock_irqrestore(&task->task_state_lock, flags);
2234 
2235 	memset(ts, 0, sizeof(*ts));
2236 	ts->resp = SAS_TASK_COMPLETE;
2237 
2238 	if (unlikely(!sas_dev)) {
2239 		dev_dbg(dev, "slot complete: port has not device\n");
2240 		ts->stat = SAS_PHY_DOWN;
2241 		goto out;
2242 	}
2243 
2244 	dw0 = le32_to_cpu(complete_hdr->dw0);
2245 	dw1 = le32_to_cpu(complete_hdr->dw1);
2246 	dw3 = le32_to_cpu(complete_hdr->dw3);
2247 
2248 	/*
2249 	 * Use SAS+TMF status codes
2250 	 */
2251 	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2252 	case STAT_IO_ABORTED:
2253 		/* this IO has been aborted by abort command */
2254 		ts->stat = SAS_ABORTED_TASK;
2255 		goto out;
2256 	case STAT_IO_COMPLETE:
2257 		/* internal abort command complete */
2258 		ts->stat = TMF_RESP_FUNC_SUCC;
2259 		goto out;
2260 	case STAT_IO_NO_DEVICE:
2261 		ts->stat = TMF_RESP_FUNC_COMPLETE;
2262 		goto out;
2263 	case STAT_IO_NOT_VALID:
2264 		/*
2265 		 * abort single IO, the controller can't find the IO
2266 		 */
2267 		ts->stat = TMF_RESP_FUNC_FAILED;
2268 		goto out;
2269 	default:
2270 		break;
2271 	}
2272 
2273 	/* check for erroneous completion */
2274 	if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2275 		u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2276 
2277 		if (slot_err_v3_hw(hisi_hba, task, slot)) {
2278 			if (ts->stat != SAS_DATA_UNDERRUN)
2279 				dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2280 					slot->idx, task, sas_dev->device_id,
2281 					SAS_ADDR(device->sas_addr),
2282 					dw0, dw1, complete_hdr->act, dw3,
2283 					error_info[0], error_info[1],
2284 					error_info[2], error_info[3]);
2285 			if (unlikely(slot->abort)) {
2286 				sas_task_abort(task);
2287 				return;
2288 			}
2289 			goto out;
2290 		}
2291 	}
2292 
2293 	switch (task->task_proto) {
2294 	case SAS_PROTOCOL_SSP: {
2295 		struct ssp_response_iu *iu =
2296 			hisi_sas_status_buf_addr_mem(slot) +
2297 			sizeof(struct hisi_sas_err_record);
2298 
2299 		sas_ssp_task_response(dev, task, iu);
2300 		break;
2301 	}
2302 	case SAS_PROTOCOL_SMP: {
2303 		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2304 		void *to = page_address(sg_page(sg_resp));
2305 
2306 		ts->stat = SAS_SAM_STAT_GOOD;
2307 
2308 		dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
2309 			     DMA_TO_DEVICE);
2310 		memcpy(to + sg_resp->offset,
2311 			hisi_sas_status_buf_addr_mem(slot) +
2312 		       sizeof(struct hisi_sas_err_record),
2313 		       sg_resp->length);
2314 		break;
2315 	}
2316 	case SAS_PROTOCOL_SATA:
2317 	case SAS_PROTOCOL_STP:
2318 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2319 		ts->stat = SAS_SAM_STAT_GOOD;
2320 		hisi_sas_sata_done(task, slot);
2321 		break;
2322 	default:
2323 		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2324 		break;
2325 	}
2326 
2327 	if (!slot->port->port_attached) {
2328 		dev_warn(dev, "slot complete: port %d has removed\n",
2329 			slot->port->sas_port.id);
2330 		ts->stat = SAS_PHY_DOWN;
2331 	}
2332 
2333 out:
2334 	spin_lock_irqsave(&task->task_state_lock, flags);
2335 	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2336 		spin_unlock_irqrestore(&task->task_state_lock, flags);
2337 		dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2338 		return;
2339 	}
2340 	task->task_state_flags |= SAS_TASK_STATE_DONE;
2341 	spin_unlock_irqrestore(&task->task_state_lock, flags);
2342 	hisi_sas_slot_task_free(hisi_hba, task, slot);
2343 
2344 	if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2345 		spin_lock_irqsave(&device->done_lock, flags);
2346 		if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2347 			spin_unlock_irqrestore(&device->done_lock, flags);
2348 			dev_info(dev, "slot complete: task(%pK) ignored\n ",
2349 				 task);
2350 			return;
2351 		}
2352 		spin_unlock_irqrestore(&device->done_lock, flags);
2353 	}
2354 
2355 	if (task->task_done)
2356 		task->task_done(task);
2357 }
2358 
2359 static irqreturn_t  cq_thread_v3_hw(int irq_no, void *p)
2360 {
2361 	struct hisi_sas_cq *cq = p;
2362 	struct hisi_hba *hisi_hba = cq->hisi_hba;
2363 	struct hisi_sas_slot *slot;
2364 	struct hisi_sas_complete_v3_hdr *complete_queue;
2365 	u32 rd_point = cq->rd_point, wr_point;
2366 	int queue = cq->id;
2367 
2368 	complete_queue = hisi_hba->complete_hdr[queue];
2369 
2370 	wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2371 				   (0x14 * queue));
2372 
2373 	while (rd_point != wr_point) {
2374 		struct hisi_sas_complete_v3_hdr *complete_hdr;
2375 		struct device *dev = hisi_hba->dev;
2376 		u32 dw1;
2377 		int iptt;
2378 
2379 		complete_hdr = &complete_queue[rd_point];
2380 		dw1 = le32_to_cpu(complete_hdr->dw1);
2381 
2382 		iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2383 		if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2384 			slot = &hisi_hba->slot_info[iptt];
2385 			slot->cmplt_queue_slot = rd_point;
2386 			slot->cmplt_queue = queue;
2387 			slot_complete_v3_hw(hisi_hba, slot);
2388 		} else
2389 			dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2390 
2391 		if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2392 			rd_point = 0;
2393 	}
2394 
2395 	/* update rd_point */
2396 	cq->rd_point = rd_point;
2397 	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2398 
2399 	return IRQ_HANDLED;
2400 }
2401 
2402 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2403 {
2404 	struct hisi_sas_cq *cq = p;
2405 	struct hisi_hba *hisi_hba = cq->hisi_hba;
2406 	int queue = cq->id;
2407 
2408 	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2409 
2410 	return IRQ_WAKE_THREAD;
2411 }
2412 
2413 static void hisi_sas_v3_free_vectors(void *data)
2414 {
2415 	struct pci_dev *pdev = data;
2416 
2417 	pci_free_irq_vectors(pdev);
2418 }
2419 
2420 static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2421 {
2422 	int vectors;
2423 	int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi;
2424 	struct Scsi_Host *shost = hisi_hba->shost;
2425 	struct pci_dev *pdev = hisi_hba->pci_dev;
2426 	struct irq_affinity desc = {
2427 		.pre_vectors = BASE_VECTORS_V3_HW,
2428 	};
2429 
2430 	min_msi = MIN_AFFINE_VECTORS_V3_HW;
2431 	vectors = pci_alloc_irq_vectors_affinity(pdev,
2432 						 min_msi, max_msi,
2433 						 PCI_IRQ_MSI |
2434 						 PCI_IRQ_AFFINITY,
2435 						 &desc);
2436 	if (vectors < 0)
2437 		return -ENOENT;
2438 
2439 
2440 	hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW;
2441 	shost->nr_hw_queues = hisi_hba->cq_nvecs;
2442 
2443 	devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2444 	return 0;
2445 }
2446 
2447 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2448 {
2449 	struct device *dev = hisi_hba->dev;
2450 	struct pci_dev *pdev = hisi_hba->pci_dev;
2451 	int rc, i;
2452 
2453 	rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2454 			      int_phy_up_down_bcast_v3_hw, 0,
2455 			      DRV_NAME " phy", hisi_hba);
2456 	if (rc) {
2457 		dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2458 		return -ENOENT;
2459 	}
2460 
2461 	rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2462 			      int_chnl_int_v3_hw, 0,
2463 			      DRV_NAME " channel", hisi_hba);
2464 	if (rc) {
2465 		dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2466 		return -ENOENT;
2467 	}
2468 
2469 	rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2470 			      fatal_axi_int_v3_hw, 0,
2471 			      DRV_NAME " fatal", hisi_hba);
2472 	if (rc) {
2473 		dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2474 		return -ENOENT;
2475 	}
2476 
2477 	if (hisi_sas_intr_conv)
2478 		dev_info(dev, "Enable interrupt converge\n");
2479 
2480 	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2481 		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2482 		int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2483 		unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2484 							      IRQF_ONESHOT;
2485 
2486 		cq->irq_no = pci_irq_vector(pdev, nr);
2487 		rc = devm_request_threaded_irq(dev, cq->irq_no,
2488 				      cq_interrupt_v3_hw,
2489 				      cq_thread_v3_hw,
2490 				      irqflags,
2491 				      DRV_NAME " cq", cq);
2492 		if (rc) {
2493 			dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2494 				i, rc);
2495 			return -ENOENT;
2496 		}
2497 		cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2498 		if (!cq->irq_mask) {
2499 			dev_err(dev, "could not get cq%d irq affinity!\n", i);
2500 			return -ENOENT;
2501 		}
2502 	}
2503 
2504 	return 0;
2505 }
2506 
2507 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2508 {
2509 	int rc;
2510 
2511 	rc = hw_init_v3_hw(hisi_hba);
2512 	if (rc)
2513 		return rc;
2514 
2515 	rc = interrupt_init_v3_hw(hisi_hba);
2516 	if (rc)
2517 		return rc;
2518 
2519 	return 0;
2520 }
2521 
2522 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2523 		struct sas_phy_linkrates *r)
2524 {
2525 	enum sas_linkrate max = r->maximum_linkrate;
2526 	u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2527 						     PROG_PHY_LINK_RATE);
2528 
2529 	prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2530 	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2531 	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2532 			     prog_phy_link_rate);
2533 }
2534 
2535 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2536 {
2537 	struct pci_dev *pdev = hisi_hba->pci_dev;
2538 	int i;
2539 
2540 	synchronize_irq(pci_irq_vector(pdev, 1));
2541 	synchronize_irq(pci_irq_vector(pdev, 2));
2542 	synchronize_irq(pci_irq_vector(pdev, 11));
2543 	for (i = 0; i < hisi_hba->queue_count; i++)
2544 		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2545 
2546 	for (i = 0; i < hisi_hba->cq_nvecs; i++)
2547 		synchronize_irq(pci_irq_vector(pdev, i + 16));
2548 
2549 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2550 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2551 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2552 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2553 
2554 	for (i = 0; i < hisi_hba->n_phy; i++) {
2555 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2556 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2557 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2558 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2559 		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2560 	}
2561 }
2562 
2563 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2564 {
2565 	return hisi_sas_read32(hisi_hba, PHY_STATE);
2566 }
2567 
2568 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2569 {
2570 	struct device *dev = hisi_hba->dev;
2571 	u32 status, reg_val;
2572 	int rc;
2573 
2574 	interrupt_disable_v3_hw(hisi_hba);
2575 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2576 
2577 	hisi_sas_stop_phys(hisi_hba);
2578 
2579 	mdelay(10);
2580 
2581 	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2582 				  AM_CTRL_GLOBAL);
2583 	reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2584 	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2585 			 AM_CTRL_GLOBAL, reg_val);
2586 
2587 	/* wait until bus idle */
2588 	rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2589 					  AM_CURR_TRANS_RETURN, status,
2590 					  status == 0x3, 10, 100);
2591 	if (rc) {
2592 		dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2593 		return rc;
2594 	}
2595 
2596 	return 0;
2597 }
2598 
2599 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2600 {
2601 	struct device *dev = hisi_hba->dev;
2602 	int rc;
2603 
2604 	rc = disable_host_v3_hw(hisi_hba);
2605 	if (rc) {
2606 		dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2607 		return rc;
2608 	}
2609 
2610 	hisi_sas_init_mem(hisi_hba);
2611 
2612 	return hw_init_v3_hw(hisi_hba);
2613 }
2614 
2615 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2616 			u8 reg_index, u8 reg_count, u8 *write_data)
2617 {
2618 	struct device *dev = hisi_hba->dev;
2619 	u32 *data = (u32 *)write_data;
2620 	int i;
2621 
2622 	switch (reg_type) {
2623 	case SAS_GPIO_REG_TX:
2624 		if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2625 			dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2626 				reg_index, reg_index + reg_count - 1);
2627 			return -EINVAL;
2628 		}
2629 
2630 		for (i = 0; i < reg_count; i++)
2631 			hisi_sas_write32(hisi_hba,
2632 					 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2633 					 data[i]);
2634 		break;
2635 	default:
2636 		dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2637 			reg_type);
2638 		return -EINVAL;
2639 	}
2640 
2641 	return 0;
2642 }
2643 
2644 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2645 					     int delay_ms, int timeout_ms)
2646 {
2647 	struct device *dev = hisi_hba->dev;
2648 	int entries, entries_old = 0, time;
2649 
2650 	for (time = 0; time < timeout_ms; time += delay_ms) {
2651 		entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2652 		if (entries == entries_old)
2653 			break;
2654 
2655 		entries_old = entries;
2656 		msleep(delay_ms);
2657 	}
2658 
2659 	if (time >= timeout_ms) {
2660 		dev_dbg(dev, "Wait commands complete timeout!\n");
2661 		return;
2662 	}
2663 
2664 	dev_dbg(dev, "wait commands complete %dms\n", time);
2665 }
2666 
2667 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2668 				    struct device_attribute *attr, char *buf)
2669 {
2670 	return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2671 }
2672 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2673 
2674 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2675 {
2676 	/* config those registers between enable and disable PHYs */
2677 	hisi_sas_stop_phys(hisi_hba);
2678 
2679 	if (hisi_hba->intr_coal_ticks == 0 ||
2680 	    hisi_hba->intr_coal_count == 0) {
2681 		hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2682 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2683 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2684 	} else {
2685 		hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2686 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2687 				 hisi_hba->intr_coal_ticks);
2688 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2689 				 hisi_hba->intr_coal_count);
2690 	}
2691 	phys_init_v3_hw(hisi_hba);
2692 }
2693 
2694 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2695 					  struct device_attribute *attr,
2696 					  char *buf)
2697 {
2698 	struct Scsi_Host *shost = class_to_shost(dev);
2699 	struct hisi_hba *hisi_hba = shost_priv(shost);
2700 
2701 	return scnprintf(buf, PAGE_SIZE, "%u\n",
2702 			 hisi_hba->intr_coal_ticks);
2703 }
2704 
2705 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2706 					   struct device_attribute *attr,
2707 					   const char *buf, size_t count)
2708 {
2709 	struct Scsi_Host *shost = class_to_shost(dev);
2710 	struct hisi_hba *hisi_hba = shost_priv(shost);
2711 	u32 intr_coal_ticks;
2712 	int ret;
2713 
2714 	ret = kstrtou32(buf, 10, &intr_coal_ticks);
2715 	if (ret) {
2716 		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2717 		return -EINVAL;
2718 	}
2719 
2720 	if (intr_coal_ticks >= BIT(24)) {
2721 		dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2722 		return -EINVAL;
2723 	}
2724 
2725 	hisi_hba->intr_coal_ticks = intr_coal_ticks;
2726 
2727 	config_intr_coal_v3_hw(hisi_hba);
2728 
2729 	return count;
2730 }
2731 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2732 
2733 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2734 					  struct device_attribute
2735 					  *attr, char *buf)
2736 {
2737 	struct Scsi_Host *shost = class_to_shost(dev);
2738 	struct hisi_hba *hisi_hba = shost_priv(shost);
2739 
2740 	return scnprintf(buf, PAGE_SIZE, "%u\n",
2741 			 hisi_hba->intr_coal_count);
2742 }
2743 
2744 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2745 		struct device_attribute
2746 		*attr, const char *buf, size_t count)
2747 {
2748 	struct Scsi_Host *shost = class_to_shost(dev);
2749 	struct hisi_hba *hisi_hba = shost_priv(shost);
2750 	u32 intr_coal_count;
2751 	int ret;
2752 
2753 	ret = kstrtou32(buf, 10, &intr_coal_count);
2754 	if (ret) {
2755 		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2756 		return -EINVAL;
2757 	}
2758 
2759 	if (intr_coal_count >= BIT(8)) {
2760 		dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2761 		return -EINVAL;
2762 	}
2763 
2764 	hisi_hba->intr_coal_count = intr_coal_count;
2765 
2766 	config_intr_coal_v3_hw(hisi_hba);
2767 
2768 	return count;
2769 }
2770 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2771 
2772 static int slave_configure_v3_hw(struct scsi_device *sdev)
2773 {
2774 	struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2775 	struct domain_device *ddev = sdev_to_domain_dev(sdev);
2776 	struct hisi_hba *hisi_hba = shost_priv(shost);
2777 	struct device *dev = hisi_hba->dev;
2778 	int ret = sas_slave_configure(sdev);
2779 
2780 	if (ret)
2781 		return ret;
2782 	if (!dev_is_sata(ddev))
2783 		sas_change_queue_depth(sdev, 64);
2784 
2785 	if (sdev->type == TYPE_ENCLOSURE)
2786 		return 0;
2787 
2788 	if (!device_link_add(&sdev->sdev_gendev, dev,
2789 			     DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2790 		if (pm_runtime_enabled(dev)) {
2791 			dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2792 			pm_runtime_disable(dev);
2793 		}
2794 	}
2795 
2796 	return 0;
2797 }
2798 
2799 static struct attribute *host_v3_hw_attrs[] = {
2800 	&dev_attr_phy_event_threshold.attr,
2801 	&dev_attr_intr_conv_v3_hw.attr,
2802 	&dev_attr_intr_coal_ticks_v3_hw.attr,
2803 	&dev_attr_intr_coal_count_v3_hw.attr,
2804 	NULL
2805 };
2806 
2807 ATTRIBUTE_GROUPS(host_v3_hw);
2808 
2809 #define HISI_SAS_DEBUGFS_REG(x) {#x, x}
2810 
2811 struct hisi_sas_debugfs_reg_lu {
2812 	char *name;
2813 	int off;
2814 };
2815 
2816 struct hisi_sas_debugfs_reg {
2817 	const struct hisi_sas_debugfs_reg_lu *lu;
2818 	int count;
2819 	int base_off;
2820 };
2821 
2822 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2823 	HISI_SAS_DEBUGFS_REG(PHY_CFG),
2824 	HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2825 	HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2826 	HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2827 	HISI_SAS_DEBUGFS_REG(SL_CFG),
2828 	HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2829 	HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2830 	HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2831 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2832 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2833 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2834 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2835 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2836 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2837 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2838 	HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2839 	HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2840 	HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2841 	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2842 	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2843 	HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2844 	HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2845 	HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2846 	HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2847 	HISI_SAS_DEBUGFS_REG(CHL_INT0),
2848 	HISI_SAS_DEBUGFS_REG(CHL_INT1),
2849 	HISI_SAS_DEBUGFS_REG(CHL_INT2),
2850 	HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2851 	HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2852 	HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2853 	HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2854 	HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2855 	HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2856 	HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2857 	HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2858 	HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2859 	HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2860 	HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2861 	HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2862 	HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2863 	HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2864 	HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2865 	HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2866 	HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2867 	HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
2868 	HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
2869 	HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
2870 	{}
2871 };
2872 
2873 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
2874 	.lu = debugfs_port_reg_lu,
2875 	.count = 0x100,
2876 	.base_off = PORT_BASE,
2877 };
2878 
2879 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
2880 	HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
2881 	HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
2882 	HISI_SAS_DEBUGFS_REG(PHY_STATE),
2883 	HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
2884 	HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
2885 	HISI_SAS_DEBUGFS_REG(ITCT_CLR),
2886 	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
2887 	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
2888 	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
2889 	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
2890 	HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
2891 	HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
2892 	HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
2893 	HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
2894 	HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
2895 	HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
2896 	HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
2897 	HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
2898 	HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
2899 	HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
2900 	HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
2901 	HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
2902 	HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
2903 	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
2904 	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
2905 	HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
2906 	HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
2907 	HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
2908 	HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
2909 	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
2910 	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
2911 	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
2912 	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
2913 	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
2914 	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
2915 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
2916 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
2917 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
2918 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
2919 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
2920 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
2921 	HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
2922 	HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
2923 	HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
2924 	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
2925 	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
2926 	HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
2927 	HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
2928 	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
2929 	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
2930 	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
2931 	HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
2932 	HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
2933 	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
2934 	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
2935 	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
2936 	HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
2937 	HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
2938 	HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
2939 	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
2940 	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
2941 	HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
2942 	HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
2943 	{}
2944 };
2945 
2946 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
2947 	.lu = debugfs_global_reg_lu,
2948 	.count = 0x800,
2949 };
2950 
2951 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
2952 	HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
2953 	HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
2954 	HISI_SAS_DEBUGFS_REG(AXI_CFG),
2955 	HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
2956 	{}
2957 };
2958 
2959 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
2960 	.lu = debugfs_axi_reg_lu,
2961 	.count = 0x61,
2962 	.base_off = AXI_MASTER_CFG_BASE,
2963 };
2964 
2965 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
2966 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
2967 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
2968 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
2969 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
2970 	HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
2971 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
2972 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
2973 	{}
2974 };
2975 
2976 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
2977 	.lu = debugfs_ras_reg_lu,
2978 	.count = 0x10,
2979 	.base_off = RAS_BASE,
2980 };
2981 
2982 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
2983 {
2984 	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2985 
2986 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
2987 
2988 	wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
2989 
2990 	hisi_sas_sync_irqs(hisi_hba);
2991 }
2992 
2993 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
2994 {
2995 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
2996 			 (u32)((1ULL << hisi_hba->queue_count) - 1));
2997 
2998 	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
2999 }
3000 
3001 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
3002 				       enum hisi_sas_debugfs_cache_type type,
3003 				       u32 *cache)
3004 {
3005 	u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
3006 			    HISI_SAS_IOST_ITCT_CACHE_NUM;
3007 	struct device *dev = hisi_hba->dev;
3008 	u32 *buf = cache;
3009 	u32 i, val;
3010 
3011 	hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
3012 
3013 	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
3014 		val = hisi_sas_read32(hisi_hba, TAB_DFX);
3015 		if (val == 0xffffffff)
3016 			break;
3017 	}
3018 
3019 	if (val != 0xffffffff) {
3020 		dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
3021 		return;
3022 	}
3023 
3024 	memset(buf, 0, cache_dw_size * 4);
3025 	buf[0] = val;
3026 
3027 	for (i = 1; i < cache_dw_size; i++)
3028 		buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3029 }
3030 
3031 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3032 {
3033 	u32 reg_val;
3034 	int phy_no = hisi_hba->debugfs_bist_phy_no;
3035 	int i;
3036 
3037 	/* disable PHY */
3038 	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3039 
3040 	/* update FFE */
3041 	for (i = 0; i < FFE_CFG_MAX; i++)
3042 		hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3043 				     hisi_hba->debugfs_bist_ffe[phy_no][i]);
3044 
3045 	/* disable ALOS */
3046 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3047 	reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3048 	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3049 }
3050 
3051 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3052 {
3053 	u32 reg_val;
3054 	int phy_no = hisi_hba->debugfs_bist_phy_no;
3055 
3056 	/* disable loopback */
3057 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3058 	reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3059 		     CFG_BIST_TEST_MSK);
3060 	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3061 
3062 	/* enable ALOS */
3063 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3064 	reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3065 	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3066 
3067 	/* restore the linkrate */
3068 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3069 	/* init OOB link rate as 1.5 Gbits */
3070 	reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3071 	reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3072 	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3073 
3074 	/* enable PHY */
3075 	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3076 }
3077 
3078 #define SAS_PHY_BIST_CODE_INIT	0x1
3079 #define SAS_PHY_BIST_CODE1_INIT	0X80
3080 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3081 {
3082 	u32 reg_val, mode_tmp;
3083 	u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3084 	u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3085 	u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3086 	u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3087 	u32 path_mode = hisi_hba->debugfs_bist_mode;
3088 	u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3089 	struct device *dev = hisi_hba->dev;
3090 
3091 	dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3092 		 phy_no, linkrate, code_mode, path_mode,
3093 		 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3094 		 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3095 		 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3096 		 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3097 		 fix_code[FIXED_CODE_1]);
3098 	mode_tmp = path_mode ? 2 : 1;
3099 	if (enable) {
3100 		/* some preparations before bist test */
3101 		hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3102 
3103 		/* set linkrate of bit test*/
3104 		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3105 					      PROG_PHY_LINK_RATE);
3106 		reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3107 		reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3108 		hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3109 				     reg_val);
3110 
3111 		/* set code mode of bit test */
3112 		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3113 					      SAS_PHY_BIST_CTRL);
3114 		reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3115 			     CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3116 			     CFG_BIST_TEST_MSK);
3117 		reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3118 			    (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3119 			    CFG_BIST_TEST_MSK);
3120 		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3121 				     reg_val);
3122 
3123 		/* set the bist init value */
3124 		if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3125 			reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3126 			hisi_sas_phy_write32(hisi_hba, phy_no,
3127 					     SAS_PHY_BIST_CODE, reg_val);
3128 
3129 			reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3130 			hisi_sas_phy_write32(hisi_hba, phy_no,
3131 					     SAS_PHY_BIST_CODE1, reg_val);
3132 		} else {
3133 			hisi_sas_phy_write32(hisi_hba, phy_no,
3134 					     SAS_PHY_BIST_CODE,
3135 					     SAS_PHY_BIST_CODE_INIT);
3136 			hisi_sas_phy_write32(hisi_hba, phy_no,
3137 					     SAS_PHY_BIST_CODE1,
3138 					     SAS_PHY_BIST_CODE1_INIT);
3139 		}
3140 
3141 		mdelay(100);
3142 		reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3143 		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3144 				     reg_val);
3145 
3146 		/* clear error bit */
3147 		mdelay(100);
3148 		hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3149 	} else {
3150 		/* disable bist test and recover it */
3151 		hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3152 				phy_no, SAS_BIST_ERR_CNT);
3153 		hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3154 	}
3155 
3156 	return 0;
3157 }
3158 
3159 static int hisi_sas_map_queues(struct Scsi_Host *shost)
3160 {
3161 	struct hisi_hba *hisi_hba = shost_priv(shost);
3162 	struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
3163 
3164 	return blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
3165 				     BASE_VECTORS_V3_HW);
3166 }
3167 
3168 static struct scsi_host_template sht_v3_hw = {
3169 	.name			= DRV_NAME,
3170 	.proc_name		= DRV_NAME,
3171 	.module			= THIS_MODULE,
3172 	.queuecommand		= sas_queuecommand,
3173 	.dma_need_drain		= ata_scsi_dma_need_drain,
3174 	.target_alloc		= sas_target_alloc,
3175 	.slave_configure	= slave_configure_v3_hw,
3176 	.scan_finished		= hisi_sas_scan_finished,
3177 	.scan_start		= hisi_sas_scan_start,
3178 	.map_queues		= hisi_sas_map_queues,
3179 	.change_queue_depth	= sas_change_queue_depth,
3180 	.bios_param		= sas_bios_param,
3181 	.this_id		= -1,
3182 	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
3183 	.sg_prot_tablesize	= HISI_SAS_SGE_PAGE_CNT,
3184 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
3185 	.eh_device_reset_handler = sas_eh_device_reset_handler,
3186 	.eh_target_reset_handler = sas_eh_target_reset_handler,
3187 	.slave_alloc		= hisi_sas_slave_alloc,
3188 	.target_destroy		= sas_target_destroy,
3189 	.ioctl			= sas_ioctl,
3190 #ifdef CONFIG_COMPAT
3191 	.compat_ioctl		= sas_ioctl,
3192 #endif
3193 	.shost_groups		= host_v3_hw_groups,
3194 	.tag_alloc_policy	= BLK_TAG_ALLOC_RR,
3195 	.host_reset             = hisi_sas_host_reset,
3196 	.host_tagset		= 1,
3197 };
3198 
3199 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3200 	.setup_itct = setup_itct_v3_hw,
3201 	.get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3202 	.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3203 	.clear_itct = clear_itct_v3_hw,
3204 	.sl_notify_ssp = sl_notify_ssp_v3_hw,
3205 	.prep_ssp = prep_ssp_v3_hw,
3206 	.prep_smp = prep_smp_v3_hw,
3207 	.prep_stp = prep_ata_v3_hw,
3208 	.prep_abort = prep_abort_v3_hw,
3209 	.start_delivery = start_delivery_v3_hw,
3210 	.phys_init = phys_init_v3_hw,
3211 	.phy_start = start_phy_v3_hw,
3212 	.phy_disable = disable_phy_v3_hw,
3213 	.phy_hard_reset = phy_hard_reset_v3_hw,
3214 	.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3215 	.phy_set_linkrate = phy_set_linkrate_v3_hw,
3216 	.dereg_device = dereg_device_v3_hw,
3217 	.soft_reset = soft_reset_v3_hw,
3218 	.get_phys_state = get_phys_state_v3_hw,
3219 	.get_events = phy_get_events_v3_hw,
3220 	.write_gpio = write_gpio_v3_hw,
3221 	.wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3222 	.debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3223 };
3224 
3225 static struct Scsi_Host *
3226 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3227 {
3228 	struct Scsi_Host *shost;
3229 	struct hisi_hba *hisi_hba;
3230 	struct device *dev = &pdev->dev;
3231 
3232 	shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3233 	if (!shost) {
3234 		dev_err(dev, "shost alloc failed\n");
3235 		return NULL;
3236 	}
3237 	hisi_hba = shost_priv(shost);
3238 
3239 	INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3240 	INIT_WORK(&hisi_hba->debugfs_work, debugfs_work_handler_v3_hw);
3241 	hisi_hba->hw = &hisi_sas_v3_hw;
3242 	hisi_hba->pci_dev = pdev;
3243 	hisi_hba->dev = dev;
3244 	hisi_hba->shost = shost;
3245 	SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3246 
3247 	if (prot_mask & ~HISI_SAS_PROT_MASK)
3248 		dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3249 			prot_mask);
3250 	else
3251 		hisi_hba->prot_mask = prot_mask;
3252 
3253 	if (hisi_sas_get_fw_info(hisi_hba) < 0)
3254 		goto err_out;
3255 
3256 	if (hisi_sas_alloc(hisi_hba)) {
3257 		hisi_sas_free(hisi_hba);
3258 		goto err_out;
3259 	}
3260 
3261 	return shost;
3262 err_out:
3263 	scsi_host_put(shost);
3264 	dev_err(dev, "shost alloc failed\n");
3265 	return NULL;
3266 }
3267 
3268 static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3269 {
3270 	int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3271 	int dump_index = hisi_hba->debugfs_dump_index;
3272 	int i;
3273 
3274 	for (i = 0; i < hisi_hba->queue_count; i++)
3275 		memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3276 		       hisi_hba->complete_hdr[i],
3277 		       HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3278 }
3279 
3280 static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3281 {
3282 	int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3283 	int dump_index = hisi_hba->debugfs_dump_index;
3284 	int i;
3285 
3286 	for (i = 0; i < hisi_hba->queue_count; i++) {
3287 		struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3288 		int j;
3289 
3290 		debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3291 		cmd_hdr = hisi_hba->cmd_hdr[i];
3292 
3293 		for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3294 			memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3295 			       queue_entry_size);
3296 	}
3297 }
3298 
3299 static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3300 {
3301 	int dump_index = hisi_hba->debugfs_dump_index;
3302 	const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3303 	int i, phy_cnt;
3304 	u32 offset;
3305 	u32 *databuf;
3306 
3307 	for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3308 		databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3309 		for (i = 0; i < port->count; i++, databuf++) {
3310 			offset = port->base_off + 4 * i;
3311 			*databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
3312 						       offset);
3313 		}
3314 	}
3315 }
3316 
3317 static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3318 {
3319 	int dump_index = hisi_hba->debugfs_dump_index;
3320 	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3321 	int i;
3322 
3323 	for (i = 0; i < debugfs_axi_reg.count; i++, databuf++)
3324 		*databuf = hisi_sas_read32(hisi_hba, 4 * i);
3325 }
3326 
3327 static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3328 {
3329 	int dump_index = hisi_hba->debugfs_dump_index;
3330 	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3331 	const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3332 	int i;
3333 
3334 	for (i = 0; i < axi->count; i++, databuf++)
3335 		*databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off);
3336 }
3337 
3338 static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3339 {
3340 	int dump_index = hisi_hba->debugfs_dump_index;
3341 	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3342 	const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3343 	int i;
3344 
3345 	for (i = 0; i < ras->count; i++, databuf++)
3346 		*databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off);
3347 }
3348 
3349 static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3350 {
3351 	int dump_index = hisi_hba->debugfs_dump_index;
3352 	void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3353 	void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3354 	struct hisi_sas_itct *itct;
3355 	int i;
3356 
3357 	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);
3358 
3359 	itct = hisi_hba->itct;
3360 
3361 	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3362 		memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3363 		databuf += sizeof(struct hisi_sas_itct);
3364 	}
3365 }
3366 
3367 static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3368 {
3369 	int dump_index = hisi_hba->debugfs_dump_index;
3370 	int max_command_entries = HISI_SAS_MAX_COMMANDS;
3371 	void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3372 	void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3373 	struct hisi_sas_iost *iost;
3374 	int i;
3375 
3376 	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);
3377 
3378 	iost = hisi_hba->iost;
3379 
3380 	for (i = 0; i < max_command_entries; i++, iost++) {
3381 		memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3382 		databuf += sizeof(struct hisi_sas_iost);
3383 	}
3384 }
3385 
3386 static const char *
3387 debugfs_to_reg_name_v3_hw(int off, int base_off,
3388 			  const struct hisi_sas_debugfs_reg_lu *lu)
3389 {
3390 	for (; lu->name; lu++) {
3391 		if (off == lu->off - base_off)
3392 			return lu->name;
3393 	}
3394 
3395 	return NULL;
3396 }
3397 
3398 static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3399 				    const struct hisi_sas_debugfs_reg *reg)
3400 {
3401 	int i;
3402 
3403 	for (i = 0; i < reg->count; i++) {
3404 		int off = i * 4;
3405 		const char *name;
3406 
3407 		name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
3408 						 reg->lu);
3409 
3410 		if (name)
3411 			seq_printf(s, "0x%08x 0x%08x %s\n", off,
3412 				   regs_val[i], name);
3413 		else
3414 			seq_printf(s, "0x%08x 0x%08x\n", off,
3415 				   regs_val[i]);
3416 	}
3417 }
3418 
3419 static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3420 {
3421 	struct hisi_sas_debugfs_regs *global = s->private;
3422 
3423 	debugfs_print_reg_v3_hw(global->data, s,
3424 				&debugfs_global_reg);
3425 
3426 	return 0;
3427 }
3428 DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3429 
3430 static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3431 {
3432 	struct hisi_sas_debugfs_regs *axi = s->private;
3433 
3434 	debugfs_print_reg_v3_hw(axi->data, s,
3435 				&debugfs_axi_reg);
3436 
3437 	return 0;
3438 }
3439 DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3440 
3441 static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3442 {
3443 	struct hisi_sas_debugfs_regs *ras = s->private;
3444 
3445 	debugfs_print_reg_v3_hw(ras->data, s,
3446 				&debugfs_ras_reg);
3447 
3448 	return 0;
3449 }
3450 DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3451 
3452 static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3453 {
3454 	struct hisi_sas_debugfs_port *port = s->private;
3455 	const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3456 
3457 	debugfs_print_reg_v3_hw(port->data, s, reg_port);
3458 
3459 	return 0;
3460 }
3461 DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3462 
3463 static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3464 				      int sz, __le64 *ptr)
3465 {
3466 	int i;
3467 
3468 	/* completion header size not fixed per HW version */
3469 	seq_printf(s, "index %04d:\n\t", index);
3470 	for (i = 1; i <= sz / 8; i++, ptr++) {
3471 		seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
3472 		if (!(i % 2))
3473 			seq_puts(s, "\n\t");
3474 	}
3475 
3476 	seq_puts(s, "\n");
3477 }
3478 
3479 static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3480 				      int sz, __le32 *ptr)
3481 {
3482 	int i;
3483 
3484 	/* completion header size not fixed per HW version */
3485 	seq_printf(s, "index %04d:\n\t", index);
3486 	for (i = 1; i <= sz / 4; i++, ptr++) {
3487 		seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
3488 		if (!(i % 4))
3489 			seq_puts(s, "\n\t");
3490 	}
3491 	seq_puts(s, "\n");
3492 }
3493 
3494 static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3495 				       struct hisi_sas_debugfs_cq *debugfs_cq)
3496 {
3497 	struct hisi_sas_cq *cq = debugfs_cq->cq;
3498 	struct hisi_hba *hisi_hba = cq->hisi_hba;
3499 	__le32 *complete_hdr = debugfs_cq->complete_hdr +
3500 			       (hisi_hba->hw->complete_hdr_size * slot);
3501 
3502 	debugfs_show_row_32_v3_hw(s, slot,
3503 				  hisi_hba->hw->complete_hdr_size,
3504 				  complete_hdr);
3505 }
3506 
3507 static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3508 {
3509 	struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3510 	int slot;
3511 
3512 	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3513 		debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3514 
3515 	return 0;
3516 }
3517 DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3518 
3519 static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3520 				       void *dq_ptr)
3521 {
3522 	struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3523 	void *cmd_queue = debugfs_dq->hdr;
3524 	__le32 *cmd_hdr = cmd_queue +
3525 		sizeof(struct hisi_sas_cmd_hdr) * slot;
3526 
3527 	debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
3528 				  cmd_hdr);
3529 }
3530 
3531 static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3532 {
3533 	int slot;
3534 
3535 	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3536 		debugfs_dq_show_slot_v3_hw(s, slot, s->private);
3537 
3538 	return 0;
3539 }
3540 DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3541 
3542 static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3543 {
3544 	struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3545 	struct hisi_sas_iost *iost = debugfs_iost->iost;
3546 	int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3547 
3548 	for (i = 0; i < max_command_entries; i++, iost++) {
3549 		__le64 *data = &iost->qw0;
3550 
3551 		debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
3552 	}
3553 
3554 	return 0;
3555 }
3556 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3557 
3558 static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3559 {
3560 	struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3561 	struct hisi_sas_iost_itct_cache *iost_cache =
3562 						debugfs_iost_cache->cache;
3563 	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3564 	int i, tab_idx;
3565 	__le64 *iost;
3566 
3567 	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3568 		/*
3569 		 * Data struct of IOST cache:
3570 		 * Data[1]: BIT0~15: Table index
3571 		 *	    Bit16:   Valid mask
3572 		 * Data[2]~[9]: IOST table
3573 		 */
3574 		tab_idx = (iost_cache->data[1] & 0xffff);
3575 		iost = (__le64 *)iost_cache;
3576 
3577 		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
3578 	}
3579 
3580 	return 0;
3581 }
3582 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3583 
3584 static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3585 {
3586 	int i;
3587 	struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3588 	struct hisi_sas_itct *itct = debugfs_itct->itct;
3589 
3590 	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3591 		__le64 *data = &itct->qw0;
3592 
3593 		debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
3594 	}
3595 
3596 	return 0;
3597 }
3598 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3599 
3600 static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3601 {
3602 	struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3603 	struct hisi_sas_iost_itct_cache *itct_cache =
3604 						debugfs_itct_cache->cache;
3605 	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3606 	int i, tab_idx;
3607 	__le64 *itct;
3608 
3609 	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3610 		/*
3611 		 * Data struct of ITCT cache:
3612 		 * Data[1]: BIT0~15: Table index
3613 		 *	    Bit16:   Valid mask
3614 		 * Data[2]~[9]: ITCT table
3615 		 */
3616 		tab_idx = itct_cache->data[1] & 0xffff;
3617 		itct = (__le64 *)itct_cache;
3618 
3619 		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
3620 	}
3621 
3622 	return 0;
3623 }
3624 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3625 
3626 static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
3627 {
3628 	u64 *debugfs_timestamp;
3629 	int dump_index = hisi_hba->debugfs_dump_index;
3630 	struct dentry *dump_dentry;
3631 	struct dentry *dentry;
3632 	char name[256];
3633 	int p;
3634 	int c;
3635 	int d;
3636 
3637 	snprintf(name, 256, "%d", dump_index);
3638 
3639 	dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
3640 
3641 	debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];
3642 
3643 	debugfs_create_u64("timestamp", 0400, dump_dentry,
3644 			   debugfs_timestamp);
3645 
3646 	debugfs_create_file("global", 0400, dump_dentry,
3647 			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
3648 			    &debugfs_global_v3_hw_fops);
3649 
3650 	/* Create port dir and files */
3651 	dentry = debugfs_create_dir("port", dump_dentry);
3652 	for (p = 0; p < hisi_hba->n_phy; p++) {
3653 		snprintf(name, 256, "%d", p);
3654 
3655 		debugfs_create_file(name, 0400, dentry,
3656 				    &hisi_hba->debugfs_port_reg[dump_index][p],
3657 				    &debugfs_port_v3_hw_fops);
3658 	}
3659 
3660 	/* Create CQ dir and files */
3661 	dentry = debugfs_create_dir("cq", dump_dentry);
3662 	for (c = 0; c < hisi_hba->queue_count; c++) {
3663 		snprintf(name, 256, "%d", c);
3664 
3665 		debugfs_create_file(name, 0400, dentry,
3666 				    &hisi_hba->debugfs_cq[dump_index][c],
3667 				    &debugfs_cq_v3_hw_fops);
3668 	}
3669 
3670 	/* Create DQ dir and files */
3671 	dentry = debugfs_create_dir("dq", dump_dentry);
3672 	for (d = 0; d < hisi_hba->queue_count; d++) {
3673 		snprintf(name, 256, "%d", d);
3674 
3675 		debugfs_create_file(name, 0400, dentry,
3676 				    &hisi_hba->debugfs_dq[dump_index][d],
3677 				    &debugfs_dq_v3_hw_fops);
3678 	}
3679 
3680 	debugfs_create_file("iost", 0400, dump_dentry,
3681 			    &hisi_hba->debugfs_iost[dump_index],
3682 			    &debugfs_iost_v3_hw_fops);
3683 
3684 	debugfs_create_file("iost_cache", 0400, dump_dentry,
3685 			    &hisi_hba->debugfs_iost_cache[dump_index],
3686 			    &debugfs_iost_cache_v3_hw_fops);
3687 
3688 	debugfs_create_file("itct", 0400, dump_dentry,
3689 			    &hisi_hba->debugfs_itct[dump_index],
3690 			    &debugfs_itct_v3_hw_fops);
3691 
3692 	debugfs_create_file("itct_cache", 0400, dump_dentry,
3693 			    &hisi_hba->debugfs_itct_cache[dump_index],
3694 			    &debugfs_itct_cache_v3_hw_fops);
3695 
3696 	debugfs_create_file("axi", 0400, dump_dentry,
3697 			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
3698 			    &debugfs_axi_v3_hw_fops);
3699 
3700 	debugfs_create_file("ras", 0400, dump_dentry,
3701 			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
3702 			    &debugfs_ras_v3_hw_fops);
3703 }
3704 
3705 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
3706 {
3707 	int debugfs_dump_index = hisi_hba->debugfs_dump_index;
3708 	struct device *dev = hisi_hba->dev;
3709 	u64 timestamp = local_clock();
3710 
3711 	if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
3712 		dev_warn(dev, "dump count exceeded!\n");
3713 		return;
3714 	}
3715 
3716 	do_div(timestamp, NSEC_PER_MSEC);
3717 	hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
3718 
3719 	debugfs_snapshot_prepare_v3_hw(hisi_hba);
3720 
3721 	debugfs_snapshot_global_reg_v3_hw(hisi_hba);
3722 	debugfs_snapshot_port_reg_v3_hw(hisi_hba);
3723 	debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
3724 	debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
3725 	debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
3726 	debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
3727 	debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
3728 	debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
3729 
3730 	debugfs_create_files_v3_hw(hisi_hba);
3731 
3732 	debugfs_snapshot_restore_v3_hw(hisi_hba);
3733 	hisi_hba->debugfs_dump_index++;
3734 }
3735 
3736 static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3737 						const char __user *user_buf,
3738 						size_t count, loff_t *ppos)
3739 {
3740 	struct hisi_hba *hisi_hba = file->f_inode->i_private;
3741 	char buf[8];
3742 
3743 	if (hisi_hba->debugfs_dump_index >= hisi_sas_debugfs_dump_count)
3744 		return -EFAULT;
3745 
3746 	if (count > 8)
3747 		return -EFAULT;
3748 
3749 	if (copy_from_user(buf, user_buf, count))
3750 		return -EFAULT;
3751 
3752 	if (buf[0] != '1')
3753 		return -EFAULT;
3754 
3755 	queue_work(hisi_hba->wq, &hisi_hba->debugfs_work);
3756 
3757 	return count;
3758 }
3759 
3760 static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
3761 	.write = &debugfs_trigger_dump_v3_hw_write,
3762 	.owner = THIS_MODULE,
3763 };
3764 
3765 enum {
3766 	HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
3767 	HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
3768 	HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
3769 };
3770 
3771 static const struct {
3772 	int		value;
3773 	char		*name;
3774 } debugfs_loop_linkrate_v3_hw[] = {
3775 	{ SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
3776 	{ SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
3777 	{ SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
3778 	{ SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
3779 };
3780 
3781 static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
3782 {
3783 	struct hisi_hba *hisi_hba = s->private;
3784 	int i;
3785 
3786 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3787 		int match = (hisi_hba->debugfs_bist_linkrate ==
3788 			     debugfs_loop_linkrate_v3_hw[i].value);
3789 
3790 		seq_printf(s, "%s%s%s ", match ? "[" : "",
3791 			   debugfs_loop_linkrate_v3_hw[i].name,
3792 			   match ? "]" : "");
3793 	}
3794 	seq_puts(s, "\n");
3795 
3796 	return 0;
3797 }
3798 
3799 static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
3800 						 const char __user *buf,
3801 						 size_t count, loff_t *ppos)
3802 {
3803 	struct seq_file *m = filp->private_data;
3804 	struct hisi_hba *hisi_hba = m->private;
3805 	char kbuf[16] = {}, *pkbuf;
3806 	bool found = false;
3807 	int i;
3808 
3809 	if (hisi_hba->debugfs_bist_enable)
3810 		return -EPERM;
3811 
3812 	if (count >= sizeof(kbuf))
3813 		return -EOVERFLOW;
3814 
3815 	if (copy_from_user(kbuf, buf, count))
3816 		return -EINVAL;
3817 
3818 	pkbuf = strstrip(kbuf);
3819 
3820 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3821 		if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
3822 			     pkbuf, 16)) {
3823 			hisi_hba->debugfs_bist_linkrate =
3824 				debugfs_loop_linkrate_v3_hw[i].value;
3825 			found = true;
3826 			break;
3827 		}
3828 	}
3829 
3830 	if (!found)
3831 		return -EINVAL;
3832 
3833 	return count;
3834 }
3835 
3836 static int debugfs_bist_linkrate_v3_hw_open(struct inode *inode,
3837 					    struct file *filp)
3838 {
3839 	return single_open(filp, debugfs_bist_linkrate_v3_hw_show,
3840 			   inode->i_private);
3841 }
3842 
3843 static const struct file_operations debugfs_bist_linkrate_v3_hw_fops = {
3844 	.open = debugfs_bist_linkrate_v3_hw_open,
3845 	.read = seq_read,
3846 	.write = debugfs_bist_linkrate_v3_hw_write,
3847 	.llseek = seq_lseek,
3848 	.release = single_release,
3849 	.owner = THIS_MODULE,
3850 };
3851 
3852 static const struct {
3853 	int		value;
3854 	char		*name;
3855 } debugfs_loop_code_mode_v3_hw[] = {
3856 	{ HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
3857 	{ HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
3858 	{ HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
3859 	{ HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
3860 	{ HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
3861 	{ HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
3862 	{ HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
3863 	{ HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
3864 	{ HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
3865 	{ HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
3866 	{ HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
3867 	{ HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
3868 };
3869 
3870 static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
3871 {
3872 	struct hisi_hba *hisi_hba = s->private;
3873 	int i;
3874 
3875 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3876 		int match = (hisi_hba->debugfs_bist_code_mode ==
3877 			     debugfs_loop_code_mode_v3_hw[i].value);
3878 
3879 		seq_printf(s, "%s%s%s ", match ? "[" : "",
3880 			   debugfs_loop_code_mode_v3_hw[i].name,
3881 			   match ? "]" : "");
3882 	}
3883 	seq_puts(s, "\n");
3884 
3885 	return 0;
3886 }
3887 
3888 static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
3889 						  const char __user *buf,
3890 						  size_t count,
3891 						  loff_t *ppos)
3892 {
3893 	struct seq_file *m = filp->private_data;
3894 	struct hisi_hba *hisi_hba = m->private;
3895 	char kbuf[16] = {}, *pkbuf;
3896 	bool found = false;
3897 	int i;
3898 
3899 	if (hisi_hba->debugfs_bist_enable)
3900 		return -EPERM;
3901 
3902 	if (count >= sizeof(kbuf))
3903 		return -EINVAL;
3904 
3905 	if (copy_from_user(kbuf, buf, count))
3906 		return -EOVERFLOW;
3907 
3908 	pkbuf = strstrip(kbuf);
3909 
3910 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
3911 		if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
3912 			     pkbuf, 16)) {
3913 			hisi_hba->debugfs_bist_code_mode =
3914 				debugfs_loop_code_mode_v3_hw[i].value;
3915 			found = true;
3916 			break;
3917 		}
3918 	}
3919 
3920 	if (!found)
3921 		return -EINVAL;
3922 
3923 	return count;
3924 }
3925 
3926 static int debugfs_bist_code_mode_v3_hw_open(struct inode *inode,
3927 					     struct file *filp)
3928 {
3929 	return single_open(filp, debugfs_bist_code_mode_v3_hw_show,
3930 			   inode->i_private);
3931 }
3932 
3933 static const struct file_operations debugfs_bist_code_mode_v3_hw_fops = {
3934 	.open = debugfs_bist_code_mode_v3_hw_open,
3935 	.read = seq_read,
3936 	.write = debugfs_bist_code_mode_v3_hw_write,
3937 	.llseek = seq_lseek,
3938 	.release = single_release,
3939 	.owner = THIS_MODULE,
3940 };
3941 
3942 static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
3943 					    const char __user *buf,
3944 					    size_t count, loff_t *ppos)
3945 {
3946 	struct seq_file *m = filp->private_data;
3947 	struct hisi_hba *hisi_hba = m->private;
3948 	unsigned int phy_no;
3949 	int val;
3950 
3951 	if (hisi_hba->debugfs_bist_enable)
3952 		return -EPERM;
3953 
3954 	val = kstrtouint_from_user(buf, count, 0, &phy_no);
3955 	if (val)
3956 		return val;
3957 
3958 	if (phy_no >= hisi_hba->n_phy)
3959 		return -EINVAL;
3960 
3961 	hisi_hba->debugfs_bist_phy_no = phy_no;
3962 
3963 	return count;
3964 }
3965 
3966 static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
3967 {
3968 	struct hisi_hba *hisi_hba = s->private;
3969 
3970 	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);
3971 
3972 	return 0;
3973 }
3974 
3975 static int debugfs_bist_phy_v3_hw_open(struct inode *inode,
3976 				       struct file *filp)
3977 {
3978 	return single_open(filp, debugfs_bist_phy_v3_hw_show,
3979 			   inode->i_private);
3980 }
3981 
3982 static const struct file_operations debugfs_bist_phy_v3_hw_fops = {
3983 	.open = debugfs_bist_phy_v3_hw_open,
3984 	.read = seq_read,
3985 	.write = debugfs_bist_phy_v3_hw_write,
3986 	.llseek = seq_lseek,
3987 	.release = single_release,
3988 	.owner = THIS_MODULE,
3989 };
3990 
3991 static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
3992 					const char __user *buf,
3993 					size_t count, loff_t *ppos)
3994 {
3995 	struct seq_file *m = filp->private_data;
3996 	struct hisi_hba *hisi_hba = m->private;
3997 	unsigned int cnt;
3998 	int val;
3999 
4000 	if (hisi_hba->debugfs_bist_enable)
4001 		return -EPERM;
4002 
4003 	val = kstrtouint_from_user(buf, count, 0, &cnt);
4004 	if (val)
4005 		return val;
4006 
4007 	if (cnt)
4008 		return -EINVAL;
4009 
4010 	hisi_hba->debugfs_bist_cnt = 0;
4011 	return count;
4012 }
4013 
4014 static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
4015 {
4016 	struct hisi_hba *hisi_hba = s->private;
4017 
4018 	seq_printf(s, "%u\n", hisi_hba->debugfs_bist_cnt);
4019 
4020 	return 0;
4021 }
4022 
4023 static int debugfs_bist_cnt_v3_hw_open(struct inode *inode,
4024 					  struct file *filp)
4025 {
4026 	return single_open(filp, debugfs_bist_cnt_v3_hw_show,
4027 			   inode->i_private);
4028 }
4029 
4030 static const struct file_operations debugfs_bist_cnt_v3_hw_ops = {
4031 	.open = debugfs_bist_cnt_v3_hw_open,
4032 	.read = seq_read,
4033 	.write = debugfs_bist_cnt_v3_hw_write,
4034 	.llseek = seq_lseek,
4035 	.release = single_release,
4036 	.owner = THIS_MODULE,
4037 };
4038 
4039 static const struct {
4040 	int		value;
4041 	char		*name;
4042 } debugfs_loop_modes_v3_hw[] = {
4043 	{ HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
4044 	{ HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
4045 	{ HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
4046 };
4047 
4048 static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
4049 {
4050 	struct hisi_hba *hisi_hba = s->private;
4051 	int i;
4052 
4053 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4054 		int match = (hisi_hba->debugfs_bist_mode ==
4055 			     debugfs_loop_modes_v3_hw[i].value);
4056 
4057 		seq_printf(s, "%s%s%s ", match ? "[" : "",
4058 			   debugfs_loop_modes_v3_hw[i].name,
4059 			   match ? "]" : "");
4060 	}
4061 	seq_puts(s, "\n");
4062 
4063 	return 0;
4064 }
4065 
4066 static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
4067 					     const char __user *buf,
4068 					     size_t count, loff_t *ppos)
4069 {
4070 	struct seq_file *m = filp->private_data;
4071 	struct hisi_hba *hisi_hba = m->private;
4072 	char kbuf[16] = {}, *pkbuf;
4073 	bool found = false;
4074 	int i;
4075 
4076 	if (hisi_hba->debugfs_bist_enable)
4077 		return -EPERM;
4078 
4079 	if (count >= sizeof(kbuf))
4080 		return -EINVAL;
4081 
4082 	if (copy_from_user(kbuf, buf, count))
4083 		return -EOVERFLOW;
4084 
4085 	pkbuf = strstrip(kbuf);
4086 
4087 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4088 		if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
4089 			hisi_hba->debugfs_bist_mode =
4090 				debugfs_loop_modes_v3_hw[i].value;
4091 			found = true;
4092 			break;
4093 		}
4094 	}
4095 
4096 	if (!found)
4097 		return -EINVAL;
4098 
4099 	return count;
4100 }
4101 
4102 static int debugfs_bist_mode_v3_hw_open(struct inode *inode,
4103 					struct file *filp)
4104 {
4105 	return single_open(filp, debugfs_bist_mode_v3_hw_show,
4106 			   inode->i_private);
4107 }
4108 
4109 static const struct file_operations debugfs_bist_mode_v3_hw_fops = {
4110 	.open = debugfs_bist_mode_v3_hw_open,
4111 	.read = seq_read,
4112 	.write = debugfs_bist_mode_v3_hw_write,
4113 	.llseek = seq_lseek,
4114 	.release = single_release,
4115 	.owner = THIS_MODULE,
4116 };
4117 
4118 static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4119 					       const char __user *buf,
4120 					       size_t count, loff_t *ppos)
4121 {
4122 	struct seq_file *m = filp->private_data;
4123 	struct hisi_hba *hisi_hba = m->private;
4124 	unsigned int enable;
4125 	int val;
4126 
4127 	val = kstrtouint_from_user(buf, count, 0, &enable);
4128 	if (val)
4129 		return val;
4130 
4131 	if (enable > 1)
4132 		return -EINVAL;
4133 
4134 	if (enable == hisi_hba->debugfs_bist_enable)
4135 		return count;
4136 
4137 	val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4138 	if (val < 0)
4139 		return val;
4140 
4141 	hisi_hba->debugfs_bist_enable = enable;
4142 
4143 	return count;
4144 }
4145 
4146 static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4147 {
4148 	struct hisi_hba *hisi_hba = s->private;
4149 
4150 	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);
4151 
4152 	return 0;
4153 }
4154 
4155 static int debugfs_bist_enable_v3_hw_open(struct inode *inode,
4156 					  struct file *filp)
4157 {
4158 	return single_open(filp, debugfs_bist_enable_v3_hw_show,
4159 			   inode->i_private);
4160 }
4161 
4162 static const struct file_operations debugfs_bist_enable_v3_hw_fops = {
4163 	.open = debugfs_bist_enable_v3_hw_open,
4164 	.read = seq_read,
4165 	.write = debugfs_bist_enable_v3_hw_write,
4166 	.llseek = seq_lseek,
4167 	.release = single_release,
4168 	.owner = THIS_MODULE,
4169 };
4170 
4171 static const struct {
4172 	char *name;
4173 } debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4174 	{ "SAS_1_5_GBPS" },
4175 	{ "SAS_3_0_GBPS" },
4176 	{ "SAS_6_0_GBPS" },
4177 	{ "SAS_12_0_GBPS" },
4178 	{ "FFE_RESV" },
4179 	{ "SATA_1_5_GBPS" },
4180 	{ "SATA_3_0_GBPS" },
4181 	{ "SATA_6_0_GBPS" },
4182 };
4183 
4184 static ssize_t debugfs_v3_hw_write(struct file *filp,
4185 				   const char __user *buf,
4186 				   size_t count, loff_t *ppos)
4187 {
4188 	struct seq_file *m = filp->private_data;
4189 	u32 *val = m->private;
4190 	int res;
4191 
4192 	res = kstrtouint_from_user(buf, count, 0, val);
4193 	if (res)
4194 		return res;
4195 
4196 	return count;
4197 }
4198 
4199 static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4200 {
4201 	u32 *val = s->private;
4202 
4203 	seq_printf(s, "0x%x\n", *val);
4204 
4205 	return 0;
4206 }
4207 
4208 static int debugfs_v3_hw_open(struct inode *inode, struct file *filp)
4209 {
4210 	return single_open(filp, debugfs_v3_hw_show,
4211 			   inode->i_private);
4212 }
4213 
4214 static const struct file_operations debugfs_v3_hw_fops = {
4215 	.open = debugfs_v3_hw_open,
4216 	.read = seq_read,
4217 	.write = debugfs_v3_hw_write,
4218 	.llseek = seq_lseek,
4219 	.release = single_release,
4220 	.owner = THIS_MODULE,
4221 };
4222 
4223 static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4224 						const char __user *buf,
4225 						size_t count, loff_t *ppos)
4226 {
4227 	struct seq_file *s = filp->private_data;
4228 	struct hisi_sas_phy *phy = s->private;
4229 	unsigned int set_val;
4230 	int res;
4231 
4232 	res = kstrtouint_from_user(buf, count, 0, &set_val);
4233 	if (res)
4234 		return res;
4235 
4236 	if (set_val > 0)
4237 		return -EINVAL;
4238 
4239 	atomic_set(&phy->down_cnt, 0);
4240 
4241 	return count;
4242 }
4243 
4244 static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4245 {
4246 	struct hisi_sas_phy *phy = s->private;
4247 
4248 	seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));
4249 
4250 	return 0;
4251 }
4252 
4253 static int debugfs_phy_down_cnt_v3_hw_open(struct inode *inode,
4254 					   struct file *filp)
4255 {
4256 	return single_open(filp, debugfs_phy_down_cnt_v3_hw_show,
4257 			   inode->i_private);
4258 }
4259 
4260 static const struct file_operations debugfs_phy_down_cnt_v3_hw_fops = {
4261 	.open = debugfs_phy_down_cnt_v3_hw_open,
4262 	.read = seq_read,
4263 	.write = debugfs_phy_down_cnt_v3_hw_write,
4264 	.llseek = seq_lseek,
4265 	.release = single_release,
4266 	.owner = THIS_MODULE,
4267 };
4268 
4269 enum fifo_dump_mode_v3_hw {
4270 	FIFO_DUMP_FORVER =		(1U << 0),
4271 	FIFO_DUMP_AFTER_TRIGGER =	(1U << 1),
4272 	FIFO_DUMP_UNTILL_TRIGGER =	(1U << 2),
4273 };
4274 
4275 enum fifo_trigger_mode_v3_hw {
4276 	FIFO_TRIGGER_EDGE =		(1U << 0),
4277 	FIFO_TRIGGER_SAME_LEVEL =	(1U << 1),
4278 	FIFO_TRIGGER_DIFF_LEVEL =	(1U << 2),
4279 };
4280 
4281 static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4282 {
4283 	struct hisi_hba *hisi_hba = phy->hisi_hba;
4284 
4285 	if (phy->fifo.signal_sel > 0xf) {
4286 		dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4287 			 phy->fifo.signal_sel);
4288 		return -EINVAL;
4289 	}
4290 
4291 	switch (phy->fifo.dump_mode) {
4292 	case FIFO_DUMP_FORVER:
4293 	case FIFO_DUMP_AFTER_TRIGGER:
4294 	case FIFO_DUMP_UNTILL_TRIGGER:
4295 		break;
4296 	default:
4297 		dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4298 			 phy->fifo.dump_mode);
4299 		return -EINVAL;
4300 	}
4301 
4302 	/* when FIFO_DUMP_FORVER, no need to check trigger_mode */
4303 	if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4304 		return 0;
4305 
4306 	switch (phy->fifo.trigger_mode) {
4307 	case FIFO_TRIGGER_EDGE:
4308 	case FIFO_TRIGGER_SAME_LEVEL:
4309 	case FIFO_TRIGGER_DIFF_LEVEL:
4310 		break;
4311 	default:
4312 		dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4313 			 phy->fifo.trigger_mode);
4314 		return -EINVAL;
4315 	}
4316 	return 0;
4317 }
4318 
4319 static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4320 {
4321 	u32 trigger_mode = phy->fifo.trigger_mode;
4322 	u32 signal_sel = phy->fifo.signal_sel;
4323 	u32 dump_mode = phy->fifo.dump_mode;
4324 	struct hisi_hba *hisi_hba = phy->hisi_hba;
4325 	int phy_no = phy->sas_phy.id;
4326 	u32 reg_val;
4327 	int res;
4328 
4329 	/* Check the validity of trace FIFO configuration */
4330 	res = debugfs_is_fifo_config_valid_v3_hw(phy);
4331 	if (res)
4332 		return res;
4333 
4334 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4335 	/* Disable trace FIFO before update configuration */
4336 	reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4337 
4338 	/* Update trace FIFO configuration */
4339 	reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4340 		     DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4341 		     DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4342 
4343 	reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4344 		    (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4345 		    (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4346 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4347 
4348 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4349 			     phy->fifo.dump_msk);
4350 
4351 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4352 			     phy->fifo.trigger);
4353 
4354 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4355 			     phy->fifo.trigger_msk);
4356 
4357 	/* Enable trace FIFO after updated configuration */
4358 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4359 	reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4360 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4361 
4362 	return 0;
4363 }
4364 
4365 static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4366 						   const char __user *buf,
4367 						   size_t count, loff_t *ppos)
4368 {
4369 	struct hisi_sas_phy *phy = filp->private_data;
4370 	bool update;
4371 	int val;
4372 
4373 	val = kstrtobool_from_user(buf, count, &update);
4374 	if (val)
4375 		return val;
4376 
4377 	if (update != 1)
4378 		return -EINVAL;
4379 
4380 	val = debugfs_update_fifo_config_v3_hw(phy);
4381 	if (val)
4382 		return val;
4383 
4384 	return count;
4385 }
4386 
4387 static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4388 	.open = simple_open,
4389 	.write = debugfs_fifo_update_cfg_v3_hw_write,
4390 	.owner = THIS_MODULE,
4391 };
4392 
4393 static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4394 {
4395 	struct hisi_hba *hisi_hba = phy->hisi_hba;
4396 	u32 *buf = phy->fifo.rd_data;
4397 	int phy_no = phy->sas_phy.id;
4398 	u32 val;
4399 	int i;
4400 
4401 	memset(buf, 0, sizeof(phy->fifo.rd_data));
4402 
4403 	/* Disable trace FIFO before read data */
4404 	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4405 	val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4406 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4407 
4408 	for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4409 		val = hisi_sas_phy_read32(hisi_hba, phy_no,
4410 					  DFX_FIFO_RD_DATA);
4411 		buf[i] = val;
4412 	}
4413 
4414 	/* Enable trace FIFO after read data */
4415 	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4416 	val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4417 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4418 }
4419 
4420 static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4421 {
4422 	struct hisi_sas_phy *phy = s->private;
4423 
4424 	debugfs_read_fifo_data_v3_hw(phy);
4425 
4426 	debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
4427 				  phy->fifo.rd_data);
4428 
4429 	return 0;
4430 }
4431 DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4432 
4433 static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4434 {
4435 	int phy_no;
4436 
4437 	hisi_hba->debugfs_fifo_dentry =
4438 			debugfs_create_dir("fifo", hisi_hba->debugfs_dir);
4439 
4440 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4441 		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4442 		struct dentry *port_dentry;
4443 		char name[256];
4444 		u32 val;
4445 
4446 		/* get default configuration for trace FIFO */
4447 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4448 		val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4449 		val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4450 		phy->fifo.dump_mode = val;
4451 
4452 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4453 		val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4454 		val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4455 		phy->fifo.trigger_mode = val;
4456 
4457 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4458 		val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4459 		val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4460 		phy->fifo.signal_sel = val;
4461 
4462 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4463 		phy->fifo.dump_msk = val;
4464 
4465 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4466 		phy->fifo.trigger = val;
4467 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4468 		phy->fifo.trigger_msk = val;
4469 
4470 		snprintf(name, 256, "%d", phy_no);
4471 		port_dentry = debugfs_create_dir(name,
4472 						 hisi_hba->debugfs_fifo_dentry);
4473 
4474 		debugfs_create_file("update_config", 0200, port_dentry, phy,
4475 				    &debugfs_fifo_update_cfg_v3_hw_fops);
4476 
4477 		debugfs_create_file("signal_sel", 0600, port_dentry,
4478 				    &phy->fifo.signal_sel,
4479 				    &debugfs_v3_hw_fops);
4480 
4481 		debugfs_create_file("dump_msk", 0600, port_dentry,
4482 				    &phy->fifo.dump_msk,
4483 				    &debugfs_v3_hw_fops);
4484 
4485 		debugfs_create_file("dump_mode", 0600, port_dentry,
4486 				    &phy->fifo.dump_mode,
4487 				    &debugfs_v3_hw_fops);
4488 
4489 		debugfs_create_file("trigger_mode", 0600, port_dentry,
4490 				    &phy->fifo.trigger_mode,
4491 				    &debugfs_v3_hw_fops);
4492 
4493 		debugfs_create_file("trigger", 0600, port_dentry,
4494 				    &phy->fifo.trigger,
4495 				    &debugfs_v3_hw_fops);
4496 
4497 		debugfs_create_file("trigger_msk", 0600, port_dentry,
4498 				    &phy->fifo.trigger_msk,
4499 				    &debugfs_v3_hw_fops);
4500 
4501 		debugfs_create_file("fifo_data", 0400, port_dentry, phy,
4502 				    &debugfs_fifo_data_v3_hw_fops);
4503 	}
4504 }
4505 
4506 static void debugfs_work_handler_v3_hw(struct work_struct *work)
4507 {
4508 	struct hisi_hba *hisi_hba =
4509 		container_of(work, struct hisi_hba, debugfs_work);
4510 
4511 	debugfs_snapshot_regs_v3_hw(hisi_hba);
4512 }
4513 
4514 static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4515 {
4516 	struct device *dev = hisi_hba->dev;
4517 	int i;
4518 
4519 	devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
4520 	devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
4521 	devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
4522 	devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);
4523 
4524 	for (i = 0; i < hisi_hba->queue_count; i++)
4525 		devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);
4526 
4527 	for (i = 0; i < hisi_hba->queue_count; i++)
4528 		devm_kfree(dev,
4529 			   hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4530 
4531 	for (i = 0; i < DEBUGFS_REGS_NUM; i++)
4532 		devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);
4533 
4534 	for (i = 0; i < hisi_hba->n_phy; i++)
4535 		devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
4536 }
4537 
4538 static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4539 	[DEBUGFS_GLOBAL] = &debugfs_global_reg,
4540 	[DEBUGFS_AXI] = &debugfs_axi_reg,
4541 	[DEBUGFS_RAS] = &debugfs_ras_reg,
4542 };
4543 
4544 static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4545 {
4546 	const struct hisi_sas_hw *hw = hisi_hba->hw;
4547 	struct device *dev = hisi_hba->dev;
4548 	int p, c, d, r, i;
4549 	size_t sz;
4550 
4551 	for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4552 		struct hisi_sas_debugfs_regs *regs =
4553 				&hisi_hba->debugfs_regs[dump_index][r];
4554 
4555 		sz = debugfs_reg_array_v3_hw[r]->count * 4;
4556 		regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4557 		if (!regs->data)
4558 			goto fail;
4559 		regs->hisi_hba = hisi_hba;
4560 	}
4561 
4562 	sz = debugfs_port_reg.count * 4;
4563 	for (p = 0; p < hisi_hba->n_phy; p++) {
4564 		struct hisi_sas_debugfs_port *port =
4565 				&hisi_hba->debugfs_port_reg[dump_index][p];
4566 
4567 		port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4568 		if (!port->data)
4569 			goto fail;
4570 		port->phy = &hisi_hba->phy[p];
4571 	}
4572 
4573 	sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4574 	for (c = 0; c < hisi_hba->queue_count; c++) {
4575 		struct hisi_sas_debugfs_cq *cq =
4576 				&hisi_hba->debugfs_cq[dump_index][c];
4577 
4578 		cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4579 		if (!cq->complete_hdr)
4580 			goto fail;
4581 		cq->cq = &hisi_hba->cq[c];
4582 	}
4583 
4584 	sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4585 	for (d = 0; d < hisi_hba->queue_count; d++) {
4586 		struct hisi_sas_debugfs_dq *dq =
4587 				&hisi_hba->debugfs_dq[dump_index][d];
4588 
4589 		dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4590 		if (!dq->hdr)
4591 			goto fail;
4592 		dq->dq = &hisi_hba->dq[d];
4593 	}
4594 
4595 	sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4596 
4597 	hisi_hba->debugfs_iost[dump_index].iost =
4598 				devm_kmalloc(dev, sz, GFP_KERNEL);
4599 	if (!hisi_hba->debugfs_iost[dump_index].iost)
4600 		goto fail;
4601 
4602 	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4603 	     sizeof(struct hisi_sas_iost_itct_cache);
4604 
4605 	hisi_hba->debugfs_iost_cache[dump_index].cache =
4606 				devm_kmalloc(dev, sz, GFP_KERNEL);
4607 	if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4608 		goto fail;
4609 
4610 	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4611 	     sizeof(struct hisi_sas_iost_itct_cache);
4612 
4613 	hisi_hba->debugfs_itct_cache[dump_index].cache =
4614 				devm_kmalloc(dev, sz, GFP_KERNEL);
4615 	if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4616 		goto fail;
4617 
4618 	/* New memory allocation must be locate before itct */
4619 	sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4620 
4621 	hisi_hba->debugfs_itct[dump_index].itct =
4622 				devm_kmalloc(dev, sz, GFP_KERNEL);
4623 	if (!hisi_hba->debugfs_itct[dump_index].itct)
4624 		goto fail;
4625 
4626 	return 0;
4627 fail:
4628 	for (i = 0; i < hisi_sas_debugfs_dump_count; i++)
4629 		debugfs_release_v3_hw(hisi_hba, i);
4630 	return -ENOMEM;
4631 }
4632 
4633 static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4634 {
4635 	struct dentry *dir = debugfs_create_dir("phy_down_cnt",
4636 						hisi_hba->debugfs_dir);
4637 	char name[16];
4638 	int phy_no;
4639 
4640 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4641 		snprintf(name, 16, "%d", phy_no);
4642 		debugfs_create_file(name, 0600, dir,
4643 				    &hisi_hba->phy[phy_no],
4644 				    &debugfs_phy_down_cnt_v3_hw_fops);
4645 	}
4646 }
4647 
4648 static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4649 {
4650 	struct dentry *ports_dentry;
4651 	int phy_no;
4652 
4653 	hisi_hba->debugfs_bist_dentry =
4654 			debugfs_create_dir("bist", hisi_hba->debugfs_dir);
4655 	debugfs_create_file("link_rate", 0600,
4656 			    hisi_hba->debugfs_bist_dentry, hisi_hba,
4657 			    &debugfs_bist_linkrate_v3_hw_fops);
4658 
4659 	debugfs_create_file("code_mode", 0600,
4660 			    hisi_hba->debugfs_bist_dentry, hisi_hba,
4661 			    &debugfs_bist_code_mode_v3_hw_fops);
4662 
4663 	debugfs_create_file("fixed_code", 0600,
4664 			    hisi_hba->debugfs_bist_dentry,
4665 			    &hisi_hba->debugfs_bist_fixed_code[0],
4666 			    &debugfs_v3_hw_fops);
4667 
4668 	debugfs_create_file("fixed_code_1", 0600,
4669 			    hisi_hba->debugfs_bist_dentry,
4670 			    &hisi_hba->debugfs_bist_fixed_code[1],
4671 			    &debugfs_v3_hw_fops);
4672 
4673 	debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
4674 			    hisi_hba, &debugfs_bist_phy_v3_hw_fops);
4675 
4676 	debugfs_create_file("cnt", 0600, hisi_hba->debugfs_bist_dentry,
4677 			    hisi_hba, &debugfs_bist_cnt_v3_hw_ops);
4678 
4679 	debugfs_create_file("loopback_mode", 0600,
4680 			    hisi_hba->debugfs_bist_dentry,
4681 			    hisi_hba, &debugfs_bist_mode_v3_hw_fops);
4682 
4683 	debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
4684 			    hisi_hba, &debugfs_bist_enable_v3_hw_fops);
4685 
4686 	ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);
4687 
4688 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4689 		struct dentry *port_dentry;
4690 		struct dentry *ffe_dentry;
4691 		char name[256];
4692 		int i;
4693 
4694 		snprintf(name, 256, "%d", phy_no);
4695 		port_dentry = debugfs_create_dir(name, ports_dentry);
4696 		ffe_dentry = debugfs_create_dir("ffe", port_dentry);
4697 		for (i = 0; i < FFE_CFG_MAX; i++) {
4698 			if (i == FFE_RESV)
4699 				continue;
4700 			debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
4701 					    0600, ffe_dentry,
4702 					    &hisi_hba->debugfs_bist_ffe[phy_no][i],
4703 					    &debugfs_v3_hw_fops);
4704 		}
4705 	}
4706 
4707 	hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4708 }
4709 
4710 static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4711 {
4712 	struct device *dev = hisi_hba->dev;
4713 	int i;
4714 
4715 	hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
4716 						   hisi_sas_debugfs_dir);
4717 	debugfs_create_file("trigger_dump", 0200,
4718 			    hisi_hba->debugfs_dir,
4719 			    hisi_hba,
4720 			    &debugfs_trigger_dump_v3_hw_fops);
4721 
4722 	/* create bist structures */
4723 	debugfs_bist_init_v3_hw(hisi_hba);
4724 
4725 	hisi_hba->debugfs_dump_dentry =
4726 			debugfs_create_dir("dump", hisi_hba->debugfs_dir);
4727 
4728 	debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4729 	debugfs_fifo_init_v3_hw(hisi_hba);
4730 
4731 	for (i = 0; i < hisi_sas_debugfs_dump_count; i++) {
4732 		if (debugfs_alloc_v3_hw(hisi_hba, i)) {
4733 			debugfs_remove_recursive(hisi_hba->debugfs_dir);
4734 			dev_dbg(dev, "failed to init debugfs!\n");
4735 			break;
4736 		}
4737 	}
4738 }
4739 
4740 static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4741 {
4742 	debugfs_remove_recursive(hisi_hba->debugfs_dir);
4743 }
4744 
4745 static int
4746 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4747 {
4748 	struct Scsi_Host *shost;
4749 	struct hisi_hba *hisi_hba;
4750 	struct device *dev = &pdev->dev;
4751 	struct asd_sas_phy **arr_phy;
4752 	struct asd_sas_port **arr_port;
4753 	struct sas_ha_struct *sha;
4754 	int rc, phy_nr, port_nr, i;
4755 
4756 	rc = pcim_enable_device(pdev);
4757 	if (rc)
4758 		goto err_out;
4759 
4760 	pci_set_master(pdev);
4761 
4762 	rc = pcim_iomap_regions(pdev, 1 << BAR_NO_V3_HW, DRV_NAME);
4763 	if (rc)
4764 		goto err_out;
4765 
4766 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4767 	if (rc) {
4768 		dev_err(dev, "No usable DMA addressing method\n");
4769 		rc = -ENODEV;
4770 		goto err_out;
4771 	}
4772 
4773 	shost = hisi_sas_shost_alloc_pci(pdev);
4774 	if (!shost) {
4775 		rc = -ENOMEM;
4776 		goto err_out;
4777 	}
4778 
4779 	sha = SHOST_TO_SAS_HA(shost);
4780 	hisi_hba = shost_priv(shost);
4781 	dev_set_drvdata(dev, sha);
4782 
4783 	hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
4784 	if (!hisi_hba->regs) {
4785 		dev_err(dev, "cannot map register\n");
4786 		rc = -ENOMEM;
4787 		goto err_out_free_host;
4788 	}
4789 
4790 	phy_nr = port_nr = hisi_hba->n_phy;
4791 
4792 	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
4793 	arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
4794 	if (!arr_phy || !arr_port) {
4795 		rc = -ENOMEM;
4796 		goto err_out_free_host;
4797 	}
4798 
4799 	sha->sas_phy = arr_phy;
4800 	sha->sas_port = arr_port;
4801 	sha->core.shost = shost;
4802 	sha->lldd_ha = hisi_hba;
4803 
4804 	shost->transportt = hisi_sas_stt;
4805 	shost->max_id = HISI_SAS_MAX_DEVICES;
4806 	shost->max_lun = ~0;
4807 	shost->max_channel = 1;
4808 	shost->max_cmd_len = 16;
4809 	shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4810 	shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
4811 
4812 	sha->sas_ha_name = DRV_NAME;
4813 	sha->dev = dev;
4814 	sha->lldd_module = THIS_MODULE;
4815 	sha->sas_addr = &hisi_hba->sas_addr[0];
4816 	sha->num_phys = hisi_hba->n_phy;
4817 
4818 	for (i = 0; i < hisi_hba->n_phy; i++) {
4819 		sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
4820 		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
4821 	}
4822 
4823 	if (hisi_hba->prot_mask) {
4824 		dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
4825 			 prot_mask);
4826 		scsi_host_set_prot(hisi_hba->shost, prot_mask);
4827 		if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
4828 			scsi_host_set_guard(hisi_hba->shost,
4829 					    SHOST_DIX_GUARD_CRC);
4830 	}
4831 
4832 	if (hisi_sas_debugfs_enable)
4833 		debugfs_init_v3_hw(hisi_hba);
4834 
4835 	rc = interrupt_preinit_v3_hw(hisi_hba);
4836 	if (rc)
4837 		goto err_out_undo_debugfs;
4838 
4839 	rc = scsi_add_host(shost, dev);
4840 	if (rc)
4841 		goto err_out_undo_debugfs;
4842 
4843 	rc = sas_register_ha(sha);
4844 	if (rc)
4845 		goto err_out_remove_host;
4846 
4847 	rc = hisi_sas_v3_init(hisi_hba);
4848 	if (rc)
4849 		goto err_out_unregister_ha;
4850 
4851 	scsi_scan_host(shost);
4852 
4853 	pm_runtime_set_autosuspend_delay(dev, 5000);
4854 	pm_runtime_use_autosuspend(dev);
4855 	/*
4856 	 * For the situation that there are ATA disks connected with SAS
4857 	 * controller, it additionally creates ata_port which will affect the
4858 	 * child_count of hisi_hba->dev. Even if suspended all the disks,
4859 	 * ata_port is still and the child_count of hisi_hba->dev is not 0.
4860 	 * So use pm_suspend_ignore_children() to ignore the effect to
4861 	 * hisi_hba->dev.
4862 	 */
4863 	pm_suspend_ignore_children(dev, true);
4864 	pm_runtime_put_noidle(&pdev->dev);
4865 
4866 	return 0;
4867 
4868 err_out_unregister_ha:
4869 	sas_unregister_ha(sha);
4870 err_out_remove_host:
4871 	scsi_remove_host(shost);
4872 err_out_undo_debugfs:
4873 	debugfs_exit_v3_hw(hisi_hba);
4874 err_out_free_host:
4875 	hisi_sas_free(hisi_hba);
4876 	scsi_host_put(shost);
4877 err_out:
4878 	return rc;
4879 }
4880 
4881 static void
4882 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
4883 {
4884 	int i;
4885 
4886 	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
4887 	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
4888 	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
4889 	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
4890 		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
4891 		int nr = hisi_sas_intr_conv ? 16 : 16 + i;
4892 
4893 		devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
4894 	}
4895 }
4896 
4897 static void hisi_sas_v3_remove(struct pci_dev *pdev)
4898 {
4899 	struct device *dev = &pdev->dev;
4900 	struct sas_ha_struct *sha = dev_get_drvdata(dev);
4901 	struct hisi_hba *hisi_hba = sha->lldd_ha;
4902 	struct Scsi_Host *shost = sha->core.shost;
4903 
4904 	pm_runtime_get_noresume(dev);
4905 	del_timer_sync(&hisi_hba->timer);
4906 
4907 	sas_unregister_ha(sha);
4908 	flush_workqueue(hisi_hba->wq);
4909 	sas_remove_host(sha->core.shost);
4910 
4911 	hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
4912 	hisi_sas_free(hisi_hba);
4913 	debugfs_exit_v3_hw(hisi_hba);
4914 	scsi_host_put(shost);
4915 }
4916 
4917 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
4918 {
4919 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4920 	struct hisi_hba *hisi_hba = sha->lldd_ha;
4921 	struct device *dev = hisi_hba->dev;
4922 	int rc;
4923 
4924 	dev_info(dev, "FLR prepare\n");
4925 	down(&hisi_hba->sem);
4926 	set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4927 	hisi_sas_controller_reset_prepare(hisi_hba);
4928 
4929 	rc = disable_host_v3_hw(hisi_hba);
4930 	if (rc)
4931 		dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
4932 }
4933 
4934 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
4935 {
4936 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4937 	struct hisi_hba *hisi_hba = sha->lldd_ha;
4938 	struct device *dev = hisi_hba->dev;
4939 	int rc;
4940 
4941 	hisi_sas_init_mem(hisi_hba);
4942 
4943 	rc = hw_init_v3_hw(hisi_hba);
4944 	if (rc) {
4945 		dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
4946 		return;
4947 	}
4948 
4949 	hisi_sas_controller_reset_done(hisi_hba);
4950 	dev_info(dev, "FLR done\n");
4951 }
4952 
4953 enum {
4954 	/* instances of the controller */
4955 	hip08,
4956 };
4957 
4958 static int _suspend_v3_hw(struct device *device)
4959 {
4960 	struct pci_dev *pdev = to_pci_dev(device);
4961 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
4962 	struct hisi_hba *hisi_hba = sha->lldd_ha;
4963 	struct device *dev = hisi_hba->dev;
4964 	struct Scsi_Host *shost = hisi_hba->shost;
4965 	int rc;
4966 
4967 	if (!pdev->pm_cap) {
4968 		dev_err(dev, "PCI PM not supported\n");
4969 		return -ENODEV;
4970 	}
4971 
4972 	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
4973 		return -1;
4974 
4975 	dev_warn(dev, "entering suspend state\n");
4976 
4977 	scsi_block_requests(shost);
4978 	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4979 	flush_workqueue(hisi_hba->wq);
4980 
4981 	rc = disable_host_v3_hw(hisi_hba);
4982 	if (rc) {
4983 		dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
4984 		clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4985 		clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4986 		scsi_unblock_requests(shost);
4987 		return rc;
4988 	}
4989 
4990 	hisi_sas_init_mem(hisi_hba);
4991 
4992 	hisi_sas_release_tasks(hisi_hba);
4993 
4994 	sas_suspend_ha(sha);
4995 
4996 	dev_warn(dev, "end of suspending controller\n");
4997 	return 0;
4998 }
4999 
5000 static int _resume_v3_hw(struct device *device)
5001 {
5002 	struct pci_dev *pdev = to_pci_dev(device);
5003 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5004 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5005 	struct Scsi_Host *shost = hisi_hba->shost;
5006 	struct device *dev = hisi_hba->dev;
5007 	unsigned int rc;
5008 	pci_power_t device_state = pdev->current_state;
5009 
5010 	dev_warn(dev, "resuming from operating state [D%d]\n",
5011 		 device_state);
5012 
5013 	scsi_unblock_requests(shost);
5014 	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5015 
5016 	sas_prep_resume_ha(sha);
5017 	rc = hw_init_v3_hw(hisi_hba);
5018 	if (rc) {
5019 		scsi_remove_host(shost);
5020 		return rc;
5021 	}
5022 	phys_init_v3_hw(hisi_hba);
5023 
5024 	/*
5025 	 * If a directly-attached disk is removed during suspend, a deadlock
5026 	 * may occur, as the PHYE_RESUME_TIMEOUT processing will require the
5027 	 * hisi_hba->device to be active, which can only happen when resume
5028 	 * completes. So don't wait for the HA event workqueue to drain upon
5029 	 * resume.
5030 	 */
5031 	sas_resume_ha_no_sync(sha);
5032 	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5033 
5034 	dev_warn(dev, "end of resuming controller\n");
5035 
5036 	return 0;
5037 }
5038 
5039 static int __maybe_unused suspend_v3_hw(struct device *device)
5040 {
5041 	struct pci_dev *pdev = to_pci_dev(device);
5042 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5043 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5044 	int rc;
5045 
5046 	set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5047 
5048 	rc = _suspend_v3_hw(device);
5049 	if (rc)
5050 		clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5051 
5052 	return rc;
5053 }
5054 
5055 static int __maybe_unused resume_v3_hw(struct device *device)
5056 {
5057 	struct pci_dev *pdev = to_pci_dev(device);
5058 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5059 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5060 	int rc = _resume_v3_hw(device);
5061 
5062 	clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5063 
5064 	return rc;
5065 }
5066 
5067 static const struct pci_device_id sas_v3_pci_table[] = {
5068 	{ PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
5069 	{}
5070 };
5071 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
5072 
5073 static const struct pci_error_handlers hisi_sas_err_handler = {
5074 	.reset_prepare	= hisi_sas_reset_prepare_v3_hw,
5075 	.reset_done	= hisi_sas_reset_done_v3_hw,
5076 };
5077 
5078 static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
5079 			    suspend_v3_hw,
5080 			    resume_v3_hw,
5081 			    NULL);
5082 
5083 static struct pci_driver sas_v3_pci_driver = {
5084 	.name		= DRV_NAME,
5085 	.id_table	= sas_v3_pci_table,
5086 	.probe		= hisi_sas_v3_probe,
5087 	.remove		= hisi_sas_v3_remove,
5088 	.err_handler	= &hisi_sas_err_handler,
5089 	.driver.pm	= &hisi_sas_v3_pm_ops,
5090 };
5091 
5092 module_pci_driver(sas_v3_pci_driver);
5093 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5094 
5095 MODULE_LICENSE("GPL");
5096 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5097 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5098 MODULE_ALIAS("pci:" DRV_NAME);
5099