1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PHY_CFG_PHY_RST_OFF 3 125 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 126 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 127 #define PHY_CTRL (PORT_BASE + 0x14) 128 #define PHY_CTRL_RESET_OFF 0 129 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 130 #define CMD_HDR_PIR_OFF 8 131 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 132 #define SL_CFG (PORT_BASE + 0x84) 133 #define AIP_LIMIT (PORT_BASE + 0x90) 134 #define SL_CONTROL (PORT_BASE + 0x94) 135 #define SL_CONTROL_NOTIFY_EN_OFF 0 136 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 137 #define SL_CTA_OFF 17 138 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 139 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 140 #define RX_BCAST_CHG_OFF 1 141 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 142 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 143 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 144 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 145 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 146 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 147 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 148 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 149 #define TXID_AUTO (PORT_BASE + 0xb8) 150 #define CT3_OFF 1 151 #define CT3_MSK (0x1 << CT3_OFF) 152 #define TX_HARDRST_OFF 2 153 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 154 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 155 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 156 #define STP_LINK_TIMER (PORT_BASE + 0x120) 157 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 158 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 159 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 160 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 161 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 162 #define CHL_INT0 (PORT_BASE + 0x1b4) 163 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 164 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 165 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 166 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 167 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 168 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 169 #define CHL_INT0_NOT_RDY_OFF 4 170 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 171 #define CHL_INT0_PHY_RDY_OFF 5 172 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 173 #define CHL_INT1 (PORT_BASE + 0x1b8) 174 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 175 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 176 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 177 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 178 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 179 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 180 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 181 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 182 #define CHL_INT2 (PORT_BASE + 0x1bc) 183 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 184 #define CHL_INT2_RX_INVLD_DW_OFF 30 185 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 186 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 189 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 190 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 191 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 192 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 193 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 194 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 195 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 196 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 197 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 198 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 199 #define DMA_TX_STATUS_BUSY_OFF 0 200 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 201 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 202 #define DMA_RX_STATUS_BUSY_OFF 0 203 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 204 205 #define COARSETUNE_TIME (PORT_BASE + 0x304) 206 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 207 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 208 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 209 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 210 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 211 212 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 213 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 214 #error Max ITCT exceeded 215 #endif 216 217 #define AXI_MASTER_CFG_BASE (0x5000) 218 #define AM_CTRL_GLOBAL (0x0) 219 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 220 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 221 #define AM_CURR_TRANS_RETURN (0x150) 222 223 #define AM_CFG_MAX_TRANS (0x5010) 224 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 225 #define AXI_CFG (0x5100) 226 #define AM_ROB_ECC_ERR_ADDR (0x510c) 227 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 228 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 229 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 230 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 231 232 /* RAS registers need init */ 233 #define RAS_BASE (0x6000) 234 #define SAS_RAS_INTR0 (RAS_BASE) 235 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 236 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 237 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 238 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 239 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 240 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 241 242 /* HW dma structures */ 243 /* Delivery queue header */ 244 /* dw0 */ 245 #define CMD_HDR_ABORT_FLAG_OFF 0 246 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 247 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 248 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 249 #define CMD_HDR_RESP_REPORT_OFF 5 250 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 251 #define CMD_HDR_TLR_CTRL_OFF 6 252 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 253 #define CMD_HDR_PORT_OFF 18 254 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 255 #define CMD_HDR_PRIORITY_OFF 27 256 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 257 #define CMD_HDR_CMD_OFF 29 258 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 259 /* dw1 */ 260 #define CMD_HDR_UNCON_CMD_OFF 3 261 #define CMD_HDR_DIR_OFF 5 262 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 263 #define CMD_HDR_RESET_OFF 7 264 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 265 #define CMD_HDR_VDTL_OFF 10 266 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 267 #define CMD_HDR_FRAME_TYPE_OFF 11 268 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 269 #define CMD_HDR_DEV_ID_OFF 16 270 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 271 /* dw2 */ 272 #define CMD_HDR_CFL_OFF 0 273 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 274 #define CMD_HDR_NCQ_TAG_OFF 10 275 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 276 #define CMD_HDR_MRFL_OFF 15 277 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 278 #define CMD_HDR_SG_MOD_OFF 24 279 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 280 /* dw3 */ 281 #define CMD_HDR_IPTT_OFF 0 282 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 283 /* dw6 */ 284 #define CMD_HDR_DIF_SGL_LEN_OFF 0 285 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 286 #define CMD_HDR_DATA_SGL_LEN_OFF 16 287 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 288 /* dw7 */ 289 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 290 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 291 #define CMD_HDR_ABORT_IPTT_OFF 16 292 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 293 294 /* Completion header */ 295 /* dw0 */ 296 #define CMPLT_HDR_CMPLT_OFF 0 297 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 298 #define CMPLT_HDR_ERROR_PHASE_OFF 2 299 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 300 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 301 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 302 #define CMPLT_HDR_ERX_OFF 12 303 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 304 #define CMPLT_HDR_ABORT_STAT_OFF 13 305 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 306 /* abort_stat */ 307 #define STAT_IO_NOT_VALID 0x1 308 #define STAT_IO_NO_DEVICE 0x2 309 #define STAT_IO_COMPLETE 0x3 310 #define STAT_IO_ABORTED 0x4 311 /* dw1 */ 312 #define CMPLT_HDR_IPTT_OFF 0 313 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 314 #define CMPLT_HDR_DEV_ID_OFF 16 315 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 316 /* dw3 */ 317 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 318 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 319 320 /* ITCT header */ 321 /* qw0 */ 322 #define ITCT_HDR_DEV_TYPE_OFF 0 323 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 324 #define ITCT_HDR_VALID_OFF 2 325 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 326 #define ITCT_HDR_MCR_OFF 5 327 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 328 #define ITCT_HDR_VLN_OFF 9 329 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 330 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 331 #define ITCT_HDR_AWT_CONTINUE_OFF 25 332 #define ITCT_HDR_PORT_ID_OFF 28 333 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 334 /* qw2 */ 335 #define ITCT_HDR_INLT_OFF 0 336 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 337 #define ITCT_HDR_RTOLT_OFF 48 338 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 339 340 struct hisi_sas_protect_iu_v3_hw { 341 u32 dw0; 342 u32 lbrtcv; 343 u32 lbrtgv; 344 u32 dw3; 345 u32 dw4; 346 u32 dw5; 347 u32 rsv; 348 }; 349 350 struct hisi_sas_complete_v3_hdr { 351 __le32 dw0; 352 __le32 dw1; 353 __le32 act; 354 __le32 dw3; 355 }; 356 357 struct hisi_sas_err_record_v3 { 358 /* dw0 */ 359 __le32 trans_tx_fail_type; 360 361 /* dw1 */ 362 __le32 trans_rx_fail_type; 363 364 /* dw2 */ 365 __le16 dma_tx_err_type; 366 __le16 sipc_rx_err_type; 367 368 /* dw3 */ 369 __le32 dma_rx_err_type; 370 }; 371 372 #define RX_DATA_LEN_UNDERFLOW_OFF 6 373 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 374 375 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 376 #define HISI_SAS_MSI_COUNT_V3_HW 32 377 378 #define DIR_NO_DATA 0 379 #define DIR_TO_INI 1 380 #define DIR_TO_DEVICE 2 381 #define DIR_RESERVED 3 382 383 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 384 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 385 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 386 ((fis.command == ATA_CMD_DEV_RESET) && \ 387 ((fis.control & ATA_SRST) != 0))) 388 389 #define T10_INSRT_EN_OFF 0 390 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 391 #define T10_RMV_EN_OFF 1 392 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 393 #define T10_RPLC_EN_OFF 2 394 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 395 #define T10_CHK_EN_OFF 3 396 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 397 #define INCR_LBRT_OFF 5 398 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 399 #define USR_DATA_BLOCK_SZ_OFF 20 400 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 401 #define T10_CHK_MSK_OFF 16 402 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 403 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 404 405 static bool hisi_sas_intr_conv; 406 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 407 408 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 409 static int prot_mask; 410 module_param(prot_mask, int, 0); 411 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 412 413 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 414 { 415 void __iomem *regs = hisi_hba->regs + off; 416 417 return readl(regs); 418 } 419 420 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 421 { 422 void __iomem *regs = hisi_hba->regs + off; 423 424 return readl_relaxed(regs); 425 } 426 427 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 428 { 429 void __iomem *regs = hisi_hba->regs + off; 430 431 writel(val, regs); 432 } 433 434 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 435 u32 off, u32 val) 436 { 437 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 438 439 writel(val, regs); 440 } 441 442 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 443 int phy_no, u32 off) 444 { 445 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 446 447 return readl(regs); 448 } 449 450 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 451 timeout_us) \ 452 ({ \ 453 void __iomem *regs = hisi_hba->regs + off; \ 454 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 455 }) 456 457 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 458 timeout_us) \ 459 ({ \ 460 void __iomem *regs = hisi_hba->regs + off; \ 461 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 462 }) 463 464 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 465 { 466 struct pci_dev *pdev = hisi_hba->pci_dev; 467 int i; 468 469 /* Global registers init */ 470 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 471 (u32)((1ULL << hisi_hba->queue_count) - 1)); 472 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 473 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 474 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 475 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 476 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 477 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 478 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 479 hisi_sas_intr_conv); 480 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 481 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 482 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 483 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 484 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 485 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 486 if (pdev->revision >= 0x21) 487 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff); 488 else 489 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 490 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 491 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 492 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 493 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 494 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 495 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 496 for (i = 0; i < hisi_hba->queue_count; i++) 497 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 498 499 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 500 501 for (i = 0; i < hisi_hba->n_phy; i++) { 502 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 503 struct asd_sas_phy *sas_phy = &phy->sas_phy; 504 u32 prog_phy_link_rate = 0x800; 505 506 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 507 SAS_LINK_RATE_1_5_GBPS)) { 508 prog_phy_link_rate = 0x855; 509 } else { 510 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 511 512 prog_phy_link_rate = 513 hisi_sas_get_prog_phy_linkrate_mask(max) | 514 0x800; 515 } 516 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 517 prog_phy_link_rate); 518 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 519 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 520 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 521 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 522 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 523 if (pdev->revision >= 0x21) 524 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 525 0xffffffff); 526 else 527 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 528 0xff87ffff); 529 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 530 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 531 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 532 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 533 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 534 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 535 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 536 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 537 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 538 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 539 /* used for 12G negotiate */ 540 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 541 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 542 } 543 544 for (i = 0; i < hisi_hba->queue_count; i++) { 545 /* Delivery queue */ 546 hisi_sas_write32(hisi_hba, 547 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 548 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 549 550 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 551 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 552 553 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 554 HISI_SAS_QUEUE_SLOTS); 555 556 /* Completion queue */ 557 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 558 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 559 560 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 561 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 562 563 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 564 HISI_SAS_QUEUE_SLOTS); 565 } 566 567 /* itct */ 568 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 569 lower_32_bits(hisi_hba->itct_dma)); 570 571 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 572 upper_32_bits(hisi_hba->itct_dma)); 573 574 /* iost */ 575 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 576 lower_32_bits(hisi_hba->iost_dma)); 577 578 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 579 upper_32_bits(hisi_hba->iost_dma)); 580 581 /* breakpoint */ 582 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 583 lower_32_bits(hisi_hba->breakpoint_dma)); 584 585 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 586 upper_32_bits(hisi_hba->breakpoint_dma)); 587 588 /* SATA broken msg */ 589 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 590 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 591 592 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 593 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 594 595 /* SATA initial fis */ 596 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 597 lower_32_bits(hisi_hba->initial_fis_dma)); 598 599 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 600 upper_32_bits(hisi_hba->initial_fis_dma)); 601 602 /* RAS registers init */ 603 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 604 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 605 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 606 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 607 608 /* LED registers init */ 609 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 610 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 611 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 612 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 613 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 614 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 615 } 616 617 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 618 { 619 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 620 621 cfg &= ~PHY_CFG_DC_OPT_MSK; 622 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 623 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 624 } 625 626 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 627 { 628 struct sas_identify_frame identify_frame; 629 u32 *identify_buffer; 630 631 memset(&identify_frame, 0, sizeof(identify_frame)); 632 identify_frame.dev_type = SAS_END_DEVICE; 633 identify_frame.frame_type = 0; 634 identify_frame._un1 = 1; 635 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 636 identify_frame.target_bits = SAS_PROTOCOL_NONE; 637 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 638 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 639 identify_frame.phy_id = phy_no; 640 identify_buffer = (u32 *)(&identify_frame); 641 642 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 643 __swab32(identify_buffer[0])); 644 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 645 __swab32(identify_buffer[1])); 646 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 647 __swab32(identify_buffer[2])); 648 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 649 __swab32(identify_buffer[3])); 650 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 651 __swab32(identify_buffer[4])); 652 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 653 __swab32(identify_buffer[5])); 654 } 655 656 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 657 struct hisi_sas_device *sas_dev) 658 { 659 struct domain_device *device = sas_dev->sas_device; 660 struct device *dev = hisi_hba->dev; 661 u64 qw0, device_id = sas_dev->device_id; 662 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 663 struct domain_device *parent_dev = device->parent; 664 struct asd_sas_port *sas_port = device->port; 665 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 666 u64 sas_addr; 667 668 memset(itct, 0, sizeof(*itct)); 669 670 /* qw0 */ 671 qw0 = 0; 672 switch (sas_dev->dev_type) { 673 case SAS_END_DEVICE: 674 case SAS_EDGE_EXPANDER_DEVICE: 675 case SAS_FANOUT_EXPANDER_DEVICE: 676 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 677 break; 678 case SAS_SATA_DEV: 679 case SAS_SATA_PENDING: 680 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 681 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 682 else 683 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 684 break; 685 default: 686 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 687 sas_dev->dev_type); 688 } 689 690 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 691 (device->linkrate << ITCT_HDR_MCR_OFF) | 692 (1 << ITCT_HDR_VLN_OFF) | 693 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 694 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 695 (port->id << ITCT_HDR_PORT_ID_OFF)); 696 itct->qw0 = cpu_to_le64(qw0); 697 698 /* qw1 */ 699 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 700 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 701 702 /* qw2 */ 703 if (!dev_is_sata(device)) 704 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 705 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 706 } 707 708 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 709 struct hisi_sas_device *sas_dev) 710 { 711 DECLARE_COMPLETION_ONSTACK(completion); 712 u64 dev_id = sas_dev->device_id; 713 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 714 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 715 716 sas_dev->completion = &completion; 717 718 /* clear the itct interrupt state */ 719 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 720 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 721 ENT_INT_SRC3_ITC_INT_MSK); 722 723 /* clear the itct table*/ 724 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 725 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 726 727 wait_for_completion(sas_dev->completion); 728 memset(itct, 0, sizeof(struct hisi_sas_itct)); 729 } 730 731 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 732 struct domain_device *device) 733 { 734 struct hisi_sas_slot *slot, *slot2; 735 struct hisi_sas_device *sas_dev = device->lldd_dev; 736 u32 cfg_abt_set_query_iptt; 737 738 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 739 CFG_ABT_SET_QUERY_IPTT); 740 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 741 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 742 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 743 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 744 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 745 cfg_abt_set_query_iptt); 746 } 747 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 748 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 749 cfg_abt_set_query_iptt); 750 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 751 1 << CFG_ABT_SET_IPTT_DONE_OFF); 752 } 753 754 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 755 { 756 struct device *dev = hisi_hba->dev; 757 int ret; 758 u32 val; 759 760 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 761 762 /* Disable all of the PHYs */ 763 hisi_sas_stop_phys(hisi_hba); 764 udelay(50); 765 766 /* Ensure axi bus idle */ 767 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 768 20000, 1000000); 769 if (ret) { 770 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 771 return -EIO; 772 } 773 774 if (ACPI_HANDLE(dev)) { 775 acpi_status s; 776 777 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 778 if (ACPI_FAILURE(s)) { 779 dev_err(dev, "Reset failed\n"); 780 return -EIO; 781 } 782 } else { 783 dev_err(dev, "no reset method!\n"); 784 return -EINVAL; 785 } 786 787 return 0; 788 } 789 790 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 791 { 792 struct device *dev = hisi_hba->dev; 793 int rc; 794 795 rc = reset_hw_v3_hw(hisi_hba); 796 if (rc) { 797 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 798 return rc; 799 } 800 801 msleep(100); 802 init_reg_v3_hw(hisi_hba); 803 804 return 0; 805 } 806 807 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 808 { 809 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 810 811 cfg |= PHY_CFG_ENA_MSK; 812 cfg &= ~PHY_CFG_PHY_RST_MSK; 813 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 814 } 815 816 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 817 { 818 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 819 u32 state; 820 821 cfg &= ~PHY_CFG_ENA_MSK; 822 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 823 824 mdelay(50); 825 826 state = hisi_sas_read32(hisi_hba, PHY_STATE); 827 if (state & BIT(phy_no)) { 828 cfg |= PHY_CFG_PHY_RST_MSK; 829 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 830 } 831 } 832 833 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 834 { 835 config_id_frame_v3_hw(hisi_hba, phy_no); 836 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 837 enable_phy_v3_hw(hisi_hba, phy_no); 838 } 839 840 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 841 { 842 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 843 u32 txid_auto; 844 845 disable_phy_v3_hw(hisi_hba, phy_no); 846 if (phy->identify.device_type == SAS_END_DEVICE) { 847 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 848 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 849 txid_auto | TX_HARDRST_MSK); 850 } 851 msleep(100); 852 start_phy_v3_hw(hisi_hba, phy_no); 853 } 854 855 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 856 { 857 return SAS_LINK_RATE_12_0_GBPS; 858 } 859 860 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 861 { 862 int i; 863 864 for (i = 0; i < hisi_hba->n_phy; i++) { 865 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 866 struct asd_sas_phy *sas_phy = &phy->sas_phy; 867 868 if (!sas_phy->phy->enabled) 869 continue; 870 871 start_phy_v3_hw(hisi_hba, i); 872 } 873 } 874 875 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 876 { 877 u32 sl_control; 878 879 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 880 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 881 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 882 msleep(1); 883 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 884 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 885 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 886 } 887 888 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 889 { 890 int i, bitmap = 0; 891 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 892 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 893 894 for (i = 0; i < hisi_hba->n_phy; i++) 895 if (phy_state & BIT(i)) 896 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 897 bitmap |= BIT(i); 898 899 return bitmap; 900 } 901 902 /** 903 * The callpath to this function and upto writing the write 904 * queue pointer should be safe from interruption. 905 */ 906 static int 907 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 908 { 909 struct device *dev = hisi_hba->dev; 910 int queue = dq->id; 911 u32 r, w; 912 913 w = dq->wr_point; 914 r = hisi_sas_read32_relaxed(hisi_hba, 915 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 916 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 917 dev_warn(dev, "full queue=%d r=%d w=%d\n", 918 queue, r, w); 919 return -EAGAIN; 920 } 921 922 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 923 924 return w; 925 } 926 927 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 928 { 929 struct hisi_hba *hisi_hba = dq->hisi_hba; 930 struct hisi_sas_slot *s, *s1, *s2 = NULL; 931 int dlvry_queue = dq->id; 932 int wp; 933 934 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 935 if (!s->ready) 936 break; 937 s2 = s; 938 list_del(&s->delivery); 939 } 940 941 if (!s2) 942 return; 943 944 /* 945 * Ensure that memories for slots built on other CPUs is observed. 946 */ 947 smp_rmb(); 948 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 949 950 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 951 } 952 953 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 954 struct hisi_sas_slot *slot, 955 struct hisi_sas_cmd_hdr *hdr, 956 struct scatterlist *scatter, 957 int n_elem) 958 { 959 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 960 struct scatterlist *sg; 961 int i; 962 963 for_each_sg(scatter, sg, n_elem, i) { 964 struct hisi_sas_sge *entry = &sge_page->sge[i]; 965 966 entry->addr = cpu_to_le64(sg_dma_address(sg)); 967 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 968 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 969 entry->data_off = 0; 970 } 971 972 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 973 974 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 975 } 976 977 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 978 struct hisi_sas_slot *slot, 979 struct hisi_sas_cmd_hdr *hdr, 980 struct scatterlist *scatter, 981 int n_elem) 982 { 983 struct hisi_sas_sge_dif_page *sge_dif_page; 984 struct scatterlist *sg; 985 int i; 986 987 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 988 989 for_each_sg(scatter, sg, n_elem, i) { 990 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 991 992 entry->addr = cpu_to_le64(sg_dma_address(sg)); 993 entry->page_ctrl_0 = 0; 994 entry->page_ctrl_1 = 0; 995 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 996 entry->data_off = 0; 997 } 998 999 hdr->dif_prd_table_addr = 1000 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1001 1002 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1003 } 1004 1005 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1006 { 1007 unsigned char prot_flags = scsi_cmnd->prot_flags; 1008 1009 if (prot_flags & SCSI_PROT_REF_CHECK) 1010 return T10_CHK_APP_TAG_MSK; 1011 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1012 } 1013 1014 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1015 struct hisi_sas_protect_iu_v3_hw *prot) 1016 { 1017 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1018 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1019 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1020 1021 switch (prot_op) { 1022 case SCSI_PROT_READ_INSERT: 1023 prot->dw0 |= T10_INSRT_EN_MSK; 1024 prot->lbrtgv = lbrt_chk_val; 1025 break; 1026 case SCSI_PROT_READ_STRIP: 1027 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1028 prot->lbrtcv = lbrt_chk_val; 1029 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1030 break; 1031 case SCSI_PROT_READ_PASS: 1032 prot->dw0 |= T10_CHK_EN_MSK; 1033 prot->lbrtcv = lbrt_chk_val; 1034 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1035 break; 1036 case SCSI_PROT_WRITE_INSERT: 1037 prot->dw0 |= T10_INSRT_EN_MSK; 1038 prot->lbrtgv = lbrt_chk_val; 1039 break; 1040 case SCSI_PROT_WRITE_STRIP: 1041 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1042 prot->lbrtcv = lbrt_chk_val; 1043 break; 1044 case SCSI_PROT_WRITE_PASS: 1045 prot->dw0 |= T10_CHK_EN_MSK; 1046 prot->lbrtcv = lbrt_chk_val; 1047 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1048 break; 1049 default: 1050 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1051 break; 1052 } 1053 1054 switch (interval) { 1055 case 512: 1056 break; 1057 case 4096: 1058 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1059 break; 1060 case 520: 1061 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1062 break; 1063 default: 1064 WARN(1, "protection interval (0x%x) invalid\n", 1065 interval); 1066 break; 1067 } 1068 1069 prot->dw0 |= INCR_LBRT_MSK; 1070 } 1071 1072 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1073 struct hisi_sas_slot *slot) 1074 { 1075 struct sas_task *task = slot->task; 1076 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1077 struct domain_device *device = task->dev; 1078 struct hisi_sas_device *sas_dev = device->lldd_dev; 1079 struct hisi_sas_port *port = slot->port; 1080 struct sas_ssp_task *ssp_task = &task->ssp_task; 1081 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1082 struct hisi_sas_tmf_task *tmf = slot->tmf; 1083 int has_data = 0, priority = !!tmf; 1084 unsigned char prot_op; 1085 u8 *buf_cmd; 1086 u32 dw1 = 0, dw2 = 0, len = 0; 1087 1088 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1089 (2 << CMD_HDR_TLR_CTRL_OFF) | 1090 (port->id << CMD_HDR_PORT_OFF) | 1091 (priority << CMD_HDR_PRIORITY_OFF) | 1092 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1093 1094 dw1 = 1 << CMD_HDR_VDTL_OFF; 1095 if (tmf) { 1096 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1097 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1098 } else { 1099 prot_op = scsi_get_prot_op(scsi_cmnd); 1100 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1101 switch (scsi_cmnd->sc_data_direction) { 1102 case DMA_TO_DEVICE: 1103 has_data = 1; 1104 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1105 break; 1106 case DMA_FROM_DEVICE: 1107 has_data = 1; 1108 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1109 break; 1110 default: 1111 dw1 &= ~CMD_HDR_DIR_MSK; 1112 } 1113 } 1114 1115 /* map itct entry */ 1116 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1117 1118 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1119 + 3) / 4) << CMD_HDR_CFL_OFF) | 1120 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1121 (2 << CMD_HDR_SG_MOD_OFF); 1122 hdr->dw2 = cpu_to_le32(dw2); 1123 hdr->transfer_tags = cpu_to_le32(slot->idx); 1124 1125 if (has_data) { 1126 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1127 slot->n_elem); 1128 1129 if (scsi_prot_sg_count(scsi_cmnd)) 1130 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1131 scsi_prot_sglist(scsi_cmnd), 1132 slot->n_elem_dif); 1133 } 1134 1135 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1136 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1137 1138 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1139 sizeof(struct ssp_frame_hdr); 1140 1141 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1142 if (!tmf) { 1143 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1144 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1145 } else { 1146 buf_cmd[10] = tmf->tmf; 1147 switch (tmf->tmf) { 1148 case TMF_ABORT_TASK: 1149 case TMF_QUERY_TASK: 1150 buf_cmd[12] = 1151 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1152 buf_cmd[13] = 1153 tmf->tag_of_task_to_be_managed & 0xff; 1154 break; 1155 default: 1156 break; 1157 } 1158 } 1159 1160 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1161 struct hisi_sas_protect_iu_v3_hw prot; 1162 u8 *buf_cmd_prot; 1163 1164 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1165 dw1 |= CMD_HDR_PIR_MSK; 1166 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1167 sizeof(struct ssp_frame_hdr) + 1168 sizeof(struct ssp_command_iu); 1169 1170 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1171 fill_prot_v3_hw(scsi_cmnd, &prot); 1172 memcpy(buf_cmd_prot, &prot, 1173 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1174 /* 1175 * For READ, we need length of info read to memory, while for 1176 * WRITE we need length of data written to the disk. 1177 */ 1178 if (prot_op == SCSI_PROT_WRITE_INSERT || 1179 prot_op == SCSI_PROT_READ_INSERT || 1180 prot_op == SCSI_PROT_WRITE_PASS || 1181 prot_op == SCSI_PROT_READ_PASS) { 1182 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1183 unsigned int ilog2_interval = ilog2(interval); 1184 1185 len = (task->total_xfer_len >> ilog2_interval) * 8; 1186 } 1187 } 1188 1189 hdr->dw1 = cpu_to_le32(dw1); 1190 1191 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1192 } 1193 1194 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1195 struct hisi_sas_slot *slot) 1196 { 1197 struct sas_task *task = slot->task; 1198 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1199 struct domain_device *device = task->dev; 1200 struct hisi_sas_port *port = slot->port; 1201 struct scatterlist *sg_req; 1202 struct hisi_sas_device *sas_dev = device->lldd_dev; 1203 dma_addr_t req_dma_addr; 1204 unsigned int req_len; 1205 1206 /* req */ 1207 sg_req = &task->smp_task.smp_req; 1208 req_len = sg_dma_len(sg_req); 1209 req_dma_addr = sg_dma_address(sg_req); 1210 1211 /* create header */ 1212 /* dw0 */ 1213 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1214 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1215 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1216 1217 /* map itct entry */ 1218 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1219 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1220 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1221 1222 /* dw2 */ 1223 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1224 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1225 CMD_HDR_MRFL_OFF)); 1226 1227 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1228 1229 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1230 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1231 1232 } 1233 1234 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1235 struct hisi_sas_slot *slot) 1236 { 1237 struct sas_task *task = slot->task; 1238 struct domain_device *device = task->dev; 1239 struct domain_device *parent_dev = device->parent; 1240 struct hisi_sas_device *sas_dev = device->lldd_dev; 1241 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1242 struct asd_sas_port *sas_port = device->port; 1243 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1244 u8 *buf_cmd; 1245 int has_data = 0, hdr_tag = 0; 1246 u32 dw1 = 0, dw2 = 0; 1247 1248 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1249 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1250 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1251 else 1252 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1253 1254 switch (task->data_dir) { 1255 case DMA_TO_DEVICE: 1256 has_data = 1; 1257 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1258 break; 1259 case DMA_FROM_DEVICE: 1260 has_data = 1; 1261 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1262 break; 1263 default: 1264 dw1 &= ~CMD_HDR_DIR_MSK; 1265 } 1266 1267 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1268 (task->ata_task.fis.control & ATA_SRST)) 1269 dw1 |= 1 << CMD_HDR_RESET_OFF; 1270 1271 dw1 |= (hisi_sas_get_ata_protocol( 1272 &task->ata_task.fis, task->data_dir)) 1273 << CMD_HDR_FRAME_TYPE_OFF; 1274 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1275 1276 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1277 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1278 1279 hdr->dw1 = cpu_to_le32(dw1); 1280 1281 /* dw2 */ 1282 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1283 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1284 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1285 } 1286 1287 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1288 2 << CMD_HDR_SG_MOD_OFF; 1289 hdr->dw2 = cpu_to_le32(dw2); 1290 1291 /* dw3 */ 1292 hdr->transfer_tags = cpu_to_le32(slot->idx); 1293 1294 if (has_data) 1295 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1296 slot->n_elem); 1297 1298 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1299 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1300 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1301 1302 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1303 1304 if (likely(!task->ata_task.device_control_reg_update)) 1305 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1306 /* fill in command FIS */ 1307 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1308 } 1309 1310 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1311 struct hisi_sas_slot *slot, 1312 int device_id, int abort_flag, int tag_to_abort) 1313 { 1314 struct sas_task *task = slot->task; 1315 struct domain_device *dev = task->dev; 1316 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1317 struct hisi_sas_port *port = slot->port; 1318 1319 /* dw0 */ 1320 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1321 (port->id << CMD_HDR_PORT_OFF) | 1322 (dev_is_sata(dev) 1323 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1324 (abort_flag 1325 << CMD_HDR_ABORT_FLAG_OFF)); 1326 1327 /* dw1 */ 1328 hdr->dw1 = cpu_to_le32(device_id 1329 << CMD_HDR_DEV_ID_OFF); 1330 1331 /* dw7 */ 1332 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1333 hdr->transfer_tags = cpu_to_le32(slot->idx); 1334 1335 } 1336 1337 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1338 { 1339 int i, res; 1340 u32 context, port_id, link_rate; 1341 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1342 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1343 struct device *dev = hisi_hba->dev; 1344 unsigned long flags; 1345 1346 del_timer(&phy->timer); 1347 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1348 1349 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1350 port_id = (port_id >> (4 * phy_no)) & 0xf; 1351 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1352 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1353 1354 if (port_id == 0xf) { 1355 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1356 res = IRQ_NONE; 1357 goto end; 1358 } 1359 sas_phy->linkrate = link_rate; 1360 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1361 1362 /* Check for SATA dev */ 1363 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1364 if (context & (1 << phy_no)) { 1365 struct hisi_sas_initial_fis *initial_fis; 1366 struct dev_to_host_fis *fis; 1367 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1368 1369 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1370 initial_fis = &hisi_hba->initial_fis[phy_no]; 1371 fis = &initial_fis->fis; 1372 1373 /* check ERR bit of Status Register */ 1374 if (fis->status & ATA_ERR) { 1375 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1376 phy_no, fis->status); 1377 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1378 res = IRQ_NONE; 1379 goto end; 1380 } 1381 1382 sas_phy->oob_mode = SATA_OOB_MODE; 1383 attached_sas_addr[0] = 0x50; 1384 attached_sas_addr[7] = phy_no; 1385 memcpy(sas_phy->attached_sas_addr, 1386 attached_sas_addr, 1387 SAS_ADDR_SIZE); 1388 memcpy(sas_phy->frame_rcvd, fis, 1389 sizeof(struct dev_to_host_fis)); 1390 phy->phy_type |= PORT_TYPE_SATA; 1391 phy->identify.device_type = SAS_SATA_DEV; 1392 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1393 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1394 } else { 1395 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1396 struct sas_identify_frame *id = 1397 (struct sas_identify_frame *)frame_rcvd; 1398 1399 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1400 for (i = 0; i < 6; i++) { 1401 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1402 RX_IDAF_DWORD0 + (i * 4)); 1403 frame_rcvd[i] = __swab32(idaf); 1404 } 1405 sas_phy->oob_mode = SAS_OOB_MODE; 1406 memcpy(sas_phy->attached_sas_addr, 1407 &id->sas_addr, 1408 SAS_ADDR_SIZE); 1409 phy->phy_type |= PORT_TYPE_SAS; 1410 phy->identify.device_type = id->dev_type; 1411 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1412 if (phy->identify.device_type == SAS_END_DEVICE) 1413 phy->identify.target_port_protocols = 1414 SAS_PROTOCOL_SSP; 1415 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1416 phy->identify.target_port_protocols = 1417 SAS_PROTOCOL_SMP; 1418 } 1419 1420 phy->port_id = port_id; 1421 phy->phy_attached = 1; 1422 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1423 res = IRQ_HANDLED; 1424 spin_lock_irqsave(&phy->lock, flags); 1425 if (phy->reset_completion) { 1426 phy->in_reset = 0; 1427 complete(phy->reset_completion); 1428 } 1429 spin_unlock_irqrestore(&phy->lock, flags); 1430 end: 1431 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1432 CHL_INT0_SL_PHY_ENABLE_MSK); 1433 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1434 1435 return res; 1436 } 1437 1438 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1439 { 1440 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1441 u32 phy_state, sl_ctrl, txid_auto; 1442 struct device *dev = hisi_hba->dev; 1443 1444 del_timer(&phy->timer); 1445 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1446 1447 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1448 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1449 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1450 1451 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1452 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1453 sl_ctrl&(~SL_CTA_MSK)); 1454 1455 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1456 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1457 txid_auto | CT3_MSK); 1458 1459 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1460 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1461 1462 return IRQ_HANDLED; 1463 } 1464 1465 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1466 { 1467 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1468 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1469 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1470 u32 bcast_status; 1471 1472 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1473 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1474 if ((bcast_status & RX_BCAST_CHG_MSK) && 1475 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1476 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1477 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1478 CHL_INT0_SL_RX_BCST_ACK_MSK); 1479 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1480 1481 return IRQ_HANDLED; 1482 } 1483 1484 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1485 { 1486 struct hisi_hba *hisi_hba = p; 1487 u32 irq_msk; 1488 int phy_no = 0; 1489 irqreturn_t res = IRQ_NONE; 1490 1491 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1492 & 0x11111111; 1493 while (irq_msk) { 1494 if (irq_msk & 1) { 1495 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1496 CHL_INT0); 1497 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1498 int rdy = phy_state & (1 << phy_no); 1499 1500 if (rdy) { 1501 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1502 /* phy up */ 1503 if (phy_up_v3_hw(phy_no, hisi_hba) 1504 == IRQ_HANDLED) 1505 res = IRQ_HANDLED; 1506 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1507 /* phy bcast */ 1508 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1509 == IRQ_HANDLED) 1510 res = IRQ_HANDLED; 1511 } else { 1512 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1513 /* phy down */ 1514 if (phy_down_v3_hw(phy_no, hisi_hba) 1515 == IRQ_HANDLED) 1516 res = IRQ_HANDLED; 1517 } 1518 } 1519 irq_msk >>= 4; 1520 phy_no++; 1521 } 1522 1523 return res; 1524 } 1525 1526 static const struct hisi_sas_hw_error port_axi_error[] = { 1527 { 1528 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1529 .msg = "dma_tx_axi_wr_err", 1530 }, 1531 { 1532 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1533 .msg = "dma_tx_axi_rd_err", 1534 }, 1535 { 1536 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1537 .msg = "dma_rx_axi_wr_err", 1538 }, 1539 { 1540 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1541 .msg = "dma_rx_axi_rd_err", 1542 }, 1543 }; 1544 1545 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1546 { 1547 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1548 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1549 struct device *dev = hisi_hba->dev; 1550 int i; 1551 1552 irq_value &= ~irq_msk; 1553 if (!irq_value) 1554 return; 1555 1556 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1557 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1558 1559 if (!(irq_value & error->irq_msk)) 1560 continue; 1561 1562 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1563 error->msg, phy_no, irq_value); 1564 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1565 } 1566 1567 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1568 } 1569 1570 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1571 { 1572 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1573 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1574 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1575 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1576 struct device *dev = hisi_hba->dev; 1577 1578 irq_value &= ~irq_msk; 1579 if (!irq_value) 1580 return; 1581 1582 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1583 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1584 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1585 } 1586 1587 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1588 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1589 STP_LINK_TIMEOUT_STATE); 1590 1591 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1592 phy_no, reg_value); 1593 if (reg_value & BIT(4)) 1594 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1595 } 1596 1597 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1598 (pci_dev->revision == 0x20)) { 1599 u32 reg_value; 1600 int rc; 1601 1602 rc = hisi_sas_read32_poll_timeout_atomic( 1603 HILINK_ERR_DFX, reg_value, 1604 !((reg_value >> 8) & BIT(phy_no)), 1605 1000, 10000); 1606 if (rc) 1607 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1608 } 1609 1610 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1611 } 1612 1613 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1614 { 1615 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1616 1617 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1618 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1619 1620 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1621 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1622 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1623 & (~CHL_INT0_NOT_RDY_MSK)); 1624 } 1625 1626 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1627 { 1628 struct hisi_hba *hisi_hba = p; 1629 u32 irq_msk; 1630 int phy_no = 0; 1631 1632 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1633 & 0xeeeeeeee; 1634 1635 while (irq_msk) { 1636 if (irq_msk & (2 << (phy_no * 4))) 1637 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1638 1639 if (irq_msk & (4 << (phy_no * 4))) 1640 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1641 1642 if (irq_msk & (8 << (phy_no * 4))) 1643 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1644 1645 irq_msk &= ~(0xe << (phy_no * 4)); 1646 phy_no++; 1647 } 1648 1649 return IRQ_HANDLED; 1650 } 1651 1652 static const struct hisi_sas_hw_error axi_error[] = { 1653 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1654 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1655 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1656 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1657 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1658 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1659 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1660 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1661 {}, 1662 }; 1663 1664 static const struct hisi_sas_hw_error fifo_error[] = { 1665 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1666 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1667 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1668 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1669 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1670 {}, 1671 }; 1672 1673 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1674 { 1675 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1676 .msg = "write pointer and depth", 1677 }, 1678 { 1679 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1680 .msg = "iptt no match slot", 1681 }, 1682 { 1683 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1684 .msg = "read pointer and depth", 1685 }, 1686 { 1687 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1688 .reg = HGC_AXI_FIFO_ERR_INFO, 1689 .sub = axi_error, 1690 }, 1691 { 1692 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1693 .reg = HGC_AXI_FIFO_ERR_INFO, 1694 .sub = fifo_error, 1695 }, 1696 { 1697 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1698 .msg = "LM add/fetch list", 1699 }, 1700 { 1701 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1702 .msg = "SAS_HGC_ABT fetch LM list", 1703 }, 1704 }; 1705 1706 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1707 { 1708 u32 irq_value, irq_msk; 1709 struct hisi_hba *hisi_hba = p; 1710 struct device *dev = hisi_hba->dev; 1711 struct pci_dev *pdev = hisi_hba->pci_dev; 1712 int i; 1713 1714 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1715 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1716 1717 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1718 irq_value &= ~irq_msk; 1719 1720 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1721 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1722 1723 if (!(irq_value & error->irq_msk)) 1724 continue; 1725 1726 if (error->sub) { 1727 const struct hisi_sas_hw_error *sub = error->sub; 1728 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1729 1730 for (; sub->msk || sub->msg; sub++) { 1731 if (!(err_value & sub->msk)) 1732 continue; 1733 1734 dev_err(dev, "%s error (0x%x) found!\n", 1735 sub->msg, irq_value); 1736 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1737 } 1738 } else { 1739 dev_err(dev, "%s error (0x%x) found!\n", 1740 error->msg, irq_value); 1741 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1742 } 1743 1744 if (pdev->revision < 0x21) { 1745 u32 reg_val; 1746 1747 reg_val = hisi_sas_read32(hisi_hba, 1748 AXI_MASTER_CFG_BASE + 1749 AM_CTRL_GLOBAL); 1750 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 1751 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 1752 AM_CTRL_GLOBAL, reg_val); 1753 } 1754 } 1755 1756 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1757 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1758 u32 dev_id = reg_val & ITCT_DEV_MSK; 1759 struct hisi_sas_device *sas_dev = 1760 &hisi_hba->devices[dev_id]; 1761 1762 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1763 dev_dbg(dev, "clear ITCT ok\n"); 1764 complete(sas_dev->completion); 1765 } 1766 1767 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1768 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1769 1770 return IRQ_HANDLED; 1771 } 1772 1773 static void 1774 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1775 struct hisi_sas_slot *slot) 1776 { 1777 struct task_status_struct *ts = &task->task_status; 1778 struct hisi_sas_complete_v3_hdr *complete_queue = 1779 hisi_hba->complete_hdr[slot->cmplt_queue]; 1780 struct hisi_sas_complete_v3_hdr *complete_hdr = 1781 &complete_queue[slot->cmplt_queue_slot]; 1782 struct hisi_sas_err_record_v3 *record = 1783 hisi_sas_status_buf_addr_mem(slot); 1784 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 1785 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 1786 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 1787 1788 switch (task->task_proto) { 1789 case SAS_PROTOCOL_SSP: 1790 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1791 ts->residual = trans_tx_fail_type; 1792 ts->stat = SAS_DATA_UNDERRUN; 1793 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1794 ts->stat = SAS_QUEUE_FULL; 1795 slot->abort = 1; 1796 } else { 1797 ts->stat = SAS_OPEN_REJECT; 1798 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1799 } 1800 break; 1801 case SAS_PROTOCOL_SATA: 1802 case SAS_PROTOCOL_STP: 1803 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1804 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1805 ts->residual = trans_tx_fail_type; 1806 ts->stat = SAS_DATA_UNDERRUN; 1807 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1808 ts->stat = SAS_PHY_DOWN; 1809 slot->abort = 1; 1810 } else { 1811 ts->stat = SAS_OPEN_REJECT; 1812 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1813 } 1814 hisi_sas_sata_done(task, slot); 1815 break; 1816 case SAS_PROTOCOL_SMP: 1817 ts->stat = SAM_STAT_CHECK_CONDITION; 1818 break; 1819 default: 1820 break; 1821 } 1822 } 1823 1824 static int 1825 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1826 { 1827 struct sas_task *task = slot->task; 1828 struct hisi_sas_device *sas_dev; 1829 struct device *dev = hisi_hba->dev; 1830 struct task_status_struct *ts; 1831 struct domain_device *device; 1832 struct sas_ha_struct *ha; 1833 enum exec_status sts; 1834 struct hisi_sas_complete_v3_hdr *complete_queue = 1835 hisi_hba->complete_hdr[slot->cmplt_queue]; 1836 struct hisi_sas_complete_v3_hdr *complete_hdr = 1837 &complete_queue[slot->cmplt_queue_slot]; 1838 unsigned long flags; 1839 bool is_internal = slot->is_internal; 1840 u32 dw0, dw1, dw3; 1841 1842 if (unlikely(!task || !task->lldd_task || !task->dev)) 1843 return -EINVAL; 1844 1845 ts = &task->task_status; 1846 device = task->dev; 1847 ha = device->port->ha; 1848 sas_dev = device->lldd_dev; 1849 1850 spin_lock_irqsave(&task->task_state_lock, flags); 1851 task->task_state_flags &= 1852 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1853 spin_unlock_irqrestore(&task->task_state_lock, flags); 1854 1855 memset(ts, 0, sizeof(*ts)); 1856 ts->resp = SAS_TASK_COMPLETE; 1857 1858 if (unlikely(!sas_dev)) { 1859 dev_dbg(dev, "slot complete: port has not device\n"); 1860 ts->stat = SAS_PHY_DOWN; 1861 goto out; 1862 } 1863 1864 dw0 = le32_to_cpu(complete_hdr->dw0); 1865 dw1 = le32_to_cpu(complete_hdr->dw1); 1866 dw3 = le32_to_cpu(complete_hdr->dw3); 1867 1868 /* 1869 * Use SAS+TMF status codes 1870 */ 1871 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 1872 case STAT_IO_ABORTED: 1873 /* this IO has been aborted by abort command */ 1874 ts->stat = SAS_ABORTED_TASK; 1875 goto out; 1876 case STAT_IO_COMPLETE: 1877 /* internal abort command complete */ 1878 ts->stat = TMF_RESP_FUNC_SUCC; 1879 goto out; 1880 case STAT_IO_NO_DEVICE: 1881 ts->stat = TMF_RESP_FUNC_COMPLETE; 1882 goto out; 1883 case STAT_IO_NOT_VALID: 1884 /* 1885 * abort single IO, the controller can't find the IO 1886 */ 1887 ts->stat = TMF_RESP_FUNC_FAILED; 1888 goto out; 1889 default: 1890 break; 1891 } 1892 1893 /* check for erroneous completion */ 1894 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1895 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1896 1897 slot_err_v3_hw(hisi_hba, task, slot); 1898 if (ts->stat != SAS_DATA_UNDERRUN) 1899 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1900 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1901 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1902 slot->idx, task, sas_dev->device_id, 1903 dw0, dw1, complete_hdr->act, dw3, 1904 error_info[0], error_info[1], 1905 error_info[2], error_info[3]); 1906 if (unlikely(slot->abort)) 1907 return ts->stat; 1908 goto out; 1909 } 1910 1911 switch (task->task_proto) { 1912 case SAS_PROTOCOL_SSP: { 1913 struct ssp_response_iu *iu = 1914 hisi_sas_status_buf_addr_mem(slot) + 1915 sizeof(struct hisi_sas_err_record); 1916 1917 sas_ssp_task_response(dev, task, iu); 1918 break; 1919 } 1920 case SAS_PROTOCOL_SMP: { 1921 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1922 void *to; 1923 1924 ts->stat = SAM_STAT_GOOD; 1925 to = kmap_atomic(sg_page(sg_resp)); 1926 1927 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1928 DMA_FROM_DEVICE); 1929 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1930 DMA_TO_DEVICE); 1931 memcpy(to + sg_resp->offset, 1932 hisi_sas_status_buf_addr_mem(slot) + 1933 sizeof(struct hisi_sas_err_record), 1934 sg_dma_len(sg_resp)); 1935 kunmap_atomic(to); 1936 break; 1937 } 1938 case SAS_PROTOCOL_SATA: 1939 case SAS_PROTOCOL_STP: 1940 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1941 ts->stat = SAM_STAT_GOOD; 1942 hisi_sas_sata_done(task, slot); 1943 break; 1944 default: 1945 ts->stat = SAM_STAT_CHECK_CONDITION; 1946 break; 1947 } 1948 1949 if (!slot->port->port_attached) { 1950 dev_warn(dev, "slot complete: port %d has removed\n", 1951 slot->port->sas_port.id); 1952 ts->stat = SAS_PHY_DOWN; 1953 } 1954 1955 out: 1956 sts = ts->stat; 1957 spin_lock_irqsave(&task->task_state_lock, flags); 1958 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1959 spin_unlock_irqrestore(&task->task_state_lock, flags); 1960 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1961 return SAS_ABORTED_TASK; 1962 } 1963 task->task_state_flags |= SAS_TASK_STATE_DONE; 1964 spin_unlock_irqrestore(&task->task_state_lock, flags); 1965 hisi_sas_slot_task_free(hisi_hba, task, slot); 1966 1967 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1968 spin_lock_irqsave(&device->done_lock, flags); 1969 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1970 spin_unlock_irqrestore(&device->done_lock, flags); 1971 dev_info(dev, "slot complete: task(%p) ignored\n ", 1972 task); 1973 return sts; 1974 } 1975 spin_unlock_irqrestore(&device->done_lock, flags); 1976 } 1977 1978 if (task->task_done) 1979 task->task_done(task); 1980 1981 return sts; 1982 } 1983 1984 static void cq_tasklet_v3_hw(unsigned long val) 1985 { 1986 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1987 struct hisi_hba *hisi_hba = cq->hisi_hba; 1988 struct hisi_sas_slot *slot; 1989 struct hisi_sas_complete_v3_hdr *complete_queue; 1990 u32 rd_point = cq->rd_point, wr_point; 1991 int queue = cq->id; 1992 1993 complete_queue = hisi_hba->complete_hdr[queue]; 1994 1995 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1996 (0x14 * queue)); 1997 1998 while (rd_point != wr_point) { 1999 struct hisi_sas_complete_v3_hdr *complete_hdr; 2000 struct device *dev = hisi_hba->dev; 2001 u32 dw1; 2002 int iptt; 2003 2004 complete_hdr = &complete_queue[rd_point]; 2005 dw1 = le32_to_cpu(complete_hdr->dw1); 2006 2007 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2008 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2009 slot = &hisi_hba->slot_info[iptt]; 2010 slot->cmplt_queue_slot = rd_point; 2011 slot->cmplt_queue = queue; 2012 slot_complete_v3_hw(hisi_hba, slot); 2013 } else 2014 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2015 2016 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2017 rd_point = 0; 2018 } 2019 2020 /* update rd_point */ 2021 cq->rd_point = rd_point; 2022 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2023 } 2024 2025 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2026 { 2027 struct hisi_sas_cq *cq = p; 2028 struct hisi_hba *hisi_hba = cq->hisi_hba; 2029 int queue = cq->id; 2030 2031 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2032 2033 tasklet_schedule(&cq->tasklet); 2034 2035 return IRQ_HANDLED; 2036 } 2037 2038 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2039 { 2040 struct device *dev = hisi_hba->dev; 2041 struct pci_dev *pdev = hisi_hba->pci_dev; 2042 int vectors, rc; 2043 int i, k; 2044 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 2045 2046 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 2047 max_msi, PCI_IRQ_MSI); 2048 if (vectors < max_msi) { 2049 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 2050 return -ENOENT; 2051 } 2052 2053 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2054 int_phy_up_down_bcast_v3_hw, 0, 2055 DRV_NAME " phy", hisi_hba); 2056 if (rc) { 2057 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2058 rc = -ENOENT; 2059 goto free_irq_vectors; 2060 } 2061 2062 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2063 int_chnl_int_v3_hw, 0, 2064 DRV_NAME " channel", hisi_hba); 2065 if (rc) { 2066 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2067 rc = -ENOENT; 2068 goto free_phy_irq; 2069 } 2070 2071 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2072 fatal_axi_int_v3_hw, 0, 2073 DRV_NAME " fatal", hisi_hba); 2074 if (rc) { 2075 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2076 rc = -ENOENT; 2077 goto free_chnl_interrupt; 2078 } 2079 2080 /* Init tasklets for cq only */ 2081 for (i = 0; i < hisi_hba->queue_count; i++) { 2082 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2083 struct tasklet_struct *t = &cq->tasklet; 2084 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2085 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2086 2087 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2088 cq_interrupt_v3_hw, irqflags, 2089 DRV_NAME " cq", cq); 2090 if (rc) { 2091 dev_err(dev, 2092 "could not request cq%d interrupt, rc=%d\n", 2093 i, rc); 2094 rc = -ENOENT; 2095 goto free_cq_irqs; 2096 } 2097 2098 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2099 } 2100 2101 return 0; 2102 2103 free_cq_irqs: 2104 for (k = 0; k < i; k++) { 2105 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2106 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2107 2108 free_irq(pci_irq_vector(pdev, nr), cq); 2109 } 2110 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2111 free_chnl_interrupt: 2112 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2113 free_phy_irq: 2114 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2115 free_irq_vectors: 2116 pci_free_irq_vectors(pdev); 2117 return rc; 2118 } 2119 2120 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2121 { 2122 int rc; 2123 2124 rc = hw_init_v3_hw(hisi_hba); 2125 if (rc) 2126 return rc; 2127 2128 rc = interrupt_init_v3_hw(hisi_hba); 2129 if (rc) 2130 return rc; 2131 2132 return 0; 2133 } 2134 2135 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2136 struct sas_phy_linkrates *r) 2137 { 2138 enum sas_linkrate max = r->maximum_linkrate; 2139 u32 prog_phy_link_rate = 0x800; 2140 2141 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2142 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2143 prog_phy_link_rate); 2144 } 2145 2146 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2147 { 2148 struct pci_dev *pdev = hisi_hba->pci_dev; 2149 int i; 2150 2151 synchronize_irq(pci_irq_vector(pdev, 1)); 2152 synchronize_irq(pci_irq_vector(pdev, 2)); 2153 synchronize_irq(pci_irq_vector(pdev, 11)); 2154 for (i = 0; i < hisi_hba->queue_count; i++) { 2155 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2156 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2157 } 2158 2159 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2160 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2161 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2162 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2163 2164 for (i = 0; i < hisi_hba->n_phy; i++) { 2165 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2166 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2167 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2168 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2169 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2170 } 2171 } 2172 2173 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2174 { 2175 return hisi_sas_read32(hisi_hba, PHY_STATE); 2176 } 2177 2178 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 2179 { 2180 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2181 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2182 struct sas_phy *sphy = sas_phy->phy; 2183 u32 reg_value; 2184 2185 /* loss dword sync */ 2186 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 2187 sphy->loss_of_dword_sync_count += reg_value; 2188 2189 /* phy reset problem */ 2190 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 2191 sphy->phy_reset_problem_count += reg_value; 2192 2193 /* invalid dword */ 2194 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 2195 sphy->invalid_dword_count += reg_value; 2196 2197 /* disparity err */ 2198 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 2199 sphy->running_disparity_error_count += reg_value; 2200 2201 } 2202 2203 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2204 { 2205 struct device *dev = hisi_hba->dev; 2206 u32 status, reg_val; 2207 int rc; 2208 2209 interrupt_disable_v3_hw(hisi_hba); 2210 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2211 hisi_sas_kill_tasklets(hisi_hba); 2212 2213 hisi_sas_stop_phys(hisi_hba); 2214 2215 mdelay(10); 2216 2217 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2218 AM_CTRL_GLOBAL); 2219 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2220 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2221 AM_CTRL_GLOBAL, reg_val); 2222 2223 /* wait until bus idle */ 2224 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2225 AM_CURR_TRANS_RETURN, status, 2226 status == 0x3, 10, 100); 2227 if (rc) { 2228 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2229 return rc; 2230 } 2231 2232 return 0; 2233 } 2234 2235 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2236 { 2237 struct device *dev = hisi_hba->dev; 2238 int rc; 2239 2240 rc = disable_host_v3_hw(hisi_hba); 2241 if (rc) { 2242 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2243 return rc; 2244 } 2245 2246 hisi_sas_init_mem(hisi_hba); 2247 2248 return hw_init_v3_hw(hisi_hba); 2249 } 2250 2251 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2252 u8 reg_index, u8 reg_count, u8 *write_data) 2253 { 2254 struct device *dev = hisi_hba->dev; 2255 u32 *data = (u32 *)write_data; 2256 int i; 2257 2258 switch (reg_type) { 2259 case SAS_GPIO_REG_TX: 2260 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2261 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2262 reg_index, reg_index + reg_count - 1); 2263 return -EINVAL; 2264 } 2265 2266 for (i = 0; i < reg_count; i++) 2267 hisi_sas_write32(hisi_hba, 2268 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2269 data[i]); 2270 break; 2271 default: 2272 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2273 reg_type); 2274 return -EINVAL; 2275 } 2276 2277 return 0; 2278 } 2279 2280 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2281 int delay_ms, int timeout_ms) 2282 { 2283 struct device *dev = hisi_hba->dev; 2284 int entries, entries_old = 0, time; 2285 2286 for (time = 0; time < timeout_ms; time += delay_ms) { 2287 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2288 if (entries == entries_old) 2289 break; 2290 2291 entries_old = entries; 2292 msleep(delay_ms); 2293 } 2294 2295 if (time >= timeout_ms) 2296 return -ETIMEDOUT; 2297 2298 dev_dbg(dev, "wait commands complete %dms\n", time); 2299 2300 return 0; 2301 } 2302 2303 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2304 struct device_attribute *attr, char *buf) 2305 { 2306 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2307 } 2308 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2309 2310 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2311 { 2312 /* config those registers between enable and disable PHYs */ 2313 hisi_sas_stop_phys(hisi_hba); 2314 2315 if (hisi_hba->intr_coal_ticks == 0 || 2316 hisi_hba->intr_coal_count == 0) { 2317 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2318 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2319 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2320 } else { 2321 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2322 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2323 hisi_hba->intr_coal_ticks); 2324 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2325 hisi_hba->intr_coal_count); 2326 } 2327 phys_init_v3_hw(hisi_hba); 2328 } 2329 2330 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2331 struct device_attribute *attr, 2332 char *buf) 2333 { 2334 struct Scsi_Host *shost = class_to_shost(dev); 2335 struct hisi_hba *hisi_hba = shost_priv(shost); 2336 2337 return scnprintf(buf, PAGE_SIZE, "%u\n", 2338 hisi_hba->intr_coal_ticks); 2339 } 2340 2341 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2342 struct device_attribute *attr, 2343 const char *buf, size_t count) 2344 { 2345 struct Scsi_Host *shost = class_to_shost(dev); 2346 struct hisi_hba *hisi_hba = shost_priv(shost); 2347 u32 intr_coal_ticks; 2348 int ret; 2349 2350 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2351 if (ret) { 2352 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2353 return -EINVAL; 2354 } 2355 2356 if (intr_coal_ticks >= BIT(24)) { 2357 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2358 return -EINVAL; 2359 } 2360 2361 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2362 2363 config_intr_coal_v3_hw(hisi_hba); 2364 2365 return count; 2366 } 2367 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2368 2369 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2370 struct device_attribute 2371 *attr, char *buf) 2372 { 2373 struct Scsi_Host *shost = class_to_shost(dev); 2374 struct hisi_hba *hisi_hba = shost_priv(shost); 2375 2376 return scnprintf(buf, PAGE_SIZE, "%u\n", 2377 hisi_hba->intr_coal_count); 2378 } 2379 2380 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2381 struct device_attribute 2382 *attr, const char *buf, size_t count) 2383 { 2384 struct Scsi_Host *shost = class_to_shost(dev); 2385 struct hisi_hba *hisi_hba = shost_priv(shost); 2386 u32 intr_coal_count; 2387 int ret; 2388 2389 ret = kstrtou32(buf, 10, &intr_coal_count); 2390 if (ret) { 2391 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2392 return -EINVAL; 2393 } 2394 2395 if (intr_coal_count >= BIT(8)) { 2396 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2397 return -EINVAL; 2398 } 2399 2400 hisi_hba->intr_coal_count = intr_coal_count; 2401 2402 config_intr_coal_v3_hw(hisi_hba); 2403 2404 return count; 2405 } 2406 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2407 2408 static struct device_attribute *host_attrs_v3_hw[] = { 2409 &dev_attr_phy_event_threshold, 2410 &dev_attr_intr_conv_v3_hw, 2411 &dev_attr_intr_coal_ticks_v3_hw, 2412 &dev_attr_intr_coal_count_v3_hw, 2413 NULL 2414 }; 2415 2416 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2417 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2418 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2419 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2420 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2421 HISI_SAS_DEBUGFS_REG(SL_CFG), 2422 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2423 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2424 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2425 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2426 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2427 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2428 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2429 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2430 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2431 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2432 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2433 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2434 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2435 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2436 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2437 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2438 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2439 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2440 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2441 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2442 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2443 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2444 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2445 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2446 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2447 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2448 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2449 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2450 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2451 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2452 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2453 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2454 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2455 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2456 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2457 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2458 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2459 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2460 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2461 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2462 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2463 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2464 {} 2465 }; 2466 2467 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2468 .lu = debugfs_port_reg_lu, 2469 .count = 0x100, 2470 .base_off = PORT_BASE, 2471 .read_port_reg = hisi_sas_phy_read32, 2472 }; 2473 2474 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2475 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2476 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2477 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2478 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2479 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2480 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2481 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2482 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2483 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2484 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2485 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2486 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2487 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2488 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2489 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2490 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2491 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2492 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2493 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2494 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2495 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2496 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2497 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2498 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2499 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2500 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2501 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2502 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2503 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2504 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2505 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2506 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2507 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2508 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2509 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2510 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2511 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2512 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2513 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2514 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2515 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2516 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2517 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2518 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2519 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2520 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2521 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2522 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2523 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2524 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2525 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2526 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2527 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2528 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2529 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2530 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2531 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2532 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2533 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2534 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2535 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2536 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2537 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2538 {} 2539 }; 2540 2541 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2542 .lu = debugfs_global_reg_lu, 2543 .count = 0x800, 2544 .read_global_reg = hisi_sas_read32, 2545 }; 2546 2547 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2548 { 2549 struct device *dev = hisi_hba->dev; 2550 2551 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2552 2553 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2554 2555 if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT) 2556 dev_dbg(dev, "Wait commands complete timeout!\n"); 2557 2558 hisi_sas_kill_tasklets(hisi_hba); 2559 } 2560 2561 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2562 { 2563 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2564 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2565 2566 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2567 } 2568 2569 static struct scsi_host_template sht_v3_hw = { 2570 .name = DRV_NAME, 2571 .module = THIS_MODULE, 2572 .queuecommand = sas_queuecommand, 2573 .target_alloc = sas_target_alloc, 2574 .slave_configure = hisi_sas_slave_configure, 2575 .scan_finished = hisi_sas_scan_finished, 2576 .scan_start = hisi_sas_scan_start, 2577 .change_queue_depth = sas_change_queue_depth, 2578 .bios_param = sas_bios_param, 2579 .this_id = -1, 2580 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2581 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2582 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2583 .eh_device_reset_handler = sas_eh_device_reset_handler, 2584 .eh_target_reset_handler = sas_eh_target_reset_handler, 2585 .target_destroy = sas_target_destroy, 2586 .ioctl = sas_ioctl, 2587 .shost_attrs = host_attrs_v3_hw, 2588 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2589 }; 2590 2591 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2592 .hw_init = hisi_sas_v3_init, 2593 .setup_itct = setup_itct_v3_hw, 2594 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2595 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2596 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2597 .clear_itct = clear_itct_v3_hw, 2598 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2599 .prep_ssp = prep_ssp_v3_hw, 2600 .prep_smp = prep_smp_v3_hw, 2601 .prep_stp = prep_ata_v3_hw, 2602 .prep_abort = prep_abort_v3_hw, 2603 .get_free_slot = get_free_slot_v3_hw, 2604 .start_delivery = start_delivery_v3_hw, 2605 .slot_complete = slot_complete_v3_hw, 2606 .phys_init = phys_init_v3_hw, 2607 .phy_start = start_phy_v3_hw, 2608 .phy_disable = disable_phy_v3_hw, 2609 .phy_hard_reset = phy_hard_reset_v3_hw, 2610 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2611 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2612 .dereg_device = dereg_device_v3_hw, 2613 .soft_reset = soft_reset_v3_hw, 2614 .get_phys_state = get_phys_state_v3_hw, 2615 .get_events = phy_get_events_v3_hw, 2616 .write_gpio = write_gpio_v3_hw, 2617 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2618 .debugfs_reg_global = &debugfs_global_reg, 2619 .debugfs_reg_port = &debugfs_port_reg, 2620 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2621 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2622 }; 2623 2624 static struct Scsi_Host * 2625 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2626 { 2627 struct Scsi_Host *shost; 2628 struct hisi_hba *hisi_hba; 2629 struct device *dev = &pdev->dev; 2630 2631 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2632 if (!shost) { 2633 dev_err(dev, "shost alloc failed\n"); 2634 return NULL; 2635 } 2636 hisi_hba = shost_priv(shost); 2637 2638 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2639 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2640 hisi_hba->hw = &hisi_sas_v3_hw; 2641 hisi_hba->pci_dev = pdev; 2642 hisi_hba->dev = dev; 2643 hisi_hba->shost = shost; 2644 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2645 2646 if (prot_mask & ~HISI_SAS_PROT_MASK) 2647 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2648 prot_mask); 2649 else 2650 hisi_hba->prot_mask = prot_mask; 2651 2652 timer_setup(&hisi_hba->timer, NULL, 0); 2653 2654 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2655 goto err_out; 2656 2657 if (hisi_sas_alloc(hisi_hba)) { 2658 hisi_sas_free(hisi_hba); 2659 goto err_out; 2660 } 2661 2662 return shost; 2663 err_out: 2664 scsi_host_put(shost); 2665 dev_err(dev, "shost alloc failed\n"); 2666 return NULL; 2667 } 2668 2669 static int 2670 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2671 { 2672 struct Scsi_Host *shost; 2673 struct hisi_hba *hisi_hba; 2674 struct device *dev = &pdev->dev; 2675 struct asd_sas_phy **arr_phy; 2676 struct asd_sas_port **arr_port; 2677 struct sas_ha_struct *sha; 2678 int rc, phy_nr, port_nr, i; 2679 2680 rc = pci_enable_device(pdev); 2681 if (rc) 2682 goto err_out; 2683 2684 pci_set_master(pdev); 2685 2686 rc = pci_request_regions(pdev, DRV_NAME); 2687 if (rc) 2688 goto err_out_disable_device; 2689 2690 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) || 2691 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { 2692 dev_err(dev, "No usable DMA addressing method\n"); 2693 rc = -EIO; 2694 goto err_out_regions; 2695 } 2696 2697 shost = hisi_sas_shost_alloc_pci(pdev); 2698 if (!shost) { 2699 rc = -ENOMEM; 2700 goto err_out_regions; 2701 } 2702 2703 sha = SHOST_TO_SAS_HA(shost); 2704 hisi_hba = shost_priv(shost); 2705 dev_set_drvdata(dev, sha); 2706 2707 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2708 if (!hisi_hba->regs) { 2709 dev_err(dev, "cannot map register.\n"); 2710 rc = -ENOMEM; 2711 goto err_out_ha; 2712 } 2713 2714 phy_nr = port_nr = hisi_hba->n_phy; 2715 2716 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2717 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2718 if (!arr_phy || !arr_port) { 2719 rc = -ENOMEM; 2720 goto err_out_ha; 2721 } 2722 2723 sha->sas_phy = arr_phy; 2724 sha->sas_port = arr_port; 2725 sha->core.shost = shost; 2726 sha->lldd_ha = hisi_hba; 2727 2728 shost->transportt = hisi_sas_stt; 2729 shost->max_id = HISI_SAS_MAX_DEVICES; 2730 shost->max_lun = ~0; 2731 shost->max_channel = 1; 2732 shost->max_cmd_len = 16; 2733 shost->can_queue = hisi_hba->hw->max_command_entries - 2734 HISI_SAS_RESERVED_IPTT_CNT; 2735 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 2736 HISI_SAS_RESERVED_IPTT_CNT; 2737 2738 sha->sas_ha_name = DRV_NAME; 2739 sha->dev = dev; 2740 sha->lldd_module = THIS_MODULE; 2741 sha->sas_addr = &hisi_hba->sas_addr[0]; 2742 sha->num_phys = hisi_hba->n_phy; 2743 sha->core.shost = hisi_hba->shost; 2744 2745 for (i = 0; i < hisi_hba->n_phy; i++) { 2746 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2747 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2748 } 2749 2750 if (hisi_sas_debugfs_enable) 2751 hisi_sas_debugfs_init(hisi_hba); 2752 2753 rc = scsi_add_host(shost, dev); 2754 if (rc) 2755 goto err_out_ha; 2756 2757 rc = sas_register_ha(sha); 2758 if (rc) 2759 goto err_out_register_ha; 2760 2761 rc = hisi_hba->hw->hw_init(hisi_hba); 2762 if (rc) 2763 goto err_out_register_ha; 2764 2765 if (hisi_hba->prot_mask) { 2766 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 2767 prot_mask); 2768 scsi_host_set_prot(hisi_hba->shost, prot_mask); 2769 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 2770 scsi_host_set_guard(hisi_hba->shost, 2771 SHOST_DIX_GUARD_CRC); 2772 } 2773 2774 scsi_scan_host(shost); 2775 2776 return 0; 2777 2778 err_out_register_ha: 2779 scsi_remove_host(shost); 2780 err_out_ha: 2781 scsi_host_put(shost); 2782 err_out_regions: 2783 pci_release_regions(pdev); 2784 err_out_disable_device: 2785 pci_disable_device(pdev); 2786 err_out: 2787 return rc; 2788 } 2789 2790 static void 2791 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2792 { 2793 int i; 2794 2795 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2796 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2797 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2798 for (i = 0; i < hisi_hba->queue_count; i++) { 2799 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2800 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2801 2802 free_irq(pci_irq_vector(pdev, nr), cq); 2803 } 2804 pci_free_irq_vectors(pdev); 2805 } 2806 2807 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2808 { 2809 struct device *dev = &pdev->dev; 2810 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2811 struct hisi_hba *hisi_hba = sha->lldd_ha; 2812 struct Scsi_Host *shost = sha->core.shost; 2813 2814 hisi_sas_debugfs_exit(hisi_hba); 2815 2816 if (timer_pending(&hisi_hba->timer)) 2817 del_timer(&hisi_hba->timer); 2818 2819 sas_unregister_ha(sha); 2820 sas_remove_host(sha->core.shost); 2821 2822 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2823 hisi_sas_kill_tasklets(hisi_hba); 2824 pci_release_regions(pdev); 2825 pci_disable_device(pdev); 2826 hisi_sas_free(hisi_hba); 2827 scsi_host_put(shost); 2828 } 2829 2830 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2831 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2832 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2833 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2834 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2835 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2836 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2837 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2838 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2839 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2840 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2841 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2842 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2843 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2844 }; 2845 2846 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2847 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2848 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2849 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2850 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2851 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2852 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2853 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2854 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2855 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2856 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2857 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2858 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2859 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2860 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2861 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2862 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2863 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2864 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2865 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2866 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2867 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2868 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2869 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2870 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2871 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2872 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2873 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2874 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2875 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2876 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2877 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2878 }; 2879 2880 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2881 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2882 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2883 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2884 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2885 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2886 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2887 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2888 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2889 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2890 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2891 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2892 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2893 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2894 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2895 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2896 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2897 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2898 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2899 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2900 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2901 }; 2902 2903 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2904 { 2905 struct device *dev = hisi_hba->dev; 2906 const struct hisi_sas_hw_error *ras_error; 2907 bool need_reset = false; 2908 u32 irq_value; 2909 int i; 2910 2911 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2912 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2913 ras_error = &sas_ras_intr0_nfe[i]; 2914 if (ras_error->irq_msk & irq_value) { 2915 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2916 ras_error->msg, irq_value); 2917 need_reset = true; 2918 } 2919 } 2920 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2921 2922 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2923 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2924 ras_error = &sas_ras_intr1_nfe[i]; 2925 if (ras_error->irq_msk & irq_value) { 2926 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2927 ras_error->msg, irq_value); 2928 need_reset = true; 2929 } 2930 } 2931 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2932 2933 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2934 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2935 ras_error = &sas_ras_intr2_nfe[i]; 2936 if (ras_error->irq_msk & irq_value) { 2937 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2938 ras_error->msg, irq_value); 2939 need_reset = true; 2940 } 2941 } 2942 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2943 2944 return need_reset; 2945 } 2946 2947 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2948 pci_channel_state_t state) 2949 { 2950 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2951 struct hisi_hba *hisi_hba = sha->lldd_ha; 2952 struct device *dev = hisi_hba->dev; 2953 2954 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2955 if (state == pci_channel_io_perm_failure) 2956 return PCI_ERS_RESULT_DISCONNECT; 2957 2958 if (process_non_fatal_error_v3_hw(hisi_hba)) 2959 return PCI_ERS_RESULT_NEED_RESET; 2960 2961 return PCI_ERS_RESULT_CAN_RECOVER; 2962 } 2963 2964 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2965 { 2966 return PCI_ERS_RESULT_RECOVERED; 2967 } 2968 2969 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2970 { 2971 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2972 struct hisi_hba *hisi_hba = sha->lldd_ha; 2973 struct device *dev = hisi_hba->dev; 2974 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2975 2976 dev_info(dev, "PCI error: slot reset callback!!\n"); 2977 queue_work(hisi_hba->wq, &r.work); 2978 wait_for_completion(r.completion); 2979 if (r.done) 2980 return PCI_ERS_RESULT_RECOVERED; 2981 2982 return PCI_ERS_RESULT_DISCONNECT; 2983 } 2984 2985 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 2986 { 2987 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2988 struct hisi_hba *hisi_hba = sha->lldd_ha; 2989 struct device *dev = hisi_hba->dev; 2990 int rc; 2991 2992 dev_info(dev, "FLR prepare\n"); 2993 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2994 hisi_sas_controller_reset_prepare(hisi_hba); 2995 2996 rc = disable_host_v3_hw(hisi_hba); 2997 if (rc) 2998 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 2999 } 3000 3001 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3002 { 3003 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3004 struct hisi_hba *hisi_hba = sha->lldd_ha; 3005 struct device *dev = hisi_hba->dev; 3006 int rc; 3007 3008 hisi_sas_init_mem(hisi_hba); 3009 3010 rc = hw_init_v3_hw(hisi_hba); 3011 if (rc) { 3012 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3013 return; 3014 } 3015 3016 hisi_sas_controller_reset_done(hisi_hba); 3017 dev_info(dev, "FLR done\n"); 3018 } 3019 3020 enum { 3021 /* instances of the controller */ 3022 hip08, 3023 }; 3024 3025 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3026 { 3027 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3028 struct hisi_hba *hisi_hba = sha->lldd_ha; 3029 struct device *dev = hisi_hba->dev; 3030 struct Scsi_Host *shost = hisi_hba->shost; 3031 pci_power_t device_state; 3032 int rc; 3033 3034 if (!pdev->pm_cap) { 3035 dev_err(dev, "PCI PM not supported\n"); 3036 return -ENODEV; 3037 } 3038 3039 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3040 return -1; 3041 3042 scsi_block_requests(shost); 3043 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3044 flush_workqueue(hisi_hba->wq); 3045 3046 rc = disable_host_v3_hw(hisi_hba); 3047 if (rc) { 3048 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3049 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3050 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3051 scsi_unblock_requests(shost); 3052 return rc; 3053 } 3054 3055 hisi_sas_init_mem(hisi_hba); 3056 3057 device_state = pci_choose_state(pdev, state); 3058 dev_warn(dev, "entering operating state [D%d]\n", 3059 device_state); 3060 pci_save_state(pdev); 3061 pci_disable_device(pdev); 3062 pci_set_power_state(pdev, device_state); 3063 3064 hisi_sas_release_tasks(hisi_hba); 3065 3066 sas_suspend_ha(sha); 3067 return 0; 3068 } 3069 3070 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3071 { 3072 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3073 struct hisi_hba *hisi_hba = sha->lldd_ha; 3074 struct Scsi_Host *shost = hisi_hba->shost; 3075 struct device *dev = hisi_hba->dev; 3076 unsigned int rc; 3077 pci_power_t device_state = pdev->current_state; 3078 3079 dev_warn(dev, "resuming from operating state [D%d]\n", 3080 device_state); 3081 pci_set_power_state(pdev, PCI_D0); 3082 pci_enable_wake(pdev, PCI_D0, 0); 3083 pci_restore_state(pdev); 3084 rc = pci_enable_device(pdev); 3085 if (rc) 3086 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3087 3088 pci_set_master(pdev); 3089 scsi_unblock_requests(shost); 3090 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3091 3092 sas_prep_resume_ha(sha); 3093 init_reg_v3_hw(hisi_hba); 3094 hisi_hba->hw->phys_init(hisi_hba); 3095 sas_resume_ha(sha); 3096 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3097 3098 return 0; 3099 } 3100 3101 static const struct pci_device_id sas_v3_pci_table[] = { 3102 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3103 {} 3104 }; 3105 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3106 3107 static const struct pci_error_handlers hisi_sas_err_handler = { 3108 .error_detected = hisi_sas_error_detected_v3_hw, 3109 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 3110 .slot_reset = hisi_sas_slot_reset_v3_hw, 3111 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3112 .reset_done = hisi_sas_reset_done_v3_hw, 3113 }; 3114 3115 static struct pci_driver sas_v3_pci_driver = { 3116 .name = DRV_NAME, 3117 .id_table = sas_v3_pci_table, 3118 .probe = hisi_sas_v3_probe, 3119 .remove = hisi_sas_v3_remove, 3120 .suspend = hisi_sas_v3_suspend, 3121 .resume = hisi_sas_v3_resume, 3122 .err_handler = &hisi_sas_err_handler, 3123 }; 3124 3125 module_pci_driver(sas_v3_pci_driver); 3126 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3127 3128 MODULE_LICENSE("GPL"); 3129 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3130 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3131 MODULE_ALIAS("pci:" DRV_NAME); 3132