1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init */ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define SAS_AXI_USER3 0x50 32 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 33 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 34 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 35 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 36 #define CFG_MAX_TAG 0x68 37 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 38 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 39 #define HGC_GET_ITV_TIME 0x90 40 #define DEVICE_MSG_WORK_MODE 0x94 41 #define OPENA_WT_CONTI_TIME 0x9c 42 #define I_T_NEXUS_LOSS_TIME 0xa0 43 #define MAX_CON_TIME_LIMIT_TIME 0xa4 44 #define BUS_INACTIVE_LIMIT_TIME 0xa8 45 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 46 #define CQ_INT_CONVERGE_EN 0xb0 47 #define CFG_AGING_TIME 0xbc 48 #define HGC_DFX_CFG2 0xc0 49 #define CFG_ABT_SET_QUERY_IPTT 0xd4 50 #define CFG_SET_ABORTED_IPTT_OFF 0 51 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 52 #define CFG_SET_ABORTED_EN_OFF 12 53 #define CFG_ABT_SET_IPTT_DONE 0xd8 54 #define CFG_ABT_SET_IPTT_DONE_OFF 0 55 #define HGC_IOMB_PROC1_STATUS 0x104 56 #define HGC_LM_DFX_STATUS2 0x128 57 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 58 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ 59 HGC_LM_DFX_STATUS2_IOSTLIST_OFF) 60 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 61 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ 62 HGC_LM_DFX_STATUS2_ITCTLIST_OFF) 63 #define HGC_CQE_ECC_ADDR 0x13c 64 #define HGC_CQE_ECC_1B_ADDR_OFF 0 65 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) 66 #define HGC_CQE_ECC_MB_ADDR_OFF 8 67 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) 68 #define HGC_IOST_ECC_ADDR 0x140 69 #define HGC_IOST_ECC_1B_ADDR_OFF 0 70 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) 71 #define HGC_IOST_ECC_MB_ADDR_OFF 16 72 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) 73 #define HGC_DQE_ECC_ADDR 0x144 74 #define HGC_DQE_ECC_1B_ADDR_OFF 0 75 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) 76 #define HGC_DQE_ECC_MB_ADDR_OFF 16 77 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) 78 #define CHNL_INT_STATUS 0x148 79 #define HGC_ITCT_ECC_ADDR 0x150 80 #define HGC_ITCT_ECC_1B_ADDR_OFF 0 81 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ 82 HGC_ITCT_ECC_1B_ADDR_OFF) 83 #define HGC_ITCT_ECC_MB_ADDR_OFF 16 84 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ 85 HGC_ITCT_ECC_MB_ADDR_OFF) 86 #define HGC_AXI_FIFO_ERR_INFO 0x154 87 #define AXI_ERR_INFO_OFF 0 88 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 89 #define FIFO_ERR_INFO_OFF 8 90 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 91 #define INT_COAL_EN 0x19c 92 #define OQ_INT_COAL_TIME 0x1a0 93 #define OQ_INT_COAL_CNT 0x1a4 94 #define ENT_INT_COAL_TIME 0x1a8 95 #define ENT_INT_COAL_CNT 0x1ac 96 #define OQ_INT_SRC 0x1b0 97 #define OQ_INT_SRC_MSK 0x1b4 98 #define ENT_INT_SRC1 0x1b8 99 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 100 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 101 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 102 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 103 #define ENT_INT_SRC2 0x1bc 104 #define ENT_INT_SRC3 0x1c0 105 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 106 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 107 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 108 #define ENT_INT_SRC3_AXI_OFF 11 109 #define ENT_INT_SRC3_FIFO_OFF 12 110 #define ENT_INT_SRC3_LM_OFF 14 111 #define ENT_INT_SRC3_ITC_INT_OFF 15 112 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 113 #define ENT_INT_SRC3_ABT_OFF 16 114 #define ENT_INT_SRC3_DQE_POISON_OFF 18 115 #define ENT_INT_SRC3_IOST_POISON_OFF 19 116 #define ENT_INT_SRC3_ITCT_POISON_OFF 20 117 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21 118 #define ENT_INT_SRC_MSK1 0x1c4 119 #define ENT_INT_SRC_MSK2 0x1c8 120 #define ENT_INT_SRC_MSK3 0x1cc 121 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 122 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 123 #define CHNL_ENT_INT_MSK 0x1d4 124 #define HGC_COM_INT_MSK 0x1d8 125 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 126 #define SAS_ECC_INTR 0x1e8 127 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 128 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 129 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 130 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 131 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4 132 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5 133 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6 134 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7 135 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8 136 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9 137 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 138 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 139 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12 140 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13 141 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14 142 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15 143 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16 144 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17 145 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18 146 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19 147 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20 148 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21 149 #define SAS_ECC_INTR_MSK 0x1ec 150 #define HGC_ERR_STAT_EN 0x238 151 #define CQE_SEND_CNT 0x248 152 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 153 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 154 #define DLVRY_Q_0_DEPTH 0x268 155 #define DLVRY_Q_0_WR_PTR 0x26c 156 #define DLVRY_Q_0_RD_PTR 0x270 157 #define HYPER_STREAM_ID_EN_CFG 0xc80 158 #define OQ0_INT_SRC_MSK 0xc90 159 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 160 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 161 #define COMPL_Q_0_DEPTH 0x4e8 162 #define COMPL_Q_0_WR_PTR 0x4ec 163 #define COMPL_Q_0_RD_PTR 0x4f0 164 #define HGC_RXM_DFX_STATUS14 0xae8 165 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 166 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ 167 HGC_RXM_DFX_STATUS14_MEM0_OFF) 168 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 169 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ 170 HGC_RXM_DFX_STATUS14_MEM1_OFF) 171 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 172 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ 173 HGC_RXM_DFX_STATUS14_MEM2_OFF) 174 #define HGC_RXM_DFX_STATUS15 0xaec 175 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 176 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ 177 HGC_RXM_DFX_STATUS15_MEM3_OFF) 178 #define AWQOS_AWCACHE_CFG 0xc84 179 #define ARQOS_ARCACHE_CFG 0xc88 180 #define HILINK_ERR_DFX 0xe04 181 #define SAS_GPIO_CFG_0 0x1000 182 #define SAS_GPIO_CFG_1 0x1004 183 #define SAS_GPIO_TX_0_1 0x1040 184 #define SAS_CFG_DRIVE_VLD 0x1070 185 186 /* phy registers requiring init */ 187 #define PORT_BASE (0x2000) 188 #define PHY_CFG (PORT_BASE + 0x0) 189 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 190 #define PHY_CFG_ENA_OFF 0 191 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 192 #define PHY_CFG_DC_OPT_OFF 2 193 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 194 #define PHY_CFG_PHY_RST_OFF 3 195 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 196 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 197 #define PHY_CTRL (PORT_BASE + 0x14) 198 #define PHY_CTRL_RESET_OFF 0 199 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 200 #define CMD_HDR_PIR_OFF 8 201 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 202 #define SERDES_CFG (PORT_BASE + 0x1c) 203 #define SL_CFG (PORT_BASE + 0x84) 204 #define AIP_LIMIT (PORT_BASE + 0x90) 205 #define SL_CONTROL (PORT_BASE + 0x94) 206 #define SL_CONTROL_NOTIFY_EN_OFF 0 207 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 208 #define SL_CTA_OFF 17 209 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 210 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 211 #define RX_BCAST_CHG_OFF 1 212 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 213 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 214 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 215 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 216 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 217 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 218 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 219 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 220 #define TXID_AUTO (PORT_BASE + 0xb8) 221 #define CT3_OFF 1 222 #define CT3_MSK (0x1 << CT3_OFF) 223 #define TX_HARDRST_OFF 2 224 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 225 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 226 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 227 #define STP_LINK_TIMER (PORT_BASE + 0x120) 228 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 229 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 230 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 231 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 232 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 233 #define CHL_INT0 (PORT_BASE + 0x1b4) 234 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 235 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 236 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 237 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 238 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 239 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 240 #define CHL_INT0_NOT_RDY_OFF 4 241 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 242 #define CHL_INT0_PHY_RDY_OFF 5 243 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 244 #define CHL_INT1 (PORT_BASE + 0x1b8) 245 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15 246 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16 247 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17 248 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18 249 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 250 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 251 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 252 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 253 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23 254 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24 255 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26 256 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27 257 #define CHL_INT2 (PORT_BASE + 0x1bc) 258 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 259 #define CHL_INT2_RX_DISP_ERR_OFF 28 260 #define CHL_INT2_RX_CODE_ERR_OFF 29 261 #define CHL_INT2_RX_INVLD_DW_OFF 30 262 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 263 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 264 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 265 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 266 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 267 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 268 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 269 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 270 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 271 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 272 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 273 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 274 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 275 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 276 #define DMA_TX_STATUS_BUSY_OFF 0 277 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 278 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 279 #define DMA_RX_STATUS_BUSY_OFF 0 280 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 281 282 #define COARSETUNE_TIME (PORT_BASE + 0x304) 283 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 284 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 285 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 286 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 287 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 288 289 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 290 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 291 #error Max ITCT exceeded 292 #endif 293 294 #define AXI_MASTER_CFG_BASE (0x5000) 295 #define AM_CTRL_GLOBAL (0x0) 296 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 297 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 298 #define AM_CURR_TRANS_RETURN (0x150) 299 300 #define AM_CFG_MAX_TRANS (0x5010) 301 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 302 #define AXI_CFG (0x5100) 303 #define AM_ROB_ECC_ERR_ADDR (0x510c) 304 #define AM_ROB_ECC_ERR_ADDR_OFF 0 305 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff 306 307 /* RAS registers need init */ 308 #define RAS_BASE (0x6000) 309 #define SAS_RAS_INTR0 (RAS_BASE) 310 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 311 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 312 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 313 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 314 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 315 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 316 317 /* HW dma structures */ 318 /* Delivery queue header */ 319 /* dw0 */ 320 #define CMD_HDR_ABORT_FLAG_OFF 0 321 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 322 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 323 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 324 #define CMD_HDR_RESP_REPORT_OFF 5 325 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 326 #define CMD_HDR_TLR_CTRL_OFF 6 327 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 328 #define CMD_HDR_PORT_OFF 18 329 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 330 #define CMD_HDR_PRIORITY_OFF 27 331 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 332 #define CMD_HDR_CMD_OFF 29 333 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 334 /* dw1 */ 335 #define CMD_HDR_UNCON_CMD_OFF 3 336 #define CMD_HDR_DIR_OFF 5 337 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 338 #define CMD_HDR_RESET_OFF 7 339 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 340 #define CMD_HDR_VDTL_OFF 10 341 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 342 #define CMD_HDR_FRAME_TYPE_OFF 11 343 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 344 #define CMD_HDR_DEV_ID_OFF 16 345 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 346 /* dw2 */ 347 #define CMD_HDR_CFL_OFF 0 348 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 349 #define CMD_HDR_NCQ_TAG_OFF 10 350 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 351 #define CMD_HDR_MRFL_OFF 15 352 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 353 #define CMD_HDR_SG_MOD_OFF 24 354 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 355 /* dw3 */ 356 #define CMD_HDR_IPTT_OFF 0 357 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 358 /* dw6 */ 359 #define CMD_HDR_DIF_SGL_LEN_OFF 0 360 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 361 #define CMD_HDR_DATA_SGL_LEN_OFF 16 362 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 363 /* dw7 */ 364 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 365 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 366 #define CMD_HDR_ABORT_IPTT_OFF 16 367 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 368 369 /* Completion header */ 370 /* dw0 */ 371 #define CMPLT_HDR_CMPLT_OFF 0 372 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 373 #define CMPLT_HDR_ERROR_PHASE_OFF 2 374 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 375 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 376 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 377 #define CMPLT_HDR_ERX_OFF 12 378 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 379 #define CMPLT_HDR_ABORT_STAT_OFF 13 380 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 381 /* abort_stat */ 382 #define STAT_IO_NOT_VALID 0x1 383 #define STAT_IO_NO_DEVICE 0x2 384 #define STAT_IO_COMPLETE 0x3 385 #define STAT_IO_ABORTED 0x4 386 /* dw1 */ 387 #define CMPLT_HDR_IPTT_OFF 0 388 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 389 #define CMPLT_HDR_DEV_ID_OFF 16 390 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 391 /* dw3 */ 392 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 393 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 394 395 /* ITCT header */ 396 /* qw0 */ 397 #define ITCT_HDR_DEV_TYPE_OFF 0 398 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 399 #define ITCT_HDR_VALID_OFF 2 400 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 401 #define ITCT_HDR_MCR_OFF 5 402 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 403 #define ITCT_HDR_VLN_OFF 9 404 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 405 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 406 #define ITCT_HDR_AWT_CONTINUE_OFF 25 407 #define ITCT_HDR_PORT_ID_OFF 28 408 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 409 /* qw2 */ 410 #define ITCT_HDR_INLT_OFF 0 411 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 412 #define ITCT_HDR_RTOLT_OFF 48 413 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 414 415 struct hisi_sas_protect_iu_v3_hw { 416 u32 dw0; 417 u32 lbrtcv; 418 u32 lbrtgv; 419 u32 dw3; 420 u32 dw4; 421 u32 dw5; 422 u32 rsv; 423 }; 424 425 struct hisi_sas_complete_v3_hdr { 426 __le32 dw0; 427 __le32 dw1; 428 __le32 act; 429 __le32 dw3; 430 }; 431 432 struct hisi_sas_err_record_v3 { 433 /* dw0 */ 434 __le32 trans_tx_fail_type; 435 436 /* dw1 */ 437 __le32 trans_rx_fail_type; 438 439 /* dw2 */ 440 __le16 dma_tx_err_type; 441 __le16 sipc_rx_err_type; 442 443 /* dw3 */ 444 __le32 dma_rx_err_type; 445 }; 446 447 #define RX_DATA_LEN_UNDERFLOW_OFF 6 448 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 449 450 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 451 #define HISI_SAS_MSI_COUNT_V3_HW 32 452 453 #define DIR_NO_DATA 0 454 #define DIR_TO_INI 1 455 #define DIR_TO_DEVICE 2 456 #define DIR_RESERVED 3 457 458 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 459 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 460 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 461 ((fis.command == ATA_CMD_DEV_RESET) && \ 462 ((fis.control & ATA_SRST) != 0))) 463 464 #define T10_INSRT_EN_OFF 0 465 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 466 #define T10_RMV_EN_OFF 1 467 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 468 #define T10_RPLC_EN_OFF 2 469 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 470 #define T10_CHK_EN_OFF 3 471 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 472 #define INCR_LBRT_OFF 5 473 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 474 #define USR_DATA_BLOCK_SZ_OFF 20 475 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 476 #define T10_CHK_MSK_OFF 16 477 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 478 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 479 480 #define BASE_VECTORS_V3_HW 16 481 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) 482 483 enum { 484 DSM_FUNC_ERR_HANDLE_MSI = 0, 485 }; 486 487 static bool hisi_sas_intr_conv; 488 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 489 490 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 491 static int prot_mask; 492 module_param(prot_mask, int, 0); 493 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 494 495 static bool auto_affine_msi_experimental; 496 module_param(auto_affine_msi_experimental, bool, 0444); 497 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n" 498 "default is off"); 499 500 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 501 { 502 void __iomem *regs = hisi_hba->regs + off; 503 504 return readl(regs); 505 } 506 507 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 508 { 509 void __iomem *regs = hisi_hba->regs + off; 510 511 return readl_relaxed(regs); 512 } 513 514 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 515 { 516 void __iomem *regs = hisi_hba->regs + off; 517 518 writel(val, regs); 519 } 520 521 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 522 u32 off, u32 val) 523 { 524 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 525 526 writel(val, regs); 527 } 528 529 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 530 int phy_no, u32 off) 531 { 532 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 533 534 return readl(regs); 535 } 536 537 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 538 timeout_us) \ 539 ({ \ 540 void __iomem *regs = hisi_hba->regs + off; \ 541 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 542 }) 543 544 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 545 timeout_us) \ 546 ({ \ 547 void __iomem *regs = hisi_hba->regs + off; \ 548 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 549 }) 550 551 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 552 { 553 int i; 554 555 /* Global registers init */ 556 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 557 (u32)((1ULL << hisi_hba->queue_count) - 1)); 558 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0); 559 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 560 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 561 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 562 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 563 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 564 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 565 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 566 hisi_sas_intr_conv); 567 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 568 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 569 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 570 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 571 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 572 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 573 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff); 574 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 575 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 576 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 577 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555); 578 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 579 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 580 for (i = 0; i < hisi_hba->queue_count; i++) 581 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 582 583 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 584 585 for (i = 0; i < hisi_hba->n_phy; i++) { 586 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 587 struct asd_sas_phy *sas_phy = &phy->sas_phy; 588 u32 prog_phy_link_rate = 0x800; 589 590 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 591 SAS_LINK_RATE_1_5_GBPS)) { 592 prog_phy_link_rate = 0x855; 593 } else { 594 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 595 596 prog_phy_link_rate = 597 hisi_sas_get_prog_phy_linkrate_mask(max) | 598 0x800; 599 } 600 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 601 prog_phy_link_rate); 602 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); 603 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 604 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 605 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 606 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 607 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 608 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff); 609 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 610 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 611 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 612 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 613 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 614 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 615 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 616 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 617 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 618 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 619 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME, 620 0x30f4240); 621 /* used for 12G negotiate */ 622 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 623 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 624 } 625 626 for (i = 0; i < hisi_hba->queue_count; i++) { 627 /* Delivery queue */ 628 hisi_sas_write32(hisi_hba, 629 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 630 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 631 632 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 633 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 634 635 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 636 HISI_SAS_QUEUE_SLOTS); 637 638 /* Completion queue */ 639 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 640 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 641 642 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 643 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 644 645 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 646 HISI_SAS_QUEUE_SLOTS); 647 } 648 649 /* itct */ 650 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 651 lower_32_bits(hisi_hba->itct_dma)); 652 653 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 654 upper_32_bits(hisi_hba->itct_dma)); 655 656 /* iost */ 657 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 658 lower_32_bits(hisi_hba->iost_dma)); 659 660 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 661 upper_32_bits(hisi_hba->iost_dma)); 662 663 /* breakpoint */ 664 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 665 lower_32_bits(hisi_hba->breakpoint_dma)); 666 667 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 668 upper_32_bits(hisi_hba->breakpoint_dma)); 669 670 /* SATA broken msg */ 671 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 672 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 673 674 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 675 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 676 677 /* SATA initial fis */ 678 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 679 lower_32_bits(hisi_hba->initial_fis_dma)); 680 681 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 682 upper_32_bits(hisi_hba->initial_fis_dma)); 683 684 /* RAS registers init */ 685 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 686 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 687 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 688 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 689 690 /* LED registers init */ 691 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 692 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 693 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 694 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 695 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 696 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 697 } 698 699 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 700 { 701 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 702 703 cfg &= ~PHY_CFG_DC_OPT_MSK; 704 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 705 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 706 } 707 708 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 709 { 710 struct sas_identify_frame identify_frame; 711 u32 *identify_buffer; 712 713 memset(&identify_frame, 0, sizeof(identify_frame)); 714 identify_frame.dev_type = SAS_END_DEVICE; 715 identify_frame.frame_type = 0; 716 identify_frame._un1 = 1; 717 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 718 identify_frame.target_bits = SAS_PROTOCOL_NONE; 719 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 720 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 721 identify_frame.phy_id = phy_no; 722 identify_buffer = (u32 *)(&identify_frame); 723 724 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 725 __swab32(identify_buffer[0])); 726 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 727 __swab32(identify_buffer[1])); 728 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 729 __swab32(identify_buffer[2])); 730 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 731 __swab32(identify_buffer[3])); 732 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 733 __swab32(identify_buffer[4])); 734 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 735 __swab32(identify_buffer[5])); 736 } 737 738 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 739 struct hisi_sas_device *sas_dev) 740 { 741 struct domain_device *device = sas_dev->sas_device; 742 struct device *dev = hisi_hba->dev; 743 u64 qw0, device_id = sas_dev->device_id; 744 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 745 struct domain_device *parent_dev = device->parent; 746 struct asd_sas_port *sas_port = device->port; 747 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 748 u64 sas_addr; 749 750 memset(itct, 0, sizeof(*itct)); 751 752 /* qw0 */ 753 qw0 = 0; 754 switch (sas_dev->dev_type) { 755 case SAS_END_DEVICE: 756 case SAS_EDGE_EXPANDER_DEVICE: 757 case SAS_FANOUT_EXPANDER_DEVICE: 758 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 759 break; 760 case SAS_SATA_DEV: 761 case SAS_SATA_PENDING: 762 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 763 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 764 else 765 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 766 break; 767 default: 768 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 769 sas_dev->dev_type); 770 } 771 772 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 773 (device->linkrate << ITCT_HDR_MCR_OFF) | 774 (1 << ITCT_HDR_VLN_OFF) | 775 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 776 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 777 (port->id << ITCT_HDR_PORT_ID_OFF)); 778 itct->qw0 = cpu_to_le64(qw0); 779 780 /* qw1 */ 781 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 782 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 783 784 /* qw2 */ 785 if (!dev_is_sata(device)) 786 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 787 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 788 } 789 790 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 791 struct hisi_sas_device *sas_dev) 792 { 793 DECLARE_COMPLETION_ONSTACK(completion); 794 u64 dev_id = sas_dev->device_id; 795 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 796 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 797 798 sas_dev->completion = &completion; 799 800 /* clear the itct interrupt state */ 801 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 802 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 803 ENT_INT_SRC3_ITC_INT_MSK); 804 805 /* clear the itct table */ 806 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 807 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 808 809 wait_for_completion(sas_dev->completion); 810 memset(itct, 0, sizeof(struct hisi_sas_itct)); 811 } 812 813 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 814 struct domain_device *device) 815 { 816 struct hisi_sas_slot *slot, *slot2; 817 struct hisi_sas_device *sas_dev = device->lldd_dev; 818 u32 cfg_abt_set_query_iptt; 819 820 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 821 CFG_ABT_SET_QUERY_IPTT); 822 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 823 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 824 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 825 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 826 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 827 cfg_abt_set_query_iptt); 828 } 829 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 830 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 831 cfg_abt_set_query_iptt); 832 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 833 1 << CFG_ABT_SET_IPTT_DONE_OFF); 834 } 835 836 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 837 { 838 struct device *dev = hisi_hba->dev; 839 int ret; 840 u32 val; 841 842 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 843 844 /* Disable all of the PHYs */ 845 hisi_sas_stop_phys(hisi_hba); 846 udelay(50); 847 848 /* Ensure axi bus idle */ 849 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 850 20000, 1000000); 851 if (ret) { 852 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 853 return -EIO; 854 } 855 856 if (ACPI_HANDLE(dev)) { 857 acpi_status s; 858 859 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 860 if (ACPI_FAILURE(s)) { 861 dev_err(dev, "Reset failed\n"); 862 return -EIO; 863 } 864 } else { 865 dev_err(dev, "no reset method!\n"); 866 return -EINVAL; 867 } 868 869 return 0; 870 } 871 872 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 873 { 874 struct device *dev = hisi_hba->dev; 875 union acpi_object *obj; 876 guid_t guid; 877 int rc; 878 879 rc = reset_hw_v3_hw(hisi_hba); 880 if (rc) { 881 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 882 return rc; 883 } 884 885 msleep(100); 886 init_reg_v3_hw(hisi_hba); 887 888 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) { 889 dev_err(dev, "Parse GUID failed\n"); 890 return -EINVAL; 891 } 892 893 /* Switch over to MSI handling , from PCI AER default */ 894 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, 895 DSM_FUNC_ERR_HANDLE_MSI, NULL); 896 if (!obj) 897 dev_warn(dev, "Switch over to MSI handling failed\n"); 898 else 899 ACPI_FREE(obj); 900 901 return 0; 902 } 903 904 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 905 { 906 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 907 908 cfg |= PHY_CFG_ENA_MSK; 909 cfg &= ~PHY_CFG_PHY_RST_MSK; 910 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 911 } 912 913 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 914 { 915 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 916 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 917 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 918 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 919 BIT(CHL_INT2_RX_INVLD_DW_OFF); 920 u32 state; 921 922 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); 923 924 cfg &= ~PHY_CFG_ENA_MSK; 925 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 926 927 mdelay(50); 928 929 state = hisi_sas_read32(hisi_hba, PHY_STATE); 930 if (state & BIT(phy_no)) { 931 cfg |= PHY_CFG_PHY_RST_MSK; 932 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 933 } 934 935 udelay(1); 936 937 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 938 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 939 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 940 941 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); 942 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); 943 } 944 945 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 946 { 947 config_id_frame_v3_hw(hisi_hba, phy_no); 948 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 949 enable_phy_v3_hw(hisi_hba, phy_no); 950 } 951 952 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 953 { 954 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 955 u32 txid_auto; 956 957 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 958 if (phy->identify.device_type == SAS_END_DEVICE) { 959 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 960 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 961 txid_auto | TX_HARDRST_MSK); 962 } 963 msleep(100); 964 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 965 } 966 967 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 968 { 969 return SAS_LINK_RATE_12_0_GBPS; 970 } 971 972 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 973 { 974 int i; 975 976 for (i = 0; i < hisi_hba->n_phy; i++) { 977 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 978 struct asd_sas_phy *sas_phy = &phy->sas_phy; 979 980 if (!sas_phy->phy->enabled) 981 continue; 982 983 hisi_sas_phy_enable(hisi_hba, i, 1); 984 } 985 } 986 987 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 988 { 989 u32 sl_control; 990 991 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 992 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 993 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 994 msleep(1); 995 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 996 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 997 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 998 } 999 1000 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 1001 { 1002 int i, bitmap = 0; 1003 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1004 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1005 1006 for (i = 0; i < hisi_hba->n_phy; i++) 1007 if (phy_state & BIT(i)) 1008 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 1009 bitmap |= BIT(i); 1010 1011 return bitmap; 1012 } 1013 1014 /** 1015 * The callpath to this function and upto writing the write 1016 * queue pointer should be safe from interruption. 1017 */ 1018 static int 1019 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 1020 { 1021 struct device *dev = hisi_hba->dev; 1022 int queue = dq->id; 1023 u32 r, w; 1024 1025 w = dq->wr_point; 1026 r = hisi_sas_read32_relaxed(hisi_hba, 1027 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 1028 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 1029 dev_warn(dev, "full queue=%d r=%d w=%d\n", 1030 queue, r, w); 1031 return -EAGAIN; 1032 } 1033 1034 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 1035 1036 return w; 1037 } 1038 1039 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 1040 { 1041 struct hisi_hba *hisi_hba = dq->hisi_hba; 1042 struct hisi_sas_slot *s, *s1, *s2 = NULL; 1043 int dlvry_queue = dq->id; 1044 int wp; 1045 1046 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 1047 if (!s->ready) 1048 break; 1049 s2 = s; 1050 list_del(&s->delivery); 1051 } 1052 1053 if (!s2) 1054 return; 1055 1056 /* 1057 * Ensure that memories for slots built on other CPUs is observed. 1058 */ 1059 smp_rmb(); 1060 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 1061 1062 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 1063 } 1064 1065 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 1066 struct hisi_sas_slot *slot, 1067 struct hisi_sas_cmd_hdr *hdr, 1068 struct scatterlist *scatter, 1069 int n_elem) 1070 { 1071 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 1072 struct scatterlist *sg; 1073 int i; 1074 1075 for_each_sg(scatter, sg, n_elem, i) { 1076 struct hisi_sas_sge *entry = &sge_page->sge[i]; 1077 1078 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1079 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1080 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1081 entry->data_off = 0; 1082 } 1083 1084 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 1085 1086 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1087 } 1088 1089 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 1090 struct hisi_sas_slot *slot, 1091 struct hisi_sas_cmd_hdr *hdr, 1092 struct scatterlist *scatter, 1093 int n_elem) 1094 { 1095 struct hisi_sas_sge_dif_page *sge_dif_page; 1096 struct scatterlist *sg; 1097 int i; 1098 1099 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 1100 1101 for_each_sg(scatter, sg, n_elem, i) { 1102 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 1103 1104 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1105 entry->page_ctrl_0 = 0; 1106 entry->page_ctrl_1 = 0; 1107 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1108 entry->data_off = 0; 1109 } 1110 1111 hdr->dif_prd_table_addr = 1112 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1113 1114 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1115 } 1116 1117 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1118 { 1119 unsigned char prot_flags = scsi_cmnd->prot_flags; 1120 1121 if (prot_flags & SCSI_PROT_REF_CHECK) 1122 return T10_CHK_APP_TAG_MSK; 1123 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1124 } 1125 1126 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1127 struct hisi_sas_protect_iu_v3_hw *prot) 1128 { 1129 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1130 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1131 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1132 1133 switch (prot_op) { 1134 case SCSI_PROT_READ_INSERT: 1135 prot->dw0 |= T10_INSRT_EN_MSK; 1136 prot->lbrtgv = lbrt_chk_val; 1137 break; 1138 case SCSI_PROT_READ_STRIP: 1139 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1140 prot->lbrtcv = lbrt_chk_val; 1141 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1142 break; 1143 case SCSI_PROT_READ_PASS: 1144 prot->dw0 |= T10_CHK_EN_MSK; 1145 prot->lbrtcv = lbrt_chk_val; 1146 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1147 break; 1148 case SCSI_PROT_WRITE_INSERT: 1149 prot->dw0 |= T10_INSRT_EN_MSK; 1150 prot->lbrtgv = lbrt_chk_val; 1151 break; 1152 case SCSI_PROT_WRITE_STRIP: 1153 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1154 prot->lbrtcv = lbrt_chk_val; 1155 break; 1156 case SCSI_PROT_WRITE_PASS: 1157 prot->dw0 |= T10_CHK_EN_MSK; 1158 prot->lbrtcv = lbrt_chk_val; 1159 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1160 break; 1161 default: 1162 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1163 break; 1164 } 1165 1166 switch (interval) { 1167 case 512: 1168 break; 1169 case 4096: 1170 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1171 break; 1172 case 520: 1173 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1174 break; 1175 default: 1176 WARN(1, "protection interval (0x%x) invalid\n", 1177 interval); 1178 break; 1179 } 1180 1181 prot->dw0 |= INCR_LBRT_MSK; 1182 } 1183 1184 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1185 struct hisi_sas_slot *slot) 1186 { 1187 struct sas_task *task = slot->task; 1188 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1189 struct domain_device *device = task->dev; 1190 struct hisi_sas_device *sas_dev = device->lldd_dev; 1191 struct hisi_sas_port *port = slot->port; 1192 struct sas_ssp_task *ssp_task = &task->ssp_task; 1193 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1194 struct hisi_sas_tmf_task *tmf = slot->tmf; 1195 int has_data = 0, priority = !!tmf; 1196 unsigned char prot_op; 1197 u8 *buf_cmd; 1198 u32 dw1 = 0, dw2 = 0, len = 0; 1199 1200 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1201 (2 << CMD_HDR_TLR_CTRL_OFF) | 1202 (port->id << CMD_HDR_PORT_OFF) | 1203 (priority << CMD_HDR_PRIORITY_OFF) | 1204 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1205 1206 dw1 = 1 << CMD_HDR_VDTL_OFF; 1207 if (tmf) { 1208 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1209 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1210 } else { 1211 prot_op = scsi_get_prot_op(scsi_cmnd); 1212 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1213 switch (scsi_cmnd->sc_data_direction) { 1214 case DMA_TO_DEVICE: 1215 has_data = 1; 1216 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1217 break; 1218 case DMA_FROM_DEVICE: 1219 has_data = 1; 1220 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1221 break; 1222 default: 1223 dw1 &= ~CMD_HDR_DIR_MSK; 1224 } 1225 } 1226 1227 /* map itct entry */ 1228 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1229 1230 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1231 + 3) / 4) << CMD_HDR_CFL_OFF) | 1232 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1233 (2 << CMD_HDR_SG_MOD_OFF); 1234 hdr->dw2 = cpu_to_le32(dw2); 1235 hdr->transfer_tags = cpu_to_le32(slot->idx); 1236 1237 if (has_data) { 1238 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1239 slot->n_elem); 1240 1241 if (scsi_prot_sg_count(scsi_cmnd)) 1242 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1243 scsi_prot_sglist(scsi_cmnd), 1244 slot->n_elem_dif); 1245 } 1246 1247 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1248 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1249 1250 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1251 sizeof(struct ssp_frame_hdr); 1252 1253 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1254 if (!tmf) { 1255 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1256 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1257 } else { 1258 buf_cmd[10] = tmf->tmf; 1259 switch (tmf->tmf) { 1260 case TMF_ABORT_TASK: 1261 case TMF_QUERY_TASK: 1262 buf_cmd[12] = 1263 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1264 buf_cmd[13] = 1265 tmf->tag_of_task_to_be_managed & 0xff; 1266 break; 1267 default: 1268 break; 1269 } 1270 } 1271 1272 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1273 struct hisi_sas_protect_iu_v3_hw prot; 1274 u8 *buf_cmd_prot; 1275 1276 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1277 dw1 |= CMD_HDR_PIR_MSK; 1278 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1279 sizeof(struct ssp_frame_hdr) + 1280 sizeof(struct ssp_command_iu); 1281 1282 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1283 fill_prot_v3_hw(scsi_cmnd, &prot); 1284 memcpy(buf_cmd_prot, &prot, 1285 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1286 /* 1287 * For READ, we need length of info read to memory, while for 1288 * WRITE we need length of data written to the disk. 1289 */ 1290 if (prot_op == SCSI_PROT_WRITE_INSERT || 1291 prot_op == SCSI_PROT_READ_INSERT || 1292 prot_op == SCSI_PROT_WRITE_PASS || 1293 prot_op == SCSI_PROT_READ_PASS) { 1294 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1295 unsigned int ilog2_interval = ilog2(interval); 1296 1297 len = (task->total_xfer_len >> ilog2_interval) * 8; 1298 } 1299 } 1300 1301 hdr->dw1 = cpu_to_le32(dw1); 1302 1303 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1304 } 1305 1306 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1307 struct hisi_sas_slot *slot) 1308 { 1309 struct sas_task *task = slot->task; 1310 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1311 struct domain_device *device = task->dev; 1312 struct hisi_sas_port *port = slot->port; 1313 struct scatterlist *sg_req; 1314 struct hisi_sas_device *sas_dev = device->lldd_dev; 1315 dma_addr_t req_dma_addr; 1316 unsigned int req_len; 1317 1318 /* req */ 1319 sg_req = &task->smp_task.smp_req; 1320 req_len = sg_dma_len(sg_req); 1321 req_dma_addr = sg_dma_address(sg_req); 1322 1323 /* create header */ 1324 /* dw0 */ 1325 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1326 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1327 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1328 1329 /* map itct entry */ 1330 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1331 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1332 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1333 1334 /* dw2 */ 1335 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1336 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1337 CMD_HDR_MRFL_OFF)); 1338 1339 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1340 1341 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1342 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1343 1344 } 1345 1346 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1347 struct hisi_sas_slot *slot) 1348 { 1349 struct sas_task *task = slot->task; 1350 struct domain_device *device = task->dev; 1351 struct domain_device *parent_dev = device->parent; 1352 struct hisi_sas_device *sas_dev = device->lldd_dev; 1353 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1354 struct asd_sas_port *sas_port = device->port; 1355 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1356 u8 *buf_cmd; 1357 int has_data = 0, hdr_tag = 0; 1358 u32 dw1 = 0, dw2 = 0; 1359 1360 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1361 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 1362 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1363 else 1364 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF); 1365 1366 switch (task->data_dir) { 1367 case DMA_TO_DEVICE: 1368 has_data = 1; 1369 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1370 break; 1371 case DMA_FROM_DEVICE: 1372 has_data = 1; 1373 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1374 break; 1375 default: 1376 dw1 &= ~CMD_HDR_DIR_MSK; 1377 } 1378 1379 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1380 (task->ata_task.fis.control & ATA_SRST)) 1381 dw1 |= 1 << CMD_HDR_RESET_OFF; 1382 1383 dw1 |= (hisi_sas_get_ata_protocol( 1384 &task->ata_task.fis, task->data_dir)) 1385 << CMD_HDR_FRAME_TYPE_OFF; 1386 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1387 1388 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1389 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1390 1391 hdr->dw1 = cpu_to_le32(dw1); 1392 1393 /* dw2 */ 1394 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1395 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1396 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1397 } 1398 1399 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1400 2 << CMD_HDR_SG_MOD_OFF; 1401 hdr->dw2 = cpu_to_le32(dw2); 1402 1403 /* dw3 */ 1404 hdr->transfer_tags = cpu_to_le32(slot->idx); 1405 1406 if (has_data) 1407 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1408 slot->n_elem); 1409 1410 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1411 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1412 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1413 1414 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1415 1416 if (likely(!task->ata_task.device_control_reg_update)) 1417 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1418 /* fill in command FIS */ 1419 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1420 } 1421 1422 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1423 struct hisi_sas_slot *slot, 1424 int device_id, int abort_flag, int tag_to_abort) 1425 { 1426 struct sas_task *task = slot->task; 1427 struct domain_device *dev = task->dev; 1428 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1429 struct hisi_sas_port *port = slot->port; 1430 1431 /* dw0 */ 1432 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/ 1433 (port->id << CMD_HDR_PORT_OFF) | 1434 (dev_is_sata(dev) 1435 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1436 (abort_flag 1437 << CMD_HDR_ABORT_FLAG_OFF)); 1438 1439 /* dw1 */ 1440 hdr->dw1 = cpu_to_le32(device_id 1441 << CMD_HDR_DEV_ID_OFF); 1442 1443 /* dw7 */ 1444 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1445 hdr->transfer_tags = cpu_to_le32(slot->idx); 1446 1447 } 1448 1449 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1450 { 1451 int i; 1452 irqreturn_t res; 1453 u32 context, port_id, link_rate; 1454 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1455 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1456 struct device *dev = hisi_hba->dev; 1457 unsigned long flags; 1458 1459 del_timer(&phy->timer); 1460 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1461 1462 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1463 port_id = (port_id >> (4 * phy_no)) & 0xf; 1464 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1465 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1466 1467 if (port_id == 0xf) { 1468 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1469 res = IRQ_NONE; 1470 goto end; 1471 } 1472 sas_phy->linkrate = link_rate; 1473 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1474 1475 /* Check for SATA dev */ 1476 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1477 if (context & (1 << phy_no)) { 1478 struct hisi_sas_initial_fis *initial_fis; 1479 struct dev_to_host_fis *fis; 1480 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1481 struct Scsi_Host *shost = hisi_hba->shost; 1482 1483 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1484 initial_fis = &hisi_hba->initial_fis[phy_no]; 1485 fis = &initial_fis->fis; 1486 1487 /* check ERR bit of Status Register */ 1488 if (fis->status & ATA_ERR) { 1489 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1490 phy_no, fis->status); 1491 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1492 res = IRQ_NONE; 1493 goto end; 1494 } 1495 1496 sas_phy->oob_mode = SATA_OOB_MODE; 1497 attached_sas_addr[0] = 0x50; 1498 attached_sas_addr[6] = shost->host_no; 1499 attached_sas_addr[7] = phy_no; 1500 memcpy(sas_phy->attached_sas_addr, 1501 attached_sas_addr, 1502 SAS_ADDR_SIZE); 1503 memcpy(sas_phy->frame_rcvd, fis, 1504 sizeof(struct dev_to_host_fis)); 1505 phy->phy_type |= PORT_TYPE_SATA; 1506 phy->identify.device_type = SAS_SATA_DEV; 1507 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1508 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1509 } else { 1510 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1511 struct sas_identify_frame *id = 1512 (struct sas_identify_frame *)frame_rcvd; 1513 1514 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1515 for (i = 0; i < 6; i++) { 1516 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1517 RX_IDAF_DWORD0 + (i * 4)); 1518 frame_rcvd[i] = __swab32(idaf); 1519 } 1520 sas_phy->oob_mode = SAS_OOB_MODE; 1521 memcpy(sas_phy->attached_sas_addr, 1522 &id->sas_addr, 1523 SAS_ADDR_SIZE); 1524 phy->phy_type |= PORT_TYPE_SAS; 1525 phy->identify.device_type = id->dev_type; 1526 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1527 if (phy->identify.device_type == SAS_END_DEVICE) 1528 phy->identify.target_port_protocols = 1529 SAS_PROTOCOL_SSP; 1530 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1531 phy->identify.target_port_protocols = 1532 SAS_PROTOCOL_SMP; 1533 } 1534 1535 phy->port_id = port_id; 1536 phy->phy_attached = 1; 1537 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1538 res = IRQ_HANDLED; 1539 spin_lock_irqsave(&phy->lock, flags); 1540 if (phy->reset_completion) { 1541 phy->in_reset = 0; 1542 complete(phy->reset_completion); 1543 } 1544 spin_unlock_irqrestore(&phy->lock, flags); 1545 end: 1546 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1547 CHL_INT0_SL_PHY_ENABLE_MSK); 1548 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1549 1550 return res; 1551 } 1552 1553 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1554 { 1555 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1556 u32 phy_state, sl_ctrl, txid_auto; 1557 struct device *dev = hisi_hba->dev; 1558 1559 del_timer(&phy->timer); 1560 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1561 1562 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1563 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1564 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1565 1566 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1567 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1568 sl_ctrl&(~SL_CTA_MSK)); 1569 1570 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1571 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1572 txid_auto | CT3_MSK); 1573 1574 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1575 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1576 1577 return IRQ_HANDLED; 1578 } 1579 1580 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1581 { 1582 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1583 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1584 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1585 u32 bcast_status; 1586 1587 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1588 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1589 if ((bcast_status & RX_BCAST_CHG_MSK) && 1590 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1591 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1592 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1593 CHL_INT0_SL_RX_BCST_ACK_MSK); 1594 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1595 1596 return IRQ_HANDLED; 1597 } 1598 1599 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1600 { 1601 struct hisi_hba *hisi_hba = p; 1602 u32 irq_msk; 1603 int phy_no = 0; 1604 irqreturn_t res = IRQ_NONE; 1605 1606 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1607 & 0x11111111; 1608 while (irq_msk) { 1609 if (irq_msk & 1) { 1610 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1611 CHL_INT0); 1612 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1613 int rdy = phy_state & (1 << phy_no); 1614 1615 if (rdy) { 1616 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1617 /* phy up */ 1618 if (phy_up_v3_hw(phy_no, hisi_hba) 1619 == IRQ_HANDLED) 1620 res = IRQ_HANDLED; 1621 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1622 /* phy bcast */ 1623 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1624 == IRQ_HANDLED) 1625 res = IRQ_HANDLED; 1626 } else { 1627 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1628 /* phy down */ 1629 if (phy_down_v3_hw(phy_no, hisi_hba) 1630 == IRQ_HANDLED) 1631 res = IRQ_HANDLED; 1632 } 1633 } 1634 irq_msk >>= 4; 1635 phy_no++; 1636 } 1637 1638 return res; 1639 } 1640 1641 static const struct hisi_sas_hw_error port_axi_error[] = { 1642 { 1643 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF), 1644 .msg = "dmac_tx_ecc_bad_err", 1645 }, 1646 { 1647 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF), 1648 .msg = "dmac_rx_ecc_bad_err", 1649 }, 1650 { 1651 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1652 .msg = "dma_tx_axi_wr_err", 1653 }, 1654 { 1655 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1656 .msg = "dma_tx_axi_rd_err", 1657 }, 1658 { 1659 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1660 .msg = "dma_rx_axi_wr_err", 1661 }, 1662 { 1663 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1664 .msg = "dma_rx_axi_rd_err", 1665 }, 1666 { 1667 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF), 1668 .msg = "dma_tx_fifo_err", 1669 }, 1670 { 1671 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF), 1672 .msg = "dma_rx_fifo_err", 1673 }, 1674 { 1675 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF), 1676 .msg = "dma_tx_axi_ruser_err", 1677 }, 1678 { 1679 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF), 1680 .msg = "dma_rx_axi_ruser_err", 1681 }, 1682 }; 1683 1684 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1685 { 1686 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1687 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1688 struct device *dev = hisi_hba->dev; 1689 int i; 1690 1691 irq_value &= ~irq_msk; 1692 if (!irq_value) 1693 return; 1694 1695 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1696 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1697 1698 if (!(irq_value & error->irq_msk)) 1699 continue; 1700 1701 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1702 error->msg, phy_no, irq_value); 1703 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1704 } 1705 1706 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1707 } 1708 1709 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1710 { 1711 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1712 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1713 struct sas_phy *sphy = sas_phy->phy; 1714 unsigned long flags; 1715 u32 reg_value; 1716 1717 spin_lock_irqsave(&phy->lock, flags); 1718 1719 /* loss dword sync */ 1720 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1721 sphy->loss_of_dword_sync_count += reg_value; 1722 1723 /* phy reset problem */ 1724 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1725 sphy->phy_reset_problem_count += reg_value; 1726 1727 /* invalid dword */ 1728 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1729 sphy->invalid_dword_count += reg_value; 1730 1731 /* disparity err */ 1732 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1733 sphy->running_disparity_error_count += reg_value; 1734 1735 /* code violation error */ 1736 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 1737 phy->code_violation_err_count += reg_value; 1738 1739 spin_unlock_irqrestore(&phy->lock, flags); 1740 } 1741 1742 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1743 { 1744 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1745 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1746 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1747 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1748 struct device *dev = hisi_hba->dev; 1749 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 1750 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 1751 BIT(CHL_INT2_RX_INVLD_DW_OFF); 1752 1753 irq_value &= ~irq_msk; 1754 if (!irq_value) 1755 return; 1756 1757 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1758 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1759 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1760 } 1761 1762 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1763 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1764 STP_LINK_TIMEOUT_STATE); 1765 1766 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1767 phy_no, reg_value); 1768 if (reg_value & BIT(4)) 1769 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1770 } 1771 1772 if (pci_dev->revision > 0x20 && (irq_value & msk)) { 1773 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1774 struct sas_phy *sphy = sas_phy->phy; 1775 1776 phy_get_events_v3_hw(hisi_hba, phy_no); 1777 1778 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) 1779 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no, 1780 sphy->invalid_dword_count); 1781 1782 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF)) 1783 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no, 1784 phy->code_violation_err_count); 1785 1786 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF)) 1787 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no, 1788 sphy->running_disparity_error_count); 1789 } 1790 1791 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1792 (pci_dev->revision == 0x20)) { 1793 u32 reg_value; 1794 int rc; 1795 1796 rc = hisi_sas_read32_poll_timeout_atomic( 1797 HILINK_ERR_DFX, reg_value, 1798 !((reg_value >> 8) & BIT(phy_no)), 1799 1000, 10000); 1800 if (rc) 1801 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1802 } 1803 1804 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1805 } 1806 1807 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1808 { 1809 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1810 1811 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1812 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1813 1814 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1815 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1816 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1817 & (~CHL_INT0_NOT_RDY_MSK)); 1818 } 1819 1820 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1821 { 1822 struct hisi_hba *hisi_hba = p; 1823 u32 irq_msk; 1824 int phy_no = 0; 1825 1826 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1827 & 0xeeeeeeee; 1828 1829 while (irq_msk) { 1830 if (irq_msk & (2 << (phy_no * 4))) 1831 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1832 1833 if (irq_msk & (4 << (phy_no * 4))) 1834 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1835 1836 if (irq_msk & (8 << (phy_no * 4))) 1837 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1838 1839 irq_msk &= ~(0xe << (phy_no * 4)); 1840 phy_no++; 1841 } 1842 1843 return IRQ_HANDLED; 1844 } 1845 1846 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { 1847 { 1848 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), 1849 .msk = HGC_DQE_ECC_MB_ADDR_MSK, 1850 .shift = HGC_DQE_ECC_MB_ADDR_OFF, 1851 .msg = "hgc_dqe_eccbad_intr", 1852 .reg = HGC_DQE_ECC_ADDR, 1853 }, 1854 { 1855 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), 1856 .msk = HGC_IOST_ECC_MB_ADDR_MSK, 1857 .shift = HGC_IOST_ECC_MB_ADDR_OFF, 1858 .msg = "hgc_iost_eccbad_intr", 1859 .reg = HGC_IOST_ECC_ADDR, 1860 }, 1861 { 1862 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), 1863 .msk = HGC_ITCT_ECC_MB_ADDR_MSK, 1864 .shift = HGC_ITCT_ECC_MB_ADDR_OFF, 1865 .msg = "hgc_itct_eccbad_intr", 1866 .reg = HGC_ITCT_ECC_ADDR, 1867 }, 1868 { 1869 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), 1870 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, 1871 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, 1872 .msg = "hgc_iostl_eccbad_intr", 1873 .reg = HGC_LM_DFX_STATUS2, 1874 }, 1875 { 1876 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), 1877 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, 1878 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, 1879 .msg = "hgc_itctl_eccbad_intr", 1880 .reg = HGC_LM_DFX_STATUS2, 1881 }, 1882 { 1883 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), 1884 .msk = HGC_CQE_ECC_MB_ADDR_MSK, 1885 .shift = HGC_CQE_ECC_MB_ADDR_OFF, 1886 .msg = "hgc_cqe_eccbad_intr", 1887 .reg = HGC_CQE_ECC_ADDR, 1888 }, 1889 { 1890 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), 1891 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, 1892 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, 1893 .msg = "rxm_mem0_eccbad_intr", 1894 .reg = HGC_RXM_DFX_STATUS14, 1895 }, 1896 { 1897 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), 1898 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, 1899 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, 1900 .msg = "rxm_mem1_eccbad_intr", 1901 .reg = HGC_RXM_DFX_STATUS14, 1902 }, 1903 { 1904 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), 1905 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, 1906 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, 1907 .msg = "rxm_mem2_eccbad_intr", 1908 .reg = HGC_RXM_DFX_STATUS14, 1909 }, 1910 { 1911 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), 1912 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, 1913 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, 1914 .msg = "rxm_mem3_eccbad_intr", 1915 .reg = HGC_RXM_DFX_STATUS15, 1916 }, 1917 { 1918 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), 1919 .msk = AM_ROB_ECC_ERR_ADDR_MSK, 1920 .shift = AM_ROB_ECC_ERR_ADDR_OFF, 1921 .msg = "ooo_ram_eccbad_intr", 1922 .reg = AM_ROB_ECC_ERR_ADDR, 1923 }, 1924 }; 1925 1926 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, 1927 u32 irq_value) 1928 { 1929 struct device *dev = hisi_hba->dev; 1930 const struct hisi_sas_hw_error *ecc_error; 1931 u32 val; 1932 int i; 1933 1934 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { 1935 ecc_error = &multi_bit_ecc_errors[i]; 1936 if (irq_value & ecc_error->irq_msk) { 1937 val = hisi_sas_read32(hisi_hba, ecc_error->reg); 1938 val &= ecc_error->msk; 1939 val >>= ecc_error->shift; 1940 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", 1941 ecc_error->msg, irq_value, val); 1942 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1943 } 1944 } 1945 } 1946 1947 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba) 1948 { 1949 u32 irq_value, irq_msk; 1950 1951 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); 1952 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff); 1953 1954 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1955 if (irq_value) 1956 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); 1957 1958 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); 1959 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); 1960 } 1961 1962 static const struct hisi_sas_hw_error axi_error[] = { 1963 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1964 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1965 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1966 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1967 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1968 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1969 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1970 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1971 {} 1972 }; 1973 1974 static const struct hisi_sas_hw_error fifo_error[] = { 1975 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1976 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1977 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1978 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1979 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1980 {} 1981 }; 1982 1983 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1984 { 1985 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1986 .msg = "write pointer and depth", 1987 }, 1988 { 1989 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1990 .msg = "iptt no match slot", 1991 }, 1992 { 1993 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1994 .msg = "read pointer and depth", 1995 }, 1996 { 1997 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1998 .reg = HGC_AXI_FIFO_ERR_INFO, 1999 .sub = axi_error, 2000 }, 2001 { 2002 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 2003 .reg = HGC_AXI_FIFO_ERR_INFO, 2004 .sub = fifo_error, 2005 }, 2006 { 2007 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 2008 .msg = "LM add/fetch list", 2009 }, 2010 { 2011 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 2012 .msg = "SAS_HGC_ABT fetch LM list", 2013 }, 2014 { 2015 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF), 2016 .msg = "read dqe poison", 2017 }, 2018 { 2019 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF), 2020 .msg = "read iost poison", 2021 }, 2022 { 2023 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF), 2024 .msg = "read itct poison", 2025 }, 2026 { 2027 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF), 2028 .msg = "read itct ncq poison", 2029 }, 2030 2031 }; 2032 2033 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 2034 { 2035 u32 irq_value, irq_msk; 2036 struct hisi_hba *hisi_hba = p; 2037 struct device *dev = hisi_hba->dev; 2038 struct pci_dev *pdev = hisi_hba->pci_dev; 2039 int i; 2040 2041 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2042 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 2043 2044 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 2045 irq_value &= ~irq_msk; 2046 2047 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 2048 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 2049 2050 if (!(irq_value & error->irq_msk)) 2051 continue; 2052 2053 if (error->sub) { 2054 const struct hisi_sas_hw_error *sub = error->sub; 2055 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 2056 2057 for (; sub->msk || sub->msg; sub++) { 2058 if (!(err_value & sub->msk)) 2059 continue; 2060 2061 dev_err(dev, "%s error (0x%x) found!\n", 2062 sub->msg, irq_value); 2063 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2064 } 2065 } else { 2066 dev_err(dev, "%s error (0x%x) found!\n", 2067 error->msg, irq_value); 2068 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2069 } 2070 2071 if (pdev->revision < 0x21) { 2072 u32 reg_val; 2073 2074 reg_val = hisi_sas_read32(hisi_hba, 2075 AXI_MASTER_CFG_BASE + 2076 AM_CTRL_GLOBAL); 2077 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2078 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2079 AM_CTRL_GLOBAL, reg_val); 2080 } 2081 } 2082 2083 fatal_ecc_int_v3_hw(hisi_hba); 2084 2085 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 2086 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 2087 u32 dev_id = reg_val & ITCT_DEV_MSK; 2088 struct hisi_sas_device *sas_dev = 2089 &hisi_hba->devices[dev_id]; 2090 2091 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 2092 dev_dbg(dev, "clear ITCT ok\n"); 2093 complete(sas_dev->completion); 2094 } 2095 2096 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 2097 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 2098 2099 return IRQ_HANDLED; 2100 } 2101 2102 static void 2103 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 2104 struct hisi_sas_slot *slot) 2105 { 2106 struct task_status_struct *ts = &task->task_status; 2107 struct hisi_sas_complete_v3_hdr *complete_queue = 2108 hisi_hba->complete_hdr[slot->cmplt_queue]; 2109 struct hisi_sas_complete_v3_hdr *complete_hdr = 2110 &complete_queue[slot->cmplt_queue_slot]; 2111 struct hisi_sas_err_record_v3 *record = 2112 hisi_sas_status_buf_addr_mem(slot); 2113 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 2114 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 2115 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 2116 2117 switch (task->task_proto) { 2118 case SAS_PROTOCOL_SSP: 2119 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2120 ts->residual = trans_tx_fail_type; 2121 ts->stat = SAS_DATA_UNDERRUN; 2122 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2123 ts->stat = SAS_QUEUE_FULL; 2124 slot->abort = 1; 2125 } else { 2126 ts->stat = SAS_OPEN_REJECT; 2127 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2128 } 2129 break; 2130 case SAS_PROTOCOL_SATA: 2131 case SAS_PROTOCOL_STP: 2132 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2133 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2134 ts->residual = trans_tx_fail_type; 2135 ts->stat = SAS_DATA_UNDERRUN; 2136 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2137 ts->stat = SAS_PHY_DOWN; 2138 slot->abort = 1; 2139 } else { 2140 ts->stat = SAS_OPEN_REJECT; 2141 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2142 } 2143 hisi_sas_sata_done(task, slot); 2144 break; 2145 case SAS_PROTOCOL_SMP: 2146 ts->stat = SAM_STAT_CHECK_CONDITION; 2147 break; 2148 default: 2149 break; 2150 } 2151 } 2152 2153 static int 2154 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 2155 { 2156 struct sas_task *task = slot->task; 2157 struct hisi_sas_device *sas_dev; 2158 struct device *dev = hisi_hba->dev; 2159 struct task_status_struct *ts; 2160 struct domain_device *device; 2161 struct sas_ha_struct *ha; 2162 enum exec_status sts; 2163 struct hisi_sas_complete_v3_hdr *complete_queue = 2164 hisi_hba->complete_hdr[slot->cmplt_queue]; 2165 struct hisi_sas_complete_v3_hdr *complete_hdr = 2166 &complete_queue[slot->cmplt_queue_slot]; 2167 unsigned long flags; 2168 bool is_internal = slot->is_internal; 2169 u32 dw0, dw1, dw3; 2170 2171 if (unlikely(!task || !task->lldd_task || !task->dev)) 2172 return -EINVAL; 2173 2174 ts = &task->task_status; 2175 device = task->dev; 2176 ha = device->port->ha; 2177 sas_dev = device->lldd_dev; 2178 2179 spin_lock_irqsave(&task->task_state_lock, flags); 2180 task->task_state_flags &= 2181 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 2182 spin_unlock_irqrestore(&task->task_state_lock, flags); 2183 2184 memset(ts, 0, sizeof(*ts)); 2185 ts->resp = SAS_TASK_COMPLETE; 2186 2187 if (unlikely(!sas_dev)) { 2188 dev_dbg(dev, "slot complete: port has not device\n"); 2189 ts->stat = SAS_PHY_DOWN; 2190 goto out; 2191 } 2192 2193 dw0 = le32_to_cpu(complete_hdr->dw0); 2194 dw1 = le32_to_cpu(complete_hdr->dw1); 2195 dw3 = le32_to_cpu(complete_hdr->dw3); 2196 2197 /* 2198 * Use SAS+TMF status codes 2199 */ 2200 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 2201 case STAT_IO_ABORTED: 2202 /* this IO has been aborted by abort command */ 2203 ts->stat = SAS_ABORTED_TASK; 2204 goto out; 2205 case STAT_IO_COMPLETE: 2206 /* internal abort command complete */ 2207 ts->stat = TMF_RESP_FUNC_SUCC; 2208 goto out; 2209 case STAT_IO_NO_DEVICE: 2210 ts->stat = TMF_RESP_FUNC_COMPLETE; 2211 goto out; 2212 case STAT_IO_NOT_VALID: 2213 /* 2214 * abort single IO, the controller can't find the IO 2215 */ 2216 ts->stat = TMF_RESP_FUNC_FAILED; 2217 goto out; 2218 default: 2219 break; 2220 } 2221 2222 /* check for erroneous completion */ 2223 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 2224 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 2225 2226 slot_err_v3_hw(hisi_hba, task, slot); 2227 if (ts->stat != SAS_DATA_UNDERRUN) 2228 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n", 2229 slot->idx, task, sas_dev->device_id, 2230 dw0, dw1, complete_hdr->act, dw3, 2231 error_info[0], error_info[1], 2232 error_info[2], error_info[3]); 2233 if (unlikely(slot->abort)) 2234 return ts->stat; 2235 goto out; 2236 } 2237 2238 switch (task->task_proto) { 2239 case SAS_PROTOCOL_SSP: { 2240 struct ssp_response_iu *iu = 2241 hisi_sas_status_buf_addr_mem(slot) + 2242 sizeof(struct hisi_sas_err_record); 2243 2244 sas_ssp_task_response(dev, task, iu); 2245 break; 2246 } 2247 case SAS_PROTOCOL_SMP: { 2248 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 2249 void *to; 2250 2251 ts->stat = SAM_STAT_GOOD; 2252 to = kmap_atomic(sg_page(sg_resp)); 2253 2254 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 2255 DMA_FROM_DEVICE); 2256 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 2257 DMA_TO_DEVICE); 2258 memcpy(to + sg_resp->offset, 2259 hisi_sas_status_buf_addr_mem(slot) + 2260 sizeof(struct hisi_sas_err_record), 2261 sg_dma_len(sg_resp)); 2262 kunmap_atomic(to); 2263 break; 2264 } 2265 case SAS_PROTOCOL_SATA: 2266 case SAS_PROTOCOL_STP: 2267 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2268 ts->stat = SAM_STAT_GOOD; 2269 hisi_sas_sata_done(task, slot); 2270 break; 2271 default: 2272 ts->stat = SAM_STAT_CHECK_CONDITION; 2273 break; 2274 } 2275 2276 if (!slot->port->port_attached) { 2277 dev_warn(dev, "slot complete: port %d has removed\n", 2278 slot->port->sas_port.id); 2279 ts->stat = SAS_PHY_DOWN; 2280 } 2281 2282 out: 2283 sts = ts->stat; 2284 spin_lock_irqsave(&task->task_state_lock, flags); 2285 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 2286 spin_unlock_irqrestore(&task->task_state_lock, flags); 2287 dev_info(dev, "slot complete: task(%p) aborted\n", task); 2288 return SAS_ABORTED_TASK; 2289 } 2290 task->task_state_flags |= SAS_TASK_STATE_DONE; 2291 spin_unlock_irqrestore(&task->task_state_lock, flags); 2292 hisi_sas_slot_task_free(hisi_hba, task, slot); 2293 2294 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 2295 spin_lock_irqsave(&device->done_lock, flags); 2296 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 2297 spin_unlock_irqrestore(&device->done_lock, flags); 2298 dev_info(dev, "slot complete: task(%p) ignored\n ", 2299 task); 2300 return sts; 2301 } 2302 spin_unlock_irqrestore(&device->done_lock, flags); 2303 } 2304 2305 if (task->task_done) 2306 task->task_done(task); 2307 2308 return sts; 2309 } 2310 2311 static void cq_tasklet_v3_hw(unsigned long val) 2312 { 2313 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 2314 struct hisi_hba *hisi_hba = cq->hisi_hba; 2315 struct hisi_sas_slot *slot; 2316 struct hisi_sas_complete_v3_hdr *complete_queue; 2317 u32 rd_point = cq->rd_point, wr_point; 2318 int queue = cq->id; 2319 2320 complete_queue = hisi_hba->complete_hdr[queue]; 2321 2322 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2323 (0x14 * queue)); 2324 2325 while (rd_point != wr_point) { 2326 struct hisi_sas_complete_v3_hdr *complete_hdr; 2327 struct device *dev = hisi_hba->dev; 2328 u32 dw1; 2329 int iptt; 2330 2331 complete_hdr = &complete_queue[rd_point]; 2332 dw1 = le32_to_cpu(complete_hdr->dw1); 2333 2334 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2335 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2336 slot = &hisi_hba->slot_info[iptt]; 2337 slot->cmplt_queue_slot = rd_point; 2338 slot->cmplt_queue = queue; 2339 slot_complete_v3_hw(hisi_hba, slot); 2340 } else 2341 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2342 2343 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2344 rd_point = 0; 2345 } 2346 2347 /* update rd_point */ 2348 cq->rd_point = rd_point; 2349 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2350 } 2351 2352 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2353 { 2354 struct hisi_sas_cq *cq = p; 2355 struct hisi_hba *hisi_hba = cq->hisi_hba; 2356 int queue = cq->id; 2357 2358 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2359 2360 tasklet_schedule(&cq->tasklet); 2361 2362 return IRQ_HANDLED; 2363 } 2364 2365 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) 2366 { 2367 const struct cpumask *mask; 2368 int queue, cpu; 2369 2370 for (queue = 0; queue < nvecs; queue++) { 2371 struct hisi_sas_cq *cq = &hisi_hba->cq[queue]; 2372 2373 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + 2374 BASE_VECTORS_V3_HW); 2375 if (!mask) 2376 goto fallback; 2377 cq->pci_irq_mask = mask; 2378 for_each_cpu(cpu, mask) 2379 hisi_hba->reply_map[cpu] = queue; 2380 } 2381 return; 2382 2383 fallback: 2384 for_each_possible_cpu(cpu) 2385 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count; 2386 /* Don't clean all CQ masks */ 2387 } 2388 2389 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2390 { 2391 struct device *dev = hisi_hba->dev; 2392 struct pci_dev *pdev = hisi_hba->pci_dev; 2393 int vectors, rc; 2394 int i, k; 2395 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; 2396 2397 if (auto_affine_msi_experimental) { 2398 struct irq_affinity desc = { 2399 .pre_vectors = BASE_VECTORS_V3_HW, 2400 }; 2401 2402 min_msi = MIN_AFFINE_VECTORS_V3_HW; 2403 2404 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids, 2405 sizeof(unsigned int), 2406 GFP_KERNEL); 2407 if (!hisi_hba->reply_map) 2408 return -ENOMEM; 2409 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev, 2410 min_msi, max_msi, 2411 PCI_IRQ_MSI | 2412 PCI_IRQ_AFFINITY, 2413 &desc); 2414 if (vectors < 0) 2415 return -ENOENT; 2416 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW); 2417 } else { 2418 min_msi = max_msi; 2419 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi, 2420 max_msi, PCI_IRQ_MSI); 2421 if (vectors < 0) 2422 return vectors; 2423 } 2424 2425 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; 2426 2427 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2428 int_phy_up_down_bcast_v3_hw, 0, 2429 DRV_NAME " phy", hisi_hba); 2430 if (rc) { 2431 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2432 rc = -ENOENT; 2433 goto free_irq_vectors; 2434 } 2435 2436 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2437 int_chnl_int_v3_hw, 0, 2438 DRV_NAME " channel", hisi_hba); 2439 if (rc) { 2440 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2441 rc = -ENOENT; 2442 goto free_phy_irq; 2443 } 2444 2445 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2446 fatal_axi_int_v3_hw, 0, 2447 DRV_NAME " fatal", hisi_hba); 2448 if (rc) { 2449 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2450 rc = -ENOENT; 2451 goto free_chnl_interrupt; 2452 } 2453 2454 /* Init tasklets for cq only */ 2455 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2456 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2457 struct tasklet_struct *t = &cq->tasklet; 2458 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2459 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2460 2461 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2462 cq_interrupt_v3_hw, irqflags, 2463 DRV_NAME " cq", cq); 2464 if (rc) { 2465 dev_err(dev, "could not request cq%d interrupt, rc=%d\n", 2466 i, rc); 2467 rc = -ENOENT; 2468 goto free_cq_irqs; 2469 } 2470 2471 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2472 } 2473 2474 return 0; 2475 2476 free_cq_irqs: 2477 for (k = 0; k < i; k++) { 2478 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2479 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2480 2481 free_irq(pci_irq_vector(pdev, nr), cq); 2482 } 2483 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2484 free_chnl_interrupt: 2485 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2486 free_phy_irq: 2487 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2488 free_irq_vectors: 2489 pci_free_irq_vectors(pdev); 2490 return rc; 2491 } 2492 2493 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2494 { 2495 int rc; 2496 2497 rc = hw_init_v3_hw(hisi_hba); 2498 if (rc) 2499 return rc; 2500 2501 rc = interrupt_init_v3_hw(hisi_hba); 2502 if (rc) 2503 return rc; 2504 2505 return 0; 2506 } 2507 2508 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2509 struct sas_phy_linkrates *r) 2510 { 2511 enum sas_linkrate max = r->maximum_linkrate; 2512 u32 prog_phy_link_rate = 0x800; 2513 2514 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2515 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2516 prog_phy_link_rate); 2517 } 2518 2519 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2520 { 2521 struct pci_dev *pdev = hisi_hba->pci_dev; 2522 int i; 2523 2524 synchronize_irq(pci_irq_vector(pdev, 1)); 2525 synchronize_irq(pci_irq_vector(pdev, 2)); 2526 synchronize_irq(pci_irq_vector(pdev, 11)); 2527 for (i = 0; i < hisi_hba->queue_count; i++) { 2528 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2529 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2530 } 2531 2532 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2533 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2534 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2535 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2536 2537 for (i = 0; i < hisi_hba->n_phy; i++) { 2538 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2539 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2540 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2541 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2542 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2543 } 2544 } 2545 2546 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2547 { 2548 return hisi_sas_read32(hisi_hba, PHY_STATE); 2549 } 2550 2551 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2552 { 2553 struct device *dev = hisi_hba->dev; 2554 u32 status, reg_val; 2555 int rc; 2556 2557 interrupt_disable_v3_hw(hisi_hba); 2558 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2559 hisi_sas_kill_tasklets(hisi_hba); 2560 2561 hisi_sas_stop_phys(hisi_hba); 2562 2563 mdelay(10); 2564 2565 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2566 AM_CTRL_GLOBAL); 2567 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2568 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2569 AM_CTRL_GLOBAL, reg_val); 2570 2571 /* wait until bus idle */ 2572 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2573 AM_CURR_TRANS_RETURN, status, 2574 status == 0x3, 10, 100); 2575 if (rc) { 2576 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2577 return rc; 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2584 { 2585 struct device *dev = hisi_hba->dev; 2586 int rc; 2587 2588 rc = disable_host_v3_hw(hisi_hba); 2589 if (rc) { 2590 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2591 return rc; 2592 } 2593 2594 hisi_sas_init_mem(hisi_hba); 2595 2596 return hw_init_v3_hw(hisi_hba); 2597 } 2598 2599 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2600 u8 reg_index, u8 reg_count, u8 *write_data) 2601 { 2602 struct device *dev = hisi_hba->dev; 2603 u32 *data = (u32 *)write_data; 2604 int i; 2605 2606 switch (reg_type) { 2607 case SAS_GPIO_REG_TX: 2608 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2609 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2610 reg_index, reg_index + reg_count - 1); 2611 return -EINVAL; 2612 } 2613 2614 for (i = 0; i < reg_count; i++) 2615 hisi_sas_write32(hisi_hba, 2616 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2617 data[i]); 2618 break; 2619 default: 2620 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2621 reg_type); 2622 return -EINVAL; 2623 } 2624 2625 return 0; 2626 } 2627 2628 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2629 int delay_ms, int timeout_ms) 2630 { 2631 struct device *dev = hisi_hba->dev; 2632 int entries, entries_old = 0, time; 2633 2634 for (time = 0; time < timeout_ms; time += delay_ms) { 2635 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2636 if (entries == entries_old) 2637 break; 2638 2639 entries_old = entries; 2640 msleep(delay_ms); 2641 } 2642 2643 if (time >= timeout_ms) 2644 return -ETIMEDOUT; 2645 2646 dev_dbg(dev, "wait commands complete %dms\n", time); 2647 2648 return 0; 2649 } 2650 2651 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2652 struct device_attribute *attr, char *buf) 2653 { 2654 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2655 } 2656 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2657 2658 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2659 { 2660 /* config those registers between enable and disable PHYs */ 2661 hisi_sas_stop_phys(hisi_hba); 2662 2663 if (hisi_hba->intr_coal_ticks == 0 || 2664 hisi_hba->intr_coal_count == 0) { 2665 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2666 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2667 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2668 } else { 2669 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2670 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2671 hisi_hba->intr_coal_ticks); 2672 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2673 hisi_hba->intr_coal_count); 2674 } 2675 phys_init_v3_hw(hisi_hba); 2676 } 2677 2678 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2679 struct device_attribute *attr, 2680 char *buf) 2681 { 2682 struct Scsi_Host *shost = class_to_shost(dev); 2683 struct hisi_hba *hisi_hba = shost_priv(shost); 2684 2685 return scnprintf(buf, PAGE_SIZE, "%u\n", 2686 hisi_hba->intr_coal_ticks); 2687 } 2688 2689 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2690 struct device_attribute *attr, 2691 const char *buf, size_t count) 2692 { 2693 struct Scsi_Host *shost = class_to_shost(dev); 2694 struct hisi_hba *hisi_hba = shost_priv(shost); 2695 u32 intr_coal_ticks; 2696 int ret; 2697 2698 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2699 if (ret) { 2700 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2701 return -EINVAL; 2702 } 2703 2704 if (intr_coal_ticks >= BIT(24)) { 2705 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2706 return -EINVAL; 2707 } 2708 2709 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2710 2711 config_intr_coal_v3_hw(hisi_hba); 2712 2713 return count; 2714 } 2715 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2716 2717 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2718 struct device_attribute 2719 *attr, char *buf) 2720 { 2721 struct Scsi_Host *shost = class_to_shost(dev); 2722 struct hisi_hba *hisi_hba = shost_priv(shost); 2723 2724 return scnprintf(buf, PAGE_SIZE, "%u\n", 2725 hisi_hba->intr_coal_count); 2726 } 2727 2728 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2729 struct device_attribute 2730 *attr, const char *buf, size_t count) 2731 { 2732 struct Scsi_Host *shost = class_to_shost(dev); 2733 struct hisi_hba *hisi_hba = shost_priv(shost); 2734 u32 intr_coal_count; 2735 int ret; 2736 2737 ret = kstrtou32(buf, 10, &intr_coal_count); 2738 if (ret) { 2739 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2740 return -EINVAL; 2741 } 2742 2743 if (intr_coal_count >= BIT(8)) { 2744 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2745 return -EINVAL; 2746 } 2747 2748 hisi_hba->intr_coal_count = intr_coal_count; 2749 2750 config_intr_coal_v3_hw(hisi_hba); 2751 2752 return count; 2753 } 2754 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2755 2756 static struct device_attribute *host_attrs_v3_hw[] = { 2757 &dev_attr_phy_event_threshold, 2758 &dev_attr_intr_conv_v3_hw, 2759 &dev_attr_intr_coal_ticks_v3_hw, 2760 &dev_attr_intr_coal_count_v3_hw, 2761 NULL 2762 }; 2763 2764 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2765 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2766 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2767 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2768 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2769 HISI_SAS_DEBUGFS_REG(SL_CFG), 2770 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2771 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2772 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2773 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2774 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2775 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2776 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2777 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2778 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2779 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2780 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2781 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2782 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2783 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2784 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2785 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2786 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2787 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2788 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2789 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2790 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2791 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2792 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2793 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2794 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2795 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2796 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2797 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2798 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2799 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2800 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2801 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2802 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2803 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2804 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2805 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2806 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2807 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2808 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2809 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2810 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2811 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2812 {} 2813 }; 2814 2815 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2816 .lu = debugfs_port_reg_lu, 2817 .count = 0x100, 2818 .base_off = PORT_BASE, 2819 .read_port_reg = hisi_sas_phy_read32, 2820 }; 2821 2822 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2823 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2824 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2825 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2826 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2827 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2828 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2829 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2830 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2831 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2832 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2833 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2834 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2835 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2836 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2837 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2838 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2839 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2840 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2841 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2842 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2843 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2844 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2845 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2846 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2847 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2848 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2849 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2850 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2851 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2852 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2853 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2854 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2855 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2856 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2857 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2858 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2859 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2860 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2861 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2862 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2863 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2864 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2865 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2866 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2867 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2868 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2869 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2870 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2871 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2872 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2873 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2874 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2875 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2876 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2877 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2878 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2879 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2880 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2881 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2882 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2883 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2884 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2885 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2886 {} 2887 }; 2888 2889 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2890 .lu = debugfs_global_reg_lu, 2891 .count = 0x800, 2892 .read_global_reg = hisi_sas_read32, 2893 }; 2894 2895 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2896 { 2897 struct device *dev = hisi_hba->dev; 2898 2899 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2900 2901 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2902 2903 if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT) 2904 dev_dbg(dev, "Wait commands complete timeout!\n"); 2905 2906 hisi_sas_kill_tasklets(hisi_hba); 2907 } 2908 2909 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2910 { 2911 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2912 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2913 2914 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2915 } 2916 2917 static struct scsi_host_template sht_v3_hw = { 2918 .name = DRV_NAME, 2919 .module = THIS_MODULE, 2920 .queuecommand = sas_queuecommand, 2921 .target_alloc = sas_target_alloc, 2922 .slave_configure = hisi_sas_slave_configure, 2923 .scan_finished = hisi_sas_scan_finished, 2924 .scan_start = hisi_sas_scan_start, 2925 .change_queue_depth = sas_change_queue_depth, 2926 .bios_param = sas_bios_param, 2927 .this_id = -1, 2928 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2929 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2930 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2931 .eh_device_reset_handler = sas_eh_device_reset_handler, 2932 .eh_target_reset_handler = sas_eh_target_reset_handler, 2933 .target_destroy = sas_target_destroy, 2934 .ioctl = sas_ioctl, 2935 .shost_attrs = host_attrs_v3_hw, 2936 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2937 .host_reset = hisi_sas_host_reset, 2938 }; 2939 2940 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2941 .hw_init = hisi_sas_v3_init, 2942 .setup_itct = setup_itct_v3_hw, 2943 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2944 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2945 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2946 .clear_itct = clear_itct_v3_hw, 2947 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2948 .prep_ssp = prep_ssp_v3_hw, 2949 .prep_smp = prep_smp_v3_hw, 2950 .prep_stp = prep_ata_v3_hw, 2951 .prep_abort = prep_abort_v3_hw, 2952 .get_free_slot = get_free_slot_v3_hw, 2953 .start_delivery = start_delivery_v3_hw, 2954 .slot_complete = slot_complete_v3_hw, 2955 .phys_init = phys_init_v3_hw, 2956 .phy_start = start_phy_v3_hw, 2957 .phy_disable = disable_phy_v3_hw, 2958 .phy_hard_reset = phy_hard_reset_v3_hw, 2959 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2960 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2961 .dereg_device = dereg_device_v3_hw, 2962 .soft_reset = soft_reset_v3_hw, 2963 .get_phys_state = get_phys_state_v3_hw, 2964 .get_events = phy_get_events_v3_hw, 2965 .write_gpio = write_gpio_v3_hw, 2966 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2967 .debugfs_reg_global = &debugfs_global_reg, 2968 .debugfs_reg_port = &debugfs_port_reg, 2969 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2970 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2971 }; 2972 2973 static struct Scsi_Host * 2974 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2975 { 2976 struct Scsi_Host *shost; 2977 struct hisi_hba *hisi_hba; 2978 struct device *dev = &pdev->dev; 2979 2980 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2981 if (!shost) { 2982 dev_err(dev, "shost alloc failed\n"); 2983 return NULL; 2984 } 2985 hisi_hba = shost_priv(shost); 2986 2987 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2988 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2989 hisi_hba->hw = &hisi_sas_v3_hw; 2990 hisi_hba->pci_dev = pdev; 2991 hisi_hba->dev = dev; 2992 hisi_hba->shost = shost; 2993 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2994 2995 if (prot_mask & ~HISI_SAS_PROT_MASK) 2996 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2997 prot_mask); 2998 else 2999 hisi_hba->prot_mask = prot_mask; 3000 3001 timer_setup(&hisi_hba->timer, NULL, 0); 3002 3003 if (hisi_sas_get_fw_info(hisi_hba) < 0) 3004 goto err_out; 3005 3006 if (hisi_sas_alloc(hisi_hba)) { 3007 hisi_sas_free(hisi_hba); 3008 goto err_out; 3009 } 3010 3011 return shost; 3012 err_out: 3013 scsi_host_put(shost); 3014 dev_err(dev, "shost alloc failed\n"); 3015 return NULL; 3016 } 3017 3018 static int 3019 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3020 { 3021 struct Scsi_Host *shost; 3022 struct hisi_hba *hisi_hba; 3023 struct device *dev = &pdev->dev; 3024 struct asd_sas_phy **arr_phy; 3025 struct asd_sas_port **arr_port; 3026 struct sas_ha_struct *sha; 3027 int rc, phy_nr, port_nr, i; 3028 3029 rc = pci_enable_device(pdev); 3030 if (rc) 3031 goto err_out; 3032 3033 pci_set_master(pdev); 3034 3035 rc = pci_request_regions(pdev, DRV_NAME); 3036 if (rc) 3037 goto err_out_disable_device; 3038 3039 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3040 if (rc) 3041 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3042 if (rc) { 3043 dev_err(dev, "No usable DMA addressing method\n"); 3044 rc = -ENODEV; 3045 goto err_out_regions; 3046 } 3047 3048 shost = hisi_sas_shost_alloc_pci(pdev); 3049 if (!shost) { 3050 rc = -ENOMEM; 3051 goto err_out_regions; 3052 } 3053 3054 sha = SHOST_TO_SAS_HA(shost); 3055 hisi_hba = shost_priv(shost); 3056 dev_set_drvdata(dev, sha); 3057 3058 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 3059 if (!hisi_hba->regs) { 3060 dev_err(dev, "cannot map register\n"); 3061 rc = -ENOMEM; 3062 goto err_out_ha; 3063 } 3064 3065 phy_nr = port_nr = hisi_hba->n_phy; 3066 3067 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 3068 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 3069 if (!arr_phy || !arr_port) { 3070 rc = -ENOMEM; 3071 goto err_out_ha; 3072 } 3073 3074 sha->sas_phy = arr_phy; 3075 sha->sas_port = arr_port; 3076 sha->core.shost = shost; 3077 sha->lldd_ha = hisi_hba; 3078 3079 shost->transportt = hisi_sas_stt; 3080 shost->max_id = HISI_SAS_MAX_DEVICES; 3081 shost->max_lun = ~0; 3082 shost->max_channel = 1; 3083 shost->max_cmd_len = 16; 3084 shost->can_queue = hisi_hba->hw->max_command_entries - 3085 HISI_SAS_RESERVED_IPTT_CNT; 3086 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 3087 HISI_SAS_RESERVED_IPTT_CNT; 3088 3089 sha->sas_ha_name = DRV_NAME; 3090 sha->dev = dev; 3091 sha->lldd_module = THIS_MODULE; 3092 sha->sas_addr = &hisi_hba->sas_addr[0]; 3093 sha->num_phys = hisi_hba->n_phy; 3094 sha->core.shost = hisi_hba->shost; 3095 3096 for (i = 0; i < hisi_hba->n_phy; i++) { 3097 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 3098 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 3099 } 3100 3101 if (hisi_hba->prot_mask) { 3102 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 3103 prot_mask); 3104 scsi_host_set_prot(hisi_hba->shost, prot_mask); 3105 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 3106 scsi_host_set_guard(hisi_hba->shost, 3107 SHOST_DIX_GUARD_CRC); 3108 } 3109 3110 if (hisi_sas_debugfs_enable) 3111 hisi_sas_debugfs_init(hisi_hba); 3112 3113 rc = scsi_add_host(shost, dev); 3114 if (rc) 3115 goto err_out_ha; 3116 3117 rc = sas_register_ha(sha); 3118 if (rc) 3119 goto err_out_register_ha; 3120 3121 rc = hisi_hba->hw->hw_init(hisi_hba); 3122 if (rc) 3123 goto err_out_register_ha; 3124 3125 scsi_scan_host(shost); 3126 3127 return 0; 3128 3129 err_out_register_ha: 3130 scsi_remove_host(shost); 3131 err_out_ha: 3132 scsi_host_put(shost); 3133 err_out_regions: 3134 pci_release_regions(pdev); 3135 err_out_disable_device: 3136 pci_disable_device(pdev); 3137 err_out: 3138 return rc; 3139 } 3140 3141 static void 3142 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 3143 { 3144 int i; 3145 3146 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 3147 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 3148 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 3149 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 3150 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 3151 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 3152 3153 free_irq(pci_irq_vector(pdev, nr), cq); 3154 } 3155 pci_free_irq_vectors(pdev); 3156 } 3157 3158 static void hisi_sas_v3_remove(struct pci_dev *pdev) 3159 { 3160 struct device *dev = &pdev->dev; 3161 struct sas_ha_struct *sha = dev_get_drvdata(dev); 3162 struct hisi_hba *hisi_hba = sha->lldd_ha; 3163 struct Scsi_Host *shost = sha->core.shost; 3164 3165 hisi_sas_debugfs_exit(hisi_hba); 3166 3167 if (timer_pending(&hisi_hba->timer)) 3168 del_timer(&hisi_hba->timer); 3169 3170 sas_unregister_ha(sha); 3171 sas_remove_host(sha->core.shost); 3172 3173 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 3174 hisi_sas_kill_tasklets(hisi_hba); 3175 pci_release_regions(pdev); 3176 pci_disable_device(pdev); 3177 hisi_sas_free(hisi_hba); 3178 scsi_host_put(shost); 3179 } 3180 3181 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 3182 { 3183 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3184 struct hisi_hba *hisi_hba = sha->lldd_ha; 3185 struct device *dev = hisi_hba->dev; 3186 int rc; 3187 3188 dev_info(dev, "FLR prepare\n"); 3189 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3190 hisi_sas_controller_reset_prepare(hisi_hba); 3191 3192 rc = disable_host_v3_hw(hisi_hba); 3193 if (rc) 3194 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 3195 } 3196 3197 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3198 { 3199 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3200 struct hisi_hba *hisi_hba = sha->lldd_ha; 3201 struct device *dev = hisi_hba->dev; 3202 int rc; 3203 3204 hisi_sas_init_mem(hisi_hba); 3205 3206 rc = hw_init_v3_hw(hisi_hba); 3207 if (rc) { 3208 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3209 return; 3210 } 3211 3212 hisi_sas_controller_reset_done(hisi_hba); 3213 dev_info(dev, "FLR done\n"); 3214 } 3215 3216 enum { 3217 /* instances of the controller */ 3218 hip08, 3219 }; 3220 3221 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3222 { 3223 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3224 struct hisi_hba *hisi_hba = sha->lldd_ha; 3225 struct device *dev = hisi_hba->dev; 3226 struct Scsi_Host *shost = hisi_hba->shost; 3227 pci_power_t device_state; 3228 int rc; 3229 3230 if (!pdev->pm_cap) { 3231 dev_err(dev, "PCI PM not supported\n"); 3232 return -ENODEV; 3233 } 3234 3235 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3236 return -1; 3237 3238 scsi_block_requests(shost); 3239 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3240 flush_workqueue(hisi_hba->wq); 3241 3242 rc = disable_host_v3_hw(hisi_hba); 3243 if (rc) { 3244 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3245 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3246 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3247 scsi_unblock_requests(shost); 3248 return rc; 3249 } 3250 3251 hisi_sas_init_mem(hisi_hba); 3252 3253 device_state = pci_choose_state(pdev, state); 3254 dev_warn(dev, "entering operating state [D%d]\n", 3255 device_state); 3256 pci_save_state(pdev); 3257 pci_disable_device(pdev); 3258 pci_set_power_state(pdev, device_state); 3259 3260 hisi_sas_release_tasks(hisi_hba); 3261 3262 sas_suspend_ha(sha); 3263 return 0; 3264 } 3265 3266 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3267 { 3268 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3269 struct hisi_hba *hisi_hba = sha->lldd_ha; 3270 struct Scsi_Host *shost = hisi_hba->shost; 3271 struct device *dev = hisi_hba->dev; 3272 unsigned int rc; 3273 pci_power_t device_state = pdev->current_state; 3274 3275 dev_warn(dev, "resuming from operating state [D%d]\n", 3276 device_state); 3277 pci_set_power_state(pdev, PCI_D0); 3278 pci_enable_wake(pdev, PCI_D0, 0); 3279 pci_restore_state(pdev); 3280 rc = pci_enable_device(pdev); 3281 if (rc) 3282 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3283 3284 pci_set_master(pdev); 3285 scsi_unblock_requests(shost); 3286 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3287 3288 sas_prep_resume_ha(sha); 3289 init_reg_v3_hw(hisi_hba); 3290 hisi_hba->hw->phys_init(hisi_hba); 3291 sas_resume_ha(sha); 3292 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3293 3294 return 0; 3295 } 3296 3297 static const struct pci_device_id sas_v3_pci_table[] = { 3298 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3299 {} 3300 }; 3301 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3302 3303 static const struct pci_error_handlers hisi_sas_err_handler = { 3304 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3305 .reset_done = hisi_sas_reset_done_v3_hw, 3306 }; 3307 3308 static struct pci_driver sas_v3_pci_driver = { 3309 .name = DRV_NAME, 3310 .id_table = sas_v3_pci_table, 3311 .probe = hisi_sas_v3_probe, 3312 .remove = hisi_sas_v3_remove, 3313 .suspend = hisi_sas_v3_suspend, 3314 .resume = hisi_sas_v3_resume, 3315 .err_handler = &hisi_sas_err_handler, 3316 }; 3317 3318 module_pci_driver(sas_v3_pci_driver); 3319 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3320 3321 MODULE_LICENSE("GPL"); 3322 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3323 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3324 MODULE_ALIAS("pci:" DRV_NAME); 3325