1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PHY_CFG_PHY_RST_OFF 3 125 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 126 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 127 #define PHY_CTRL (PORT_BASE + 0x14) 128 #define PHY_CTRL_RESET_OFF 0 129 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 130 #define CMD_HDR_PIR_OFF 8 131 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 132 #define SL_CFG (PORT_BASE + 0x84) 133 #define AIP_LIMIT (PORT_BASE + 0x90) 134 #define SL_CONTROL (PORT_BASE + 0x94) 135 #define SL_CONTROL_NOTIFY_EN_OFF 0 136 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 137 #define SL_CTA_OFF 17 138 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 139 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 140 #define RX_BCAST_CHG_OFF 1 141 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 142 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 143 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 144 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 145 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 146 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 147 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 148 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 149 #define TXID_AUTO (PORT_BASE + 0xb8) 150 #define CT3_OFF 1 151 #define CT3_MSK (0x1 << CT3_OFF) 152 #define TX_HARDRST_OFF 2 153 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 154 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 155 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 156 #define STP_LINK_TIMER (PORT_BASE + 0x120) 157 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 158 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 159 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 160 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 161 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 162 #define CHL_INT0 (PORT_BASE + 0x1b4) 163 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 164 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 165 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 166 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 167 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 168 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 169 #define CHL_INT0_NOT_RDY_OFF 4 170 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 171 #define CHL_INT0_PHY_RDY_OFF 5 172 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 173 #define CHL_INT1 (PORT_BASE + 0x1b8) 174 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 175 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 176 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 177 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 178 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 179 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 180 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 181 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 182 #define CHL_INT2 (PORT_BASE + 0x1bc) 183 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 184 #define CHL_INT2_RX_INVLD_DW_OFF 30 185 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 186 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 189 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 190 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 191 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 192 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 193 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 194 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 195 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 196 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 197 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 198 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 199 #define DMA_TX_STATUS_BUSY_OFF 0 200 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 201 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 202 #define DMA_RX_STATUS_BUSY_OFF 0 203 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 204 205 #define COARSETUNE_TIME (PORT_BASE + 0x304) 206 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 207 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 208 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 209 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 210 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 211 212 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 213 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 214 #error Max ITCT exceeded 215 #endif 216 217 #define AXI_MASTER_CFG_BASE (0x5000) 218 #define AM_CTRL_GLOBAL (0x0) 219 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 220 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 221 #define AM_CURR_TRANS_RETURN (0x150) 222 223 #define AM_CFG_MAX_TRANS (0x5010) 224 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 225 #define AXI_CFG (0x5100) 226 #define AM_ROB_ECC_ERR_ADDR (0x510c) 227 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 228 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 229 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 230 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 231 232 /* RAS registers need init */ 233 #define RAS_BASE (0x6000) 234 #define SAS_RAS_INTR0 (RAS_BASE) 235 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 236 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 237 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 238 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 239 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 240 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 241 242 /* HW dma structures */ 243 /* Delivery queue header */ 244 /* dw0 */ 245 #define CMD_HDR_ABORT_FLAG_OFF 0 246 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 247 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 248 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 249 #define CMD_HDR_RESP_REPORT_OFF 5 250 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 251 #define CMD_HDR_TLR_CTRL_OFF 6 252 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 253 #define CMD_HDR_PORT_OFF 18 254 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 255 #define CMD_HDR_PRIORITY_OFF 27 256 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 257 #define CMD_HDR_CMD_OFF 29 258 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 259 /* dw1 */ 260 #define CMD_HDR_UNCON_CMD_OFF 3 261 #define CMD_HDR_DIR_OFF 5 262 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 263 #define CMD_HDR_RESET_OFF 7 264 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 265 #define CMD_HDR_VDTL_OFF 10 266 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 267 #define CMD_HDR_FRAME_TYPE_OFF 11 268 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 269 #define CMD_HDR_DEV_ID_OFF 16 270 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 271 /* dw2 */ 272 #define CMD_HDR_CFL_OFF 0 273 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 274 #define CMD_HDR_NCQ_TAG_OFF 10 275 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 276 #define CMD_HDR_MRFL_OFF 15 277 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 278 #define CMD_HDR_SG_MOD_OFF 24 279 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 280 /* dw3 */ 281 #define CMD_HDR_IPTT_OFF 0 282 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 283 /* dw6 */ 284 #define CMD_HDR_DIF_SGL_LEN_OFF 0 285 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 286 #define CMD_HDR_DATA_SGL_LEN_OFF 16 287 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 288 /* dw7 */ 289 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 290 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 291 #define CMD_HDR_ABORT_IPTT_OFF 16 292 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 293 294 /* Completion header */ 295 /* dw0 */ 296 #define CMPLT_HDR_CMPLT_OFF 0 297 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 298 #define CMPLT_HDR_ERROR_PHASE_OFF 2 299 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 300 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 301 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 302 #define CMPLT_HDR_ERX_OFF 12 303 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 304 #define CMPLT_HDR_ABORT_STAT_OFF 13 305 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 306 /* abort_stat */ 307 #define STAT_IO_NOT_VALID 0x1 308 #define STAT_IO_NO_DEVICE 0x2 309 #define STAT_IO_COMPLETE 0x3 310 #define STAT_IO_ABORTED 0x4 311 /* dw1 */ 312 #define CMPLT_HDR_IPTT_OFF 0 313 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 314 #define CMPLT_HDR_DEV_ID_OFF 16 315 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 316 /* dw3 */ 317 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 318 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 319 320 /* ITCT header */ 321 /* qw0 */ 322 #define ITCT_HDR_DEV_TYPE_OFF 0 323 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 324 #define ITCT_HDR_VALID_OFF 2 325 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 326 #define ITCT_HDR_MCR_OFF 5 327 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 328 #define ITCT_HDR_VLN_OFF 9 329 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 330 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 331 #define ITCT_HDR_AWT_CONTINUE_OFF 25 332 #define ITCT_HDR_PORT_ID_OFF 28 333 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 334 /* qw2 */ 335 #define ITCT_HDR_INLT_OFF 0 336 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 337 #define ITCT_HDR_RTOLT_OFF 48 338 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 339 340 struct hisi_sas_protect_iu_v3_hw { 341 u32 dw0; 342 u32 lbrtcv; 343 u32 lbrtgv; 344 u32 dw3; 345 u32 dw4; 346 u32 dw5; 347 u32 rsv; 348 }; 349 350 struct hisi_sas_complete_v3_hdr { 351 __le32 dw0; 352 __le32 dw1; 353 __le32 act; 354 __le32 dw3; 355 }; 356 357 struct hisi_sas_err_record_v3 { 358 /* dw0 */ 359 __le32 trans_tx_fail_type; 360 361 /* dw1 */ 362 __le32 trans_rx_fail_type; 363 364 /* dw2 */ 365 __le16 dma_tx_err_type; 366 __le16 sipc_rx_err_type; 367 368 /* dw3 */ 369 __le32 dma_rx_err_type; 370 }; 371 372 #define RX_DATA_LEN_UNDERFLOW_OFF 6 373 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 374 375 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 376 #define HISI_SAS_MSI_COUNT_V3_HW 32 377 378 #define DIR_NO_DATA 0 379 #define DIR_TO_INI 1 380 #define DIR_TO_DEVICE 2 381 #define DIR_RESERVED 3 382 383 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 384 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 385 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 386 ((fis.command == ATA_CMD_DEV_RESET) && \ 387 ((fis.control & ATA_SRST) != 0))) 388 389 #define T10_INSRT_EN_OFF 0 390 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 391 #define T10_RMV_EN_OFF 1 392 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 393 #define T10_RPLC_EN_OFF 2 394 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 395 #define T10_CHK_EN_OFF 3 396 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 397 #define INCR_LBRT_OFF 5 398 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 399 #define USR_DATA_BLOCK_SZ_OFF 20 400 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 401 #define T10_CHK_MSK_OFF 16 402 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 403 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 404 405 #define BASE_VECTORS_V3_HW 16 406 407 static bool hisi_sas_intr_conv; 408 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 409 410 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 411 static int prot_mask; 412 module_param(prot_mask, int, 0); 413 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 414 415 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 416 { 417 void __iomem *regs = hisi_hba->regs + off; 418 419 return readl(regs); 420 } 421 422 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 423 { 424 void __iomem *regs = hisi_hba->regs + off; 425 426 return readl_relaxed(regs); 427 } 428 429 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 430 { 431 void __iomem *regs = hisi_hba->regs + off; 432 433 writel(val, regs); 434 } 435 436 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 437 u32 off, u32 val) 438 { 439 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 440 441 writel(val, regs); 442 } 443 444 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 445 int phy_no, u32 off) 446 { 447 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 448 449 return readl(regs); 450 } 451 452 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 453 timeout_us) \ 454 ({ \ 455 void __iomem *regs = hisi_hba->regs + off; \ 456 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 457 }) 458 459 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 460 timeout_us) \ 461 ({ \ 462 void __iomem *regs = hisi_hba->regs + off; \ 463 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 464 }) 465 466 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 467 { 468 struct pci_dev *pdev = hisi_hba->pci_dev; 469 int i; 470 471 /* Global registers init */ 472 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 473 (u32)((1ULL << hisi_hba->queue_count) - 1)); 474 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 475 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 476 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 477 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 478 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 479 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 480 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 481 hisi_sas_intr_conv); 482 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 483 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 484 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 485 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 486 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 487 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 488 if (pdev->revision >= 0x21) 489 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff); 490 else 491 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 492 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 493 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 494 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 495 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 496 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 497 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 498 for (i = 0; i < hisi_hba->queue_count; i++) 499 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 500 501 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 502 503 for (i = 0; i < hisi_hba->n_phy; i++) { 504 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 505 struct asd_sas_phy *sas_phy = &phy->sas_phy; 506 u32 prog_phy_link_rate = 0x800; 507 508 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 509 SAS_LINK_RATE_1_5_GBPS)) { 510 prog_phy_link_rate = 0x855; 511 } else { 512 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 513 514 prog_phy_link_rate = 515 hisi_sas_get_prog_phy_linkrate_mask(max) | 516 0x800; 517 } 518 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 519 prog_phy_link_rate); 520 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 521 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 522 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 523 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 524 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 525 if (pdev->revision >= 0x21) 526 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 527 0xffffffff); 528 else 529 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 530 0xff87ffff); 531 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 532 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 533 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 534 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 535 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 536 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 537 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 538 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 539 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 540 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 541 /* used for 12G negotiate */ 542 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 543 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 544 } 545 546 for (i = 0; i < hisi_hba->queue_count; i++) { 547 /* Delivery queue */ 548 hisi_sas_write32(hisi_hba, 549 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 550 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 551 552 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 553 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 554 555 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 556 HISI_SAS_QUEUE_SLOTS); 557 558 /* Completion queue */ 559 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 560 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 561 562 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 563 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 564 565 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 566 HISI_SAS_QUEUE_SLOTS); 567 } 568 569 /* itct */ 570 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 571 lower_32_bits(hisi_hba->itct_dma)); 572 573 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 574 upper_32_bits(hisi_hba->itct_dma)); 575 576 /* iost */ 577 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 578 lower_32_bits(hisi_hba->iost_dma)); 579 580 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 581 upper_32_bits(hisi_hba->iost_dma)); 582 583 /* breakpoint */ 584 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 585 lower_32_bits(hisi_hba->breakpoint_dma)); 586 587 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 588 upper_32_bits(hisi_hba->breakpoint_dma)); 589 590 /* SATA broken msg */ 591 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 592 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 593 594 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 595 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 596 597 /* SATA initial fis */ 598 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 599 lower_32_bits(hisi_hba->initial_fis_dma)); 600 601 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 602 upper_32_bits(hisi_hba->initial_fis_dma)); 603 604 /* RAS registers init */ 605 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 606 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 607 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 608 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 609 610 /* LED registers init */ 611 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 612 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 613 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 614 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 615 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 616 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 617 } 618 619 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 620 { 621 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 622 623 cfg &= ~PHY_CFG_DC_OPT_MSK; 624 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 625 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 626 } 627 628 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 629 { 630 struct sas_identify_frame identify_frame; 631 u32 *identify_buffer; 632 633 memset(&identify_frame, 0, sizeof(identify_frame)); 634 identify_frame.dev_type = SAS_END_DEVICE; 635 identify_frame.frame_type = 0; 636 identify_frame._un1 = 1; 637 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 638 identify_frame.target_bits = SAS_PROTOCOL_NONE; 639 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 640 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 641 identify_frame.phy_id = phy_no; 642 identify_buffer = (u32 *)(&identify_frame); 643 644 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 645 __swab32(identify_buffer[0])); 646 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 647 __swab32(identify_buffer[1])); 648 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 649 __swab32(identify_buffer[2])); 650 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 651 __swab32(identify_buffer[3])); 652 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 653 __swab32(identify_buffer[4])); 654 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 655 __swab32(identify_buffer[5])); 656 } 657 658 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 659 struct hisi_sas_device *sas_dev) 660 { 661 struct domain_device *device = sas_dev->sas_device; 662 struct device *dev = hisi_hba->dev; 663 u64 qw0, device_id = sas_dev->device_id; 664 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 665 struct domain_device *parent_dev = device->parent; 666 struct asd_sas_port *sas_port = device->port; 667 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 668 u64 sas_addr; 669 670 memset(itct, 0, sizeof(*itct)); 671 672 /* qw0 */ 673 qw0 = 0; 674 switch (sas_dev->dev_type) { 675 case SAS_END_DEVICE: 676 case SAS_EDGE_EXPANDER_DEVICE: 677 case SAS_FANOUT_EXPANDER_DEVICE: 678 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 679 break; 680 case SAS_SATA_DEV: 681 case SAS_SATA_PENDING: 682 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 683 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 684 else 685 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 686 break; 687 default: 688 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 689 sas_dev->dev_type); 690 } 691 692 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 693 (device->linkrate << ITCT_HDR_MCR_OFF) | 694 (1 << ITCT_HDR_VLN_OFF) | 695 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 696 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 697 (port->id << ITCT_HDR_PORT_ID_OFF)); 698 itct->qw0 = cpu_to_le64(qw0); 699 700 /* qw1 */ 701 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 702 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 703 704 /* qw2 */ 705 if (!dev_is_sata(device)) 706 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 707 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 708 } 709 710 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 711 struct hisi_sas_device *sas_dev) 712 { 713 DECLARE_COMPLETION_ONSTACK(completion); 714 u64 dev_id = sas_dev->device_id; 715 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 716 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 717 718 sas_dev->completion = &completion; 719 720 /* clear the itct interrupt state */ 721 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 722 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 723 ENT_INT_SRC3_ITC_INT_MSK); 724 725 /* clear the itct table*/ 726 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 727 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 728 729 wait_for_completion(sas_dev->completion); 730 memset(itct, 0, sizeof(struct hisi_sas_itct)); 731 } 732 733 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 734 struct domain_device *device) 735 { 736 struct hisi_sas_slot *slot, *slot2; 737 struct hisi_sas_device *sas_dev = device->lldd_dev; 738 u32 cfg_abt_set_query_iptt; 739 740 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 741 CFG_ABT_SET_QUERY_IPTT); 742 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 743 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 744 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 745 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 746 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 747 cfg_abt_set_query_iptt); 748 } 749 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 750 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 751 cfg_abt_set_query_iptt); 752 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 753 1 << CFG_ABT_SET_IPTT_DONE_OFF); 754 } 755 756 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 757 { 758 struct device *dev = hisi_hba->dev; 759 int ret; 760 u32 val; 761 762 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 763 764 /* Disable all of the PHYs */ 765 hisi_sas_stop_phys(hisi_hba); 766 udelay(50); 767 768 /* Ensure axi bus idle */ 769 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 770 20000, 1000000); 771 if (ret) { 772 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 773 return -EIO; 774 } 775 776 if (ACPI_HANDLE(dev)) { 777 acpi_status s; 778 779 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 780 if (ACPI_FAILURE(s)) { 781 dev_err(dev, "Reset failed\n"); 782 return -EIO; 783 } 784 } else { 785 dev_err(dev, "no reset method!\n"); 786 return -EINVAL; 787 } 788 789 return 0; 790 } 791 792 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 793 { 794 struct device *dev = hisi_hba->dev; 795 int rc; 796 797 rc = reset_hw_v3_hw(hisi_hba); 798 if (rc) { 799 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 800 return rc; 801 } 802 803 msleep(100); 804 init_reg_v3_hw(hisi_hba); 805 806 return 0; 807 } 808 809 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 810 { 811 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 812 813 cfg |= PHY_CFG_ENA_MSK; 814 cfg &= ~PHY_CFG_PHY_RST_MSK; 815 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 816 } 817 818 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 819 { 820 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 821 u32 state; 822 823 cfg &= ~PHY_CFG_ENA_MSK; 824 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 825 826 mdelay(50); 827 828 state = hisi_sas_read32(hisi_hba, PHY_STATE); 829 if (state & BIT(phy_no)) { 830 cfg |= PHY_CFG_PHY_RST_MSK; 831 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 832 } 833 } 834 835 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 836 { 837 config_id_frame_v3_hw(hisi_hba, phy_no); 838 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 839 enable_phy_v3_hw(hisi_hba, phy_no); 840 } 841 842 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 843 { 844 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 845 u32 txid_auto; 846 847 disable_phy_v3_hw(hisi_hba, phy_no); 848 if (phy->identify.device_type == SAS_END_DEVICE) { 849 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 850 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 851 txid_auto | TX_HARDRST_MSK); 852 } 853 msleep(100); 854 start_phy_v3_hw(hisi_hba, phy_no); 855 } 856 857 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 858 { 859 return SAS_LINK_RATE_12_0_GBPS; 860 } 861 862 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 863 { 864 int i; 865 866 for (i = 0; i < hisi_hba->n_phy; i++) { 867 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 868 struct asd_sas_phy *sas_phy = &phy->sas_phy; 869 870 if (!sas_phy->phy->enabled) 871 continue; 872 873 start_phy_v3_hw(hisi_hba, i); 874 } 875 } 876 877 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 878 { 879 u32 sl_control; 880 881 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 882 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 883 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 884 msleep(1); 885 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 886 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 887 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 888 } 889 890 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 891 { 892 int i, bitmap = 0; 893 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 894 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 895 896 for (i = 0; i < hisi_hba->n_phy; i++) 897 if (phy_state & BIT(i)) 898 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 899 bitmap |= BIT(i); 900 901 return bitmap; 902 } 903 904 /** 905 * The callpath to this function and upto writing the write 906 * queue pointer should be safe from interruption. 907 */ 908 static int 909 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 910 { 911 struct device *dev = hisi_hba->dev; 912 int queue = dq->id; 913 u32 r, w; 914 915 w = dq->wr_point; 916 r = hisi_sas_read32_relaxed(hisi_hba, 917 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 918 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 919 dev_warn(dev, "full queue=%d r=%d w=%d\n", 920 queue, r, w); 921 return -EAGAIN; 922 } 923 924 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 925 926 return w; 927 } 928 929 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 930 { 931 struct hisi_hba *hisi_hba = dq->hisi_hba; 932 struct hisi_sas_slot *s, *s1, *s2 = NULL; 933 int dlvry_queue = dq->id; 934 int wp; 935 936 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 937 if (!s->ready) 938 break; 939 s2 = s; 940 list_del(&s->delivery); 941 } 942 943 if (!s2) 944 return; 945 946 /* 947 * Ensure that memories for slots built on other CPUs is observed. 948 */ 949 smp_rmb(); 950 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 951 952 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 953 } 954 955 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 956 struct hisi_sas_slot *slot, 957 struct hisi_sas_cmd_hdr *hdr, 958 struct scatterlist *scatter, 959 int n_elem) 960 { 961 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 962 struct scatterlist *sg; 963 int i; 964 965 for_each_sg(scatter, sg, n_elem, i) { 966 struct hisi_sas_sge *entry = &sge_page->sge[i]; 967 968 entry->addr = cpu_to_le64(sg_dma_address(sg)); 969 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 970 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 971 entry->data_off = 0; 972 } 973 974 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 975 976 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 977 } 978 979 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 980 struct hisi_sas_slot *slot, 981 struct hisi_sas_cmd_hdr *hdr, 982 struct scatterlist *scatter, 983 int n_elem) 984 { 985 struct hisi_sas_sge_dif_page *sge_dif_page; 986 struct scatterlist *sg; 987 int i; 988 989 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 990 991 for_each_sg(scatter, sg, n_elem, i) { 992 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 993 994 entry->addr = cpu_to_le64(sg_dma_address(sg)); 995 entry->page_ctrl_0 = 0; 996 entry->page_ctrl_1 = 0; 997 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 998 entry->data_off = 0; 999 } 1000 1001 hdr->dif_prd_table_addr = 1002 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1003 1004 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1005 } 1006 1007 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1008 { 1009 unsigned char prot_flags = scsi_cmnd->prot_flags; 1010 1011 if (prot_flags & SCSI_PROT_REF_CHECK) 1012 return T10_CHK_APP_TAG_MSK; 1013 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1014 } 1015 1016 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1017 struct hisi_sas_protect_iu_v3_hw *prot) 1018 { 1019 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1020 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1021 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1022 1023 switch (prot_op) { 1024 case SCSI_PROT_READ_INSERT: 1025 prot->dw0 |= T10_INSRT_EN_MSK; 1026 prot->lbrtgv = lbrt_chk_val; 1027 break; 1028 case SCSI_PROT_READ_STRIP: 1029 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1030 prot->lbrtcv = lbrt_chk_val; 1031 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1032 break; 1033 case SCSI_PROT_READ_PASS: 1034 prot->dw0 |= T10_CHK_EN_MSK; 1035 prot->lbrtcv = lbrt_chk_val; 1036 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1037 break; 1038 case SCSI_PROT_WRITE_INSERT: 1039 prot->dw0 |= T10_INSRT_EN_MSK; 1040 prot->lbrtgv = lbrt_chk_val; 1041 break; 1042 case SCSI_PROT_WRITE_STRIP: 1043 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1044 prot->lbrtcv = lbrt_chk_val; 1045 break; 1046 case SCSI_PROT_WRITE_PASS: 1047 prot->dw0 |= T10_CHK_EN_MSK; 1048 prot->lbrtcv = lbrt_chk_val; 1049 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1050 break; 1051 default: 1052 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1053 break; 1054 } 1055 1056 switch (interval) { 1057 case 512: 1058 break; 1059 case 4096: 1060 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1061 break; 1062 case 520: 1063 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1064 break; 1065 default: 1066 WARN(1, "protection interval (0x%x) invalid\n", 1067 interval); 1068 break; 1069 } 1070 1071 prot->dw0 |= INCR_LBRT_MSK; 1072 } 1073 1074 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1075 struct hisi_sas_slot *slot) 1076 { 1077 struct sas_task *task = slot->task; 1078 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1079 struct domain_device *device = task->dev; 1080 struct hisi_sas_device *sas_dev = device->lldd_dev; 1081 struct hisi_sas_port *port = slot->port; 1082 struct sas_ssp_task *ssp_task = &task->ssp_task; 1083 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1084 struct hisi_sas_tmf_task *tmf = slot->tmf; 1085 int has_data = 0, priority = !!tmf; 1086 unsigned char prot_op; 1087 u8 *buf_cmd; 1088 u32 dw1 = 0, dw2 = 0, len = 0; 1089 1090 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1091 (2 << CMD_HDR_TLR_CTRL_OFF) | 1092 (port->id << CMD_HDR_PORT_OFF) | 1093 (priority << CMD_HDR_PRIORITY_OFF) | 1094 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1095 1096 dw1 = 1 << CMD_HDR_VDTL_OFF; 1097 if (tmf) { 1098 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1099 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1100 } else { 1101 prot_op = scsi_get_prot_op(scsi_cmnd); 1102 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1103 switch (scsi_cmnd->sc_data_direction) { 1104 case DMA_TO_DEVICE: 1105 has_data = 1; 1106 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1107 break; 1108 case DMA_FROM_DEVICE: 1109 has_data = 1; 1110 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1111 break; 1112 default: 1113 dw1 &= ~CMD_HDR_DIR_MSK; 1114 } 1115 } 1116 1117 /* map itct entry */ 1118 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1119 1120 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1121 + 3) / 4) << CMD_HDR_CFL_OFF) | 1122 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1123 (2 << CMD_HDR_SG_MOD_OFF); 1124 hdr->dw2 = cpu_to_le32(dw2); 1125 hdr->transfer_tags = cpu_to_le32(slot->idx); 1126 1127 if (has_data) { 1128 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1129 slot->n_elem); 1130 1131 if (scsi_prot_sg_count(scsi_cmnd)) 1132 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1133 scsi_prot_sglist(scsi_cmnd), 1134 slot->n_elem_dif); 1135 } 1136 1137 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1138 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1139 1140 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1141 sizeof(struct ssp_frame_hdr); 1142 1143 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1144 if (!tmf) { 1145 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1146 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1147 } else { 1148 buf_cmd[10] = tmf->tmf; 1149 switch (tmf->tmf) { 1150 case TMF_ABORT_TASK: 1151 case TMF_QUERY_TASK: 1152 buf_cmd[12] = 1153 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1154 buf_cmd[13] = 1155 tmf->tag_of_task_to_be_managed & 0xff; 1156 break; 1157 default: 1158 break; 1159 } 1160 } 1161 1162 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1163 struct hisi_sas_protect_iu_v3_hw prot; 1164 u8 *buf_cmd_prot; 1165 1166 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1167 dw1 |= CMD_HDR_PIR_MSK; 1168 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1169 sizeof(struct ssp_frame_hdr) + 1170 sizeof(struct ssp_command_iu); 1171 1172 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1173 fill_prot_v3_hw(scsi_cmnd, &prot); 1174 memcpy(buf_cmd_prot, &prot, 1175 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1176 /* 1177 * For READ, we need length of info read to memory, while for 1178 * WRITE we need length of data written to the disk. 1179 */ 1180 if (prot_op == SCSI_PROT_WRITE_INSERT || 1181 prot_op == SCSI_PROT_READ_INSERT || 1182 prot_op == SCSI_PROT_WRITE_PASS || 1183 prot_op == SCSI_PROT_READ_PASS) { 1184 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1185 unsigned int ilog2_interval = ilog2(interval); 1186 1187 len = (task->total_xfer_len >> ilog2_interval) * 8; 1188 } 1189 } 1190 1191 hdr->dw1 = cpu_to_le32(dw1); 1192 1193 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1194 } 1195 1196 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1197 struct hisi_sas_slot *slot) 1198 { 1199 struct sas_task *task = slot->task; 1200 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1201 struct domain_device *device = task->dev; 1202 struct hisi_sas_port *port = slot->port; 1203 struct scatterlist *sg_req; 1204 struct hisi_sas_device *sas_dev = device->lldd_dev; 1205 dma_addr_t req_dma_addr; 1206 unsigned int req_len; 1207 1208 /* req */ 1209 sg_req = &task->smp_task.smp_req; 1210 req_len = sg_dma_len(sg_req); 1211 req_dma_addr = sg_dma_address(sg_req); 1212 1213 /* create header */ 1214 /* dw0 */ 1215 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1216 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1217 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1218 1219 /* map itct entry */ 1220 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1221 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1222 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1223 1224 /* dw2 */ 1225 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1226 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1227 CMD_HDR_MRFL_OFF)); 1228 1229 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1230 1231 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1232 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1233 1234 } 1235 1236 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1237 struct hisi_sas_slot *slot) 1238 { 1239 struct sas_task *task = slot->task; 1240 struct domain_device *device = task->dev; 1241 struct domain_device *parent_dev = device->parent; 1242 struct hisi_sas_device *sas_dev = device->lldd_dev; 1243 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1244 struct asd_sas_port *sas_port = device->port; 1245 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1246 u8 *buf_cmd; 1247 int has_data = 0, hdr_tag = 0; 1248 u32 dw1 = 0, dw2 = 0; 1249 1250 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1251 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1252 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1253 else 1254 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1255 1256 switch (task->data_dir) { 1257 case DMA_TO_DEVICE: 1258 has_data = 1; 1259 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1260 break; 1261 case DMA_FROM_DEVICE: 1262 has_data = 1; 1263 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1264 break; 1265 default: 1266 dw1 &= ~CMD_HDR_DIR_MSK; 1267 } 1268 1269 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1270 (task->ata_task.fis.control & ATA_SRST)) 1271 dw1 |= 1 << CMD_HDR_RESET_OFF; 1272 1273 dw1 |= (hisi_sas_get_ata_protocol( 1274 &task->ata_task.fis, task->data_dir)) 1275 << CMD_HDR_FRAME_TYPE_OFF; 1276 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1277 1278 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1279 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1280 1281 hdr->dw1 = cpu_to_le32(dw1); 1282 1283 /* dw2 */ 1284 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1285 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1286 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1287 } 1288 1289 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1290 2 << CMD_HDR_SG_MOD_OFF; 1291 hdr->dw2 = cpu_to_le32(dw2); 1292 1293 /* dw3 */ 1294 hdr->transfer_tags = cpu_to_le32(slot->idx); 1295 1296 if (has_data) 1297 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1298 slot->n_elem); 1299 1300 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1301 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1302 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1303 1304 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1305 1306 if (likely(!task->ata_task.device_control_reg_update)) 1307 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1308 /* fill in command FIS */ 1309 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1310 } 1311 1312 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1313 struct hisi_sas_slot *slot, 1314 int device_id, int abort_flag, int tag_to_abort) 1315 { 1316 struct sas_task *task = slot->task; 1317 struct domain_device *dev = task->dev; 1318 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1319 struct hisi_sas_port *port = slot->port; 1320 1321 /* dw0 */ 1322 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1323 (port->id << CMD_HDR_PORT_OFF) | 1324 (dev_is_sata(dev) 1325 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1326 (abort_flag 1327 << CMD_HDR_ABORT_FLAG_OFF)); 1328 1329 /* dw1 */ 1330 hdr->dw1 = cpu_to_le32(device_id 1331 << CMD_HDR_DEV_ID_OFF); 1332 1333 /* dw7 */ 1334 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1335 hdr->transfer_tags = cpu_to_le32(slot->idx); 1336 1337 } 1338 1339 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1340 { 1341 int i, res; 1342 u32 context, port_id, link_rate; 1343 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1344 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1345 struct device *dev = hisi_hba->dev; 1346 unsigned long flags; 1347 1348 del_timer(&phy->timer); 1349 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1350 1351 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1352 port_id = (port_id >> (4 * phy_no)) & 0xf; 1353 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1354 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1355 1356 if (port_id == 0xf) { 1357 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1358 res = IRQ_NONE; 1359 goto end; 1360 } 1361 sas_phy->linkrate = link_rate; 1362 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1363 1364 /* Check for SATA dev */ 1365 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1366 if (context & (1 << phy_no)) { 1367 struct hisi_sas_initial_fis *initial_fis; 1368 struct dev_to_host_fis *fis; 1369 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1370 1371 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1372 initial_fis = &hisi_hba->initial_fis[phy_no]; 1373 fis = &initial_fis->fis; 1374 1375 /* check ERR bit of Status Register */ 1376 if (fis->status & ATA_ERR) { 1377 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1378 phy_no, fis->status); 1379 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1380 res = IRQ_NONE; 1381 goto end; 1382 } 1383 1384 sas_phy->oob_mode = SATA_OOB_MODE; 1385 attached_sas_addr[0] = 0x50; 1386 attached_sas_addr[7] = phy_no; 1387 memcpy(sas_phy->attached_sas_addr, 1388 attached_sas_addr, 1389 SAS_ADDR_SIZE); 1390 memcpy(sas_phy->frame_rcvd, fis, 1391 sizeof(struct dev_to_host_fis)); 1392 phy->phy_type |= PORT_TYPE_SATA; 1393 phy->identify.device_type = SAS_SATA_DEV; 1394 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1395 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1396 } else { 1397 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1398 struct sas_identify_frame *id = 1399 (struct sas_identify_frame *)frame_rcvd; 1400 1401 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1402 for (i = 0; i < 6; i++) { 1403 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1404 RX_IDAF_DWORD0 + (i * 4)); 1405 frame_rcvd[i] = __swab32(idaf); 1406 } 1407 sas_phy->oob_mode = SAS_OOB_MODE; 1408 memcpy(sas_phy->attached_sas_addr, 1409 &id->sas_addr, 1410 SAS_ADDR_SIZE); 1411 phy->phy_type |= PORT_TYPE_SAS; 1412 phy->identify.device_type = id->dev_type; 1413 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1414 if (phy->identify.device_type == SAS_END_DEVICE) 1415 phy->identify.target_port_protocols = 1416 SAS_PROTOCOL_SSP; 1417 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1418 phy->identify.target_port_protocols = 1419 SAS_PROTOCOL_SMP; 1420 } 1421 1422 phy->port_id = port_id; 1423 phy->phy_attached = 1; 1424 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1425 res = IRQ_HANDLED; 1426 spin_lock_irqsave(&phy->lock, flags); 1427 if (phy->reset_completion) { 1428 phy->in_reset = 0; 1429 complete(phy->reset_completion); 1430 } 1431 spin_unlock_irqrestore(&phy->lock, flags); 1432 end: 1433 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1434 CHL_INT0_SL_PHY_ENABLE_MSK); 1435 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1436 1437 return res; 1438 } 1439 1440 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1441 { 1442 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1443 u32 phy_state, sl_ctrl, txid_auto; 1444 struct device *dev = hisi_hba->dev; 1445 1446 del_timer(&phy->timer); 1447 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1448 1449 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1450 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1451 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1452 1453 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1454 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1455 sl_ctrl&(~SL_CTA_MSK)); 1456 1457 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1458 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1459 txid_auto | CT3_MSK); 1460 1461 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1462 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1463 1464 return IRQ_HANDLED; 1465 } 1466 1467 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1468 { 1469 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1470 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1471 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1472 u32 bcast_status; 1473 1474 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1475 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1476 if ((bcast_status & RX_BCAST_CHG_MSK) && 1477 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1478 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1479 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1480 CHL_INT0_SL_RX_BCST_ACK_MSK); 1481 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1482 1483 return IRQ_HANDLED; 1484 } 1485 1486 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1487 { 1488 struct hisi_hba *hisi_hba = p; 1489 u32 irq_msk; 1490 int phy_no = 0; 1491 irqreturn_t res = IRQ_NONE; 1492 1493 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1494 & 0x11111111; 1495 while (irq_msk) { 1496 if (irq_msk & 1) { 1497 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1498 CHL_INT0); 1499 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1500 int rdy = phy_state & (1 << phy_no); 1501 1502 if (rdy) { 1503 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1504 /* phy up */ 1505 if (phy_up_v3_hw(phy_no, hisi_hba) 1506 == IRQ_HANDLED) 1507 res = IRQ_HANDLED; 1508 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1509 /* phy bcast */ 1510 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1511 == IRQ_HANDLED) 1512 res = IRQ_HANDLED; 1513 } else { 1514 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1515 /* phy down */ 1516 if (phy_down_v3_hw(phy_no, hisi_hba) 1517 == IRQ_HANDLED) 1518 res = IRQ_HANDLED; 1519 } 1520 } 1521 irq_msk >>= 4; 1522 phy_no++; 1523 } 1524 1525 return res; 1526 } 1527 1528 static const struct hisi_sas_hw_error port_axi_error[] = { 1529 { 1530 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1531 .msg = "dma_tx_axi_wr_err", 1532 }, 1533 { 1534 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1535 .msg = "dma_tx_axi_rd_err", 1536 }, 1537 { 1538 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1539 .msg = "dma_rx_axi_wr_err", 1540 }, 1541 { 1542 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1543 .msg = "dma_rx_axi_rd_err", 1544 }, 1545 }; 1546 1547 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1548 { 1549 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1550 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1551 struct device *dev = hisi_hba->dev; 1552 int i; 1553 1554 irq_value &= ~irq_msk; 1555 if (!irq_value) 1556 return; 1557 1558 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1559 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1560 1561 if (!(irq_value & error->irq_msk)) 1562 continue; 1563 1564 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1565 error->msg, phy_no, irq_value); 1566 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1567 } 1568 1569 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1570 } 1571 1572 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1573 { 1574 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1575 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1576 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1577 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1578 struct device *dev = hisi_hba->dev; 1579 1580 irq_value &= ~irq_msk; 1581 if (!irq_value) 1582 return; 1583 1584 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1585 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1586 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1587 } 1588 1589 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1590 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1591 STP_LINK_TIMEOUT_STATE); 1592 1593 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1594 phy_no, reg_value); 1595 if (reg_value & BIT(4)) 1596 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1597 } 1598 1599 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1600 (pci_dev->revision == 0x20)) { 1601 u32 reg_value; 1602 int rc; 1603 1604 rc = hisi_sas_read32_poll_timeout_atomic( 1605 HILINK_ERR_DFX, reg_value, 1606 !((reg_value >> 8) & BIT(phy_no)), 1607 1000, 10000); 1608 if (rc) 1609 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1610 } 1611 1612 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1613 } 1614 1615 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1616 { 1617 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1618 1619 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1620 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1621 1622 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1623 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1624 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1625 & (~CHL_INT0_NOT_RDY_MSK)); 1626 } 1627 1628 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1629 { 1630 struct hisi_hba *hisi_hba = p; 1631 u32 irq_msk; 1632 int phy_no = 0; 1633 1634 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1635 & 0xeeeeeeee; 1636 1637 while (irq_msk) { 1638 if (irq_msk & (2 << (phy_no * 4))) 1639 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1640 1641 if (irq_msk & (4 << (phy_no * 4))) 1642 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1643 1644 if (irq_msk & (8 << (phy_no * 4))) 1645 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1646 1647 irq_msk &= ~(0xe << (phy_no * 4)); 1648 phy_no++; 1649 } 1650 1651 return IRQ_HANDLED; 1652 } 1653 1654 static const struct hisi_sas_hw_error axi_error[] = { 1655 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1656 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1657 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1658 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1659 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1660 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1661 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1662 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1663 {}, 1664 }; 1665 1666 static const struct hisi_sas_hw_error fifo_error[] = { 1667 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1668 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1669 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1670 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1671 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1672 {}, 1673 }; 1674 1675 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1676 { 1677 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1678 .msg = "write pointer and depth", 1679 }, 1680 { 1681 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1682 .msg = "iptt no match slot", 1683 }, 1684 { 1685 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1686 .msg = "read pointer and depth", 1687 }, 1688 { 1689 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1690 .reg = HGC_AXI_FIFO_ERR_INFO, 1691 .sub = axi_error, 1692 }, 1693 { 1694 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1695 .reg = HGC_AXI_FIFO_ERR_INFO, 1696 .sub = fifo_error, 1697 }, 1698 { 1699 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1700 .msg = "LM add/fetch list", 1701 }, 1702 { 1703 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1704 .msg = "SAS_HGC_ABT fetch LM list", 1705 }, 1706 }; 1707 1708 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1709 { 1710 u32 irq_value, irq_msk; 1711 struct hisi_hba *hisi_hba = p; 1712 struct device *dev = hisi_hba->dev; 1713 struct pci_dev *pdev = hisi_hba->pci_dev; 1714 int i; 1715 1716 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1717 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1718 1719 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1720 irq_value &= ~irq_msk; 1721 1722 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1723 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1724 1725 if (!(irq_value & error->irq_msk)) 1726 continue; 1727 1728 if (error->sub) { 1729 const struct hisi_sas_hw_error *sub = error->sub; 1730 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1731 1732 for (; sub->msk || sub->msg; sub++) { 1733 if (!(err_value & sub->msk)) 1734 continue; 1735 1736 dev_err(dev, "%s error (0x%x) found!\n", 1737 sub->msg, irq_value); 1738 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1739 } 1740 } else { 1741 dev_err(dev, "%s error (0x%x) found!\n", 1742 error->msg, irq_value); 1743 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1744 } 1745 1746 if (pdev->revision < 0x21) { 1747 u32 reg_val; 1748 1749 reg_val = hisi_sas_read32(hisi_hba, 1750 AXI_MASTER_CFG_BASE + 1751 AM_CTRL_GLOBAL); 1752 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 1753 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 1754 AM_CTRL_GLOBAL, reg_val); 1755 } 1756 } 1757 1758 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1759 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1760 u32 dev_id = reg_val & ITCT_DEV_MSK; 1761 struct hisi_sas_device *sas_dev = 1762 &hisi_hba->devices[dev_id]; 1763 1764 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1765 dev_dbg(dev, "clear ITCT ok\n"); 1766 complete(sas_dev->completion); 1767 } 1768 1769 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1770 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1771 1772 return IRQ_HANDLED; 1773 } 1774 1775 static void 1776 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1777 struct hisi_sas_slot *slot) 1778 { 1779 struct task_status_struct *ts = &task->task_status; 1780 struct hisi_sas_complete_v3_hdr *complete_queue = 1781 hisi_hba->complete_hdr[slot->cmplt_queue]; 1782 struct hisi_sas_complete_v3_hdr *complete_hdr = 1783 &complete_queue[slot->cmplt_queue_slot]; 1784 struct hisi_sas_err_record_v3 *record = 1785 hisi_sas_status_buf_addr_mem(slot); 1786 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 1787 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 1788 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 1789 1790 switch (task->task_proto) { 1791 case SAS_PROTOCOL_SSP: 1792 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1793 ts->residual = trans_tx_fail_type; 1794 ts->stat = SAS_DATA_UNDERRUN; 1795 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1796 ts->stat = SAS_QUEUE_FULL; 1797 slot->abort = 1; 1798 } else { 1799 ts->stat = SAS_OPEN_REJECT; 1800 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1801 } 1802 break; 1803 case SAS_PROTOCOL_SATA: 1804 case SAS_PROTOCOL_STP: 1805 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1806 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1807 ts->residual = trans_tx_fail_type; 1808 ts->stat = SAS_DATA_UNDERRUN; 1809 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1810 ts->stat = SAS_PHY_DOWN; 1811 slot->abort = 1; 1812 } else { 1813 ts->stat = SAS_OPEN_REJECT; 1814 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1815 } 1816 hisi_sas_sata_done(task, slot); 1817 break; 1818 case SAS_PROTOCOL_SMP: 1819 ts->stat = SAM_STAT_CHECK_CONDITION; 1820 break; 1821 default: 1822 break; 1823 } 1824 } 1825 1826 static int 1827 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1828 { 1829 struct sas_task *task = slot->task; 1830 struct hisi_sas_device *sas_dev; 1831 struct device *dev = hisi_hba->dev; 1832 struct task_status_struct *ts; 1833 struct domain_device *device; 1834 struct sas_ha_struct *ha; 1835 enum exec_status sts; 1836 struct hisi_sas_complete_v3_hdr *complete_queue = 1837 hisi_hba->complete_hdr[slot->cmplt_queue]; 1838 struct hisi_sas_complete_v3_hdr *complete_hdr = 1839 &complete_queue[slot->cmplt_queue_slot]; 1840 unsigned long flags; 1841 bool is_internal = slot->is_internal; 1842 u32 dw0, dw1, dw3; 1843 1844 if (unlikely(!task || !task->lldd_task || !task->dev)) 1845 return -EINVAL; 1846 1847 ts = &task->task_status; 1848 device = task->dev; 1849 ha = device->port->ha; 1850 sas_dev = device->lldd_dev; 1851 1852 spin_lock_irqsave(&task->task_state_lock, flags); 1853 task->task_state_flags &= 1854 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1855 spin_unlock_irqrestore(&task->task_state_lock, flags); 1856 1857 memset(ts, 0, sizeof(*ts)); 1858 ts->resp = SAS_TASK_COMPLETE; 1859 1860 if (unlikely(!sas_dev)) { 1861 dev_dbg(dev, "slot complete: port has not device\n"); 1862 ts->stat = SAS_PHY_DOWN; 1863 goto out; 1864 } 1865 1866 dw0 = le32_to_cpu(complete_hdr->dw0); 1867 dw1 = le32_to_cpu(complete_hdr->dw1); 1868 dw3 = le32_to_cpu(complete_hdr->dw3); 1869 1870 /* 1871 * Use SAS+TMF status codes 1872 */ 1873 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 1874 case STAT_IO_ABORTED: 1875 /* this IO has been aborted by abort command */ 1876 ts->stat = SAS_ABORTED_TASK; 1877 goto out; 1878 case STAT_IO_COMPLETE: 1879 /* internal abort command complete */ 1880 ts->stat = TMF_RESP_FUNC_SUCC; 1881 goto out; 1882 case STAT_IO_NO_DEVICE: 1883 ts->stat = TMF_RESP_FUNC_COMPLETE; 1884 goto out; 1885 case STAT_IO_NOT_VALID: 1886 /* 1887 * abort single IO, the controller can't find the IO 1888 */ 1889 ts->stat = TMF_RESP_FUNC_FAILED; 1890 goto out; 1891 default: 1892 break; 1893 } 1894 1895 /* check for erroneous completion */ 1896 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1897 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1898 1899 slot_err_v3_hw(hisi_hba, task, slot); 1900 if (ts->stat != SAS_DATA_UNDERRUN) 1901 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1902 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1903 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1904 slot->idx, task, sas_dev->device_id, 1905 dw0, dw1, complete_hdr->act, dw3, 1906 error_info[0], error_info[1], 1907 error_info[2], error_info[3]); 1908 if (unlikely(slot->abort)) 1909 return ts->stat; 1910 goto out; 1911 } 1912 1913 switch (task->task_proto) { 1914 case SAS_PROTOCOL_SSP: { 1915 struct ssp_response_iu *iu = 1916 hisi_sas_status_buf_addr_mem(slot) + 1917 sizeof(struct hisi_sas_err_record); 1918 1919 sas_ssp_task_response(dev, task, iu); 1920 break; 1921 } 1922 case SAS_PROTOCOL_SMP: { 1923 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1924 void *to; 1925 1926 ts->stat = SAM_STAT_GOOD; 1927 to = kmap_atomic(sg_page(sg_resp)); 1928 1929 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1930 DMA_FROM_DEVICE); 1931 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1932 DMA_TO_DEVICE); 1933 memcpy(to + sg_resp->offset, 1934 hisi_sas_status_buf_addr_mem(slot) + 1935 sizeof(struct hisi_sas_err_record), 1936 sg_dma_len(sg_resp)); 1937 kunmap_atomic(to); 1938 break; 1939 } 1940 case SAS_PROTOCOL_SATA: 1941 case SAS_PROTOCOL_STP: 1942 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1943 ts->stat = SAM_STAT_GOOD; 1944 hisi_sas_sata_done(task, slot); 1945 break; 1946 default: 1947 ts->stat = SAM_STAT_CHECK_CONDITION; 1948 break; 1949 } 1950 1951 if (!slot->port->port_attached) { 1952 dev_warn(dev, "slot complete: port %d has removed\n", 1953 slot->port->sas_port.id); 1954 ts->stat = SAS_PHY_DOWN; 1955 } 1956 1957 out: 1958 sts = ts->stat; 1959 spin_lock_irqsave(&task->task_state_lock, flags); 1960 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1961 spin_unlock_irqrestore(&task->task_state_lock, flags); 1962 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1963 return SAS_ABORTED_TASK; 1964 } 1965 task->task_state_flags |= SAS_TASK_STATE_DONE; 1966 spin_unlock_irqrestore(&task->task_state_lock, flags); 1967 hisi_sas_slot_task_free(hisi_hba, task, slot); 1968 1969 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1970 spin_lock_irqsave(&device->done_lock, flags); 1971 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1972 spin_unlock_irqrestore(&device->done_lock, flags); 1973 dev_info(dev, "slot complete: task(%p) ignored\n ", 1974 task); 1975 return sts; 1976 } 1977 spin_unlock_irqrestore(&device->done_lock, flags); 1978 } 1979 1980 if (task->task_done) 1981 task->task_done(task); 1982 1983 return sts; 1984 } 1985 1986 static void cq_tasklet_v3_hw(unsigned long val) 1987 { 1988 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1989 struct hisi_hba *hisi_hba = cq->hisi_hba; 1990 struct hisi_sas_slot *slot; 1991 struct hisi_sas_complete_v3_hdr *complete_queue; 1992 u32 rd_point = cq->rd_point, wr_point; 1993 int queue = cq->id; 1994 1995 complete_queue = hisi_hba->complete_hdr[queue]; 1996 1997 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1998 (0x14 * queue)); 1999 2000 while (rd_point != wr_point) { 2001 struct hisi_sas_complete_v3_hdr *complete_hdr; 2002 struct device *dev = hisi_hba->dev; 2003 u32 dw1; 2004 int iptt; 2005 2006 complete_hdr = &complete_queue[rd_point]; 2007 dw1 = le32_to_cpu(complete_hdr->dw1); 2008 2009 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2010 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2011 slot = &hisi_hba->slot_info[iptt]; 2012 slot->cmplt_queue_slot = rd_point; 2013 slot->cmplt_queue = queue; 2014 slot_complete_v3_hw(hisi_hba, slot); 2015 } else 2016 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2017 2018 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2019 rd_point = 0; 2020 } 2021 2022 /* update rd_point */ 2023 cq->rd_point = rd_point; 2024 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2025 } 2026 2027 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2028 { 2029 struct hisi_sas_cq *cq = p; 2030 struct hisi_hba *hisi_hba = cq->hisi_hba; 2031 int queue = cq->id; 2032 2033 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2034 2035 tasklet_schedule(&cq->tasklet); 2036 2037 return IRQ_HANDLED; 2038 } 2039 2040 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2041 { 2042 struct device *dev = hisi_hba->dev; 2043 struct pci_dev *pdev = hisi_hba->pci_dev; 2044 int vectors, rc; 2045 int i, k; 2046 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 2047 2048 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 2049 max_msi, PCI_IRQ_MSI); 2050 if (vectors < max_msi) { 2051 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 2052 return -ENOENT; 2053 } 2054 2055 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; 2056 2057 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2058 int_phy_up_down_bcast_v3_hw, 0, 2059 DRV_NAME " phy", hisi_hba); 2060 if (rc) { 2061 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2062 rc = -ENOENT; 2063 goto free_irq_vectors; 2064 } 2065 2066 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2067 int_chnl_int_v3_hw, 0, 2068 DRV_NAME " channel", hisi_hba); 2069 if (rc) { 2070 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2071 rc = -ENOENT; 2072 goto free_phy_irq; 2073 } 2074 2075 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2076 fatal_axi_int_v3_hw, 0, 2077 DRV_NAME " fatal", hisi_hba); 2078 if (rc) { 2079 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2080 rc = -ENOENT; 2081 goto free_chnl_interrupt; 2082 } 2083 2084 /* Init tasklets for cq only */ 2085 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2086 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2087 struct tasklet_struct *t = &cq->tasklet; 2088 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2089 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2090 2091 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2092 cq_interrupt_v3_hw, irqflags, 2093 DRV_NAME " cq", cq); 2094 if (rc) { 2095 dev_err(dev, 2096 "could not request cq%d interrupt, rc=%d\n", 2097 i, rc); 2098 rc = -ENOENT; 2099 goto free_cq_irqs; 2100 } 2101 2102 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2103 } 2104 2105 return 0; 2106 2107 free_cq_irqs: 2108 for (k = 0; k < i; k++) { 2109 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2110 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2111 2112 free_irq(pci_irq_vector(pdev, nr), cq); 2113 } 2114 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2115 free_chnl_interrupt: 2116 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2117 free_phy_irq: 2118 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2119 free_irq_vectors: 2120 pci_free_irq_vectors(pdev); 2121 return rc; 2122 } 2123 2124 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2125 { 2126 int rc; 2127 2128 rc = hw_init_v3_hw(hisi_hba); 2129 if (rc) 2130 return rc; 2131 2132 rc = interrupt_init_v3_hw(hisi_hba); 2133 if (rc) 2134 return rc; 2135 2136 return 0; 2137 } 2138 2139 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2140 struct sas_phy_linkrates *r) 2141 { 2142 enum sas_linkrate max = r->maximum_linkrate; 2143 u32 prog_phy_link_rate = 0x800; 2144 2145 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2146 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2147 prog_phy_link_rate); 2148 } 2149 2150 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2151 { 2152 struct pci_dev *pdev = hisi_hba->pci_dev; 2153 int i; 2154 2155 synchronize_irq(pci_irq_vector(pdev, 1)); 2156 synchronize_irq(pci_irq_vector(pdev, 2)); 2157 synchronize_irq(pci_irq_vector(pdev, 11)); 2158 for (i = 0; i < hisi_hba->queue_count; i++) { 2159 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2160 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2161 } 2162 2163 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2164 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2165 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2166 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2167 2168 for (i = 0; i < hisi_hba->n_phy; i++) { 2169 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2170 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2171 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2172 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2173 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2174 } 2175 } 2176 2177 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2178 { 2179 return hisi_sas_read32(hisi_hba, PHY_STATE); 2180 } 2181 2182 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 2183 { 2184 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 2185 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2186 struct sas_phy *sphy = sas_phy->phy; 2187 u32 reg_value; 2188 2189 /* loss dword sync */ 2190 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 2191 sphy->loss_of_dword_sync_count += reg_value; 2192 2193 /* phy reset problem */ 2194 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 2195 sphy->phy_reset_problem_count += reg_value; 2196 2197 /* invalid dword */ 2198 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 2199 sphy->invalid_dword_count += reg_value; 2200 2201 /* disparity err */ 2202 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 2203 sphy->running_disparity_error_count += reg_value; 2204 2205 } 2206 2207 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2208 { 2209 struct device *dev = hisi_hba->dev; 2210 u32 status, reg_val; 2211 int rc; 2212 2213 interrupt_disable_v3_hw(hisi_hba); 2214 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2215 hisi_sas_kill_tasklets(hisi_hba); 2216 2217 hisi_sas_stop_phys(hisi_hba); 2218 2219 mdelay(10); 2220 2221 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2222 AM_CTRL_GLOBAL); 2223 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2224 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2225 AM_CTRL_GLOBAL, reg_val); 2226 2227 /* wait until bus idle */ 2228 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2229 AM_CURR_TRANS_RETURN, status, 2230 status == 0x3, 10, 100); 2231 if (rc) { 2232 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2233 return rc; 2234 } 2235 2236 return 0; 2237 } 2238 2239 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2240 { 2241 struct device *dev = hisi_hba->dev; 2242 int rc; 2243 2244 rc = disable_host_v3_hw(hisi_hba); 2245 if (rc) { 2246 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2247 return rc; 2248 } 2249 2250 hisi_sas_init_mem(hisi_hba); 2251 2252 return hw_init_v3_hw(hisi_hba); 2253 } 2254 2255 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2256 u8 reg_index, u8 reg_count, u8 *write_data) 2257 { 2258 struct device *dev = hisi_hba->dev; 2259 u32 *data = (u32 *)write_data; 2260 int i; 2261 2262 switch (reg_type) { 2263 case SAS_GPIO_REG_TX: 2264 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2265 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2266 reg_index, reg_index + reg_count - 1); 2267 return -EINVAL; 2268 } 2269 2270 for (i = 0; i < reg_count; i++) 2271 hisi_sas_write32(hisi_hba, 2272 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2273 data[i]); 2274 break; 2275 default: 2276 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2277 reg_type); 2278 return -EINVAL; 2279 } 2280 2281 return 0; 2282 } 2283 2284 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2285 int delay_ms, int timeout_ms) 2286 { 2287 struct device *dev = hisi_hba->dev; 2288 int entries, entries_old = 0, time; 2289 2290 for (time = 0; time < timeout_ms; time += delay_ms) { 2291 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2292 if (entries == entries_old) 2293 break; 2294 2295 entries_old = entries; 2296 msleep(delay_ms); 2297 } 2298 2299 if (time >= timeout_ms) 2300 return -ETIMEDOUT; 2301 2302 dev_dbg(dev, "wait commands complete %dms\n", time); 2303 2304 return 0; 2305 } 2306 2307 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2308 struct device_attribute *attr, char *buf) 2309 { 2310 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2311 } 2312 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2313 2314 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2315 { 2316 /* config those registers between enable and disable PHYs */ 2317 hisi_sas_stop_phys(hisi_hba); 2318 2319 if (hisi_hba->intr_coal_ticks == 0 || 2320 hisi_hba->intr_coal_count == 0) { 2321 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2322 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2323 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2324 } else { 2325 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2326 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2327 hisi_hba->intr_coal_ticks); 2328 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2329 hisi_hba->intr_coal_count); 2330 } 2331 phys_init_v3_hw(hisi_hba); 2332 } 2333 2334 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2335 struct device_attribute *attr, 2336 char *buf) 2337 { 2338 struct Scsi_Host *shost = class_to_shost(dev); 2339 struct hisi_hba *hisi_hba = shost_priv(shost); 2340 2341 return scnprintf(buf, PAGE_SIZE, "%u\n", 2342 hisi_hba->intr_coal_ticks); 2343 } 2344 2345 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2346 struct device_attribute *attr, 2347 const char *buf, size_t count) 2348 { 2349 struct Scsi_Host *shost = class_to_shost(dev); 2350 struct hisi_hba *hisi_hba = shost_priv(shost); 2351 u32 intr_coal_ticks; 2352 int ret; 2353 2354 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2355 if (ret) { 2356 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2357 return -EINVAL; 2358 } 2359 2360 if (intr_coal_ticks >= BIT(24)) { 2361 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2362 return -EINVAL; 2363 } 2364 2365 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2366 2367 config_intr_coal_v3_hw(hisi_hba); 2368 2369 return count; 2370 } 2371 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2372 2373 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2374 struct device_attribute 2375 *attr, char *buf) 2376 { 2377 struct Scsi_Host *shost = class_to_shost(dev); 2378 struct hisi_hba *hisi_hba = shost_priv(shost); 2379 2380 return scnprintf(buf, PAGE_SIZE, "%u\n", 2381 hisi_hba->intr_coal_count); 2382 } 2383 2384 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2385 struct device_attribute 2386 *attr, const char *buf, size_t count) 2387 { 2388 struct Scsi_Host *shost = class_to_shost(dev); 2389 struct hisi_hba *hisi_hba = shost_priv(shost); 2390 u32 intr_coal_count; 2391 int ret; 2392 2393 ret = kstrtou32(buf, 10, &intr_coal_count); 2394 if (ret) { 2395 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2396 return -EINVAL; 2397 } 2398 2399 if (intr_coal_count >= BIT(8)) { 2400 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2401 return -EINVAL; 2402 } 2403 2404 hisi_hba->intr_coal_count = intr_coal_count; 2405 2406 config_intr_coal_v3_hw(hisi_hba); 2407 2408 return count; 2409 } 2410 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2411 2412 static struct device_attribute *host_attrs_v3_hw[] = { 2413 &dev_attr_phy_event_threshold, 2414 &dev_attr_intr_conv_v3_hw, 2415 &dev_attr_intr_coal_ticks_v3_hw, 2416 &dev_attr_intr_coal_count_v3_hw, 2417 NULL 2418 }; 2419 2420 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2421 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2422 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2423 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2424 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2425 HISI_SAS_DEBUGFS_REG(SL_CFG), 2426 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2427 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2428 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2429 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2430 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2431 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2432 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2433 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2434 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2435 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2436 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2437 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2438 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2439 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2440 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2441 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2442 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2443 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2444 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2445 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2446 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2447 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2448 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2449 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2450 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2451 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2452 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2453 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2454 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2455 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2456 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2457 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2458 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2459 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2460 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2461 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2462 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2463 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2464 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2465 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2466 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2467 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2468 {} 2469 }; 2470 2471 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2472 .lu = debugfs_port_reg_lu, 2473 .count = 0x100, 2474 .base_off = PORT_BASE, 2475 .read_port_reg = hisi_sas_phy_read32, 2476 }; 2477 2478 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2479 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2480 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2481 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2482 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2483 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2484 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2485 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2486 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2487 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2488 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2489 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2490 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2491 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2492 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2493 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2494 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2495 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2496 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2497 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2498 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2499 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2500 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2501 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2502 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2503 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2504 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2505 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2506 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2507 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2508 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2509 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2510 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2511 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2512 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2513 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2514 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2515 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2516 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2517 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2518 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2519 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2520 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2521 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2522 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2523 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2524 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2525 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2526 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2527 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2528 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2529 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2530 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2531 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2532 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2533 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2534 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2535 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2536 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2537 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2538 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2539 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2540 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2541 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2542 {} 2543 }; 2544 2545 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2546 .lu = debugfs_global_reg_lu, 2547 .count = 0x800, 2548 .read_global_reg = hisi_sas_read32, 2549 }; 2550 2551 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2552 { 2553 struct device *dev = hisi_hba->dev; 2554 2555 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2556 2557 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2558 2559 if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT) 2560 dev_dbg(dev, "Wait commands complete timeout!\n"); 2561 2562 hisi_sas_kill_tasklets(hisi_hba); 2563 } 2564 2565 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2566 { 2567 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2568 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2569 2570 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2571 } 2572 2573 static struct scsi_host_template sht_v3_hw = { 2574 .name = DRV_NAME, 2575 .module = THIS_MODULE, 2576 .queuecommand = sas_queuecommand, 2577 .target_alloc = sas_target_alloc, 2578 .slave_configure = hisi_sas_slave_configure, 2579 .scan_finished = hisi_sas_scan_finished, 2580 .scan_start = hisi_sas_scan_start, 2581 .change_queue_depth = sas_change_queue_depth, 2582 .bios_param = sas_bios_param, 2583 .this_id = -1, 2584 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2585 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2586 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2587 .eh_device_reset_handler = sas_eh_device_reset_handler, 2588 .eh_target_reset_handler = sas_eh_target_reset_handler, 2589 .target_destroy = sas_target_destroy, 2590 .ioctl = sas_ioctl, 2591 .shost_attrs = host_attrs_v3_hw, 2592 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2593 }; 2594 2595 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2596 .hw_init = hisi_sas_v3_init, 2597 .setup_itct = setup_itct_v3_hw, 2598 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2599 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2600 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2601 .clear_itct = clear_itct_v3_hw, 2602 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2603 .prep_ssp = prep_ssp_v3_hw, 2604 .prep_smp = prep_smp_v3_hw, 2605 .prep_stp = prep_ata_v3_hw, 2606 .prep_abort = prep_abort_v3_hw, 2607 .get_free_slot = get_free_slot_v3_hw, 2608 .start_delivery = start_delivery_v3_hw, 2609 .slot_complete = slot_complete_v3_hw, 2610 .phys_init = phys_init_v3_hw, 2611 .phy_start = start_phy_v3_hw, 2612 .phy_disable = disable_phy_v3_hw, 2613 .phy_hard_reset = phy_hard_reset_v3_hw, 2614 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2615 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2616 .dereg_device = dereg_device_v3_hw, 2617 .soft_reset = soft_reset_v3_hw, 2618 .get_phys_state = get_phys_state_v3_hw, 2619 .get_events = phy_get_events_v3_hw, 2620 .write_gpio = write_gpio_v3_hw, 2621 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2622 .debugfs_reg_global = &debugfs_global_reg, 2623 .debugfs_reg_port = &debugfs_port_reg, 2624 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2625 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2626 }; 2627 2628 static struct Scsi_Host * 2629 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2630 { 2631 struct Scsi_Host *shost; 2632 struct hisi_hba *hisi_hba; 2633 struct device *dev = &pdev->dev; 2634 2635 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2636 if (!shost) { 2637 dev_err(dev, "shost alloc failed\n"); 2638 return NULL; 2639 } 2640 hisi_hba = shost_priv(shost); 2641 2642 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2643 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2644 hisi_hba->hw = &hisi_sas_v3_hw; 2645 hisi_hba->pci_dev = pdev; 2646 hisi_hba->dev = dev; 2647 hisi_hba->shost = shost; 2648 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2649 2650 if (prot_mask & ~HISI_SAS_PROT_MASK) 2651 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2652 prot_mask); 2653 else 2654 hisi_hba->prot_mask = prot_mask; 2655 2656 timer_setup(&hisi_hba->timer, NULL, 0); 2657 2658 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2659 goto err_out; 2660 2661 if (hisi_sas_alloc(hisi_hba)) { 2662 hisi_sas_free(hisi_hba); 2663 goto err_out; 2664 } 2665 2666 return shost; 2667 err_out: 2668 scsi_host_put(shost); 2669 dev_err(dev, "shost alloc failed\n"); 2670 return NULL; 2671 } 2672 2673 static int 2674 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2675 { 2676 struct Scsi_Host *shost; 2677 struct hisi_hba *hisi_hba; 2678 struct device *dev = &pdev->dev; 2679 struct asd_sas_phy **arr_phy; 2680 struct asd_sas_port **arr_port; 2681 struct sas_ha_struct *sha; 2682 int rc, phy_nr, port_nr, i; 2683 2684 rc = pci_enable_device(pdev); 2685 if (rc) 2686 goto err_out; 2687 2688 pci_set_master(pdev); 2689 2690 rc = pci_request_regions(pdev, DRV_NAME); 2691 if (rc) 2692 goto err_out_disable_device; 2693 2694 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) || 2695 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { 2696 dev_err(dev, "No usable DMA addressing method\n"); 2697 rc = -EIO; 2698 goto err_out_regions; 2699 } 2700 2701 shost = hisi_sas_shost_alloc_pci(pdev); 2702 if (!shost) { 2703 rc = -ENOMEM; 2704 goto err_out_regions; 2705 } 2706 2707 sha = SHOST_TO_SAS_HA(shost); 2708 hisi_hba = shost_priv(shost); 2709 dev_set_drvdata(dev, sha); 2710 2711 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2712 if (!hisi_hba->regs) { 2713 dev_err(dev, "cannot map register.\n"); 2714 rc = -ENOMEM; 2715 goto err_out_ha; 2716 } 2717 2718 phy_nr = port_nr = hisi_hba->n_phy; 2719 2720 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2721 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2722 if (!arr_phy || !arr_port) { 2723 rc = -ENOMEM; 2724 goto err_out_ha; 2725 } 2726 2727 sha->sas_phy = arr_phy; 2728 sha->sas_port = arr_port; 2729 sha->core.shost = shost; 2730 sha->lldd_ha = hisi_hba; 2731 2732 shost->transportt = hisi_sas_stt; 2733 shost->max_id = HISI_SAS_MAX_DEVICES; 2734 shost->max_lun = ~0; 2735 shost->max_channel = 1; 2736 shost->max_cmd_len = 16; 2737 shost->can_queue = hisi_hba->hw->max_command_entries - 2738 HISI_SAS_RESERVED_IPTT_CNT; 2739 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 2740 HISI_SAS_RESERVED_IPTT_CNT; 2741 2742 sha->sas_ha_name = DRV_NAME; 2743 sha->dev = dev; 2744 sha->lldd_module = THIS_MODULE; 2745 sha->sas_addr = &hisi_hba->sas_addr[0]; 2746 sha->num_phys = hisi_hba->n_phy; 2747 sha->core.shost = hisi_hba->shost; 2748 2749 for (i = 0; i < hisi_hba->n_phy; i++) { 2750 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2751 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2752 } 2753 2754 if (hisi_sas_debugfs_enable) 2755 hisi_sas_debugfs_init(hisi_hba); 2756 2757 rc = scsi_add_host(shost, dev); 2758 if (rc) 2759 goto err_out_ha; 2760 2761 rc = sas_register_ha(sha); 2762 if (rc) 2763 goto err_out_register_ha; 2764 2765 rc = hisi_hba->hw->hw_init(hisi_hba); 2766 if (rc) 2767 goto err_out_register_ha; 2768 2769 if (hisi_hba->prot_mask) { 2770 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 2771 prot_mask); 2772 scsi_host_set_prot(hisi_hba->shost, prot_mask); 2773 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 2774 scsi_host_set_guard(hisi_hba->shost, 2775 SHOST_DIX_GUARD_CRC); 2776 } 2777 2778 scsi_scan_host(shost); 2779 2780 return 0; 2781 2782 err_out_register_ha: 2783 scsi_remove_host(shost); 2784 err_out_ha: 2785 scsi_host_put(shost); 2786 err_out_regions: 2787 pci_release_regions(pdev); 2788 err_out_disable_device: 2789 pci_disable_device(pdev); 2790 err_out: 2791 return rc; 2792 } 2793 2794 static void 2795 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2796 { 2797 int i; 2798 2799 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2800 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2801 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2802 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2803 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2804 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2805 2806 free_irq(pci_irq_vector(pdev, nr), cq); 2807 } 2808 pci_free_irq_vectors(pdev); 2809 } 2810 2811 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2812 { 2813 struct device *dev = &pdev->dev; 2814 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2815 struct hisi_hba *hisi_hba = sha->lldd_ha; 2816 struct Scsi_Host *shost = sha->core.shost; 2817 2818 hisi_sas_debugfs_exit(hisi_hba); 2819 2820 if (timer_pending(&hisi_hba->timer)) 2821 del_timer(&hisi_hba->timer); 2822 2823 sas_unregister_ha(sha); 2824 sas_remove_host(sha->core.shost); 2825 2826 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2827 hisi_sas_kill_tasklets(hisi_hba); 2828 pci_release_regions(pdev); 2829 pci_disable_device(pdev); 2830 hisi_sas_free(hisi_hba); 2831 scsi_host_put(shost); 2832 } 2833 2834 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2835 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2836 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2837 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2838 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2839 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2840 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2841 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2842 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2843 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2844 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2845 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2846 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2847 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2848 }; 2849 2850 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2851 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2852 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2853 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2854 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2855 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2856 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2857 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2858 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2859 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2860 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2861 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2862 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2863 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2864 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2865 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2866 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2867 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2868 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2869 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2870 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2871 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2872 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2873 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2874 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2875 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2876 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2877 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2878 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2879 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2880 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2881 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2882 }; 2883 2884 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2885 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2886 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2887 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2888 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2889 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2890 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2891 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2892 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2893 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2894 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2895 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2896 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2897 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2898 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2899 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2900 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2901 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2902 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2903 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2904 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2905 }; 2906 2907 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2908 { 2909 struct device *dev = hisi_hba->dev; 2910 const struct hisi_sas_hw_error *ras_error; 2911 bool need_reset = false; 2912 u32 irq_value; 2913 int i; 2914 2915 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2916 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2917 ras_error = &sas_ras_intr0_nfe[i]; 2918 if (ras_error->irq_msk & irq_value) { 2919 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2920 ras_error->msg, irq_value); 2921 need_reset = true; 2922 } 2923 } 2924 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2925 2926 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2927 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2928 ras_error = &sas_ras_intr1_nfe[i]; 2929 if (ras_error->irq_msk & irq_value) { 2930 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2931 ras_error->msg, irq_value); 2932 need_reset = true; 2933 } 2934 } 2935 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2936 2937 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2938 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2939 ras_error = &sas_ras_intr2_nfe[i]; 2940 if (ras_error->irq_msk & irq_value) { 2941 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2942 ras_error->msg, irq_value); 2943 need_reset = true; 2944 } 2945 } 2946 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2947 2948 return need_reset; 2949 } 2950 2951 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2952 pci_channel_state_t state) 2953 { 2954 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2955 struct hisi_hba *hisi_hba = sha->lldd_ha; 2956 struct device *dev = hisi_hba->dev; 2957 2958 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2959 if (state == pci_channel_io_perm_failure) 2960 return PCI_ERS_RESULT_DISCONNECT; 2961 2962 if (process_non_fatal_error_v3_hw(hisi_hba)) 2963 return PCI_ERS_RESULT_NEED_RESET; 2964 2965 return PCI_ERS_RESULT_CAN_RECOVER; 2966 } 2967 2968 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2969 { 2970 return PCI_ERS_RESULT_RECOVERED; 2971 } 2972 2973 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2974 { 2975 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2976 struct hisi_hba *hisi_hba = sha->lldd_ha; 2977 struct device *dev = hisi_hba->dev; 2978 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2979 2980 dev_info(dev, "PCI error: slot reset callback!!\n"); 2981 queue_work(hisi_hba->wq, &r.work); 2982 wait_for_completion(r.completion); 2983 if (r.done) 2984 return PCI_ERS_RESULT_RECOVERED; 2985 2986 return PCI_ERS_RESULT_DISCONNECT; 2987 } 2988 2989 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 2990 { 2991 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2992 struct hisi_hba *hisi_hba = sha->lldd_ha; 2993 struct device *dev = hisi_hba->dev; 2994 int rc; 2995 2996 dev_info(dev, "FLR prepare\n"); 2997 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2998 hisi_sas_controller_reset_prepare(hisi_hba); 2999 3000 rc = disable_host_v3_hw(hisi_hba); 3001 if (rc) 3002 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 3003 } 3004 3005 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3006 { 3007 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3008 struct hisi_hba *hisi_hba = sha->lldd_ha; 3009 struct device *dev = hisi_hba->dev; 3010 int rc; 3011 3012 hisi_sas_init_mem(hisi_hba); 3013 3014 rc = hw_init_v3_hw(hisi_hba); 3015 if (rc) { 3016 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3017 return; 3018 } 3019 3020 hisi_sas_controller_reset_done(hisi_hba); 3021 dev_info(dev, "FLR done\n"); 3022 } 3023 3024 enum { 3025 /* instances of the controller */ 3026 hip08, 3027 }; 3028 3029 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3030 { 3031 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3032 struct hisi_hba *hisi_hba = sha->lldd_ha; 3033 struct device *dev = hisi_hba->dev; 3034 struct Scsi_Host *shost = hisi_hba->shost; 3035 pci_power_t device_state; 3036 int rc; 3037 3038 if (!pdev->pm_cap) { 3039 dev_err(dev, "PCI PM not supported\n"); 3040 return -ENODEV; 3041 } 3042 3043 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3044 return -1; 3045 3046 scsi_block_requests(shost); 3047 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3048 flush_workqueue(hisi_hba->wq); 3049 3050 rc = disable_host_v3_hw(hisi_hba); 3051 if (rc) { 3052 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3053 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3054 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3055 scsi_unblock_requests(shost); 3056 return rc; 3057 } 3058 3059 hisi_sas_init_mem(hisi_hba); 3060 3061 device_state = pci_choose_state(pdev, state); 3062 dev_warn(dev, "entering operating state [D%d]\n", 3063 device_state); 3064 pci_save_state(pdev); 3065 pci_disable_device(pdev); 3066 pci_set_power_state(pdev, device_state); 3067 3068 hisi_sas_release_tasks(hisi_hba); 3069 3070 sas_suspend_ha(sha); 3071 return 0; 3072 } 3073 3074 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3075 { 3076 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3077 struct hisi_hba *hisi_hba = sha->lldd_ha; 3078 struct Scsi_Host *shost = hisi_hba->shost; 3079 struct device *dev = hisi_hba->dev; 3080 unsigned int rc; 3081 pci_power_t device_state = pdev->current_state; 3082 3083 dev_warn(dev, "resuming from operating state [D%d]\n", 3084 device_state); 3085 pci_set_power_state(pdev, PCI_D0); 3086 pci_enable_wake(pdev, PCI_D0, 0); 3087 pci_restore_state(pdev); 3088 rc = pci_enable_device(pdev); 3089 if (rc) 3090 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3091 3092 pci_set_master(pdev); 3093 scsi_unblock_requests(shost); 3094 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3095 3096 sas_prep_resume_ha(sha); 3097 init_reg_v3_hw(hisi_hba); 3098 hisi_hba->hw->phys_init(hisi_hba); 3099 sas_resume_ha(sha); 3100 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3101 3102 return 0; 3103 } 3104 3105 static const struct pci_device_id sas_v3_pci_table[] = { 3106 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3107 {} 3108 }; 3109 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3110 3111 static const struct pci_error_handlers hisi_sas_err_handler = { 3112 .error_detected = hisi_sas_error_detected_v3_hw, 3113 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 3114 .slot_reset = hisi_sas_slot_reset_v3_hw, 3115 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3116 .reset_done = hisi_sas_reset_done_v3_hw, 3117 }; 3118 3119 static struct pci_driver sas_v3_pci_driver = { 3120 .name = DRV_NAME, 3121 .id_table = sas_v3_pci_table, 3122 .probe = hisi_sas_v3_probe, 3123 .remove = hisi_sas_v3_remove, 3124 .suspend = hisi_sas_v3_suspend, 3125 .resume = hisi_sas_v3_resume, 3126 .err_handler = &hisi_sas_err_handler, 3127 }; 3128 3129 module_pci_driver(sas_v3_pci_driver); 3130 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3131 3132 MODULE_LICENSE("GPL"); 3133 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3134 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3135 MODULE_ALIAS("pci:" DRV_NAME); 3136