1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2017 Hisilicon Limited. 4 */ 5 6 #include "hisi_sas.h" 7 #define DRV_NAME "hisi_sas_v3_hw" 8 9 /* global registers need init */ 10 #define DLVRY_QUEUE_ENABLE 0x0 11 #define IOST_BASE_ADDR_LO 0x8 12 #define IOST_BASE_ADDR_HI 0xc 13 #define ITCT_BASE_ADDR_LO 0x10 14 #define ITCT_BASE_ADDR_HI 0x14 15 #define IO_BROKEN_MSG_ADDR_LO 0x18 16 #define IO_BROKEN_MSG_ADDR_HI 0x1c 17 #define PHY_CONTEXT 0x20 18 #define PHY_STATE 0x24 19 #define PHY_PORT_NUM_MA 0x28 20 #define PHY_CONN_RATE 0x30 21 #define ITCT_CLR 0x44 22 #define ITCT_CLR_EN_OFF 16 23 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 24 #define ITCT_DEV_OFF 0 25 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 26 #define SAS_AXI_USER3 0x50 27 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 28 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 29 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 30 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 31 #define CFG_MAX_TAG 0x68 32 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 33 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 34 #define HGC_GET_ITV_TIME 0x90 35 #define DEVICE_MSG_WORK_MODE 0x94 36 #define OPENA_WT_CONTI_TIME 0x9c 37 #define I_T_NEXUS_LOSS_TIME 0xa0 38 #define MAX_CON_TIME_LIMIT_TIME 0xa4 39 #define BUS_INACTIVE_LIMIT_TIME 0xa8 40 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 41 #define CQ_INT_CONVERGE_EN 0xb0 42 #define CFG_AGING_TIME 0xbc 43 #define HGC_DFX_CFG2 0xc0 44 #define CFG_ABT_SET_QUERY_IPTT 0xd4 45 #define CFG_SET_ABORTED_IPTT_OFF 0 46 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 47 #define CFG_SET_ABORTED_EN_OFF 12 48 #define CFG_ABT_SET_IPTT_DONE 0xd8 49 #define CFG_ABT_SET_IPTT_DONE_OFF 0 50 #define HGC_IOMB_PROC1_STATUS 0x104 51 #define HGC_LM_DFX_STATUS2 0x128 52 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 53 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ 54 HGC_LM_DFX_STATUS2_IOSTLIST_OFF) 55 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 56 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ 57 HGC_LM_DFX_STATUS2_ITCTLIST_OFF) 58 #define HGC_CQE_ECC_ADDR 0x13c 59 #define HGC_CQE_ECC_1B_ADDR_OFF 0 60 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) 61 #define HGC_CQE_ECC_MB_ADDR_OFF 8 62 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) 63 #define HGC_IOST_ECC_ADDR 0x140 64 #define HGC_IOST_ECC_1B_ADDR_OFF 0 65 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) 66 #define HGC_IOST_ECC_MB_ADDR_OFF 16 67 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) 68 #define HGC_DQE_ECC_ADDR 0x144 69 #define HGC_DQE_ECC_1B_ADDR_OFF 0 70 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) 71 #define HGC_DQE_ECC_MB_ADDR_OFF 16 72 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) 73 #define CHNL_INT_STATUS 0x148 74 #define TAB_DFX 0x14c 75 #define HGC_ITCT_ECC_ADDR 0x150 76 #define HGC_ITCT_ECC_1B_ADDR_OFF 0 77 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ 78 HGC_ITCT_ECC_1B_ADDR_OFF) 79 #define HGC_ITCT_ECC_MB_ADDR_OFF 16 80 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ 81 HGC_ITCT_ECC_MB_ADDR_OFF) 82 #define HGC_AXI_FIFO_ERR_INFO 0x154 83 #define AXI_ERR_INFO_OFF 0 84 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 85 #define FIFO_ERR_INFO_OFF 8 86 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 87 #define TAB_RD_TYPE 0x15c 88 #define INT_COAL_EN 0x19c 89 #define OQ_INT_COAL_TIME 0x1a0 90 #define OQ_INT_COAL_CNT 0x1a4 91 #define ENT_INT_COAL_TIME 0x1a8 92 #define ENT_INT_COAL_CNT 0x1ac 93 #define OQ_INT_SRC 0x1b0 94 #define OQ_INT_SRC_MSK 0x1b4 95 #define ENT_INT_SRC1 0x1b8 96 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 97 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 98 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 99 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 100 #define ENT_INT_SRC2 0x1bc 101 #define ENT_INT_SRC3 0x1c0 102 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 103 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 104 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 105 #define ENT_INT_SRC3_AXI_OFF 11 106 #define ENT_INT_SRC3_FIFO_OFF 12 107 #define ENT_INT_SRC3_LM_OFF 14 108 #define ENT_INT_SRC3_ITC_INT_OFF 15 109 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 110 #define ENT_INT_SRC3_ABT_OFF 16 111 #define ENT_INT_SRC3_DQE_POISON_OFF 18 112 #define ENT_INT_SRC3_IOST_POISON_OFF 19 113 #define ENT_INT_SRC3_ITCT_POISON_OFF 20 114 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21 115 #define ENT_INT_SRC_MSK1 0x1c4 116 #define ENT_INT_SRC_MSK2 0x1c8 117 #define ENT_INT_SRC_MSK3 0x1cc 118 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 119 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 120 #define CHNL_ENT_INT_MSK 0x1d4 121 #define HGC_COM_INT_MSK 0x1d8 122 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 123 #define SAS_ECC_INTR 0x1e8 124 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 125 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 126 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 127 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 128 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4 129 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5 130 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6 131 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7 132 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8 133 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9 134 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 135 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 136 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12 137 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13 138 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14 139 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15 140 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16 141 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17 142 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18 143 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19 144 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20 145 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21 146 #define SAS_ECC_INTR_MSK 0x1ec 147 #define HGC_ERR_STAT_EN 0x238 148 #define CQE_SEND_CNT 0x248 149 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 150 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 151 #define DLVRY_Q_0_DEPTH 0x268 152 #define DLVRY_Q_0_WR_PTR 0x26c 153 #define DLVRY_Q_0_RD_PTR 0x270 154 #define HYPER_STREAM_ID_EN_CFG 0xc80 155 #define OQ0_INT_SRC_MSK 0xc90 156 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 157 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 158 #define COMPL_Q_0_DEPTH 0x4e8 159 #define COMPL_Q_0_WR_PTR 0x4ec 160 #define COMPL_Q_0_RD_PTR 0x4f0 161 #define HGC_RXM_DFX_STATUS14 0xae8 162 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 163 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ 164 HGC_RXM_DFX_STATUS14_MEM0_OFF) 165 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 166 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ 167 HGC_RXM_DFX_STATUS14_MEM1_OFF) 168 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 169 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ 170 HGC_RXM_DFX_STATUS14_MEM2_OFF) 171 #define HGC_RXM_DFX_STATUS15 0xaec 172 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 173 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ 174 HGC_RXM_DFX_STATUS15_MEM3_OFF) 175 #define AWQOS_AWCACHE_CFG 0xc84 176 #define ARQOS_ARCACHE_CFG 0xc88 177 #define HILINK_ERR_DFX 0xe04 178 #define SAS_GPIO_CFG_0 0x1000 179 #define SAS_GPIO_CFG_1 0x1004 180 #define SAS_GPIO_TX_0_1 0x1040 181 #define SAS_CFG_DRIVE_VLD 0x1070 182 183 /* phy registers requiring init */ 184 #define PORT_BASE (0x2000) 185 #define PHY_CFG (PORT_BASE + 0x0) 186 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 187 #define PHY_CFG_ENA_OFF 0 188 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 189 #define PHY_CFG_DC_OPT_OFF 2 190 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 191 #define PHY_CFG_PHY_RST_OFF 3 192 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 193 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 194 #define PHY_CTRL (PORT_BASE + 0x14) 195 #define PHY_CTRL_RESET_OFF 0 196 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 197 #define CMD_HDR_PIR_OFF 8 198 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 199 #define SERDES_CFG (PORT_BASE + 0x1c) 200 #define SL_CFG (PORT_BASE + 0x84) 201 #define AIP_LIMIT (PORT_BASE + 0x90) 202 #define SL_CONTROL (PORT_BASE + 0x94) 203 #define SL_CONTROL_NOTIFY_EN_OFF 0 204 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 205 #define SL_CTA_OFF 17 206 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 207 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 208 #define RX_BCAST_CHG_OFF 1 209 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 210 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 211 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 212 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 213 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 214 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 215 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 216 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 217 #define TXID_AUTO (PORT_BASE + 0xb8) 218 #define CT3_OFF 1 219 #define CT3_MSK (0x1 << CT3_OFF) 220 #define TX_HARDRST_OFF 2 221 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 222 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 223 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 224 #define STP_LINK_TIMER (PORT_BASE + 0x120) 225 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 226 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 227 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 228 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 229 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 230 #define CHL_INT0 (PORT_BASE + 0x1b4) 231 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 232 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 233 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 234 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 235 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 236 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 237 #define CHL_INT0_NOT_RDY_OFF 4 238 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 239 #define CHL_INT0_PHY_RDY_OFF 5 240 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 241 #define CHL_INT1 (PORT_BASE + 0x1b8) 242 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15 243 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16 244 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17 245 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18 246 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 247 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 248 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 249 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 250 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23 251 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24 252 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26 253 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27 254 #define CHL_INT2 (PORT_BASE + 0x1bc) 255 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 256 #define CHL_INT2_RX_DISP_ERR_OFF 28 257 #define CHL_INT2_RX_CODE_ERR_OFF 29 258 #define CHL_INT2_RX_INVLD_DW_OFF 30 259 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 260 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 261 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 262 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 263 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 264 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 265 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 266 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 267 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 268 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 269 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 270 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 271 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 272 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 273 #define DMA_TX_STATUS_BUSY_OFF 0 274 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 275 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 276 #define DMA_RX_STATUS_BUSY_OFF 0 277 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 278 279 #define COARSETUNE_TIME (PORT_BASE + 0x304) 280 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 281 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 282 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 283 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 284 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 285 286 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 287 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 288 #error Max ITCT exceeded 289 #endif 290 291 #define AXI_MASTER_CFG_BASE (0x5000) 292 #define AM_CTRL_GLOBAL (0x0) 293 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 294 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 295 #define AM_CURR_TRANS_RETURN (0x150) 296 297 #define AM_CFG_MAX_TRANS (0x5010) 298 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 299 #define AXI_CFG (0x5100) 300 #define AM_ROB_ECC_ERR_ADDR (0x510c) 301 #define AM_ROB_ECC_ERR_ADDR_OFF 0 302 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff 303 304 /* RAS registers need init */ 305 #define RAS_BASE (0x6000) 306 #define SAS_RAS_INTR0 (RAS_BASE) 307 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 308 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 309 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 310 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 311 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 312 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 313 314 /* HW dma structures */ 315 /* Delivery queue header */ 316 /* dw0 */ 317 #define CMD_HDR_ABORT_FLAG_OFF 0 318 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 319 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 320 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 321 #define CMD_HDR_RESP_REPORT_OFF 5 322 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 323 #define CMD_HDR_TLR_CTRL_OFF 6 324 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 325 #define CMD_HDR_PORT_OFF 18 326 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 327 #define CMD_HDR_PRIORITY_OFF 27 328 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 329 #define CMD_HDR_CMD_OFF 29 330 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 331 /* dw1 */ 332 #define CMD_HDR_UNCON_CMD_OFF 3 333 #define CMD_HDR_DIR_OFF 5 334 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 335 #define CMD_HDR_RESET_OFF 7 336 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 337 #define CMD_HDR_VDTL_OFF 10 338 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 339 #define CMD_HDR_FRAME_TYPE_OFF 11 340 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 341 #define CMD_HDR_DEV_ID_OFF 16 342 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 343 /* dw2 */ 344 #define CMD_HDR_CFL_OFF 0 345 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 346 #define CMD_HDR_NCQ_TAG_OFF 10 347 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 348 #define CMD_HDR_MRFL_OFF 15 349 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 350 #define CMD_HDR_SG_MOD_OFF 24 351 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 352 /* dw3 */ 353 #define CMD_HDR_IPTT_OFF 0 354 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 355 /* dw6 */ 356 #define CMD_HDR_DIF_SGL_LEN_OFF 0 357 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 358 #define CMD_HDR_DATA_SGL_LEN_OFF 16 359 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 360 /* dw7 */ 361 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 362 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 363 #define CMD_HDR_ABORT_IPTT_OFF 16 364 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 365 366 /* Completion header */ 367 /* dw0 */ 368 #define CMPLT_HDR_CMPLT_OFF 0 369 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 370 #define CMPLT_HDR_ERROR_PHASE_OFF 2 371 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 372 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 373 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 374 #define CMPLT_HDR_ERX_OFF 12 375 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 376 #define CMPLT_HDR_ABORT_STAT_OFF 13 377 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 378 /* abort_stat */ 379 #define STAT_IO_NOT_VALID 0x1 380 #define STAT_IO_NO_DEVICE 0x2 381 #define STAT_IO_COMPLETE 0x3 382 #define STAT_IO_ABORTED 0x4 383 /* dw1 */ 384 #define CMPLT_HDR_IPTT_OFF 0 385 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 386 #define CMPLT_HDR_DEV_ID_OFF 16 387 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 388 /* dw3 */ 389 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 390 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 391 392 /* ITCT header */ 393 /* qw0 */ 394 #define ITCT_HDR_DEV_TYPE_OFF 0 395 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 396 #define ITCT_HDR_VALID_OFF 2 397 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 398 #define ITCT_HDR_MCR_OFF 5 399 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 400 #define ITCT_HDR_VLN_OFF 9 401 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 402 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 403 #define ITCT_HDR_AWT_CONTINUE_OFF 25 404 #define ITCT_HDR_PORT_ID_OFF 28 405 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 406 /* qw2 */ 407 #define ITCT_HDR_INLT_OFF 0 408 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 409 #define ITCT_HDR_RTOLT_OFF 48 410 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 411 412 struct hisi_sas_protect_iu_v3_hw { 413 u32 dw0; 414 u32 lbrtcv; 415 u32 lbrtgv; 416 u32 dw3; 417 u32 dw4; 418 u32 dw5; 419 u32 rsv; 420 }; 421 422 struct hisi_sas_complete_v3_hdr { 423 __le32 dw0; 424 __le32 dw1; 425 __le32 act; 426 __le32 dw3; 427 }; 428 429 struct hisi_sas_err_record_v3 { 430 /* dw0 */ 431 __le32 trans_tx_fail_type; 432 433 /* dw1 */ 434 __le32 trans_rx_fail_type; 435 436 /* dw2 */ 437 __le16 dma_tx_err_type; 438 __le16 sipc_rx_err_type; 439 440 /* dw3 */ 441 __le32 dma_rx_err_type; 442 }; 443 444 #define RX_DATA_LEN_UNDERFLOW_OFF 6 445 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 446 447 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 448 #define HISI_SAS_MSI_COUNT_V3_HW 32 449 450 #define DIR_NO_DATA 0 451 #define DIR_TO_INI 1 452 #define DIR_TO_DEVICE 2 453 #define DIR_RESERVED 3 454 455 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 456 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 457 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 458 ((fis.command == ATA_CMD_DEV_RESET) && \ 459 ((fis.control & ATA_SRST) != 0))) 460 461 #define T10_INSRT_EN_OFF 0 462 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 463 #define T10_RMV_EN_OFF 1 464 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 465 #define T10_RPLC_EN_OFF 2 466 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 467 #define T10_CHK_EN_OFF 3 468 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 469 #define INCR_LBRT_OFF 5 470 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 471 #define USR_DATA_BLOCK_SZ_OFF 20 472 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 473 #define T10_CHK_MSK_OFF 16 474 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 475 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 476 477 #define BASE_VECTORS_V3_HW 16 478 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) 479 480 enum { 481 DSM_FUNC_ERR_HANDLE_MSI = 0, 482 }; 483 484 static bool hisi_sas_intr_conv; 485 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 486 487 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 488 static int prot_mask; 489 module_param(prot_mask, int, 0); 490 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 491 492 static bool auto_affine_msi_experimental; 493 module_param(auto_affine_msi_experimental, bool, 0444); 494 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n" 495 "default is off"); 496 497 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 498 { 499 void __iomem *regs = hisi_hba->regs + off; 500 501 return readl(regs); 502 } 503 504 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 505 { 506 void __iomem *regs = hisi_hba->regs + off; 507 508 writel(val, regs); 509 } 510 511 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 512 u32 off, u32 val) 513 { 514 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 515 516 writel(val, regs); 517 } 518 519 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 520 int phy_no, u32 off) 521 { 522 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 523 524 return readl(regs); 525 } 526 527 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 528 timeout_us) \ 529 ({ \ 530 void __iomem *regs = hisi_hba->regs + off; \ 531 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 532 }) 533 534 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 535 timeout_us) \ 536 ({ \ 537 void __iomem *regs = hisi_hba->regs + off; \ 538 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 539 }) 540 541 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 542 { 543 int i; 544 545 /* Global registers init */ 546 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 547 (u32)((1ULL << hisi_hba->queue_count) - 1)); 548 hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0); 549 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 550 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 551 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 552 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 553 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 554 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 555 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 556 hisi_sas_intr_conv); 557 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 558 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 559 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 560 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 561 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 562 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 563 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff); 564 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 565 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 566 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 567 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555); 568 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 569 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 570 for (i = 0; i < hisi_hba->queue_count; i++) 571 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 572 573 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 574 575 for (i = 0; i < hisi_hba->n_phy; i++) { 576 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 577 struct asd_sas_phy *sas_phy = &phy->sas_phy; 578 u32 prog_phy_link_rate = 0x800; 579 580 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 581 SAS_LINK_RATE_1_5_GBPS)) { 582 prog_phy_link_rate = 0x855; 583 } else { 584 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 585 586 prog_phy_link_rate = 587 hisi_sas_get_prog_phy_linkrate_mask(max) | 588 0x800; 589 } 590 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 591 prog_phy_link_rate); 592 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); 593 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 594 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 595 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 596 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 597 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 598 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff); 599 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 600 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 601 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 602 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 603 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 604 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 605 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 606 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 607 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 608 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 609 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME, 610 0x30f4240); 611 /* used for 12G negotiate */ 612 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 613 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 614 } 615 616 for (i = 0; i < hisi_hba->queue_count; i++) { 617 /* Delivery queue */ 618 hisi_sas_write32(hisi_hba, 619 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 620 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 621 622 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 623 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 624 625 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 626 HISI_SAS_QUEUE_SLOTS); 627 628 /* Completion queue */ 629 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 630 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 631 632 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 633 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 634 635 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 636 HISI_SAS_QUEUE_SLOTS); 637 } 638 639 /* itct */ 640 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 641 lower_32_bits(hisi_hba->itct_dma)); 642 643 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 644 upper_32_bits(hisi_hba->itct_dma)); 645 646 /* iost */ 647 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 648 lower_32_bits(hisi_hba->iost_dma)); 649 650 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 651 upper_32_bits(hisi_hba->iost_dma)); 652 653 /* breakpoint */ 654 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 655 lower_32_bits(hisi_hba->breakpoint_dma)); 656 657 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 658 upper_32_bits(hisi_hba->breakpoint_dma)); 659 660 /* SATA broken msg */ 661 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 662 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 663 664 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 665 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 666 667 /* SATA initial fis */ 668 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 669 lower_32_bits(hisi_hba->initial_fis_dma)); 670 671 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 672 upper_32_bits(hisi_hba->initial_fis_dma)); 673 674 /* RAS registers init */ 675 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 676 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 677 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 678 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 679 680 /* LED registers init */ 681 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 682 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 683 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 684 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 685 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 686 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 687 } 688 689 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 690 { 691 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 692 693 cfg &= ~PHY_CFG_DC_OPT_MSK; 694 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 695 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 696 } 697 698 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 699 { 700 struct sas_identify_frame identify_frame; 701 u32 *identify_buffer; 702 703 memset(&identify_frame, 0, sizeof(identify_frame)); 704 identify_frame.dev_type = SAS_END_DEVICE; 705 identify_frame.frame_type = 0; 706 identify_frame._un1 = 1; 707 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 708 identify_frame.target_bits = SAS_PROTOCOL_NONE; 709 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 710 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 711 identify_frame.phy_id = phy_no; 712 identify_buffer = (u32 *)(&identify_frame); 713 714 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 715 __swab32(identify_buffer[0])); 716 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 717 __swab32(identify_buffer[1])); 718 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 719 __swab32(identify_buffer[2])); 720 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 721 __swab32(identify_buffer[3])); 722 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 723 __swab32(identify_buffer[4])); 724 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 725 __swab32(identify_buffer[5])); 726 } 727 728 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 729 struct hisi_sas_device *sas_dev) 730 { 731 struct domain_device *device = sas_dev->sas_device; 732 struct device *dev = hisi_hba->dev; 733 u64 qw0, device_id = sas_dev->device_id; 734 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 735 struct domain_device *parent_dev = device->parent; 736 struct asd_sas_port *sas_port = device->port; 737 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 738 u64 sas_addr; 739 740 memset(itct, 0, sizeof(*itct)); 741 742 /* qw0 */ 743 qw0 = 0; 744 switch (sas_dev->dev_type) { 745 case SAS_END_DEVICE: 746 case SAS_EDGE_EXPANDER_DEVICE: 747 case SAS_FANOUT_EXPANDER_DEVICE: 748 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 749 break; 750 case SAS_SATA_DEV: 751 case SAS_SATA_PENDING: 752 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 753 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 754 else 755 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 756 break; 757 default: 758 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 759 sas_dev->dev_type); 760 } 761 762 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 763 (device->linkrate << ITCT_HDR_MCR_OFF) | 764 (1 << ITCT_HDR_VLN_OFF) | 765 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 766 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 767 (port->id << ITCT_HDR_PORT_ID_OFF)); 768 itct->qw0 = cpu_to_le64(qw0); 769 770 /* qw1 */ 771 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 772 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 773 774 /* qw2 */ 775 if (!dev_is_sata(device)) 776 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 777 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 778 } 779 780 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 781 struct hisi_sas_device *sas_dev) 782 { 783 DECLARE_COMPLETION_ONSTACK(completion); 784 u64 dev_id = sas_dev->device_id; 785 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 786 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 787 788 sas_dev->completion = &completion; 789 790 /* clear the itct interrupt state */ 791 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 792 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 793 ENT_INT_SRC3_ITC_INT_MSK); 794 795 /* clear the itct table */ 796 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 797 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 798 799 wait_for_completion(sas_dev->completion); 800 memset(itct, 0, sizeof(struct hisi_sas_itct)); 801 } 802 803 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 804 struct domain_device *device) 805 { 806 struct hisi_sas_slot *slot, *slot2; 807 struct hisi_sas_device *sas_dev = device->lldd_dev; 808 u32 cfg_abt_set_query_iptt; 809 810 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 811 CFG_ABT_SET_QUERY_IPTT); 812 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 813 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 814 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 815 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 816 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 817 cfg_abt_set_query_iptt); 818 } 819 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 820 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 821 cfg_abt_set_query_iptt); 822 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 823 1 << CFG_ABT_SET_IPTT_DONE_OFF); 824 } 825 826 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 827 { 828 struct device *dev = hisi_hba->dev; 829 int ret; 830 u32 val; 831 832 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 833 834 /* Disable all of the PHYs */ 835 hisi_sas_stop_phys(hisi_hba); 836 udelay(50); 837 838 /* Ensure axi bus idle */ 839 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 840 20000, 1000000); 841 if (ret) { 842 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 843 return -EIO; 844 } 845 846 if (ACPI_HANDLE(dev)) { 847 acpi_status s; 848 849 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 850 if (ACPI_FAILURE(s)) { 851 dev_err(dev, "Reset failed\n"); 852 return -EIO; 853 } 854 } else { 855 dev_err(dev, "no reset method!\n"); 856 return -EINVAL; 857 } 858 859 return 0; 860 } 861 862 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 863 { 864 struct device *dev = hisi_hba->dev; 865 union acpi_object *obj; 866 guid_t guid; 867 int rc; 868 869 rc = reset_hw_v3_hw(hisi_hba); 870 if (rc) { 871 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 872 return rc; 873 } 874 875 msleep(100); 876 init_reg_v3_hw(hisi_hba); 877 878 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) { 879 dev_err(dev, "Parse GUID failed\n"); 880 return -EINVAL; 881 } 882 883 /* Switch over to MSI handling , from PCI AER default */ 884 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, 885 DSM_FUNC_ERR_HANDLE_MSI, NULL); 886 if (!obj) 887 dev_warn(dev, "Switch over to MSI handling failed\n"); 888 else 889 ACPI_FREE(obj); 890 891 return 0; 892 } 893 894 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 895 { 896 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 897 898 cfg |= PHY_CFG_ENA_MSK; 899 cfg &= ~PHY_CFG_PHY_RST_MSK; 900 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 901 } 902 903 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 904 { 905 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 906 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 907 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 908 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 909 BIT(CHL_INT2_RX_INVLD_DW_OFF); 910 u32 state; 911 912 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); 913 914 cfg &= ~PHY_CFG_ENA_MSK; 915 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 916 917 mdelay(50); 918 919 state = hisi_sas_read32(hisi_hba, PHY_STATE); 920 if (state & BIT(phy_no)) { 921 cfg |= PHY_CFG_PHY_RST_MSK; 922 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 923 } 924 925 udelay(1); 926 927 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 928 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 929 hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 930 931 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); 932 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); 933 } 934 935 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 936 { 937 config_id_frame_v3_hw(hisi_hba, phy_no); 938 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 939 enable_phy_v3_hw(hisi_hba, phy_no); 940 } 941 942 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 943 { 944 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 945 u32 txid_auto; 946 947 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 948 if (phy->identify.device_type == SAS_END_DEVICE) { 949 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 950 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 951 txid_auto | TX_HARDRST_MSK); 952 } 953 msleep(100); 954 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 955 } 956 957 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 958 { 959 return SAS_LINK_RATE_12_0_GBPS; 960 } 961 962 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 963 { 964 int i; 965 966 for (i = 0; i < hisi_hba->n_phy; i++) { 967 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 968 struct asd_sas_phy *sas_phy = &phy->sas_phy; 969 970 if (!sas_phy->phy->enabled) 971 continue; 972 973 hisi_sas_phy_enable(hisi_hba, i, 1); 974 } 975 } 976 977 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 978 { 979 u32 sl_control; 980 981 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 982 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 983 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 984 msleep(1); 985 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 986 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 987 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 988 } 989 990 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 991 { 992 int i, bitmap = 0; 993 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 994 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 995 996 for (i = 0; i < hisi_hba->n_phy; i++) 997 if (phy_state & BIT(i)) 998 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 999 bitmap |= BIT(i); 1000 1001 return bitmap; 1002 } 1003 1004 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 1005 { 1006 struct hisi_hba *hisi_hba = dq->hisi_hba; 1007 struct hisi_sas_slot *s, *s1, *s2 = NULL; 1008 int dlvry_queue = dq->id; 1009 int wp; 1010 1011 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 1012 if (!s->ready) 1013 break; 1014 s2 = s; 1015 list_del(&s->delivery); 1016 } 1017 1018 if (!s2) 1019 return; 1020 1021 /* 1022 * Ensure that memories for slots built on other CPUs is observed. 1023 */ 1024 smp_rmb(); 1025 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 1026 1027 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 1028 } 1029 1030 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 1031 struct hisi_sas_slot *slot, 1032 struct hisi_sas_cmd_hdr *hdr, 1033 struct scatterlist *scatter, 1034 int n_elem) 1035 { 1036 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 1037 struct scatterlist *sg; 1038 int i; 1039 1040 for_each_sg(scatter, sg, n_elem, i) { 1041 struct hisi_sas_sge *entry = &sge_page->sge[i]; 1042 1043 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1044 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1045 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1046 entry->data_off = 0; 1047 } 1048 1049 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 1050 1051 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1052 } 1053 1054 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 1055 struct hisi_sas_slot *slot, 1056 struct hisi_sas_cmd_hdr *hdr, 1057 struct scatterlist *scatter, 1058 int n_elem) 1059 { 1060 struct hisi_sas_sge_dif_page *sge_dif_page; 1061 struct scatterlist *sg; 1062 int i; 1063 1064 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 1065 1066 for_each_sg(scatter, sg, n_elem, i) { 1067 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 1068 1069 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1070 entry->page_ctrl_0 = 0; 1071 entry->page_ctrl_1 = 0; 1072 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1073 entry->data_off = 0; 1074 } 1075 1076 hdr->dif_prd_table_addr = 1077 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1078 1079 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1080 } 1081 1082 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1083 { 1084 unsigned char prot_flags = scsi_cmnd->prot_flags; 1085 1086 if (prot_flags & SCSI_PROT_REF_CHECK) 1087 return T10_CHK_APP_TAG_MSK; 1088 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1089 } 1090 1091 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1092 struct hisi_sas_protect_iu_v3_hw *prot) 1093 { 1094 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1095 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1096 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1097 1098 switch (prot_op) { 1099 case SCSI_PROT_READ_INSERT: 1100 prot->dw0 |= T10_INSRT_EN_MSK; 1101 prot->lbrtgv = lbrt_chk_val; 1102 break; 1103 case SCSI_PROT_READ_STRIP: 1104 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1105 prot->lbrtcv = lbrt_chk_val; 1106 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1107 break; 1108 case SCSI_PROT_READ_PASS: 1109 prot->dw0 |= T10_CHK_EN_MSK; 1110 prot->lbrtcv = lbrt_chk_val; 1111 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1112 break; 1113 case SCSI_PROT_WRITE_INSERT: 1114 prot->dw0 |= T10_INSRT_EN_MSK; 1115 prot->lbrtgv = lbrt_chk_val; 1116 break; 1117 case SCSI_PROT_WRITE_STRIP: 1118 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1119 prot->lbrtcv = lbrt_chk_val; 1120 break; 1121 case SCSI_PROT_WRITE_PASS: 1122 prot->dw0 |= T10_CHK_EN_MSK; 1123 prot->lbrtcv = lbrt_chk_val; 1124 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1125 break; 1126 default: 1127 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1128 break; 1129 } 1130 1131 switch (interval) { 1132 case 512: 1133 break; 1134 case 4096: 1135 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1136 break; 1137 case 520: 1138 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1139 break; 1140 default: 1141 WARN(1, "protection interval (0x%x) invalid\n", 1142 interval); 1143 break; 1144 } 1145 1146 prot->dw0 |= INCR_LBRT_MSK; 1147 } 1148 1149 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1150 struct hisi_sas_slot *slot) 1151 { 1152 struct sas_task *task = slot->task; 1153 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1154 struct domain_device *device = task->dev; 1155 struct hisi_sas_device *sas_dev = device->lldd_dev; 1156 struct hisi_sas_port *port = slot->port; 1157 struct sas_ssp_task *ssp_task = &task->ssp_task; 1158 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1159 struct hisi_sas_tmf_task *tmf = slot->tmf; 1160 int has_data = 0, priority = !!tmf; 1161 unsigned char prot_op; 1162 u8 *buf_cmd; 1163 u32 dw1 = 0, dw2 = 0, len = 0; 1164 1165 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1166 (2 << CMD_HDR_TLR_CTRL_OFF) | 1167 (port->id << CMD_HDR_PORT_OFF) | 1168 (priority << CMD_HDR_PRIORITY_OFF) | 1169 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1170 1171 dw1 = 1 << CMD_HDR_VDTL_OFF; 1172 if (tmf) { 1173 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1174 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1175 } else { 1176 prot_op = scsi_get_prot_op(scsi_cmnd); 1177 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1178 switch (scsi_cmnd->sc_data_direction) { 1179 case DMA_TO_DEVICE: 1180 has_data = 1; 1181 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1182 break; 1183 case DMA_FROM_DEVICE: 1184 has_data = 1; 1185 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1186 break; 1187 default: 1188 dw1 &= ~CMD_HDR_DIR_MSK; 1189 } 1190 } 1191 1192 /* map itct entry */ 1193 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1194 1195 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1196 + 3) / 4) << CMD_HDR_CFL_OFF) | 1197 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1198 (2 << CMD_HDR_SG_MOD_OFF); 1199 hdr->dw2 = cpu_to_le32(dw2); 1200 hdr->transfer_tags = cpu_to_le32(slot->idx); 1201 1202 if (has_data) { 1203 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1204 slot->n_elem); 1205 1206 if (scsi_prot_sg_count(scsi_cmnd)) 1207 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1208 scsi_prot_sglist(scsi_cmnd), 1209 slot->n_elem_dif); 1210 } 1211 1212 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1213 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1214 1215 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1216 sizeof(struct ssp_frame_hdr); 1217 1218 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1219 if (!tmf) { 1220 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1221 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1222 } else { 1223 buf_cmd[10] = tmf->tmf; 1224 switch (tmf->tmf) { 1225 case TMF_ABORT_TASK: 1226 case TMF_QUERY_TASK: 1227 buf_cmd[12] = 1228 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1229 buf_cmd[13] = 1230 tmf->tag_of_task_to_be_managed & 0xff; 1231 break; 1232 default: 1233 break; 1234 } 1235 } 1236 1237 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1238 struct hisi_sas_protect_iu_v3_hw prot; 1239 u8 *buf_cmd_prot; 1240 1241 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1242 dw1 |= CMD_HDR_PIR_MSK; 1243 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1244 sizeof(struct ssp_frame_hdr) + 1245 sizeof(struct ssp_command_iu); 1246 1247 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1248 fill_prot_v3_hw(scsi_cmnd, &prot); 1249 memcpy(buf_cmd_prot, &prot, 1250 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1251 /* 1252 * For READ, we need length of info read to memory, while for 1253 * WRITE we need length of data written to the disk. 1254 */ 1255 if (prot_op == SCSI_PROT_WRITE_INSERT || 1256 prot_op == SCSI_PROT_READ_INSERT || 1257 prot_op == SCSI_PROT_WRITE_PASS || 1258 prot_op == SCSI_PROT_READ_PASS) { 1259 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1260 unsigned int ilog2_interval = ilog2(interval); 1261 1262 len = (task->total_xfer_len >> ilog2_interval) * 8; 1263 } 1264 } 1265 1266 hdr->dw1 = cpu_to_le32(dw1); 1267 1268 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1269 } 1270 1271 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1272 struct hisi_sas_slot *slot) 1273 { 1274 struct sas_task *task = slot->task; 1275 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1276 struct domain_device *device = task->dev; 1277 struct hisi_sas_port *port = slot->port; 1278 struct scatterlist *sg_req; 1279 struct hisi_sas_device *sas_dev = device->lldd_dev; 1280 dma_addr_t req_dma_addr; 1281 unsigned int req_len; 1282 1283 /* req */ 1284 sg_req = &task->smp_task.smp_req; 1285 req_len = sg_dma_len(sg_req); 1286 req_dma_addr = sg_dma_address(sg_req); 1287 1288 /* create header */ 1289 /* dw0 */ 1290 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1291 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1292 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1293 1294 /* map itct entry */ 1295 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1296 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1297 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1298 1299 /* dw2 */ 1300 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1301 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1302 CMD_HDR_MRFL_OFF)); 1303 1304 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1305 1306 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1307 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1308 1309 } 1310 1311 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1312 struct hisi_sas_slot *slot) 1313 { 1314 struct sas_task *task = slot->task; 1315 struct domain_device *device = task->dev; 1316 struct domain_device *parent_dev = device->parent; 1317 struct hisi_sas_device *sas_dev = device->lldd_dev; 1318 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1319 struct asd_sas_port *sas_port = device->port; 1320 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1321 u8 *buf_cmd; 1322 int has_data = 0, hdr_tag = 0; 1323 u32 dw1 = 0, dw2 = 0; 1324 1325 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1326 if (parent_dev && dev_is_expander(parent_dev->dev_type)) 1327 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1328 else 1329 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF); 1330 1331 switch (task->data_dir) { 1332 case DMA_TO_DEVICE: 1333 has_data = 1; 1334 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1335 break; 1336 case DMA_FROM_DEVICE: 1337 has_data = 1; 1338 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1339 break; 1340 default: 1341 dw1 &= ~CMD_HDR_DIR_MSK; 1342 } 1343 1344 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1345 (task->ata_task.fis.control & ATA_SRST)) 1346 dw1 |= 1 << CMD_HDR_RESET_OFF; 1347 1348 dw1 |= (hisi_sas_get_ata_protocol( 1349 &task->ata_task.fis, task->data_dir)) 1350 << CMD_HDR_FRAME_TYPE_OFF; 1351 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1352 1353 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1354 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1355 1356 hdr->dw1 = cpu_to_le32(dw1); 1357 1358 /* dw2 */ 1359 if (task->ata_task.use_ncq) { 1360 struct ata_queued_cmd *qc = task->uldd_task; 1361 1362 hdr_tag = qc->tag; 1363 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1364 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1365 } 1366 1367 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1368 2 << CMD_HDR_SG_MOD_OFF; 1369 hdr->dw2 = cpu_to_le32(dw2); 1370 1371 /* dw3 */ 1372 hdr->transfer_tags = cpu_to_le32(slot->idx); 1373 1374 if (has_data) 1375 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1376 slot->n_elem); 1377 1378 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1379 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1380 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1381 1382 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1383 1384 if (likely(!task->ata_task.device_control_reg_update)) 1385 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1386 /* fill in command FIS */ 1387 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1388 } 1389 1390 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1391 struct hisi_sas_slot *slot, 1392 int device_id, int abort_flag, int tag_to_abort) 1393 { 1394 struct sas_task *task = slot->task; 1395 struct domain_device *dev = task->dev; 1396 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1397 struct hisi_sas_port *port = slot->port; 1398 1399 /* dw0 */ 1400 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/ 1401 (port->id << CMD_HDR_PORT_OFF) | 1402 (dev_is_sata(dev) 1403 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1404 (abort_flag 1405 << CMD_HDR_ABORT_FLAG_OFF)); 1406 1407 /* dw1 */ 1408 hdr->dw1 = cpu_to_le32(device_id 1409 << CMD_HDR_DEV_ID_OFF); 1410 1411 /* dw7 */ 1412 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1413 hdr->transfer_tags = cpu_to_le32(slot->idx); 1414 1415 } 1416 1417 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1418 { 1419 int i; 1420 irqreturn_t res; 1421 u32 context, port_id, link_rate; 1422 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1423 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1424 struct device *dev = hisi_hba->dev; 1425 unsigned long flags; 1426 1427 del_timer(&phy->timer); 1428 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1429 1430 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1431 port_id = (port_id >> (4 * phy_no)) & 0xf; 1432 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1433 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1434 1435 if (port_id == 0xf) { 1436 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1437 res = IRQ_NONE; 1438 goto end; 1439 } 1440 sas_phy->linkrate = link_rate; 1441 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1442 1443 /* Check for SATA dev */ 1444 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1445 if (context & (1 << phy_no)) { 1446 struct hisi_sas_initial_fis *initial_fis; 1447 struct dev_to_host_fis *fis; 1448 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1449 struct Scsi_Host *shost = hisi_hba->shost; 1450 1451 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1452 initial_fis = &hisi_hba->initial_fis[phy_no]; 1453 fis = &initial_fis->fis; 1454 1455 /* check ERR bit of Status Register */ 1456 if (fis->status & ATA_ERR) { 1457 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1458 phy_no, fis->status); 1459 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1460 res = IRQ_NONE; 1461 goto end; 1462 } 1463 1464 sas_phy->oob_mode = SATA_OOB_MODE; 1465 attached_sas_addr[0] = 0x50; 1466 attached_sas_addr[6] = shost->host_no; 1467 attached_sas_addr[7] = phy_no; 1468 memcpy(sas_phy->attached_sas_addr, 1469 attached_sas_addr, 1470 SAS_ADDR_SIZE); 1471 memcpy(sas_phy->frame_rcvd, fis, 1472 sizeof(struct dev_to_host_fis)); 1473 phy->phy_type |= PORT_TYPE_SATA; 1474 phy->identify.device_type = SAS_SATA_DEV; 1475 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1476 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1477 } else { 1478 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1479 struct sas_identify_frame *id = 1480 (struct sas_identify_frame *)frame_rcvd; 1481 1482 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1483 for (i = 0; i < 6; i++) { 1484 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1485 RX_IDAF_DWORD0 + (i * 4)); 1486 frame_rcvd[i] = __swab32(idaf); 1487 } 1488 sas_phy->oob_mode = SAS_OOB_MODE; 1489 memcpy(sas_phy->attached_sas_addr, 1490 &id->sas_addr, 1491 SAS_ADDR_SIZE); 1492 phy->phy_type |= PORT_TYPE_SAS; 1493 phy->identify.device_type = id->dev_type; 1494 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1495 if (phy->identify.device_type == SAS_END_DEVICE) 1496 phy->identify.target_port_protocols = 1497 SAS_PROTOCOL_SSP; 1498 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1499 phy->identify.target_port_protocols = 1500 SAS_PROTOCOL_SMP; 1501 } 1502 1503 phy->port_id = port_id; 1504 phy->phy_attached = 1; 1505 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1506 res = IRQ_HANDLED; 1507 spin_lock_irqsave(&phy->lock, flags); 1508 if (phy->reset_completion) { 1509 phy->in_reset = 0; 1510 complete(phy->reset_completion); 1511 } 1512 spin_unlock_irqrestore(&phy->lock, flags); 1513 end: 1514 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1515 CHL_INT0_SL_PHY_ENABLE_MSK); 1516 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1517 1518 return res; 1519 } 1520 1521 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1522 { 1523 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1524 u32 phy_state, sl_ctrl, txid_auto; 1525 struct device *dev = hisi_hba->dev; 1526 1527 del_timer(&phy->timer); 1528 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1529 1530 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1531 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1532 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1533 1534 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1535 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1536 sl_ctrl&(~SL_CTA_MSK)); 1537 1538 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1539 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1540 txid_auto | CT3_MSK); 1541 1542 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1543 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1544 1545 return IRQ_HANDLED; 1546 } 1547 1548 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1549 { 1550 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1551 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1552 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1553 u32 bcast_status; 1554 1555 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1556 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1557 if ((bcast_status & RX_BCAST_CHG_MSK) && 1558 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1559 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1560 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1561 CHL_INT0_SL_RX_BCST_ACK_MSK); 1562 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1563 1564 return IRQ_HANDLED; 1565 } 1566 1567 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1568 { 1569 struct hisi_hba *hisi_hba = p; 1570 u32 irq_msk; 1571 int phy_no = 0; 1572 irqreturn_t res = IRQ_NONE; 1573 1574 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1575 & 0x11111111; 1576 while (irq_msk) { 1577 if (irq_msk & 1) { 1578 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1579 CHL_INT0); 1580 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1581 int rdy = phy_state & (1 << phy_no); 1582 1583 if (rdy) { 1584 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1585 /* phy up */ 1586 if (phy_up_v3_hw(phy_no, hisi_hba) 1587 == IRQ_HANDLED) 1588 res = IRQ_HANDLED; 1589 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1590 /* phy bcast */ 1591 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1592 == IRQ_HANDLED) 1593 res = IRQ_HANDLED; 1594 } else { 1595 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1596 /* phy down */ 1597 if (phy_down_v3_hw(phy_no, hisi_hba) 1598 == IRQ_HANDLED) 1599 res = IRQ_HANDLED; 1600 } 1601 } 1602 irq_msk >>= 4; 1603 phy_no++; 1604 } 1605 1606 return res; 1607 } 1608 1609 static const struct hisi_sas_hw_error port_axi_error[] = { 1610 { 1611 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF), 1612 .msg = "dmac_tx_ecc_bad_err", 1613 }, 1614 { 1615 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF), 1616 .msg = "dmac_rx_ecc_bad_err", 1617 }, 1618 { 1619 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1620 .msg = "dma_tx_axi_wr_err", 1621 }, 1622 { 1623 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1624 .msg = "dma_tx_axi_rd_err", 1625 }, 1626 { 1627 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1628 .msg = "dma_rx_axi_wr_err", 1629 }, 1630 { 1631 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1632 .msg = "dma_rx_axi_rd_err", 1633 }, 1634 { 1635 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF), 1636 .msg = "dma_tx_fifo_err", 1637 }, 1638 { 1639 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF), 1640 .msg = "dma_rx_fifo_err", 1641 }, 1642 { 1643 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF), 1644 .msg = "dma_tx_axi_ruser_err", 1645 }, 1646 { 1647 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF), 1648 .msg = "dma_rx_axi_ruser_err", 1649 }, 1650 }; 1651 1652 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1653 { 1654 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1655 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1656 struct device *dev = hisi_hba->dev; 1657 int i; 1658 1659 irq_value &= ~irq_msk; 1660 if (!irq_value) 1661 return; 1662 1663 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1664 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1665 1666 if (!(irq_value & error->irq_msk)) 1667 continue; 1668 1669 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1670 error->msg, phy_no, irq_value); 1671 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1672 } 1673 1674 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1675 } 1676 1677 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1678 { 1679 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1680 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1681 struct sas_phy *sphy = sas_phy->phy; 1682 unsigned long flags; 1683 u32 reg_value; 1684 1685 spin_lock_irqsave(&phy->lock, flags); 1686 1687 /* loss dword sync */ 1688 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1689 sphy->loss_of_dword_sync_count += reg_value; 1690 1691 /* phy reset problem */ 1692 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1693 sphy->phy_reset_problem_count += reg_value; 1694 1695 /* invalid dword */ 1696 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1697 sphy->invalid_dword_count += reg_value; 1698 1699 /* disparity err */ 1700 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1701 sphy->running_disparity_error_count += reg_value; 1702 1703 /* code violation error */ 1704 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 1705 phy->code_violation_err_count += reg_value; 1706 1707 spin_unlock_irqrestore(&phy->lock, flags); 1708 } 1709 1710 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1711 { 1712 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1713 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1714 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1715 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1716 struct device *dev = hisi_hba->dev; 1717 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 1718 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 1719 BIT(CHL_INT2_RX_INVLD_DW_OFF); 1720 1721 irq_value &= ~irq_msk; 1722 if (!irq_value) 1723 return; 1724 1725 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1726 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1727 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1728 } 1729 1730 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1731 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1732 STP_LINK_TIMEOUT_STATE); 1733 1734 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1735 phy_no, reg_value); 1736 if (reg_value & BIT(4)) 1737 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1738 } 1739 1740 if (pci_dev->revision > 0x20 && (irq_value & msk)) { 1741 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1742 struct sas_phy *sphy = sas_phy->phy; 1743 1744 phy_get_events_v3_hw(hisi_hba, phy_no); 1745 1746 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) 1747 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no, 1748 sphy->invalid_dword_count); 1749 1750 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF)) 1751 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no, 1752 phy->code_violation_err_count); 1753 1754 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF)) 1755 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no, 1756 sphy->running_disparity_error_count); 1757 } 1758 1759 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1760 (pci_dev->revision == 0x20)) { 1761 u32 reg_value; 1762 int rc; 1763 1764 rc = hisi_sas_read32_poll_timeout_atomic( 1765 HILINK_ERR_DFX, reg_value, 1766 !((reg_value >> 8) & BIT(phy_no)), 1767 1000, 10000); 1768 if (rc) 1769 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1770 } 1771 1772 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1773 } 1774 1775 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1776 { 1777 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1778 1779 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1780 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1781 1782 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1783 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1784 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1785 & (~CHL_INT0_NOT_RDY_MSK)); 1786 } 1787 1788 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1789 { 1790 struct hisi_hba *hisi_hba = p; 1791 u32 irq_msk; 1792 int phy_no = 0; 1793 1794 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1795 & 0xeeeeeeee; 1796 1797 while (irq_msk) { 1798 if (irq_msk & (2 << (phy_no * 4))) 1799 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1800 1801 if (irq_msk & (4 << (phy_no * 4))) 1802 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1803 1804 if (irq_msk & (8 << (phy_no * 4))) 1805 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1806 1807 irq_msk &= ~(0xe << (phy_no * 4)); 1808 phy_no++; 1809 } 1810 1811 return IRQ_HANDLED; 1812 } 1813 1814 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { 1815 { 1816 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), 1817 .msk = HGC_DQE_ECC_MB_ADDR_MSK, 1818 .shift = HGC_DQE_ECC_MB_ADDR_OFF, 1819 .msg = "hgc_dqe_eccbad_intr", 1820 .reg = HGC_DQE_ECC_ADDR, 1821 }, 1822 { 1823 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), 1824 .msk = HGC_IOST_ECC_MB_ADDR_MSK, 1825 .shift = HGC_IOST_ECC_MB_ADDR_OFF, 1826 .msg = "hgc_iost_eccbad_intr", 1827 .reg = HGC_IOST_ECC_ADDR, 1828 }, 1829 { 1830 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), 1831 .msk = HGC_ITCT_ECC_MB_ADDR_MSK, 1832 .shift = HGC_ITCT_ECC_MB_ADDR_OFF, 1833 .msg = "hgc_itct_eccbad_intr", 1834 .reg = HGC_ITCT_ECC_ADDR, 1835 }, 1836 { 1837 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), 1838 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, 1839 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, 1840 .msg = "hgc_iostl_eccbad_intr", 1841 .reg = HGC_LM_DFX_STATUS2, 1842 }, 1843 { 1844 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), 1845 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, 1846 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, 1847 .msg = "hgc_itctl_eccbad_intr", 1848 .reg = HGC_LM_DFX_STATUS2, 1849 }, 1850 { 1851 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), 1852 .msk = HGC_CQE_ECC_MB_ADDR_MSK, 1853 .shift = HGC_CQE_ECC_MB_ADDR_OFF, 1854 .msg = "hgc_cqe_eccbad_intr", 1855 .reg = HGC_CQE_ECC_ADDR, 1856 }, 1857 { 1858 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), 1859 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, 1860 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, 1861 .msg = "rxm_mem0_eccbad_intr", 1862 .reg = HGC_RXM_DFX_STATUS14, 1863 }, 1864 { 1865 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), 1866 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, 1867 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, 1868 .msg = "rxm_mem1_eccbad_intr", 1869 .reg = HGC_RXM_DFX_STATUS14, 1870 }, 1871 { 1872 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), 1873 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, 1874 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, 1875 .msg = "rxm_mem2_eccbad_intr", 1876 .reg = HGC_RXM_DFX_STATUS14, 1877 }, 1878 { 1879 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), 1880 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, 1881 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, 1882 .msg = "rxm_mem3_eccbad_intr", 1883 .reg = HGC_RXM_DFX_STATUS15, 1884 }, 1885 { 1886 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), 1887 .msk = AM_ROB_ECC_ERR_ADDR_MSK, 1888 .shift = AM_ROB_ECC_ERR_ADDR_OFF, 1889 .msg = "ooo_ram_eccbad_intr", 1890 .reg = AM_ROB_ECC_ERR_ADDR, 1891 }, 1892 }; 1893 1894 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, 1895 u32 irq_value) 1896 { 1897 struct device *dev = hisi_hba->dev; 1898 const struct hisi_sas_hw_error *ecc_error; 1899 u32 val; 1900 int i; 1901 1902 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { 1903 ecc_error = &multi_bit_ecc_errors[i]; 1904 if (irq_value & ecc_error->irq_msk) { 1905 val = hisi_sas_read32(hisi_hba, ecc_error->reg); 1906 val &= ecc_error->msk; 1907 val >>= ecc_error->shift; 1908 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", 1909 ecc_error->msg, irq_value, val); 1910 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1911 } 1912 } 1913 } 1914 1915 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba) 1916 { 1917 u32 irq_value, irq_msk; 1918 1919 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); 1920 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1921 1922 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1923 if (irq_value) 1924 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); 1925 1926 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); 1927 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); 1928 } 1929 1930 static const struct hisi_sas_hw_error axi_error[] = { 1931 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1932 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1933 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1934 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1935 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1936 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1937 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1938 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1939 {} 1940 }; 1941 1942 static const struct hisi_sas_hw_error fifo_error[] = { 1943 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1944 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1945 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1946 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1947 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1948 {} 1949 }; 1950 1951 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1952 { 1953 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1954 .msg = "write pointer and depth", 1955 }, 1956 { 1957 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1958 .msg = "iptt no match slot", 1959 }, 1960 { 1961 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1962 .msg = "read pointer and depth", 1963 }, 1964 { 1965 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1966 .reg = HGC_AXI_FIFO_ERR_INFO, 1967 .sub = axi_error, 1968 }, 1969 { 1970 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1971 .reg = HGC_AXI_FIFO_ERR_INFO, 1972 .sub = fifo_error, 1973 }, 1974 { 1975 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1976 .msg = "LM add/fetch list", 1977 }, 1978 { 1979 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1980 .msg = "SAS_HGC_ABT fetch LM list", 1981 }, 1982 { 1983 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF), 1984 .msg = "read dqe poison", 1985 }, 1986 { 1987 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF), 1988 .msg = "read iost poison", 1989 }, 1990 { 1991 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF), 1992 .msg = "read itct poison", 1993 }, 1994 { 1995 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF), 1996 .msg = "read itct ncq poison", 1997 }, 1998 1999 }; 2000 2001 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 2002 { 2003 u32 irq_value, irq_msk; 2004 struct hisi_hba *hisi_hba = p; 2005 struct device *dev = hisi_hba->dev; 2006 struct pci_dev *pdev = hisi_hba->pci_dev; 2007 int i; 2008 2009 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2010 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 2011 2012 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 2013 irq_value &= ~irq_msk; 2014 2015 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 2016 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 2017 2018 if (!(irq_value & error->irq_msk)) 2019 continue; 2020 2021 if (error->sub) { 2022 const struct hisi_sas_hw_error *sub = error->sub; 2023 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 2024 2025 for (; sub->msk || sub->msg; sub++) { 2026 if (!(err_value & sub->msk)) 2027 continue; 2028 2029 dev_err(dev, "%s error (0x%x) found!\n", 2030 sub->msg, irq_value); 2031 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2032 } 2033 } else { 2034 dev_err(dev, "%s error (0x%x) found!\n", 2035 error->msg, irq_value); 2036 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2037 } 2038 2039 if (pdev->revision < 0x21) { 2040 u32 reg_val; 2041 2042 reg_val = hisi_sas_read32(hisi_hba, 2043 AXI_MASTER_CFG_BASE + 2044 AM_CTRL_GLOBAL); 2045 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2046 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2047 AM_CTRL_GLOBAL, reg_val); 2048 } 2049 } 2050 2051 fatal_ecc_int_v3_hw(hisi_hba); 2052 2053 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 2054 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 2055 u32 dev_id = reg_val & ITCT_DEV_MSK; 2056 struct hisi_sas_device *sas_dev = 2057 &hisi_hba->devices[dev_id]; 2058 2059 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 2060 dev_dbg(dev, "clear ITCT ok\n"); 2061 complete(sas_dev->completion); 2062 } 2063 2064 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 2065 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 2066 2067 return IRQ_HANDLED; 2068 } 2069 2070 static void 2071 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 2072 struct hisi_sas_slot *slot) 2073 { 2074 struct task_status_struct *ts = &task->task_status; 2075 struct hisi_sas_complete_v3_hdr *complete_queue = 2076 hisi_hba->complete_hdr[slot->cmplt_queue]; 2077 struct hisi_sas_complete_v3_hdr *complete_hdr = 2078 &complete_queue[slot->cmplt_queue_slot]; 2079 struct hisi_sas_err_record_v3 *record = 2080 hisi_sas_status_buf_addr_mem(slot); 2081 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 2082 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 2083 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 2084 2085 switch (task->task_proto) { 2086 case SAS_PROTOCOL_SSP: 2087 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2088 ts->residual = trans_tx_fail_type; 2089 ts->stat = SAS_DATA_UNDERRUN; 2090 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2091 ts->stat = SAS_QUEUE_FULL; 2092 slot->abort = 1; 2093 } else { 2094 ts->stat = SAS_OPEN_REJECT; 2095 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2096 } 2097 break; 2098 case SAS_PROTOCOL_SATA: 2099 case SAS_PROTOCOL_STP: 2100 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2101 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2102 ts->residual = trans_tx_fail_type; 2103 ts->stat = SAS_DATA_UNDERRUN; 2104 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2105 ts->stat = SAS_PHY_DOWN; 2106 slot->abort = 1; 2107 } else { 2108 ts->stat = SAS_OPEN_REJECT; 2109 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2110 } 2111 hisi_sas_sata_done(task, slot); 2112 break; 2113 case SAS_PROTOCOL_SMP: 2114 ts->stat = SAM_STAT_CHECK_CONDITION; 2115 break; 2116 default: 2117 break; 2118 } 2119 } 2120 2121 static int 2122 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 2123 { 2124 struct sas_task *task = slot->task; 2125 struct hisi_sas_device *sas_dev; 2126 struct device *dev = hisi_hba->dev; 2127 struct task_status_struct *ts; 2128 struct domain_device *device; 2129 struct sas_ha_struct *ha; 2130 enum exec_status sts; 2131 struct hisi_sas_complete_v3_hdr *complete_queue = 2132 hisi_hba->complete_hdr[slot->cmplt_queue]; 2133 struct hisi_sas_complete_v3_hdr *complete_hdr = 2134 &complete_queue[slot->cmplt_queue_slot]; 2135 unsigned long flags; 2136 bool is_internal = slot->is_internal; 2137 u32 dw0, dw1, dw3; 2138 2139 if (unlikely(!task || !task->lldd_task || !task->dev)) 2140 return -EINVAL; 2141 2142 ts = &task->task_status; 2143 device = task->dev; 2144 ha = device->port->ha; 2145 sas_dev = device->lldd_dev; 2146 2147 spin_lock_irqsave(&task->task_state_lock, flags); 2148 task->task_state_flags &= 2149 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 2150 spin_unlock_irqrestore(&task->task_state_lock, flags); 2151 2152 memset(ts, 0, sizeof(*ts)); 2153 ts->resp = SAS_TASK_COMPLETE; 2154 2155 if (unlikely(!sas_dev)) { 2156 dev_dbg(dev, "slot complete: port has not device\n"); 2157 ts->stat = SAS_PHY_DOWN; 2158 goto out; 2159 } 2160 2161 dw0 = le32_to_cpu(complete_hdr->dw0); 2162 dw1 = le32_to_cpu(complete_hdr->dw1); 2163 dw3 = le32_to_cpu(complete_hdr->dw3); 2164 2165 /* 2166 * Use SAS+TMF status codes 2167 */ 2168 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 2169 case STAT_IO_ABORTED: 2170 /* this IO has been aborted by abort command */ 2171 ts->stat = SAS_ABORTED_TASK; 2172 goto out; 2173 case STAT_IO_COMPLETE: 2174 /* internal abort command complete */ 2175 ts->stat = TMF_RESP_FUNC_SUCC; 2176 goto out; 2177 case STAT_IO_NO_DEVICE: 2178 ts->stat = TMF_RESP_FUNC_COMPLETE; 2179 goto out; 2180 case STAT_IO_NOT_VALID: 2181 /* 2182 * abort single IO, the controller can't find the IO 2183 */ 2184 ts->stat = TMF_RESP_FUNC_FAILED; 2185 goto out; 2186 default: 2187 break; 2188 } 2189 2190 /* check for erroneous completion */ 2191 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 2192 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 2193 2194 slot_err_v3_hw(hisi_hba, task, slot); 2195 if (ts->stat != SAS_DATA_UNDERRUN) 2196 dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n", 2197 slot->idx, task, sas_dev->device_id, 2198 dw0, dw1, complete_hdr->act, dw3, 2199 error_info[0], error_info[1], 2200 error_info[2], error_info[3]); 2201 if (unlikely(slot->abort)) 2202 return ts->stat; 2203 goto out; 2204 } 2205 2206 switch (task->task_proto) { 2207 case SAS_PROTOCOL_SSP: { 2208 struct ssp_response_iu *iu = 2209 hisi_sas_status_buf_addr_mem(slot) + 2210 sizeof(struct hisi_sas_err_record); 2211 2212 sas_ssp_task_response(dev, task, iu); 2213 break; 2214 } 2215 case SAS_PROTOCOL_SMP: { 2216 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 2217 void *to = page_address(sg_page(sg_resp)); 2218 2219 ts->stat = SAM_STAT_GOOD; 2220 2221 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 2222 DMA_TO_DEVICE); 2223 memcpy(to + sg_resp->offset, 2224 hisi_sas_status_buf_addr_mem(slot) + 2225 sizeof(struct hisi_sas_err_record), 2226 sg_resp->length); 2227 break; 2228 } 2229 case SAS_PROTOCOL_SATA: 2230 case SAS_PROTOCOL_STP: 2231 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2232 ts->stat = SAM_STAT_GOOD; 2233 hisi_sas_sata_done(task, slot); 2234 break; 2235 default: 2236 ts->stat = SAM_STAT_CHECK_CONDITION; 2237 break; 2238 } 2239 2240 if (!slot->port->port_attached) { 2241 dev_warn(dev, "slot complete: port %d has removed\n", 2242 slot->port->sas_port.id); 2243 ts->stat = SAS_PHY_DOWN; 2244 } 2245 2246 out: 2247 sts = ts->stat; 2248 spin_lock_irqsave(&task->task_state_lock, flags); 2249 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 2250 spin_unlock_irqrestore(&task->task_state_lock, flags); 2251 dev_info(dev, "slot complete: task(%pK) aborted\n", task); 2252 return SAS_ABORTED_TASK; 2253 } 2254 task->task_state_flags |= SAS_TASK_STATE_DONE; 2255 spin_unlock_irqrestore(&task->task_state_lock, flags); 2256 hisi_sas_slot_task_free(hisi_hba, task, slot); 2257 2258 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 2259 spin_lock_irqsave(&device->done_lock, flags); 2260 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 2261 spin_unlock_irqrestore(&device->done_lock, flags); 2262 dev_info(dev, "slot complete: task(%pK) ignored\n ", 2263 task); 2264 return sts; 2265 } 2266 spin_unlock_irqrestore(&device->done_lock, flags); 2267 } 2268 2269 if (task->task_done) 2270 task->task_done(task); 2271 2272 return sts; 2273 } 2274 2275 static void cq_tasklet_v3_hw(unsigned long val) 2276 { 2277 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 2278 struct hisi_hba *hisi_hba = cq->hisi_hba; 2279 struct hisi_sas_slot *slot; 2280 struct hisi_sas_complete_v3_hdr *complete_queue; 2281 u32 rd_point = cq->rd_point, wr_point; 2282 int queue = cq->id; 2283 2284 complete_queue = hisi_hba->complete_hdr[queue]; 2285 2286 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2287 (0x14 * queue)); 2288 2289 while (rd_point != wr_point) { 2290 struct hisi_sas_complete_v3_hdr *complete_hdr; 2291 struct device *dev = hisi_hba->dev; 2292 u32 dw1; 2293 int iptt; 2294 2295 complete_hdr = &complete_queue[rd_point]; 2296 dw1 = le32_to_cpu(complete_hdr->dw1); 2297 2298 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2299 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2300 slot = &hisi_hba->slot_info[iptt]; 2301 slot->cmplt_queue_slot = rd_point; 2302 slot->cmplt_queue = queue; 2303 slot_complete_v3_hw(hisi_hba, slot); 2304 } else 2305 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2306 2307 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2308 rd_point = 0; 2309 } 2310 2311 /* update rd_point */ 2312 cq->rd_point = rd_point; 2313 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2314 } 2315 2316 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2317 { 2318 struct hisi_sas_cq *cq = p; 2319 struct hisi_hba *hisi_hba = cq->hisi_hba; 2320 int queue = cq->id; 2321 2322 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2323 2324 tasklet_schedule(&cq->tasklet); 2325 2326 return IRQ_HANDLED; 2327 } 2328 2329 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) 2330 { 2331 const struct cpumask *mask; 2332 int queue, cpu; 2333 2334 for (queue = 0; queue < nvecs; queue++) { 2335 struct hisi_sas_cq *cq = &hisi_hba->cq[queue]; 2336 2337 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + 2338 BASE_VECTORS_V3_HW); 2339 if (!mask) 2340 goto fallback; 2341 cq->pci_irq_mask = mask; 2342 for_each_cpu(cpu, mask) 2343 hisi_hba->reply_map[cpu] = queue; 2344 } 2345 return; 2346 2347 fallback: 2348 for_each_possible_cpu(cpu) 2349 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count; 2350 /* Don't clean all CQ masks */ 2351 } 2352 2353 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2354 { 2355 struct device *dev = hisi_hba->dev; 2356 struct pci_dev *pdev = hisi_hba->pci_dev; 2357 int vectors, rc, i; 2358 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; 2359 2360 if (auto_affine_msi_experimental) { 2361 struct irq_affinity desc = { 2362 .pre_vectors = BASE_VECTORS_V3_HW, 2363 }; 2364 2365 min_msi = MIN_AFFINE_VECTORS_V3_HW; 2366 2367 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids, 2368 sizeof(unsigned int), 2369 GFP_KERNEL); 2370 if (!hisi_hba->reply_map) 2371 return -ENOMEM; 2372 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev, 2373 min_msi, max_msi, 2374 PCI_IRQ_MSI | 2375 PCI_IRQ_AFFINITY, 2376 &desc); 2377 if (vectors < 0) 2378 return -ENOENT; 2379 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW); 2380 } else { 2381 min_msi = max_msi; 2382 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi, 2383 max_msi, PCI_IRQ_MSI); 2384 if (vectors < 0) 2385 return vectors; 2386 } 2387 2388 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; 2389 2390 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2391 int_phy_up_down_bcast_v3_hw, 0, 2392 DRV_NAME " phy", hisi_hba); 2393 if (rc) { 2394 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2395 rc = -ENOENT; 2396 goto free_irq_vectors; 2397 } 2398 2399 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2400 int_chnl_int_v3_hw, 0, 2401 DRV_NAME " channel", hisi_hba); 2402 if (rc) { 2403 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2404 rc = -ENOENT; 2405 goto free_irq_vectors; 2406 } 2407 2408 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2409 fatal_axi_int_v3_hw, 0, 2410 DRV_NAME " fatal", hisi_hba); 2411 if (rc) { 2412 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2413 rc = -ENOENT; 2414 goto free_irq_vectors; 2415 } 2416 2417 /* Init tasklets for cq only */ 2418 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2419 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2420 struct tasklet_struct *t = &cq->tasklet; 2421 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2422 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2423 2424 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2425 cq_interrupt_v3_hw, irqflags, 2426 DRV_NAME " cq", cq); 2427 if (rc) { 2428 dev_err(dev, "could not request cq%d interrupt, rc=%d\n", 2429 i, rc); 2430 rc = -ENOENT; 2431 goto free_irq_vectors; 2432 } 2433 2434 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2435 } 2436 2437 return 0; 2438 2439 free_irq_vectors: 2440 pci_free_irq_vectors(pdev); 2441 return rc; 2442 } 2443 2444 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2445 { 2446 int rc; 2447 2448 rc = hw_init_v3_hw(hisi_hba); 2449 if (rc) 2450 return rc; 2451 2452 rc = interrupt_init_v3_hw(hisi_hba); 2453 if (rc) 2454 return rc; 2455 2456 return 0; 2457 } 2458 2459 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2460 struct sas_phy_linkrates *r) 2461 { 2462 enum sas_linkrate max = r->maximum_linkrate; 2463 u32 prog_phy_link_rate = 0x800; 2464 2465 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2466 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2467 prog_phy_link_rate); 2468 } 2469 2470 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2471 { 2472 struct pci_dev *pdev = hisi_hba->pci_dev; 2473 int i; 2474 2475 synchronize_irq(pci_irq_vector(pdev, 1)); 2476 synchronize_irq(pci_irq_vector(pdev, 2)); 2477 synchronize_irq(pci_irq_vector(pdev, 11)); 2478 for (i = 0; i < hisi_hba->queue_count; i++) { 2479 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2480 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2481 } 2482 2483 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2484 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2485 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2486 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2487 2488 for (i = 0; i < hisi_hba->n_phy; i++) { 2489 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2490 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2491 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2492 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2493 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2494 } 2495 } 2496 2497 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2498 { 2499 return hisi_sas_read32(hisi_hba, PHY_STATE); 2500 } 2501 2502 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2503 { 2504 struct device *dev = hisi_hba->dev; 2505 u32 status, reg_val; 2506 int rc; 2507 2508 interrupt_disable_v3_hw(hisi_hba); 2509 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2510 hisi_sas_kill_tasklets(hisi_hba); 2511 2512 hisi_sas_stop_phys(hisi_hba); 2513 2514 mdelay(10); 2515 2516 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2517 AM_CTRL_GLOBAL); 2518 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2519 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2520 AM_CTRL_GLOBAL, reg_val); 2521 2522 /* wait until bus idle */ 2523 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2524 AM_CURR_TRANS_RETURN, status, 2525 status == 0x3, 10, 100); 2526 if (rc) { 2527 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2528 return rc; 2529 } 2530 2531 return 0; 2532 } 2533 2534 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2535 { 2536 struct device *dev = hisi_hba->dev; 2537 int rc; 2538 2539 rc = disable_host_v3_hw(hisi_hba); 2540 if (rc) { 2541 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2542 return rc; 2543 } 2544 2545 hisi_sas_init_mem(hisi_hba); 2546 2547 return hw_init_v3_hw(hisi_hba); 2548 } 2549 2550 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2551 u8 reg_index, u8 reg_count, u8 *write_data) 2552 { 2553 struct device *dev = hisi_hba->dev; 2554 u32 *data = (u32 *)write_data; 2555 int i; 2556 2557 switch (reg_type) { 2558 case SAS_GPIO_REG_TX: 2559 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2560 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2561 reg_index, reg_index + reg_count - 1); 2562 return -EINVAL; 2563 } 2564 2565 for (i = 0; i < reg_count; i++) 2566 hisi_sas_write32(hisi_hba, 2567 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2568 data[i]); 2569 break; 2570 default: 2571 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2572 reg_type); 2573 return -EINVAL; 2574 } 2575 2576 return 0; 2577 } 2578 2579 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2580 int delay_ms, int timeout_ms) 2581 { 2582 struct device *dev = hisi_hba->dev; 2583 int entries, entries_old = 0, time; 2584 2585 for (time = 0; time < timeout_ms; time += delay_ms) { 2586 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2587 if (entries == entries_old) 2588 break; 2589 2590 entries_old = entries; 2591 msleep(delay_ms); 2592 } 2593 2594 if (time >= timeout_ms) { 2595 dev_dbg(dev, "Wait commands complete timeout!\n"); 2596 return; 2597 } 2598 2599 dev_dbg(dev, "wait commands complete %dms\n", time); 2600 } 2601 2602 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2603 struct device_attribute *attr, char *buf) 2604 { 2605 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2606 } 2607 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2608 2609 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2610 { 2611 /* config those registers between enable and disable PHYs */ 2612 hisi_sas_stop_phys(hisi_hba); 2613 2614 if (hisi_hba->intr_coal_ticks == 0 || 2615 hisi_hba->intr_coal_count == 0) { 2616 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2617 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2618 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2619 } else { 2620 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2621 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2622 hisi_hba->intr_coal_ticks); 2623 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2624 hisi_hba->intr_coal_count); 2625 } 2626 phys_init_v3_hw(hisi_hba); 2627 } 2628 2629 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2630 struct device_attribute *attr, 2631 char *buf) 2632 { 2633 struct Scsi_Host *shost = class_to_shost(dev); 2634 struct hisi_hba *hisi_hba = shost_priv(shost); 2635 2636 return scnprintf(buf, PAGE_SIZE, "%u\n", 2637 hisi_hba->intr_coal_ticks); 2638 } 2639 2640 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2641 struct device_attribute *attr, 2642 const char *buf, size_t count) 2643 { 2644 struct Scsi_Host *shost = class_to_shost(dev); 2645 struct hisi_hba *hisi_hba = shost_priv(shost); 2646 u32 intr_coal_ticks; 2647 int ret; 2648 2649 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2650 if (ret) { 2651 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2652 return -EINVAL; 2653 } 2654 2655 if (intr_coal_ticks >= BIT(24)) { 2656 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2657 return -EINVAL; 2658 } 2659 2660 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2661 2662 config_intr_coal_v3_hw(hisi_hba); 2663 2664 return count; 2665 } 2666 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2667 2668 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2669 struct device_attribute 2670 *attr, char *buf) 2671 { 2672 struct Scsi_Host *shost = class_to_shost(dev); 2673 struct hisi_hba *hisi_hba = shost_priv(shost); 2674 2675 return scnprintf(buf, PAGE_SIZE, "%u\n", 2676 hisi_hba->intr_coal_count); 2677 } 2678 2679 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2680 struct device_attribute 2681 *attr, const char *buf, size_t count) 2682 { 2683 struct Scsi_Host *shost = class_to_shost(dev); 2684 struct hisi_hba *hisi_hba = shost_priv(shost); 2685 u32 intr_coal_count; 2686 int ret; 2687 2688 ret = kstrtou32(buf, 10, &intr_coal_count); 2689 if (ret) { 2690 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2691 return -EINVAL; 2692 } 2693 2694 if (intr_coal_count >= BIT(8)) { 2695 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2696 return -EINVAL; 2697 } 2698 2699 hisi_hba->intr_coal_count = intr_coal_count; 2700 2701 config_intr_coal_v3_hw(hisi_hba); 2702 2703 return count; 2704 } 2705 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2706 2707 static struct device_attribute *host_attrs_v3_hw[] = { 2708 &dev_attr_phy_event_threshold, 2709 &dev_attr_intr_conv_v3_hw, 2710 &dev_attr_intr_coal_ticks_v3_hw, 2711 &dev_attr_intr_coal_count_v3_hw, 2712 NULL 2713 }; 2714 2715 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2716 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2717 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2718 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2719 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2720 HISI_SAS_DEBUGFS_REG(SL_CFG), 2721 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2722 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2723 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2724 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2725 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2726 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2727 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2728 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2729 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2730 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2731 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2732 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2733 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2734 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2735 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2736 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2737 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2738 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2739 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2740 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2741 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2742 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2743 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2744 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2745 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2746 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2747 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2748 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2749 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2750 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2751 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2752 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2753 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2754 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2755 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2756 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2757 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2758 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2759 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2760 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2761 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2762 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2763 {} 2764 }; 2765 2766 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2767 .lu = debugfs_port_reg_lu, 2768 .count = 0x100, 2769 .base_off = PORT_BASE, 2770 .read_port_reg = hisi_sas_phy_read32, 2771 }; 2772 2773 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2774 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2775 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2776 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2777 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2778 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2779 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2780 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2781 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2782 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2783 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2784 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2785 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2786 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2787 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2788 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2789 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2790 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2791 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2792 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2793 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2794 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2795 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2796 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2797 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2798 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2799 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2800 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2801 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2802 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2803 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2804 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2805 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2806 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2807 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2808 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2809 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2810 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2811 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2812 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2813 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2814 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2815 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2816 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2817 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2818 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2819 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2820 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2821 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2822 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2823 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2824 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2825 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2826 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2827 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2828 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2829 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2830 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2831 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2832 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2833 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2834 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2835 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2836 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2837 {} 2838 }; 2839 2840 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2841 .lu = debugfs_global_reg_lu, 2842 .count = 0x800, 2843 .read_global_reg = hisi_sas_read32, 2844 }; 2845 2846 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = { 2847 HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS), 2848 HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS), 2849 HISI_SAS_DEBUGFS_REG(AXI_CFG), 2850 HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR), 2851 {} 2852 }; 2853 2854 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = { 2855 .lu = debugfs_axi_reg_lu, 2856 .count = 0x61, 2857 .base_off = AXI_MASTER_CFG_BASE, 2858 .read_global_reg = hisi_sas_read32, 2859 }; 2860 2861 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = { 2862 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1), 2863 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK), 2864 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK), 2865 HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK), 2866 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2), 2867 HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK), 2868 {} 2869 }; 2870 2871 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = { 2872 .lu = debugfs_ras_reg_lu, 2873 .count = 0x10, 2874 .base_off = RAS_BASE, 2875 .read_global_reg = hisi_sas_read32, 2876 }; 2877 2878 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2879 { 2880 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2881 2882 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2883 2884 wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000); 2885 2886 hisi_sas_kill_tasklets(hisi_hba); 2887 } 2888 2889 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2890 { 2891 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2892 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2893 2894 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2895 } 2896 2897 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba, 2898 enum hisi_sas_debugfs_cache_type type, 2899 u32 *cache) 2900 { 2901 u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 2902 HISI_SAS_IOST_ITCT_CACHE_NUM; 2903 u32 *buf = cache; 2904 u32 i, val; 2905 2906 hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type); 2907 2908 for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) { 2909 val = hisi_sas_read32(hisi_hba, TAB_DFX); 2910 if (val == 0xffffffff) 2911 break; 2912 } 2913 2914 if (val != 0xffffffff) { 2915 pr_err("Issue occur when reading IOST/ITCT cache!\n"); 2916 return; 2917 } 2918 2919 memset(buf, 0, cache_dw_size * 4); 2920 buf[0] = val; 2921 2922 for (i = 1; i < cache_dw_size; i++) 2923 buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX); 2924 } 2925 2926 static struct scsi_host_template sht_v3_hw = { 2927 .name = DRV_NAME, 2928 .module = THIS_MODULE, 2929 .queuecommand = sas_queuecommand, 2930 .target_alloc = sas_target_alloc, 2931 .slave_configure = hisi_sas_slave_configure, 2932 .scan_finished = hisi_sas_scan_finished, 2933 .scan_start = hisi_sas_scan_start, 2934 .change_queue_depth = sas_change_queue_depth, 2935 .bios_param = sas_bios_param, 2936 .this_id = -1, 2937 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2938 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2939 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2940 .eh_device_reset_handler = sas_eh_device_reset_handler, 2941 .eh_target_reset_handler = sas_eh_target_reset_handler, 2942 .target_destroy = sas_target_destroy, 2943 .ioctl = sas_ioctl, 2944 .shost_attrs = host_attrs_v3_hw, 2945 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2946 .host_reset = hisi_sas_host_reset, 2947 }; 2948 2949 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2950 .hw_init = hisi_sas_v3_init, 2951 .setup_itct = setup_itct_v3_hw, 2952 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2953 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2954 .clear_itct = clear_itct_v3_hw, 2955 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2956 .prep_ssp = prep_ssp_v3_hw, 2957 .prep_smp = prep_smp_v3_hw, 2958 .prep_stp = prep_ata_v3_hw, 2959 .prep_abort = prep_abort_v3_hw, 2960 .start_delivery = start_delivery_v3_hw, 2961 .phys_init = phys_init_v3_hw, 2962 .phy_start = start_phy_v3_hw, 2963 .phy_disable = disable_phy_v3_hw, 2964 .phy_hard_reset = phy_hard_reset_v3_hw, 2965 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2966 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2967 .dereg_device = dereg_device_v3_hw, 2968 .soft_reset = soft_reset_v3_hw, 2969 .get_phys_state = get_phys_state_v3_hw, 2970 .get_events = phy_get_events_v3_hw, 2971 .write_gpio = write_gpio_v3_hw, 2972 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2973 .debugfs_reg_array[DEBUGFS_GLOBAL] = &debugfs_global_reg, 2974 .debugfs_reg_array[DEBUGFS_AXI] = &debugfs_axi_reg, 2975 .debugfs_reg_array[DEBUGFS_RAS] = &debugfs_ras_reg, 2976 .debugfs_reg_port = &debugfs_port_reg, 2977 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2978 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2979 .read_iost_itct_cache = read_iost_itct_cache_v3_hw, 2980 }; 2981 2982 static struct Scsi_Host * 2983 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2984 { 2985 struct Scsi_Host *shost; 2986 struct hisi_hba *hisi_hba; 2987 struct device *dev = &pdev->dev; 2988 2989 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2990 if (!shost) { 2991 dev_err(dev, "shost alloc failed\n"); 2992 return NULL; 2993 } 2994 hisi_hba = shost_priv(shost); 2995 2996 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2997 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2998 hisi_hba->hw = &hisi_sas_v3_hw; 2999 hisi_hba->pci_dev = pdev; 3000 hisi_hba->dev = dev; 3001 hisi_hba->shost = shost; 3002 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 3003 3004 if (prot_mask & ~HISI_SAS_PROT_MASK) 3005 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 3006 prot_mask); 3007 else 3008 hisi_hba->prot_mask = prot_mask; 3009 3010 if (hisi_sas_get_fw_info(hisi_hba) < 0) 3011 goto err_out; 3012 3013 if (hisi_sas_alloc(hisi_hba)) { 3014 hisi_sas_free(hisi_hba); 3015 goto err_out; 3016 } 3017 3018 return shost; 3019 err_out: 3020 scsi_host_put(shost); 3021 dev_err(dev, "shost alloc failed\n"); 3022 return NULL; 3023 } 3024 3025 static int 3026 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3027 { 3028 struct Scsi_Host *shost; 3029 struct hisi_hba *hisi_hba; 3030 struct device *dev = &pdev->dev; 3031 struct asd_sas_phy **arr_phy; 3032 struct asd_sas_port **arr_port; 3033 struct sas_ha_struct *sha; 3034 int rc, phy_nr, port_nr, i; 3035 3036 rc = pci_enable_device(pdev); 3037 if (rc) 3038 goto err_out; 3039 3040 pci_set_master(pdev); 3041 3042 rc = pci_request_regions(pdev, DRV_NAME); 3043 if (rc) 3044 goto err_out_disable_device; 3045 3046 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3047 if (rc) 3048 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3049 if (rc) { 3050 dev_err(dev, "No usable DMA addressing method\n"); 3051 rc = -ENODEV; 3052 goto err_out_regions; 3053 } 3054 3055 shost = hisi_sas_shost_alloc_pci(pdev); 3056 if (!shost) { 3057 rc = -ENOMEM; 3058 goto err_out_regions; 3059 } 3060 3061 sha = SHOST_TO_SAS_HA(shost); 3062 hisi_hba = shost_priv(shost); 3063 dev_set_drvdata(dev, sha); 3064 3065 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 3066 if (!hisi_hba->regs) { 3067 dev_err(dev, "cannot map register\n"); 3068 rc = -ENOMEM; 3069 goto err_out_ha; 3070 } 3071 3072 phy_nr = port_nr = hisi_hba->n_phy; 3073 3074 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 3075 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 3076 if (!arr_phy || !arr_port) { 3077 rc = -ENOMEM; 3078 goto err_out_ha; 3079 } 3080 3081 sha->sas_phy = arr_phy; 3082 sha->sas_port = arr_port; 3083 sha->core.shost = shost; 3084 sha->lldd_ha = hisi_hba; 3085 3086 shost->transportt = hisi_sas_stt; 3087 shost->max_id = HISI_SAS_MAX_DEVICES; 3088 shost->max_lun = ~0; 3089 shost->max_channel = 1; 3090 shost->max_cmd_len = 16; 3091 shost->can_queue = HISI_SAS_UNRESERVED_IPTT; 3092 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT; 3093 3094 sha->sas_ha_name = DRV_NAME; 3095 sha->dev = dev; 3096 sha->lldd_module = THIS_MODULE; 3097 sha->sas_addr = &hisi_hba->sas_addr[0]; 3098 sha->num_phys = hisi_hba->n_phy; 3099 3100 for (i = 0; i < hisi_hba->n_phy; i++) { 3101 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 3102 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 3103 } 3104 3105 if (hisi_hba->prot_mask) { 3106 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 3107 prot_mask); 3108 scsi_host_set_prot(hisi_hba->shost, prot_mask); 3109 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 3110 scsi_host_set_guard(hisi_hba->shost, 3111 SHOST_DIX_GUARD_CRC); 3112 } 3113 3114 if (hisi_sas_debugfs_enable) 3115 hisi_sas_debugfs_init(hisi_hba); 3116 3117 rc = scsi_add_host(shost, dev); 3118 if (rc) 3119 goto err_out_ha; 3120 3121 rc = sas_register_ha(sha); 3122 if (rc) 3123 goto err_out_register_ha; 3124 3125 rc = hisi_hba->hw->hw_init(hisi_hba); 3126 if (rc) 3127 goto err_out_register_ha; 3128 3129 scsi_scan_host(shost); 3130 3131 return 0; 3132 3133 err_out_register_ha: 3134 scsi_remove_host(shost); 3135 err_out_ha: 3136 scsi_host_put(shost); 3137 err_out_regions: 3138 pci_release_regions(pdev); 3139 err_out_disable_device: 3140 pci_disable_device(pdev); 3141 err_out: 3142 return rc; 3143 } 3144 3145 static void 3146 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 3147 { 3148 int i; 3149 3150 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 3151 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 3152 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 3153 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 3154 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 3155 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 3156 3157 free_irq(pci_irq_vector(pdev, nr), cq); 3158 } 3159 pci_free_irq_vectors(pdev); 3160 } 3161 3162 static void hisi_sas_v3_remove(struct pci_dev *pdev) 3163 { 3164 struct device *dev = &pdev->dev; 3165 struct sas_ha_struct *sha = dev_get_drvdata(dev); 3166 struct hisi_hba *hisi_hba = sha->lldd_ha; 3167 struct Scsi_Host *shost = sha->core.shost; 3168 3169 hisi_sas_debugfs_exit(hisi_hba); 3170 3171 if (timer_pending(&hisi_hba->timer)) 3172 del_timer(&hisi_hba->timer); 3173 3174 sas_unregister_ha(sha); 3175 sas_remove_host(sha->core.shost); 3176 3177 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 3178 hisi_sas_kill_tasklets(hisi_hba); 3179 pci_release_regions(pdev); 3180 pci_disable_device(pdev); 3181 hisi_sas_free(hisi_hba); 3182 scsi_host_put(shost); 3183 } 3184 3185 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 3186 { 3187 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3188 struct hisi_hba *hisi_hba = sha->lldd_ha; 3189 struct device *dev = hisi_hba->dev; 3190 int rc; 3191 3192 dev_info(dev, "FLR prepare\n"); 3193 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3194 hisi_sas_controller_reset_prepare(hisi_hba); 3195 3196 rc = disable_host_v3_hw(hisi_hba); 3197 if (rc) 3198 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 3199 } 3200 3201 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3202 { 3203 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3204 struct hisi_hba *hisi_hba = sha->lldd_ha; 3205 struct device *dev = hisi_hba->dev; 3206 int rc; 3207 3208 hisi_sas_init_mem(hisi_hba); 3209 3210 rc = hw_init_v3_hw(hisi_hba); 3211 if (rc) { 3212 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3213 return; 3214 } 3215 3216 hisi_sas_controller_reset_done(hisi_hba); 3217 dev_info(dev, "FLR done\n"); 3218 } 3219 3220 enum { 3221 /* instances of the controller */ 3222 hip08, 3223 }; 3224 3225 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3226 { 3227 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3228 struct hisi_hba *hisi_hba = sha->lldd_ha; 3229 struct device *dev = hisi_hba->dev; 3230 struct Scsi_Host *shost = hisi_hba->shost; 3231 pci_power_t device_state; 3232 int rc; 3233 3234 if (!pdev->pm_cap) { 3235 dev_err(dev, "PCI PM not supported\n"); 3236 return -ENODEV; 3237 } 3238 3239 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3240 return -1; 3241 3242 scsi_block_requests(shost); 3243 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3244 flush_workqueue(hisi_hba->wq); 3245 3246 rc = disable_host_v3_hw(hisi_hba); 3247 if (rc) { 3248 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3249 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3250 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3251 scsi_unblock_requests(shost); 3252 return rc; 3253 } 3254 3255 hisi_sas_init_mem(hisi_hba); 3256 3257 device_state = pci_choose_state(pdev, state); 3258 dev_warn(dev, "entering operating state [D%d]\n", 3259 device_state); 3260 pci_save_state(pdev); 3261 pci_disable_device(pdev); 3262 pci_set_power_state(pdev, device_state); 3263 3264 hisi_sas_release_tasks(hisi_hba); 3265 3266 sas_suspend_ha(sha); 3267 return 0; 3268 } 3269 3270 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3271 { 3272 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3273 struct hisi_hba *hisi_hba = sha->lldd_ha; 3274 struct Scsi_Host *shost = hisi_hba->shost; 3275 struct device *dev = hisi_hba->dev; 3276 unsigned int rc; 3277 pci_power_t device_state = pdev->current_state; 3278 3279 dev_warn(dev, "resuming from operating state [D%d]\n", 3280 device_state); 3281 pci_set_power_state(pdev, PCI_D0); 3282 pci_enable_wake(pdev, PCI_D0, 0); 3283 pci_restore_state(pdev); 3284 rc = pci_enable_device(pdev); 3285 if (rc) { 3286 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3287 return rc; 3288 } 3289 3290 pci_set_master(pdev); 3291 scsi_unblock_requests(shost); 3292 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3293 3294 sas_prep_resume_ha(sha); 3295 rc = hw_init_v3_hw(hisi_hba); 3296 if (rc) { 3297 scsi_remove_host(shost); 3298 pci_disable_device(pdev); 3299 } 3300 hisi_hba->hw->phys_init(hisi_hba); 3301 sas_resume_ha(sha); 3302 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3303 3304 return 0; 3305 } 3306 3307 static const struct pci_device_id sas_v3_pci_table[] = { 3308 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3309 {} 3310 }; 3311 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3312 3313 static const struct pci_error_handlers hisi_sas_err_handler = { 3314 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3315 .reset_done = hisi_sas_reset_done_v3_hw, 3316 }; 3317 3318 static struct pci_driver sas_v3_pci_driver = { 3319 .name = DRV_NAME, 3320 .id_table = sas_v3_pci_table, 3321 .probe = hisi_sas_v3_probe, 3322 .remove = hisi_sas_v3_remove, 3323 .suspend = hisi_sas_v3_suspend, 3324 .resume = hisi_sas_v3_resume, 3325 .err_handler = &hisi_sas_err_handler, 3326 }; 3327 3328 module_pci_driver(sas_v3_pci_driver); 3329 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3330 3331 MODULE_LICENSE("GPL"); 3332 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3333 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3334 MODULE_ALIAS("pci:" DRV_NAME); 3335