1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CFG_AGING_TIME 0xbc 46 #define HGC_DFX_CFG2 0xc0 47 #define CFG_ABT_SET_QUERY_IPTT 0xd4 48 #define CFG_SET_ABORTED_IPTT_OFF 0 49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 50 #define CFG_SET_ABORTED_EN_OFF 12 51 #define CFG_ABT_SET_IPTT_DONE 0xd8 52 #define CFG_ABT_SET_IPTT_DONE_OFF 0 53 #define HGC_IOMB_PROC1_STATUS 0x104 54 #define CFG_1US_TIMER_TRSH 0xcc 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 125 #define PHY_CTRL (PORT_BASE + 0x14) 126 #define PHY_CTRL_RESET_OFF 0 127 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 128 #define SL_CFG (PORT_BASE + 0x84) 129 #define SL_CONTROL (PORT_BASE + 0x94) 130 #define SL_CONTROL_NOTIFY_EN_OFF 0 131 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 132 #define SL_CTA_OFF 17 133 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 134 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 135 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 136 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 137 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 138 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 139 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 140 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 141 #define TXID_AUTO (PORT_BASE + 0xb8) 142 #define CT3_OFF 1 143 #define CT3_MSK (0x1 << CT3_OFF) 144 #define TX_HARDRST_OFF 2 145 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 146 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 147 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 148 #define STP_LINK_TIMER (PORT_BASE + 0x120) 149 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 150 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 151 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 152 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 153 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 154 #define CHL_INT0 (PORT_BASE + 0x1b4) 155 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 156 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 157 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 158 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 159 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 160 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 161 #define CHL_INT0_NOT_RDY_OFF 4 162 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 163 #define CHL_INT0_PHY_RDY_OFF 5 164 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 165 #define CHL_INT1 (PORT_BASE + 0x1b8) 166 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 167 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 168 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 169 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 170 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 171 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 172 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 173 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 174 #define CHL_INT2 (PORT_BASE + 0x1bc) 175 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 176 #define CHL_INT2_RX_INVLD_DW_OFF 30 177 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 178 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 179 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 180 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 181 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 182 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 183 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 184 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 185 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 186 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 187 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 188 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 189 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 190 #define DMA_TX_STATUS_BUSY_OFF 0 191 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 192 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 193 #define DMA_RX_STATUS_BUSY_OFF 0 194 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 195 196 #define COARSETUNE_TIME (PORT_BASE + 0x304) 197 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 198 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 199 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 200 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 201 202 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 203 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 204 #error Max ITCT exceeded 205 #endif 206 207 #define AXI_MASTER_CFG_BASE (0x5000) 208 #define AM_CTRL_GLOBAL (0x0) 209 #define AM_CURR_TRANS_RETURN (0x150) 210 211 #define AM_CFG_MAX_TRANS (0x5010) 212 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 213 #define AXI_CFG (0x5100) 214 #define AM_ROB_ECC_ERR_ADDR (0x510c) 215 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 216 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 217 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 218 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 219 220 /* RAS registers need init */ 221 #define RAS_BASE (0x6000) 222 #define SAS_RAS_INTR0 (RAS_BASE) 223 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 224 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 225 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 226 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 227 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 228 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 229 230 /* HW dma structures */ 231 /* Delivery queue header */ 232 /* dw0 */ 233 #define CMD_HDR_ABORT_FLAG_OFF 0 234 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 235 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 236 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 237 #define CMD_HDR_RESP_REPORT_OFF 5 238 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 239 #define CMD_HDR_TLR_CTRL_OFF 6 240 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 241 #define CMD_HDR_PORT_OFF 18 242 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 243 #define CMD_HDR_PRIORITY_OFF 27 244 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 245 #define CMD_HDR_CMD_OFF 29 246 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 247 /* dw1 */ 248 #define CMD_HDR_UNCON_CMD_OFF 3 249 #define CMD_HDR_DIR_OFF 5 250 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 251 #define CMD_HDR_RESET_OFF 7 252 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 253 #define CMD_HDR_VDTL_OFF 10 254 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 255 #define CMD_HDR_FRAME_TYPE_OFF 11 256 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 257 #define CMD_HDR_DEV_ID_OFF 16 258 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 259 /* dw2 */ 260 #define CMD_HDR_CFL_OFF 0 261 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 262 #define CMD_HDR_NCQ_TAG_OFF 10 263 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 264 #define CMD_HDR_MRFL_OFF 15 265 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 266 #define CMD_HDR_SG_MOD_OFF 24 267 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 268 /* dw3 */ 269 #define CMD_HDR_IPTT_OFF 0 270 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 271 /* dw6 */ 272 #define CMD_HDR_DIF_SGL_LEN_OFF 0 273 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 274 #define CMD_HDR_DATA_SGL_LEN_OFF 16 275 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 276 /* dw7 */ 277 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 278 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 279 #define CMD_HDR_ABORT_IPTT_OFF 16 280 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 281 282 /* Completion header */ 283 /* dw0 */ 284 #define CMPLT_HDR_CMPLT_OFF 0 285 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 286 #define CMPLT_HDR_ERROR_PHASE_OFF 2 287 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 288 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 289 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 290 #define CMPLT_HDR_ERX_OFF 12 291 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 292 #define CMPLT_HDR_ABORT_STAT_OFF 13 293 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 294 /* abort_stat */ 295 #define STAT_IO_NOT_VALID 0x1 296 #define STAT_IO_NO_DEVICE 0x2 297 #define STAT_IO_COMPLETE 0x3 298 #define STAT_IO_ABORTED 0x4 299 /* dw1 */ 300 #define CMPLT_HDR_IPTT_OFF 0 301 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 302 #define CMPLT_HDR_DEV_ID_OFF 16 303 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 304 /* dw3 */ 305 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 306 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 307 308 /* ITCT header */ 309 /* qw0 */ 310 #define ITCT_HDR_DEV_TYPE_OFF 0 311 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 312 #define ITCT_HDR_VALID_OFF 2 313 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 314 #define ITCT_HDR_MCR_OFF 5 315 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 316 #define ITCT_HDR_VLN_OFF 9 317 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 318 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 319 #define ITCT_HDR_AWT_CONTINUE_OFF 25 320 #define ITCT_HDR_PORT_ID_OFF 28 321 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 322 /* qw2 */ 323 #define ITCT_HDR_INLT_OFF 0 324 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 325 #define ITCT_HDR_RTOLT_OFF 48 326 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 327 328 struct hisi_sas_complete_v3_hdr { 329 __le32 dw0; 330 __le32 dw1; 331 __le32 act; 332 __le32 dw3; 333 }; 334 335 struct hisi_sas_err_record_v3 { 336 /* dw0 */ 337 __le32 trans_tx_fail_type; 338 339 /* dw1 */ 340 __le32 trans_rx_fail_type; 341 342 /* dw2 */ 343 __le16 dma_tx_err_type; 344 __le16 sipc_rx_err_type; 345 346 /* dw3 */ 347 __le32 dma_rx_err_type; 348 }; 349 350 #define RX_DATA_LEN_UNDERFLOW_OFF 6 351 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 352 353 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 354 #define HISI_SAS_MSI_COUNT_V3_HW 32 355 356 #define DIR_NO_DATA 0 357 #define DIR_TO_INI 1 358 #define DIR_TO_DEVICE 2 359 #define DIR_RESERVED 3 360 361 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 362 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 363 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 364 ((fis.command == ATA_CMD_DEV_RESET) && \ 365 ((fis.control & ATA_SRST) != 0))) 366 367 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 368 { 369 void __iomem *regs = hisi_hba->regs + off; 370 371 return readl(regs); 372 } 373 374 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 375 { 376 void __iomem *regs = hisi_hba->regs + off; 377 378 return readl_relaxed(regs); 379 } 380 381 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 382 { 383 void __iomem *regs = hisi_hba->regs + off; 384 385 writel(val, regs); 386 } 387 388 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 389 u32 off, u32 val) 390 { 391 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 392 393 writel(val, regs); 394 } 395 396 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 397 int phy_no, u32 off) 398 { 399 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 400 401 return readl(regs); 402 } 403 404 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 405 timeout_us) \ 406 ({ \ 407 void __iomem *regs = hisi_hba->regs + off; \ 408 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 409 }) 410 411 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 412 timeout_us) \ 413 ({ \ 414 void __iomem *regs = hisi_hba->regs + off; \ 415 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 416 }) 417 418 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 419 { 420 struct pci_dev *pdev = hisi_hba->pci_dev; 421 int i; 422 423 /* Global registers init */ 424 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 425 (u32)((1ULL << hisi_hba->queue_count) - 1)); 426 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 427 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 428 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd); 429 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 430 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 431 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 432 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 433 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 434 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 435 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 436 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 437 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 438 if (pdev->revision >= 0x21) 439 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff); 440 else 441 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 442 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 443 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 444 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 445 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 446 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 447 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 448 for (i = 0; i < hisi_hba->queue_count; i++) 449 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 450 451 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 452 453 for (i = 0; i < hisi_hba->n_phy; i++) { 454 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 455 struct asd_sas_phy *sas_phy = &phy->sas_phy; 456 u32 prog_phy_link_rate = 0x800; 457 458 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 459 SAS_LINK_RATE_1_5_GBPS)) { 460 prog_phy_link_rate = 0x855; 461 } else { 462 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 463 464 prog_phy_link_rate = 465 hisi_sas_get_prog_phy_linkrate_mask(max) | 466 0x800; 467 } 468 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 469 prog_phy_link_rate); 470 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 471 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 472 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 473 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 474 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 475 if (pdev->revision >= 0x21) 476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 477 0xffffffff); 478 else 479 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 480 0xff87ffff); 481 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 482 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 483 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 484 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 485 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 486 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 487 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 488 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 489 490 /* used for 12G negotiate */ 491 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 492 } 493 494 for (i = 0; i < hisi_hba->queue_count; i++) { 495 /* Delivery queue */ 496 hisi_sas_write32(hisi_hba, 497 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 498 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 499 500 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 501 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 502 503 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 504 HISI_SAS_QUEUE_SLOTS); 505 506 /* Completion queue */ 507 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 508 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 509 510 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 511 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 512 513 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 514 HISI_SAS_QUEUE_SLOTS); 515 } 516 517 /* itct */ 518 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 519 lower_32_bits(hisi_hba->itct_dma)); 520 521 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 522 upper_32_bits(hisi_hba->itct_dma)); 523 524 /* iost */ 525 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 526 lower_32_bits(hisi_hba->iost_dma)); 527 528 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 529 upper_32_bits(hisi_hba->iost_dma)); 530 531 /* breakpoint */ 532 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 533 lower_32_bits(hisi_hba->breakpoint_dma)); 534 535 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 536 upper_32_bits(hisi_hba->breakpoint_dma)); 537 538 /* SATA broken msg */ 539 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 540 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 541 542 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 543 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 544 545 /* SATA initial fis */ 546 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 547 lower_32_bits(hisi_hba->initial_fis_dma)); 548 549 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 550 upper_32_bits(hisi_hba->initial_fis_dma)); 551 552 /* RAS registers init */ 553 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 554 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 555 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 556 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 557 558 /* LED registers init */ 559 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 560 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 561 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 562 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 563 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 564 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 565 } 566 567 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 568 { 569 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 570 571 cfg &= ~PHY_CFG_DC_OPT_MSK; 572 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 573 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 574 } 575 576 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 577 { 578 struct sas_identify_frame identify_frame; 579 u32 *identify_buffer; 580 581 memset(&identify_frame, 0, sizeof(identify_frame)); 582 identify_frame.dev_type = SAS_END_DEVICE; 583 identify_frame.frame_type = 0; 584 identify_frame._un1 = 1; 585 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 586 identify_frame.target_bits = SAS_PROTOCOL_NONE; 587 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 588 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 589 identify_frame.phy_id = phy_no; 590 identify_buffer = (u32 *)(&identify_frame); 591 592 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 593 __swab32(identify_buffer[0])); 594 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 595 __swab32(identify_buffer[1])); 596 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 597 __swab32(identify_buffer[2])); 598 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 599 __swab32(identify_buffer[3])); 600 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 601 __swab32(identify_buffer[4])); 602 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 603 __swab32(identify_buffer[5])); 604 } 605 606 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 607 struct hisi_sas_device *sas_dev) 608 { 609 struct domain_device *device = sas_dev->sas_device; 610 struct device *dev = hisi_hba->dev; 611 u64 qw0, device_id = sas_dev->device_id; 612 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 613 struct domain_device *parent_dev = device->parent; 614 struct asd_sas_port *sas_port = device->port; 615 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 616 617 memset(itct, 0, sizeof(*itct)); 618 619 /* qw0 */ 620 qw0 = 0; 621 switch (sas_dev->dev_type) { 622 case SAS_END_DEVICE: 623 case SAS_EDGE_EXPANDER_DEVICE: 624 case SAS_FANOUT_EXPANDER_DEVICE: 625 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 626 break; 627 case SAS_SATA_DEV: 628 case SAS_SATA_PENDING: 629 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 630 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 631 else 632 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 633 break; 634 default: 635 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 636 sas_dev->dev_type); 637 } 638 639 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 640 (device->linkrate << ITCT_HDR_MCR_OFF) | 641 (1 << ITCT_HDR_VLN_OFF) | 642 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 643 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 644 (port->id << ITCT_HDR_PORT_ID_OFF)); 645 itct->qw0 = cpu_to_le64(qw0); 646 647 /* qw1 */ 648 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 649 itct->sas_addr = __swab64(itct->sas_addr); 650 651 /* qw2 */ 652 if (!dev_is_sata(device)) 653 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 654 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 655 } 656 657 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 658 struct hisi_sas_device *sas_dev) 659 { 660 DECLARE_COMPLETION_ONSTACK(completion); 661 u64 dev_id = sas_dev->device_id; 662 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 663 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 664 665 sas_dev->completion = &completion; 666 667 /* clear the itct interrupt state */ 668 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 669 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 670 ENT_INT_SRC3_ITC_INT_MSK); 671 672 /* clear the itct table*/ 673 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 674 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 675 676 wait_for_completion(sas_dev->completion); 677 memset(itct, 0, sizeof(struct hisi_sas_itct)); 678 } 679 680 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 681 struct domain_device *device) 682 { 683 struct hisi_sas_slot *slot, *slot2; 684 struct hisi_sas_device *sas_dev = device->lldd_dev; 685 u32 cfg_abt_set_query_iptt; 686 687 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 688 CFG_ABT_SET_QUERY_IPTT); 689 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 690 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 691 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 692 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 693 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 694 cfg_abt_set_query_iptt); 695 } 696 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 697 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 698 cfg_abt_set_query_iptt); 699 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 700 1 << CFG_ABT_SET_IPTT_DONE_OFF); 701 } 702 703 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 704 { 705 struct device *dev = hisi_hba->dev; 706 int ret; 707 u32 val; 708 709 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 710 711 /* Disable all of the PHYs */ 712 hisi_sas_stop_phys(hisi_hba); 713 udelay(50); 714 715 /* Ensure axi bus idle */ 716 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 717 20000, 1000000); 718 if (ret) { 719 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 720 return -EIO; 721 } 722 723 if (ACPI_HANDLE(dev)) { 724 acpi_status s; 725 726 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 727 if (ACPI_FAILURE(s)) { 728 dev_err(dev, "Reset failed\n"); 729 return -EIO; 730 } 731 } else { 732 dev_err(dev, "no reset method!\n"); 733 return -EINVAL; 734 } 735 736 return 0; 737 } 738 739 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 740 { 741 struct device *dev = hisi_hba->dev; 742 int rc; 743 744 rc = reset_hw_v3_hw(hisi_hba); 745 if (rc) { 746 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 747 return rc; 748 } 749 750 msleep(100); 751 init_reg_v3_hw(hisi_hba); 752 753 return 0; 754 } 755 756 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 757 { 758 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 759 760 cfg |= PHY_CFG_ENA_MSK; 761 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 762 } 763 764 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 765 { 766 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 767 768 cfg &= ~PHY_CFG_ENA_MSK; 769 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 770 } 771 772 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 773 { 774 config_id_frame_v3_hw(hisi_hba, phy_no); 775 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 776 enable_phy_v3_hw(hisi_hba, phy_no); 777 } 778 779 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 780 { 781 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 782 u32 txid_auto; 783 784 disable_phy_v3_hw(hisi_hba, phy_no); 785 if (phy->identify.device_type == SAS_END_DEVICE) { 786 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 787 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 788 txid_auto | TX_HARDRST_MSK); 789 } 790 msleep(100); 791 start_phy_v3_hw(hisi_hba, phy_no); 792 } 793 794 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 795 { 796 return SAS_LINK_RATE_12_0_GBPS; 797 } 798 799 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 800 { 801 int i; 802 803 for (i = 0; i < hisi_hba->n_phy; i++) { 804 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 805 struct asd_sas_phy *sas_phy = &phy->sas_phy; 806 807 if (!sas_phy->phy->enabled) 808 continue; 809 810 start_phy_v3_hw(hisi_hba, i); 811 } 812 } 813 814 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 815 { 816 u32 sl_control; 817 818 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 819 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 820 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 821 msleep(1); 822 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 823 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 824 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 825 } 826 827 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 828 { 829 int i, bitmap = 0; 830 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 831 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 832 833 for (i = 0; i < hisi_hba->n_phy; i++) 834 if (phy_state & BIT(i)) 835 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 836 bitmap |= BIT(i); 837 838 return bitmap; 839 } 840 841 /** 842 * The callpath to this function and upto writing the write 843 * queue pointer should be safe from interruption. 844 */ 845 static int 846 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 847 { 848 struct device *dev = hisi_hba->dev; 849 int queue = dq->id; 850 u32 r, w; 851 852 w = dq->wr_point; 853 r = hisi_sas_read32_relaxed(hisi_hba, 854 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 855 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 856 dev_warn(dev, "full queue=%d r=%d w=%d\n", 857 queue, r, w); 858 return -EAGAIN; 859 } 860 861 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 862 863 return w; 864 } 865 866 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 867 { 868 struct hisi_hba *hisi_hba = dq->hisi_hba; 869 struct hisi_sas_slot *s, *s1; 870 struct list_head *dq_list; 871 int dlvry_queue = dq->id; 872 int wp, count = 0; 873 874 dq_list = &dq->list; 875 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 876 if (!s->ready) 877 break; 878 count++; 879 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 880 list_del(&s->delivery); 881 } 882 883 if (!count) 884 return; 885 886 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 887 } 888 889 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 890 struct hisi_sas_slot *slot, 891 struct hisi_sas_cmd_hdr *hdr, 892 struct scatterlist *scatter, 893 int n_elem) 894 { 895 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 896 struct scatterlist *sg; 897 int i; 898 899 for_each_sg(scatter, sg, n_elem, i) { 900 struct hisi_sas_sge *entry = &sge_page->sge[i]; 901 902 entry->addr = cpu_to_le64(sg_dma_address(sg)); 903 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 904 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 905 entry->data_off = 0; 906 } 907 908 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 909 910 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 911 } 912 913 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 914 struct hisi_sas_slot *slot) 915 { 916 struct sas_task *task = slot->task; 917 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 918 struct domain_device *device = task->dev; 919 struct hisi_sas_device *sas_dev = device->lldd_dev; 920 struct hisi_sas_port *port = slot->port; 921 struct sas_ssp_task *ssp_task = &task->ssp_task; 922 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 923 struct hisi_sas_tmf_task *tmf = slot->tmf; 924 int has_data = 0, priority = !!tmf; 925 u8 *buf_cmd; 926 u32 dw1 = 0, dw2 = 0; 927 928 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 929 (2 << CMD_HDR_TLR_CTRL_OFF) | 930 (port->id << CMD_HDR_PORT_OFF) | 931 (priority << CMD_HDR_PRIORITY_OFF) | 932 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 933 934 dw1 = 1 << CMD_HDR_VDTL_OFF; 935 if (tmf) { 936 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 937 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 938 } else { 939 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 940 switch (scsi_cmnd->sc_data_direction) { 941 case DMA_TO_DEVICE: 942 has_data = 1; 943 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 944 break; 945 case DMA_FROM_DEVICE: 946 has_data = 1; 947 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 948 break; 949 default: 950 dw1 &= ~CMD_HDR_DIR_MSK; 951 } 952 } 953 954 /* map itct entry */ 955 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 956 hdr->dw1 = cpu_to_le32(dw1); 957 958 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 959 + 3) / 4) << CMD_HDR_CFL_OFF) | 960 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 961 (2 << CMD_HDR_SG_MOD_OFF); 962 hdr->dw2 = cpu_to_le32(dw2); 963 hdr->transfer_tags = cpu_to_le32(slot->idx); 964 965 if (has_data) 966 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 967 slot->n_elem); 968 969 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 970 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 971 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 972 973 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 974 sizeof(struct ssp_frame_hdr); 975 976 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 977 if (!tmf) { 978 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 979 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 980 } else { 981 buf_cmd[10] = tmf->tmf; 982 switch (tmf->tmf) { 983 case TMF_ABORT_TASK: 984 case TMF_QUERY_TASK: 985 buf_cmd[12] = 986 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 987 buf_cmd[13] = 988 tmf->tag_of_task_to_be_managed & 0xff; 989 break; 990 default: 991 break; 992 } 993 } 994 } 995 996 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 997 struct hisi_sas_slot *slot) 998 { 999 struct sas_task *task = slot->task; 1000 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1001 struct domain_device *device = task->dev; 1002 struct hisi_sas_port *port = slot->port; 1003 struct scatterlist *sg_req; 1004 struct hisi_sas_device *sas_dev = device->lldd_dev; 1005 dma_addr_t req_dma_addr; 1006 unsigned int req_len; 1007 1008 /* req */ 1009 sg_req = &task->smp_task.smp_req; 1010 req_len = sg_dma_len(sg_req); 1011 req_dma_addr = sg_dma_address(sg_req); 1012 1013 /* create header */ 1014 /* dw0 */ 1015 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1016 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1017 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1018 1019 /* map itct entry */ 1020 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1021 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1022 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1023 1024 /* dw2 */ 1025 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1026 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1027 CMD_HDR_MRFL_OFF)); 1028 1029 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1030 1031 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1032 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1033 1034 } 1035 1036 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1037 struct hisi_sas_slot *slot) 1038 { 1039 struct sas_task *task = slot->task; 1040 struct domain_device *device = task->dev; 1041 struct domain_device *parent_dev = device->parent; 1042 struct hisi_sas_device *sas_dev = device->lldd_dev; 1043 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1044 struct asd_sas_port *sas_port = device->port; 1045 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1046 u8 *buf_cmd; 1047 int has_data = 0, hdr_tag = 0; 1048 u32 dw1 = 0, dw2 = 0; 1049 1050 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1051 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1052 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1053 else 1054 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1055 1056 switch (task->data_dir) { 1057 case DMA_TO_DEVICE: 1058 has_data = 1; 1059 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1060 break; 1061 case DMA_FROM_DEVICE: 1062 has_data = 1; 1063 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1064 break; 1065 default: 1066 dw1 &= ~CMD_HDR_DIR_MSK; 1067 } 1068 1069 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1070 (task->ata_task.fis.control & ATA_SRST)) 1071 dw1 |= 1 << CMD_HDR_RESET_OFF; 1072 1073 dw1 |= (hisi_sas_get_ata_protocol( 1074 &task->ata_task.fis, task->data_dir)) 1075 << CMD_HDR_FRAME_TYPE_OFF; 1076 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1077 1078 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1079 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1080 1081 hdr->dw1 = cpu_to_le32(dw1); 1082 1083 /* dw2 */ 1084 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1085 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1086 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1087 } 1088 1089 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1090 2 << CMD_HDR_SG_MOD_OFF; 1091 hdr->dw2 = cpu_to_le32(dw2); 1092 1093 /* dw3 */ 1094 hdr->transfer_tags = cpu_to_le32(slot->idx); 1095 1096 if (has_data) 1097 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1098 slot->n_elem); 1099 1100 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1101 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1102 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1103 1104 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1105 1106 if (likely(!task->ata_task.device_control_reg_update)) 1107 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1108 /* fill in command FIS */ 1109 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1110 } 1111 1112 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1113 struct hisi_sas_slot *slot, 1114 int device_id, int abort_flag, int tag_to_abort) 1115 { 1116 struct sas_task *task = slot->task; 1117 struct domain_device *dev = task->dev; 1118 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1119 struct hisi_sas_port *port = slot->port; 1120 1121 /* dw0 */ 1122 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1123 (port->id << CMD_HDR_PORT_OFF) | 1124 (dev_is_sata(dev) 1125 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1126 (abort_flag 1127 << CMD_HDR_ABORT_FLAG_OFF)); 1128 1129 /* dw1 */ 1130 hdr->dw1 = cpu_to_le32(device_id 1131 << CMD_HDR_DEV_ID_OFF); 1132 1133 /* dw7 */ 1134 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1135 hdr->transfer_tags = cpu_to_le32(slot->idx); 1136 1137 } 1138 1139 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1140 { 1141 int i, res; 1142 u32 context, port_id, link_rate; 1143 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1144 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1145 struct device *dev = hisi_hba->dev; 1146 unsigned long flags; 1147 1148 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1149 1150 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1151 port_id = (port_id >> (4 * phy_no)) & 0xf; 1152 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1153 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1154 1155 if (port_id == 0xf) { 1156 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1157 res = IRQ_NONE; 1158 goto end; 1159 } 1160 sas_phy->linkrate = link_rate; 1161 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1162 1163 /* Check for SATA dev */ 1164 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1165 if (context & (1 << phy_no)) { 1166 struct hisi_sas_initial_fis *initial_fis; 1167 struct dev_to_host_fis *fis; 1168 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1169 1170 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1171 initial_fis = &hisi_hba->initial_fis[phy_no]; 1172 fis = &initial_fis->fis; 1173 sas_phy->oob_mode = SATA_OOB_MODE; 1174 attached_sas_addr[0] = 0x50; 1175 attached_sas_addr[7] = phy_no; 1176 memcpy(sas_phy->attached_sas_addr, 1177 attached_sas_addr, 1178 SAS_ADDR_SIZE); 1179 memcpy(sas_phy->frame_rcvd, fis, 1180 sizeof(struct dev_to_host_fis)); 1181 phy->phy_type |= PORT_TYPE_SATA; 1182 phy->identify.device_type = SAS_SATA_DEV; 1183 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1184 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1185 } else { 1186 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1187 struct sas_identify_frame *id = 1188 (struct sas_identify_frame *)frame_rcvd; 1189 1190 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1191 for (i = 0; i < 6; i++) { 1192 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1193 RX_IDAF_DWORD0 + (i * 4)); 1194 frame_rcvd[i] = __swab32(idaf); 1195 } 1196 sas_phy->oob_mode = SAS_OOB_MODE; 1197 memcpy(sas_phy->attached_sas_addr, 1198 &id->sas_addr, 1199 SAS_ADDR_SIZE); 1200 phy->phy_type |= PORT_TYPE_SAS; 1201 phy->identify.device_type = id->dev_type; 1202 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1203 if (phy->identify.device_type == SAS_END_DEVICE) 1204 phy->identify.target_port_protocols = 1205 SAS_PROTOCOL_SSP; 1206 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1207 phy->identify.target_port_protocols = 1208 SAS_PROTOCOL_SMP; 1209 } 1210 1211 phy->port_id = port_id; 1212 phy->phy_attached = 1; 1213 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1214 res = IRQ_HANDLED; 1215 spin_lock_irqsave(&phy->lock, flags); 1216 if (phy->reset_completion) { 1217 phy->in_reset = 0; 1218 complete(phy->reset_completion); 1219 } 1220 spin_unlock_irqrestore(&phy->lock, flags); 1221 end: 1222 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1223 CHL_INT0_SL_PHY_ENABLE_MSK); 1224 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1225 1226 return res; 1227 } 1228 1229 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1230 { 1231 u32 phy_state, sl_ctrl, txid_auto; 1232 struct device *dev = hisi_hba->dev; 1233 1234 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1235 1236 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1237 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1238 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1239 1240 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1241 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1242 sl_ctrl&(~SL_CTA_MSK)); 1243 1244 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1245 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1246 txid_auto | CT3_MSK); 1247 1248 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1249 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1250 1251 return IRQ_HANDLED; 1252 } 1253 1254 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1255 { 1256 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1257 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1258 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1259 1260 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1261 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1262 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1263 CHL_INT0_SL_RX_BCST_ACK_MSK); 1264 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1265 1266 return IRQ_HANDLED; 1267 } 1268 1269 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1270 { 1271 struct hisi_hba *hisi_hba = p; 1272 u32 irq_msk; 1273 int phy_no = 0; 1274 irqreturn_t res = IRQ_NONE; 1275 1276 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1277 & 0x11111111; 1278 while (irq_msk) { 1279 if (irq_msk & 1) { 1280 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1281 CHL_INT0); 1282 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1283 int rdy = phy_state & (1 << phy_no); 1284 1285 if (rdy) { 1286 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1287 /* phy up */ 1288 if (phy_up_v3_hw(phy_no, hisi_hba) 1289 == IRQ_HANDLED) 1290 res = IRQ_HANDLED; 1291 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1292 /* phy bcast */ 1293 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1294 == IRQ_HANDLED) 1295 res = IRQ_HANDLED; 1296 } else { 1297 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1298 /* phy down */ 1299 if (phy_down_v3_hw(phy_no, hisi_hba) 1300 == IRQ_HANDLED) 1301 res = IRQ_HANDLED; 1302 } 1303 } 1304 irq_msk >>= 4; 1305 phy_no++; 1306 } 1307 1308 return res; 1309 } 1310 1311 static const struct hisi_sas_hw_error port_axi_error[] = { 1312 { 1313 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1314 .msg = "dma_tx_axi_wr_err", 1315 }, 1316 { 1317 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1318 .msg = "dma_tx_axi_rd_err", 1319 }, 1320 { 1321 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1322 .msg = "dma_rx_axi_wr_err", 1323 }, 1324 { 1325 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1326 .msg = "dma_rx_axi_rd_err", 1327 }, 1328 }; 1329 1330 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1331 { 1332 struct hisi_hba *hisi_hba = p; 1333 struct device *dev = hisi_hba->dev; 1334 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1335 u32 irq_msk; 1336 int phy_no = 0; 1337 1338 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1339 & 0xeeeeeeee; 1340 1341 while (irq_msk) { 1342 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1343 CHL_INT0); 1344 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1345 CHL_INT1); 1346 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1347 CHL_INT2); 1348 u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1349 CHL_INT1_MSK); 1350 u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1351 CHL_INT2_MSK); 1352 1353 irq_value1 &= ~irq_msk1; 1354 irq_value2 &= ~irq_msk2; 1355 1356 if ((irq_msk & (4 << (phy_no * 4))) && 1357 irq_value1) { 1358 int i; 1359 1360 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1361 const struct hisi_sas_hw_error *error = 1362 &port_axi_error[i]; 1363 1364 if (!(irq_value1 & error->irq_msk)) 1365 continue; 1366 1367 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1368 error->msg, phy_no, irq_value1); 1369 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1370 } 1371 1372 hisi_sas_phy_write32(hisi_hba, phy_no, 1373 CHL_INT1, irq_value1); 1374 } 1375 1376 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) { 1377 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1378 1379 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1380 dev_warn(dev, "phy%d identify timeout\n", 1381 phy_no); 1382 hisi_sas_notify_phy_event(phy, 1383 HISI_PHYE_LINK_RESET); 1384 1385 } 1386 1387 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1388 u32 reg_value = hisi_sas_phy_read32(hisi_hba, 1389 phy_no, STP_LINK_TIMEOUT_STATE); 1390 1391 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1392 phy_no, reg_value); 1393 if (reg_value & BIT(4)) 1394 hisi_sas_notify_phy_event(phy, 1395 HISI_PHYE_LINK_RESET); 1396 } 1397 1398 hisi_sas_phy_write32(hisi_hba, phy_no, 1399 CHL_INT2, irq_value2); 1400 1401 if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1402 (pci_dev->revision == 0x20)) { 1403 u32 reg_value; 1404 int rc; 1405 1406 rc = hisi_sas_read32_poll_timeout_atomic( 1407 HILINK_ERR_DFX, reg_value, 1408 !((reg_value >> 8) & BIT(phy_no)), 1409 1000, 10000); 1410 if (rc) { 1411 disable_phy_v3_hw(hisi_hba, phy_no); 1412 hisi_sas_phy_write32(hisi_hba, phy_no, 1413 CHL_INT2, 1414 BIT(CHL_INT2_RX_INVLD_DW_OFF)); 1415 hisi_sas_phy_read32(hisi_hba, phy_no, 1416 ERR_CNT_INVLD_DW); 1417 mdelay(1); 1418 enable_phy_v3_hw(hisi_hba, phy_no); 1419 } 1420 } 1421 } 1422 1423 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1424 hisi_sas_phy_write32(hisi_hba, phy_no, 1425 CHL_INT0, irq_value0 1426 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1427 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1428 & (~CHL_INT0_NOT_RDY_MSK)); 1429 } 1430 irq_msk &= ~(0xe << (phy_no * 4)); 1431 phy_no++; 1432 } 1433 1434 return IRQ_HANDLED; 1435 } 1436 1437 static const struct hisi_sas_hw_error axi_error[] = { 1438 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1439 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1440 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1441 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1442 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1443 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1444 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1445 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1446 {}, 1447 }; 1448 1449 static const struct hisi_sas_hw_error fifo_error[] = { 1450 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1451 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1452 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1453 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1454 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1455 {}, 1456 }; 1457 1458 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1459 { 1460 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1461 .msg = "write pointer and depth", 1462 }, 1463 { 1464 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1465 .msg = "iptt no match slot", 1466 }, 1467 { 1468 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1469 .msg = "read pointer and depth", 1470 }, 1471 { 1472 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1473 .reg = HGC_AXI_FIFO_ERR_INFO, 1474 .sub = axi_error, 1475 }, 1476 { 1477 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1478 .reg = HGC_AXI_FIFO_ERR_INFO, 1479 .sub = fifo_error, 1480 }, 1481 { 1482 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1483 .msg = "LM add/fetch list", 1484 }, 1485 { 1486 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1487 .msg = "SAS_HGC_ABT fetch LM list", 1488 }, 1489 }; 1490 1491 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1492 { 1493 u32 irq_value, irq_msk; 1494 struct hisi_hba *hisi_hba = p; 1495 struct device *dev = hisi_hba->dev; 1496 int i; 1497 1498 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1499 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1500 1501 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1502 irq_value &= ~irq_msk; 1503 1504 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1505 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1506 1507 if (!(irq_value & error->irq_msk)) 1508 continue; 1509 1510 if (error->sub) { 1511 const struct hisi_sas_hw_error *sub = error->sub; 1512 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1513 1514 for (; sub->msk || sub->msg; sub++) { 1515 if (!(err_value & sub->msk)) 1516 continue; 1517 1518 dev_err(dev, "%s error (0x%x) found!\n", 1519 sub->msg, irq_value); 1520 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1521 } 1522 } else { 1523 dev_err(dev, "%s error (0x%x) found!\n", 1524 error->msg, irq_value); 1525 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1526 } 1527 } 1528 1529 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1530 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1531 u32 dev_id = reg_val & ITCT_DEV_MSK; 1532 struct hisi_sas_device *sas_dev = 1533 &hisi_hba->devices[dev_id]; 1534 1535 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1536 dev_dbg(dev, "clear ITCT ok\n"); 1537 complete(sas_dev->completion); 1538 } 1539 1540 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1541 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1542 1543 return IRQ_HANDLED; 1544 } 1545 1546 static void 1547 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1548 struct hisi_sas_slot *slot) 1549 { 1550 struct task_status_struct *ts = &task->task_status; 1551 struct hisi_sas_complete_v3_hdr *complete_queue = 1552 hisi_hba->complete_hdr[slot->cmplt_queue]; 1553 struct hisi_sas_complete_v3_hdr *complete_hdr = 1554 &complete_queue[slot->cmplt_queue_slot]; 1555 struct hisi_sas_err_record_v3 *record = 1556 hisi_sas_status_buf_addr_mem(slot); 1557 u32 dma_rx_err_type = record->dma_rx_err_type; 1558 u32 trans_tx_fail_type = record->trans_tx_fail_type; 1559 1560 switch (task->task_proto) { 1561 case SAS_PROTOCOL_SSP: 1562 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1563 ts->residual = trans_tx_fail_type; 1564 ts->stat = SAS_DATA_UNDERRUN; 1565 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1566 ts->stat = SAS_QUEUE_FULL; 1567 slot->abort = 1; 1568 } else { 1569 ts->stat = SAS_OPEN_REJECT; 1570 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1571 } 1572 break; 1573 case SAS_PROTOCOL_SATA: 1574 case SAS_PROTOCOL_STP: 1575 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1576 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1577 ts->residual = trans_tx_fail_type; 1578 ts->stat = SAS_DATA_UNDERRUN; 1579 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1580 ts->stat = SAS_PHY_DOWN; 1581 slot->abort = 1; 1582 } else { 1583 ts->stat = SAS_OPEN_REJECT; 1584 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1585 } 1586 hisi_sas_sata_done(task, slot); 1587 break; 1588 case SAS_PROTOCOL_SMP: 1589 ts->stat = SAM_STAT_CHECK_CONDITION; 1590 break; 1591 default: 1592 break; 1593 } 1594 } 1595 1596 static int 1597 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1598 { 1599 struct sas_task *task = slot->task; 1600 struct hisi_sas_device *sas_dev; 1601 struct device *dev = hisi_hba->dev; 1602 struct task_status_struct *ts; 1603 struct domain_device *device; 1604 struct sas_ha_struct *ha; 1605 enum exec_status sts; 1606 struct hisi_sas_complete_v3_hdr *complete_queue = 1607 hisi_hba->complete_hdr[slot->cmplt_queue]; 1608 struct hisi_sas_complete_v3_hdr *complete_hdr = 1609 &complete_queue[slot->cmplt_queue_slot]; 1610 unsigned long flags; 1611 bool is_internal = slot->is_internal; 1612 1613 if (unlikely(!task || !task->lldd_task || !task->dev)) 1614 return -EINVAL; 1615 1616 ts = &task->task_status; 1617 device = task->dev; 1618 ha = device->port->ha; 1619 sas_dev = device->lldd_dev; 1620 1621 spin_lock_irqsave(&task->task_state_lock, flags); 1622 task->task_state_flags &= 1623 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1624 spin_unlock_irqrestore(&task->task_state_lock, flags); 1625 1626 memset(ts, 0, sizeof(*ts)); 1627 ts->resp = SAS_TASK_COMPLETE; 1628 1629 if (unlikely(!sas_dev)) { 1630 dev_dbg(dev, "slot complete: port has not device\n"); 1631 ts->stat = SAS_PHY_DOWN; 1632 goto out; 1633 } 1634 1635 /* 1636 * Use SAS+TMF status codes 1637 */ 1638 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1639 >> CMPLT_HDR_ABORT_STAT_OFF) { 1640 case STAT_IO_ABORTED: 1641 /* this IO has been aborted by abort command */ 1642 ts->stat = SAS_ABORTED_TASK; 1643 goto out; 1644 case STAT_IO_COMPLETE: 1645 /* internal abort command complete */ 1646 ts->stat = TMF_RESP_FUNC_SUCC; 1647 goto out; 1648 case STAT_IO_NO_DEVICE: 1649 ts->stat = TMF_RESP_FUNC_COMPLETE; 1650 goto out; 1651 case STAT_IO_NOT_VALID: 1652 /* 1653 * abort single IO, the controller can't find the IO 1654 */ 1655 ts->stat = TMF_RESP_FUNC_FAILED; 1656 goto out; 1657 default: 1658 break; 1659 } 1660 1661 /* check for erroneous completion */ 1662 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1663 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1664 1665 slot_err_v3_hw(hisi_hba, task, slot); 1666 if (ts->stat != SAS_DATA_UNDERRUN) 1667 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1668 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1669 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1670 slot->idx, task, sas_dev->device_id, 1671 complete_hdr->dw0, complete_hdr->dw1, 1672 complete_hdr->act, complete_hdr->dw3, 1673 error_info[0], error_info[1], 1674 error_info[2], error_info[3]); 1675 if (unlikely(slot->abort)) 1676 return ts->stat; 1677 goto out; 1678 } 1679 1680 switch (task->task_proto) { 1681 case SAS_PROTOCOL_SSP: { 1682 struct ssp_response_iu *iu = 1683 hisi_sas_status_buf_addr_mem(slot) + 1684 sizeof(struct hisi_sas_err_record); 1685 1686 sas_ssp_task_response(dev, task, iu); 1687 break; 1688 } 1689 case SAS_PROTOCOL_SMP: { 1690 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1691 void *to; 1692 1693 ts->stat = SAM_STAT_GOOD; 1694 to = kmap_atomic(sg_page(sg_resp)); 1695 1696 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1697 DMA_FROM_DEVICE); 1698 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1699 DMA_TO_DEVICE); 1700 memcpy(to + sg_resp->offset, 1701 hisi_sas_status_buf_addr_mem(slot) + 1702 sizeof(struct hisi_sas_err_record), 1703 sg_dma_len(sg_resp)); 1704 kunmap_atomic(to); 1705 break; 1706 } 1707 case SAS_PROTOCOL_SATA: 1708 case SAS_PROTOCOL_STP: 1709 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1710 ts->stat = SAM_STAT_GOOD; 1711 hisi_sas_sata_done(task, slot); 1712 break; 1713 default: 1714 ts->stat = SAM_STAT_CHECK_CONDITION; 1715 break; 1716 } 1717 1718 if (!slot->port->port_attached) { 1719 dev_warn(dev, "slot complete: port %d has removed\n", 1720 slot->port->sas_port.id); 1721 ts->stat = SAS_PHY_DOWN; 1722 } 1723 1724 out: 1725 hisi_sas_slot_task_free(hisi_hba, task, slot); 1726 sts = ts->stat; 1727 spin_lock_irqsave(&task->task_state_lock, flags); 1728 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1729 spin_unlock_irqrestore(&task->task_state_lock, flags); 1730 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1731 return SAS_ABORTED_TASK; 1732 } 1733 task->task_state_flags |= SAS_TASK_STATE_DONE; 1734 spin_unlock_irqrestore(&task->task_state_lock, flags); 1735 1736 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1737 spin_lock_irqsave(&device->done_lock, flags); 1738 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1739 spin_unlock_irqrestore(&device->done_lock, flags); 1740 dev_info(dev, "slot complete: task(%p) ignored\n ", 1741 task); 1742 return sts; 1743 } 1744 spin_unlock_irqrestore(&device->done_lock, flags); 1745 } 1746 1747 if (task->task_done) 1748 task->task_done(task); 1749 1750 return sts; 1751 } 1752 1753 static void cq_tasklet_v3_hw(unsigned long val) 1754 { 1755 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1756 struct hisi_hba *hisi_hba = cq->hisi_hba; 1757 struct hisi_sas_slot *slot; 1758 struct hisi_sas_complete_v3_hdr *complete_queue; 1759 u32 rd_point = cq->rd_point, wr_point; 1760 int queue = cq->id; 1761 1762 complete_queue = hisi_hba->complete_hdr[queue]; 1763 1764 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1765 (0x14 * queue)); 1766 1767 while (rd_point != wr_point) { 1768 struct hisi_sas_complete_v3_hdr *complete_hdr; 1769 struct device *dev = hisi_hba->dev; 1770 int iptt; 1771 1772 complete_hdr = &complete_queue[rd_point]; 1773 1774 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 1775 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 1776 slot = &hisi_hba->slot_info[iptt]; 1777 slot->cmplt_queue_slot = rd_point; 1778 slot->cmplt_queue = queue; 1779 slot_complete_v3_hw(hisi_hba, slot); 1780 } else 1781 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 1782 1783 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1784 rd_point = 0; 1785 } 1786 1787 /* update rd_point */ 1788 cq->rd_point = rd_point; 1789 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1790 } 1791 1792 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1793 { 1794 struct hisi_sas_cq *cq = p; 1795 struct hisi_hba *hisi_hba = cq->hisi_hba; 1796 int queue = cq->id; 1797 1798 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1799 1800 tasklet_schedule(&cq->tasklet); 1801 1802 return IRQ_HANDLED; 1803 } 1804 1805 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1806 { 1807 struct device *dev = hisi_hba->dev; 1808 struct pci_dev *pdev = hisi_hba->pci_dev; 1809 int vectors, rc; 1810 int i, k; 1811 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1812 1813 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1814 max_msi, PCI_IRQ_MSI); 1815 if (vectors < max_msi) { 1816 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1817 return -ENOENT; 1818 } 1819 1820 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1821 int_phy_up_down_bcast_v3_hw, 0, 1822 DRV_NAME " phy", hisi_hba); 1823 if (rc) { 1824 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1825 rc = -ENOENT; 1826 goto free_irq_vectors; 1827 } 1828 1829 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1830 int_chnl_int_v3_hw, 0, 1831 DRV_NAME " channel", hisi_hba); 1832 if (rc) { 1833 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1834 rc = -ENOENT; 1835 goto free_phy_irq; 1836 } 1837 1838 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1839 fatal_axi_int_v3_hw, 0, 1840 DRV_NAME " fatal", hisi_hba); 1841 if (rc) { 1842 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 1843 rc = -ENOENT; 1844 goto free_chnl_interrupt; 1845 } 1846 1847 /* Init tasklets for cq only */ 1848 for (i = 0; i < hisi_hba->queue_count; i++) { 1849 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 1850 struct tasklet_struct *t = &cq->tasklet; 1851 1852 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), 1853 cq_interrupt_v3_hw, 0, 1854 DRV_NAME " cq", cq); 1855 if (rc) { 1856 dev_err(dev, 1857 "could not request cq%d interrupt, rc=%d\n", 1858 i, rc); 1859 rc = -ENOENT; 1860 goto free_cq_irqs; 1861 } 1862 1863 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 1864 } 1865 1866 return 0; 1867 1868 free_cq_irqs: 1869 for (k = 0; k < i; k++) { 1870 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 1871 1872 free_irq(pci_irq_vector(pdev, k+16), cq); 1873 } 1874 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 1875 free_chnl_interrupt: 1876 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 1877 free_phy_irq: 1878 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 1879 free_irq_vectors: 1880 pci_free_irq_vectors(pdev); 1881 return rc; 1882 } 1883 1884 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 1885 { 1886 int rc; 1887 1888 rc = hw_init_v3_hw(hisi_hba); 1889 if (rc) 1890 return rc; 1891 1892 rc = interrupt_init_v3_hw(hisi_hba); 1893 if (rc) 1894 return rc; 1895 1896 return 0; 1897 } 1898 1899 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 1900 struct sas_phy_linkrates *r) 1901 { 1902 enum sas_linkrate max = r->maximum_linkrate; 1903 u32 prog_phy_link_rate = 0x800; 1904 1905 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 1906 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1907 prog_phy_link_rate); 1908 } 1909 1910 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 1911 { 1912 struct pci_dev *pdev = hisi_hba->pci_dev; 1913 int i; 1914 1915 synchronize_irq(pci_irq_vector(pdev, 1)); 1916 synchronize_irq(pci_irq_vector(pdev, 2)); 1917 synchronize_irq(pci_irq_vector(pdev, 11)); 1918 for (i = 0; i < hisi_hba->queue_count; i++) { 1919 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 1920 synchronize_irq(pci_irq_vector(pdev, i + 16)); 1921 } 1922 1923 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 1924 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 1925 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 1926 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1927 1928 for (i = 0; i < hisi_hba->n_phy; i++) { 1929 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 1930 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 1931 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 1932 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 1933 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 1934 } 1935 } 1936 1937 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 1938 { 1939 return hisi_sas_read32(hisi_hba, PHY_STATE); 1940 } 1941 1942 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1943 { 1944 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1945 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1946 struct sas_phy *sphy = sas_phy->phy; 1947 u32 reg_value; 1948 1949 /* loss dword sync */ 1950 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1951 sphy->loss_of_dword_sync_count += reg_value; 1952 1953 /* phy reset problem */ 1954 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1955 sphy->phy_reset_problem_count += reg_value; 1956 1957 /* invalid dword */ 1958 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1959 sphy->invalid_dword_count += reg_value; 1960 1961 /* disparity err */ 1962 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1963 sphy->running_disparity_error_count += reg_value; 1964 1965 } 1966 1967 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 1968 { 1969 struct device *dev = hisi_hba->dev; 1970 int rc; 1971 u32 status; 1972 1973 interrupt_disable_v3_hw(hisi_hba); 1974 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 1975 hisi_sas_kill_tasklets(hisi_hba); 1976 1977 hisi_sas_stop_phys(hisi_hba); 1978 1979 mdelay(10); 1980 1981 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); 1982 1983 /* wait until bus idle */ 1984 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 1985 AM_CURR_TRANS_RETURN, status, 1986 status == 0x3, 10, 100); 1987 if (rc) { 1988 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 1989 return rc; 1990 } 1991 1992 hisi_sas_init_mem(hisi_hba); 1993 1994 return hw_init_v3_hw(hisi_hba); 1995 } 1996 1997 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 1998 u8 reg_index, u8 reg_count, u8 *write_data) 1999 { 2000 struct device *dev = hisi_hba->dev; 2001 u32 *data = (u32 *)write_data; 2002 int i; 2003 2004 switch (reg_type) { 2005 case SAS_GPIO_REG_TX: 2006 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2007 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2008 reg_index, reg_index + reg_count - 1); 2009 return -EINVAL; 2010 } 2011 2012 for (i = 0; i < reg_count; i++) 2013 hisi_sas_write32(hisi_hba, 2014 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2015 data[i]); 2016 break; 2017 default: 2018 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2019 reg_type); 2020 return -EINVAL; 2021 } 2022 2023 return 0; 2024 } 2025 2026 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2027 int delay_ms, int timeout_ms) 2028 { 2029 struct device *dev = hisi_hba->dev; 2030 int entries, entries_old = 0, time; 2031 2032 for (time = 0; time < timeout_ms; time += delay_ms) { 2033 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2034 if (entries == entries_old) 2035 break; 2036 2037 entries_old = entries; 2038 msleep(delay_ms); 2039 } 2040 2041 dev_dbg(dev, "wait commands complete %dms\n", time); 2042 } 2043 2044 static struct scsi_host_template sht_v3_hw = { 2045 .name = DRV_NAME, 2046 .module = THIS_MODULE, 2047 .queuecommand = sas_queuecommand, 2048 .target_alloc = sas_target_alloc, 2049 .slave_configure = hisi_sas_slave_configure, 2050 .scan_finished = hisi_sas_scan_finished, 2051 .scan_start = hisi_sas_scan_start, 2052 .change_queue_depth = sas_change_queue_depth, 2053 .bios_param = sas_bios_param, 2054 .can_queue = 1, 2055 .this_id = -1, 2056 .sg_tablesize = SG_ALL, 2057 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2058 .use_clustering = ENABLE_CLUSTERING, 2059 .eh_device_reset_handler = sas_eh_device_reset_handler, 2060 .eh_target_reset_handler = sas_eh_target_reset_handler, 2061 .target_destroy = sas_target_destroy, 2062 .ioctl = sas_ioctl, 2063 .shost_attrs = host_attrs, 2064 }; 2065 2066 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2067 .hw_init = hisi_sas_v3_init, 2068 .setup_itct = setup_itct_v3_hw, 2069 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2070 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2071 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2072 .clear_itct = clear_itct_v3_hw, 2073 .sl_notify = sl_notify_v3_hw, 2074 .prep_ssp = prep_ssp_v3_hw, 2075 .prep_smp = prep_smp_v3_hw, 2076 .prep_stp = prep_ata_v3_hw, 2077 .prep_abort = prep_abort_v3_hw, 2078 .get_free_slot = get_free_slot_v3_hw, 2079 .start_delivery = start_delivery_v3_hw, 2080 .slot_complete = slot_complete_v3_hw, 2081 .phys_init = phys_init_v3_hw, 2082 .phy_start = start_phy_v3_hw, 2083 .phy_disable = disable_phy_v3_hw, 2084 .phy_hard_reset = phy_hard_reset_v3_hw, 2085 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2086 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2087 .dereg_device = dereg_device_v3_hw, 2088 .soft_reset = soft_reset_v3_hw, 2089 .get_phys_state = get_phys_state_v3_hw, 2090 .get_events = phy_get_events_v3_hw, 2091 .write_gpio = write_gpio_v3_hw, 2092 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2093 }; 2094 2095 static struct Scsi_Host * 2096 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2097 { 2098 struct Scsi_Host *shost; 2099 struct hisi_hba *hisi_hba; 2100 struct device *dev = &pdev->dev; 2101 2102 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2103 if (!shost) { 2104 dev_err(dev, "shost alloc failed\n"); 2105 return NULL; 2106 } 2107 hisi_hba = shost_priv(shost); 2108 2109 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2110 hisi_hba->hw = &hisi_sas_v3_hw; 2111 hisi_hba->pci_dev = pdev; 2112 hisi_hba->dev = dev; 2113 hisi_hba->shost = shost; 2114 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2115 2116 timer_setup(&hisi_hba->timer, NULL, 0); 2117 2118 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2119 goto err_out; 2120 2121 if (hisi_sas_alloc(hisi_hba, shost)) { 2122 hisi_sas_free(hisi_hba); 2123 goto err_out; 2124 } 2125 2126 return shost; 2127 err_out: 2128 scsi_host_put(shost); 2129 dev_err(dev, "shost alloc failed\n"); 2130 return NULL; 2131 } 2132 2133 static int 2134 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2135 { 2136 struct Scsi_Host *shost; 2137 struct hisi_hba *hisi_hba; 2138 struct device *dev = &pdev->dev; 2139 struct asd_sas_phy **arr_phy; 2140 struct asd_sas_port **arr_port; 2141 struct sas_ha_struct *sha; 2142 int rc, phy_nr, port_nr, i; 2143 2144 rc = pci_enable_device(pdev); 2145 if (rc) 2146 goto err_out; 2147 2148 pci_set_master(pdev); 2149 2150 rc = pci_request_regions(pdev, DRV_NAME); 2151 if (rc) 2152 goto err_out_disable_device; 2153 2154 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 2155 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 2156 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 2157 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { 2158 dev_err(dev, "No usable DMA addressing method\n"); 2159 rc = -EIO; 2160 goto err_out_regions; 2161 } 2162 } 2163 2164 shost = hisi_sas_shost_alloc_pci(pdev); 2165 if (!shost) { 2166 rc = -ENOMEM; 2167 goto err_out_regions; 2168 } 2169 2170 sha = SHOST_TO_SAS_HA(shost); 2171 hisi_hba = shost_priv(shost); 2172 dev_set_drvdata(dev, sha); 2173 2174 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2175 if (!hisi_hba->regs) { 2176 dev_err(dev, "cannot map register.\n"); 2177 rc = -ENOMEM; 2178 goto err_out_ha; 2179 } 2180 2181 phy_nr = port_nr = hisi_hba->n_phy; 2182 2183 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2184 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2185 if (!arr_phy || !arr_port) { 2186 rc = -ENOMEM; 2187 goto err_out_ha; 2188 } 2189 2190 sha->sas_phy = arr_phy; 2191 sha->sas_port = arr_port; 2192 sha->core.shost = shost; 2193 sha->lldd_ha = hisi_hba; 2194 2195 shost->transportt = hisi_sas_stt; 2196 shost->max_id = HISI_SAS_MAX_DEVICES; 2197 shost->max_lun = ~0; 2198 shost->max_channel = 1; 2199 shost->max_cmd_len = 16; 2200 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); 2201 shost->can_queue = hisi_hba->hw->max_command_entries; 2202 shost->cmd_per_lun = hisi_hba->hw->max_command_entries; 2203 2204 sha->sas_ha_name = DRV_NAME; 2205 sha->dev = dev; 2206 sha->lldd_module = THIS_MODULE; 2207 sha->sas_addr = &hisi_hba->sas_addr[0]; 2208 sha->num_phys = hisi_hba->n_phy; 2209 sha->core.shost = hisi_hba->shost; 2210 2211 for (i = 0; i < hisi_hba->n_phy; i++) { 2212 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2213 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2214 } 2215 2216 rc = scsi_add_host(shost, dev); 2217 if (rc) 2218 goto err_out_ha; 2219 2220 rc = sas_register_ha(sha); 2221 if (rc) 2222 goto err_out_register_ha; 2223 2224 rc = hisi_hba->hw->hw_init(hisi_hba); 2225 if (rc) 2226 goto err_out_register_ha; 2227 2228 scsi_scan_host(shost); 2229 2230 return 0; 2231 2232 err_out_register_ha: 2233 scsi_remove_host(shost); 2234 err_out_ha: 2235 scsi_host_put(shost); 2236 err_out_regions: 2237 pci_release_regions(pdev); 2238 err_out_disable_device: 2239 pci_disable_device(pdev); 2240 err_out: 2241 return rc; 2242 } 2243 2244 static void 2245 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2246 { 2247 int i; 2248 2249 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2250 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2251 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2252 for (i = 0; i < hisi_hba->queue_count; i++) { 2253 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2254 2255 free_irq(pci_irq_vector(pdev, i+16), cq); 2256 } 2257 pci_free_irq_vectors(pdev); 2258 } 2259 2260 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2261 { 2262 struct device *dev = &pdev->dev; 2263 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2264 struct hisi_hba *hisi_hba = sha->lldd_ha; 2265 struct Scsi_Host *shost = sha->core.shost; 2266 2267 if (timer_pending(&hisi_hba->timer)) 2268 del_timer(&hisi_hba->timer); 2269 2270 sas_unregister_ha(sha); 2271 sas_remove_host(sha->core.shost); 2272 2273 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2274 hisi_sas_kill_tasklets(hisi_hba); 2275 pci_release_regions(pdev); 2276 pci_disable_device(pdev); 2277 hisi_sas_free(hisi_hba); 2278 scsi_host_put(shost); 2279 } 2280 2281 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2282 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2283 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2284 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2285 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2286 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2287 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2288 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2289 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2290 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2291 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2292 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2293 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2294 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2295 }; 2296 2297 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2298 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2299 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2300 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2301 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2302 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2303 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2304 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2305 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2306 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2307 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2308 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2309 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2310 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2311 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2312 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2313 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2314 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2315 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2316 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2317 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2318 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2319 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2320 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2321 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2322 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2323 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2324 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2325 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2326 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2327 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2328 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2329 }; 2330 2331 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2332 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2333 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2334 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2335 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2336 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2337 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2338 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2339 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2340 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2341 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2342 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2343 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2344 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2345 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2346 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2347 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2348 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2349 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2350 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2351 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2352 }; 2353 2354 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2355 { 2356 struct device *dev = hisi_hba->dev; 2357 const struct hisi_sas_hw_error *ras_error; 2358 bool need_reset = false; 2359 u32 irq_value; 2360 int i; 2361 2362 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2363 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2364 ras_error = &sas_ras_intr0_nfe[i]; 2365 if (ras_error->irq_msk & irq_value) { 2366 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2367 ras_error->msg, irq_value); 2368 need_reset = true; 2369 } 2370 } 2371 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2372 2373 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2374 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2375 ras_error = &sas_ras_intr1_nfe[i]; 2376 if (ras_error->irq_msk & irq_value) { 2377 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2378 ras_error->msg, irq_value); 2379 need_reset = true; 2380 } 2381 } 2382 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2383 2384 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2385 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2386 ras_error = &sas_ras_intr2_nfe[i]; 2387 if (ras_error->irq_msk & irq_value) { 2388 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2389 ras_error->msg, irq_value); 2390 need_reset = true; 2391 } 2392 } 2393 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2394 2395 return need_reset; 2396 } 2397 2398 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2399 pci_channel_state_t state) 2400 { 2401 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2402 struct hisi_hba *hisi_hba = sha->lldd_ha; 2403 struct device *dev = hisi_hba->dev; 2404 2405 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2406 if (state == pci_channel_io_perm_failure) 2407 return PCI_ERS_RESULT_DISCONNECT; 2408 2409 if (process_non_fatal_error_v3_hw(hisi_hba)) 2410 return PCI_ERS_RESULT_NEED_RESET; 2411 2412 return PCI_ERS_RESULT_CAN_RECOVER; 2413 } 2414 2415 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2416 { 2417 return PCI_ERS_RESULT_RECOVERED; 2418 } 2419 2420 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2421 { 2422 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2423 struct hisi_hba *hisi_hba = sha->lldd_ha; 2424 struct device *dev = hisi_hba->dev; 2425 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2426 2427 dev_info(dev, "PCI error: slot reset callback!!\n"); 2428 queue_work(hisi_hba->wq, &r.work); 2429 wait_for_completion(r.completion); 2430 if (r.done) 2431 return PCI_ERS_RESULT_RECOVERED; 2432 2433 return PCI_ERS_RESULT_DISCONNECT; 2434 } 2435 2436 enum { 2437 /* instances of the controller */ 2438 hip08, 2439 }; 2440 2441 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2442 { 2443 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2444 struct hisi_hba *hisi_hba = sha->lldd_ha; 2445 struct device *dev = hisi_hba->dev; 2446 struct Scsi_Host *shost = hisi_hba->shost; 2447 u32 device_state, status; 2448 int rc; 2449 u32 reg_val; 2450 2451 if (!pdev->pm_cap) { 2452 dev_err(dev, "PCI PM not supported\n"); 2453 return -ENODEV; 2454 } 2455 2456 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2457 scsi_block_requests(shost); 2458 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2459 flush_workqueue(hisi_hba->wq); 2460 /* disable DQ/PHY/bus */ 2461 interrupt_disable_v3_hw(hisi_hba); 2462 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2463 hisi_sas_kill_tasklets(hisi_hba); 2464 2465 hisi_sas_stop_phys(hisi_hba); 2466 2467 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2468 AM_CTRL_GLOBAL); 2469 reg_val |= 0x1; 2470 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2471 AM_CTRL_GLOBAL, reg_val); 2472 2473 /* wait until bus idle */ 2474 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2475 AM_CURR_TRANS_RETURN, status, 2476 status == 0x3, 10, 100); 2477 if (rc) { 2478 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 2479 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2480 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2481 scsi_unblock_requests(shost); 2482 return rc; 2483 } 2484 2485 hisi_sas_init_mem(hisi_hba); 2486 2487 device_state = pci_choose_state(pdev, state); 2488 dev_warn(dev, "entering operating state [D%d]\n", 2489 device_state); 2490 pci_save_state(pdev); 2491 pci_disable_device(pdev); 2492 pci_set_power_state(pdev, device_state); 2493 2494 hisi_sas_release_tasks(hisi_hba); 2495 2496 sas_suspend_ha(sha); 2497 return 0; 2498 } 2499 2500 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2501 { 2502 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2503 struct hisi_hba *hisi_hba = sha->lldd_ha; 2504 struct Scsi_Host *shost = hisi_hba->shost; 2505 struct device *dev = hisi_hba->dev; 2506 unsigned int rc; 2507 u32 device_state = pdev->current_state; 2508 2509 dev_warn(dev, "resuming from operating state [D%d]\n", 2510 device_state); 2511 pci_set_power_state(pdev, PCI_D0); 2512 pci_enable_wake(pdev, PCI_D0, 0); 2513 pci_restore_state(pdev); 2514 rc = pci_enable_device(pdev); 2515 if (rc) 2516 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2517 2518 pci_set_master(pdev); 2519 scsi_unblock_requests(shost); 2520 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2521 2522 sas_prep_resume_ha(sha); 2523 init_reg_v3_hw(hisi_hba); 2524 hisi_hba->hw->phys_init(hisi_hba); 2525 sas_resume_ha(sha); 2526 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2527 2528 return 0; 2529 } 2530 2531 static const struct pci_device_id sas_v3_pci_table[] = { 2532 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2533 {} 2534 }; 2535 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 2536 2537 static const struct pci_error_handlers hisi_sas_err_handler = { 2538 .error_detected = hisi_sas_error_detected_v3_hw, 2539 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2540 .slot_reset = hisi_sas_slot_reset_v3_hw, 2541 }; 2542 2543 static struct pci_driver sas_v3_pci_driver = { 2544 .name = DRV_NAME, 2545 .id_table = sas_v3_pci_table, 2546 .probe = hisi_sas_v3_probe, 2547 .remove = hisi_sas_v3_remove, 2548 .suspend = hisi_sas_v3_suspend, 2549 .resume = hisi_sas_v3_resume, 2550 .err_handler = &hisi_sas_err_handler, 2551 }; 2552 2553 module_pci_driver(sas_v3_pci_driver); 2554 2555 MODULE_LICENSE("GPL"); 2556 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2557 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2558 MODULE_ALIAS("pci:" DRV_NAME); 2559